Index: head/sys/mips/nlm/board.c =================================================================== --- head/sys/mips/nlm/board.c (revision 279386) +++ head/sys/mips/nlm/board.c (revision 279387) @@ -1,537 +1,537 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static uint8_t board_eeprom_buf[EEPROM_SIZE]; static int board_eeprom_set; struct xlp_board_info xlp_board_info; struct vfbid_tbl { int vfbid; int dest_vc; }; /* XXXJC : this should be derived from msg thread mask */ static struct vfbid_tbl nlm_vfbid[] = { /* NULL FBID should map to cpu0 to detect NAE send msg errors */ {127, 0}, /* NAE <-> NAE mappings */ {51, 1019}, {50, 1018}, {49, 1017}, {48, 1016}, {47, 1015}, {46, 1014}, {45, 1013}, {44, 1012}, {43, 1011}, {42, 1010}, {41, 1009}, {40, 1008}, {39, 1007}, {38, 1006}, {37, 1005}, {36, 1004}, {35, 1003}, {34, 1002}, {33, 1001}, {32, 1000}, - /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ + /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ {31, 127}, {30, 123}, {29, 119}, {28, 115}, {27, 111}, {26, 107}, {25, 103}, {24, 99}, {23, 95}, {22, 91}, {21, 87}, {20, 83}, {19, 79}, {18, 75}, {17, 71}, {16, 67}, {15, 63}, {14, 59}, {13, 55}, {12, 51}, {11, 47}, {10, 43}, { 9, 39}, { 8, 35}, { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19}, { 3, 15}, { 2, 11}, { 1, 7}, { 0, 3}, }; static struct vfbid_tbl nlm3xx_vfbid[] = { /* NULL FBID should map to cpu0 to detect NAE send msg errors */ {127, 0}, /* NAE <-> NAE mappings */ {39, 503}, {38, 502}, {37, 501}, {36, 500}, {35, 499}, {34, 498}, {33, 497}, {32, 496}, - /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ + /* NAE <-> CPU mappings, freeback got to vc 3 of each thread */ {31, 127}, {30, 123}, {29, 119}, {28, 115}, {27, 111}, {26, 107}, {25, 103}, {24, 99}, {23, 95}, {22, 91}, {21, 87}, {20, 83}, {19, 79}, {18, 75}, {17, 71}, {16, 67}, {15, 63}, {14, 59}, {13, 55}, {12, 51}, {11, 47}, {10, 43}, { 9, 39}, { 8, 35}, { 7, 31}, { 6, 27}, { 5, 23}, { 4, 19}, { 3, 15}, { 2, 11}, { 1, 7}, { 0, 3}, }; int nlm_get_vfbid_mapping(int vfbid) { int i, nentries; struct vfbid_tbl *p; if (nlm_is_xlp3xx()) { nentries = sizeof(nlm3xx_vfbid)/sizeof(struct vfbid_tbl); p = nlm3xx_vfbid; } else { nentries = sizeof(nlm_vfbid)/sizeof(struct vfbid_tbl); p = nlm_vfbid; } for (i = 0; i < nentries; i++) { if (p[i].vfbid == vfbid) return (p[i].dest_vc); } return (-1); } int nlm_get_poe_distvec(int vec, uint32_t *distvec) { if (vec != 0) return (-1); /* we support just vec 0 */ nlm_calc_poe_distvec(xlp_msg_thread_mask, 0, 0, 0, 0x1 << XLPGE_RX_VC, distvec); return (0); } /* * All our knowledge of chip and board that cannot be detected by probing * at run-time goes here */ void xlpge_get_macaddr(uint8_t *macaddr) { if (board_eeprom_set == 0) { /* No luck, take some reasonable value */ macaddr[0] = 0x00; macaddr[1] = 0x0f; macaddr[2] = 0x30; macaddr[3] = 0x20; macaddr[4] = 0x0d; macaddr[5] = 0x5b; } else memcpy(macaddr, &board_eeprom_buf[EEPROM_MACADDR_OFFSET], ETHER_ADDR_LEN); } static void nlm_setup_port_defaults(struct xlp_port_ivars *p) { p->loopback_mode = 0; p->num_channels = 1; p->free_desc_sizes = 2048; p->vlan_pri_en = 0; p->hw_parser_en = 1; p->ieee1588_userval = 0; p->ieee1588_ptpoff = 0; p->ieee1588_tmr1 = 0; p->ieee1588_tmr2 = 0; p->ieee1588_tmr3 = 0; p->ieee1588_inc_intg = 0; p->ieee1588_inc_den = 1; p->ieee1588_inc_num = 1; if (nlm_is_xlp3xx()) { p->stg2_fifo_size = XLP3XX_STG2_FIFO_SZ; p->eh_fifo_size = XLP3XX_EH_FIFO_SZ; p->frout_fifo_size = XLP3XX_FROUT_FIFO_SZ; p->ms_fifo_size = XLP3XX_MS_FIFO_SZ; p->pkt_fifo_size = XLP3XX_PKT_FIFO_SZ; p->pktlen_fifo_size = XLP3XX_PKTLEN_FIFO_SZ; p->max_stg2_offset = XLP3XX_MAX_STG2_OFFSET; p->max_eh_offset = XLP3XX_MAX_EH_OFFSET; p->max_frout_offset = XLP3XX_MAX_FREE_OUT_OFFSET; p->max_ms_offset = XLP3XX_MAX_MS_OFFSET; p->max_pmem_offset = XLP3XX_MAX_PMEM_OFFSET; p->stg1_2_credit = XLP3XX_STG1_2_CREDIT; p->stg2_eh_credit = XLP3XX_STG2_EH_CREDIT; p->stg2_frout_credit = XLP3XX_STG2_FROUT_CREDIT; p->stg2_ms_credit = XLP3XX_STG2_MS_CREDIT; } else { p->stg2_fifo_size = XLP8XX_STG2_FIFO_SZ; p->eh_fifo_size = XLP8XX_EH_FIFO_SZ; p->frout_fifo_size = XLP8XX_FROUT_FIFO_SZ; p->ms_fifo_size = XLP8XX_MS_FIFO_SZ; p->pkt_fifo_size = XLP8XX_PKT_FIFO_SZ; p->pktlen_fifo_size = XLP8XX_PKTLEN_FIFO_SZ; p->max_stg2_offset = XLP8XX_MAX_STG2_OFFSET; p->max_eh_offset = XLP8XX_MAX_EH_OFFSET; p->max_frout_offset = XLP8XX_MAX_FREE_OUT_OFFSET; p->max_ms_offset = XLP8XX_MAX_MS_OFFSET; p->max_pmem_offset = XLP8XX_MAX_PMEM_OFFSET; p->stg1_2_credit = XLP8XX_STG1_2_CREDIT; p->stg2_eh_credit = XLP8XX_STG2_EH_CREDIT; p->stg2_frout_credit = XLP8XX_STG2_FROUT_CREDIT; p->stg2_ms_credit = XLP8XX_STG2_MS_CREDIT; } switch (p->type) { case SGMIIC: p->num_free_descs = 52; p->iface_fifo_size = 13; p->rxbuf_size = 128; p->rx_slots_reqd = SGMII_CAL_SLOTS; p->tx_slots_reqd = SGMII_CAL_SLOTS; if (nlm_is_xlp3xx()) p->pseq_fifo_size = 30; else p->pseq_fifo_size = 62; break; case ILC: p->num_free_descs = 150; p->rxbuf_size = 944; p->rx_slots_reqd = IL8_CAL_SLOTS; p->tx_slots_reqd = IL8_CAL_SLOTS; p->pseq_fifo_size = 225; p->iface_fifo_size = 55; break; case XAUIC: default: p->num_free_descs = 150; p->rxbuf_size = 944; p->rx_slots_reqd = XAUI_CAL_SLOTS; p->tx_slots_reqd = XAUI_CAL_SLOTS; if (nlm_is_xlp3xx()) { p->pseq_fifo_size = 120; p->iface_fifo_size = 52; } else { p->pseq_fifo_size = 225; p->iface_fifo_size = 55; } break; } } /* XLP 8XX evaluation boards have the following phy-addr * assignment. There are two external mdio buses in XLP -- * bus 0 and bus 1. The management ports (16 and 17) are - * on mdio bus 0 while blocks/complexes[0 to 3] are all + * on mdio bus 0 while blocks/complexes[0 to 3] are all * on mdio bus 1. The phy_addr on bus 0 (mgmt ports 16 * and 17) match the port numbers. * These are the details: * block port phy_addr mdio_bus * ==================================== * 0 0 4 1 * 0 1 7 1 * 0 2 6 1 * 0 3 5 1 * 1 0 8 1 * 1 1 11 1 * 1 2 10 1 * 1 3 9 1 * 2 0 0 1 * 2 1 3 1 * 2 2 2 1 * 2 3 1 1 * 3 0 12 1 * 3 1 15 1 * 3 2 14 1 * 3 3 13 1 * - * 4 0 16 0 + * 4 0 16 0 * 4 1 17 0 * * The XLP 3XX evaluation boards have the following phy-addr * assignments. * block port phy_addr mdio_bus * ==================================== * 0 0 4 0 * 0 1 7 0 * 0 2 6 0 * 0 3 5 0 * 1 0 8 0 * 1 1 11 0 * 1 2 10 0 * 1 3 9 0 */ static void nlm_board_get_phyaddr(int block, int port, int *phyaddr) { switch (block) { case 0: switch (port) { case 0: *phyaddr = 4; break; case 1: *phyaddr = 7; break; case 2: *phyaddr = 6; break; case 3: *phyaddr = 5; break; } break; case 1: switch (port) { case 0: *phyaddr = 8; break; case 1: *phyaddr = 11; break; case 2: *phyaddr = 10; break; case 3: *phyaddr = 9; break; } break; case 2: switch (port) { case 0: *phyaddr = 0; break; case 1: *phyaddr = 3; break; case 2: *phyaddr = 2; break; case 3: *phyaddr = 1; break; } break; case 3: switch (port) { case 0: *phyaddr = 12; break; case 1: *phyaddr = 15; break; case 2: *phyaddr = 14; break; case 3: *phyaddr = 13; break; } break; case 4: switch (port) { /* management SGMII */ case 0: *phyaddr = 16; break; case 1: *phyaddr = 17; break; } break; } } static void nlm_print_processor_info(void) { uint32_t procid; int prid, rev; char *chip, *revstr; procid = mips_rd_prid(); prid = (procid >> 8) & 0xff; rev = procid & 0xff; switch (prid) { case CHIP_PROCESSOR_ID_XLP_8XX: chip = "XLP 832"; break; case CHIP_PROCESSOR_ID_XLP_3XX: chip = "XLP 3xx"; break; case CHIP_PROCESSOR_ID_XLP_432: case CHIP_PROCESSOR_ID_XLP_416: chip = "XLP 4xx"; break; default: chip = "XLP ?xx"; break; } switch (rev) { case 0: revstr = "A0"; break; case 1: revstr = "A1"; break; case 2: revstr = "A2"; break; case 3: revstr = "B0"; break; case 4: revstr = "B1"; break; default: revstr = "??"; break; } printf("Processor info:\n"); printf(" Netlogic %s %s [%x]\n", chip, revstr, procid); } /* - * All our knowledge of chip and board that cannot be detected by probing + * All our knowledge of chip and board that cannot be detected by probing * at run-time goes here */ static int nlm_setup_xlp_board(int node) { struct xlp_board_info *boardp; struct xlp_node_info *nodep; struct xlp_nae_ivars *naep; struct xlp_block_ivars *blockp; struct xlp_port_ivars *portp; uint64_t cpldbase, nae_pcibase; int block, port, rv, dbtype, usecpld = 0, evp = 0, svp = 0; uint8_t *b; /* start with a clean slate */ boardp = &xlp_board_info; if (boardp->nodemask == 0) memset(boardp, 0, sizeof(xlp_board_info)); boardp->nodemask |= (1 << node); nlm_print_processor_info(); b = board_eeprom_buf; rv = nlm_board_eeprom_read(node, EEPROM_I2CBUS, EEPROM_I2CADDR, 0, b, EEPROM_SIZE); if (rv == 0) { board_eeprom_set = 1; printf("Board info (EEPROM on i2c@%d at %#X):\n", EEPROM_I2CBUS, EEPROM_I2CADDR); printf(" Model: %7.7s %2.2s\n", &b[16], &b[24]); printf(" Serial #: %3.3s-%2.2s\n", &b[27], &b[31]); printf(" MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n", b[2], b[3], b[4], b[5], b[6], b[7]); } else printf("Board Info: Error on EEPROM read (i2c@%d %#X).\n", EEPROM_I2CBUS, EEPROM_I2CADDR); nae_pcibase = nlm_get_nae_pcibase(node); nodep = &boardp->nodes[node]; naep = &nodep->nae_ivars; naep->node = node; /* frequency at which network block runs */ naep->freq = 500; /* CRC16 polynomial used for flow table generation */ naep->flow_crc_poly = 0xffff; naep->hw_parser_en = 1; naep->prepad_en = 1; naep->prepad_size = 3; /* size in 16 byte units */ naep->ieee_1588_en = 1; naep->ilmask = 0x0; /* set this based on daughter card */ naep->xauimask = 0x0; /* set this based on daughter card */ naep->sgmiimask = 0x0; /* set this based on daughter card */ naep->nblocks = nae_num_complex(nae_pcibase); if (strncmp(&b[16], "PCIE", 4) == 0) { usecpld = 0; /* XLP PCIe card */ /* Broadcom's XLP PCIe card has the following * blocks fixed. * blk 0-XAUI, 1-XAUI, 4-SGMII(one port) */ naep->blockmask = 0x13; } else if (strncmp(&b[16], "MB-EVP", 6) == 0) { usecpld = 1; /* XLP non-PCIe card which has CPLD */ evp = 1; naep->blockmask = (1 << naep->nblocks) - 1; } else if ((strncmp(&b[16], "MB-S", 4) == 0) || (strncmp(&b[16], "MB_S", 4) == 0)) { usecpld = 1; /* XLP non-PCIe card which has CPLD */ svp = 1; /* 3xx chip reports one block extra which is a bug */ naep->nblocks = naep->nblocks - 1; naep->blockmask = (1 << naep->nblocks) - 1; } else { printf("ERROR!!! Board type:%7s didn't match any board" " type we support\n", &b[16]); return (-1); } cpldbase = nlm_board_cpld_base(node, XLP_EVB_CPLD_CHIPSELECT); /* pretty print network config */ printf("Network config"); if (usecpld) printf("(from CPLD@%d):\n", XLP_EVB_CPLD_CHIPSELECT); else printf("(defaults):\n"); printf(" NAE@%d Blocks: ", node); for (block = 0; block < naep->nblocks; block++) { char *s = "???"; if ((naep->blockmask & (1 << block)) == 0) continue; blockp = &naep->block_ivars[block]; blockp->block = block; if (usecpld) dbtype = nlm_board_cpld_dboard_type(cpldbase, block); else dbtype = DCARD_XAUI; /* default XAUI */ /* XLP PCIe cards */ if ((!evp && !svp) && ((block == 2) || (block == 3))) dbtype = DCARD_NOT_PRSNT; if (block == 4) { /* management block 4 on 8xx or XLP PCIe */ blockp->type = SGMIIC; if (evp) blockp->portmask = 0x3; else blockp->portmask = 0x1; naep->sgmiimask |= (1 << block); } else { switch (dbtype) { case DCARD_ILAKEN: blockp->type = ILC; blockp->portmask = 0x1; naep->ilmask |= (1 << block); break; case DCARD_SGMII: blockp->type = SGMIIC; blockp->portmask = 0xf; naep->sgmiimask |= (1 << block); break; case DCARD_XAUI: blockp->type = XAUIC; blockp->portmask = 0x1; naep->xauimask |= (1 << block); break; default: /* DCARD_NOT_PRSNT */ blockp->type = UNKNOWN; blockp->portmask = 0; break; } } if (blockp->type != UNKNOWN) { for (port = 0; port < PORTS_PER_CMPLX; port++) { if ((blockp->portmask & (1 << port)) == 0) continue; portp = &blockp->port_ivars[port]; nlm_board_get_phyaddr(block, port, &portp->phy_addr); if (svp || (block == 4)) portp->mdio_bus = 0; else portp->mdio_bus = 1; portp->port = port; portp->block = block; portp->node = node; portp->type = blockp->type; nlm_setup_port_defaults(portp); } } switch (blockp->type) { case SGMIIC : s = "SGMII"; break; case XAUIC : s = "XAUI"; break; case ILC : s = "IL"; break; } printf(" [%d %s]", block, s); } printf("\n"); return (0); } int nlm_board_info_setup(void) { if (nlm_setup_xlp_board(0) != 0) return (-1); return (0); } Index: head/sys/mips/nlm/board.h =================================================================== --- head/sys/mips/nlm/board.h (revision 279386) +++ head/sys/mips/nlm/board.h (revision 279387) @@ -1,157 +1,157 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: - * + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef __NLM_BOARD_H__ #define __NLM_BOARD_H__ #define XLP_NAE_NBLOCKS 5 #define XLP_NAE_NPORTS 4 /* * EVP board EEPROM info */ #define EEPROM_I2CBUS 1 #define EEPROM_I2CADDR 0xAE -#define EEPROM_SIZE 48 +#define EEPROM_SIZE 48 #define EEPROM_MACADDR_OFFSET 2 /* used if there is no FDT */ #define BOARD_CONSOLE_SPEED 115200 #define BOARD_CONSOLE_UART 0 /* * EVP board CPLD chip select and daughter card info field */ #define XLP_EVB_CPLD_CHIPSELECT 2 #define DCARD_ILAKEN 0x0 #define DCARD_SGMII 0x1 #define DCARD_XAUI 0x2 #define DCARD_NOT_PRSNT 0x3 #if !defined(LOCORE) && !defined(__ASSEMBLY__) /* * NAE configuration */ struct xlp_port_ivars { int port; int block; int node; int type; int phy_addr; int mdio_bus; int loopback_mode; int num_channels; int free_desc_sizes; int num_free_descs; int pseq_fifo_size; int iface_fifo_size; int rxbuf_size; int rx_slots_reqd; int tx_slots_reqd; int vlan_pri_en; int stg2_fifo_size; int eh_fifo_size; int frout_fifo_size; int ms_fifo_size; int pkt_fifo_size; int pktlen_fifo_size; int max_stg2_offset; int max_eh_offset; int max_frout_offset; int max_ms_offset; int max_pmem_offset; int stg1_2_credit; int stg2_eh_credit; int stg2_frout_credit; int stg2_ms_credit; int hw_parser_en; u_int ieee1588_inc_intg; u_int ieee1588_inc_den; u_int ieee1588_inc_num; uint64_t ieee1588_userval; uint64_t ieee1588_ptpoff; uint64_t ieee1588_tmr1; uint64_t ieee1588_tmr2; uint64_t ieee1588_tmr3; }; struct xlp_block_ivars { int block; int type; u_int portmask; struct xlp_port_ivars port_ivars[XLP_NAE_NPORTS]; }; struct xlp_nae_ivars { - int node; + int node; int nblocks; u_int blockmask; u_int ilmask; u_int xauimask; u_int sgmiimask; int freq; u_int flow_crc_poly; u_int hw_parser_en; u_int prepad_en; u_int prepad_size; /* size in 16 byte units */ u_int ieee_1588_en; struct xlp_block_ivars block_ivars[XLP_NAE_NBLOCKS]; }; struct xlp_board_info { u_int nodemask; struct xlp_node_info { struct xlp_nae_ivars nae_ivars; } nodes[XLP_MAX_NODES]; }; extern struct xlp_board_info xlp_board_info; /* Network configuration */ int nlm_get_vfbid_mapping(int); int nlm_get_poe_distvec(int vec, uint32_t *distvec); void xlpge_get_macaddr(uint8_t *macaddr); int nlm_board_info_setup(void); /* EEPROM & CPLD */ int nlm_board_eeprom_read(int node, int i2cbus, int addr, int offs, uint8_t *buf,int sz); uint64_t nlm_board_cpld_base(int node, int chipselect); int nlm_board_cpld_majorversion(uint64_t cpldbase); int nlm_board_cpld_minorversion(uint64_t cpldbase); void nlm_board_cpld_reset(uint64_t cpldbase); int nlm_board_cpld_dboard_type(uint64_t cpldbase, int slot); #endif #endif Index: head/sys/mips/nlm/board_cpld.c =================================================================== --- head/sys/mips/nlm/board_cpld.c (revision 279386) +++ head/sys/mips/nlm/board_cpld.c (revision 279387) @@ -1,113 +1,113 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #define CPLD_REVISION 0x0 #define CPLD_RESET 0x1 #define CPLD_CTRL 0x2 #define CPLD_RSVD 0x3 #define CPLD_PWR_CTRL 0x4 #define CPLD_MISC 0x5 #define CPLD_CTRL_STATUS 0x6 #define CPLD_PWR_INTR_STATUS 0x7 #define CPLD_DATA 0x8 static __inline int nlm_cpld_read(uint64_t base, int reg) { uint16_t val; val = *(volatile uint16_t *)(long)(base + reg * 2); return le16toh(val); } static __inline void nlm_cpld_write(uint64_t base, int reg, uint16_t data) { data = htole16(data); *(volatile uint16_t *)(long)(base + reg * 2) = data; } int nlm_board_cpld_majorversion(uint64_t base) { return (nlm_cpld_read(base, CPLD_REVISION) >> 8); } int nlm_board_cpld_minorversion(uint64_t base) { return (nlm_cpld_read(base, CPLD_REVISION) & 0xff); } uint64_t nlm_board_cpld_base(int node, int chipselect) { uint64_t gbubase, cpld_phys; gbubase = nlm_get_gbu_regbase(node); cpld_phys = nlm_read_gbu_reg(gbubase, GBU_CS_BASEADDR(chipselect)); return (MIPS_PHYS_TO_KSEG1(cpld_phys << 8)); } void nlm_board_cpld_reset(uint64_t base) { nlm_cpld_write(base, CPLD_RESET, 1 << 15); for(;;) __asm __volatile("wait"); } /* get daughter board type */ int nlm_board_cpld_dboard_type(uint64_t base, int slot) { uint16_t val; int shift = 0; switch (slot) { case 0: shift = 0; break; case 1: shift = 4; break; case 2: shift = 2; break; case 3: shift = 6; break; } val = nlm_cpld_read(base, CPLD_CTRL_STATUS) >> shift; return (val & 0x3); } Index: head/sys/mips/nlm/board_eeprom.c =================================================================== --- head/sys/mips/nlm/board_eeprom.c (revision 279386) +++ head/sys/mips/nlm/board_eeprom.c (revision 279387) @@ -1,172 +1,172 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include /* needed by board.h */ #include /* * We have to read the EEPROM in early boot (now only for MAC addr) * but later for board information. Use simple polled mode driver * for I2C */ #define oc_read_reg(reg) nlm_read_reg(eeprom_i2c_base, reg) #define oc_write_reg(reg, val) nlm_write_reg(eeprom_i2c_base, reg, val) static uint64_t eeprom_i2c_base; static int oc_wait_on_status(uint8_t bit) { int tries = I2C_TIMEOUT; uint8_t status; do { status = oc_read_reg(OC_I2C_STATUS_REG); } while ((status & bit) != 0 && --tries > 0); return (tries == 0 ? -1: 0); } static int oc_rd_cmd(uint8_t cmd) { uint8_t data; oc_write_reg(OC_I2C_CMD_REG, cmd); if (oc_wait_on_status(OC_STATUS_TIP) < 0) return (-1); data = oc_read_reg(OC_I2C_DATA_REG); return (data); } - + static int oc_wr_cmd(uint8_t data, uint8_t cmd) { oc_write_reg(OC_I2C_DATA_REG, data); oc_write_reg(OC_I2C_CMD_REG, cmd); if (oc_wait_on_status(OC_STATUS_TIP) < 0) return (-1); return (0); } int nlm_board_eeprom_read(int node, int bus, int addr, int offs, uint8_t *buf, int sz) { int rd, i; char *err = NULL; eeprom_i2c_base = nlm_pcicfg_base(XLP_IO_I2C_OFFSET(node, bus)) + XLP_IO_PCI_HDRSZ; if (oc_wait_on_status(OC_STATUS_BUSY) < 0) { err = "Not idle"; goto err_exit; } /* write start */ if (oc_wr_cmd(addr, OC_COMMAND_START)) { err = "I2C write start failed."; goto err_exit; } if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) { err = "No ack after start"; goto err_exit_stop; } if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_AL) { err = "I2C Bus Arbitration Lost"; goto err_exit_stop; } /* Write offset */ if (oc_wr_cmd(offs, OC_COMMAND_WRITE)) { err = "I2C write slave offset failed."; goto err_exit_stop; } if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) { err = "No ack after write"; goto err_exit_stop; } /* read start */ if (oc_wr_cmd(addr | 1, OC_COMMAND_START)) { err = "I2C read start failed."; goto err_exit_stop; } if (oc_read_reg(OC_I2C_STATUS_REG) & OC_STATUS_NACK) { err = "No ack after read start"; goto err_exit_stop; } - + for (i = 0; i < sz - 1; i++) { if ((rd = oc_rd_cmd(OC_COMMAND_READ)) < 0) { err = "I2C read data byte failed."; goto err_exit_stop; } buf[i] = rd; } /* last byte */ if ((rd = oc_rd_cmd(OC_COMMAND_RDNACK)) < 0) { err = "I2C read last data byte failed."; goto err_exit_stop; } buf[sz - 1] = rd; err_exit_stop: oc_write_reg(OC_I2C_CMD_REG, OC_COMMAND_STOP); if (oc_wait_on_status(OC_STATUS_BUSY) < 0) printf("%s: stop failed", __func__); err_exit: if (err) { printf("%s: Failed (%s)\n", __func__, err); return (-1); } return (0); } Index: head/sys/mips/nlm/bus_space_rmi_pci.c =================================================================== --- head/sys/mips/nlm/bus_space_rmi_pci.c (revision 279386) +++ head/sys/mips/nlm/bus_space_rmi_pci.c (revision 279387) @@ -1,768 +1,771 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include -static int +static int rmi_pci_bus_space_map(void *t, bus_addr_t addr, bus_size_t size, int flags, bus_space_handle_t * bshp); -static void +static void rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh, bus_size_t size); -static int +static int rmi_pci_bus_space_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t * nbshp); -static u_int8_t +static u_int8_t rmi_pci_bus_space_read_1(void *t, bus_space_handle_t handle, bus_size_t offset); -static u_int16_t +static u_int16_t rmi_pci_bus_space_read_2(void *t, bus_space_handle_t handle, bus_size_t offset); -static u_int32_t +static u_int32_t rmi_pci_bus_space_read_4(void *t, bus_space_handle_t handle, bus_size_t offset); -static void +static void rmi_pci_bus_space_read_multi_1(void *t, bus_space_handle_t handle, bus_size_t offset, u_int8_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_multi_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_multi_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int8_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int32_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_1(void *t, bus_space_handle_t handle, bus_size_t offset, u_int8_t value); -static void +static void rmi_pci_bus_space_write_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t value); -static void +static void rmi_pci_bus_space_write_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t value); -static void +static void rmi_pci_bus_space_write_multi_1(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int8_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_multi_2(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_multi_4(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int32_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, const u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, const u_int32_t * addr, size_t count); - -static void +static void rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int16_t value, size_t count); -static void + +static void rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int32_t value, size_t count); -static void +static void rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, bus_size_t offset __unused, bus_size_t len __unused, int flags); -static void +static void rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1, bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, size_t count); -u_int8_t +u_int8_t rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, bus_size_t offset); -static u_int16_t +static u_int16_t rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset); -static u_int32_t +static u_int32_t rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset); -static void + +static void rmi_pci_bus_space_read_multi_stream_1(void *t, bus_space_handle_t handle, bus_size_t offset, u_int8_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_multi_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_read_multi_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t * addr, size_t count); -void +void rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int8_t value); -static void + +static void rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t value); -static void +static void rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t value); -static void +static void rmi_pci_bus_space_write_multi_stream_1(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int8_t * addr, size_t count); -static void + +static void rmi_pci_bus_space_write_multi_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int16_t * addr, size_t count); -static void +static void rmi_pci_bus_space_write_multi_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset, const u_int32_t * addr, size_t count); #define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__) static struct bus_space local_rmi_pci_bus_space = { /* cookie */ (void *)0, /* mapping/unmapping */ rmi_pci_bus_space_map, rmi_pci_bus_space_unmap, rmi_pci_bus_space_subregion, /* allocation/deallocation */ NULL, NULL, /* barrier */ rmi_pci_bus_space_barrier, /* read (single) */ rmi_pci_bus_space_read_1, rmi_pci_bus_space_read_2, rmi_pci_bus_space_read_4, NULL, /* read multiple */ rmi_pci_bus_space_read_multi_1, rmi_pci_bus_space_read_multi_2, rmi_pci_bus_space_read_multi_4, NULL, /* read region */ rmi_pci_bus_space_read_region_1, rmi_pci_bus_space_read_region_2, rmi_pci_bus_space_read_region_4, NULL, /* write (single) */ rmi_pci_bus_space_write_1, rmi_pci_bus_space_write_2, rmi_pci_bus_space_write_4, NULL, /* write multiple */ rmi_pci_bus_space_write_multi_1, rmi_pci_bus_space_write_multi_2, rmi_pci_bus_space_write_multi_4, NULL, /* write region */ NULL, rmi_pci_bus_space_write_region_2, rmi_pci_bus_space_write_region_4, NULL, /* set multiple */ NULL, NULL, NULL, NULL, /* set region */ NULL, rmi_pci_bus_space_set_region_2, rmi_pci_bus_space_set_region_4, NULL, /* copy */ NULL, rmi_pci_bus_space_copy_region_2, NULL, NULL, /* read (single) stream */ rmi_pci_bus_space_read_stream_1, rmi_pci_bus_space_read_stream_2, rmi_pci_bus_space_read_stream_4, NULL, /* read multiple stream */ rmi_pci_bus_space_read_multi_stream_1, rmi_pci_bus_space_read_multi_stream_2, rmi_pci_bus_space_read_multi_stream_4, NULL, /* read region stream */ rmi_pci_bus_space_read_region_1, rmi_pci_bus_space_read_region_2, rmi_pci_bus_space_read_region_4, NULL, /* write (single) stream */ rmi_pci_bus_space_write_stream_1, rmi_pci_bus_space_write_stream_2, rmi_pci_bus_space_write_stream_4, NULL, /* write multiple stream */ rmi_pci_bus_space_write_multi_stream_1, rmi_pci_bus_space_write_multi_stream_2, rmi_pci_bus_space_write_multi_stream_4, NULL, /* write region stream */ NULL, rmi_pci_bus_space_write_region_2, rmi_pci_bus_space_write_region_4, NULL, }; /* generic bus_space tag */ bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space; /* * Map a region of device bus space into CPU virtual address space. */ static int rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr, bus_size_t size __unused, int flags __unused, bus_space_handle_t * bshp) { *bshp = addr; return (0); } /* * Unmap a region of device bus space. */ static void rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused, bus_size_t size __unused) { } /* * Get a new handle for a subregion of an already-mapped area of bus space. */ static int rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size __unused, bus_space_handle_t * nbshp) { *nbshp = bsh + offset; return (0); } /* * Read a 1, 2, 4, or 8 byte quantity from bus space * described by tag/handle/offset. */ static u_int8_t rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle, bus_size_t offset) { return (u_int8_t) (*(volatile u_int8_t *)(handle + offset)); } static u_int16_t rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle, bus_size_t offset) { u_int16_t value; value = *(volatile u_int16_t *)(handle + offset); return bswap16(value); } static u_int32_t rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle, bus_size_t offset) { uint32_t value; value = *(volatile u_int32_t *)(handle + offset); return bswap32(value); } /* * Read `count' 1, 2, 4, or 8 byte quantities from bus space * described by tag/handle/offset and copy into buffer provided. */ static void rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int8_t * addr, size_t count) { while (count--) { *addr = *(volatile u_int8_t *)(handle + offset); addr++; } } static void rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int16_t * addr, size_t count) { while (count--) { *addr = *(volatile u_int16_t *)(handle + offset); *addr = bswap16(*addr); addr++; } } static void rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int32_t * addr, size_t count) { while (count--) { *addr = *(volatile u_int32_t *)(handle + offset); *addr = bswap32(*addr); addr++; } } /* * Write the 1, 2, 4, or 8 byte value `value' to bus space * described by tag/handle/offset. */ static void rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int8_t value) { mips_sync(); *(volatile u_int8_t *)(handle + offset) = value; } static void rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int16_t value) { mips_sync(); *(volatile u_int16_t *)(handle + offset) = bswap16(value); } static void rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int32_t value) { mips_sync(); *(volatile u_int32_t *)(handle + offset) = bswap32(value); } /* * Write `count' 1, 2, 4, or 8 byte quantities from the buffer * provided to bus space described by tag/handle/offset. */ static void rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle, bus_size_t offset, const u_int8_t * addr, size_t count) { mips_sync(); while (count--) { (*(volatile u_int8_t *)(handle + offset)) = *addr; addr++; } } static void rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle, bus_size_t offset, const u_int16_t * addr, size_t count) { mips_sync(); while (count--) { (*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr); addr++; } } static void rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle, bus_size_t offset, const u_int32_t * addr, size_t count) { mips_sync(); while (count--) { (*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr); addr++; } } /* * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described * by tag/handle starting at `offset'. */ static void rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int16_t value, size_t count) { bus_addr_t addr = bsh + offset; for (; count != 0; count--, addr += 2) (*(volatile u_int16_t *)(addr)) = value; } static void rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int32_t value, size_t count) { bus_addr_t addr = bsh + offset; for (; count != 0; count--, addr += 4) (*(volatile u_int32_t *)(addr)) = value; } /* * Copy `count' 1, 2, 4, or 8 byte values from bus space starting * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. */ static void rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1, bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, size_t count) { TODO(); } /* * Read `count' 1, 2, 4, or 8 byte quantities from bus space * described by tag/handle/offset and copy into buffer provided. */ u_int8_t rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, bus_size_t offset) { return *((volatile u_int8_t *)(handle + offset)); } static u_int16_t rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset) { return *(volatile u_int16_t *)(handle + offset); } static u_int32_t rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset) { return (*(volatile u_int32_t *)(handle + offset)); } static void rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int8_t * addr, size_t count) { while (count--) { *addr = (*(volatile u_int8_t *)(handle + offset)); addr++; } } static void rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int16_t * addr, size_t count) { while (count--) { *addr = (*(volatile u_int16_t *)(handle + offset)); addr++; } } static void rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle, bus_size_t offset, u_int32_t * addr, size_t count) { while (count--) { *addr = (*(volatile u_int32_t *)(handle + offset)); addr++; } } /* * Read `count' 1, 2, 4, or 8 byte quantities from bus space * described by tag/handle and starting at `offset' and copy into * buffer provided. */ void rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int8_t * addr, size_t count) { bus_addr_t baddr = bsh + offset; while (count--) { *addr++ = (*(volatile u_int8_t *)(baddr)); baddr += 1; } } void rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int16_t * addr, size_t count) { bus_addr_t baddr = bsh + offset; while (count--) { *addr++ = (*(volatile u_int16_t *)(baddr)); baddr += 2; } } void rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, u_int32_t * addr, size_t count) { bus_addr_t baddr = bsh + offset; while (count--) { *addr++ = (*(volatile u_int32_t *)(baddr)); baddr += 4; } } void rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle, bus_size_t offset, u_int8_t value) { mips_sync(); *(volatile u_int8_t *)(handle + offset) = value; } static void rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, bus_size_t offset, u_int16_t value) { mips_sync(); *(volatile u_int16_t *)(handle + offset) = value; } static void rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, bus_size_t offset, u_int32_t value) { mips_sync(); *(volatile u_int32_t *)(handle + offset) = value; } static void rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle, bus_size_t offset, const u_int8_t * addr, size_t count) { mips_sync(); while (count--) { (*(volatile u_int8_t *)(handle + offset)) = *addr; addr++; } } static void rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle, bus_size_t offset, const u_int16_t * addr, size_t count) { mips_sync(); while (count--) { (*(volatile u_int16_t *)(handle + offset)) = *addr; addr++; } } static void rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle, bus_size_t offset, const u_int32_t * addr, size_t count) { mips_sync(); while (count--) { (*(volatile u_int32_t *)(handle + offset)) = *addr; addr++; } } void rmi_pci_bus_space_write_region_2(void *t, bus_space_handle_t bsh, bus_size_t offset, const u_int16_t * addr, size_t count) { bus_addr_t baddr = (bus_addr_t) bsh + offset; while (count--) { (*(volatile u_int16_t *)(baddr)) = *addr; addr++; baddr += 2; } } void rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh, bus_size_t offset, const u_int32_t * addr, size_t count) { bus_addr_t baddr = bsh + offset; while (count--) { (*(volatile u_int32_t *)(baddr)) = *addr; addr++; baddr += 4; } } static void rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, bus_size_t offset __unused, bus_size_t len __unused, int flags) { } Index: head/sys/mips/nlm/cms.c =================================================================== --- head/sys/mips/nlm/cms.c (revision 279386) +++ head/sys/mips/nlm/cms.c (revision 279387) @@ -1,501 +1,501 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define MSGRNG_NSTATIONS 1024 /* * Keep track of our message ring handler threads, each core has a * different message station. Ideally we will need to start a few * message handling threads every core, and wake them up depending on * load */ struct msgring_thread { struct thread *thread; /* msgring handler threads */ int needed; /* thread needs to wake up */ }; static struct msgring_thread msgring_threads[XLP_MAX_CORES * XLP_MAX_THREADS]; static struct proc *msgring_proc; /* all threads are under a proc */ /* * The device drivers can register a handler for the messages sent * from a station (corresponding to the device). */ struct tx_stn_handler { msgring_handler action; void *arg; }; static struct tx_stn_handler msgmap[MSGRNG_NSTATIONS]; static struct mtx msgmap_lock; uint32_t xlp_msg_thread_mask; static int xlp_msg_threads_per_core = XLP_MAX_THREADS; static void create_msgring_thread(int hwtid); static int msgring_process_fast_intr(void *arg); /* Debug counters */ static int msgring_nintr[XLP_MAX_CORES * XLP_MAX_THREADS]; static int msgring_wakeup_sleep[XLP_MAX_CORES * XLP_MAX_THREADS]; static int msgring_wakeup_nosleep[XLP_MAX_CORES * XLP_MAX_THREADS]; static int fmn_msgcount[XLP_MAX_CORES * XLP_MAX_THREADS][4]; static int fmn_loops[XLP_MAX_CORES * XLP_MAX_THREADS]; /* Whether polled driver implementation */ static int polled = 0; /* We do only i/o device credit setup here. CPU credit setup is now - * moved to xlp_msgring_cpu_init() so that the credits get setup + * moved to xlp_msgring_cpu_init() so that the credits get setup * only if the CPU exists. xlp_msgring_cpu_init() gets called from * platform_init_ap; and this makes it easy for us to setup CMS * credits for various types of XLP chips, with varying number of * cpu's and cores. */ static void xlp_cms_credit_setup(int credit) { uint64_t cmspcibase, cmsbase, pcibase; uint32_t devoffset; int dev, fn, maxqid; int src, qid, i; for (i = 0; i < XLP_MAX_NODES; i++) { cmspcibase = nlm_get_cms_pcibase(i); if (!nlm_dev_exists(XLP_IO_CMS_OFFSET(i))) continue; cmsbase = nlm_get_cms_regbase(i); maxqid = nlm_read_reg(cmspcibase, XLP_PCI_DEVINFO_REG0); for (dev = 0; dev < 8; dev++) { for (fn = 0; fn < 8; fn++) { devoffset = XLP_HDR_OFFSET(i, 0, dev, fn); if (nlm_dev_exists(devoffset) == 0) continue; pcibase = nlm_pcicfg_base(devoffset); src = nlm_qidstart(pcibase); if (src == 0) continue; #if 0 /* Debug */ printf("Setup CMS credits for queues "); printf("[%d to %d] from src %d\n", 0, maxqid, src); #endif for (qid = 0; qid < maxqid; qid++) nlm_cms_setup_credits(cmsbase, qid, src, credit); } } } } void xlp_msgring_cpu_init(int node, int cpu, int credit) { uint64_t cmspcibase = nlm_get_cms_pcibase(node); uint64_t cmsbase = nlm_get_cms_regbase(node); int qid, maxqid, src; maxqid = nlm_read_reg(cmspcibase, XLP_PCI_DEVINFO_REG0); /* cpu credit setup is done only from thread-0 of each core */ if((cpu % 4) == 0) { src = cpu << 2; /* each thread has 4 vc's */ for (qid = 0; qid < maxqid; qid++) nlm_cms_setup_credits(cmsbase, qid, src, credit); } } /* * Drain out max_messages for the buckets set in the bucket mask. * Use max_msgs = 0 to drain out all messages. */ int xlp_handle_msg_vc(u_int vcmask, int max_msgs) { struct nlm_fmn_msg msg; int srcid = 0, size = 0, code = 0; struct tx_stn_handler *he; uint32_t mflags, status; int n_msgs = 0, vc, m, hwtid; u_int msgmask; hwtid = nlm_cpuid(); for (;;) { /* check if VC empty */ mflags = nlm_save_flags_cop2(); status = nlm_read_c2_msgstatus1(); nlm_restore_flags(mflags); msgmask = ((status >> 24) & 0xf) ^ 0xf; msgmask &= vcmask; if (msgmask == 0) break; m = 0; for (vc = 0; vc < 4; vc++) { if ((msgmask & (1 << vc)) == 0) continue; mflags = nlm_save_flags_cop2(); status = nlm_fmn_msgrcv(vc, &srcid, &size, &code, - &msg); + &msg); nlm_restore_flags(mflags); - if (status != 0) /* no msg or error */ + if (status != 0) /* no msg or error */ continue; if (srcid < 0 && srcid >= 1024) { printf("[%s]: bad src id %d\n", __func__, srcid); continue; } he = &msgmap[srcid]; if(he->action != NULL) (he->action)(vc, size, code, srcid, &msg, he->arg); #if 0 else printf("[%s]: No Handler for msg from stn %d," " vc=%d, size=%d, msg0=%jx, droppinge\n", __func__, srcid, vc, size, (uintmax_t)msg.msg[0]); #endif fmn_msgcount[hwtid][vc] += 1; m++; /* msgs handled in this iter */ } if (m == 0) break; /* nothing done in this iter */ n_msgs += m; if (max_msgs > 0 && n_msgs >= max_msgs) break; } return (n_msgs); } static void xlp_discard_msg_vc(u_int vcmask) { struct nlm_fmn_msg msg; int srcid = 0, size = 0, code = 0, vc; uint32_t mflags, status; for (vc = 0; vc < 4; vc++) { for (;;) { mflags = nlm_save_flags_cop2(); status = nlm_fmn_msgrcv(vc, &srcid, &size, &code, &msg); nlm_restore_flags(mflags); /* break if there is no msg or error */ if (status != 0) break; } } } void xlp_cms_enable_intr(int node, int cpu, int type, int watermark) { uint64_t cmsbase; int i, qid; cmsbase = nlm_get_cms_regbase(node); for (i = 0; i < 4; i++) { qid = (i + (cpu * 4)) & 0x7f; nlm_cms_per_queue_level_intr(cmsbase, qid, type, watermark); nlm_cms_per_queue_timer_intr(cmsbase, qid, 0x1, 0); } } static int msgring_process_fast_intr(void *arg) { struct msgring_thread *mthd; struct thread *td; int cpu; cpu = nlm_cpuid(); mthd = &msgring_threads[cpu]; msgring_nintr[cpu]++; td = mthd->thread; /* clear pending interrupts */ nlm_write_c0_eirr(1ULL << IRQ_MSGRING); /* wake up the target thread */ mthd->needed = 1; thread_lock(td); if (TD_AWAITING_INTR(td)) { msgring_wakeup_sleep[cpu]++; TD_CLR_IWAIT(td); sched_add(td, SRQ_INTR); } else msgring_wakeup_nosleep[cpu]++; thread_unlock(td); return (FILTER_HANDLED); } static void msgring_process(void * arg) { volatile struct msgring_thread *mthd; struct thread *td; uint32_t mflags, msgstatus1; int hwtid, nmsgs; hwtid = (intptr_t)arg; mthd = &msgring_threads[hwtid]; td = mthd->thread; KASSERT(curthread == td, ("%s:msg_ithread and proc linkage out of sync", __func__)); /* First bind this thread to the right CPU */ thread_lock(td); sched_bind(td, xlp_hwtid_to_cpuid[hwtid]); thread_unlock(td); if (hwtid != nlm_cpuid()) printf("Misscheduled hwtid %d != cpuid %d\n", hwtid, nlm_cpuid()); xlp_discard_msg_vc(0xf); xlp_msgring_cpu_init(nlm_nodeid(), nlm_cpuid(), CMS_DEFAULT_CREDIT); if (polled == 0) { mflags = nlm_save_flags_cop2(); nlm_fmn_cpu_init(IRQ_MSGRING, 0, 0, 0, 0, 0); nlm_restore_flags(mflags); xlp_cms_enable_intr(nlm_nodeid(), nlm_cpuid(), 0x2, 0); /* clear pending interrupts. * they will get re-raised if still valid */ nlm_write_c0_eirr(1ULL << IRQ_MSGRING); } /* start processing messages */ for (;;) { atomic_store_rel_int(&mthd->needed, 0); nmsgs = xlp_handle_msg_vc(0xf, 0); /* sleep */ if (polled == 0) { /* clear VC-pend bits */ mflags = nlm_save_flags_cop2(); msgstatus1 = nlm_read_c2_msgstatus1(); msgstatus1 |= (0xf << 16); nlm_write_c2_msgstatus1(msgstatus1); nlm_restore_flags(mflags); thread_lock(td); if (mthd->needed) { thread_unlock(td); continue; } sched_class(td, PRI_ITHD); TD_SET_IWAIT(td); mi_switch(SW_VOL, NULL); thread_unlock(td); } else pause("wmsg", 1); fmn_loops[hwtid]++; } } static void create_msgring_thread(int hwtid) { struct msgring_thread *mthd; struct thread *td; int error; mthd = &msgring_threads[hwtid]; error = kproc_kthread_add(msgring_process, (void *)(uintptr_t)hwtid, &msgring_proc, &td, RFSTOPPED, 2, "msgrngproc", "msgthr%d", hwtid); if (error) panic("kproc_kthread_add() failed with %d", error); mthd->thread = td; thread_lock(td); sched_class(td, PRI_ITHD); sched_add(td, SRQ_INTR); thread_unlock(td); } int register_msgring_handler(int startb, int endb, msgring_handler action, void *arg) { int i; if (bootverbose) printf("Register handler %d-%d %p(%p)\n", startb, endb, action, arg); KASSERT(startb >= 0 && startb <= endb && endb < MSGRNG_NSTATIONS, ("Invalid value for bucket range %d,%d", startb, endb)); mtx_lock_spin(&msgmap_lock); for (i = startb; i <= endb; i++) { KASSERT(msgmap[i].action == NULL, ("Bucket %d already used [action %p]", i, msgmap[i].action)); msgmap[i].action = action; msgmap[i].arg = arg; } mtx_unlock_spin(&msgmap_lock); return (0); } /* * Initialize the messaging subsystem. * * Message Stations are shared among all threads in a cpu core, this * has to be called once from every core which is online. */ static void xlp_msgring_config(void *arg) { void *cookie; unsigned int thrmask, mask; int i; /* used polled handler for Ax silion */ if (nlm_is_xlp8xx_ax()) polled = 1; /* Don't poll on all threads, if polled */ if (polled) xlp_msg_threads_per_core -= 1; mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN); if (xlp_threads_per_core < xlp_msg_threads_per_core) xlp_msg_threads_per_core = xlp_threads_per_core; thrmask = ((1 << xlp_msg_threads_per_core) - 1); mask = 0; for (i = 0; i < XLP_MAX_CORES; i++) { mask <<= XLP_MAX_THREADS; mask |= thrmask; } xlp_msg_thread_mask = xlp_hw_thread_mask & mask; #if 0 printf("CMS Message handler thread mask %#jx\n", (uintmax_t)xlp_msg_thread_mask); #endif xlp_cms_credit_setup(CMS_DEFAULT_CREDIT); create_msgring_thread(0); cpu_establish_hardintr("msgring", msgring_process_fast_intr, NULL, NULL, IRQ_MSGRING, INTR_TYPE_NET, &cookie); } /* * Start message ring processing threads on other CPUs, after SMP start */ static void start_msgring_threads(void *arg) { int hwt; for (hwt = 1; hwt < XLP_MAX_CORES * XLP_MAX_THREADS; hwt++) { if ((xlp_msg_thread_mask & (1 << hwt)) == 0) continue; create_msgring_thread(hwt); } } SYSINIT(xlp_msgring_config, SI_SUB_DRIVERS, SI_ORDER_FIRST, xlp_msgring_config, NULL); SYSINIT(start_msgring_threads, SI_SUB_SMP, SI_ORDER_MIDDLE, start_msgring_threads, NULL); /* * DEBUG support, XXX: static buffer, not locked */ static int sys_print_debug(SYSCTL_HANDLER_ARGS) { int error, nb, i, fs; static char xprintb[4096], *buf; buf = xprintb; fs = sizeof(xprintb); nb = snprintf(buf, fs, "\nID vc0 vc1 vc2 vc3 loops\n"); buf += nb; fs -= nb; for (i = 0; i < 32; i++) { if ((xlp_hw_thread_mask & (1 << i)) == 0) continue; nb = snprintf(buf, fs, "%2d: %8d %8d %8d %8d %8d\n", i, fmn_msgcount[i][0], fmn_msgcount[i][1], fmn_msgcount[i][2], fmn_msgcount[i][3], fmn_loops[i]); buf += nb; fs -= nb; } error = SYSCTL_OUT(req, xprintb, buf - xprintb); return (error); } SYSCTL_PROC(_debug, OID_AUTO, msgring, CTLTYPE_STRING | CTLFLAG_RD, 0, 0, sys_print_debug, "A", "msgring debug info"); Index: head/sys/mips/nlm/hal/fmn.h =================================================================== --- head/sys/mips/nlm/hal/fmn.h (revision 279386) +++ head/sys/mips/nlm/hal/fmn.h (revision 279387) @@ -1,245 +1,245 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef __NLM_FMNV2_H__ #define __NLM_FMNV2_H__ /** * @file_name fmn.h * @author Netlogic Microsystems * @brief HAL for Fast message network V2 */ /* FMN configuration registers */ #define CMS_OUTPUTQ_CONFIG(i) ((i)*2) #define CMS_MAX_OUTPUTQ 1024 #define CMS_OUTPUTQ_CREDIT_CFG (0x2000/4) #define CMS_MSG_CONFIG (0x2008/4) #define CMS_MSG_ERR (0x2010/4) #define CMS_TRACE_CONFIG (0x2018/4) #define CMS_TRACE_BASE_ADDR (0x2020/4) #define CMS_TRACE_LIMIT_ADDR (0x2028/4) #define CMS_TRACE_CURRENT_ADDR (0x2030/4) #define CMS_MSG_ENDIAN_SWAP (0x2038/4) #define CMS_CPU_PUSHQ(node, core, thread, vc) \ (((node)<<10) | ((core)<<4) | ((thread)<<2) | ((vc)<<0)) #define CMS_POPQ(node, queue) (((node)<<10) | (queue)) #define CMS_IO_PUSHQ(node, queue) (((node)<<10) | (queue)) #define CMS_POPQ_QID(i) (128+(i)) /* FMN Level Interrupt Type */ #define CMS_LVL_INTR_DISABLE 0 #define CMS_LVL_LOW_WATERMARK 1 #define CMS_LVL_HI_WATERMARK 2 /* FMN Level interrupt trigger values */ #define CMS_QUEUE_NON_EMPTY 0 #define CMS_QUEUE_QUARTER_FULL 1 #define CMS_QUEUE_HALF_FULL 2 #define CMS_QUEUE_THREE_QUARTER_FULL 3 #define CMS_QUEUE_FULL 4 /* FMN Timer Interrupt Type */ #define CMS_TIMER_INTR_DISABLE 0 #define CMS_TIMER_CONSUMER 1 #define CMS_TIMER_PRODUCER 1 /* FMN timer interrupt trigger values */ #define CMS_TWO_POW_EIGHT_CYCLES 0 #define CMS_TWO_POW_TEN_CYCLES 1 #define CMS_TWO_POW_TWELVE_CYCLES 2 #define CMS_TWO_POW_FOURTEEN_CYCLES 3 #define CMS_TWO_POW_SIXTEEN_CYCLES 4 #define CMS_TWO_POW_EIGHTTEEN_CYCLES 5 #define CMS_TWO_POW_TWENTY_CYCLES 6 #define CMS_TWO_POW_TWENTYTWO_CYCLES 7 #define CMS_QUEUE_ENA 1ULL #define CMS_QUEUE_DIS 0 #define CMS_SPILL_ENA 1ULL #define CMS_SPILL_DIS 0 #define CMS_MAX_VCPU_VC 4 /* Each XLP chip can hold upto 32K messages on the chip itself */ #define CMS_ON_CHIP_MESG_SPACE (32*1024) #define CMS_MAX_ONCHIP_SEGMENTS 1024 -#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64 +#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64 /* FMN Network error */ #define CMS_ILLEGAL_DST_ERROR 0x100 #define CMS_BIU_TIMEOUT_ERROR 0x080 #define CMS_BIU_ERROR 0x040 #define CMS_SPILL_FILL_UNCORRECT_ECC_ERROR 0x020 #define CMS_SPILL_FILL_CORRECT_ECC_ERROR 0x010 #define CMS_SPILL_UNCORRECT_ECC_ERROR 0x008 #define CMS_SPILL_CORRECT_ECC_ERROR 0x004 #define CMS_OUTPUTQ_UNCORRECT_ECC_ERROR 0x002 #define CMS_OUTPUTQ_CORRECT_ECC_ERROR 0x001 /* worst case, a single entry message consists of a 4 byte header * and an 8-byte entry = 12 bytes in total */ #define CMS_SINGLE_ENTRY_MSG_SIZE 12 /* total spill memory needed for one FMN queue */ #define CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs) \ ((spilltotmsgs) * (CMS_SINGLE_ENTRY_MSG_SIZE)) /* FMN Src station id's */ #define CMS_CPU0_SRC_STID (0 << 4) #define CMS_CPU1_SRC_STID (1 << 4) #define CMS_CPU2_SRC_STID (2 << 4) #define CMS_CPU3_SRC_STID (3 << 4) #define CMS_CPU4_SRC_STID (4 << 4) #define CMS_CPU5_SRC_STID (5 << 4) #define CMS_CPU6_SRC_STID (6 << 4) #define CMS_CPU7_SRC_STID (7 << 4) #define CMS_PCIE0_SRC_STID 256 #define CMS_PCIE1_SRC_STID 258 #define CMS_PCIE2_SRC_STID 260 #define CMS_PCIE3_SRC_STID 262 #define CMS_DTE_SRC_STID 264 #define CMS_RSA_ECC_SRC_STID 272 #define CMS_CRYPTO_SRC_STID 281 #define CMS_CMP_SRC_STID 298 #define CMS_POE_SRC_STID 384 #define CMS_NAE_SRC_STID 476 /* POPQ related defines */ #define CMS_POPQID_START 128 #define CMS_POPQID_END 255 #define CMS_INT_RCVD 0x800000000000000ULL #define nlm_read_cms_reg(b, r) nlm_read_reg64_xkphys(b,r) #define nlm_write_cms_reg(b, r, v) nlm_write_reg64_xkphys(b,r,v) #define nlm_get_cms_pcibase(node) \ nlm_pcicfg_base(XLP_IO_CMS_OFFSET(node)) #define nlm_get_cms_regbase(node) \ nlm_xkphys_map_pcibar0(nlm_get_cms_pcibase(node)) #define XLP_CMS_ON_CHIP_PER_QUEUE_SPACE(node) \ ((XLP_CMS_ON_CHIP_MESG_SPACE)/ \ (nlm_read_reg(nlm_pcibase_cms(node), \ XLP_PCI_DEVINFO_REG0)) /* total spill memory needed */ #define XLP_CMS_TOTAL_SPILL_MEM(node, spilltotmsgs) \ ((XLP_CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs)) * \ (nlm_read_reg(nlm_pcibase_cms(node), \ XLP_PCI_DEVINFO_REG0)) #define CMS_TOTAL_QUEUE_SIZE(node, spilltotmsgs) \ ((spilltotmsgs) + (CMS_ON_CHIP_PER_QUEUE_SPACE(node))) enum fmn_swcode { FMN_SWCODE_CPU0=1, FMN_SWCODE_CPU1, FMN_SWCODE_CPU2, FMN_SWCODE_CPU3, FMN_SWCODE_CPU4, FMN_SWCODE_CPU5, FMN_SWCODE_CPU6, FMN_SWCODE_CPU7, FMN_SWCODE_CPU8, FMN_SWCODE_CPU9, FMN_SWCODE_CPU10, FMN_SWCODE_CPU11, FMN_SWCODE_CPU12, FMN_SWCODE_CPU13, FMN_SWCODE_CPU14, FMN_SWCODE_CPU15, FMN_SWCODE_CPU16, FMN_SWCODE_CPU17, FMN_SWCODE_CPU18, FMN_SWCODE_CPU19, FMN_SWCODE_CPU20, FMN_SWCODE_CPU21, FMN_SWCODE_CPU22, FMN_SWCODE_CPU23, FMN_SWCODE_CPU24, FMN_SWCODE_CPU25, FMN_SWCODE_CPU26, FMN_SWCODE_CPU27, FMN_SWCODE_CPU28, FMN_SWCODE_CPU29, FMN_SWCODE_CPU30, FMN_SWCODE_CPU31, FMN_SWCODE_CPU32, FMN_SWCODE_PCIE0, FMN_SWCODE_PCIE1, FMN_SWCODE_PCIE2, FMN_SWCODE_PCIE3, FMN_SWCODE_DTE, FMN_SWCODE_CRYPTO, FMN_SWCODE_RSA, FMN_SWCODE_CMP, FMN_SWCODE_POE, FMN_SWCODE_NAE, }; extern uint64_t nlm_cms_spill_total_messages; extern uint32_t nlm_cms_total_stations; extern uint64_t cms_base_addr(int node); extern int nlm_cms_verify_credit_config (int spill_en, int tot_credit); extern int nlm_cms_get_oc_space(int qsize, int max_queues, int qid, int *ocbase, int *ocstart, int *ocend); extern void nlm_cms_setup_credits (uint64_t base, int destid, int srcid, int credit); extern int nlm_cms_config_onchip_queue (uint64_t base, uint64_t cms_spill_base, int qid, int spill_en); extern void nlm_cms_default_setup(int node, uint64_t spill_base, int spill_en, int popq_en); extern uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid); extern void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val); extern void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type, int intr_val); extern void nlm_cms_level_intr(int node, int sub_type, int intr_val); extern void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type, int intr_val); extern void nlm_cms_timer_intr(int node, int en, int sub_type, int intr_val); extern int nlm_cms_outputq_intr_check(uint64_t base, int qid); extern void nlm_cms_outputq_clr_intr(uint64_t base, int qid); extern void nlm_cms_illegal_dst_error_intr(uint64_t base, int en); extern void nlm_cms_timeout_error_intr(uint64_t base, int en); extern void nlm_cms_biu_error_resp_intr(uint64_t base, int en); extern void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en); extern void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en); extern void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en); extern void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en); extern uint64_t nlm_cms_network_error_status(uint64_t base); extern int nlm_cms_get_net_error_code(uint64_t err); extern int nlm_cms_get_net_error_syndrome(uint64_t err); extern int nlm_cms_get_net_error_ramindex(uint64_t err); extern int nlm_cms_get_net_error_outputq(uint64_t err); extern void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base, uint64_t trace_limit, int match_dstid_en, int dst_id, int match_srcid_en, int src_id, int wrap); extern void nlm_cms_endian_byte_swap (uint64_t base, int en); extern uint8_t xlp_msg_send(uint8_t vc, uint8_t size); extern int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base, int nsegs); extern int nlm_cms_alloc_onchip_q(uint64_t base, int qid, int nsegs); #endif Index: head/sys/mips/nlm/hal/gbu.h =================================================================== --- head/sys/mips/nlm/hal/gbu.h (revision 279386) +++ head/sys/mips/nlm/hal/gbu.h (revision 279387) @@ -1,100 +1,100 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _NLM_HAL_GBU_H__ #define _NLM_HAL_GBU_H__ /* Global Bus Unit (GBU) for flash Specific registers */ #define GBU_CS_BASEADDR(cs) (0x0+cs) #define GBU_CS0_BASEADDR 0x0 #define GBU_CS1_BASEADDR 0x1 #define GBU_CS2_BASEADDR 0x2 #define GBU_CS3_BASEADDR 0x3 #define GBU_CS4_BASEADDR 0x4 #define GBU_CS5_BASEADDR 0x5 #define GBU_CS6_BASEADDR 0x6 #define GBU_CS7_BASEADDR 0x7 #define GBU_CS_BASELIMIT(cs) (0x8+cs) #define GBU_CS0_BASELIMIT 0x8 #define GBU_CS1_BASELIMIT 0x9 #define GBU_CS2_BASELIMIT 0xa #define GBU_CS3_BASELIMIT 0xb #define GBU_CS4_BASELIMIT 0xc #define GBU_CS5_BASELIMIT 0xd #define GBU_CS6_BASELIMIT 0xe #define GBU_CS7_BASELIMIT 0xf #define GBU_CS_DEVPARAM(cs) (0x10+cs) #define GBU_CS0_DEVPARAM 0x10 #define GBU_CS1_DEVPARAM 0x11 #define GBU_CS2_DEVPARAM 0x12 #define GBU_CS3_DEVPARAM 0x13 #define GBU_CS4_DEVPARAM 0x14 #define GBU_CS5_DEVPARAM 0x15 #define GBU_CS6_DEVPARAM 0x16 #define GBU_CS7_DEVPARAM 0x17 #define GBU_CS_DEVTIME0(cs) (0x18+cs) #define GBU_CS0_DEVTIME0 0x18 #define GBU_CS1_DEVTIME0 0x1a #define GBU_CS2_DEVTIME0 0x1c #define GBU_CS3_DEVTIME0 0x1e #define GBU_CS4_DEVTIME0 0x20 #define GBU_CS5_DEVTIME0 0x22 #define GBU_CS6_DEVTIME0 0x24 #define GBU_CS7_DEVTIME0 0x26 #define GBU_CS_DEVTIME1(cs) (0x19+cs) #define GBU_CS0_DEVTIME1 0x19 #define GBU_CS1_DEVTIME1 0x1b #define GBU_CS2_DEVTIME1 0x1d #define GBU_CS3_DEVTIME1 0x1f #define GBU_CS4_DEVTIME1 0x21 #define GBU_CS5_DEVTIME1 0x23 #define GBU_CS6_DEVTIME1 0x25 #define GBU_CS7_DEVTIME1 0x27 #define GBU_SYSCTRL 0x28 #define GBU_BYTESWAP 0x29 #define GBU_DI_TIMEOUT_VAL 0x2d #define GBU_INTSTAT 0x2e #define GBU_INTEN 0x2f #define GBU_STATUS 0x30 #define GBU_ERRLOG0 0x2a #define GBU_ERRLOG1 0x2b #define GBU_ERRLOG2 0x2c #if !defined(LOCORE) && !defined(__ASSEMBLY__) #define nlm_read_gbu_reg(b, r) nlm_read_reg(b, r) #define nlm_write_gbu_reg(b, r, v) nlm_write_reg(b, r, v) #define nlm_get_gbu_pcibase(node) \ nlm_pcicfg_base(XLP_IO_NOR_OFFSET(node)) #define nlm_get_gbu_regbase(node) \ (nlm_get_gbu_pcibase(node) + XLP_IO_PCI_HDRSZ) #endif /* !LOCORE && !__ASSEMBLY__ */ #endif /* _NLM_HAL_GBU_H__ */ Index: head/sys/mips/nlm/hal/interlaken.h =================================================================== --- head/sys/mips/nlm/hal/interlaken.h (revision 279386) +++ head/sys/mips/nlm/hal/interlaken.h (revision 279387) @@ -1,70 +1,70 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __NLM_ILAKEN_H__ #define __NLM_ILAKEN_H__ /** * @file_name interlaken.h * @author Netlogic Microsystems * @brief Basic definitions of XLP ILAKEN ports */ #define ILK_TX_CONTROL(block) NAE_REG(block, 5, 0x00) #define ILK_TX_RATE_LIMIT(block) NAE_REG(block, 5, 0x01) #define ILK_TX_META_CTRL(block) NAE_REG(block, 5, 0x02) #define ILK_RX_CTRL(block) NAE_REG(block, 5, 0x03) #define ILK_RX_STATUS1(block) NAE_REG(block, 5, 0x04) #define ILK_RX_STATUS2(block) NAE_REG(block, 5, 0x05) #define ILK_GENERAL_CTRL1(block) NAE_REG(block, 5, 0x06) #define ILK_STATUS3(block) NAE_REG(block, 5, 0x07) #define ILK_RX_FC_TMAP0(block) NAE_REG(block, 5, 0x08) #define ILK_RX_FC_TMAP1(block) NAE_REG(block, 5, 0x09) #define ILK_RX_FC_TMAP2(block) NAE_REG(block, 5, 0x0a) #define ILK_RX_FC_TMAP3(block) NAE_REG(block, 5, 0x0b) #define ILK_RX_FC_TMAP4(block) NAE_REG(block, 5, 0x0c) #define ILK_RX_FC_TADDR(block) NAE_REG(block, 5, 0x0d) #define ILK_GENERAL_CTRL2(block) NAE_REG(block, 5, 0x0e) #define ILK_GENERAL_CTRL3(block) NAE_REG(block, 5, 0x0f) #define ILK_SMALL_COUNT0(block) NAE_REG(block, 5, 0x10) #define ILK_SMALL_COUNT1(block) NAE_REG(block, 5, 0x11) #define ILK_SMALL_COUNT2(block) NAE_REG(block, 5, 0x12) #define ILK_SMALL_COUNT3(block) NAE_REG(block, 5, 0x13) #define ILK_SMALL_COUNT4(block) NAE_REG(block, 5, 0x14) #define ILK_SMALL_COUNT5(block) NAE_REG(block, 5, 0x15) #define ILK_SMALL_COUNT6(block) NAE_REG(block, 5, 0x16) #define ILK_SMALL_COUNT7(block) NAE_REG(block, 5, 0x17) #define ILK_MID_COUNT0(block) NAE_REG(block, 5, 0x18) #define ILK_MID_COUNT1(block) NAE_REG(block, 5, 0x19) #define ILK_LARGE_COUNT0(block) NAE_REG(block, 5, 0x1a) #define ILK_LARGE_COUNT1(block) NAE_REG(block, 5, 0x1b) #define ILK_LARGE_COUNT_H0(block) NAE_REG(block, 5, 0x1c) #define ILK_LARGE_COUNT_H1(block) NAE_REG(block, 5, 0x1d) #endif Index: head/sys/mips/nlm/hal/mdio.h =================================================================== --- head/sys/mips/nlm/hal/mdio.h (revision 279386) +++ head/sys/mips/nlm/hal/mdio.h (revision 279387) @@ -1,106 +1,106 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __NLM_MDIO_H__ #define __NLM_MDIO_H__ /** * @file_name mdio.h * @author Netlogic Microsystems -* @brief Access functions for XLP MDIO +* @brief Access functions for XLP MDIO */ #define INT_MDIO_CTRL 0x19 #define INT_MDIO_CTRL_DATA 0x1A #define INT_MDIO_RD_STAT 0x1B #define INT_MDIO_LINK_STAT 0x1C #define EXT_G0_MDIO_CTRL 0x1D #define EXT_G1_MDIO_CTRL 0x21 #define EXT_G0_MDIO_CTRL_DATA 0x1E #define EXT_G1_MDIO_CTRL_DATA 0x22 #define EXT_G0_MDIO_LINK_STAT 0x20 #define EXT_G1_MDIO_LINK_STAT 0x24 #define EXT_G0_MDIO_RD_STAT 0x1F #define EXT_G1_MDIO_RD_STAT 0x23 #define INT_MDIO_CTRL_ST_POS 0 #define INT_MDIO_CTRL_OP_POS 2 #define INT_MDIO_CTRL_PHYADDR_POS 4 #define INT_MDIO_CTRL_DEVTYPE_POS 9 #define INT_MDIO_CTRL_TA_POS 14 #define INT_MDIO_CTRL_MIIM_POS 16 #define INT_MDIO_CTRL_LOAD_POS 19 #define INT_MDIO_CTRL_XDIV_POS 21 #define INT_MDIO_CTRL_MCDIV_POS 28 #define INT_MDIO_CTRL_RST 0x40000000 #define INT_MDIO_CTRL_SMP 0x00100000 #define INT_MDIO_CTRL_CMD_LOAD 0x00080000 #define INT_MDIO_RD_STAT_MASK 0x0000FFFF #define INT_MDIO_STAT_LFV 0x00010000 #define INT_MDIO_STAT_SC 0x00020000 #define INT_MDIO_STAT_SM 0x00040000 #define INT_MDIO_STAT_MIILFS 0x00080000 #define INT_MDIO_STAT_MBSY 0x00100000 #define EXT_G_MDIO_CLOCK_DIV_4 0 #define EXT_G_MDIO_CLOCK_DIV_2 1 #define EXT_G_MDIO_CLOCK_DIV_1 2 #define EXT_G_MDIO_REGADDR_POS 5 #define EXT_G_MDIO_PHYADDR_POS 10 #define EXT_G_MDIO_CMD_SP 0x00008000 #define EXT_G_MDIO_CMD_PSIA 0x00010000 #define EXT_G_MDIO_CMD_LCD 0x00020000 #define EXT_G_MDIO_CMD_RDS 0x00040000 #define EXT_G_MDIO_CMD_SC 0x00080000 #define EXT_G_MDIO_MMRST 0x00100000 #define EXT_G_MDIO_DIV 0x0000001E #define EXT_G_MDIO_DIV_WITH_HW_DIV64 0x00000010 #define EXT_G_MDIO_RD_STAT_MASK 0x0000FFFF #define EXT_G_MDIO_STAT_LFV 0x00010000 #define EXT_G_MDIO_STAT_SC 0x00020000 #define EXT_G_MDIO_STAT_SM 0x00040000 #define EXT_G_MDIO_STAT_MIILFS 0x00080000 #define EXT_G_MDIO_STAT_MBSY 0x80000000 #define MDIO_OP_CMD_READ 0x10 #define MDIO_OP_CMD_WRITE 0x01 #if !defined(LOCORE) && !defined(__ASSEMBLY__) int nlm_int_gmac_mdio_read(uint64_t, int, int, int, int, int); int nlm_int_gmac_mdio_write(uint64_t, int, int, int, int, int, uint16_t); int nlm_int_gmac_mdio_reset(uint64_t, int, int, int); int nlm_gmac_mdio_read(uint64_t, int, int, int, int, int); int nlm_gmac_mdio_write(uint64_t, int, int, int, int, int, uint16_t); int nlm_gmac_mdio_reset(uint64_t, int, int, int); void nlm_mdio_reset_all(uint64_t); #endif /* !(LOCORE) && !(__ASSEMBLY__) */ #endif Index: head/sys/mips/nlm/hal/mips-extns.h =================================================================== --- head/sys/mips/nlm/hal/mips-extns.h (revision 279386) +++ head/sys/mips/nlm/hal/mips-extns.h (revision 279387) @@ -1,274 +1,274 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef __NLM_MIPS_EXTNS_H__ #define __NLM_MIPS_EXTNS_H__ #if !defined(LOCORE) && !defined(__ASSEMBLY__) static __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val) { int32_t oldval = 0; __asm__ __volatile__ ( ".set push\n" ".set noreorder\n" "move $9, %2\n" "move $8, %3\n" ".word 0x71280014\n" /* "swapw $8, $9\n" */ "move %1, $8\n" ".set pop\n" : "+m" (*loc), "=r" (oldval) : "r" (loc), "r" (val) : "$8", "$9" ); return oldval; } static __inline__ uint32_t nlm_swapwu(int32_t *loc, uint32_t val) { uint32_t oldval; __asm__ __volatile__ ( ".set push\n" ".set noreorder\n" "move $9, %2\n" "move $8, %3\n" ".word 0x71280015\n" /* "swapwu $8, $9\n" */ "move %1, $8\n" ".set pop\n" : "+m" (*loc), "=r" (oldval) : "r" (loc), "r" (val) : "$8", "$9" ); return oldval; } #if (__mips == 64) static __inline__ uint64_t nlm_swapd(int32_t *loc, uint64_t val) { uint64_t oldval; __asm__ __volatile__ ( ".set push\n" ".set noreorder\n" "move $9, %2\n" "move $8, %3\n" ".word 0x71280014\n" /* "swapw $8, $9\n" */ "move %1, $8\n" ".set pop\n" : "+m" (*loc), "=r" (oldval) : "r" (loc), "r" (val) : "$8", "$9" ); return oldval; } #endif /* * Atomic increment a unsigned int */ static __inline unsigned int nlm_ldaddwu(unsigned int value, unsigned int *addr) { __asm__ __volatile__( ".set push\n" ".set noreorder\n" "move $8, %2\n" "move $9, %3\n" ".word 0x71280011\n" /* ldaddwu $8, $9 */ "move %0, $8\n" ".set pop\n" : "=&r"(value), "+m"(*addr) : "0"(value), "r" ((unsigned long)addr) : "$8", "$9"); return (value); } /* * 32 bit read write for c0 */ #define read_c0_register32(reg, sel) \ ({ \ uint32_t __rv; \ __asm__ __volatile__( \ ".set push\n\t" \ ".set mips32\n\t" \ "mfc0 %0, $%1, %2\n\t" \ ".set pop\n" \ : "=r" (__rv) : "i" (reg), "i" (sel) ); \ __rv; \ }) #define write_c0_register32(reg, sel, value) \ __asm__ __volatile__( \ ".set push\n\t" \ ".set mips32\n\t" \ "mtc0 %0, $%1, %2\n\t" \ ".set pop\n" \ : : "r" (value), "i" (reg), "i" (sel) ); #if defined(__mips_n64) || defined(__mips_n32) /* * On 64 bit compilation, the operations are simple */ #define read_c0_register64(reg, sel) \ ({ \ uint64_t __rv; \ __asm__ __volatile__( \ ".set push\n\t" \ ".set mips64\n\t" \ "dmfc0 %0, $%1, %2\n\t" \ ".set pop\n" \ : "=r" (__rv) : "i" (reg), "i" (sel) ); \ __rv; \ }) #define write_c0_register64(reg, sel, value) \ __asm__ __volatile__( \ ".set push\n\t" \ ".set mips64\n\t" \ "dmtc0 %0, $%1, %2\n\t" \ ".set pop\n" \ : : "r" (value), "i" (reg), "i" (sel) ); #else /* ! (defined(__mips_n64) || defined(__mips_n32)) */ /* - * 32 bit compilation, 64 bit values has to split + * 32 bit compilation, 64 bit values has to split */ #define read_c0_register64(reg, sel) \ ({ \ uint32_t __high, __low; \ __asm__ __volatile__( \ ".set push\n\t" \ ".set noreorder\n\t" \ ".set mips64\n\t" \ "dmfc0 $8, $%2, %3\n\t" \ "dsra32 %0, $8, 0\n\t" \ "sll %1, $8, 0\n\t" \ ".set pop\n" \ : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \ : "$8"); \ ((uint64_t)__high << 32) | __low; \ }) #define write_c0_register64(reg, sel, value) \ do { \ uint32_t __high = value >> 32; \ uint32_t __low = value & 0xffffffff; \ __asm__ __volatile__( \ ".set push\n\t" \ ".set noreorder\n\t" \ ".set mips64\n\t" \ "dsll32 $8, %1, 0\n\t" \ "dsll32 $9, %0, 0\n\t" \ "dsrl32 $8, $8, 0\n\t" \ "or $8, $8, $9\n\t" \ "dmtc0 $8, $%2, %3\n\t" \ ".set pop" \ :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \ :"$8", "$9"); \ } while(0) #endif /* functions to write to and read from the extended * cp0 registers. * EIRR : Extended Interrupt Request Register * cp0 register 9 sel 6 * bits 0...7 are same as cause register 8...15 * EIMR : Extended Interrupt Mask Register * cp0 register 9 sel 7 * bits 0...7 are same as status register 8...15 */ -static __inline uint64_t +static __inline uint64_t nlm_read_c0_eirr(void) { return (read_c0_register64(9, 6)); } static __inline void nlm_write_c0_eirr(uint64_t val) { write_c0_register64(9, 6, val); } -static __inline uint64_t +static __inline uint64_t nlm_read_c0_eimr(void) { return (read_c0_register64(9, 7)); } static __inline void nlm_write_c0_eimr(uint64_t val) { write_c0_register64(9, 7, val); } static __inline__ uint32_t nlm_read_c0_ebase(void) { return (read_c0_register32(15, 1)); } static __inline__ int nlm_nodeid(void) { return (nlm_read_c0_ebase() >> 5) & 0x3; } static __inline__ int nlm_cpuid(void) { return nlm_read_c0_ebase() & 0x1f; } static __inline__ int nlm_threadid(void) { return nlm_read_c0_ebase() & 0x3; } static __inline__ int nlm_coreid(void) { return (nlm_read_c0_ebase() >> 2) & 0x7; } #endif #define XLP_MAX_NODES 4 #define XLP_MAX_CORES 8 #define XLP_MAX_THREADS 4 #endif Index: head/sys/mips/nlm/hal/mmu.h =================================================================== --- head/sys/mips/nlm/hal/mmu.h (revision 279386) +++ head/sys/mips/nlm/hal/mmu.h (revision 279387) @@ -1,165 +1,165 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef __XLP_MMU_H__ #define __XLP_MMU_H__ #include static __inline__ uint32_t nlm_read_c0_config6(void) { uint32_t rv; __asm__ __volatile__ ( ".set push\n" ".set mips64\n" "mfc0 %0, $16, 6\n" - ".set pop\n" + ".set pop\n" : "=r" (rv)); return rv; } static __inline__ void nlm_write_c0_config6(uint32_t value) { __asm__ __volatile__ ( ".set push\n" ".set mips64\n" "mtc0 %0, $16, 6\n" - ".set pop\n" + ".set pop\n" : : "r" (value)); } static __inline__ uint32_t nlm_read_c0_config7(void) { uint32_t rv; __asm__ __volatile__ ( ".set push\n" ".set mips64\n" "mfc0 %0, $16, 7\n" - ".set pop\n" + ".set pop\n" : "=r" (rv)); return rv; } static __inline__ void nlm_write_c0_config7(uint32_t value) { __asm__ __volatile__ ( ".set push\n" ".set mips64\n" "mtc0 %0, $16, 7\n" - ".set pop\n" + ".set pop\n" : : "r" (value)); } /** * On power on reset, XLP comes up with 64 TLBs. * Large-variable-tlb's (ELVT) and extended TLB is disabled. * Enabling large-variable-tlb's sets up the standard * TLB size from 64 to 128 TLBs. * Enabling fixed TLB (EFT) sets up an additional 2048 tlbs. * ELVT + EFT = 128 + 2048 = 2176 TLB entries. * threads 64-entry-standard-tlb 128-entry-standard-tlb * per std-tlb-only| std+EFT | std-tlb-only| std+EFT * core | | | * -------------------------------------------------------- * 1 64 64+2048 128 128+2048 * 2 64 64+1024 64 64+1024 * 4 32 32+512 32 32+512 * * 1(G) 64 64+2048 128 128+2048 * 2(G) 128 128+2048 128 128+2048 * 4(G) 128 128+2048 128 128+2048 * (G) = Global mode */ /* en = 1 to enable * en = 0 to disable */ static __inline__ void nlm_large_variable_tlb_en (int en) { unsigned int val; val = nlm_read_c0_config6(); val |= (en << 5); nlm_write_c0_config6(val); return; } /* en = 1 to enable * en = 0 to disable */ static __inline__ void nlm_pagewalker_en(int en) { unsigned int val; val = nlm_read_c0_config6(); val |= (en << 3); nlm_write_c0_config6(val); return; } /* en = 1 to enable * en = 0 to disable */ static __inline__ void nlm_extended_tlb_en(int en) { unsigned int val; val = nlm_read_c0_config6(); val |= (en << 2); nlm_write_c0_config6(val); return; } static __inline__ int nlm_get_num_combined_tlbs(void) { return (((nlm_read_c0_config6() >> 16) & 0xffff) + 1); } /* get number of variable TLB entries */ static __inline__ int nlm_get_num_vtlbs(void) { return (((nlm_read_c0_config6() >> 6) & 0x3ff) + 1); } static __inline__ void nlm_setup_extended_pagemask(int mask) { nlm_write_c0_config7(mask); } #endif Index: head/sys/mips/nlm/hal/nae.h =================================================================== --- head/sys/mips/nlm/hal/nae.h (revision 279386) +++ head/sys/mips/nlm/hal/nae.h (revision 279387) @@ -1,656 +1,656 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __NLM_NAE_H__ #define __NLM_NAE_H__ /** * @file_name nae.h * @author Netlogic Microsystems * @brief Basic definitions of XLP Networt Accelerator Engine */ /* NAE specific registers */ #define NAE_REG(blk, intf, reg) (((blk) << 11) | ((intf) << 7) | (reg)) /* ingress path registers */ #define NAE_RX_CONFIG NAE_REG(7, 0, 0x10) #define NAE_RX_IF_BASE_CONFIG0 NAE_REG(7, 0, 0x12) #define NAE_RX_IF_BASE_CONFIG1 NAE_REG(7, 0, 0x13) #define NAE_RX_IF_BASE_CONFIG2 NAE_REG(7, 0, 0x14) #define NAE_RX_IF_BASE_CONFIG3 NAE_REG(7, 0, 0x15) #define NAE_RX_IF_BASE_CONFIG4 NAE_REG(7, 0, 0x16) #define NAE_RX_IF_BASE_CONFIG5 NAE_REG(7, 0, 0x17) #define NAE_RX_IF_BASE_CONFIG6 NAE_REG(7, 0, 0x18) #define NAE_RX_IF_BASE_CONFIG7 NAE_REG(7, 0, 0x19) #define NAE_RX_IF_BASE_CONFIG8 NAE_REG(7, 0, 0x1a) #define NAE_RX_IF_BASE_CONFIG9 NAE_REG(7, 0, 0x1b) #define NAE_RX_IF_VEC_VALID NAE_REG(7, 0, 0x1c) #define NAE_RX_IF_SLOT_CAL NAE_REG(7, 0, 0x1d) #define NAE_PARSER_CONFIG NAE_REG(7, 0, 0x1e) #define NAE_PARSER_SEQ_FIFO_CFG NAE_REG(7, 0, 0x1f) #define NAE_FREE_IN_FIFO_CFG NAE_REG(7, 0, 0x20) #define NAE_RXBUF_BASE_DPTH_ADDR NAE_REG(7, 0, 0x21) #define NAE_RXBUF_BASE_DPTH NAE_REG(7, 0, 0x22) #define NAE_RX_UCORE_CFG NAE_REG(7, 0, 0x23) #define NAE_RX_UCORE_CAM_MASK0 NAE_REG(7, 0, 0x24) #define NAE_RX_UCORE_CAM_MASK1 NAE_REG(7, 0, 0x25) #define NAE_RX_UCORE_CAM_MASK2 NAE_REG(7, 0, 0x26) #define NAE_RX_UCORE_CAM_MASK3 NAE_REG(7, 0, 0x27) #define NAE_FREEIN_FIFO_UNIQ_SZ_CFG NAE_REG(7, 0, 0x28) #define NAE_RX_CRC_POLY0_CFG NAE_REG(7, 0, 0x2a) #define NAE_RX_CRC_POLY1_CFG NAE_REG(7, 0, 0x2b) #define NAE_FREE_SPILL0_MEM_CFG NAE_REG(7, 0, 0x2c) #define NAE_FREE_SPILL1_MEM_CFG NAE_REG(7, 0, 0x2d) #define NAE_FREEFIFO_THRESH_CFG NAE_REG(7, 0, 0x2e) #define NAE_FLOW_CRC16_POLY_CFG NAE_REG(7, 0, 0x2f) #define NAE_EGR_NIOR_CAL_LEN_REG NAE_REG(7, 0, 0x4e) #define NAE_EGR_NIOR_CRDT_CAL_PROG NAE_REG(7, 0, 0x52) #define NAE_TEST NAE_REG(7, 0, 0x5f) #define NAE_BIU_TIMEOUT_CFG NAE_REG(7, 0, 0x60) #define NAE_BIU_CFG NAE_REG(7, 0, 0x61) #define NAE_RX_FREE_FIFO_POP NAE_REG(7, 0, 0x62) #define NAE_RX_DSBL_ECC NAE_REG(7, 0, 0x63) #define NAE_FLOW_BASEMASK_CFG NAE_REG(7, 0, 0x80) #define NAE_POE_CLASS_SETUP_CFG NAE_REG(7, 0, 0x81) #define NAE_UCORE_IFACEMASK_CFG NAE_REG(7, 0, 0x82) #define NAE_RXBUF_XOFFON_THRESH NAE_REG(7, 0, 0x83) #define NAE_FLOW_TABLE1_CFG NAE_REG(7, 0, 0x84) #define NAE_FLOW_TABLE2_CFG NAE_REG(7, 0, 0x85) #define NAE_FLOW_TABLE3_CFG NAE_REG(7, 0, 0x86) #define NAE_RX_FREE_FIFO_THRESH NAE_REG(7, 0, 0x87) #define NAE_RX_PARSER_UNCLA NAE_REG(7, 0, 0x88) #define NAE_RX_BUF_INTR_THRESH NAE_REG(7, 0, 0x89) #define NAE_IFACE_FIFO_CFG NAE_REG(7, 0, 0x8a) #define NAE_PARSER_SEQ_FIFO_THRESH_CFG NAE_REG(7, 0, 0x8b) #define NAE_RX_ERRINJ_CTRL0 NAE_REG(7, 0, 0x8c) #define NAE_RX_ERRINJ_CTRL1 NAE_REG(7, 0, 0x8d) #define NAE_RX_ERR_LATCH0 NAE_REG(7, 0, 0x8e) #define NAE_RX_ERR_LATCH1 NAE_REG(7, 0, 0x8f) #define NAE_RX_PERF_CTR_CFG NAE_REG(7, 0, 0xa0) #define NAE_RX_PERF_CTR_VAL NAE_REG(7, 0, 0xa1) /* NAE hardware parser registers */ #define NAE_L2_TYPE_PORT0 NAE_REG(7, 0, 0x210) #define NAE_L2_TYPE_PORT1 NAE_REG(7, 0, 0x211) #define NAE_L2_TYPE_PORT2 NAE_REG(7, 0, 0x212) #define NAE_L2_TYPE_PORT3 NAE_REG(7, 0, 0x213) #define NAE_L2_TYPE_PORT4 NAE_REG(7, 0, 0x214) #define NAE_L2_TYPE_PORT5 NAE_REG(7, 0, 0x215) #define NAE_L2_TYPE_PORT6 NAE_REG(7, 0, 0x216) #define NAE_L2_TYPE_PORT7 NAE_REG(7, 0, 0x217) #define NAE_L2_TYPE_PORT8 NAE_REG(7, 0, 0x218) #define NAE_L2_TYPE_PORT9 NAE_REG(7, 0, 0x219) #define NAE_L2_TYPE_PORT10 NAE_REG(7, 0, 0x21a) #define NAE_L2_TYPE_PORT11 NAE_REG(7, 0, 0x21b) #define NAE_L2_TYPE_PORT12 NAE_REG(7, 0, 0x21c) #define NAE_L2_TYPE_PORT13 NAE_REG(7, 0, 0x21d) #define NAE_L2_TYPE_PORT14 NAE_REG(7, 0, 0x21e) #define NAE_L2_TYPE_PORT15 NAE_REG(7, 0, 0x21f) #define NAE_L2_TYPE_PORT16 NAE_REG(7, 0, 0x220) #define NAE_L2_TYPE_PORT17 NAE_REG(7, 0, 0x221) #define NAE_L2_TYPE_PORT18 NAE_REG(7, 0, 0x222) #define NAE_L2_TYPE_PORT19 NAE_REG(7, 0, 0x223) #define NAE_L3_CTABLE_MASK0 NAE_REG(7, 0, 0x22c) #define NAE_L3_CTABLE_MASK1 NAE_REG(7, 0, 0x22d) #define NAE_L3_CTABLE_MASK2 NAE_REG(7, 0, 0x22e) #define NAE_L3_CTABLE_MASK3 NAE_REG(7, 0, 0x22f) #define NAE_L3CTABLE0 NAE_REG(7, 0, 0x230) #define NAE_L3CTABLE1 NAE_REG(7, 0, 0x231) #define NAE_L3CTABLE2 NAE_REG(7, 0, 0x232) #define NAE_L3CTABLE3 NAE_REG(7, 0, 0x233) #define NAE_L3CTABLE4 NAE_REG(7, 0, 0x234) #define NAE_L3CTABLE5 NAE_REG(7, 0, 0x235) #define NAE_L3CTABLE6 NAE_REG(7, 0, 0x236) #define NAE_L3CTABLE7 NAE_REG(7, 0, 0x237) #define NAE_L3CTABLE8 NAE_REG(7, 0, 0x238) #define NAE_L3CTABLE9 NAE_REG(7, 0, 0x239) #define NAE_L3CTABLE10 NAE_REG(7, 0, 0x23a) #define NAE_L3CTABLE11 NAE_REG(7, 0, 0x23b) #define NAE_L3CTABLE12 NAE_REG(7, 0, 0x23c) #define NAE_L3CTABLE13 NAE_REG(7, 0, 0x23d) #define NAE_L3CTABLE14 NAE_REG(7, 0, 0x23e) #define NAE_L3CTABLE15 NAE_REG(7, 0, 0x23f) #define NAE_L4CTABLE0 NAE_REG(7, 0, 0x250) #define NAE_L4CTABLE1 NAE_REG(7, 0, 0x251) #define NAE_L4CTABLE2 NAE_REG(7, 0, 0x252) #define NAE_L4CTABLE3 NAE_REG(7, 0, 0x253) #define NAE_L4CTABLE4 NAE_REG(7, 0, 0x254) #define NAE_L4CTABLE5 NAE_REG(7, 0, 0x255) #define NAE_L4CTABLE6 NAE_REG(7, 0, 0x256) #define NAE_L4CTABLE7 NAE_REG(7, 0, 0x257) #define NAE_IPV6_EXT_HEADER0 NAE_REG(7, 0, 0x260) #define NAE_IPV6_EXT_HEADER1 NAE_REG(7, 0, 0x261) #define NAE_VLAN_TYPES01 NAE_REG(7, 0, 0x262) #define NAE_VLAN_TYPES23 NAE_REG(7, 0, 0x263) /* NAE Egress path registers */ #define NAE_TX_CONFIG NAE_REG(7, 0, 0x11) #define NAE_DMA_TX_CREDIT_TH NAE_REG(7, 0, 0x29) #define NAE_STG1_STG2CRDT_CMD NAE_REG(7, 0, 0x30) #define NAE_STG2_EHCRDT_CMD NAE_REG(7, 0, 0x32) #define NAE_EH_FREECRDT_CMD NAE_REG(7, 0, 0x34) #define NAE_STG2_STRCRDT_CMD NAE_REG(7, 0, 0x36) #define NAE_TXFIFO_IFACEMAP_CMD NAE_REG(7, 0, 0x38) #define NAE_VFBID_DESTMAP_CMD NAE_REG(7, 0, 0x3a) #define NAE_STG1_PMEM_PROG NAE_REG(7, 0, 0x3c) #define NAE_STG2_PMEM_PROG NAE_REG(7, 0, 0x3e) #define NAE_EH_PMEM_PROG NAE_REG(7, 0, 0x40) #define NAE_FREE_PMEM_PROG NAE_REG(7, 0, 0x42) #define NAE_TX_DDR_ACTVLIST_CMD NAE_REG(7, 0, 0x44) #define NAE_TX_IF_BURSTMAX_CMD NAE_REG(7, 0, 0x46) #define NAE_TX_IF_ENABLE_CMD NAE_REG(7, 0, 0x48) #define NAE_TX_PKTLEN_PMEM_CMD NAE_REG(7, 0, 0x4a) #define NAE_TX_SCHED_MAP_CMD0 NAE_REG(7, 0, 0x4c) #define NAE_TX_SCHED_MAP_CMD1 NAE_REG(7, 0, 0x4d) #define NAE_TX_PKT_PMEM_CMD0 NAE_REG(7, 0, 0x50) #define NAE_TX_PKT_PMEM_CMD1 NAE_REG(7, 0, 0x51) #define NAE_TX_SCHED_CTRL NAE_REG(7, 0, 0x53) #define NAE_TX_CRC_POLY0 NAE_REG(7, 0, 0x54) #define NAE_TX_CRC_POLY1 NAE_REG(7, 0, 0x55) #define NAE_TX_CRC_POLY2 NAE_REG(7, 0, 0x56) #define NAE_TX_CRC_POLY3 NAE_REG(7, 0, 0x57) #define NAE_STR_PMEM_CMD NAE_REG(7, 0, 0x58) #define NAE_TX_IORCRDT_INIT NAE_REG(7, 0, 0x59) #define NAE_TX_DSBL_ECC NAE_REG(7, 0, 0x5a) #define NAE_TX_IORCRDT_IGNORE NAE_REG(7, 0, 0x5b) #define NAE_IF0_1588_TMSTMP_HI NAE_REG(7, 0, 0x300) #define NAE_IF1_1588_TMSTMP_HI NAE_REG(7, 0, 0x302) #define NAE_IF2_1588_TMSTMP_HI NAE_REG(7, 0, 0x304) #define NAE_IF3_1588_TMSTMP_HI NAE_REG(7, 0, 0x306) #define NAE_IF4_1588_TMSTMP_HI NAE_REG(7, 0, 0x308) #define NAE_IF5_1588_TMSTMP_HI NAE_REG(7, 0, 0x30a) #define NAE_IF6_1588_TMSTMP_HI NAE_REG(7, 0, 0x30c) #define NAE_IF7_1588_TMSTMP_HI NAE_REG(7, 0, 0x30e) #define NAE_IF8_1588_TMSTMP_HI NAE_REG(7, 0, 0x310) #define NAE_IF9_1588_TMSTMP_HI NAE_REG(7, 0, 0x312) #define NAE_IF10_1588_TMSTMP_HI NAE_REG(7, 0, 0x314) #define NAE_IF11_1588_TMSTMP_HI NAE_REG(7, 0, 0x316) #define NAE_IF12_1588_TMSTMP_HI NAE_REG(7, 0, 0x318) #define NAE_IF13_1588_TMSTMP_HI NAE_REG(7, 0, 0x31a) #define NAE_IF14_1588_TMSTMP_HI NAE_REG(7, 0, 0x31c) #define NAE_IF15_1588_TMSTMP_HI NAE_REG(7, 0, 0x31e) #define NAE_IF16_1588_TMSTMP_HI NAE_REG(7, 0, 0x320) #define NAE_IF17_1588_TMSTMP_HI NAE_REG(7, 0, 0x322) #define NAE_IF18_1588_TMSTMP_HI NAE_REG(7, 0, 0x324) #define NAE_IF19_1588_TMSTMP_HI NAE_REG(7, 0, 0x326) #define NAE_IF0_1588_TMSTMP_LO NAE_REG(7, 0, 0x301) #define NAE_IF1_1588_TMSTMP_LO NAE_REG(7, 0, 0x303) #define NAE_IF2_1588_TMSTMP_LO NAE_REG(7, 0, 0x305) #define NAE_IF3_1588_TMSTMP_LO NAE_REG(7, 0, 0x307) #define NAE_IF4_1588_TMSTMP_LO NAE_REG(7, 0, 0x309) #define NAE_IF5_1588_TMSTMP_LO NAE_REG(7, 0, 0x30b) #define NAE_IF6_1588_TMSTMP_LO NAE_REG(7, 0, 0x30d) #define NAE_IF7_1588_TMSTMP_LO NAE_REG(7, 0, 0x30f) #define NAE_IF8_1588_TMSTMP_LO NAE_REG(7, 0, 0x311) #define NAE_IF9_1588_TMSTMP_LO NAE_REG(7, 0, 0x313) #define NAE_IF10_1588_TMSTMP_LO NAE_REG(7, 0, 0x315) #define NAE_IF11_1588_TMSTMP_LO NAE_REG(7, 0, 0x317) #define NAE_IF12_1588_TMSTMP_LO NAE_REG(7, 0, 0x319) #define NAE_IF13_1588_TMSTMP_LO NAE_REG(7, 0, 0x31b) #define NAE_IF14_1588_TMSTMP_LO NAE_REG(7, 0, 0x31d) #define NAE_IF15_1588_TMSTMP_LO NAE_REG(7, 0, 0x31f) #define NAE_IF16_1588_TMSTMP_LO NAE_REG(7, 0, 0x321) #define NAE_IF17_1588_TMSTMP_LO NAE_REG(7, 0, 0x323) #define NAE_IF18_1588_TMSTMP_LO NAE_REG(7, 0, 0x325) #define NAE_IF19_1588_TMSTMP_LO NAE_REG(7, 0, 0x327) #define NAE_TX_EL0 NAE_REG(7, 0, 0x328) #define NAE_TX_EL1 NAE_REG(7, 0, 0x329) #define NAE_EIC0 NAE_REG(7, 0, 0x32a) #define NAE_EIC1 NAE_REG(7, 0, 0x32b) #define NAE_STG1_STG2CRDT_STATUS NAE_REG(7, 0, 0x32c) #define NAE_STG2_EHCRDT_STATUS NAE_REG(7, 0, 0x32d) #define NAE_STG2_FREECRDT_STATUS NAE_REG(7, 0, 0x32e) #define NAE_STG2_STRCRDT_STATUS NAE_REG(7, 0, 0x32f) #define NAE_TX_PERF_CNTR_INTR_STATUS NAE_REG(7, 0, 0x330) #define NAE_TX_PERF_CNTR_ROLL_STATUS NAE_REG(7, 0, 0x331) #define NAE_TX_PERF_CNTR0 NAE_REG(7, 0, 0x332) #define NAE_TX_PERF_CNTR1 NAE_REG(7, 0, 0x334) #define NAE_TX_PERF_CNTR2 NAE_REG(7, 0, 0x336) #define NAE_TX_PERF_CNTR3 NAE_REG(7, 0, 0x338) #define NAE_TX_PERF_CNTR4 NAE_REG(7, 0, 0x33a) #define NAE_TX_PERF_CNTR0_CTL NAE_REG(7, 0, 0x333) #define NAE_TX_PERF_CNTR1_CTL NAE_REG(7, 0, 0x335) #define NAE_TX_PERF_CNTR2_CTL NAE_REG(7, 0, 0x337) #define NAE_TX_PERF_CNTR3_CTL NAE_REG(7, 0, 0x339) #define NAE_TX_PERF_CNTR4_CTL NAE_REG(7, 0, 0x33b) #define NAE_VFBID_DESTMAP_STATUS NAE_REG(7, 0, 0x380) #define NAE_STG2_PMEM_STATUS NAE_REG(7, 0, 0x381) #define NAE_EH_PMEM_STATUS NAE_REG(7, 0, 0x382) #define NAE_FREE_PMEM_STATUS NAE_REG(7, 0, 0x383) #define NAE_TX_DDR_ACTVLIST_STATUS NAE_REG(7, 0, 0x384) #define NAE_TX_IF_BURSTMAX_STATUS NAE_REG(7, 0, 0x385) #define NAE_TX_PKTLEN_PMEM_STATUS NAE_REG(7, 0, 0x386) #define NAE_TX_SCHED_MAP_STATUS0 NAE_REG(7, 0, 0x387) #define NAE_TX_SCHED_MAP_STATUS1 NAE_REG(7, 0, 0x388) #define NAE_TX_PKT_PMEM_STATUS NAE_REG(7, 0, 0x389) #define NAE_STR_PMEM_STATUS NAE_REG(7, 0, 0x38a) /* Network interface interrupt registers */ #define NAE_NET_IF0_INTR_STAT NAE_REG(7, 0, 0x280) #define NAE_NET_IF1_INTR_STAT NAE_REG(7, 0, 0x282) #define NAE_NET_IF2_INTR_STAT NAE_REG(7, 0, 0x284) #define NAE_NET_IF3_INTR_STAT NAE_REG(7, 0, 0x286) #define NAE_NET_IF4_INTR_STAT NAE_REG(7, 0, 0x288) #define NAE_NET_IF5_INTR_STAT NAE_REG(7, 0, 0x28a) #define NAE_NET_IF6_INTR_STAT NAE_REG(7, 0, 0x28c) #define NAE_NET_IF7_INTR_STAT NAE_REG(7, 0, 0x28e) #define NAE_NET_IF8_INTR_STAT NAE_REG(7, 0, 0x290) #define NAE_NET_IF9_INTR_STAT NAE_REG(7, 0, 0x292) #define NAE_NET_IF10_INTR_STAT NAE_REG(7, 0, 0x294) #define NAE_NET_IF11_INTR_STAT NAE_REG(7, 0, 0x296) #define NAE_NET_IF12_INTR_STAT NAE_REG(7, 0, 0x298) #define NAE_NET_IF13_INTR_STAT NAE_REG(7, 0, 0x29a) #define NAE_NET_IF14_INTR_STAT NAE_REG(7, 0, 0x29c) #define NAE_NET_IF15_INTR_STAT NAE_REG(7, 0, 0x29e) #define NAE_NET_IF16_INTR_STAT NAE_REG(7, 0, 0x2a0) #define NAE_NET_IF17_INTR_STAT NAE_REG(7, 0, 0x2a2) #define NAE_NET_IF18_INTR_STAT NAE_REG(7, 0, 0x2a4) #define NAE_NET_IF19_INTR_STAT NAE_REG(7, 0, 0x2a6) #define NAE_NET_IF0_INTR_MASK NAE_REG(7, 0, 0x281) #define NAE_NET_IF1_INTR_MASK NAE_REG(7, 0, 0x283) #define NAE_NET_IF2_INTR_MASK NAE_REG(7, 0, 0x285) #define NAE_NET_IF3_INTR_MASK NAE_REG(7, 0, 0x287) #define NAE_NET_IF4_INTR_MASK NAE_REG(7, 0, 0x289) #define NAE_NET_IF5_INTR_MASK NAE_REG(7, 0, 0x28b) #define NAE_NET_IF6_INTR_MASK NAE_REG(7, 0, 0x28d) #define NAE_NET_IF7_INTR_MASK NAE_REG(7, 0, 0x28f) #define NAE_NET_IF8_INTR_MASK NAE_REG(7, 0, 0x291) #define NAE_NET_IF9_INTR_MASK NAE_REG(7, 0, 0x293) #define NAE_NET_IF10_INTR_MASK NAE_REG(7, 0, 0x295) #define NAE_NET_IF11_INTR_MASK NAE_REG(7, 0, 0x297) #define NAE_NET_IF12_INTR_MASK NAE_REG(7, 0, 0x299) #define NAE_NET_IF13_INTR_MASK NAE_REG(7, 0, 0x29b) #define NAE_NET_IF14_INTR_MASK NAE_REG(7, 0, 0x29d) #define NAE_NET_IF15_INTR_MASK NAE_REG(7, 0, 0x29f) #define NAE_NET_IF16_INTR_MASK NAE_REG(7, 0, 0x2a1) #define NAE_NET_IF17_INTR_MASK NAE_REG(7, 0, 0x2a3) #define NAE_NET_IF18_INTR_MASK NAE_REG(7, 0, 0x2a5) #define NAE_NET_IF19_INTR_MASK NAE_REG(7, 0, 0x2a7) #define NAE_COMMON0_INTR_STAT NAE_REG(7, 0, 0x2a8) #define NAE_COMMON0_INTR_MASK NAE_REG(7, 0, 0x2a9) #define NAE_COMMON1_INTR_STAT NAE_REG(7, 0, 0x2aa) #define NAE_COMMON1_INTR_MASK NAE_REG(7, 0, 0x2ab) /* Network Interface Low-block Registers */ #define NAE_PHY_LANE0_STATUS(block) NAE_REG(block, 0xe, 0) #define NAE_PHY_LANE1_STATUS(block) NAE_REG(block, 0xe, 1) #define NAE_PHY_LANE2_STATUS(block) NAE_REG(block, 0xe, 2) #define NAE_PHY_LANE3_STATUS(block) NAE_REG(block, 0xe, 3) #define NAE_PHY_LANE0_CTRL(block) NAE_REG(block, 0xe, 4) #define NAE_PHY_LANE1_CTRL(block) NAE_REG(block, 0xe, 5) #define NAE_PHY_LANE2_CTRL(block) NAE_REG(block, 0xe, 6) #define NAE_PHY_LANE3_CTRL(block) NAE_REG(block, 0xe, 7) /* Network interface Top-block registers */ #define NAE_LANE_CFG_CPLX_0_1 NAE_REG(7, 0, 0x780) #define NAE_LANE_CFG_CPLX_2_3 NAE_REG(7, 0, 0x781) #define NAE_LANE_CFG_CPLX_4 NAE_REG(7, 0, 0x782) #define NAE_LANE_CFG_SOFTRESET NAE_REG(7, 0, 0x783) #define NAE_1588_PTP_OFFSET_HI NAE_REG(7, 0, 0x784) #define NAE_1588_PTP_OFFSET_LO NAE_REG(7, 0, 0x785) #define NAE_1588_PTP_INC_DEN NAE_REG(7, 0, 0x786) #define NAE_1588_PTP_INC_NUM NAE_REG(7, 0, 0x787) #define NAE_1588_PTP_INC_INTG NAE_REG(7, 0, 0x788) #define NAE_1588_PTP_CONTROL NAE_REG(7, 0, 0x789) #define NAE_1588_PTP_STATUS NAE_REG(7, 0, 0x78a) #define NAE_1588_PTP_USER_VALUE_HI NAE_REG(7, 0, 0x78b) #define NAE_1588_PTP_USER_VALUE_LO NAE_REG(7, 0, 0x78c) #define NAE_1588_PTP_TMR1_HI NAE_REG(7, 0, 0x78d) #define NAE_1588_PTP_TMR1_LO NAE_REG(7, 0, 0x78e) #define NAE_1588_PTP_TMR2_HI NAE_REG(7, 0, 0x78f) #define NAE_1588_PTP_TMR2_LO NAE_REG(7, 0, 0x790) #define NAE_1588_PTP_TMR3_HI NAE_REG(7, 0, 0x791) #define NAE_1588_PTP_TMR3_LO NAE_REG(7, 0, 0x792) #define NAE_TX_FC_CAL_IDX_TBL_CTRL NAE_REG(7, 0, 0x793) #define NAE_TX_FC_CAL_TBL_CTRL NAE_REG(7, 0, 0x794) #define NAE_TX_FC_CAL_TBL_DATA0 NAE_REG(7, 0, 0x795) #define NAE_TX_FC_CAL_TBL_DATA1 NAE_REG(7, 0, 0x796) #define NAE_TX_FC_CAL_TBL_DATA2 NAE_REG(7, 0, 0x797) #define NAE_TX_FC_CAL_TBL_DATA3 NAE_REG(7, 0, 0x798) #define NAE_INT_MDIO_CTRL NAE_REG(7, 0, 0x799) #define NAE_INT_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79a) #define NAE_INT_MDIO_RD_STAT NAE_REG(7, 0, 0x79b) #define NAE_INT_MDIO_LINK_STAT NAE_REG(7, 0, 0x79c) #define NAE_EXT_G0_MDIO_CTRL NAE_REG(7, 0, 0x79d) #define NAE_EXT_G1_MDIO_CTRL NAE_REG(7, 0, 0x7a1) #define NAE_EXT_G0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x79e) #define NAE_EXT_G1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a2) #define NAE_EXT_G0_MDIO_RD_STAT NAE_REG(7, 0, 0x79f) #define NAE_EXT_G1_MDIO_RD_STAT NAE_REG(7, 0, 0x7a3) #define NAE_EXT_G0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a0) #define NAE_EXT_G1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a4) #define NAE_EXT_XG0_MDIO_CTRL NAE_REG(7, 0, 0x7a5) #define NAE_EXT_XG1_MDIO_CTRL NAE_REG(7, 0, 0x7a9) #define NAE_EXT_XG0_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7a6) #define NAE_EXT_XG1_MDIO_CTRL_DATA NAE_REG(7, 0, 0x7aa) #define NAE_EXT_XG0_MDIO_RD_STAT NAE_REG(7, 0, 0x7a7) #define NAE_EXT_XG1_MDIO_RD_STAT NAE_REG(7, 0, 0x7ab) #define NAE_EXT_XG0_MDIO_LINK_STAT NAE_REG(7, 0, 0x7a8) #define NAE_EXT_XG1_MDIO_LINK_STAT NAE_REG(7, 0, 0x7ac) #define NAE_GMAC_FC_SLOT0 NAE_REG(7, 0, 0x7ad) #define NAE_GMAC_FC_SLOT1 NAE_REG(7, 0, 0x7ae) #define NAE_GMAC_FC_SLOT2 NAE_REG(7, 0, 0x7af) #define NAE_GMAC_FC_SLOT3 NAE_REG(7, 0, 0x7b0) #define NAE_NETIOR_NTB_SLOT NAE_REG(7, 0, 0x7b1) #define NAE_NETIOR_MISC_CTRL0 NAE_REG(7, 0, 0x7b2) #define NAE_NETIOR_INT0 NAE_REG(7, 0, 0x7b3) #define NAE_NETIOR_INT0_MASK NAE_REG(7, 0, 0x7b4) #define NAE_NETIOR_INT1 NAE_REG(7, 0, 0x7b5) #define NAE_NETIOR_INT1_MASK NAE_REG(7, 0, 0x7b6) #define NAE_GMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b7) #define NAE_XGMAC_PFC_REPEAT NAE_REG(7, 0, 0x7b8) #define NAE_NETIOR_MISC_CTRL1 NAE_REG(7, 0, 0x7b9) #define NAE_NETIOR_MISC_CTRL2 NAE_REG(7, 0, 0x7ba) #define NAE_NETIOR_INT2 NAE_REG(7, 0, 0x7bb) #define NAE_NETIOR_INT2_MASK NAE_REG(7, 0, 0x7bc) #define NAE_NETIOR_MISC_CTRL3 NAE_REG(7, 0, 0x7bd) /* Network interface lane configuration registers */ #define NAE_LANE_CFG_MISCREG1 NAE_REG(7, 0xf, 0x39) #define NAE_LANE_CFG_MISCREG2 NAE_REG(7, 0xf, 0x3A) /* Network interface soft reset register */ #define NAE_SOFT_RESET NAE_REG(7, 0xf, 3) /* ucore instruction/shared CAM RAM access */ #define NAE_UCORE_SHARED_RAM_OFFSET 0x10000 #define PORTS_PER_CMPLX 4 #define NAE_CACHELINE_SIZE 64 #define PHY_LANE_0_CTRL 4 #define PHY_LANE_1_CTRL 5 #define PHY_LANE_2_CTRL 6 #define PHY_LANE_3_CTRL 7 #define PHY_LANE_STAT_SRCS 0x00000001 #define PHY_LANE_STAT_STD 0x00000010 #define PHY_LANE_STAT_SFEA 0x00000020 #define PHY_LANE_STAT_STCS 0x00000040 #define PHY_LANE_STAT_SPC 0x00000200 #define PHY_LANE_STAT_XLF 0x00000400 #define PHY_LANE_STAT_PCR 0x00000800 #define PHY_LANE_CTRL_DATA_POS 0 #define PHY_LANE_CTRL_ADDR_POS 8 #define PHY_LANE_CTRL_CMD_READ 0x00010000 #define PHY_LANE_CTRL_CMD_WRITE 0x00000000 #define PHY_LANE_CTRL_CMD_START 0x00020000 #define PHY_LANE_CTRL_CMD_PENDING 0x00040000 #define PHY_LANE_CTRL_ALL 0x00200000 #define PHY_LANE_CTRL_FAST_INIT 0x00400000 #define PHY_LANE_CTRL_REXSEL_POS 23 #define PHY_LANE_CTRL_PHYMODE_POS 25 #define PHY_LANE_CTRL_PWRDOWN 0x20000000 #define PHY_LANE_CTRL_RST 0x40000000 #define PHY_LANE_CTRL_RST_XAUI 0xc0000000 #define PHY_LANE_CTRL_BPC_XAUI 0x80000000 #define LANE_CFG_CPLX_0_1 0x0 #define LANE_CFG_CPLX_2_3 0x1 #define LANE_CFG_CPLX_4 0x2 #define MAC_CONF1 0x0 #define MAC_CONF2 0x1 #define MAX_FRM 0x4 #define NETIOR_GMAC_CTRL1 0x7F #define NETIOR_GMAC_CTRL2 0x7E #define NETIOR_GMAC_CTRL3 0x7C #define SGMII_CAL_SLOTS 3 #define XAUI_CAL_SLOTS 13 #define IL8_CAL_SLOTS 26 #define IL4_CAL_SLOTS 10 #define NAE_DRR_QUANTA 2048 #define XLP3XX_STG2_FIFO_SZ 512 #define XLP3XX_EH_FIFO_SZ 512 #define XLP3XX_FROUT_FIFO_SZ 512 #define XLP3XX_MS_FIFO_SZ 512 #define XLP3XX_PKT_FIFO_SZ 8192 #define XLP3XX_PKTLEN_FIFO_SZ 512 #define XLP3XX_MAX_STG2_OFFSET 0x7F #define XLP3XX_MAX_EH_OFFSET 0x1f #define XLP3XX_MAX_FREE_OUT_OFFSET 0x1f #define XLP3XX_MAX_MS_OFFSET 0xF #define XLP3XX_MAX_PMEM_OFFSET 0x7FE #define XLP3XX_STG1_2_CREDIT XLP3XX_STG2_FIFO_SZ #define XLP3XX_STG2_EH_CREDIT XLP3XX_EH_FIFO_SZ #define XLP3XX_STG2_FROUT_CREDIT XLP3XX_FROUT_FIFO_SZ #define XLP3XX_STG2_MS_CREDIT XLP3XX_MS_FIFO_SZ #define XLP8XX_STG2_FIFO_SZ 2048 #define XLP8XX_EH_FIFO_SZ 4096 #define XLP8XX_FROUT_FIFO_SZ 4096 #define XLP8XX_MS_FIFO_SZ 2048 #define XLP8XX_PKT_FIFO_SZ 16384 #define XLP8XX_PKTLEN_FIFO_SZ 2048 - + #define XLP8XX_MAX_STG2_OFFSET 0x7F #define XLP8XX_MAX_EH_OFFSET 0x7F #define XLP8XX_MAX_FREE_OUT_OFFSET 0x7F #define XLP8XX_MAX_MS_OFFSET 0x1F #define XLP8XX_MAX_PMEM_OFFSET 0x7FE #define XLP8XX_STG1_2_CREDIT XLP8XX_STG2_FIFO_SZ #define XLP8XX_STG2_EH_CREDIT XLP8XX_EH_FIFO_SZ #define XLP8XX_STG2_FROUT_CREDIT XLP8XX_FROUT_FIFO_SZ #define XLP8XX_STG2_MS_CREDIT XLP8XX_MS_FIFO_SZ #define MAX_CAL_SLOTS 64 #define XLP_MAX_PORTS 18 #define XLP_STORM_MAX_PORTS 8 #define MAX_FREE_FIFO_POOL_8XX 20 #define MAX_FREE_FIFO_POOL_3XX 9 #if !defined(LOCORE) && !defined(__ASSEMBLY__) #define nlm_read_nae_reg(b, r) nlm_read_reg_xkphys(b, r) #define nlm_write_nae_reg(b, r, v) nlm_write_reg_xkphys(b, r, v) #define nlm_get_nae_pcibase(node) \ nlm_pcicfg_base(XLP_IO_NAE_OFFSET(node)) #define nlm_get_nae_regbase(node) \ nlm_xkphys_map_pcibar0(nlm_get_nae_pcibase(node)) #define MAX_POE_CLASSES 8 #define MAX_POE_CLASS_CTXT_TBL_SZ ((NUM_CONTEXTS / MAX_POE_CLASSES) + 1) #define TXINITIORCR(x) (((x) & 0x7ffff) << 8) enum XLPNAE_TX_TYPE { P2D_NEOP = 0, P2P, P2D_EOP, MSC }; enum nblock_type { UNKNOWN = 0, /* DONT MAKE IT NON-ZERO */ SGMIIC = 1, XAUIC = 2, ILC = 3 }; enum nae_interface_type { GMAC_0 = 0, GMAC_1, GMAC_2, GMAC_3, XGMAC, INTERLAKEN, PHY = 0xE, LANE_CFG = 0xF, }; enum { LM_UNCONNECTED = 0, LM_SGMII = 1, LM_XAUI = 2, LM_IL = 3, }; enum nae_block { BLOCK_0 = 0, BLOCK_1, BLOCK_2, BLOCK_3, BLOCK_4, BLOCK_5, BLOCK_6, BLOCK_7, }; enum { PHYMODE_NONE = 0, PHYMODE_HS_SGMII = 1, PHYMODE_XAUI = 1, PHYMODE_SGMII = 2, PHYMODE_IL = 3, }; static __inline int nae_num_complex(uint64_t nae_pcibase) { return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG0) & 0xff); } static __inline int nae_num_context(uint64_t nae_pcibase) { return (nlm_read_reg(nae_pcibase, XLP_PCI_DEVINFO_REG5)); } /* per port config structure */ struct nae_port_config { int node; /* node id (quickread) */ int block; /* network block id (quickread) */ int port; /* port id - among the 18 in XLP */ int type; /* port type - see xlp_gmac_port_types */ int mdio_bus; int phy_addr; int num_channels; int num_free_descs; int free_desc_sizes; int ucore_mask; int loopback_mode; /* is complex is in loopback? */ uint32_t freein_spill_size; /* Freein spill size for each port */ uint32_t free_fifo_size; /* (512entries x 2desc/entry)1024desc */ uint32_t iface_fifo_size;/* 256 entries x 64B/entry = 16KB */ uint32_t pseq_fifo_size; /* 1024 entries - 1 pktlen/entry */ uint32_t rxbuf_size; /* 4096 entries x 64B = 256KB */ uint32_t rx_if_base_config; uint32_t rx_slots_reqd; uint32_t tx_slots_reqd; uint32_t stg2_fifo_size; uint32_t eh_fifo_size; uint32_t frout_fifo_size; uint32_t ms_fifo_size; uint32_t pkt_fifo_size; uint32_t pktlen_fifo_size; uint32_t max_stg2_offset; uint32_t max_eh_offset; uint32_t max_frout_offset; uint32_t max_ms_offset; uint32_t max_pmem_offset; uint32_t stg1_2_credit; uint32_t stg2_eh_credit; uint32_t stg2_frout_credit; uint32_t stg2_ms_credit; uint32_t vlan_pri_en; uint32_t txq; uint32_t rxfreeq; uint32_t ieee1588_inc_intg; uint32_t ieee1588_inc_den; uint32_t ieee1588_inc_num; uint64_t ieee1588_userval; uint64_t ieee1588_ptpoff; uint64_t ieee1588_tmr1; uint64_t ieee1588_tmr2; uint64_t ieee1588_tmr3; }; void nlm_nae_flush_free_fifo(uint64_t nae_base, int nblocks); void nlm_program_nae_parser_seq_fifo(uint64_t, int, struct nae_port_config *); void nlm_setup_rx_cal_cfg(uint64_t, int, struct nae_port_config *); void nlm_setup_tx_cal_cfg(uint64_t, int, struct nae_port_config *cfg); void nlm_deflate_frin_fifo_carving(uint64_t, int); void nlm_reset_nae(int); int nlm_set_nae_frequency(int, int); void nlm_setup_poe_class_config(uint64_t nae_base, int max_poe_classes, int num_contexts, int *poe_cl_tbl); void nlm_setup_vfbid_mapping(uint64_t); void nlm_setup_flow_crc_poly(uint64_t, uint32_t); void nlm_setup_iface_fifo_cfg(uint64_t, int, struct nae_port_config *); void nlm_setup_rx_base_config(uint64_t, int, struct nae_port_config *); void nlm_setup_rx_buf_config(uint64_t, int, struct nae_port_config *); void nlm_setup_freein_fifo_cfg(uint64_t, struct nae_port_config *); int nlm_get_flow_mask(int); void nlm_program_flow_cfg(uint64_t, int, uint32_t, uint32_t); void xlp_ax_nae_lane_reset_txpll(uint64_t, int, int, int); void xlp_nae_lane_reset_txpll(uint64_t, int, int, int); void xlp_nae_config_lane_gmac(uint64_t, int); void config_egress_fifo_carvings(uint64_t, int, int, int, int, struct nae_port_config *); void config_egress_fifo_credits(uint64_t, int, int, int, int, struct nae_port_config *); void nlm_config_freein_fifo_uniq_cfg(uint64_t, int, int); void nlm_config_ucore_iface_mask_cfg(uint64_t, int, int); int nlm_nae_init_netior(uint64_t nae_base, int nblocks); void nlm_nae_init_ingress(uint64_t, uint32_t); void nlm_nae_init_egress(uint64_t); uint32_t ucore_spray_config(uint32_t, uint32_t, int); void nlm_nae_init_ucore(uint64_t nae_base, int if_num, uint32_t ucore_mask); int nlm_nae_open_if(uint64_t, int, int, int, uint32_t); void nlm_mac_enable(uint64_t, int, int, int); void nlm_mac_disable(uint64_t, int, int, int); uint64_t nae_tx_desc(u_int, u_int, u_int, u_int, uint64_t); void nlm_setup_l2type(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); void nlm_setup_l3ctable_mask(uint64_t, int, uint32_t, uint32_t); void nlm_setup_l3ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); void nlm_setup_l3ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); void nlm_setup_l4ctable_even(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); void nlm_setup_l4ctable_odd(uint64_t, int, uint32_t, uint32_t, uint32_t, uint32_t); void nlm_enable_hardware_parser(uint64_t); void nlm_enable_hardware_parser_per_port(uint64_t, int, int); void nlm_prepad_enable(uint64_t, int); void nlm_setup_1588_timer(uint64_t, struct nae_port_config *); #endif /* !(LOCORE) && !(__ASSEMBLY__) */ #endif Index: head/sys/mips/nlm/hal/nlm_hal.c =================================================================== --- head/sys/mips/nlm/hal/nlm_hal.c (revision 279386) +++ head/sys/mips/nlm/hal/nlm_hal.c (revision 279387) @@ -1,112 +1,112 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include uint32_t xlp_get_cpu_frequency(int node, int core) { uint64_t sysbase = nlm_get_sys_regbase(node); unsigned int pll_divf, pll_divr, dfs_div, ext_div; unsigned int rstval, dfsval; rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE); pll_divf = ((rstval >> 10) & 0x7f) + 1; pll_divr = ((rstval >> 8) & 0x3) + 1; if (!nlm_is_xlp8xx_ax()) ext_div = ((rstval >> 30) & 0x3) + 1; else ext_div = 1; dfs_div = ((dfsval >> (core << 2)) & 0xf) + 1; return ((800000000ULL * pll_divf)/(3 * pll_divr * ext_div * dfs_div)); } static u_int nlm_get_device_frequency(uint64_t sysbase, int devtype) { uint32_t pllctrl, dfsdiv, spf, spr, div_val; int extra_div; pllctrl = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL); if (devtype <= 7) div_val = nlm_read_sys_reg(sysbase, SYS_DFS_DIV_VALUE0); else { devtype -= 8; div_val = nlm_read_sys_reg(sysbase, SYS_DFS_DIV_VALUE1); } dfsdiv = ((div_val >> (devtype << 2)) & 0xf) + 1; spf = (pllctrl >> 3 & 0x7f) + 1; spr = (pllctrl >> 1 & 0x03) + 1; if (devtype == DFS_DEVICE_NAE && !nlm_is_xlp8xx_ax()) extra_div = 2; else extra_div = 1; return ((400 * spf) / (3 * extra_div * spr * dfsdiv)); } int nlm_set_device_frequency(int node, int devtype, int frequency) { uint64_t sysbase; u_int cur_freq; int dec_div; sysbase = nlm_get_sys_regbase(node); cur_freq = nlm_get_device_frequency(sysbase, devtype); if (cur_freq < (frequency - 5)) dec_div = 1; else dec_div = 0; for(;;) { if ((cur_freq >= (frequency - 5)) && (cur_freq <= frequency)) break; if (dec_div) nlm_write_sys_reg(sysbase, SYS_DFS_DIV_DEC_CTRL, (1 << devtype)); else nlm_write_sys_reg(sysbase, SYS_DFS_DIV_INC_CTRL, (1 << devtype)); cur_freq = nlm_get_device_frequency(sysbase, devtype); } return (nlm_get_device_frequency(sysbase, devtype)); } Index: head/sys/mips/nlm/hal/nlmsaelib.h =================================================================== --- head/sys/mips/nlm/hal/nlmsaelib.h (revision 279386) +++ head/sys/mips/nlm/hal/nlmsaelib.h (revision 279387) @@ -1,607 +1,605 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _NLM_HAL_CRYPTO_H_ #define _NLM_HAL_CRYPTO_H_ #define SAE_CFG_REG 0x00 #define SAE_ENG_SEL_0 0x01 #define SAE_ENG_SEL_1 0x02 #define SAE_ENG_SEL_2 0x03 #define SAE_ENG_SEL_3 0x04 #define SAE_ENG_SEL_4 0x05 #define SAE_ENG_SEL_5 0x06 #define SAE_ENG_SEL_6 0x07 #define SAE_ENG_SEL_7 0x08 #define RSA_CFG_REG 0x00 #define RSA_ENG_SEL_0 0x01 #define RSA_ENG_SEL_1 0x02 #define RSA_ENG_SEL_2 0x03 #define nlm_read_sec_reg(b, r) nlm_read_reg(b, r) #define nlm_write_sec_reg(b, r, v) nlm_write_reg(b, r, v) #define nlm_get_sec_pcibase(node) nlm_pcicfg_base(XLP_IO_SEC_OFFSET(node)) #define nlm_get_sec_regbase(node) \ (nlm_get_sec_pcibase(node) + XLP_IO_PCI_HDRSZ) #define nlm_read_rsa_reg(b, r) nlm_read_reg(b, r) #define nlm_write_rsa_reg(b, r, v) nlm_write_reg(b, r, v) #define nlm_get_rsa_pcibase(node) nlm_pcicfg_base(XLP_IO_RSA_OFFSET(node)) #define nlm_get_rsa_regbase(node) \ (nlm_get_rsa_pcibase(node) + XLP_IO_PCI_HDRSZ) #define nlm_pcibase_sec(node) nlm_pcicfg_base(XLP_IO_SEC_OFFSET(node)) #define nlm_qidstart_sec(node) nlm_qidstart_kseg(nlm_pcibase_sec(node)) #define nlm_qnum_sec(node) nlm_qnum_kseg(nlm_pcibase_sec(node)) /* * Since buffer allocation for crypto at kernel is done as malloc, each * segment size is given as page size which is 4K by default */ -#define NLM_CRYPTO_MAX_SEG_LEN PAGE_SIZE +#define NLM_CRYPTO_MAX_SEG_LEN PAGE_SIZE #define MAX_KEY_LEN_IN_DW 20 #define left_shift64(x, bitshift, numofbits) \ ((uint64_t)(x) << (bitshift)) #define left_shift64_mask(x, bitshift, numofbits) \ (((uint64_t)(x) & ((1ULL << (numofbits)) - 1)) << (bitshift)) /** * @brief cipher algorithms * @ingroup crypto */ enum nlm_cipher_algo { NLM_CIPHER_BYPASS = 0, NLM_CIPHER_DES = 1, - NLM_CIPHER_3DES = 2, + NLM_CIPHER_3DES = 2, NLM_CIPHER_AES128 = 3, NLM_CIPHER_AES192 = 4, - NLM_CIPHER_AES256 = 5, - NLM_CIPHER_ARC4 = 6, + NLM_CIPHER_AES256 = 5, + NLM_CIPHER_ARC4 = 6, NLM_CIPHER_KASUMI_F8 = 7, - NLM_CIPHER_SNOW3G_F8 = 8, - NLM_CIPHER_CAMELLIA128 = 9, - NLM_CIPHER_CAMELLIA192 = 0xA, - NLM_CIPHER_CAMELLIA256 = 0xB, + NLM_CIPHER_SNOW3G_F8 = 8, + NLM_CIPHER_CAMELLIA128 = 9, + NLM_CIPHER_CAMELLIA192 = 0xA, + NLM_CIPHER_CAMELLIA256 = 0xB, NLM_CIPHER_MAX = 0xC, }; /** * @brief cipher modes * @ingroup crypto */ enum nlm_cipher_mode { NLM_CIPHER_MODE_ECB = 0, NLM_CIPHER_MODE_CBC = 1, NLM_CIPHER_MODE_CFB = 2, NLM_CIPHER_MODE_OFB = 3, NLM_CIPHER_MODE_CTR = 4, NLM_CIPHER_MODE_AES_F8 = 5, NLM_CIPHER_MODE_GCM = 6, NLM_CIPHER_MODE_CCM = 7, NLM_CIPHER_MODE_UNDEFINED1 = 8, NLM_CIPHER_MODE_UNDEFINED2 = 9, NLM_CIPHER_MODE_LRW = 0xA, NLM_CIPHER_MODE_XTS = 0xB, NLM_CIPHER_MODE_MAX = 0xC, }; /** * @brief hash algorithms * @ingroup crypto */ enum nlm_hash_algo { NLM_HASH_BYPASS = 0, NLM_HASH_MD5 = 1, NLM_HASH_SHA = 2, NLM_HASH_UNDEFINED = 3, NLM_HASH_AES128 = 4, NLM_HASH_AES192 = 5, NLM_HASH_AES256 = 6, NLM_HASH_KASUMI_F9 = 7, NLM_HASH_SNOW3G_F9 = 8, NLM_HASH_CAMELLIA128 = 9, NLM_HASH_CAMELLIA192 = 0xA, NLM_HASH_CAMELLIA256 = 0xB, NLM_HASH_GHASH = 0xC, NLM_HASH_MAX = 0xD }; /** * @brief hash modes * @ingroup crypto */ enum nlm_hash_mode { NLM_HASH_MODE_SHA1 = 0, /* Only SHA */ NLM_HASH_MODE_SHA224 = 1, /* Only SHA */ NLM_HASH_MODE_SHA256 = 2, /* Only SHA */ NLM_HASH_MODE_SHA384 = 3, /* Only SHA */ NLM_HASH_MODE_SHA512 = 4, /* Only SHA */ NLM_HASH_MODE_CMAC = 5, /* AES and Camellia */ NLM_HASH_MODE_XCBC = 6, /* AES and Camellia */ NLM_HASH_MODE_CBC_MAC = 7, /* AES and Camellia */ NLM_HASH_MODE_CCM = 8, /* AES */ NLM_HASH_MODE_GCM = 9, /* AES */ NLM_HASH_MODE_MAX = 0xA, -}; +}; /** * @brief crypto control descriptor, should be cache aligned * @ingroup crypto */ struct nlm_crypto_pkt_ctrl { uint64_t desc0; /* combination of cipher and hash keys */ uint64_t key[MAX_KEY_LEN_IN_DW]; - uint32_t cipherkeylen; - uint32_t hashkeylen; + uint32_t cipherkeylen; + uint32_t hashkeylen; uint32_t taglen; }; /** -* @brief crypto packet descriptor, should be cache aligned +* @brief crypto packet descriptor, should be cache aligned * @ingroup crypto */ struct nlm_crypto_pkt_param { uint64_t desc0; - uint64_t desc1; + uint64_t desc1; uint64_t desc2; uint64_t desc3; uint64_t segment[1][2]; }; static __inline__ uint64_t -nlm_crypto_form_rsa_ecc_fmn_entry0(unsigned int l3alloc, unsigned int type, +nlm_crypto_form_rsa_ecc_fmn_entry0(unsigned int l3alloc, unsigned int type, unsigned int func, uint64_t srcaddr) { - return (left_shift64(l3alloc, 61, 1) | + return (left_shift64(l3alloc, 61, 1) | left_shift64(type, 46, 7) | left_shift64(func, 40, 6) | left_shift64(srcaddr, 0, 40)); } static __inline__ uint64_t nlm_crypto_form_rsa_ecc_fmn_entry1(unsigned int dstclobber, unsigned int l3alloc, unsigned int fbvc, uint64_t dstaddr) { return (left_shift64(dstclobber, 62, 1) | left_shift64(l3alloc, 61, 1) | left_shift64(fbvc, 40, 12) | left_shift64(dstaddr, 0, 40)); } /** * @brief Generate cypto control descriptor * @ingroup crypto -* hmac : 1 for hash with hmac +* hmac : 1 for hash with hmac * hashalg, see hash_alg enums * hashmode, see hash_mode enums * cipherhalg, see cipher_alg enums * ciphermode, see cipher_mode enums -* arc4_cipherkeylen : length of arc4 cipher key, 0 is interpreted as 32 -* arc4_keyinit : -* cfbmask : cipher text for feedback, +* arc4_cipherkeylen : length of arc4 cipher key, 0 is interpreted as 32 +* arc4_keyinit : +* cfbmask : cipher text for feedback, * 0(1 bit), 1(2 bits), 2(4 bits), 3(8 bits), 4(16bits), 5(32 bits), * 6(64 bits), 7(128 bits) */ static __inline__ uint64_t nlm_crypto_form_pkt_ctrl_desc(unsigned int hmac, unsigned int hashalg, unsigned int hashmode, unsigned int cipheralg, unsigned int ciphermode, unsigned int arc4_cipherkeylen, unsigned int arc4_keyinit, unsigned int cfbmask) { - return (left_shift64(hmac, 61, 1) | - left_shift64(hashalg, 52, 8) | - left_shift64(hashmode, 43, 8) | - left_shift64(cipheralg, 34, 8) | - left_shift64(ciphermode, 25, 8) | - left_shift64(arc4_cipherkeylen, 18, 5) | - left_shift64(arc4_keyinit, 17, 1) | + return (left_shift64(hmac, 61, 1) | + left_shift64(hashalg, 52, 8) | + left_shift64(hashmode, 43, 8) | + left_shift64(cipheralg, 34, 8) | + left_shift64(ciphermode, 25, 8) | + left_shift64(arc4_cipherkeylen, 18, 5) | + left_shift64(arc4_keyinit, 17, 1) | left_shift64(cfbmask, 0, 3)); } /** * @brief Generate cypto packet descriptor 0 * @ingroup crypto * tls : 1 (tls enabled) 0(tls disabled) * hash_source : 1 (encrypted data is sent to the auth engine) * 0 (plain data is sent to the auth engine) * hashout_l3alloc : 1 (auth output is transited through l3 cache) * encrypt : 1 (for encrypt) 0 (for decrypt) * ivlen : iv length in bytes * hashdst_addr : hash out physical address, byte aligned */ static __inline__ uint64_t nlm_crypto_form_pkt_desc0(unsigned int tls, unsigned int hash_source, unsigned int hashout_l3alloc, unsigned int encrypt, unsigned int ivlen, uint64_t hashdst_addr) { return (left_shift64(tls, 63, 1) | left_shift64(hash_source, 62, 1) | left_shift64(hashout_l3alloc, 60, 1) | left_shift64(encrypt, 59, 1) | left_shift64_mask((ivlen - 1), 41, 16) | left_shift64(hashdst_addr, 0, 40)); } /** * @brief Generate cypto packet descriptor 1 * @ingroup crypto * cipherlen : cipher length in bytes * hashlen : hash length in bytes */ static __inline__ uint64_t nlm_crypto_form_pkt_desc1(unsigned int cipherlen, unsigned int hashlen) { return (left_shift64_mask((cipherlen - 1), 32, 32) | left_shift64_mask((hashlen - 1), 0, 32)); -} +} /** * @brief Generate cypto packet descriptor 2 * @ingroup crypto * ivoff : iv offset, offset from start of src data addr * ciperbit_cnt : number of valid bits in the last input byte to the cipher, * 0 (8 bits), 1 (1 bit)..7 (7 bits) * cipheroff : cipher offset, offset from start of src data addr * hashbit_cnt : number of valid bits in the last input byte to the auth * 0 (8 bits), 1 (1 bit)..7 (7 bits) * hashclobber : 1 (hash output will be written as multiples of cachelines, no * read modify write) * hashoff : hash offset, offset from start of src data addr */ static __inline__ uint64_t nlm_crypto_form_pkt_desc2(unsigned int ivoff, unsigned int cipherbit_cnt, unsigned int cipheroff, unsigned int hashbit_cnt, unsigned int hashclobber, unsigned int hashoff) { return (left_shift64(ivoff , 45, 16) | left_shift64(cipherbit_cnt, 42, 3) | left_shift64(cipheroff, 22, 16) | left_shift64(hashbit_cnt, 19, 3) | left_shift64(hashclobber, 18, 1) | left_shift64(hashoff, 0, 16)); } /** * @brief Generate cypto packet descriptor 3 * @ingroup crypto * designer_vc : designer freeback fmn destination id * taglen : length in bits of the tag generated by the auth engine * md5 (128 bits), sha1 (160), sha224 (224), sha384 (384), * sha512 (512), Kasumi (32), snow3g (32), gcm (128) -* hmacpad : 1 if hmac padding is already done +* hmacpad : 1 if hmac padding is already done */ static __inline__ uint64_t nlm_crypto_form_pkt_desc3(unsigned int designer_vc, unsigned int taglen, unsigned int arc4_state_save_l3, unsigned int arc4_save_state, unsigned int hmacpad) { return (left_shift64(designer_vc, 48, 16) | left_shift64(taglen, 11, 16) | left_shift64(arc4_state_save_l3, 8, 1) | left_shift64(arc4_save_state, 6, 1) | left_shift64(hmacpad, 5, 1)); } /** * @brief Generate cypto packet descriptor 4 * @ingroup crypto * srcfraglen : length of the source fragment(header + data + tail) in bytes * srcfragaddr : physical address of the srouce fragment */ static __inline__ uint64_t nlm_crypto_form_pkt_desc4(uint64_t srcfraglen, unsigned int srcfragaddr ) { return (left_shift64_mask((srcfraglen - 1), 48, 16) | left_shift64(srcfragaddr, 0, 40)); } /** * @brief Generate cypto packet descriptor 5 * @ingroup crypto * dstfraglen : length of the dst fragment(header + data + tail) in bytes * chipherout_l3alloc : 1(cipher output is transited through l3 cache) * cipherclobber : 1 (cipher output will be written as multiples of cachelines, * no read modify write) * chiperdst_addr : physical address of the cipher destination address */ static __inline__ uint64_t nlm_crypto_form_pkt_desc5(unsigned int dstfraglen, unsigned int cipherout_l3alloc, unsigned int cipherclobber, uint64_t cipherdst_addr) { return (left_shift64_mask((dstfraglen - 1), 48, 16) | left_shift64(cipherout_l3alloc, 46, 1) | left_shift64(cipherclobber, 41, 1) | left_shift64(cipherdst_addr, 0, 40)); } /** * @brief Generate crypto packet fmn message entry 0 * @ingroup crypto * freeback_vc: freeback response destination address * designer_fblen : Designer freeback length, 1 - 4 * designerdesc_valid : designer desc valid or not * cipher_keylen : cipher key length in bytes * ctrldesc_addr : physicall address of the control descriptor */ static __inline__ uint64_t nlm_crypto_form_pkt_fmn_entry0(unsigned int freeback_vc, unsigned int designer_fblen, unsigned int designerdesc_valid, unsigned int cipher_keylen, uint64_t cntldesc_addr) { return (left_shift64(freeback_vc, 48, 16) | left_shift64_mask(designer_fblen - 1, 46, 2) | left_shift64(designerdesc_valid, 45, 1) | left_shift64_mask(((cipher_keylen + 7) >> 3), 40, 5) | left_shift64(cntldesc_addr >> 6, 0, 34)); } /** * @brief Generate crypto packet fmn message entry 1 * @ingroup crypto * arc4load_state : 1 if load state required 0 otherwise * hash_keylen : hash key length in bytes * pktdesc_size : packet descriptor size in bytes * pktdesc_addr : physicall address of the packet descriptor */ static __inline__ uint64_t nlm_crypto_form_pkt_fmn_entry1(unsigned int arc4load_state, unsigned int hash_keylen, unsigned int pktdesc_size, uint64_t pktdesc_addr) { return (left_shift64(arc4load_state, 63, 1) | left_shift64_mask(((hash_keylen + 7) >> 3), 56, 5) | left_shift64_mask(((pktdesc_size >> 4) - 1), 43, 12) | left_shift64(pktdesc_addr >> 6, 0, 34)); } static __inline__ int nlm_crypto_get_hklen_taglen(enum nlm_hash_algo hashalg, enum nlm_hash_mode hashmode, unsigned int *taglen, unsigned int *hklen) { if (hashalg == NLM_HASH_MD5) { *taglen = 128; *hklen = 64; } else if (hashalg == NLM_HASH_SHA) { switch (hashmode) { - case NLM_HASH_MODE_SHA1: + case NLM_HASH_MODE_SHA1: *taglen = 160; *hklen = 64; break; - case NLM_HASH_MODE_SHA224: + case NLM_HASH_MODE_SHA224: *taglen = 224; *hklen = 64; break; - case NLM_HASH_MODE_SHA256: + case NLM_HASH_MODE_SHA256: *taglen = 256; *hklen = 64; break; - case NLM_HASH_MODE_SHA384: + case NLM_HASH_MODE_SHA384: *taglen = 384; *hklen = 128; break; - case NLM_HASH_MODE_SHA512: + case NLM_HASH_MODE_SHA512: *taglen = 512; *hklen = 128; break; default: printf("Error : invalid shaid (%s)\n", __func__); return (-1); } } else if (hashalg == NLM_HASH_KASUMI_F9) { *taglen = 32; *hklen = 0; } else if (hashalg == NLM_HASH_SNOW3G_F9) { *taglen = 32; *hklen = 0; } else if (hashmode == NLM_HASH_MODE_XCBC) { *taglen = 128; *hklen = 0; } else if (hashmode == NLM_HASH_MODE_GCM) { *taglen = 128; *hklen = 0; } else if (hashalg == NLM_HASH_BYPASS) { *taglen = 0; *hklen = 0; } else { printf("Error:Hash alg/mode not found\n"); return (-1); } /* TODO : Add remaining cases */ return (0); } /** * @brief Generate fill cryto control info structure * @ingroup crypto -* hmac : 1 for hash with hmac +* hmac : 1 for hash with hmac * hashalg: see above, hash_alg enums * hashmode: see above, hash_mode enums * cipherhalg: see above, cipher_alg enums * ciphermode: see above, cipher_mode enums * */ static __inline__ int nlm_crypto_fill_pkt_ctrl(struct nlm_crypto_pkt_ctrl *ctrl, unsigned int hmac, enum nlm_hash_algo hashalg, enum nlm_hash_mode hashmode, enum nlm_cipher_algo cipheralg, enum nlm_cipher_mode ciphermode, unsigned char *cipherkey, unsigned int cipherkeylen, unsigned char *hashkey, unsigned int hashkeylen) { unsigned int taglen = 0, hklen = 0; - ctrl->desc0 = nlm_crypto_form_pkt_ctrl_desc(hmac, hashalg, hashmode, + ctrl->desc0 = nlm_crypto_form_pkt_ctrl_desc(hmac, hashalg, hashmode, cipheralg, ciphermode, 0, 0, 0); memset(ctrl->key, 0, sizeof(ctrl->key)); if (cipherkey) memcpy(ctrl->key, cipherkey, cipherkeylen); if (hashkey) memcpy((unsigned char *)&ctrl->key[(cipherkeylen + 7) / 8], hashkey, hashkeylen); if (nlm_crypto_get_hklen_taglen(hashalg, hashmode, &taglen, &hklen) < 0) return (-1); ctrl->cipherkeylen = cipherkeylen; ctrl->hashkeylen = hklen; ctrl->taglen = taglen; - + /* TODO : add the invalid checks and return error */ return (0); } /** * @brief Top level function for generation pkt desc 0 to 3 for cipher auth * @ingroup crypto * ctrl : pointer to control structure * param : pointer to the param structure * encrypt : 1(for encrypt) 0(for decrypt) * hash_source : 1(encrypted data is sent to the auth engine) 0(plain data is * sent to the auth engine) * ivoff : iv offset from start of data * ivlen : iv length in bytes * hashoff : hash offset from start of data * hashlen : hash length in bytes * hmacpad : hmac padding required or not, 1 if already padded * cipheroff : cipher offset from start of data * cipherlen : cipher length in bytes * hashdst_addr : hash destination physical address */ static __inline__ void nlm_crypto_fill_cipher_auth_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl, struct nlm_crypto_pkt_param *param, unsigned int encrypt, unsigned int hash_source, unsigned int ivoff, unsigned int ivlen, unsigned int hashoff, unsigned int hashlen, unsigned int hmacpad, unsigned int cipheroff, unsigned int cipherlen, unsigned char *hashdst_addr) { param->desc0 = nlm_crypto_form_pkt_desc0(0, hash_source, 1, encrypt, ivlen, vtophys(hashdst_addr)); param->desc1 = nlm_crypto_form_pkt_desc1(cipherlen, hashlen); param->desc2 = nlm_crypto_form_pkt_desc2(ivoff, 0, cipheroff, 0, 0, hashoff); param->desc3 = nlm_crypto_form_pkt_desc3(0, ctrl->taglen, 0, 0, hmacpad); } /** * @brief Top level function for generation pkt desc 0 to 3 for cipher operation * @ingroup crypto * ctrl : pointer to control structure * param : pointer to the param structure * encrypt : 1(for encrypt) 0(for decrypt) * ivoff : iv offset from start of data * ivlen : iv length in bytes * cipheroff : cipher offset from start of data * cipherlen : cipher length in bytes */ - - static __inline__ void nlm_crypto_fill_cipher_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl, struct nlm_crypto_pkt_param *param, unsigned int encrypt, unsigned int ivoff, unsigned int ivlen, unsigned int cipheroff, unsigned int cipherlen) { param->desc0 = nlm_crypto_form_pkt_desc0(0, 0, 0, encrypt, ivlen, 0ULL); param->desc1 = nlm_crypto_form_pkt_desc1(cipherlen, 1); param->desc2 = nlm_crypto_form_pkt_desc2(ivoff, 0, cipheroff, 0, 0, 0); param->desc3 = nlm_crypto_form_pkt_desc3(0, ctrl->taglen, 0, 0, 0); } /** * @brief Top level function for generation pkt desc 0 to 3 for auth operation * @ingroup crypto * ctrl : pointer to control structure * param : pointer to the param structure * hashoff : hash offset from start of data * hashlen : hash length in bytes * hmacpad : hmac padding required or not, 1 if already padded * hashdst_addr : hash destination physical address */ static __inline__ void nlm_crypto_fill_auth_pkt_param(struct nlm_crypto_pkt_ctrl *ctrl, struct nlm_crypto_pkt_param *param, unsigned int hashoff, unsigned int hashlen, unsigned int hmacpad, unsigned char *hashdst_addr) { param->desc0 = nlm_crypto_form_pkt_desc0(0, 0, 1, 0, 1, vtophys(hashdst_addr)); param->desc1 = nlm_crypto_form_pkt_desc1(1, hashlen); param->desc2 = nlm_crypto_form_pkt_desc2(0, 0, 0, 0, 0, hashoff); param->desc3 = nlm_crypto_form_pkt_desc3(0, ctrl->taglen, 0, 0, hmacpad); } static __inline__ unsigned int nlm_crypto_fill_src_seg(struct nlm_crypto_pkt_param *param, int seg, unsigned char *input, unsigned int inlen) { unsigned off = 0, len = 0; unsigned int remlen = inlen; for (; remlen > 0;) { len = remlen > NLM_CRYPTO_MAX_SEG_LEN ? NLM_CRYPTO_MAX_SEG_LEN : remlen; param->segment[seg][0] = nlm_crypto_form_pkt_desc4(len, vtophys(input + off)); remlen -= len; off += len; seg++; } return (seg); } static __inline__ unsigned int -nlm_crypto_fill_dst_seg(struct nlm_crypto_pkt_param *param, +nlm_crypto_fill_dst_seg(struct nlm_crypto_pkt_param *param, int seg, unsigned char *output, unsigned int outlen) { unsigned off = 0, len = 0; unsigned int remlen = outlen; for (; remlen > 0;) { len = remlen > NLM_CRYPTO_MAX_SEG_LEN ? NLM_CRYPTO_MAX_SEG_LEN : remlen; param->segment[seg][1] = nlm_crypto_form_pkt_desc5(len, 1, 0, vtophys(output + off)); remlen -= len; off += len; seg++; } return (seg); } #endif Index: head/sys/mips/nlm/hal/pcibus.h =================================================================== --- head/sys/mips/nlm/hal/pcibus.h (revision 279386) +++ head/sys/mips/nlm/hal/pcibus.h (revision 279387) @@ -1,121 +1,121 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef __XLP_PCIBUS_H__ #define __XLP_PCIBUS_H__ #define MSI_MIPS_ADDR_BASE 0xfee00000 /* MSI support */ #define MSI_MIPS_ADDR_DEST 0x000ff000 #define MSI_MIPS_ADDR_RH 0x00000008 #define MSI_MIPS_ADDR_RH_OFF 0x00000000 #define MSI_MIPS_ADDR_RH_ON 0x00000008 #define MSI_MIPS_ADDR_DM 0x00000004 #define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000 #define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004 /* Fields in data for Intel MSI messages. */ #define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */ #define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */ #define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */ #define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */ #define MSI_MIPS_DATA_DEASSERT 0x00000000 #define MSI_MIPS_DATA_ASSERT 0x00004000 #define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */ #define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */ #define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */ #define MSI_MIPS_DATA_INTVEC 0x000000ff /* PCIE Memory and IO regions */ #define PCIE_MEM_BASE 0xd0000000ULL #define PCIE_MEM_LIMIT 0xdfffffffULL #define PCIE_IO_BASE 0x14000000ULL #define PCIE_IO_LIMIT 0x15ffffffULL #define PCIE_BRIDGE_CMD 0x1 #define PCIE_BRIDGE_MSI_CAP 0x14 #define PCIE_BRIDGE_MSI_ADDRL 0x15 #define PCIE_BRIDGE_MSI_ADDRH 0x16 #define PCIE_BRIDGE_MSI_DATA 0x17 /* XLP Global PCIE configuration space registers */ #define PCIE_BYTE_SWAP_MEM_BASE 0x247 #define PCIE_BYTE_SWAP_MEM_LIM 0x248 #define PCIE_BYTE_SWAP_IO_BASE 0x249 #define PCIE_BYTE_SWAP_IO_LIM 0x24A #define PCIE_MSI_STATUS 0x25A #define PCIE_MSI_EN 0x25B #define PCIE_INT_EN0 0x261 /* PCIE_MSI_EN */ #define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF /* PCIE_INT_EN0 */ #define PCIE_MSI_INT_EN (1 << 9) /* XXXJC: Ax workaround */ #define PCIE_LINK0_IRT 78 #if !defined(LOCORE) && !defined(__ASSEMBLY__) #define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) #define nlm_get_pcie_base(node, inst) \ nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) #define nlm_get_pcie_regbase(node, inst) \ (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) static __inline int xlp_pcie_link_irt(int link) { if ((link < 0) || (link > 3)) return (-1); return (PCIE_LINK0_IRT + link); } /* * Build Intel MSI message and data values from a source. AMD64 systems * seem to be compatible, so we use the same function for both. */ #define MIPS_MSI_ADDR(cpu) \ (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \ MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL) #define MIPS_MSI_DATA(irq) \ (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \ MSI_MIPS_DATA_ASSERT | (irq)) #endif #endif /* __XLP_PCIBUS_H__ */ Index: head/sys/mips/nlm/hal/poe.h =================================================================== --- head/sys/mips/nlm/hal/poe.h (revision 279386) +++ head/sys/mips/nlm/hal/poe.h (revision 279387) @@ -1,352 +1,352 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __NLM_POE_H__ #define __NLM_POE_H__ /** * @file_name poe.h * @author Netlogic Microsystems * @brief Basic definitions of XLP Packet Order Engine */ /* POE specific registers */ #define POE_CL0_ENQ_SPILL_BASE_LO 0x0 #define POE_CL1_ENQ_SPILL_BASE_LO 0x2 #define POE_CL2_ENQ_SPILL_BASE_LO 0x4 #define POE_CL3_ENQ_SPILL_BASE_LO 0x6 #define POE_CL4_ENQ_SPILL_BASE_LO 0x8 #define POE_CL5_ENQ_SPILL_BASE_LO 0xa #define POE_CL6_ENQ_SPILL_BASE_LO 0xc #define POE_CL7_ENQ_SPILL_BASE_LO 0xe #define POE_CL0_ENQ_SPILL_BASE_HI 0x1 #define POE_CL1_ENQ_SPILL_BASE_HI 0x3 #define POE_CL2_ENQ_SPILL_BASE_HI 0x5 #define POE_CL3_ENQ_SPILL_BASE_HI 0x7 #define POE_CL4_ENQ_SPILL_BASE_HI 0x9 #define POE_CL5_ENQ_SPILL_BASE_HI 0xb #define POE_CL6_ENQ_SPILL_BASE_HI 0xd #define POE_CL7_ENQ_SPILL_BASE_HI 0xf #define POE_CL0_DEQ_SPILL_BASE_LO 0x10 #define POE_CL1_DEQ_SPILL_BASE_LO 0x12 #define POE_CL2_DEQ_SPILL_BASE_LO 0x14 #define POE_CL3_DEQ_SPILL_BASE_LO 0x16 #define POE_CL4_DEQ_SPILL_BASE_LO 0x18 #define POE_CL5_DEQ_SPILL_BASE_LO 0x1a #define POE_CL6_DEQ_SPILL_BASE_LO 0x1c #define POE_CL7_DEQ_SPILL_BASE_LO 0x1e #define POE_CL0_DEQ_SPILL_BASE_HI 0x11 #define POE_CL1_DEQ_SPILL_BASE_HI 0x13 #define POE_CL2_DEQ_SPILL_BASE_HI 0x15 #define POE_CL3_DEQ_SPILL_BASE_HI 0x17 #define POE_CL4_DEQ_SPILL_BASE_HI 0x19 #define POE_CL5_DEQ_SPILL_BASE_HI 0x1b #define POE_CL6_DEQ_SPILL_BASE_HI 0x1d #define POE_CL7_DEQ_SPILL_BASE_HI 0x1f #define POE_MSG_STORAGE_BASE_ADDR_LO 0x20 #define POE_MSG_STORAGE_BASE_ADDR_HI 0x21 #define POE_FBP_BASE_ADDR_LO 0x22 #define POE_FBP_BASE_ADDR_HI 0x23 #define POE_CL0_ENQ_SPILL_MAXLINE_LO 0x24 #define POE_CL1_ENQ_SPILL_MAXLINE_LO 0x25 #define POE_CL2_ENQ_SPILL_MAXLINE_LO 0x26 #define POE_CL3_ENQ_SPILL_MAXLINE_LO 0x27 #define POE_CL4_ENQ_SPILL_MAXLINE_LO 0x28 #define POE_CL5_ENQ_SPILL_MAXLINE_LO 0x29 #define POE_CL6_ENQ_SPILL_MAXLINE_LO 0x2a #define POE_CL7_ENQ_SPILL_MAXLINE_LO 0x2b #define POE_CL0_ENQ_SPILL_MAXLINE_HI 0x2c #define POE_CL1_ENQ_SPILL_MAXLINE_HI 0x2d #define POE_CL2_ENQ_SPILL_MAXLINE_HI 0x2e #define POE_CL3_ENQ_SPILL_MAXLINE_HI 0x2f #define POE_CL4_ENQ_SPILL_MAXLINE_HI 0x30 #define POE_CL5_ENQ_SPILL_MAXLINE_HI 0x31 #define POE_CL6_ENQ_SPILL_MAXLINE_HI 0x32 #define POE_CL7_ENQ_SPILL_MAXLINE_HI 0x33 #define POE_MAX_FLOW_MSG0 0x40 #define POE_MAX_FLOW_MSG1 0x41 #define POE_MAX_FLOW_MSG2 0x42 #define POE_MAX_FLOW_MSG3 0x43 #define POE_MAX_FLOW_MSG4 0x44 #define POE_MAX_FLOW_MSG5 0x45 #define POE_MAX_FLOW_MSG6 0x46 #define POE_MAX_FLOW_MSG7 0x47 #define POE_MAX_MSG_CL0 0x48 #define POE_MAX_MSG_CL1 0x49 #define POE_MAX_MSG_CL2 0x4a #define POE_MAX_MSG_CL3 0x4b #define POE_MAX_MSG_CL4 0x4c #define POE_MAX_MSG_CL5 0x4d #define POE_MAX_MSG_CL6 0x4e #define POE_MAX_MSG_CL7 0x4f #define POE_MAX_LOC_BUF_STG_CL0 0x50 #define POE_MAX_LOC_BUF_STG_CL1 0x51 #define POE_MAX_LOC_BUF_STG_CL2 0x52 #define POE_MAX_LOC_BUF_STG_CL3 0x53 #define POE_MAX_LOC_BUF_STG_CL4 0x54 #define POE_MAX_LOC_BUF_STG_CL5 0x55 #define POE_MAX_LOC_BUF_STG_CL6 0x56 #define POE_MAX_LOC_BUF_STG_CL7 0x57 #define POE_ENQ_MSG_COUNT0_SIZE 0x58 #define POE_ENQ_MSG_COUNT1_SIZE 0x59 #define POE_ENQ_MSG_COUNT2_SIZE 0x5a #define POE_ENQ_MSG_COUNT3_SIZE 0x5b #define POE_ENQ_MSG_COUNT4_SIZE 0x5c #define POE_ENQ_MSG_COUNT5_SIZE 0x5d #define POE_ENQ_MSG_COUNT6_SIZE 0x5e #define POE_ENQ_MSG_COUNT7_SIZE 0x5f #define POE_ERR_MSG_DESCRIP_LO0 0x60 #define POE_ERR_MSG_DESCRIP_LO1 0x62 #define POE_ERR_MSG_DESCRIP_LO2 0x64 #define POE_ERR_MSG_DESCRIP_LO3 0x66 #define POE_ERR_MSG_DESCRIP_HI0 0x61 #define POE_ERR_MSG_DESCRIP_HI1 0x63 #define POE_ERR_MSG_DESCRIP_HI2 0x65 #define POE_ERR_MSG_DESCRIP_HI3 0x67 #define POE_OOO_MSG_CNT_LO 0x68 #define POE_IN_ORDER_MSG_CNT_LO 0x69 #define POE_LOC_BUF_STOR_CNT_LO 0x6a #define POE_EXT_BUF_STOR_CNT_LO 0x6b #define POE_LOC_BUF_ALLOC_CNT_LO 0x6c #define POE_EXT_BUF_ALLOC_CNT_LO 0x6d #define POE_OOO_MSG_CNT_HI 0x6e #define POE_IN_ORDER_MSG_CNT_HI 0x6f #define POE_LOC_BUF_STOR_CNT_HI 0x70 #define POE_EXT_BUF_STOR_CNT_HI 0x71 #define POE_LOC_BUF_ALLOC_CNT_HI 0x72 #define POE_EXT_BUF_ALLOC_CNT_HI 0x73 #define POE_MODE_ERR_FLOW_ID 0x74 #define POE_STATISTICS_ENABLE 0x75 #define POE_MAX_SIZE_FLOW 0x76 #define POE_MAX_SIZE 0x77 #define POE_FBP_SP 0x78 #define POE_FBP_SP_EN 0x79 #define POE_LOC_ALLOC_EN 0x7a #define POE_EXT_ALLOC_EN 0x7b #define POE_DISTR_0_DROP_CNT 0xc0 #define POE_DISTR_1_DROP_CNT 0xc1 #define POE_DISTR_2_DROP_CNT 0xc2 #define POE_DISTR_3_DROP_CNT 0xc3 #define POE_DISTR_4_DROP_CNT 0xc4 #define POE_DISTR_5_DROP_CNT 0xc5 #define POE_DISTR_6_DROP_CNT 0xc6 #define POE_DISTR_7_DROP_CNT 0xc7 #define POE_DISTR_8_DROP_CNT 0xc8 #define POE_DISTR_9_DROP_CNT 0xc9 #define POE_DISTR_10_DROP_CNT 0xca #define POE_DISTR_11_DROP_CNT 0xcb #define POE_DISTR_12_DROP_CNT 0xcc #define POE_DISTR_13_DROP_CNT 0xcd #define POE_DISTR_14_DROP_CNT 0xce #define POE_DISTR_15_DROP_CNT 0xcf #define POE_CLASS_0_DROP_CNT 0xd0 #define POE_CLASS_1_DROP_CNT 0xd1 #define POE_CLASS_2_DROP_CNT 0xd2 #define POE_CLASS_3_DROP_CNT 0xd3 #define POE_CLASS_4_DROP_CNT 0xd4 #define POE_CLASS_5_DROP_CNT 0xd5 #define POE_CLASS_6_DROP_CNT 0xd6 #define POE_CLASS_7_DROP_CNT 0xd7 #define POE_DISTR_C0_DROP_CNT 0xd8 #define POE_DISTR_C1_DROP_CNT 0xd9 #define POE_DISTR_C2_DROP_CNT 0xda #define POE_DISTR_C3_DROP_CNT 0xdb #define POE_DISTR_C4_DROP_CNT 0xdc #define POE_DISTR_C5_DROP_CNT 0xdd #define POE_DISTR_C6_DROP_CNT 0xde #define POE_DISTR_C7_DROP_CNT 0xdf #define POE_CPU_DROP_CNT 0xe0 #define POE_MAX_FLOW_DROP_CNT 0xe1 #define POE_INTERRUPT_VEC 0x140 #define POE_INTERRUPT_MASK 0x141 #define POE_FATALERR_MASK 0x142 #define POE_IDI_CFG 0x143 #define POE_TIMEOUT_VALUE 0x144 #define POE_CACHE_ALLOC_EN 0x145 #define POE_FBP_ECC_ERR_CNT 0x146 #define POE_MSG_STRG_ECC_ERR_CNT 0x147 #define POE_FID_INFO_ECC_ERR_CNT 0x148 #define POE_MSG_INFO_ECC_ERR_CNT 0x149 #define POE_LL_ECC_ERR_CNT 0x14a #define POE_SIZE_ECC_ERR_CNT 0x14b #define POE_FMN_TXCR_ECC_ERR_CNT 0x14c #define POE_ENQ_INSPIL_ECC_ERR_CNT 0x14d #define POE_ENQ_OUTSPIL_ECC_ERR_CNT 0x14e #define POE_DEQ_OUTSPIL_ECC_ERR_CNT 0x14f #define POE_ENQ_MSG_SENT 0x150 #define POE_ENQ_MSG_CNT 0x151 #define POE_FID_RDATA 0x152 #define POE_FID_WDATA 0x153 #define POE_FID_CMD 0x154 #define POE_FID_ADDR 0x155 #define POE_MSG_INFO_CMD 0x156 #define POE_MSG_INFO_ADDR 0x157 #define POE_MSG_INFO_RDATA 0x158 #define POE_LL_CMD 0x159 #define POE_LL_ADDR 0x15a #define POE_LL_RDATA 0x15b #define POE_MSG_STG_CMD 0x15c #define POE_MSG_STG_ADDR 0x15d #define POE_MSG_STG_RDATA 0x15e #define POE_DISTR_THRESHOLD_0 0x1c0 #define POE_DISTR_THRESHOLD_1 0x1c1 #define POE_DISTR_THRESHOLD_2 0x1c2 #define POE_DISTR_THRESHOLD_3 0x1c3 #define POE_DISTR_THRESHOLD_4 0x1c4 #define POE_DISTR_THRESHOLD(i) (0x1c0 + (i)) #define POE_DISTR_EN 0x1c5 #define POE_ENQ_SPILL_THOLD 0x1c8 #define POE_DEQ_SPILL_THOLD 0x1c9 #define POE_DEQ_SPILL_TIMER 0x1ca #define POE_DISTR_CLASS_DROP_EN 0x1cb #define POE_DISTR_VEC_DROP_EN 0x1cc #define POE_DISTR_DROP_TIMER 0x1cd #define POE_ERROR_LOG_W0 0x1ce #define POE_ERROR_LOG_W1 0x1cf #define POE_ERROR_LOG_W2 0x1d0 #define POE_ERR_INJ_CTRL0 0x1d1 #define POE_TX_TIMER 0x1d4 #define NUM_DIST_VEC 16 #define NUM_WORDS_PER_DV 16 #define MAX_DV_TBL_ENTRIES (NUM_DIST_VEC * NUM_WORDS_PER_DV) #define POE_DIST_THRESHOLD_VAL 0xa /* * POE distribution vectors * * Each vector is 512 bit with msb indicating vc 512 and lsb indicating vc 0 * 512-bit-vector is specified as 16 32-bit words. * Left most word has the vc range 511-479 right most word has vc range 31 - 0 * Each word has the MSB select higer vc number and LSB select lower vc num */ #define POE_DISTVECT_BASE 0x100 #define POE_DISTVECT(vec) (POE_DISTVECT_BASE + 16 * (vec)) #define POE_DISTVECT_OFFSET(node,cpu) (4 * (3 - (node)) + (3 - (cpu)/8)) #define POE_DISTVECT_SHIFT(node,cpu) (((cpu) % 8 ) * 4) #if !defined(LOCORE) && !defined(__ASSEMBLY__) #define nlm_read_poe_reg(b, r) nlm_read_reg(b, r) #define nlm_write_poe_reg(b, r, v) nlm_write_reg(b, r, v) #define nlm_read_poedv_reg(b, r) nlm_read_reg_xkphys(b, r) #define nlm_write_poedv_reg(b, r, v) nlm_write_reg_xkphys(b, r, v) #define nlm_get_poe_pcibase(node) \ nlm_pcicfg_base(XLP_IO_POE_OFFSET(node)) #define nlm_get_poe_regbase(node) \ (nlm_get_poe_pcibase(node) + XLP_IO_PCI_HDRSZ) #define nlm_get_poedv_regbase(node) \ nlm_xkphys_map_pcibar0(nlm_get_poe_pcibase(node)) static __inline int nlm_poe_max_flows(uint64_t poe_pcibase) { return (nlm_read_reg(poe_pcibase, XLP_PCI_DEVINFO_REG0)); } /* * Helper function, calculate the distribution vector * cm0, cm1, cm2, cm3 : CPU masks for nodes 0..3 * thr_vcmask: destination VCs for a thread */ static __inline void -nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3, +nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3, uint32_t thr_vcmask, uint32_t *distvec) { uint32_t cpumask = 0, val; int i, cpu, node, startcpu, index; thr_vcmask &= 0xf; for (node = 0; node < XLP_MAX_NODES; node++) { switch (node) { case 0: cpumask = cm0; break; case 1: cpumask = cm1; break; case 2: cpumask = cm2; break; case 3: cpumask = cm3; break; } for (i = 0; i < 4; i++) { val = 0; startcpu = 31 - i * 8; for (cpu = startcpu; cpu >= startcpu - 7; cpu--) { val <<= 4; if (cpumask & (1U << cpu)) val |= thr_vcmask; } index = POE_DISTVECT_OFFSET(node, startcpu); distvec[index] = val; } } } static __inline int nlm_write_poe_distvec(uint64_t poedv_base, int vec, uint32_t *distvec) { uint32_t reg; int i; if (vec < 0 || vec >= NUM_DIST_VEC) return (-1); for (i = 0; i < NUM_WORDS_PER_DV; i++) { reg = POE_DISTVECT(vec) + i; nlm_write_poedv_reg(poedv_base, reg, distvec[i]); } return (0); } static __inline void nlm_config_poe(uint64_t poe_base, uint64_t poedv_base) { uint32_t zerodv[NUM_WORDS_PER_DV]; int i; /* First disable distribution vector logic */ nlm_write_poe_reg(poe_base, POE_DISTR_EN, 0); memset(zerodv, 0, sizeof(zerodv)); for (i = 0; i < NUM_DIST_VEC; i++) nlm_write_poe_distvec(poedv_base, i, zerodv); /* set the threshold */ for (i = 0; i < 5; i++) nlm_write_poe_reg(poe_base, POE_DISTR_THRESHOLD(i), POE_DIST_THRESHOLD_VAL); nlm_write_poe_reg(poe_base, POE_DISTR_EN, 1); /* always enable local message store */ nlm_write_poe_reg(poe_base, POE_LOC_ALLOC_EN, 1); nlm_write_poe_reg(poe_base, POE_TX_TIMER, 0x3); } #endif /* !(LOCORE) && !(__ASSEMBLY__) */ #endif Index: head/sys/mips/nlm/hal/sgmii.h =================================================================== --- head/sys/mips/nlm/hal/sgmii.h (revision 279386) +++ head/sys/mips/nlm/hal/sgmii.h (revision 279387) @@ -1,217 +1,217 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __NLM_SGMII_H__ #define __NLM_SGMII_H__ /** * @file_name sgmii.h * @author Netlogic Microsystems * @brief Basic definitions of XLP SGMII ports */ #define SGMII_MAC_CONF1(block, i) NAE_REG(block, i, 0x00) #define SGMII_MAC_CONF2(block, i) NAE_REG(block, i, 0x01) #define SGMII_IPG_IFG(block, i) NAE_REG(block, i, 0x02) #define SGMII_HLF_DUP(block, i) NAE_REG(block, i, 0x03) #define SGMII_MAX_FRAME(block, i) NAE_REG(block, i, 0x04) #define SGMII_TEST(block, i) NAE_REG(block, i, 0x07) #define SGMII_MIIM_CONF(block, i) NAE_REG(block, i, 0x08) #define SGMII_MIIM_CMD(block, i) NAE_REG(block, i, 0x09) #define SGMII_MIIM_ADDR(block, i) NAE_REG(block, i, 0x0a) #define SGMII_MIIM_CTRL(block, i) NAE_REG(block, i, 0x0b) #define SGMII_MIIM_STAT(block, i) NAE_REG(block, i, 0x0c) #define SGMII_MIIM_IND(block, i) NAE_REG(block, i, 0x0d) #define SGMII_IO_CTRL(block, i) NAE_REG(block, i, 0x0e) #define SGMII_IO_STAT(block, i) NAE_REG(block, i, 0x0f) #define SGMII_STATS_MLR(block, i) NAE_REG(block, i, 0x1f) #define SGMII_STATS_TR64(block, i) NAE_REG(block, i, 0x20) #define SGMII_STATS_TR127(block, i) NAE_REG(block, i, 0x21) #define SGMII_STATS_TR255(block, i) NAE_REG(block, i, 0x22) #define SGMII_STATS_TR511(block, i) NAE_REG(block, i, 0x23) #define SGMII_STATS_TR1K(block, i) NAE_REG(block, i, 0x24) #define SGMII_STATS_TRMAX(block, i) NAE_REG(block, i, 0x25) #define SGMII_STATS_TRMGV(block, i) NAE_REG(block, i, 0x26) #define SGMII_STATS_RBYT(block, i) NAE_REG(block, i, 0x27) #define SGMII_STATS_RPKT(block, i) NAE_REG(block, i, 0x28) #define SGMII_STATS_RFCS(block, i) NAE_REG(block, i, 0x29) #define SGMII_STATS_RMCA(block, i) NAE_REG(block, i, 0x2a) #define SGMII_STATS_RBCA(block, i) NAE_REG(block, i, 0x2b) #define SGMII_STATS_RXCF(block, i) NAE_REG(block, i, 0x2c) #define SGMII_STATS_RXPF(block, i) NAE_REG(block, i, 0x2d) #define SGMII_STATS_RXUO(block, i) NAE_REG(block, i, 0x2e) #define SGMII_STATS_RALN(block, i) NAE_REG(block, i, 0x2f) #define SGMII_STATS_RFLR(block, i) NAE_REG(block, i, 0x30) #define SGMII_STATS_RCDE(block, i) NAE_REG(block, i, 0x31) #define SGMII_STATS_RCSE(block, i) NAE_REG(block, i, 0x32) #define SGMII_STATS_RUND(block, i) NAE_REG(block, i, 0x33) #define SGMII_STATS_ROVR(block, i) NAE_REG(block, i, 0x34) #define SGMII_STATS_RFRG(block, i) NAE_REG(block, i, 0x35) #define SGMII_STATS_RJBR(block, i) NAE_REG(block, i, 0x36) #define SGMII_STATS_TBYT(block, i) NAE_REG(block, i, 0x38) #define SGMII_STATS_TPKT(block, i) NAE_REG(block, i, 0x39) #define SGMII_STATS_TMCA(block, i) NAE_REG(block, i, 0x3a) #define SGMII_STATS_TBCA(block, i) NAE_REG(block, i, 0x3b) #define SGMII_STATS_TXPF(block, i) NAE_REG(block, i, 0x3c) #define SGMII_STATS_TDFR(block, i) NAE_REG(block, i, 0x3d) #define SGMII_STATS_TEDF(block, i) NAE_REG(block, i, 0x3e) #define SGMII_STATS_TSCL(block, i) NAE_REG(block, i, 0x3f) #define SGMII_STATS_TMCL(block, i) NAE_REG(block, i, 0x40) #define SGMII_STATS_TLCL(block, i) NAE_REG(block, i, 0x41) #define SGMII_STATS_TXCL(block, i) NAE_REG(block, i, 0x42) #define SGMII_STATS_TNCL(block, i) NAE_REG(block, i, 0x43) #define SGMII_STATS_TJBR(block, i) NAE_REG(block, i, 0x46) #define SGMII_STATS_TFCS(block, i) NAE_REG(block, i, 0x47) #define SGMII_STATS_TXCF(block, i) NAE_REG(block, i, 0x48) #define SGMII_STATS_TOVR(block, i) NAE_REG(block, i, 0x49) #define SGMII_STATS_TUND(block, i) NAE_REG(block, i, 0x4a) #define SGMII_STATS_TFRG(block, i) NAE_REG(block, i, 0x4b) #define SGMII_STATS_CAR1(block, i) NAE_REG(block, i, 0x4c) #define SGMII_STATS_CAR2(block, i) NAE_REG(block, i, 0x4d) #define SGMII_STATS_CAM1(block, i) NAE_REG(block, i, 0x4e) #define SGMII_STATS_CAM2(block, i) NAE_REG(block, i, 0x4f) #define SGMII_MAC_ADDR0_LO(block, i) NAE_REG(block, i, 0x50) #define SGMII_MAC_ADDR0_HI(block, i) NAE_REG(block, i, 0x51) #define SGMII_MAC_ADDR1_LO(block, i) NAE_REG(block, i, 0x52) #define SGMII_MAC_ADDR1_HI(block, i) NAE_REG(block, i, 0x53) #define SGMII_MAC_ADDR2_LO(block, i) NAE_REG(block, i, 0x54) #define SGMII_MAC_ADDR2_HI(block, i) NAE_REG(block, i, 0x55) #define SGMII_MAC_ADDR3_LO(block, i) NAE_REG(block, i, 0x56) #define SGMII_MAC_ADDR3_HI(block, i) NAE_REG(block, i, 0x57) #define SGMII_MAC_ADDR_MASK0_LO(block, i) NAE_REG(block, i, 0x58) #define SGMII_MAC_ADDR_MASK0_HI(block, i) NAE_REG(block, i, 0x59) #define SGMII_MAC_ADDR_MASK1_LO(block, i) NAE_REG(block, i, 0x5a) #define SGMII_MAC_ADDR_MASK1_HI(block, i) NAE_REG(block, i, 0x5b) #define SGMII_MAC_FILTER_CONFIG(block, i) NAE_REG(block, i, 0x5c) #define SGMII_HASHTBL_VEC_B31_0(block, i) NAE_REG(block, i, 0x60) #define SGMII_HASHTBL_VEC_B63_32(block, i) NAE_REG(block, i, 0x61) #define SGMII_HASHTBL_VEC_B95_64(block, i) NAE_REG(block, i, 0x62) #define SGMII_HASHTBL_VEC_B127_96(block, i) NAE_REG(block, i, 0x63) #define SGMII_HASHTBL_VEC_B159_128(block, i) NAE_REG(block, i, 0x64) #define SGMII_HASHTBL_VEC_B191_160(block, i) NAE_REG(block, i, 0x65) #define SGMII_HASHTBL_VEC_B223_192(block, i) NAE_REG(block, i, 0x66) #define SGMII_HASHTBL_VEC_B255_224(block, i) NAE_REG(block, i, 0x67) #define SGMII_HASHTBL_VEC_B287_256(block, i) NAE_REG(block, i, 0x68) #define SGMII_HASHTBL_VEC_B319_288(block, i) NAE_REG(block, i, 0x69) #define SGMII_HASHTBL_VEC_B351_320(block, i) NAE_REG(block, i, 0x6a) #define SGMII_HASHTBL_VEC_B383_352(block, i) NAE_REG(block, i, 0x6b) #define SGMII_HASHTBL_VEC_B415_384(block, i) NAE_REG(block, i, 0x6c) #define SGMII_HASHTBL_VEC_B447_416(block, i) NAE_REG(block, i, 0x6d) #define SGMII_HASHTBL_VEC_B479_448(block, i) NAE_REG(block, i, 0x6e) #define SGMII_HASHTBL_VEC_B511_480(block, i) NAE_REG(block, i, 0x6f) #define SGMII_NETIOR_VLANTYPE_FILTER(block, i) NAE_REG(block, i, 0x76) #define SGMII_NETIOR_RXDROP_CNTR(block, i) NAE_REG(block, i, 0x77) #define SGMII_NETIOR_PAUSE_QUANTAMULT(block, i) NAE_REG(block, i, 0x78) #define SGMII_NETIOR_MAC_CTRL_OPCODE(block, i) NAE_REG(block, i, 0x79) #define SGMII_NETIOR_MAC_DA_H(block, i) NAE_REG(block, i, 0x7a) #define SGMII_NETIOR_MAC_DA_L(block, i) NAE_REG(block, i, 0x7b) #define SGMII_NET_IFACE_CTRL3(block, i) NAE_REG(block, i, 0x7c) #define SGMII_NETIOR_GMAC_STAT(block, i) NAE_REG(block, i, 0x7d) #define SGMII_NET_IFACE_CTRL2(block, i) NAE_REG(block, i, 0x7e) #define SGMII_NET_IFACE_CTRL(block, i) NAE_REG(block, i, 0x7f) #if !defined(LOCORE) && !defined(__ASSEMBLY__) /* speed */ enum nlm_sgmii_speed { NLM_SGMII_SPEED_10, NLM_SGMII_SPEED_100, NLM_SGMII_SPEED_1000, NLM_SGMII_SPEED_RSVD }; /* duplexity */ enum nlm_sgmii_duplex_mode { NLM_SGMII_DUPLEX_AUTO, NLM_SGMII_DUPLEX_HALF, NLM_SGMII_DUPLEX_FULL }; /* stats */ enum { nlm_sgmii_stats_mlr, nlm_sgmii_stats_tr64, nlm_sgmii_stats_tr127, nlm_sgmii_stats_tr255, nlm_sgmii_stats_tr511, nlm_sgmii_stats_tr1k, nlm_sgmii_stats_trmax, nlm_sgmii_stats_trmgv, nlm_sgmii_stats_rbyt, nlm_sgmii_stats_rpkt, nlm_sgmii_stats_rfcs, nlm_sgmii_stats_rmca, nlm_sgmii_stats_rbca, nlm_sgmii_stats_rxcf, nlm_sgmii_stats_rxpf, nlm_sgmii_stats_rxuo, nlm_sgmii_stats_raln, nlm_sgmii_stats_rflr, nlm_sgmii_stats_rcde, nlm_sgmii_stats_rcse, nlm_sgmii_stats_rund, nlm_sgmii_stats_rovr, nlm_sgmii_stats_rfrg, nlm_sgmii_stats_rjbr, nlm_sgmii_stats_rdummy, /* not used */ nlm_sgmii_stats_tbyt, nlm_sgmii_stats_tpkt, nlm_sgmii_stats_tmca, nlm_sgmii_stats_tbca, nlm_sgmii_stats_txpf, nlm_sgmii_stats_tdfr, nlm_sgmii_stats_tedf, nlm_sgmii_stats_tscl, nlm_sgmii_stats_tmcl, nlm_sgmii_stats_tlcl, nlm_sgmii_stats_txcl, nlm_sgmii_stats_tncl, nlm_sgmii_stats_tjbr, nlm_sgmii_stats_tfcs, nlm_sgmii_stats_txcf, nlm_sgmii_stats_tovr, nlm_sgmii_stats_tund, nlm_sgmii_stats_tfrg, nlm_sgmii_stats_car1, nlm_sgmii_stats_car2, nlm_sgmii_stats_cam1, nlm_sgmii_stats_cam2 }; void nlm_configure_sgmii_interface(uint64_t, int, int, int, int); void nlm_sgmii_pcs_init(uint64_t, uint32_t); void nlm_nae_setup_mac(uint64_t, int, int, int, int, int, int, int); void nlm_nae_setup_rx_mode_sgmii(uint64_t, int, int, int, int, int, int, int); void nlm_nae_setup_mac_addr_sgmii(uint64_t, int, int, int, uint8_t *); #endif /* !(LOCORE) && !(__ASSEMBLY__) */ #endif Index: head/sys/mips/nlm/hal/ucore_loader.h =================================================================== --- head/sys/mips/nlm/hal/ucore_loader.h (revision 279386) +++ head/sys/mips/nlm/hal/ucore_loader.h (revision 279387) @@ -1,141 +1,141 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __NLM_UCORE_LOADER_H__ #define __NLM_UCORE_LOADER_H__ /** * @file_name ucore_loader.h * @author Netlogic Microsystems * @brief Ucore loader API header */ #define CODE_SIZE_PER_UCORE (4 << 10) static __inline__ void nlm_ucore_load_image(uint64_t nae_base, int ucore) { uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET + (ucore * CODE_SIZE_PER_UCORE); uint32_t *p = (uint32_t *)ucore_app_bin; int i, size; size = sizeof(ucore_app_bin)/sizeof(uint32_t); for (i = 0; i < size; i++, addr += 4) nlm_store_word_daddr(addr, htobe32(p[i])); /* add a 'nop' if number of instructions are odd */ - if (size & 0x1) + if (size & 0x1) nlm_store_word_daddr(addr, 0x0); } static __inline int nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data) { uint32_t ucore_cfg; uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET; if (index > 128) return (-1); ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); - /* set iram to zero */ + /* set iram to zero */ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, (ucore_cfg & ~(0x1 << 7))); - nlm_store_word_daddr(addr + (index * 4), data); + nlm_store_word_daddr(addr + (index * 4), data); /* restore ucore config */ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); return (0); } static __inline uint32_t nlm_ucore_read_sharedmem(uint64_t nae_base, int index) { uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET; uint32_t ucore_cfg, val; ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); - /* set iram to zero */ + /* set iram to zero */ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, (ucore_cfg & ~(0x1 << 7))); - val = nlm_load_word_daddr(addr + (index * 4)); + val = nlm_load_word_daddr(addr + (index * 4)); /* restore ucore config */ nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); return val; } static __inline__ int nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done) { int i, count = 0; uint32_t mask; uint32_t ucore_cfg = 0; mask = ucore_mask & 0xffff; /* Stop all ucores */ if (nae_reset_done == 0) { /* Skip the Ucore reset if NAE reset is done */ ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg | (1 << 24)); /* poll for ucore to get in to a wait state */ do { ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); } while ((ucore_cfg & (1 << 25)) == 0); } for (i = 0; i < sizeof(ucore_mask) * NBBY; i++) { if ((mask & (1 << i)) == 0) continue; nlm_ucore_load_image(nae_base, i); count++; } /* Enable per-domain ucores */ ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG); /* write one to reset bits to put the ucores in reset */ ucore_cfg = ucore_cfg | (((mask) & 0xffff) << 8); nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); /* write zero to reset bits to pull them out of reset */ ucore_cfg = ucore_cfg & (~(((mask) & 0xffff) << 8)) & ~(1 << 24); nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg); return (count); } #endif Index: head/sys/mips/nlm/hal/usb.h =================================================================== --- head/sys/mips/nlm/hal/usb.h (revision 279386) +++ head/sys/mips/nlm/hal/usb.h (revision 279387) @@ -1,59 +1,59 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef __NLM_USB_H__ #define __NLM_USB_H__ #define USB_CTL_0 0x01 #define USB_PHY_0 0x0A #define USB_PHY_RESET 0x01 #define USB_PHY_PORT_RESET_0 0x10 #define USB_PHY_PORT_RESET_1 0x20 #define USB_CONTROLLER_RESET 0x01 #define USB_INT_STATUS 0x0E #define USB_INT_EN 0x0F #define USB_PHY_INTERRUPT_EN 0x01 #define USB_OHCI_INTERRUPT_EN 0x02 #define USB_OHCI_INTERRUPT1_EN 0x04 #define USB_OHCI_INTERRUPT2_EN 0x08 #define USB_CTRL_INTERRUPT_EN 0x10 #if !defined(LOCORE) && !defined(__ASSEMBLY__) #define nlm_read_usb_reg(b, r) nlm_read_reg(b,r) #define nlm_write_usb_reg(b, r, v) nlm_write_reg(b,r,v) #define nlm_get_usb_pcibase(node, inst) nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst)) #define nlm_get_usb_hcd_base(node, inst) nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst)) #define nlm_get_usb_regbase(node, inst) (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) #endif #endif Index: head/sys/mips/nlm/hal/xaui.h =================================================================== --- head/sys/mips/nlm/hal/xaui.h (revision 279386) +++ head/sys/mips/nlm/hal/xaui.h (revision 279387) @@ -1,193 +1,193 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __NLM_XAUI_H__ #define __NLM_XAUI_H__ /** * @file_name xaui.h * @author Netlogic Microsystems * @brief Basic definitions of XLP XAUI ports */ #define XAUI_CONFIG0(block) NAE_REG(block, 4, 0x00) #define XAUI_CONFIG1(block) NAE_REG(block, 4, 0x01) #define XAUI_CONFIG2(block) NAE_REG(block, 4, 0x02) #define XAUI_CONFIG3(block) NAE_REG(block, 4, 0x03) /* #define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x04) #define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x05) */ #define XAUI_MAX_FRAME_LEN(block) NAE_REG(block, 4, 0x08) #define XAUI_REVISION_LVL(block) NAE_REG(block, 4, 0x0b) #define XAUI_MII_MGMT_CMD(block) NAE_REG(block, 4, 0x10) #define XAUI_MII_MGMT_FIELD(block) NAE_REG(block, 4, 0x11) #define XAUI_MII_MGMT_CFG(block) NAE_REG(block, 4, 0x12) #define XAUI_MIIM_LINK_FALL_VEC(block) NAE_REG(block, 4, 0x13) #define XAUI_MII_MGMT_IND(block) NAE_REG(block, 4, 0x14) #define XAUI_STATS_MLR(block) NAE_REG(block, 4, 0x1f) #define XAUI_STATS_TR64(block) NAE_REG(block, 4, 0x20) #define XAUI_STATS_TR127(block) NAE_REG(block, 4, 0x21) #define XAUI_STATS_TR255(block) NAE_REG(block, 4, 0x22) #define XAUI_STATS_TR511(block) NAE_REG(block, 4, 0x23) #define XAUI_STATS_TR1K(block) NAE_REG(block, 4, 0x24) #define XAUI_STATS_TRMAX(block) NAE_REG(block, 4, 0x25) #define XAUI_STATS_TRMGV(block) NAE_REG(block, 4, 0x26) #define XAUI_STATS_RBYT(block) NAE_REG(block, 4, 0x27) #define XAUI_STATS_RPKT(block) NAE_REG(block, 4, 0x28) #define XAUI_STATS_RFCS(block) NAE_REG(block, 4, 0x29) #define XAUI_STATS_RMCA(block) NAE_REG(block, 4, 0x2a) #define XAUI_STATS_RBCA(block) NAE_REG(block, 4, 0x2b) #define XAUI_STATS_RXCF(block) NAE_REG(block, 4, 0x2c) #define XAUI_STATS_RXPF(block) NAE_REG(block, 4, 0x2d) #define XAUI_STATS_RXUO(block) NAE_REG(block, 4, 0x2e) #define XAUI_STATS_RALN(block) NAE_REG(block, 4, 0x2f) #define XAUI_STATS_RFLR(block) NAE_REG(block, 4, 0x30) #define XAUI_STATS_RCDE(block) NAE_REG(block, 4, 0x31) #define XAUI_STATS_RCSE(block) NAE_REG(block, 4, 0x32) #define XAUI_STATS_RUND(block) NAE_REG(block, 4, 0x33) #define XAUI_STATS_ROVR(block) NAE_REG(block, 4, 0x34) #define XAUI_STATS_RFRG(block) NAE_REG(block, 4, 0x35) #define XAUI_STATS_RJBR(block) NAE_REG(block, 4, 0x36) #define XAUI_STATS_TBYT(block) NAE_REG(block, 4, 0x38) #define XAUI_STATS_TPKT(block) NAE_REG(block, 4, 0x39) #define XAUI_STATS_TMCA(block) NAE_REG(block, 4, 0x3a) #define XAUI_STATS_TBCA(block) NAE_REG(block, 4, 0x3b) #define XAUI_STATS_TXPF(block) NAE_REG(block, 4, 0x3c) #define XAUI_STATS_TDFR(block) NAE_REG(block, 4, 0x3d) #define XAUI_STATS_TEDF(block) NAE_REG(block, 4, 0x3e) #define XAUI_STATS_TSCL(block) NAE_REG(block, 4, 0x3f) #define XAUI_STATS_TMCL(block) NAE_REG(block, 4, 0x40) #define XAUI_STATS_TLCL(block) NAE_REG(block, 4, 0x41) #define XAUI_STATS_TXCL(block) NAE_REG(block, 4, 0x42) #define XAUI_STATS_TNCL(block) NAE_REG(block, 4, 0x43) #define XAUI_STATS_TJBR(block) NAE_REG(block, 4, 0x46) #define XAUI_STATS_TFCS(block) NAE_REG(block, 4, 0x47) #define XAUI_STATS_TXCF(block) NAE_REG(block, 4, 0x48) #define XAUI_STATS_TOVR(block) NAE_REG(block, 4, 0x49) #define XAUI_STATS_TUND(block) NAE_REG(block, 4, 0x4a) #define XAUI_STATS_TFRG(block) NAE_REG(block, 4, 0x4b) #define XAUI_STATS_CAR1(block) NAE_REG(block, 4, 0x4c) #define XAUI_STATS_CAR2(block) NAE_REG(block, 4, 0x4d) #define XAUI_STATS_CAM1(block) NAE_REG(block, 4, 0x4e) #define XAUI_STATS_CAM2(block) NAE_REG(block, 4, 0x4f) #define XAUI_MAC_ADDR0_LO(block) NAE_REG(block, 4, 0x50) #define XAUI_MAC_ADDR0_HI(block) NAE_REG(block, 4, 0x51) #define XAUI_MAC_ADDR1_LO(block) NAE_REG(block, 4, 0x52) #define XAUI_MAC_ADDR1_HI(block) NAE_REG(block, 4, 0x53) #define XAUI_MAC_ADDR2_LO(block) NAE_REG(block, 4, 0x54) #define XAUI_MAC_ADDR2_HI(block) NAE_REG(block, 4, 0x55) #define XAUI_MAC_ADDR3_LO(block) NAE_REG(block, 4, 0x56) #define XAUI_MAC_ADDR3_HI(block) NAE_REG(block, 4, 0x57) #define XAUI_MAC_ADDR_MASK0_LO(block) NAE_REG(block, 4, 0x58) #define XAUI_MAC_ADDR_MASK0_HI(block) NAE_REG(block, 4, 0x59) #define XAUI_MAC_ADDR_MASK1_LO(block) NAE_REG(block, 4, 0x5a) #define XAUI_MAC_ADDR_MASK1_HI(block) NAE_REG(block, 4, 0x5b) #define XAUI_MAC_FILTER_CFG(block) NAE_REG(block, 4, 0x5c) #define XAUI_HASHTBL_VEC_B31_0(block) NAE_REG(block, 4, 0x60) #define XAUI_HASHTBL_VEC_B63_32(block) NAE_REG(block, 4, 0x61) #define XAUI_HASHTBL_VEC_B95_64(block) NAE_REG(block, 4, 0x62) #define XAUI_HASHTBL_VEC_B127_96(block) NAE_REG(block, 4, 0x63) #define XAUI_HASHTBL_VEC_B159_128(block) NAE_REG(block, 4, 0x64) #define XAUI_HASHTBL_VEC_B191_160(block) NAE_REG(block, 4, 0x65) #define XAUI_HASHTBL_VEC_B223_192(block) NAE_REG(block, 4, 0x66) #define XAUI_HASHTBL_VEC_B255_224(block) NAE_REG(block, 4, 0x67) #define XAUI_HASHTBL_VEC_B287_256(block) NAE_REG(block, 4, 0x68) #define XAUI_HASHTBL_VEC_B319_288(block) NAE_REG(block, 4, 0x69) #define XAUI_HASHTBL_VEC_B351_320(block) NAE_REG(block, 4, 0x6a) #define XAUI_HASHTBL_VEC_B383_352(block) NAE_REG(block, 4, 0x6b) #define XAUI_HASHTBL_VEC_B415_384(block) NAE_REG(block, 4, 0x6c) #define XAUI_HASHTBL_VEC_B447_416(block) NAE_REG(block, 4, 0x6d) #define XAUI_HASHTBL_VEC_B479_448(block) NAE_REG(block, 4, 0x6e) #define XAUI_HASHTBL_VEC_B511_480(block) NAE_REG(block, 4, 0x6f) #define XAUI_NETIOR_XGMAC_MISC0(block) NAE_REG(block, 4, 0x76) #define XAUI_NETIOR_RX_ABORT_DROP_COUNT(block) NAE_REG(block, 4, 0x77) #define XAUI_NETIOR_MACCTRL_PAUSE_QUANTA(block) NAE_REG(block, 4, 0x78) #define XAUI_NETIOR_MACCTRL_OPCODE(block) NAE_REG(block, 4, 0x79) #define XAUI_NETIOR_MAC_DA_H(block) NAE_REG(block, 4, 0x7a) #define XAUI_NETIOR_MAC_DA_L(block) NAE_REG(block, 4, 0x7b) #define XAUI_NETIOR_XGMAC_STAT(block) NAE_REG(block, 4, 0x7c) #define XAUI_NETIOR_XGMAC_CTRL3(block) NAE_REG(block, 4, 0x7d) #define XAUI_NETIOR_XGMAC_CTRL2(block) NAE_REG(block, 4, 0x7e) #define XAUI_NETIOR_XGMAC_CTRL1(block) NAE_REG(block, 4, 0x7f) #define LANE_RX_CLK (1 << 0) #define LANE_TX_CLK (1 << 6) #define XAUI_LANE_FAULT 0x400 #define XAUI_CONFIG_0 0 #define XAUI_CONFIG_MACRST 0x80000000 #define XAUI_CONFIG_RSTRCTL 0x00400000 #define XAUI_CONFIG_RSTRFN 0x00200000 #define XAUI_CONFIG_RSTTCTL 0x00040000 #define XAUI_CONFIG_RSTTFN 0x00020000 #define XAUI_CONFIG_RSTMIIM 0x00010000 #define XAUI_CONFIG_1 1 #define XAUI_CONFIG_TCTLEN 0x80000000 #define XAUI_CONFIG_TFEN 0x40000000 #define XAUI_CONFIG_RCTLEN 0x20000000 #define XAUI_CONFIG_RFEN 0x10000000 #define XAUI_CONFIG_DRPLT64 0x00000020 #define XAUI_CONFIG_LENCHK 0x00000008 #define XAUI_CONFIG_GENFCS 0x00000004 #define XAUI_CONFIG_PAD_0 0x00000000 #define XAUI_CONFIG_PAD_64 0x00000001 #define XAUI_CONFIG_PAD_COND 0x00000002 #define XAUI_CONFIG_PAD_68 0x00000003 #define XAUI_PHY_CTRL_1 0x00 #define NETIOR_XGMAC_CTRL1 0x7F #define NETIOR_XGMAC_CTRL3 0x7D #define NETIOR_XGMAC_VLAN_DC_POS 28 #define NETIOR_XGMAC_PHYADDR_POS 23 #define NETIOR_XGMAC_DEVID_POS 18 #define NETIOR_XGMAC_STATS_EN_POS 17 #define NETIOR_XGMAC_TX_PFC_EN_POS 14 #define NETIOR_XGMAC_RX_PFC_EN_POS 13 #define NETIOR_XGMAC_SOFT_RST_POS 11 #define NETIOR_XGMAC_TX_PAUSE_POS 10 #define NETIOR_XGMAC_STATS_CLR_POS 16 #if !defined(LOCORE) && !defined(__ASSEMBLY__) void nlm_xaui_pcs_init(uint64_t, int); void nlm_nae_setup_rx_mode_xaui(uint64_t, int, int, int, int, int, int, int); void nlm_nae_setup_mac_addr_xaui(uint64_t, int, int, int, unsigned char *); void nlm_config_xaui_mtu(uint64_t, int, int, int); void nlm_config_xaui(uint64_t, int, int, int, int); #endif /* !(LOCORE) && !(__ASSEMBLY__) */ #endif Index: head/sys/mips/nlm/interrupt.h =================================================================== --- head/sys/mips/nlm/interrupt.h (revision 279386) +++ head/sys/mips/nlm/interrupt.h (revision 279387) @@ -1,74 +1,74 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef _RMI_INTERRUPT_H_ #define _RMI_INTERRUPT_H_ /* Defines for the IRQ numbers */ #define IRQ_IPI 41 /* 8-39 are used by PIC interrupts */ #define IRQ_MSGRING 6 #define IRQ_TIMER 7 #define PIC_IRQ_BASE 8 #define PIC_IRT_LAST_IRQ 39 #define XLP_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \ (irq) <= PIC_IRT_LAST_IRQ) #define PIC_UART_0_IRQ 17 #define PIC_UART_1_IRQ 18 #define PIC_PCIE_0_IRQ 19 #define PIC_PCIE_1_IRQ 20 #define PIC_PCIE_2_IRQ 21 #define PIC_PCIE_3_IRQ 22 #define PIC_PCIE_IRQ(l) (PIC_PCIE_0_IRQ + (l)) #define PIC_USB_0_IRQ 23 #define PIC_USB_1_IRQ 24 #define PIC_USB_2_IRQ 25 #define PIC_USB_3_IRQ 26 #define PIC_USB_4_IRQ 27 #define PIC_USB_IRQ(n) (PIC_USB_0_IRQ + (n)) #define PIC_MMC_IRQ 29 #define PIC_I2C_0_IRQ 30 #define PIC_I2C_1_IRQ 31 #define PIC_I2C_IRQ(n) (PIC_I2C_0_IRQ + (n)) /* * XLR needs custom pre and post handlers for PCI/PCI-e interrupts * XXX: maybe follow i386 intsrc model */ void xlp_enable_irq(int irq); void xlp_set_bus_ack(int irq, void (*ack)(int, void *), void *arg); #endif /* _RMI_INTERRUPT_H_ */ Index: head/sys/mips/nlm/intr_machdep.c =================================================================== --- head/sys/mips/nlm/intr_machdep.c (revision 279386) +++ head/sys/mips/nlm/intr_machdep.c (revision 279387) @@ -1,340 +1,340 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include struct xlp_intrsrc { void (*bus_ack)(int, void *); /* Additional ack */ void *bus_ack_arg; /* arg for additional ack */ struct intr_event *ie; /* event corresponding to intr */ int irq; int irt; }; - + static struct xlp_intrsrc xlp_interrupts[XLR_MAX_INTR]; static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR]; static int intrcnt_index; int xlp_irq_to_irt(int irq) { uint32_t offset; switch (irq) { case PIC_UART_0_IRQ: case PIC_UART_1_IRQ: offset = XLP_IO_UART_OFFSET(0, irq - PIC_UART_0_IRQ); return (xlp_socdev_irt(offset)); case PIC_PCIE_0_IRQ: case PIC_PCIE_1_IRQ: case PIC_PCIE_2_IRQ: case PIC_PCIE_3_IRQ: offset = XLP_IO_PCIE_OFFSET(0, irq - PIC_PCIE_0_IRQ); return (xlp_socdev_irt(offset)); case PIC_USB_0_IRQ: case PIC_USB_1_IRQ: case PIC_USB_2_IRQ: case PIC_USB_3_IRQ: case PIC_USB_4_IRQ: offset = XLP_IO_USB_OFFSET(0, irq - PIC_USB_0_IRQ); return (xlp_socdev_irt(offset)); case PIC_I2C_0_IRQ: case PIC_I2C_1_IRQ: offset = XLP_IO_I2C0_OFFSET(0); return (xlp_socdev_irt(offset) + irq - PIC_I2C_0_IRQ); default: printf("ERROR: %s: unknown irq %d\n", __func__, irq); return (-1); } } void xlp_enable_irq(int irq) { uint64_t eimr; eimr = nlm_read_c0_eimr(); nlm_write_c0_eimr(eimr | (1ULL << irq)); } void cpu_establish_softintr(const char *name, driver_filter_t * filt, void (*handler) (void *), void *arg, int irq, int flags, void **cookiep) { panic("Soft interrupts unsupported!\n"); } static void xlp_post_filter(void *source) { struct xlp_intrsrc *src = source; - + if (src->bus_ack) src->bus_ack(src->irq, src->bus_ack_arg); nlm_pic_ack(xlp_pic_base, src->irt); } static void xlp_pre_ithread(void *source) { struct xlp_intrsrc *src = source; if (src->bus_ack) src->bus_ack(src->irq, src->bus_ack_arg); } static void xlp_post_ithread(void *source) { struct xlp_intrsrc *src = source; nlm_pic_ack(xlp_pic_base, src->irt); } void xlp_set_bus_ack(int irq, void (*ack)(int, void *), void *arg) { struct xlp_intrsrc *src; KASSERT(irq > 0 && irq <= XLR_MAX_INTR, ("%s called for bad hard intr %d", __func__, irq)); /* no locking needed - this will called early in boot */ src = &xlp_interrupts[irq]; KASSERT(src->ie != NULL, ("%s called after IRQ enable for %d.", __func__, irq)); src->bus_ack_arg = arg; src->bus_ack = ack; } void cpu_establish_hardintr(const char *name, driver_filter_t * filt, void (*handler) (void *), void *arg, int irq, int flags, void **cookiep) { struct intr_event *ie; /* descriptor for the IRQ */ struct xlp_intrsrc *src = NULL; int errcode; KASSERT(irq > 0 && irq <= XLR_MAX_INTR , ("%s called for bad hard intr %d", __func__, irq)); /* * Locking - not needed now, because we do this only on * startup from CPU0 */ src = &xlp_interrupts[irq]; ie = src->ie; if (ie == NULL) { /* * PIC based interrupts need ack in PIC, and some SoC * components need additional acks (e.g. PCI) */ if (XLP_IRQ_IS_PICINTR(irq)) errcode = intr_event_create(&ie, src, 0, irq, xlp_pre_ithread, xlp_post_ithread, xlp_post_filter, NULL, "hard intr%d:", irq); else { if (filt == NULL) panic("Unsupported non filter percpu intr %d", irq); errcode = intr_event_create(&ie, src, 0, irq, NULL, NULL, NULL, NULL, "hard intr%d:", irq); } if (errcode) { printf("Could not create event for intr %d\n", irq); return; } src->irq = irq; src->ie = ie; } if (XLP_IRQ_IS_PICINTR(irq)) { /* Set all irqs to CPU 0 for now */ src->irt = xlp_irq_to_irt(irq); nlm_pic_write_irt_direct(xlp_pic_base, src->irt, 1, 0, PIC_LOCAL_SCHEDULING, irq, 0); } intr_event_add_handler(ie, name, filt, handler, arg, intr_priority(flags), flags, cookiep); xlp_enable_irq(irq); } void cpu_intr(struct trapframe *tf) { struct intr_event *ie; uint64_t eirr, eimr; int i; critical_enter(); /* find a list of enabled interrupts */ eirr = nlm_read_c0_eirr(); eimr = nlm_read_c0_eimr(); eirr &= eimr; - - if (eirr == 0) { + + if (eirr == 0) { critical_exit(); return; } /* * No need to clear the EIRR here as the handler writes to * compare which ACKs the interrupt. */ if (eirr & (1 << IRQ_TIMER)) { intr_event_handle(xlp_interrupts[IRQ_TIMER].ie, tf); critical_exit(); return; } - + /* FIXME sched pin >? LOCK>? */ for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) { if ((eirr & (1ULL << i)) == 0) continue; ie = xlp_interrupts[i].ie; /* Don't account special IRQs */ switch (i) { case IRQ_IPI: case IRQ_MSGRING: break; default: mips_intrcnt_inc(mips_intr_counters[i]); } /* Ack the IRQ on the CPU */ nlm_write_c0_eirr(1ULL << i); if (intr_event_handle(ie, tf) != 0) { printf("stray interrupt %d\n", i); } } critical_exit(); } void mips_intrcnt_setname(mips_intrcnt_t counter, const char *name) { int idx = counter - intrcnt; KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter")); snprintf(intrnames + (MAXCOMLEN + 1) * idx, MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name); } mips_intrcnt_t mips_intrcnt_create(const char* name) { mips_intrcnt_t counter = &intrcnt[intrcnt_index++]; mips_intrcnt_setname(counter, name); return counter; } void cpu_init_interrupts() { int i; char name[MAXCOMLEN + 1]; /* * Initialize all available vectors so spare IRQ - * would show up in systat output + * would show up in systat output */ for (i = 0; i < XLR_MAX_INTR; i++) { snprintf(name, MAXCOMLEN + 1, "int%d:", i); mips_intr_counters[i] = mips_intrcnt_create(name); } } static int xlp_pic_probe(device_t); static int xlp_pic_attach(device_t); static int xlp_pic_probe(device_t dev) { if (!ofw_bus_is_compatible(dev, "netlogic,xlp-pic")) return (ENXIO); device_set_desc(dev, "XLP PIC"); return (0); } static int xlp_pic_attach(device_t dev) { return (0); } static device_method_t xlp_pic_methods[] = { DEVMETHOD(device_probe, xlp_pic_probe), DEVMETHOD(device_attach, xlp_pic_attach), DEVMETHOD_END }; static driver_t xlp_pic_driver = { "xlp_pic", xlp_pic_methods, 1, /* no softc */ }; static devclass_t xlp_pic_devclass; DRIVER_MODULE(xlp_pic, simplebus, xlp_pic_driver, xlp_pic_devclass, 0, 0); Index: head/sys/mips/nlm/mpreset.S =================================================================== --- head/sys/mips/nlm/mpreset.S (revision 279386) +++ head/sys/mips/nlm/mpreset.S (revision 279387) @@ -1,201 +1,201 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #include #include #include #include #include #include #define SYS_REG_KSEG1(node, reg) (0xa0000000 + XLP_DEFAULT_IO_BASE + \ XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + (reg) * 4) #include "assym.s" .text .set noat .set noreorder .set mips64 #define MFCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x18)) #define MTCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x19)) /* * We need to do this to really flush the dcache before splitting it */ .macro flush_l1_dcache .set push .set noreorder li $8, LSU_DEBUG_DATA0 /* use register number to handle */ li $9, LSU_DEBUG_ADDR /* different ABIs */ li t2, 0 /* index */ li t3, 0x1000 /* loop count, 512 sets * 8 whatever? */ 1: sll v0, t2, 5 MTCR(0, 8) ori v1, v0, 0x3 /* way0 | write_enable | write_active */ MTCR(3, 9) 2: MFCR(3, 9) andi v1, 0x1 /* wait for write_active == 0 */ bnez v1, 2b nop MTCR(0, 8) ori v1, v0, 0x7 /* way1 | write_enable | write_active */ MTCR(3, 9) 3: MFCR(3, 9) andi v1, 0x1 /* wait for write_active == 0 */ bnez v1, 3b nop addi t2, 1 bne t3, t2, 1b nop .set pop .endm VECTOR(XLPResetEntry, unknown) mfc0 t0, MIPS_COP_0_STATUS li t1, 0x80000 and t1, t0, t1 bnez t1, nmi_handler nop #ifdef SMP /* Reset entry for secordary cores */ mfc0 t0, MIPS_COP_0_PRID, 1 srl t0, t0, 2 /* discard thread id */ andi t0, t0, 0x7 /* core id */ li t1, 1 sll t0, t1, t0 nor t0, t0, zero /* mask with core id bit clear */ /* clear CPU non-coherent bit */ li t2, SYS_REG_KSEG1(0, SYS_CPU_NONCOHERENT_MODE) lw t1, 0(t2) and t1, t1, t0 sw t1, 0(t2) lw t1, 0(t2) /* read-back ensures operation complete */ sync dla t2, mpentry jr t2 nop #endif nop /* NOT REACHED */ VECTOR_END(XLPResetEntry) /* Not yet */ nmi_handler: nop nop j nmi_handler #ifdef SMP /* * Enable other threads in the core, called from thread 0 * of the core - */ + */ LEAF(xlp_enable_threads) /* * Save and restore callee saved registers of all ABIs * Enabling threads trashes the registers */ dmtc0 sp, $4, 2 /* SP saved in UserLocal */ ori sp, sp, 0x7 xori sp, sp, 0x7 /* align 64 bit */ addiu sp, sp, -128 mfc0 t1, MIPS_COP_0_STATUS sd s0, 0(sp) sd s1, 8(sp) sd s2, 16(sp) sd s3, 24(sp) sd s4, 32(sp) sd s5, 40(sp) sd s6, 48(sp) sd s7, 56(sp) sd s8, 64(sp) sd t1, 72(sp) sd gp, 80(sp) sd ra, 88(sp) flush_l1_dcache /* Use register number to work in o32 and n32 */ li $9, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) - move $8, a0 + move $8, a0 sync MTCR(8, 9) mfc0 t0, MIPS_COP_0_PRID, 1 andi t0, 0x3 beqz t0, 2f nop dla t1, mpentry /* child thread, go to hardware init */ jr t1 nop -2: /* +2: /* * Parent hardware thread, restore registers, return */ #if 1 /* * A0 Errata - Write MMU_SETUP after changing thread mode register. */ li $9, 0x400 li $8, 0 MTCR(8, 9) sll zero,3 /* ehb */ #endif dmfc0 t0, $4, 2 /* SP saved in UserLocal */ ori sp, t0, 0x7 xori sp, sp, 0x7 /* align 64 bit */ addiu sp, sp, -128 ld s0, 0(sp) ld s1, 8(sp) ld s2, 16(sp) ld s3, 24(sp) ld s4, 32(sp) ld s5, 40(sp) ld s6, 48(sp) ld s7, 56(sp) ld s8, 64(sp) ld t1, 72(sp) ld gp, 80(sp) ld ra, 88(sp) mfc0 t1, MIPS_COP_0_STATUS move sp, t0 /* Restore the real SP */ jr.hb ra nop END(xlp_enable_threads) #endif Index: head/sys/mips/nlm/msgring.h =================================================================== --- head/sys/mips/nlm/msgring.h (revision 279386) +++ head/sys/mips/nlm/msgring.h (revision 279387) @@ -1,52 +1,52 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef _NLM_MSGRING_H #define _NLM_MSGRING_H #define CMS_DEFAULT_CREDIT 50 /* * packets are sent to VC 0 of a thread * freebacks are sent to VC 3 of a thread */ #define XLPGE_RX_VC 0 #define XLPGE_FB_VC 3 extern uint32_t xlp_msg_thread_mask; struct nlm_fmn_msg; typedef void (*msgring_handler)(int, int, int, int, struct nlm_fmn_msg *, void *); int register_msgring_handler(int startb, int endb, msgring_handler action, void *arg); int xlp_handle_msg_vc(u_int vcmask, int max_msgs); void xlp_msgring_cpu_init(int, int, int); void xlp_cms_enable_intr(int , int , int , int); #endif /* _NLM_MSGRING_H */ Index: head/sys/mips/nlm/tick.c =================================================================== --- head/sys/mips/nlm/tick.c (revision 279386) +++ head/sys/mips/nlm/tick.c (revision 279387) @@ -1,383 +1,383 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ /* * Simple driver for the 32-bit interval counter built in to all * MIPS32 CPUs. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include uint64_t counter_freq; struct timecounter *platform_timecounter; static DPCPU_DEFINE(uint32_t, cycles_per_tick); static uint32_t cycles_per_usec; static DPCPU_DEFINE(volatile uint32_t, counter_upper); static DPCPU_DEFINE(volatile uint32_t, counter_lower_last); static DPCPU_DEFINE(uint32_t, compare_ticks); static DPCPU_DEFINE(uint32_t, lost_ticks); struct clock_softc { int intr_rid; struct resource *intr_res; void *intr_handler; struct timecounter tc; struct eventtimer et; }; static struct clock_softc *softc; /* * Device methods */ static int clock_probe(device_t); static void clock_identify(driver_t *, device_t); static int clock_attach(device_t); static unsigned counter_get_timecount(struct timecounter *tc); -void +void mips_timer_early_init(uint64_t clock_hz) { /* Initialize clock early so that we can use DELAY sooner */ counter_freq = clock_hz; cycles_per_usec = (clock_hz / (1000 * 1000)); } void platform_initclocks(void) { if (platform_timecounter != NULL) tc_init(platform_timecounter); } static uint64_t tick_ticker(void) { uint64_t ret; uint32_t ticktock; uint32_t t_lower_last, t_upper; /* * Disable preemption because we are working with cpu specific data. */ critical_enter(); /* * Note that even though preemption is disabled, interrupts are * still enabled. In particular there is a race with clock_intr() * reading the values of 'counter_upper' and 'counter_lower_last'. * * XXX this depends on clock_intr() being executed periodically * so that 'counter_upper' and 'counter_lower_last' are not stale. */ do { t_upper = DPCPU_GET(counter_upper); t_lower_last = DPCPU_GET(counter_lower_last); } while (t_upper != DPCPU_GET(counter_upper)); ticktock = mips_rd_count(); critical_exit(); /* COUNT register wrapped around */ if (ticktock < t_lower_last) t_upper++; ret = ((uint64_t)t_upper << 32) | ticktock; return (ret); } void mips_timer_init_params(uint64_t platform_counter_freq, int double_count) { /* * XXX: Do not use printf here: uart code 8250 may use DELAY so this * function should be called before cninit. */ counter_freq = platform_counter_freq; /* * XXX: Some MIPS32 cores update the Count register only every two * pipeline cycles. * We know this because of status registers in CP0, make it automatic. */ if (double_count != 0) counter_freq /= 2; cycles_per_usec = counter_freq / (1 * 1000 * 1000); set_cputicker(tick_ticker, counter_freq, 1); } static int sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS) { int error; uint64_t freq; if (softc == NULL) return (EOPNOTSUPP); freq = counter_freq; error = sysctl_handle_64(oidp, &freq, sizeof(freq), req); if (error == 0 && req->newptr != NULL) { counter_freq = freq; softc->et.et_frequency = counter_freq; softc->tc.tc_frequency = counter_freq; } return (error); } SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW, NULL, 0, sysctl_machdep_counter_freq, "QU", "Timecounter frequency in Hz"); static unsigned counter_get_timecount(struct timecounter *tc) { return (mips_rd_count()); } /* * Wait for about n microseconds (at least!). */ void DELAY(int n) { uint32_t cur, last, delta, usecs; /* * This works by polling the timer and counting the number of * microseconds that go by. */ last = mips_rd_count(); delta = usecs = 0; while (n > usecs) { cur = mips_rd_count(); /* Check to see if the timer has wrapped around. */ if (cur < last) delta += cur + (0xffffffff - last) + 1; else delta += cur - last; last = cur; if (delta >= cycles_per_usec) { usecs += delta / cycles_per_usec; delta %= cycles_per_usec; } } } static int clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period) { uint32_t fdiv, div, next; if (period != 0) div = (et->et_frequency * period) >> 32; else div = 0; if (first != 0) fdiv = (et->et_frequency * first) >> 32; else fdiv = div; DPCPU_SET(cycles_per_tick, div); next = mips_rd_count() + fdiv; DPCPU_SET(compare_ticks, next); mips_wr_compare(next); return (0); } static int clock_stop(struct eventtimer *et) { DPCPU_SET(cycles_per_tick, 0); mips_wr_compare(0xffffffff); return (0); } /* * Device section of file below */ static int clock_intr(void *arg) { struct clock_softc *sc = (struct clock_softc *)arg; uint32_t cycles_per_tick; uint32_t count, compare_last, compare_next, lost_ticks; cycles_per_tick = DPCPU_GET(cycles_per_tick); /* * Set next clock edge. */ count = mips_rd_count(); compare_last = DPCPU_GET(compare_ticks); if (cycles_per_tick > 0) { compare_next = count + cycles_per_tick; DPCPU_SET(compare_ticks, compare_next); mips_wr_compare(compare_next); } else /* In one-shot mode timer should be stopped after the event. */ mips_wr_compare(0xffffffff); /* COUNT register wrapped around */ if (count < DPCPU_GET(counter_lower_last)) { DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1); } DPCPU_SET(counter_lower_last, count); if (cycles_per_tick > 0) { /* * Account for the "lost time" between when the timer interrupt * fired and when 'clock_intr' actually started executing. */ lost_ticks = DPCPU_GET(lost_ticks); lost_ticks += count - compare_last; - + /* * If the COUNT and COMPARE registers are no longer in sync * then make up some reasonable value for the 'lost_ticks'. * * This could happen, for e.g., after we resume normal * operations after exiting the debugger. */ if (lost_ticks > 2 * cycles_per_tick) lost_ticks = cycles_per_tick; while (lost_ticks >= cycles_per_tick) { if (sc->et.et_active) sc->et.et_event_cb(&sc->et, sc->et.et_arg); lost_ticks -= cycles_per_tick; } DPCPU_SET(lost_ticks, lost_ticks); } if (sc->et.et_active) sc->et.et_event_cb(&sc->et, sc->et.et_arg); return (FILTER_HANDLED); } static int clock_probe(device_t dev) { device_set_desc(dev, "Generic MIPS32 ticker"); return (BUS_PROBE_NOWILDCARD); } static void clock_identify(driver_t * drv, device_t parent) { BUS_ADD_CHILD(parent, 0, "clock", 0); } static int clock_attach(device_t dev) { struct clock_softc *sc; if (device_get_unit(dev) != 0) panic("can't attach more clocks"); softc = sc = device_get_softc(dev); cpu_establish_hardintr("compare", clock_intr, NULL, sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler); sc->tc.tc_get_timecount = counter_get_timecount; sc->tc.tc_counter_mask = 0xffffffff; sc->tc.tc_frequency = counter_freq; sc->tc.tc_name = "MIPS32"; sc->tc.tc_quality = 800; sc->tc.tc_priv = sc; tc_init(&sc->tc); sc->et.et_name = "MIPS32"; #if 0 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; #endif sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_PERCPU; sc->et.et_quality = 800; sc->et.et_frequency = counter_freq; sc->et.et_min_period = 0x00004000LLU; /* To be safe. */ sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; sc->et.et_start = clock_start; sc->et.et_stop = clock_stop; sc->et.et_priv = sc; et_register(&sc->et); return (0); } static device_method_t clock_methods[] = { /* Device interface */ DEVMETHOD(device_probe, clock_probe), DEVMETHOD(device_identify, clock_identify), DEVMETHOD(device_attach, clock_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), {0, 0} }; static driver_t clock_driver = { "clock", clock_methods, sizeof(struct clock_softc), }; static devclass_t clock_devclass; DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0); Index: head/sys/mips/nlm/uart_cpu_xlp.c =================================================================== --- head/sys/mips/nlm/uart_cpu_xlp.c (revision 279386) +++ head/sys/mips/nlm/uart_cpu_xlp.c (revision 279387) @@ -1,95 +1,95 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ /* * Skeleton of this file was based on respective code for ARM * code written by Olivier Houchard. */ /* * XLRMIPS: This file is hacked from arm/... */ #include "opt_platform.h" #ifndef FDT /* use FDT uart when fdt is enable */ #include "opt_uart.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; int uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) { return (b1->bsh == b2->bsh && b1->bst == b2->bst); } int uart_cpu_getdev(int devtype, struct uart_devinfo *di) { di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; di->bas.bst = rmi_uart_bus_space; di->bas.bsh = nlm_get_uart_regbase(0, BOARD_CONSOLE_UART); - + di->bas.regshft = 2; /* divisor = rclk / (baudrate * 16); */ di->bas.rclk = XLP_IO_CLK; di->baudrate = BOARD_CONSOLE_SPEED; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; uart_bus_space_io = NULL; uart_bus_space_mem = rmi_uart_bus_space; return (0); } #endif Index: head/sys/mips/nlm/usb_init.c =================================================================== --- head/sys/mips/nlm/usb_init.c (revision 279386) +++ head/sys/mips/nlm/usb_init.c (revision 279387) @@ -1,91 +1,91 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include static void nlm_usb_intr_en(int node, int port) { uint32_t val; uint64_t port_addr; - port_addr = nlm_get_usb_regbase(node, port); + port_addr = nlm_get_usb_regbase(node, port); val = nlm_read_usb_reg(port_addr, USB_INT_EN); - val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | + val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN; nlm_write_usb_reg(port_addr, USB_INT_EN, val); } -static void +static void nlm_usb_hw_reset(int node, int port) { uint64_t port_addr; uint32_t val; - + /* reset USB phy */ - port_addr = nlm_get_usb_regbase(node, port); + port_addr = nlm_get_usb_regbase(node, port); val = nlm_read_usb_reg(port_addr, USB_PHY_0); val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1); nlm_write_usb_reg(port_addr, USB_PHY_0, val); - + DELAY(100); val = nlm_read_usb_reg(port_addr, USB_CTL_0); val &= ~(USB_CONTROLLER_RESET); val |= 0x4; nlm_write_usb_reg(port_addr, USB_CTL_0, val); } -static void +static void nlm_usb_init(void) { /* XXX: should be checking if these are in Device mode here */ printf("Initialize USB Interface\n"); - nlm_usb_hw_reset(0, 0); - nlm_usb_hw_reset(0, 3); + nlm_usb_hw_reset(0, 0); + nlm_usb_hw_reset(0, 3); /* Enable PHY interrupts */ - nlm_usb_intr_en(0, 0); - nlm_usb_intr_en(0, 3); + nlm_usb_intr_en(0, 0); + nlm_usb_intr_en(0, 3); } SYSINIT(nlm_usb_init, SI_SUB_CPU, SI_ORDER_MIDDLE, nlm_usb_init, NULL); Index: head/sys/mips/nlm/xlp.h =================================================================== --- head/sys/mips/nlm/xlp.h (revision 279386) +++ head/sys/mips/nlm/xlp.h (revision 279387) @@ -1,137 +1,137 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD * $FreeBSD$ */ #ifndef __NLM_XLP_H__ #define __NLM_XLP_H__ #include #include /* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */ #define CHIP_PROCESSOR_ID_XLP_8XX 0x10 #define CHIP_PROCESSOR_ID_XLP_3XX 0x11 #define CHIP_PROCESSOR_ID_XLP_416 0x94 #define CHIP_PROCESSOR_ID_XLP_432 0x14 /* Revision id's */ #define XLP_REVISION_A0 0x00 #define XLP_REVISION_A1 0x01 #define XLP_REVISION_A2 0x02 #define XLP_REVISION_B0 0x03 #define XLP_REVISION_B1 0x04 #ifndef LOCORE /* * FreeBSD can be started with few threads and cores turned off, * so have a hardware thread id to FreeBSD cpuid mapping. */ extern int xlp_ncores; extern int xlp_threads_per_core; extern uint32_t xlp_hw_thread_mask; extern int xlp_cpuid_to_hwtid[]; extern int xlp_hwtid_to_cpuid[]; #ifdef SMP extern void xlp_enable_threads(int code); #endif uint32_t xlp_get_cpu_frequency(int node, int core); int nlm_set_device_frequency(int node, int devtype, int frequency); int xlp_irq_to_irt(int irq); static __inline int nlm_processor_id(void) { return ((mips_rd_prid() >> 8) & 0xff); } static __inline int nlm_is_xlp3xx(void) { return (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_3XX); } static __inline int nlm_is_xlp3xx_ax(void) { uint32_t procid = mips_rd_prid(); int prid = (procid >> 8) & 0xff; int rev = procid & 0xff; return (prid == CHIP_PROCESSOR_ID_XLP_3XX && rev < XLP_REVISION_B0); } static __inline int nlm_is_xlp4xx(void) { int prid = nlm_processor_id(); return (prid == CHIP_PROCESSOR_ID_XLP_432 || prid == CHIP_PROCESSOR_ID_XLP_416); } static __inline int nlm_is_xlp8xx(void) { int prid = nlm_processor_id(); return (prid == CHIP_PROCESSOR_ID_XLP_8XX || prid == CHIP_PROCESSOR_ID_XLP_432 || prid == CHIP_PROCESSOR_ID_XLP_416); } static __inline int nlm_is_xlp8xx_ax(void) { uint32_t procid = mips_rd_prid(); int prid = (procid >> 8) & 0xff; int rev = procid & 0xff; return ((prid == CHIP_PROCESSOR_ID_XLP_8XX || prid == CHIP_PROCESSOR_ID_XLP_432 || prid == CHIP_PROCESSOR_ID_XLP_416) && (rev < XLP_REVISION_B0)); } static __inline int nlm_is_xlp8xx_b0(void) { uint32_t procid = mips_rd_prid(); int prid = (procid >> 8) & 0xff; int rev = procid & 0xff; return ((prid == CHIP_PROCESSOR_ID_XLP_8XX || prid == CHIP_PROCESSOR_ID_XLP_432 || prid == CHIP_PROCESSOR_ID_XLP_416) && rev == XLP_REVISION_B0); } static __inline int xlp_socdev_irt(uint32_t offset) { uint64_t base; base = nlm_pcicfg_base(offset); return (nlm_irtstart(base)); } #endif /* LOCORE */ #endif /* __NLM_XLP_H__ */ Index: head/sys/mips/nlm/xlp_machdep.c =================================================================== --- head/sys/mips/nlm/xlp_machdep.c (revision 279386) +++ head/sys/mips/nlm/xlp_machdep.c (revision 279387) @@ -1,737 +1,737 @@ /*- * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * NETLOGIC_BSD */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include /* cinit() */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #endif /* 4KB static data aread to keep a copy of the bootload env until the dynamic kenv is setup */ char boot1_env[4096]; uint64_t xlp_cpu_frequency; uint64_t xlp_io_base = MIPS_PHYS_TO_DIRECT_UNCACHED(XLP_DEFAULT_IO_BASE); int xlp_ncores; int xlp_threads_per_core; uint32_t xlp_hw_thread_mask; int xlp_cpuid_to_hwtid[MAXCPU]; int xlp_hwtid_to_cpuid[MAXCPU]; uint64_t xlp_pic_base; static int xlp_mmuval; extern uint32_t _end; extern char XLPResetEntry[], XLPResetEntryEnd[]; static void xlp_setup_core(void) { uint64_t reg; reg = nlm_mfcr(LSU_DEFEATURE); /* Enable Unaligned and L2HPE */ reg |= (1 << 30) | (1 << 23); /* * Experimental : Enable SUE * Speculative Unmap Enable. Enable speculative L2 cache request for * unmapped access. */ reg |= (1ull << 31); /* Clear S1RCM - A0 errata */ reg &= ~0xeull; nlm_mtcr(LSU_DEFEATURE, reg); reg = nlm_mfcr(SCHED_DEFEATURE); /* Experimental: Disable BRU accepting ALU ops - A0 errata */ reg |= (1 << 24); nlm_mtcr(SCHED_DEFEATURE, reg); } -static void +static void xlp_setup_mmu(void) { uint32_t pagegrain; if (nlm_threadid() == 0) { nlm_setup_extended_pagemask(0); nlm_large_variable_tlb_en(1); nlm_extended_tlb_en(1); nlm_mmu_setup(0, 0, 0); } /* Enable no-read, no-exec, large-physical-address */ pagegrain = mips_rd_pagegrain(); pagegrain |= (1U << 31) | /* RIE */ (1 << 30) | /* XIE */ (1 << 29); /* ELPA */ mips_wr_pagegrain(pagegrain); } static void xlp_enable_blocks(void) { uint64_t sysbase; int i; for (i = 0; i < XLP_MAX_NODES; i++) { if (!nlm_dev_exists(XLP_IO_SYS_OFFSET(i))) continue; sysbase = nlm_get_sys_regbase(i); nlm_sys_enable_block(sysbase, DFS_DEVICE_RSA); } } static void xlp_parse_mmu_options(void) { uint64_t sysbase; uint32_t cpu_map = xlp_hw_thread_mask; uint32_t core0_thr_mask, core_thr_mask, cpu_rst_mask; int i, j, k; #ifdef SMP if (cpu_map == 0) cpu_map = 0xffffffff; #else /* Uniprocessor! */ if (cpu_map == 0) cpu_map = 0x1; else if (cpu_map != 0x1) { printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n" "WARNING: Other CPUs will be unused.\n", (u_long)cpu_map); cpu_map = 0x1; } #endif xlp_ncores = 1; core0_thr_mask = cpu_map & 0xf; switch (core0_thr_mask) { case 1: xlp_threads_per_core = 1; xlp_mmuval = 0; - break; + break; case 3: xlp_threads_per_core = 2; xlp_mmuval = 2; - break; - case 0xf: + break; + case 0xf: xlp_threads_per_core = 4; xlp_mmuval = 3; - break; + break; default: goto unsupp; } /* Try to find the enabled cores from SYS block */ sysbase = nlm_get_sys_regbase(0); cpu_rst_mask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET) & 0xff; /* XLP 416 does not report this correctly, fix */ if (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_416) cpu_rst_mask = 0xe; /* Take out cores which do not exist on chip */ for (i = 1; i < XLP_MAX_CORES; i++) { if ((cpu_rst_mask & (1 << i)) == 0) cpu_map &= ~(0xfu << (4 * i)); } - /* Verify other cores' CPU masks */ + /* Verify other cores' CPU masks */ for (i = 1; i < XLP_MAX_CORES; i++) { core_thr_mask = (cpu_map >> (4 * i)) & 0xf; if (core_thr_mask == 0) - continue; + continue; if (core_thr_mask != core0_thr_mask) - goto unsupp; + goto unsupp; xlp_ncores++; } xlp_hw_thread_mask = cpu_map; /* setup hardware processor id to cpu id mapping */ for (i = 0; i< MAXCPU; i++) - xlp_cpuid_to_hwtid[i] = + xlp_cpuid_to_hwtid[i] = xlp_hwtid_to_cpuid[i] = -1; for (i = 0, k = 0; i < XLP_MAX_CORES; i++) { if (((cpu_map >> (i * 4)) & 0xf) == 0) continue; for (j = 0; j < xlp_threads_per_core; j++) { xlp_cpuid_to_hwtid[k] = i * 4 + j; xlp_hwtid_to_cpuid[i * 4 + j] = k; k++; } } return; unsupp: printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n" "\tcore0 thread mask [%lx], boot cpu mask [%lx].\n", (u_long)core0_thr_mask, (u_long)cpu_map); panic("Invalid CPU mask - halting.\n"); return; } /* Parse cmd line args as env - copied from ar71xx */ static void xlp_parse_bootargs(char *cmdline) { char *n, *v; while ((v = strsep(&cmdline, " \n")) != NULL) { if (*v == '\0') continue; if (*v == '-') { while (*v != '\0') { v++; switch (*v) { case 'a': boothowto |= RB_ASKNAME; break; case 'd': boothowto |= RB_KDB; break; case 'g': boothowto |= RB_GDB; break; case 's': boothowto |= RB_SINGLE; break; case 'v': boothowto |= RB_VERBOSE; break; } } } else { n = strsep(&v, "="); if (v == NULL) kern_setenv(n, "1"); else kern_setenv(n, v); } } } #ifdef FDT static void xlp_bootargs_init(__register_t arg) { char buf[2048]; /* early stack is big enough */ void *dtbp; phandle_t chosen; ihandle_t mask; dtbp = (void *)(intptr_t)arg; #if defined(FDT_DTB_STATIC) /* * In case the device tree blob was not passed as argument try * to use the statically embedded one. */ if (dtbp == NULL) dtbp = &fdt_static_dtb; #endif if (OF_install(OFW_FDT, 0) == FALSE) while (1); if (OF_init((void *)dtbp) != 0) while (1); if (fdt_immr_addr(xlp_io_base) != 0) while (1); OF_interpret("perform-fixup", 0); chosen = OF_finddevice("/chosen"); if (OF_getprop(chosen, "cpumask", &mask, sizeof(mask)) != -1) { xlp_hw_thread_mask = mask; } if (OF_getprop(chosen, "bootargs", buf, sizeof(buf)) != -1) xlp_parse_bootargs(buf); } #else /* * arg is a pointer to the environment block, the format of the block is * a=xyz\0b=pqr\0\0 */ static void xlp_bootargs_init(__register_t arg) { char buf[2048]; /* early stack is big enough */ char *p, *v, *n; uint32_t mask; /* * provide backward compat for passing cpu mask as arg */ if (arg & 1) { xlp_hw_thread_mask = arg; return; } p = (void *)(intptr_t)arg; while (*p != '\0') { strlcpy(buf, p, sizeof(buf)); v = buf; n = strsep(&v, "="); if (v == NULL) kern_setenv(n, "1"); else kern_setenv(n, v); p += strlen(p) + 1; } /* CPU mask can be passed thru env */ if (getenv_uint("cpumask", &mask) != 0) xlp_hw_thread_mask = mask; /* command line argument */ v = kern_getenv("bootargs"); if (v != NULL) { strlcpy(buf, v, sizeof(buf)); xlp_parse_bootargs(buf); freeenv(v); } } #endif static void mips_init(void) { init_param1(); init_param2(physmem); mips_cpu_init(); cpuinfo.cache_coherent_dma = TRUE; pmap_bootstrap(); mips_proc0_init(); mutex_init(); #ifdef DDB kdb_init(); if (boothowto & RB_KDB) { kdb_enter("Boot flags requested debugger", NULL); } #endif } unsigned int platform_get_timecount(struct timecounter *tc __unused) { uint64_t count = nlm_pic_read_timer(xlp_pic_base, PIC_CLOCK_TIMER); return (unsigned int)~count; } -static void +static void xlp_pic_init(void) { struct timecounter pic_timecounter = { platform_get_timecount, /* get_timecount */ 0, /* no poll_pps */ ~0U, /* counter_mask */ XLP_IO_CLK, /* frequency */ "XLRPIC", /* name */ 2000, /* quality (adjusted in code) */ }; int i; int maxirt; xlp_pic_base = nlm_get_pic_regbase(0); /* TOOD: Add other nodes */ maxirt = nlm_read_reg(nlm_get_pic_pcibase(nlm_nodeid()), XLP_PCI_DEVINFO_REG0); printf("Initializing PIC...@%jx %d IRTs\n", (uintmax_t)xlp_pic_base, maxirt); /* Bind all PIC irqs to cpu 0 */ for (i = 0; i < maxirt; i++) nlm_pic_write_irt(xlp_pic_base, i, 0, 0, 1, 0, 1, 0, 0x1); nlm_pic_set_timer(xlp_pic_base, PIC_CLOCK_TIMER, ~0ULL, 0, 0); platform_timecounter = &pic_timecounter; } #if defined(__mips_n32) || defined(__mips_n64) /* PHYSADDR_64_BIT */ #ifdef XLP_SIM #define XLP_MEM_LIM 0x200000000ULL #else #define XLP_MEM_LIM 0x10000000000ULL #endif #else #define XLP_MEM_LIM 0xfffff000UL #endif static vm_paddr_t xlp_mem_excl[] = { 0, 0, /* for kernel image region, see xlp_mem_init */ 0x0c000000, 0x14000000, /* uboot area, cms queue and other stuff */ 0x1fc00000, 0x1fd00000, /* reset vec */ 0x1e000000, 0x1e200000, /* poe buffers */ }; static int mem_exclude_add(vm_paddr_t *avail, vm_paddr_t mstart, vm_paddr_t mend) { int nreg = sizeof(xlp_mem_excl)/sizeof(xlp_mem_excl[0]); int i, pos; pos = 0; for (i = 0; i < nreg; i += 2) { if (mstart > xlp_mem_excl[i + 1]) continue; if (mstart < xlp_mem_excl[i]) { avail[pos++] = mstart; - if (mend < xlp_mem_excl[i]) + if (mend < xlp_mem_excl[i]) avail[pos++] = mend; else avail[pos++] = xlp_mem_excl[i]; } mstart = xlp_mem_excl[i + 1]; if (mend <= mstart) break; } if (mstart < mend) { avail[pos++] = mstart; avail[pos++] = mend; } return (pos); } static void xlp_mem_init(void) { vm_paddr_t physsz, tmp; uint64_t bridgebase, base, lim, val; int i, j, k, n; /* update kernel image area in exclude regions */ tmp = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(&_end); tmp = round_page(tmp) + 0x20000; /* round up */ xlp_mem_excl[1] = tmp; printf("Memory (from DRAM BARs):\n"); bridgebase = nlm_get_bridge_regbase(0); /* TODO: Add other nodes */ physsz = 0; for (i = 0, j = 0; i < 8; i++) { val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i)); val = (val >> 12) & 0xfffff; base = val << 20; val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i)); val = (val >> 12) & 0xfffff; if (val == 0) /* BAR not enabled */ continue; lim = (val + 1) << 20; printf(" BAR %d: %#jx - %#jx : ", i, (intmax_t)base, (intmax_t)lim); if (lim <= base) { printf("\tskipped - malformed %#jx -> %#jx\n", (intmax_t)base, (intmax_t)lim); continue; } else if (base >= XLP_MEM_LIM) { printf(" skipped - outside usable limit %#jx.\n", (intmax_t)XLP_MEM_LIM); continue; } else if (lim >= XLP_MEM_LIM) { lim = XLP_MEM_LIM; printf(" truncated to %#jx.\n", (intmax_t)XLP_MEM_LIM); } else printf(" usable\n"); /* exclude unusable regions from BAR and add rest */ n = mem_exclude_add(&phys_avail[j], base, lim); for (k = j; k < j + n; k += 2) { physsz += phys_avail[k + 1] - phys_avail[k]; printf("\tMem[%d]: %#jx - %#jx\n", k/2, (intmax_t)phys_avail[k], (intmax_t)phys_avail[k+1]); } j = k; } /* setup final entry with 0 */ phys_avail[j] = phys_avail[j + 1] = 0; /* copy phys_avail to dump_avail */ - for (i = 0; i <= j + 1; i++) + for (i = 0; i <= j + 1; i++) dump_avail[i] = phys_avail[i]; realmem = physmem = btoc(physsz); } void platform_start(__register_t a0 __unused, __register_t a1 __unused, __register_t a2 __unused, __register_t a3 __unused) { /* Initialize pcpu stuff */ mips_pcpu0_init(); /* initialize console so that we have printf */ boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */ init_static_kenv(boot1_env, sizeof(boot1_env)); xlp_bootargs_init(a0); /* clockrate used by delay, so initialize it here */ xlp_cpu_frequency = xlp_get_cpu_frequency(0, 0); cpu_clock = xlp_cpu_frequency / 1000000; mips_timer_early_init(xlp_cpu_frequency); /* Init console please */ cninit(); /* Early core init and fixes for errata */ xlp_setup_core(); xlp_parse_mmu_options(); xlp_mem_init(); bcopy(XLPResetEntry, (void *)MIPS_RESET_EXC_VEC, XLPResetEntryEnd - XLPResetEntry); #ifdef SMP - /* + /* * We will enable the other threads in core 0 here * so that the TLB and cache info is correct when * mips_init runs */ xlp_enable_threads(xlp_mmuval); #endif /* setup for the startup core */ xlp_setup_mmu(); xlp_enable_blocks(); /* Read/Guess/setup board information */ nlm_board_info_setup(); /* MIPS generic init */ mips_init(); /* * XLP specific post initialization - * initialize other on chip stuff + * initialize other on chip stuff */ xlp_pic_init(); mips_timer_init_params(xlp_cpu_frequency, 0); } -void +void platform_cpu_init() { } void platform_reset(void) { uint64_t sysbase = nlm_get_sys_regbase(0); nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1); for( ; ; ) __asm __volatile("wait"); } #ifdef SMP /* * XLP threads are started simultaneously when we enable threads, this will - * ensure that the threads are blocked in platform_init_ap, until they are + * ensure that the threads are blocked in platform_init_ap, until they are * ready to proceed to smp_init_secondary() */ static volatile int thr_unblock[4]; int platform_start_ap(int cpuid) { uint32_t coremask, val; uint64_t sysbase = nlm_get_sys_regbase(0); int hwtid = xlp_cpuid_to_hwtid[cpuid]; int core, thr; core = hwtid / 4; thr = hwtid % 4; if (thr == 0) { /* First thread in core, do core wake up */ coremask = 1u << core; /* Enable core clock */ val = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL); val &= ~coremask; nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, val); /* Remove CPU Reset */ val = nlm_read_sys_reg(sysbase, SYS_CPU_RESET); val &= ~coremask & 0xff; nlm_write_sys_reg(sysbase, SYS_CPU_RESET, val); if (bootverbose) printf("Waking up core %d ...", core); /* Poll for CPU to mark itself coherent */ do { val = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE); - } while ((val & coremask) != 0); + } while ((val & coremask) != 0); if (bootverbose) printf("Done\n"); } else { /* otherwise release the threads stuck in platform_init_ap */ thr_unblock[thr] = 1; } return (0); } void platform_init_ap(int cpuid) { uint32_t stat; int thr; /* The first thread has to setup the MMU and enable other threads */ thr = nlm_threadid(); if (thr == 0) { xlp_setup_core(); xlp_enable_threads(xlp_mmuval); } else { /* - * FIXME busy wait here eats too many cycles, especially + * FIXME busy wait here eats too many cycles, especially * in the core 0 while bootup */ while (thr_unblock[thr] == 0) __asm__ __volatile__ ("nop;nop;nop;nop"); thr_unblock[thr] = 0; } xlp_setup_mmu(); stat = mips_rd_status(); KASSERT((stat & MIPS_SR_INT_IE) == 0, ("Interrupts enabled in %s!", __func__)); stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT; mips_wr_status(stat); nlm_write_c0_eimr(0ull); xlp_enable_irq(IRQ_IPI); xlp_enable_irq(IRQ_TIMER); xlp_enable_irq(IRQ_MSGRING); return; } int -platform_ipi_intrnum(void) +platform_ipi_intrnum(void) { return (IRQ_IPI); } void platform_ipi_send(int cpuid) { nlm_pic_send_ipi(xlp_pic_base, xlp_cpuid_to_hwtid[cpuid], platform_ipi_intrnum(), 0); } void platform_ipi_clear(void) { } int platform_processor_id(void) { return (xlp_hwtid_to_cpuid[nlm_cpuid()]); } void platform_cpu_mask(cpuset_t *mask) { int i, s; CPU_ZERO(mask); s = xlp_ncores * xlp_threads_per_core; for (i = 0; i < s; i++) CPU_SET(i, mask); } struct cpu_group * platform_smp_topo() { return (smp_topo_2level(CG_SHARE_L2, xlp_ncores, CG_SHARE_L1, xlp_threads_per_core, CG_FLAG_THREAD)); } #endif Index: head/sys/mips/nlm/xlp_pci.c =================================================================== --- head/sys/mips/nlm/xlp_pci.c (revision 279386) +++ head/sys/mips/nlm/xlp_pci.c (revision 279387) @@ -1,574 +1,574 @@ /*- * Copyright (c) 2003-2012 Broadcom Corporation * All Rights Reserved * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * + * * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #include "pci_if.h" static int xlp_pci_attach(device_t dev) { struct pci_devinfo *dinfo; device_t pcib; int maxslots, s, f, pcifunchigh, irq; int busno, node, devoffset; uint16_t devid; uint8_t hdrtype; /* * The on-chip devices are on a bus that is almost, but not * quite, completely like PCI. Add those things by hand. */ pcib = device_get_parent(dev); busno = pcib_get_bus(dev); maxslots = PCIB_MAXSLOTS(pcib); for (s = 0; s <= maxslots; s++) { pcifunchigh = 0; f = 0; hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1); if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) continue; if (hdrtype & PCIM_MFDEV) pcifunchigh = PCI_FUNCMAX; node = s / 8; for (f = 0; f <= pcifunchigh; f++) { devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f); if (!nlm_dev_exists(devoffset)) continue; /* Find if there is a desc for the SoC device */ devid = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_DEVICE, 2); /* Skip devices that don't have a proper PCI header */ switch (devid) { case PCI_DEVICE_ID_NLM_ICI: case PCI_DEVICE_ID_NLM_PIC: case PCI_DEVICE_ID_NLM_FMN: case PCI_DEVICE_ID_NLM_UART: case PCI_DEVICE_ID_NLM_I2C: case PCI_DEVICE_ID_NLM_NOR: case PCI_DEVICE_ID_NLM_MMC: continue; case PCI_DEVICE_ID_NLM_EHCI: irq = PIC_USB_IRQ(f); PCIB_WRITE_CONFIG(pcib, busno, s, f, XLP_PCI_DEVSCRATCH_REG0 << 2, (1 << 8) | irq, 4); } dinfo = pci_read_device(pcib, pcib_get_domain(dev), busno, s, f, sizeof(*dinfo)); pci_add_child(dev, dinfo); } } return (bus_generic_attach(dev)); } static int xlp_pci_probe(device_t dev) { device_t pcib; pcib = device_get_parent(dev); /* * Only the top level bus has SoC devices, leave the rest to * Generic PCI code */ if (strcmp(device_get_nameunit(pcib), "pcib0") != 0) return (ENXIO); device_set_desc(dev, "XLP SoCbus"); return (BUS_PROBE_DEFAULT); } static devclass_t pci_devclass; static device_method_t xlp_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, xlp_pci_probe), DEVMETHOD(device_attach, xlp_pci_attach), DEVMETHOD_END }; DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc), pci_driver); DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0); static int xlp_pcib_probe(device_t dev) { if (ofw_bus_is_compatible(dev, "netlogic,xlp-pci")) { device_set_desc(dev, "XLP PCI bus"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) { switch (which) { case PCIB_IVAR_DOMAIN: *result = 0; return (0); case PCIB_IVAR_BUS: *result = 0; return (0); } return (ENOENT); } static int xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result) { switch (which) { case PCIB_IVAR_DOMAIN: return (EINVAL); case PCIB_IVAR_BUS: return (EINVAL); } return (ENOENT); } static int xlp_pcib_maxslots(device_t dev) { return (PCI_SLOTMAX); } static u_int32_t xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) { uint32_t data = 0; uint64_t cfgaddr; int regindex = reg/sizeof(uint32_t); cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); if ((width == 2) && (reg & 1)) return 0xFFFFFFFF; else if ((width == 4) && (reg & 3)) return 0xFFFFFFFF; - /* + /* * The intline and int pin of SoC devices are DOA, except * for bridges (slot %8 == 1). * use the values we stashed in a writable PCI scratch reg. */ if (b == 0 && regindex == 0xf && s % 8 > 1) regindex = XLP_PCI_DEVSCRATCH_REG0; data = nlm_read_pci_reg(cfgaddr, regindex); if (width == 1) return ((data >> ((reg & 3) << 3)) & 0xff); else if (width == 2) return ((data >> ((reg & 3) << 3)) & 0xffff); else return (data); } static void xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, u_int32_t val, int width) { uint64_t cfgaddr; uint32_t data = 0; int regindex = reg / sizeof(uint32_t); cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f)); if ((width == 2) && (reg & 1)) return; else if ((width == 4) && (reg & 3)) return; if (width == 1) { data = nlm_read_pci_reg(cfgaddr, regindex); data = (data & ~(0xff << ((reg & 3) << 3))) | (val << ((reg & 3) << 3)); } else if (width == 2) { data = nlm_read_pci_reg(cfgaddr, regindex); data = (data & ~(0xffff << ((reg & 3) << 3))) | (val << ((reg & 3) << 3)); } else { data = val; } /* * use shadow reg for intpin/intline which are dead */ if (b == 0 && regindex == 0xf && s % 8 > 1) regindex = XLP_PCI_DEVSCRATCH_REG0; nlm_write_pci_reg(cfgaddr, regindex, data); } /* * Enable byte swap in hardware when compiled big-endian. * Programs a link's PCIe SWAP regions from the link's IO and MEM address * ranges. */ static void xlp_pcib_hardware_swap_enable(int node, int link) { #if BYTE_ORDER == BIG_ENDIAN uint64_t bbase, linkpcibase; uint32_t bar; int pcieoffset; pcieoffset = XLP_IO_PCIE_OFFSET(node, link); if (!nlm_dev_exists(pcieoffset)) return; bbase = nlm_get_bridge_regbase(node); linkpcibase = nlm_pcicfg_base(pcieoffset); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link); nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF); #endif } -static int +static int xlp_pcib_attach(device_t dev) { int node, link; /* enable hardware swap on all nodes/links */ for (node = 0; node < XLP_MAX_NODES; node++) for (link = 0; link < 4; link++) xlp_pcib_hardware_swap_enable(node, link); device_add_child(dev, "pci", 0); bus_generic_attach(dev); return (0); } /* * XLS PCIe can have upto 4 links, and each link has its on IRQ - * Find the link on which the device is on + * Find the link on which the device is on */ static int xlp_pcie_link(device_t pcib, device_t dev) { device_t parent, tmp; /* find the lane on which the slot is connected to */ tmp = dev; while (1) { parent = device_get_parent(tmp); if (parent == NULL || parent == pcib) { device_printf(dev, "Cannot find parent bus\n"); return (-1); } if (strcmp(device_get_nameunit(parent), "pci0") == 0) break; tmp = parent; } return (pci_get_function(tmp)); } static int xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) { int i, link; /* * Each link has 32 MSIs that can be allocated, but for now * we only support one device per link. - * msi_alloc() equivalent is needed when we start supporting + * msi_alloc() equivalent is needed when we start supporting * bridges on the PCIe link. */ link = xlp_pcie_link(pcib, dev); if (link == -1) return (ENXIO); /* * encode the irq so that we know it is a MSI interrupt when we * setup interrupts */ for (i = 0; i < count; i++) irqs[i] = 64 + link * 32 + i; return (0); } static int xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs) { return (0); } static int xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data) { int link; if (irq < 64) { - device_printf(dev, "%s: map_msi for irq %d - ignored", + device_printf(dev, "%s: map_msi for irq %d - ignored", device_get_nameunit(pcib), irq); return (ENXIO); } link = (irq - 64) / 32; *addr = MIPS_MSI_ADDR(0); *data = MIPS_MSI_DATA(PIC_PCIE_IRQ(link)); return (0); } static void bridge_pcie_ack(int irq, void *arg) { uint32_t node,reg; uint64_t base; node = nlm_nodeid(); reg = PCIE_MSI_STATUS; switch (irq) { case PIC_PCIE_0_IRQ: base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node)); break; case PIC_PCIE_1_IRQ: base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node)); break; case PIC_PCIE_2_IRQ: base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node)); break; case PIC_PCIE_3_IRQ: base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node)); break; default: return; } nlm_write_pci_reg(base, reg, 0xFFFFFFFF); return; } static int mips_platform_pcib_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error = 0; int xlpirq; error = rman_activate_resource(irq); if (error) return error; if (rman_get_start(irq) != rman_get_end(irq)) { device_printf(dev, "Interrupt allocation %lu != %lu\n", rman_get_start(irq), rman_get_end(irq)); return (EINVAL); } xlpirq = rman_get_start(irq); if (xlpirq == 0) return (0); if (strcmp(device_get_name(dev), "pcib") != 0) return (0); - /* + /* * temporary hack for MSI, we support just one device per * link, and assign the link interrupt to the device interrupt */ if (xlpirq >= 64) { int node, val, link; uint64_t base; xlpirq -= 64; if (xlpirq % 32 != 0) return (0); node = nlm_nodeid(); link = xlpirq / 32; base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link)); /* MSI Interrupt Vector enable at bridge's configuration */ nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN); val = nlm_read_pci_reg(base, PCIE_INT_EN0); /* MSI Interrupt enable at bridge's configuration */ nlm_write_pci_reg(base, PCIE_INT_EN0, (val | PCIE_MSI_INT_EN)); /* legacy interrupt disable at bridge */ val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD); nlm_write_pci_reg(base, PCIE_BRIDGE_CMD, (val | PCIM_CMD_INTxDIS)); /* MSI address update at bridge */ nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL, MSI_MIPS_ADDR_BASE); nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0); val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP); /* MSI capability enable at bridge */ - nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP, + nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP, (val | (PCIM_MSICTRL_MSI_ENABLE << 16) | (PCIM_MSICTRL_MMC_32 << 16))); xlpirq = PIC_PCIE_IRQ(link); } /* if it is for real PCIe, we need to ack at bridge too */ if (xlpirq >= PIC_PCIE_IRQ(0) && xlpirq <= PIC_PCIE_IRQ(3)) xlp_set_bus_ack(xlpirq, bridge_pcie_ack, NULL); cpu_establish_hardintr(device_get_name(child), filt, intr, arg, xlpirq, flags, cookiep); return (0); } static int mips_platform_pcib_teardown_intr(device_t dev, device_t child, struct resource *irq, void *cookie) { if (strcmp(device_get_name(child), "pci") == 0) { /* if needed reprogram the pic to clear pcix related entry */ device_printf(dev, "teardown intr\n"); } return (bus_generic_teardown_intr(dev, child, irq, cookie)); } static int mips_pcib_route_interrupt(device_t bus, device_t dev, int pin) { int f, d; /* * Validate requested pin number. */ if ((pin < 1) || (pin > 4)) return (255); if (pci_get_bus(dev) == 0 && pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) { f = pci_get_function(dev); d = pci_get_slot(dev) % 8; /* * For PCIe links, return link IRT, for other SoC devices * get the IRT from its PCIe header */ if (d == 1) return (PIC_PCIE_IRQ(f)); else return (255); /* use intline, don't reroute */ } else { /* Regular PCI devices */ return (PIC_PCIE_IRQ(xlp_pcie_link(bus, dev))); } } static device_method_t xlp_pcib_methods[] = { /* Device interface */ DEVMETHOD(device_probe, xlp_pcib_probe), DEVMETHOD(device_attach, xlp_pcib_attach), /* Bus interface */ DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar), DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar), DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr), DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr), /* pcib interface */ DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots), DEVMETHOD(pcib_read_config, xlp_pcib_read_config), DEVMETHOD(pcib_write_config, xlp_pcib_write_config), DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt), DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi), DEVMETHOD(pcib_release_msi, xlp_release_msi), DEVMETHOD(pcib_map_msi, xlp_map_msi), DEVMETHOD_END }; static driver_t xlp_pcib_driver = { "pcib", xlp_pcib_methods, 1, /* no softc */ }; static devclass_t pcib_devclass; DRIVER_MODULE(xlp_pcib, simplebus, xlp_pcib_driver, pcib_devclass, 0, 0);