Index: stable/10/sys/arm/allwinner/a20/files.a20 =================================================================== --- stable/10/sys/arm/allwinner/a20/files.a20 (revision 278726) +++ stable/10/sys/arm/allwinner/a20/files.a20 (revision 278727) @@ -1,23 +1,23 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard arm/arm/gic.c standard arm/allwinner/a20/a20_cpu_cfg.c standard arm/allwinner/a10_clk.c standard arm/allwinner/a10_sramc.c standard arm/allwinner/a10_gpio.c optional gpio arm/allwinner/a10_ehci.c optional ehci arm/allwinner/if_emac.c optional emac arm/allwinner/a10_wdog.c standard arm/allwinner/timer.c standard -arm/arm/bus_space-v6.c standard -arm/allwinner/a10_common.c standard +arm/arm/bus_space_base.c standard +arm/allwinner/a10_common.c standard arm/allwinner/a10_machdep.c standard arm/allwinner/a20/a20_mp.c optional smp Index: stable/10/sys/arm/allwinner/files.a10 =================================================================== --- stable/10/sys/arm/allwinner/files.a10 (revision 278726) +++ stable/10/sys/arm/allwinner/files.a10 (revision 278727) @@ -1,23 +1,23 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard arm/allwinner/a10_clk.c standard arm/allwinner/a10_common.c standard arm/allwinner/a10_gpio.c optional gpio arm/allwinner/a10_ehci.c optional ehci arm/allwinner/a10_machdep.c standard arm/allwinner/a10_sramc.c standard arm/allwinner/a10_wdog.c standard arm/allwinner/a20/a20_cpu_cfg.c standard arm/allwinner/aintc.c standard arm/allwinner/if_emac.c optional emac arm/allwinner/timer.c standard -arm/arm/bus_space-v6.c standard -#arm/allwinner/console.c standard +arm/arm/bus_space_base.c standard +#arm/allwinner/console.c standard Index: stable/10/sys/arm/arm/bus_space-v6.c =================================================================== --- stable/10/sys/arm/arm/bus_space-v6.c (revision 278726) +++ stable/10/sys/arm/arm/bus_space-v6.c (nonexistent) @@ -1,158 +0,0 @@ -/*- - * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. - * All rights reserved. - * - * Developed by Semihalf. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of MARVELL nor the names of contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include - -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); -bs_protos(generic_armv4); - -/* - * The bus space tag. This is constant for all instances, so - * we never have to explicitly "create" it. - */ -static struct bus_space _base_tag = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - generic_bs_alloc, - generic_bs_free, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - generic_bs_wr_1, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - generic_bs_sr_1, - generic_armv4_bs_sr_2, - generic_bs_sr_4, - NULL, - - /* copy */ - NULL, - generic_armv4_bs_c_2, - NULL, - NULL, - - /* read stream (single) */ - NULL, - NULL, - NULL, - NULL, - - /* read multiple stream */ - NULL, - generic_armv4_bs_rm_2, /* bus_space_read_multi_stream_2 */ - NULL, - NULL, - - /* read region stream */ - NULL, - NULL, - NULL, - NULL, - - /* write stream (single) */ - NULL, - NULL, - NULL, - NULL, - - /* write multiple stream */ - NULL, - generic_armv4_bs_wm_2, /* bus_space_write_multi_stream_2 */ - NULL, - NULL, - - /* write region stream */ - NULL, - NULL, - NULL, - NULL -}; - -bus_space_tag_t fdtbus_bs_tag = &_base_tag; Property changes on: stable/10/sys/arm/arm/bus_space-v6.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/arm/bus_space_asm_generic.S =================================================================== --- stable/10/sys/arm/arm/bus_space_asm_generic.S (revision 278726) +++ stable/10/sys/arm/arm/bus_space_asm_generic.S (revision 278727) @@ -1,360 +1,360 @@ /* $NetBSD: bus_space_asm_generic.S,v 1.3 2003/03/27 19:46:14 mycroft Exp $ */ /*- * Copyright (c) 1997 Causality Limited. * Copyright (c) 1997 Mark Brinicombe. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Mark Brinicombe * for the NetBSD Project. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include #include __FBSDID("$FreeBSD$"); /* * Generic bus_space functions. */ /* * read single */ ENTRY(generic_bs_r_1) ldrb r0, [r1, r2] RET END(generic_bs_r_1) -ENTRY(generic_armv4_bs_r_2) +ENTRY(generic_bs_r_2) ldrh r0, [r1, r2] RET -END(generic_armv4_bs_r_2) +END(generic_bs_r_2) ENTRY(generic_bs_r_4) ldr r0, [r1, r2] RET END(generic_bs_r_4) /* * write single */ ENTRY(generic_bs_w_1) strb r3, [r1, r2] RET END(generic_bs_w_1) -ENTRY(generic_armv4_bs_w_2) +ENTRY(generic_bs_w_2) strh r3, [r1, r2] RET -END(generic_armv4_bs_w_2) +END(generic_bs_w_2) ENTRY(generic_bs_w_4) str r3, [r1, r2] RET END(generic_bs_w_4) /* * read multiple */ ENTRY(generic_bs_rm_1) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldrb r3, [r0] strb r3, [r1], #1 subs r2, r2, #1 bne 1b RET END(generic_bs_rm_1) -ENTRY(generic_armv4_bs_rm_2) +ENTRY(generic_bs_rm_2) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldrh r3, [r0] strh r3, [r1], #2 subs r2, r2, #1 bne 1b RET -END(generic_armv4_bs_rm_2) +END(generic_bs_rm_2) ENTRY(generic_bs_rm_4) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldr r3, [r0] str r3, [r1], #4 subs r2, r2, #1 bne 1b RET END(generic_bs_rm_4) /* * write multiple */ ENTRY(generic_bs_wm_1) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldrb r3, [r1], #1 strb r3, [r0] subs r2, r2, #1 bne 1b RET END(generic_bs_wm_1) -ENTRY(generic_armv4_bs_wm_2) +ENTRY(generic_bs_wm_2) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldrh r3, [r1], #2 strh r3, [r0] subs r2, r2, #1 bne 1b RET -END(generic_armv4_bs_wm_2) +END(generic_bs_wm_2) ENTRY(generic_bs_wm_4) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldr r3, [r1], #4 str r3, [r0] subs r2, r2, #1 bne 1b RET END(generic_bs_wm_4) /* * read region */ ENTRY(generic_bs_rr_1) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldrb r3, [r0], #1 strb r3, [r1], #1 subs r2, r2, #1 bne 1b RET END(generic_bs_rr_1) -ENTRY(generic_armv4_bs_rr_2) +ENTRY(generic_bs_rr_2) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldrh r3, [r0], #2 strh r3, [r1], #2 subs r2, r2, #1 bne 1b RET -END(generic_armv4_bs_rr_2) +END(generic_bs_rr_2) ENTRY(generic_bs_rr_4) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldr r3, [r0], #4 str r3, [r1], #4 subs r2, r2, #1 bne 1b RET END(generic_bs_rr_4) /* * write region. */ ENTRY(generic_bs_wr_1) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldrb r3, [r1], #1 strb r3, [r0], #1 subs r2, r2, #1 bne 1b RET END(generic_bs_wr_1) -ENTRY(generic_armv4_bs_wr_2) +ENTRY(generic_bs_wr_2) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldrh r3, [r1], #2 strh r3, [r0], #2 subs r2, r2, #1 bne 1b RET -END(generic_armv4_bs_wr_2) +END(generic_bs_wr_2) ENTRY(generic_bs_wr_4) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: ldr r3, [r1], #4 str r3, [r0], #4 subs r2, r2, #1 bne 1b RET END(generic_bs_wr_4) /* * set region */ ENTRY(generic_bs_sr_1) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: strb r1, [r0], #1 subs r2, r2, #1 bne 1b RET END(generic_bs_sr_1) -ENTRY(generic_armv4_bs_sr_2) +ENTRY(generic_bs_sr_2) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: strh r1, [r0], #2 subs r2, r2, #1 bne 1b RET -END(generic_armv4_bs_sr_2) +END(generic_bs_sr_2) ENTRY(generic_bs_sr_4) add r0, r1, r2 mov r1, r3 ldr r2, [sp, #0] teq r2, #0 RETeq 1: str r1, [r0], #4 subs r2, r2, #1 bne 1b RET END(generic_bs_sr_4) /* * copy region */ -ENTRY(generic_armv4_bs_c_2) +ENTRY(generic_bs_c_2) add r0, r1, r2 ldr r2, [sp, #0] add r1, r2, r3 ldr r2, [sp, #4] teq r2, #0 RETeq cmp r0, r1 blt 2f 1: ldrh r3, [r0], #2 strh r3, [r1], #2 subs r2, r2, #1 bne 1b RET 2: add r0, r0, r2, lsl #1 add r1, r1, r2, lsl #1 sub r0, r0, #2 sub r1, r1, #2 3: ldrh r3, [r0], #-2 strh r3, [r1], #-2 subs r2, r2, #1 bne 3b RET -END(generic_armv4_bs_c_2) +END(generic_bs_c_2) Index: stable/10/sys/arm/arm/bus_space_base.c =================================================================== --- stable/10/sys/arm/arm/bus_space_base.c (nonexistent) +++ stable/10/sys/arm/arm/bus_space_base.c (revision 278727) @@ -0,0 +1,159 @@ +/*- + * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. + * All rights reserved. + * + * Developed by Semihalf. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of MARVELL nor the names of contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include + +#include "opt_platform.h" + +/* Prototypes for all the bus_space structure functions */ +bs_protos(generic); + +/* + * The bus space tag. This is constant for all instances, so + * we never have to explicitly "create" it. + */ +static struct bus_space arm_base_bus_space __aligned(CACHE_LINE_SIZE) = { + /* privdata is whatever the implementer wants; unused in base tag */ + .bs_privdata = NULL, + + /* mapping/unmapping */ + .bs_map = generic_bs_map, + .bs_unmap = generic_bs_unmap, + .bs_subregion = generic_bs_subregion, + + /* allocation/deallocation */ + .bs_alloc = generic_bs_alloc, + .bs_free = generic_bs_free, + + /* barrier */ + .bs_barrier = generic_bs_barrier, + + /* read (single) */ + .bs_r_1 = NULL, /* Use inline code in bus.h */ + .bs_r_2 = NULL, /* Use inline code in bus.h */ + .bs_r_4 = NULL, /* Use inline code in bus.h */ + .bs_r_8 = NULL, /* Use inline code in bus.h */ + + /* read multiple */ + .bs_rm_1 = generic_bs_rm_1, + .bs_rm_2 = generic_bs_rm_2, + .bs_rm_4 = generic_bs_rm_4, + .bs_rm_8 = BS_UNIMPLEMENTED, + + /* read region */ + .bs_rr_1 = generic_bs_rr_1, + .bs_rr_2 = generic_bs_rr_2, + .bs_rr_4 = generic_bs_rr_4, + .bs_rr_8 = BS_UNIMPLEMENTED, + + /* write (single) */ + .bs_w_1 = NULL, /* Use inline code in bus.h */ + .bs_w_2 = NULL, /* Use inline code in bus.h */ + .bs_w_4 = NULL, /* Use inline code in bus.h */ + .bs_w_8 = NULL, /* Use inline code in bus.h */ + + /* write multiple */ + .bs_wm_1 = generic_bs_wm_1, + .bs_wm_2 = generic_bs_wm_2, + .bs_wm_4 = generic_bs_wm_4, + .bs_wm_8 = BS_UNIMPLEMENTED, + + /* write region */ + .bs_wr_1 = generic_bs_wr_1, + .bs_wr_2 = generic_bs_wr_2, + .bs_wr_4 = generic_bs_wr_4, + .bs_wr_8 = BS_UNIMPLEMENTED, + + /* set multiple */ + .bs_sm_1 = BS_UNIMPLEMENTED, + .bs_sm_2 = BS_UNIMPLEMENTED, + .bs_sm_4 = BS_UNIMPLEMENTED, + .bs_sm_8 = BS_UNIMPLEMENTED, + + /* set region */ + .bs_sr_1 = generic_bs_sr_1, + .bs_sr_2 = generic_bs_sr_2, + .bs_sr_4 = generic_bs_sr_4, + .bs_sr_8 = BS_UNIMPLEMENTED, + + /* copy */ + .bs_c_1 = BS_UNIMPLEMENTED, + .bs_c_2 = generic_bs_c_2, + .bs_c_4 = BS_UNIMPLEMENTED, + .bs_c_8 = BS_UNIMPLEMENTED, + + /* read stream (single) */ + .bs_r_1_s = NULL, /* Use inline code in bus.h */ + .bs_r_2_s = NULL, /* Use inline code in bus.h */ + .bs_r_4_s = NULL, /* Use inline code in bus.h */ + .bs_r_8_s = NULL, /* Use inline code in bus.h */ + + /* read multiple stream */ + .bs_rm_1_s = generic_bs_rm_1, + .bs_rm_2_s = generic_bs_rm_2, + .bs_rm_4_s = generic_bs_rm_4, + .bs_rm_8_s = BS_UNIMPLEMENTED, + + /* read region stream */ + .bs_rr_1_s = generic_bs_rr_1, + .bs_rr_2_s = generic_bs_rr_2, + .bs_rr_4_s = generic_bs_rr_4, + .bs_rr_8_s = BS_UNIMPLEMENTED, + + /* write stream (single) */ + .bs_w_1_s = NULL, /* Use inline code in bus.h */ + .bs_w_2_s = NULL, /* Use inline code in bus.h */ + .bs_w_4_s = NULL, /* Use inline code in bus.h */ + .bs_w_8_s = NULL, /* Use inline code in bus.h */ + + /* write multiple stream */ + .bs_wm_1_s = generic_bs_wm_1, + .bs_wm_2_s = generic_bs_wm_2, + .bs_wm_4_s = generic_bs_wm_4, + .bs_wm_8_s = BS_UNIMPLEMENTED, + + /* write region stream */ + .bs_wr_1_s = generic_bs_wr_1, + .bs_wr_2_s = generic_bs_wr_2, + .bs_wr_4_s = generic_bs_wr_4, + .bs_wr_8_s = BS_UNIMPLEMENTED, +}; + +#ifdef FDT +bus_space_tag_t fdtbus_bs_tag = &arm_base_bus_space; +#endif + +bus_space_tag_t arm_base_bs_tag = &arm_base_bus_space; Property changes on: stable/10/sys/arm/arm/bus_space_base.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/arm/bus_space_generic.c =================================================================== --- stable/10/sys/arm/arm/bus_space_generic.c (revision 278726) +++ stable/10/sys/arm/arm/bus_space_generic.c (revision 278727) @@ -1,126 +1,133 @@ /* $NetBSD: obio_space.c,v 1.6 2003/07/15 00:25:05 lukem Exp $ */ /*- * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include +void +generic_bs_unimplemented(void) +{ + + panic("unimplemented bus_space function called"); +} + /* Prototypes for all the bus_space structure functions */ bs_protos(generic); int -generic_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, +generic_bs_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) { void *va; /* * We don't even examine the passed-in flags. For ARM, the CACHEABLE * flag doesn't make sense (we create PTE_DEVICE mappings), and the * LINEAR flag is just implied because we use kva_alloc(size). */ if ((va = pmap_mapdev(bpa, size)) == NULL) return (ENOMEM); *bshp = (bus_space_handle_t)va; return (0); } int -generic_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, +generic_bs_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) { panic("generic_bs_alloc(): not implemented"); } void -generic_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) +generic_bs_unmap(bus_space_tag_t t, bus_space_handle_t h, bus_size_t size) { pmap_unmapdev((vm_offset_t)h, size); } void -generic_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) +generic_bs_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) { panic("generic_bs_free(): not implemented"); } int -generic_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, +generic_bs_subregion(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) { *nbshp = bsh + offset; return (0); } void -generic_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, +generic_bs_barrier(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t len, int flags) { /* * dsb() will drain the L1 write buffer and establish a memory access * barrier point on platforms where that has meaning. On a write we * also need to drain the L2 write buffer, because most on-chip memory * mapped devices are downstream of the L2 cache. Note that this needs * to be done even for memory mapped as Device type, because while * Device memory is not cached, writes to it are still buffered. */ dsb(); if (flags & BUS_SPACE_BARRIER_WRITE) { cpu_l2cache_drain_writebuf(); } } Index: stable/10/sys/arm/at91/at91.c =================================================================== --- stable/10/sys/arm/at91/at91.c (revision 278726) +++ stable/10/sys/arm/at91/at91.c (revision 278727) @@ -1,534 +1,528 @@ /*- * Copyright (c) 2005 Olivier Houchard. All rights reserved. * Copyright (c) 2010 Greg Ansley. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include uint32_t at91_master_clock; static int -at91_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, +at91_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) { vm_paddr_t pa, endpa; pa = trunc_page(bpa); if (pa >= AT91_PA_BASE + 0xff00000) { *bshp = bpa - AT91_PA_BASE + AT91_BASE; return (0); } if (pa >= AT91_BASE + 0xff00000) { *bshp = bpa; return (0); } endpa = round_page(bpa + size); *bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa) + (bpa - pa); return (0); } static void -at91_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) +at91_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) { - vm_offset_t va, endva; + vm_offset_t va; - if (t == 0) - return; - va = trunc_page((vm_offset_t)t); + va = (vm_offset_t)h; if (va >= AT91_BASE && va <= AT91_BASE + 0xff00000) return; - endva = round_page((vm_offset_t)t + size); - - /* Free the kernel virtual mapping. */ - kva_free(va, endva - va); + pmap_unmapdev(va, size); } static int -at91_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, +at91_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) { *nbshp = bsh + offset; return (0); } static void -at91_barrier(void *t, bus_space_handle_t bsh, bus_size_t size, bus_size_t b, +at91_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size, bus_size_t b, int a) { } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } int bus_dma_get_range_nb(void) { return (0); } bs_protos(generic); -bs_protos(generic_armv4); struct bus_space at91_bs_tag = { - /* cookie */ - (void *) 0, + /* privdata is whatever the implementer wants; unused in base tag */ + .bs_privdata = NULL, /* mapping/unmapping */ - at91_bs_map, - at91_bs_unmap, - at91_bs_subregion, + .bs_map = at91_bs_map, + .bs_unmap = at91_bs_unmap, + .bs_subregion = at91_bs_subregion, /* allocation/deallocation */ - NULL, - NULL, + .bs_alloc = generic_bs_alloc, + .bs_free = generic_bs_free, /* barrier */ - at91_barrier, + .bs_barrier = at91_barrier, /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, + .bs_r_1 = NULL, /* Use inline code in bus.h */ + .bs_r_2 = NULL, /* Use inline code in bus.h */ + .bs_r_4 = NULL, /* Use inline code in bus.h */ + .bs_r_8 = NULL, /* Use inline code in bus.h */ /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, + .bs_rm_1 = generic_bs_rm_1, + .bs_rm_2 = generic_bs_rm_2, + .bs_rm_4 = generic_bs_rm_4, + .bs_rm_8 = BS_UNIMPLEMENTED, /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, + .bs_rr_1 = generic_bs_rr_1, + .bs_rr_2 = generic_bs_rr_2, + .bs_rr_4 = generic_bs_rr_4, + .bs_rr_8 = BS_UNIMPLEMENTED, /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, + .bs_w_1 = NULL, /* Use inline code in bus.h */ + .bs_w_2 = NULL, /* Use inline code in bus.h */ + .bs_w_4 = NULL, /* Use inline code in bus.h */ + .bs_w_8 = NULL, /* Use inline code in bus.h */ /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, + .bs_wm_1 = generic_bs_wm_1, + .bs_wm_2 = generic_bs_wm_2, + .bs_wm_4 = generic_bs_wm_4, + .bs_wm_8 = BS_UNIMPLEMENTED, /* write region */ - NULL, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, + .bs_wr_1 = generic_bs_wr_1, + .bs_wr_2 = generic_bs_wr_2, + .bs_wr_4 = generic_bs_wr_4, + .bs_wr_8 = BS_UNIMPLEMENTED, /* set multiple */ - NULL, - NULL, - NULL, - NULL, + .bs_sm_1 = BS_UNIMPLEMENTED, + .bs_sm_2 = BS_UNIMPLEMENTED, + .bs_sm_4 = BS_UNIMPLEMENTED, + .bs_sm_8 = BS_UNIMPLEMENTED, /* set region */ - NULL, - generic_armv4_bs_sr_2, - generic_bs_sr_4, - NULL, + .bs_sr_1 = generic_bs_sr_1, + .bs_sr_2 = generic_bs_sr_2, + .bs_sr_4 = generic_bs_sr_4, + .bs_sr_8 = BS_UNIMPLEMENTED, /* copy */ - NULL, - generic_armv4_bs_c_2, - NULL, - NULL, + .bs_c_1 = BS_UNIMPLEMENTED, + .bs_c_2 = generic_bs_c_2, + .bs_c_4 = BS_UNIMPLEMENTED, + .bs_c_8 = BS_UNIMPLEMENTED, - /* read (single) stream */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, + /* read stream (single) */ + .bs_r_1_s = NULL, /* Use inline code in bus.h */ + .bs_r_2_s = NULL, /* Use inline code in bus.h */ + .bs_r_4_s = NULL, /* Use inline code in bus.h */ + .bs_r_8_s = NULL, /* Use inline code in bus.h */ /* read multiple stream */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, + .bs_rm_1_s = generic_bs_rm_1, + .bs_rm_2_s = generic_bs_rm_2, + .bs_rm_4_s = generic_bs_rm_4, + .bs_rm_8_s = BS_UNIMPLEMENTED, /* read region stream */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, + .bs_rr_1_s = generic_bs_rr_1, + .bs_rr_2_s = generic_bs_rr_2, + .bs_rr_4_s = generic_bs_rr_4, + .bs_rr_8_s = BS_UNIMPLEMENTED, - /* write (single) stream */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, + /* write stream (single) */ + .bs_w_1_s = NULL, /* Use inline code in bus.h */ + .bs_w_2_s = NULL, /* Use inline code in bus.h */ + .bs_w_4_s = NULL, /* Use inline code in bus.h */ + .bs_w_8_s = NULL, /* Use inline code in bus.h */ /* write multiple stream */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, + .bs_wm_1_s = generic_bs_wm_1, + .bs_wm_2_s = generic_bs_wm_2, + .bs_wm_4_s = generic_bs_wm_4, + .bs_wm_8_s = BS_UNIMPLEMENTED, /* write region stream */ - NULL, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, + .bs_wr_1_s = generic_bs_wr_1, + .bs_wr_2_s = generic_bs_wr_2, + .bs_wr_4_s = generic_bs_wr_4, + .bs_wr_8_s = BS_UNIMPLEMENTED, }; #ifndef FDT static struct at91_softc *at91_softc; static void at91_eoi(void *); static int at91_probe(device_t dev) { device_set_desc(dev, soc_info.name); return (BUS_PROBE_NOWILDCARD); } static void at91_identify(driver_t *drv, device_t parent) { BUS_ADD_CHILD(parent, 0, "atmelarm", 0); } static void at91_cpu_add_builtin_children(device_t dev, const struct cpu_devs *walker) { int i; for (i = 1; walker->name; i++, walker++) { at91_add_child(dev, i, walker->name, walker->unit, walker->mem_base, walker->mem_len, walker->irq0, walker->irq1, walker->irq2); } } static int at91_attach(device_t dev) { struct at91_softc *sc = device_get_softc(dev); arm_post_filter = at91_eoi; at91_softc = sc; sc->sc_st = &at91_bs_tag; sc->sc_sh = AT91_BASE; sc->sc_aic_sh = AT91_BASE + AT91_SYS_BASE; sc->dev = dev; sc->sc_irq_rman.rm_type = RMAN_ARRAY; sc->sc_irq_rman.rm_descr = "AT91 IRQs"; if (rman_init(&sc->sc_irq_rman) != 0 || rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0) panic("at91_attach: failed to set up IRQ rman"); sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "AT91 Memory"; if (rman_init(&sc->sc_mem_rman) != 0) panic("at91_attach: failed to set up memory rman"); /* * Manage the physical space, defined as being everything that isn't * DRAM. */ if (rman_manage_region(&sc->sc_mem_rman, 0, PHYSADDR - 1) != 0) panic("at91_attach: failed to set up memory rman"); if (rman_manage_region(&sc->sc_mem_rman, PHYSADDR + (256 << 20), 0xfffffffful) != 0) panic("at91_attach: failed to set up memory rman"); /* * Add this device's children... */ at91_cpu_add_builtin_children(dev, soc_info.soc_data->soc_children); soc_info.soc_data->soc_clock_init(); bus_generic_probe(dev); bus_generic_attach(dev); enable_interrupts(PSR_I | PSR_F); return (0); } static struct resource * at91_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct at91_softc *sc = device_get_softc(dev); struct resource_list_entry *rle; struct at91_ivar *ivar = device_get_ivars(child); struct resource_list *rl = &ivar->resources; bus_space_handle_t bsh; if (device_get_parent(child) != dev) return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, start, end, count, flags)); rle = resource_list_find(rl, type, *rid); if (rle == NULL) return (NULL); if (rle->res) panic("Resource rid %d type %d already in use", *rid, type); if (start == 0UL && end == ~0UL) { start = rle->start; count = ulmax(count, rle->count); end = ulmax(rle->end, start + count - 1); } switch (type) { case SYS_RES_IRQ: rle->res = rman_reserve_resource(&sc->sc_irq_rman, start, end, count, flags, child); break; case SYS_RES_MEMORY: rle->res = rman_reserve_resource(&sc->sc_mem_rman, start, end, count, flags, child); if (rle->res != NULL) { bus_space_map(&at91_bs_tag, start, rman_get_size(rle->res), 0, &bsh); rman_set_bustag(rle->res, &at91_bs_tag); rman_set_bushandle(rle->res, bsh); } break; } if (rle->res) { rle->start = rman_get_start(rle->res); rle->end = rman_get_end(rle->res); rle->count = count; rman_set_rid(rle->res, *rid); } return (rle->res); } static struct resource_list * at91_get_resource_list(device_t dev, device_t child) { struct at91_ivar *ivar; ivar = device_get_ivars(child); return (&(ivar->resources)); } static int at91_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct resource_list *rl; struct resource_list_entry *rle; rl = at91_get_resource_list(dev, child); if (rl == NULL) return (EINVAL); rle = resource_list_find(rl, type, rid); if (rle == NULL) return (EINVAL); rman_release_resource(r); rle->res = NULL; return (0); } static int at91_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error; if (rman_get_start(ires) == AT91_IRQ_SYSTEM && filt == NULL) panic("All system interrupt ISRs must be FILTER"); error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep); if (error) return (error); return (0); } static int at91_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { struct at91_softc *sc = device_get_softc(dev); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 1 << rman_get_start(res)); return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static int at91_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { #if 0 u_long p; int error; if (type == SYS_RES_MEMORY) { error = bus_space_map(rman_get_bustag(r), rman_get_bushandle(r), rman_get_size(r), 0, &p); if (error) return (error); rman_set_bushandle(r, p); } #endif return (rman_activate_resource(r)); } static int at91_print_child(device_t dev, device_t child) { struct at91_ivar *ivars; struct resource_list *rl; int retval = 0; ivars = device_get_ivars(child); rl = &ivars->resources; retval += bus_print_child_header(dev, child); retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); if (device_get_flags(dev)) retval += printf(" flags %#x", device_get_flags(dev)); retval += bus_print_child_footer(dev, child); return (retval); } static void at91_eoi(void *unused) { bus_space_write_4(at91_softc->sc_st, at91_softc->sc_aic_sh, IC_EOICR, 0); } void at91_add_child(device_t dev, int prio, const char *name, int unit, bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2) { device_t kid; struct at91_ivar *ivar; kid = device_add_child_ordered(dev, prio, name, unit); if (kid == NULL) { printf("Can't add child %s%d ordered\n", name, unit); return; } ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO); if (ivar == NULL) { device_delete_child(dev, kid); printf("Can't add alloc ivar\n"); return; } device_set_ivars(kid, ivar); resource_list_init(&ivar->resources); if (irq0 != -1) { bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1); if (irq0 != AT91_IRQ_SYSTEM) at91_pmc_clock_add(device_get_nameunit(kid), irq0, 0); } if (irq1 != 0) bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1); if (irq2 != 0) bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1); /* * Special case for on-board devices. These have their address * defined relative to AT91_PA_BASE in all the register files we * have. We could change this, but that's a lot of effort which * will be obsoleted when FDT arrives. */ if (addr != 0 && addr < 0x10000000 && addr >= 0x0f000000) addr += AT91_PA_BASE; if (addr != 0) bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size); } static device_method_t at91_methods[] = { DEVMETHOD(device_probe, at91_probe), DEVMETHOD(device_attach, at91_attach), DEVMETHOD(device_identify, at91_identify), DEVMETHOD(bus_alloc_resource, at91_alloc_resource), DEVMETHOD(bus_setup_intr, at91_setup_intr), DEVMETHOD(bus_teardown_intr, at91_teardown_intr), DEVMETHOD(bus_activate_resource, at91_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_get_resource_list,at91_get_resource_list), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_release_resource, at91_release_resource), DEVMETHOD(bus_print_child, at91_print_child), {0, 0}, }; static driver_t at91_driver = { "atmelarm", at91_methods, sizeof(struct at91_softc), }; static devclass_t at91_devclass; DRIVER_MODULE(atmelarm, nexus, at91_driver, at91_devclass, 0, 0); #endif Index: stable/10/sys/arm/at91/files.at91 =================================================================== --- stable/10/sys/arm/at91/files.at91 (revision 278726) +++ stable/10/sys/arm/at91/files.at91 (revision 278727) @@ -1,58 +1,59 @@ # $FreeBSD$ +arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_arm9.S standard arm/at91/at91_machdep.c standard arm/at91/at91_aic.c standard arm/at91/at91.c standard arm/at91/at91_cfata.c optional at91_cfata arm/at91/at91_mci.c optional at91_mci dev/nand/nfc_at91.c optional nand arm/at91/at91_pio.c standard arm/at91/at91_pmc.c standard arm/at91/at91_pit.c optional at91sam9 arm/at91/at91_reset.S optional at91sam9 arm/at91/at91_rst.c optional at91sam9 arm/at91/at91_rtc.c optional at91_rtc arm/at91/at91_smc.c standard arm/at91/at91_spi.c optional at91_spi \ dependency "spibus_if.h" arm/at91/at91_ssc.c optional at91_ssc arm/at91/at91_st.c optional at91rm9200 arm/at91/at91_tc.c optional at91_tc arm/at91/at91_twi.c optional at91_twi arm/at91/at91_wdt.c optional at91_wdt arm/at91/if_ate.c optional ate arm/at91/if_macb.c optional macb arm/at91/uart_bus_at91usart.c optional uart arm/at91/uart_cpu_at91usart.c optional uart arm/at91/uart_dev_at91usart.c optional uart # # All the "systems on a chip" we support # arm/at91/at91soc.c standard arm/at91/at91rm9200.c optional at91rm9200 arm/at91/at91rm9200_devices.c optional at91rm9200 arm/at91/at91sam9260.c optional at91sam9260 arm/at91/at91sam9g20.c optional at91sam9g20 arm/at91/at91sam9g45.c optional at91sam9g45 arm/at91/at91sam9x5.c optional at91sam9x5 # # All the boards we support # arm/at91/board_bwct.c optional at91_board_bwct arm/at91/board_eb9200.c optional at91_board_eb9200 arm/at91/board_ethernut5.c optional at91_board_ethernut5 arm/at91/board_hl200.c optional at91_board_hl200 arm/at91/board_hl201.c optional at91_board_hl201 arm/at91/board_kb920x.c optional at91_board_kb920x arm/at91/board_qila9g20.c optional at91_board_qila9g20 arm/at91/board_sam9260ek.c optional at91_board_sam9260ek arm/at91/board_sam9g20ek.c optional at91_board_sam9g20ek arm/at91/board_sam9x25ek.c optional at91_board_sam9x25ek arm/at91/board_sn9g45.c optional at91_board_sn9g45 arm/at91/board_tsc4370.c optional at91_board_tsc4370 # # usb # dev/usb/controller/at91dci.c optional at91_dci dev/usb/controller/at91dci_atmelarm.c optional at91_dci dev/usb/controller/ohci_atmelarm.c optional ohci Index: stable/10/sys/arm/broadcom/bcm2835/files.bcm2835 =================================================================== --- stable/10/sys/arm/broadcom/bcm2835/files.bcm2835 (revision 278726) +++ stable/10/sys/arm/broadcom/bcm2835/files.bcm2835 (revision 278727) @@ -1,30 +1,30 @@ # $FreeBSD$ arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc arm/broadcom/bcm2835/bcm2835_common.c optional fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c standard arm/broadcom/bcm2835/bcm2835_dma.c standard arm/broadcom/bcm2835/bcm2835_fb.c optional sc arm/broadcom/bcm2835/bcm2835_fbd.c optional vt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio arm/broadcom/bcm2835/bcm2835_intr.c standard arm/broadcom/bcm2835/bcm2835_machdep.c standard arm/broadcom/bcm2835/bcm2835_mbox.c standard arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi arm/broadcom/bcm2835/bcm2835_systimer.c standard arm/broadcom/bcm2835/bcm2835_wdog.c standard dev/usb/controller/dwc_otg_fdt.c optional dwcotg -arm/arm/bus_space-v6.c standard +arm/arm/bus_space_base.c standard arm/arm/bus_space_generic.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_arm11x6.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_armv6.S standard kern/kern_clocksource.c standard dev/mbox/mbox_if.m standard dev/ofw/ofw_cpu.c standard Index: stable/10/sys/arm/cavium/cns11xx/econa.c =================================================================== --- stable/10/sys/arm/cavium/cns11xx/econa.c (revision 278726) +++ stable/10/sys/arm/cavium/cns11xx/econa.c (revision 278727) @@ -1,760 +1,652 @@ /*- * Copyright (c) 2009 Yohanes Nugroho * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include "econa_reg.h" #include "econa_var.h" static struct econa_softc *econa_softc; unsigned int CPU_clock = 200000000; unsigned int AHB_clock; unsigned int APB_clock; -bs_protos(generic); -bs_protos(generic_armv4); +bus_space_tag_t obio_tag; -struct bus_space econa_bs_tag = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - generic_bs_alloc, - generic_bs_free, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - NULL, - NULL, - NULL, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - NULL, - NULL, - NULL, - - /* copy */ - NULL, - NULL, - NULL, - NULL, - - /* read (single) stream */ - NULL, - NULL, - NULL, - NULL, - - /* read multiple stream */ - NULL, - generic_armv4_bs_rm_2, - NULL, - NULL, - - /* read region stream */ - NULL, - NULL, - NULL, - NULL, - - /* write (single) stream */ - NULL, - NULL, - NULL, - NULL, - - /* write multiple stream */ - NULL, - generic_armv4_bs_wm_2, - NULL, - NULL, - - /* write region stream */ - NULL, - NULL, - NULL, - NULL -}; - -bus_space_tag_t obio_tag = &econa_bs_tag; - static int econa_probe(device_t dev) { device_set_desc(dev, "ECONA device bus"); return (BUS_PROBE_NOWILDCARD); } static void econa_identify(driver_t *drv, device_t parent) { BUS_ADD_CHILD(parent, 0, "econaarm", 0); } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } int bus_dma_get_range_nb(void) { return (0); } extern void irq_entry(void); static void econa_add_child(device_t dev, int prio, const char *name, int unit, bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2, int irq3, int irq4) { device_t kid; struct econa_ivar *ivar; kid = device_add_child_ordered(dev, prio, name, unit); if (kid == NULL) { printf("Can't add child %s%d ordered\n", name, unit); return; } ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO); if (ivar == NULL) { device_delete_child(dev, kid); return; } device_set_ivars(kid, ivar); resource_list_init(&ivar->resources); if (irq0 != -1) bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1); if (irq1 != 0) bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1); if (irq2 != 0) bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1); if (irq3 != 0) bus_set_resource(kid, SYS_RES_IRQ, 3, irq3, 1); if (irq4 != 0) bus_set_resource(kid, SYS_RES_IRQ, 4, irq4, 1); if (addr != 0) bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size); } struct cpu_devs { const char *name; int unit; bus_addr_t mem_base; bus_size_t mem_len; int irq0; int irq1; int irq2; int irq3; int irq4; }; struct cpu_devs econarm_devs[] = { { "econa_ic", 0, ECONA_IO_BASE + ECONA_PIC_BASE, ECONA_PIC_SIZE, 0 }, { "system", 0, ECONA_IO_BASE + ECONA_SYSTEM_BASE, ECONA_SYSTEM_SIZE, 0 }, { "uart", 0, ECONA_IO_BASE + ECONA_UART_BASE, ECONA_UART_SIZE, ECONA_IRQ_UART }, { "timer", 0, ECONA_IO_BASE + ECONA_TIMER_BASE, ECONA_TIMER_SIZE, ECONA_IRQ_TIMER_1, ECONA_IRQ_TIMER_2 }, { "ohci", 0, ECONA_OHCI_VBASE, ECONA_OHCI_SIZE, ECONA_IRQ_OHCI }, { "ehci", 0, ECONA_EHCI_VBASE, ECONA_EHCI_SIZE, ECONA_IRQ_EHCI }, { "cfi", 0, ECONA_CFI_VBASE, ECONA_CFI_SIZE, 0 }, { "ece", 0, ECONA_IO_BASE + ECONA_NET_BASE, ECONA_NET_SIZE, ECONA_IRQ_STATUS, ECONA_IRQ_TSTC, ECONA_IRQ_FSRC, ECONA_IRQ_TSQE, ECONA_IRQ_FSQF, }, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } }; static void econa_cpu_add_builtin_children(device_t dev, struct econa_softc *sc) { int i; struct cpu_devs *walker; for (i = 0, walker = econarm_devs; walker->name; i++, walker++) { econa_add_child(dev, i, walker->name, walker->unit, walker->mem_base, walker->mem_len, walker->irq0,walker->irq1, walker->irq2, walker->irq3, walker->irq4); } } struct intc_trigger_t { int mode; int level; }; static struct intc_trigger_t intc_trigger_table[] = { {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_FALLING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_EDGE_TRIGGER, INTC_FALLING_EDGE}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW}, }; static inline uint32_t read_4(struct econa_softc *sc, bus_size_t off) { return bus_space_read_4(sc->ec_st, sc->ec_sys_sh, off); } static inline void write_4(struct econa_softc *sc, bus_size_t off, uint32_t val) { return bus_space_write_4(sc->ec_st, sc->ec_sys_sh, off, val); } static inline uint32_t system_read_4(struct econa_softc *sc, bus_size_t off) { return bus_space_read_4(sc->ec_st, sc->ec_system_sh, off); } static inline void system_write_4(struct econa_softc *sc, bus_size_t off, uint32_t val) { return bus_space_write_4(sc->ec_st, sc->ec_system_sh, off, val); } static inline void econa_set_irq_mode(struct econa_softc * sc, unsigned int irq, unsigned int mode) { unsigned int val; if ((mode != INTC_LEVEL_TRIGGER) && (mode != INTC_EDGE_TRIGGER)) return; val = read_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET); if (mode == INTC_LEVEL_TRIGGER) { if (val & (1UL << irq)) { val &= ~(1UL << irq); write_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET, val); } } else { if (!(val & (1UL << irq))) { val |= (1UL << irq); write_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET, val); } } } /* * Configure interrupt trigger level to be Active High/Low * or Rising/Falling Edge */ static inline void econa_set_irq_level(struct econa_softc * sc, unsigned int irq, unsigned int level) { unsigned int val; if ((level != INTC_ACTIVE_HIGH) && (level != INTC_ACTIVE_LOW) && (level != INTC_RISING_EDGE) && (level != INTC_FALLING_EDGE)) { return; } val = read_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET); if ((level == INTC_ACTIVE_HIGH) || (level == INTC_RISING_EDGE)) { if (val & (1UL << irq)) { val &= ~(1UL << irq); write_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET, val); } } else { if (!(val & (1UL << irq))) { val |= (1UL << irq); write_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET, val); } } } static void get_system_clock(void) { uint32_t sclock = system_read_4(econa_softc, SYSTEM_CLOCK); sclock = (sclock >> 6) & 0x03; switch (sclock) { case 0: CPU_clock = 175000000; break; case 1: CPU_clock = 200000000; break; case 2: CPU_clock = 225000000; break; case 3: CPU_clock = 250000000; break; } AHB_clock = CPU_clock >> 1; APB_clock = AHB_clock >> 1; } static int econa_attach(device_t dev) { struct econa_softc *sc = device_get_softc(dev); int i; + obio_tag = arm_base_bs_tag; + econa_softc = sc; - sc->ec_st = &econa_bs_tag; + sc->ec_st = arm_base_bs_tag; sc->ec_sh = ECONA_IO_BASE; sc->dev = dev; if (bus_space_subregion(sc->ec_st, sc->ec_sh, ECONA_PIC_BASE, ECONA_PIC_SIZE, &sc->ec_sys_sh) != 0) panic("Unable to map IRQ registers"); if (bus_space_subregion(sc->ec_st, sc->ec_sh, ECONA_SYSTEM_BASE, ECONA_SYSTEM_SIZE, &sc->ec_system_sh) != 0) panic("Unable to map IRQ registers"); sc->ec_irq_rman.rm_type = RMAN_ARRAY; sc->ec_irq_rman.rm_descr = "ECONA IRQs"; sc->ec_mem_rman.rm_type = RMAN_ARRAY; sc->ec_mem_rman.rm_descr = "ECONA Memory"; if (rman_init(&sc->ec_irq_rman) != 0 || rman_manage_region(&sc->ec_irq_rman, 0, 31) != 0) panic("econa_attach: failed to set up IRQ rman"); if (rman_init(&sc->ec_mem_rman) != 0 || rman_manage_region(&sc->ec_mem_rman, 0, ~0) != 0) panic("econa_attach: failed to set up memory rman"); write_4(sc, INTC_INTERRUPT_CLEAR_EDGE_TRIGGER_REG_OFFSET, 0xffffffff); write_4(sc, INTC_INTERRUPT_MASK_REG_OFFSET, 0xffffffff); write_4(sc, INTC_FIQ_MODE_SELECT_REG_OFFSET, 0); /*initialize irq*/ for (i = 0; i < 32; i++) { if (intc_trigger_table[i].mode != INTC_TRIGGER_UNKNOWN) { econa_set_irq_mode(sc,i, intc_trigger_table[i].mode); econa_set_irq_level(sc, i, intc_trigger_table[i].level); } } get_system_clock(); econa_cpu_add_builtin_children(dev, sc); bus_generic_probe(dev); bus_generic_attach(dev); enable_interrupts(PSR_I | PSR_F); return (0); } static struct resource * econa_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct econa_softc *sc = device_get_softc(dev); struct resource_list_entry *rle; struct econa_ivar *ivar = device_get_ivars(child); struct resource_list *rl = &ivar->resources; if (device_get_parent(child) != dev) return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, start, end, count, flags)); rle = resource_list_find(rl, type, *rid); if (rle == NULL) { return (NULL); } if (rle->res) panic("Resource rid %d type %d already in use", *rid, type); if (start == 0UL && end == ~0UL) { start = rle->start; count = ulmax(count, rle->count); end = ulmax(rle->end, start + count - 1); } switch (type) { case SYS_RES_IRQ: rle->res = rman_reserve_resource(&sc->ec_irq_rman, start, end, count, flags, child); break; case SYS_RES_MEMORY: rle->res = rman_reserve_resource(&sc->ec_mem_rman, start, end, count, flags, child); if (rle->res != NULL) { - rman_set_bustag(rle->res, &econa_bs_tag); + rman_set_bustag(rle->res, arm_base_bs_tag); rman_set_bushandle(rle->res, start); } break; } if (rle->res) { rle->start = rman_get_start(rle->res); rle->end = rman_get_end(rle->res); rle->count = count; rman_set_rid(rle->res, *rid); } return (rle->res); } static struct resource_list * econa_get_resource_list(device_t dev, device_t child) { struct econa_ivar *ivar; ivar = device_get_ivars(child); return (&(ivar->resources)); } static int econa_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct resource_list *rl; struct resource_list_entry *rle; rl = econa_get_resource_list(dev, child); if (rl == NULL) return (EINVAL); rle = resource_list_find(rl, type, rid); if (rle == NULL) return (EINVAL); rman_release_resource(r); rle->res = NULL; return (0); } static int econa_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error; if (rman_get_start(ires) == ECONA_IRQ_SYSTEM && filt == NULL) panic("All system interrupt ISRs must be FILTER"); error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep); if (error) return (error); return (0); } static int econa_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static int econa_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { return (rman_activate_resource(r)); } static int econa_print_child(device_t dev, device_t child) { struct econa_ivar *ivars; struct resource_list *rl; int retval = 0; ivars = device_get_ivars(child); rl = &ivars->resources; retval += bus_print_child_header(dev, child); retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); if (device_get_flags(dev)) retval += printf(" flags %#x", device_get_flags(dev)); retval += bus_print_child_footer(dev, child); return (retval); } void arm_mask_irq(uintptr_t nb) { unsigned int value; value = read_4(econa_softc,INTC_INTERRUPT_MASK_REG_OFFSET) | 1< /* * int bus_space_map (bus_space_tag_t t, bus_addr_t addr, * bus_size_t size, int flags, bus_space_handle_t *bshp); * * Map a region of bus space. */ #define BUS_SPACE_MAP_CACHEABLE 0x01 #define BUS_SPACE_MAP_LINEAR 0x02 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 +/* + * Bus space for ARM. + * + * The functions used most often are grouped together at the beginning to ensure + * that all the data fits into a single cache line. The inline implementations + * of single read/write access these values a lot. + */ struct bus_space { - /* cookie */ - void *bs_cookie; + /* Read/write single and barrier: the most commonly used functions. */ + uint8_t (*bs_r_1)(bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint32_t (*bs_r_4)(bus_space_tag_t, bus_space_handle_t, bus_size_t); + void (*bs_w_1)(bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t); + void (*bs_w_4)(bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t); + void (*bs_barrier)(bus_space_tag_t, bus_space_handle_t, + bus_size_t, bus_size_t, int); + /* Backlink to parent (if copied), and implementation private data. */ + struct bus_space *bs_parent; + void *bs_privdata; + /* mapping/unmapping */ - int (*bs_map) (void *, bus_addr_t, bus_size_t, + int (*bs_map) (bus_space_tag_t, bus_addr_t, bus_size_t, int, bus_space_handle_t *); - void (*bs_unmap) (void *, bus_space_handle_t, bus_size_t); - int (*bs_subregion) (void *, bus_space_handle_t, + void (*bs_unmap) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + int (*bs_subregion) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_size_t, bus_space_handle_t *); /* allocation/deallocation */ - int (*bs_alloc) (void *, bus_addr_t, bus_addr_t, + int (*bs_alloc) (bus_space_tag_t, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); - void (*bs_free) (void *, bus_space_handle_t, + void (*bs_free) (bus_space_tag_t, bus_space_handle_t, bus_size_t); - /* get kernel virtual address */ - /* barrier */ - void (*bs_barrier) (void *, bus_space_handle_t, - bus_size_t, bus_size_t, int); + /* Read single, the less commonly used functions. */ + uint16_t (*bs_r_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint64_t (*bs_r_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t); - /* read (single) */ - u_int8_t (*bs_r_1) (void *, bus_space_handle_t, bus_size_t); - u_int16_t (*bs_r_2) (void *, bus_space_handle_t, bus_size_t); - u_int32_t (*bs_r_4) (void *, bus_space_handle_t, bus_size_t); - u_int64_t (*bs_r_8) (void *, bus_space_handle_t, bus_size_t); - /* read multiple */ - void (*bs_rm_1) (void *, bus_space_handle_t, bus_size_t, - u_int8_t *, bus_size_t); - void (*bs_rm_2) (void *, bus_space_handle_t, bus_size_t, - u_int16_t *, bus_size_t); - void (*bs_rm_4) (void *, bus_space_handle_t, - bus_size_t, u_int32_t *, bus_size_t); - void (*bs_rm_8) (void *, bus_space_handle_t, - bus_size_t, u_int64_t *, bus_size_t); + void (*bs_rm_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + uint8_t *, bus_size_t); + void (*bs_rm_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + uint16_t *, bus_size_t); + void (*bs_rm_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rm_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); /* read region */ - void (*bs_rr_1) (void *, bus_space_handle_t, - bus_size_t, u_int8_t *, bus_size_t); - void (*bs_rr_2) (void *, bus_space_handle_t, - bus_size_t, u_int16_t *, bus_size_t); - void (*bs_rr_4) (void *, bus_space_handle_t, - bus_size_t, u_int32_t *, bus_size_t); - void (*bs_rr_8) (void *, bus_space_handle_t, - bus_size_t, u_int64_t *, bus_size_t); + void (*bs_rr_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t *, bus_size_t); + void (*bs_rr_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t *, bus_size_t); + void (*bs_rr_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rr_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); - /* write (single) */ - void (*bs_w_1) (void *, bus_space_handle_t, - bus_size_t, u_int8_t); - void (*bs_w_2) (void *, bus_space_handle_t, - bus_size_t, u_int16_t); - void (*bs_w_4) (void *, bus_space_handle_t, - bus_size_t, u_int32_t); - void (*bs_w_8) (void *, bus_space_handle_t, - bus_size_t, u_int64_t); + /* Write single, the less commonly used functions. */ + void (*bs_w_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t); + void (*bs_w_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t); /* write multiple */ - void (*bs_wm_1) (void *, bus_space_handle_t, - bus_size_t, const u_int8_t *, bus_size_t); - void (*bs_wm_2) (void *, bus_space_handle_t, - bus_size_t, const u_int16_t *, bus_size_t); - void (*bs_wm_4) (void *, bus_space_handle_t, - bus_size_t, const u_int32_t *, bus_size_t); - void (*bs_wm_8) (void *, bus_space_handle_t, - bus_size_t, const u_int64_t *, bus_size_t); + void (*bs_wm_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wm_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wm_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wm_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); /* write region */ - void (*bs_wr_1) (void *, bus_space_handle_t, - bus_size_t, const u_int8_t *, bus_size_t); - void (*bs_wr_2) (void *, bus_space_handle_t, - bus_size_t, const u_int16_t *, bus_size_t); - void (*bs_wr_4) (void *, bus_space_handle_t, - bus_size_t, const u_int32_t *, bus_size_t); - void (*bs_wr_8) (void *, bus_space_handle_t, - bus_size_t, const u_int64_t *, bus_size_t); + void (*bs_wr_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wr_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wr_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wr_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); /* set multiple */ - void (*bs_sm_1) (void *, bus_space_handle_t, - bus_size_t, u_int8_t, bus_size_t); - void (*bs_sm_2) (void *, bus_space_handle_t, - bus_size_t, u_int16_t, bus_size_t); - void (*bs_sm_4) (void *, bus_space_handle_t, - bus_size_t, u_int32_t, bus_size_t); - void (*bs_sm_8) (void *, bus_space_handle_t, - bus_size_t, u_int64_t, bus_size_t); + void (*bs_sm_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t, bus_size_t); + void (*bs_sm_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t, bus_size_t); + void (*bs_sm_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t, bus_size_t); + void (*bs_sm_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t, bus_size_t); /* set region */ - void (*bs_sr_1) (void *, bus_space_handle_t, - bus_size_t, u_int8_t, bus_size_t); - void (*bs_sr_2) (void *, bus_space_handle_t, - bus_size_t, u_int16_t, bus_size_t); - void (*bs_sr_4) (void *, bus_space_handle_t, - bus_size_t, u_int32_t, bus_size_t); - void (*bs_sr_8) (void *, bus_space_handle_t, - bus_size_t, u_int64_t, bus_size_t); + void (*bs_sr_1) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t, bus_size_t); + void (*bs_sr_2) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t, bus_size_t); + void (*bs_sr_4) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t, bus_size_t); + void (*bs_sr_8) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t, bus_size_t); /* copy */ - void (*bs_c_1) (void *, bus_space_handle_t, bus_size_t, + void (*bs_c_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); - void (*bs_c_2) (void *, bus_space_handle_t, bus_size_t, + void (*bs_c_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); - void (*bs_c_4) (void *, bus_space_handle_t, bus_size_t, + void (*bs_c_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); - void (*bs_c_8) (void *, bus_space_handle_t, bus_size_t, + void (*bs_c_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); /* read stream (single) */ - u_int8_t (*bs_r_1_s) (void *, bus_space_handle_t, bus_size_t); - u_int16_t (*bs_r_2_s) (void *, bus_space_handle_t, bus_size_t); - u_int32_t (*bs_r_4_s) (void *, bus_space_handle_t, bus_size_t); - u_int64_t (*bs_r_8_s) (void *, bus_space_handle_t, bus_size_t); + uint8_t (*bs_r_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint16_t (*bs_r_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint32_t (*bs_r_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); + uint64_t (*bs_r_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); /* read multiple stream */ - void (*bs_rm_1_s) (void *, bus_space_handle_t, bus_size_t, - u_int8_t *, bus_size_t); - void (*bs_rm_2_s) (void *, bus_space_handle_t, bus_size_t, - u_int16_t *, bus_size_t); - void (*bs_rm_4_s) (void *, bus_space_handle_t, - bus_size_t, u_int32_t *, bus_size_t); - void (*bs_rm_8_s) (void *, bus_space_handle_t, - bus_size_t, u_int64_t *, bus_size_t); + void (*bs_rm_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + uint8_t *, bus_size_t); + void (*bs_rm_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, + uint16_t *, bus_size_t); + void (*bs_rm_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rm_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); /* read region stream */ - void (*bs_rr_1_s) (void *, bus_space_handle_t, - bus_size_t, u_int8_t *, bus_size_t); - void (*bs_rr_2_s) (void *, bus_space_handle_t, - bus_size_t, u_int16_t *, bus_size_t); - void (*bs_rr_4_s) (void *, bus_space_handle_t, - bus_size_t, u_int32_t *, bus_size_t); - void (*bs_rr_8_s) (void *, bus_space_handle_t, - bus_size_t, u_int64_t *, bus_size_t); + void (*bs_rr_1_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t *, bus_size_t); + void (*bs_rr_2_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t *, bus_size_t); + void (*bs_rr_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t *, bus_size_t); + void (*bs_rr_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t *, bus_size_t); /* write stream (single) */ - void (*bs_w_1_s) (void *, bus_space_handle_t, - bus_size_t, u_int8_t); - void (*bs_w_2_s) (void *, bus_space_handle_t, - bus_size_t, u_int16_t); - void (*bs_w_4_s) (void *, bus_space_handle_t, - bus_size_t, u_int32_t); - void (*bs_w_8_s) (void *, bus_space_handle_t, - bus_size_t, u_int64_t); + void (*bs_w_1_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint8_t); + void (*bs_w_2_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint16_t); + void (*bs_w_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint32_t); + void (*bs_w_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, uint64_t); /* write multiple stream */ - void (*bs_wm_1_s) (void *, bus_space_handle_t, - bus_size_t, const u_int8_t *, bus_size_t); - void (*bs_wm_2_s) (void *, bus_space_handle_t, - bus_size_t, const u_int16_t *, bus_size_t); - void (*bs_wm_4_s) (void *, bus_space_handle_t, - bus_size_t, const u_int32_t *, bus_size_t); - void (*bs_wm_8_s) (void *, bus_space_handle_t, - bus_size_t, const u_int64_t *, bus_size_t); + void (*bs_wm_1_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wm_2_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wm_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wm_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); /* write region stream */ - void (*bs_wr_1_s) (void *, bus_space_handle_t, - bus_size_t, const u_int8_t *, bus_size_t); - void (*bs_wr_2_s) (void *, bus_space_handle_t, - bus_size_t, const u_int16_t *, bus_size_t); - void (*bs_wr_4_s) (void *, bus_space_handle_t, - bus_size_t, const u_int32_t *, bus_size_t); - void (*bs_wr_8_s) (void *, bus_space_handle_t, - bus_size_t, const u_int64_t *, bus_size_t); + void (*bs_wr_1_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint8_t *, bus_size_t); + void (*bs_wr_2_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint16_t *, bus_size_t); + void (*bs_wr_4_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint32_t *, bus_size_t); + void (*bs_wr_8_s) (bus_space_tag_t, bus_space_handle_t, + bus_size_t, const uint64_t *, bus_size_t); }; +extern bus_space_tag_t arm_base_bs_tag; /* * Utility macros; INTERNAL USE ONLY. */ #define __bs_c(a,b) __CONCAT(a,b) #define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size) -#define __bs_rs(sz, t, h, o) \ - (*(t)->__bs_opname(r,sz))((t)->bs_cookie, h, o) -#define __bs_ws(sz, t, h, o, v) \ - (*(t)->__bs_opname(w,sz))((t)->bs_cookie, h, o, v) #define __bs_nonsingle(type, sz, t, h, o, a, c) \ - (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, a, c) + (*(t)->__bs_opname(type,sz))((t), h, o, a, c) #define __bs_set(type, sz, t, h, o, v, c) \ - (*(t)->__bs_opname(type,sz))((t)->bs_cookie, h, o, v, c) + (*(t)->__bs_opname(type,sz))((t), h, o, v, c) #define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \ - (*(t)->__bs_opname(c,sz))((t)->bs_cookie, h1, o1, h2, o2, cnt) + (*(t)->__bs_opname(c,sz))((t), h1, o1, h2, o2, cnt) #define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s) #define __bs_rs_s(sz, t, h, o) \ - (*(t)->__bs_opname_s(r,sz))((t)->bs_cookie, h, o) + (*(t)->__bs_opname_s(r,sz))((t), h, o) #define __bs_ws_s(sz, t, h, o, v) \ - (*(t)->__bs_opname_s(w,sz))((t)->bs_cookie, h, o, v) + (*(t)->__bs_opname_s(w,sz))((t), h, o, v) #define __bs_nonsingle_s(type, sz, t, h, o, a, c) \ - (*(t)->__bs_opname_s(type,sz))((t)->bs_cookie, h, o, a, c) + (*(t)->__bs_opname_s(type,sz))((t), h, o, a, c) +#define __generate_inline_bs_rs(IFN, MBR, TYP) \ + static inline TYP \ + IFN(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) \ + { \ + \ + if (__predict_true(t->MBR == NULL)) \ + return (*(volatile TYP *)(h + o)); \ + else \ + return (t->MBR(t, h, o)); \ + } + +#define __generate_inline_bs_ws(IFN, MBR, TYP) \ + static inline void \ + IFN(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, TYP v)\ + { \ + \ + if (__predict_true(t->MBR == NULL)) \ + *(volatile TYP *)(h + o) = v; \ + else \ + t->MBR(t, h, o, v); \ + } + /* * Mapping and unmapping operations. */ #define bus_space_map(t, a, s, c, hp) \ - (*(t)->bs_map)((t)->bs_cookie, (a), (s), (c), (hp)) + (*(t)->bs_map)((t), (a), (s), (c), (hp)) #define bus_space_unmap(t, h, s) \ - (*(t)->bs_unmap)((t)->bs_cookie, (h), (s)) + (*(t)->bs_unmap)((t), (h), (s)) #define bus_space_subregion(t, h, o, s, hp) \ - (*(t)->bs_subregion)((t)->bs_cookie, (h), (o), (s), (hp)) + (*(t)->bs_subregion)((t), (h), (o), (s), (hp)) /* * Allocation and deallocation operations. */ #define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \ - (*(t)->bs_alloc)((t)->bs_cookie, (rs), (re), (s), (a), (b), \ + (*(t)->bs_alloc)((t), (rs), (re), (s), (a), (b), \ (c), (ap), (hp)) #define bus_space_free(t, h, s) \ - (*(t)->bs_free)((t)->bs_cookie, (h), (s)) + (*(t)->bs_free)((t), (h), (s)) /* * Bus barrier operations. */ #define bus_space_barrier(t, h, o, l, f) \ - (*(t)->bs_barrier)((t)->bs_cookie, (h), (o), (l), (f)) + (*(t)->bs_barrier)((t), (h), (o), (l), (f)) #define BUS_SPACE_BARRIER_READ 0x01 #define BUS_SPACE_BARRIER_WRITE 0x02 /* * Bus read (single) operations. */ -#define bus_space_read_1(t, h, o) __bs_rs(1,(t),(h),(o)) -#define bus_space_read_2(t, h, o) __bs_rs(2,(t),(h),(o)) -#define bus_space_read_4(t, h, o) __bs_rs(4,(t),(h),(o)) -#define bus_space_read_8(t, h, o) __bs_rs(8,(t),(h),(o)) +__generate_inline_bs_rs(bus_space_read_1, bs_r_1, uint8_t); +__generate_inline_bs_rs(bus_space_read_2, bs_r_2, uint16_t); +__generate_inline_bs_rs(bus_space_read_4, bs_r_4, uint32_t); +__generate_inline_bs_rs(bus_space_read_8, bs_r_8, uint64_t); -#define bus_space_read_stream_1(t, h, o) __bs_rs_s(1,(t), (h), (o)) -#define bus_space_read_stream_2(t, h, o) __bs_rs_s(2,(t), (h), (o)) -#define bus_space_read_stream_4(t, h, o) __bs_rs_s(4,(t), (h), (o)) -#define bus_space_read_stream_8(t, h, o) __bs_rs_s(8,8,(t),(h),(o)) +__generate_inline_bs_rs(bus_space_read_stream_1, bs_r_1_s, uint8_t); +__generate_inline_bs_rs(bus_space_read_stream_2, bs_r_2_s, uint16_t); +__generate_inline_bs_rs(bus_space_read_stream_4, bs_r_4_s, uint32_t); +__generate_inline_bs_rs(bus_space_read_stream_8, bs_r_8_s, uint64_t); /* * Bus read multiple operations. */ #define bus_space_read_multi_1(t, h, o, a, c) \ __bs_nonsingle(rm,1,(t),(h),(o),(a),(c)) #define bus_space_read_multi_2(t, h, o, a, c) \ __bs_nonsingle(rm,2,(t),(h),(o),(a),(c)) #define bus_space_read_multi_4(t, h, o, a, c) \ __bs_nonsingle(rm,4,(t),(h),(o),(a),(c)) #define bus_space_read_multi_8(t, h, o, a, c) \ __bs_nonsingle(rm,8,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c)) /* * Bus read region operations. */ #define bus_space_read_region_1(t, h, o, a, c) \ __bs_nonsingle(rr,1,(t),(h),(o),(a),(c)) #define bus_space_read_region_2(t, h, o, a, c) \ __bs_nonsingle(rr,2,(t),(h),(o),(a),(c)) #define bus_space_read_region_4(t, h, o, a, c) \ __bs_nonsingle(rr,4,(t),(h),(o),(a),(c)) #define bus_space_read_region_8(t, h, o, a, c) \ __bs_nonsingle(rr,8,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c)) /* * Bus write (single) operations. */ -#define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v)) -#define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v)) -#define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v)) -#define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v)) +__generate_inline_bs_ws(bus_space_write_1, bs_w_1, uint8_t); +__generate_inline_bs_ws(bus_space_write_2, bs_w_2, uint16_t); +__generate_inline_bs_ws(bus_space_write_4, bs_w_4, uint32_t); +__generate_inline_bs_ws(bus_space_write_8, bs_w_8, uint64_t); -#define bus_space_write_stream_1(t, h, o, v) __bs_ws_s(1,(t),(h),(o),(v)) -#define bus_space_write_stream_2(t, h, o, v) __bs_ws_s(2,(t),(h),(o),(v)) -#define bus_space_write_stream_4(t, h, o, v) __bs_ws_s(4,(t),(h),(o),(v)) -#define bus_space_write_stream_8(t, h, o, v) __bs_ws_s(8,(t),(h),(o),(v)) +__generate_inline_bs_ws(bus_space_write_stream_1, bs_w_1_s, uint8_t); +__generate_inline_bs_ws(bus_space_write_stream_2, bs_w_2_s, uint16_t); +__generate_inline_bs_ws(bus_space_write_stream_4, bs_w_4_s, uint32_t); +__generate_inline_bs_ws(bus_space_write_stream_8, bs_w_8_s, uint64_t); /* * Bus write multiple operations. */ #define bus_space_write_multi_1(t, h, o, a, c) \ __bs_nonsingle(wm,1,(t),(h),(o),(a),(c)) #define bus_space_write_multi_2(t, h, o, a, c) \ __bs_nonsingle(wm,2,(t),(h),(o),(a),(c)) #define bus_space_write_multi_4(t, h, o, a, c) \ __bs_nonsingle(wm,4,(t),(h),(o),(a),(c)) #define bus_space_write_multi_8(t, h, o, a, c) \ __bs_nonsingle(wm,8,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c)) /* * Bus write region operations. */ #define bus_space_write_region_1(t, h, o, a, c) \ __bs_nonsingle(wr,1,(t),(h),(o),(a),(c)) #define bus_space_write_region_2(t, h, o, a, c) \ __bs_nonsingle(wr,2,(t),(h),(o),(a),(c)) #define bus_space_write_region_4(t, h, o, a, c) \ __bs_nonsingle(wr,4,(t),(h),(o),(a),(c)) #define bus_space_write_region_8(t, h, o, a, c) \ __bs_nonsingle(wr,8,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c)) /* * Set multiple operations. */ #define bus_space_set_multi_1(t, h, o, v, c) \ __bs_set(sm,1,(t),(h),(o),(v),(c)) #define bus_space_set_multi_2(t, h, o, v, c) \ __bs_set(sm,2,(t),(h),(o),(v),(c)) #define bus_space_set_multi_4(t, h, o, v, c) \ __bs_set(sm,4,(t),(h),(o),(v),(c)) #define bus_space_set_multi_8(t, h, o, v, c) \ __bs_set(sm,8,(t),(h),(o),(v),(c)) /* * Set region operations. */ #define bus_space_set_region_1(t, h, o, v, c) \ __bs_set(sr,1,(t),(h),(o),(v),(c)) #define bus_space_set_region_2(t, h, o, v, c) \ __bs_set(sr,2,(t),(h),(o),(v),(c)) #define bus_space_set_region_4(t, h, o, v, c) \ __bs_set(sr,4,(t),(h),(o),(v),(c)) #define bus_space_set_region_8(t, h, o, v, c) \ __bs_set(sr,8,(t),(h),(o),(v),(c)) /* * Copy operations. */ #define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ __bs_copy(1, t, h1, o1, h2, o2, c) #define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ __bs_copy(2, t, h1, o1, h2, o2, c) #define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ __bs_copy(4, t, h1, o1, h2, o2, c) #define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ __bs_copy(8, t, h1, o1, h2, o2, c) /* * Macros to provide prototypes for all the functions used in the * bus_space structure */ #define bs_map_proto(f) \ -int __bs_c(f,_bs_map) (void *t, bus_addr_t addr, \ +int __bs_c(f,_bs_map) (bus_space_tag_t t, bus_addr_t addr, \ bus_size_t size, int cacheable, bus_space_handle_t *bshp); #define bs_unmap_proto(f) \ -void __bs_c(f,_bs_unmap) (void *t, bus_space_handle_t bsh, \ +void __bs_c(f,_bs_unmap) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t size); #define bs_subregion_proto(f) \ -int __bs_c(f,_bs_subregion) (void *t, bus_space_handle_t bsh, \ +int __bs_c(f,_bs_subregion) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, bus_size_t size, \ bus_space_handle_t *nbshp); #define bs_alloc_proto(f) \ -int __bs_c(f,_bs_alloc) (void *t, bus_addr_t rstart, \ +int __bs_c(f,_bs_alloc) (bus_space_tag_t t, bus_addr_t rstart, \ bus_addr_t rend, bus_size_t size, bus_size_t align, \ bus_size_t boundary, int cacheable, bus_addr_t *addrp, \ bus_space_handle_t *bshp); #define bs_free_proto(f) \ -void __bs_c(f,_bs_free) (void *t, bus_space_handle_t bsh, \ +void __bs_c(f,_bs_free) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t size); #define bs_mmap_proto(f) \ int __bs_c(f,_bs_mmap) (struct cdev *, vm_offset_t, vm_paddr_t *, int); #define bs_barrier_proto(f) \ -void __bs_c(f,_bs_barrier) (void *t, bus_space_handle_t bsh, \ +void __bs_c(f,_bs_barrier) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, bus_size_t len, int flags); #define bs_r_1_proto(f) \ -u_int8_t __bs_c(f,_bs_r_1) (void *t, bus_space_handle_t bsh, \ +uint8_t __bs_c(f,_bs_r_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_2_proto(f) \ -u_int16_t __bs_c(f,_bs_r_2) (void *t, bus_space_handle_t bsh, \ +uint16_t __bs_c(f,_bs_r_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_4_proto(f) \ -u_int32_t __bs_c(f,_bs_r_4) (void *t, bus_space_handle_t bsh, \ +uint32_t __bs_c(f,_bs_r_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_8_proto(f) \ -u_int64_t __bs_c(f,_bs_r_8) (void *t, bus_space_handle_t bsh, \ +uint64_t __bs_c(f,_bs_r_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_1_s_proto(f) \ -u_int8_t __bs_c(f,_bs_r_1_s) (void *t, bus_space_handle_t bsh, \ +uint8_t __bs_c(f,_bs_r_1_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_2_s_proto(f) \ -u_int16_t __bs_c(f,_bs_r_2_s) (void *t, bus_space_handle_t bsh, \ +uint16_t __bs_c(f,_bs_r_2_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_4_s_proto(f) \ -u_int32_t __bs_c(f,_bs_r_4_s) (void *t, bus_space_handle_t bsh, \ +uint32_t __bs_c(f,_bs_r_4_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_w_1_proto(f) \ -void __bs_c(f,_bs_w_1) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int8_t value); +void __bs_c(f,_bs_w_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t value); #define bs_w_2_proto(f) \ -void __bs_c(f,_bs_w_2) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int16_t value); +void __bs_c(f,_bs_w_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t value); #define bs_w_4_proto(f) \ -void __bs_c(f,_bs_w_4) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int32_t value); +void __bs_c(f,_bs_w_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t value); #define bs_w_8_proto(f) \ -void __bs_c(f,_bs_w_8) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int64_t value); +void __bs_c(f,_bs_w_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t value); #define bs_w_1_s_proto(f) \ -void __bs_c(f,_bs_w_1_s) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int8_t value); +void __bs_c(f,_bs_w_1_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t value); #define bs_w_2_s_proto(f) \ -void __bs_c(f,_bs_w_2_s) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int16_t value); +void __bs_c(f,_bs_w_2_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t value); #define bs_w_4_s_proto(f) \ -void __bs_c(f,_bs_w_4_s) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int32_t value); +void __bs_c(f,_bs_w_4_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t value); #define bs_rm_1_proto(f) \ -void __bs_c(f,_bs_rm_1) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int8_t *addr, bus_size_t count); +void __bs_c(f,_bs_rm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t *addr, bus_size_t count); #define bs_rm_2_proto(f) \ -void __bs_c(f,_bs_rm_2) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int16_t *addr, bus_size_t count); +void __bs_c(f,_bs_rm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t *addr, bus_size_t count); #define bs_rm_4_proto(f) \ -void __bs_c(f,_bs_rm_4) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int32_t *addr, bus_size_t count); +void __bs_c(f,_bs_rm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t *addr, bus_size_t count); #define bs_rm_8_proto(f) \ -void __bs_c(f,_bs_rm_8) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int64_t *addr, bus_size_t count); +void __bs_c(f,_bs_rm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t *addr, bus_size_t count); #define bs_wm_1_proto(f) \ -void __bs_c(f,_bs_wm_1) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, const u_int8_t *addr, bus_size_t count); +void __bs_c(f,_bs_wm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint8_t *addr, bus_size_t count); #define bs_wm_2_proto(f) \ -void __bs_c(f,_bs_wm_2) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, const u_int16_t *addr, bus_size_t count); +void __bs_c(f,_bs_wm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint16_t *addr, bus_size_t count); #define bs_wm_4_proto(f) \ -void __bs_c(f,_bs_wm_4) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, const u_int32_t *addr, bus_size_t count); +void __bs_c(f,_bs_wm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint32_t *addr, bus_size_t count); #define bs_wm_8_proto(f) \ -void __bs_c(f,_bs_wm_8) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, const u_int64_t *addr, bus_size_t count); +void __bs_c(f,_bs_wm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint64_t *addr, bus_size_t count); #define bs_rr_1_proto(f) \ -void __bs_c(f, _bs_rr_1) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int8_t *addr, bus_size_t count); +void __bs_c(f, _bs_rr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t *addr, bus_size_t count); #define bs_rr_2_proto(f) \ -void __bs_c(f, _bs_rr_2) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int16_t *addr, bus_size_t count); +void __bs_c(f, _bs_rr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t *addr, bus_size_t count); #define bs_rr_4_proto(f) \ -void __bs_c(f, _bs_rr_4) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int32_t *addr, bus_size_t count); +void __bs_c(f, _bs_rr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t *addr, bus_size_t count); #define bs_rr_8_proto(f) \ -void __bs_c(f, _bs_rr_8) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int64_t *addr, bus_size_t count); +void __bs_c(f, _bs_rr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t *addr, bus_size_t count); #define bs_wr_1_proto(f) \ -void __bs_c(f, _bs_wr_1) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, const u_int8_t *addr, bus_size_t count); +void __bs_c(f, _bs_wr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint8_t *addr, bus_size_t count); #define bs_wr_2_proto(f) \ -void __bs_c(f, _bs_wr_2) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, const u_int16_t *addr, bus_size_t count); +void __bs_c(f, _bs_wr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint16_t *addr, bus_size_t count); #define bs_wr_4_proto(f) \ -void __bs_c(f, _bs_wr_4) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, const u_int32_t *addr, bus_size_t count); +void __bs_c(f, _bs_wr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint32_t *addr, bus_size_t count); #define bs_wr_8_proto(f) \ -void __bs_c(f, _bs_wr_8) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, const u_int64_t *addr, bus_size_t count); +void __bs_c(f, _bs_wr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, const uint64_t *addr, bus_size_t count); #define bs_sm_1_proto(f) \ -void __bs_c(f,_bs_sm_1) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int8_t value, bus_size_t count); +void __bs_c(f,_bs_sm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t value, bus_size_t count); #define bs_sm_2_proto(f) \ -void __bs_c(f,_bs_sm_2) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int16_t value, bus_size_t count); +void __bs_c(f,_bs_sm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t value, bus_size_t count); #define bs_sm_4_proto(f) \ -void __bs_c(f,_bs_sm_4) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int32_t value, bus_size_t count); +void __bs_c(f,_bs_sm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t value, bus_size_t count); #define bs_sm_8_proto(f) \ -void __bs_c(f,_bs_sm_8) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int64_t value, bus_size_t count); +void __bs_c(f,_bs_sm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t value, bus_size_t count); #define bs_sr_1_proto(f) \ -void __bs_c(f,_bs_sr_1) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int8_t value, bus_size_t count); +void __bs_c(f,_bs_sr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint8_t value, bus_size_t count); #define bs_sr_2_proto(f) \ -void __bs_c(f,_bs_sr_2) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int16_t value, bus_size_t count); +void __bs_c(f,_bs_sr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint16_t value, bus_size_t count); #define bs_sr_4_proto(f) \ -void __bs_c(f,_bs_sr_4) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int32_t value, bus_size_t count); +void __bs_c(f,_bs_sr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint32_t value, bus_size_t count); #define bs_sr_8_proto(f) \ -void __bs_c(f,_bs_sr_8) (void *t, bus_space_handle_t bsh, \ - bus_size_t offset, u_int64_t value, bus_size_t count); +void __bs_c(f,_bs_sr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ + bus_size_t offset, uint64_t value, bus_size_t count); #define bs_c_1_proto(f) \ -void __bs_c(f,_bs_c_1) (void *t, bus_space_handle_t bsh1, \ +void __bs_c(f,_bs_c_1) (bus_space_tag_t t, bus_space_handle_t bsh1, \ bus_size_t offset1, bus_space_handle_t bsh2, \ bus_size_t offset2, bus_size_t count); #define bs_c_2_proto(f) \ -void __bs_c(f,_bs_c_2) (void *t, bus_space_handle_t bsh1, \ +void __bs_c(f,_bs_c_2) (bus_space_tag_t t, bus_space_handle_t bsh1, \ bus_size_t offset1, bus_space_handle_t bsh2, \ bus_size_t offset2, bus_size_t count); #define bs_c_4_proto(f) \ -void __bs_c(f,_bs_c_4) (void *t, bus_space_handle_t bsh1, \ +void __bs_c(f,_bs_c_4) (bus_space_tag_t t, bus_space_handle_t bsh1, \ bus_size_t offset1, bus_space_handle_t bsh2, \ bus_size_t offset2, bus_size_t count); #define bs_c_8_proto(f) \ -void __bs_c(f,_bs_c_8) (void *t, bus_space_handle_t bsh1, \ +void __bs_c(f,_bs_c_8) (bus_space_tag_t t, bus_space_handle_t bsh1, \ bus_size_t offset1, bus_space_handle_t bsh2, \ bus_size_t offset2, bus_size_t count); #define bs_protos(f) \ bs_map_proto(f); \ bs_unmap_proto(f); \ bs_subregion_proto(f); \ bs_alloc_proto(f); \ bs_free_proto(f); \ bs_mmap_proto(f); \ bs_barrier_proto(f); \ bs_r_1_proto(f); \ bs_r_2_proto(f); \ bs_r_4_proto(f); \ bs_r_8_proto(f); \ bs_r_1_s_proto(f); \ bs_r_2_s_proto(f); \ bs_r_4_s_proto(f); \ bs_w_1_proto(f); \ bs_w_2_proto(f); \ bs_w_4_proto(f); \ bs_w_8_proto(f); \ bs_w_1_s_proto(f); \ bs_w_2_s_proto(f); \ bs_w_4_s_proto(f); \ bs_rm_1_proto(f); \ bs_rm_2_proto(f); \ bs_rm_4_proto(f); \ bs_rm_8_proto(f); \ bs_wm_1_proto(f); \ bs_wm_2_proto(f); \ bs_wm_4_proto(f); \ bs_wm_8_proto(f); \ bs_rr_1_proto(f); \ bs_rr_2_proto(f); \ bs_rr_4_proto(f); \ bs_rr_8_proto(f); \ bs_wr_1_proto(f); \ bs_wr_2_proto(f); \ bs_wr_4_proto(f); \ bs_wr_8_proto(f); \ bs_sm_1_proto(f); \ bs_sm_2_proto(f); \ bs_sm_4_proto(f); \ bs_sm_8_proto(f); \ bs_sr_1_proto(f); \ bs_sr_2_proto(f); \ bs_sr_4_proto(f); \ bs_sr_8_proto(f); \ bs_c_1_proto(f); \ bs_c_2_proto(f); \ bs_c_4_proto(f); \ bs_c_8_proto(f); + +void generic_bs_unimplemented(void); +#define BS_UNIMPLEMENTED (void *)generic_bs_unimplemented #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) #define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF #define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF #define BUS_SPACE_MAXADDR 0xFFFFFFFF #define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF #define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF #define BUS_SPACE_MAXSIZE 0xFFFFFFFF #define BUS_SPACE_UNRESTRICTED (~0) #include /* * Get the physical address of a bus space memory-mapped resource. * Doing this as a macro is a temporary solution until a more robust fix is * designed. It also serves to mark the locations needing that fix. */ #define BUS_SPACE_PHYSADDR(res, offs) \ ((u_int)(rman_get_start(res)+(offs))) #endif /* _MACHINE_BUS_H_ */ Index: stable/10/sys/arm/lpc/lpc_space.c =================================================================== --- stable/10/sys/arm/lpc/lpc_space.c (revision 278726) +++ stable/10/sys/arm/lpc/lpc_space.c (nonexistent) @@ -1,147 +0,0 @@ -/*- - * Copyright (c) 2011 Jakub Wojciech Klama - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include - -bs_protos(generic); -bs_protos(generic_armv4); - -static struct bus_space _base_tag = { - /* cookie */ - NULL, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - generic_bs_alloc, - generic_bs_free, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read (multiple) */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - NULL, - NULL, - NULL, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - NULL, - NULL, - NULL, - - /* copy */ - NULL, - NULL, - NULL, - NULL, - - /* read stream (single) */ - NULL, - NULL, - NULL, - NULL, - - /* read multiple stream */ - NULL, - generic_armv4_bs_rm_2, - NULL, - NULL, - - /* read region stream */ - NULL, - NULL, - NULL, - NULL, - - /* write stream (single) */ - NULL, - NULL, - NULL, - NULL, - - /* write multiple stream */ - NULL, - generic_armv4_bs_wm_2, - NULL, - NULL, - - /* write region stream */ - NULL, - NULL, - NULL, - NULL, -}; - -bus_space_tag_t fdtbus_bs_tag = &_base_tag; Property changes on: stable/10/sys/arm/lpc/lpc_space.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/lpc/files.lpc =================================================================== --- stable/10/sys/arm/lpc/files.lpc (revision 278726) +++ stable/10/sys/arm/lpc/files.lpc (revision 278727) @@ -1,20 +1,20 @@ # $FreeBSD$ +arm/arm/bus_space_base.c standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_arm9.S standard arm/arm/cpufunc_asm_armv5.S standard arm/lpc/lpc_machdep.c standard -arm/lpc/lpc_space.c standard arm/lpc/lpc_pwr.c standard arm/lpc/lpc_intc.c standard arm/lpc/lpc_timer.c standard arm/lpc/lpc_rtc.c standard arm/lpc/if_lpe.c optional lpe arm/lpc/lpc_ohci.c optional ohci arm/lpc/lpc_mmc.c optional lpcmmc arm/lpc/lpc_fb.c optional lpcfb arm/lpc/lpc_gpio.c optional lpcgpio arm/lpc/lpc_spi.c optional lpcspi arm/lpc/lpc_dmac.c optional dmac arm/lpc/ssd1289.c optional ssd1289 dev/uart/uart_dev_lpc.c optional uart kern/kern_clocksource.c standard Index: stable/10/sys/arm/mv/bus_space.c =================================================================== --- stable/10/sys/arm/mv/bus_space.c (revision 278726) +++ stable/10/sys/arm/mv/bus_space.c (nonexistent) @@ -1,162 +0,0 @@ -/*- - * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. - * All rights reserved. - * - * Developed by Semihalf. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of MARVELL nor the names of contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include - -#include - -/* - * Bus space functions for Marvell SoC family - */ - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); -bs_protos(generic_armv4); - -/* - * The bus space tag. This is constant for all instances, so - * we never have to explicitly "create" it. - */ -static struct bus_space _base_tag = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - generic_bs_alloc, - generic_bs_free, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - NULL, - NULL, - NULL, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - NULL, - NULL, - NULL, - - /* copy */ - NULL, - NULL, - NULL, - NULL, - - /* read stream (single) */ - NULL, - NULL, - NULL, - NULL, - - /* read multiple stream */ - NULL, - generic_armv4_bs_rm_2, /* bus_space_read_multi_stream_2 */ - NULL, - NULL, - - /* read region stream */ - NULL, - NULL, - NULL, - NULL, - - /* write stream (single) */ - NULL, - NULL, - NULL, - NULL, - - /* write multiple stream */ - NULL, - generic_armv4_bs_wm_2, /* bus_space_write_multi_stream_2 */ - NULL, - NULL, - - /* write region stream */ - NULL, - NULL, - NULL, - NULL -}; - -bus_space_tag_t fdtbus_bs_tag = &_base_tag; Property changes on: stable/10/sys/arm/mv/bus_space.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/mv/files.mv =================================================================== --- stable/10/sys/arm/mv/files.mv (revision 278726) +++ stable/10/sys/arm/mv/files.mv (revision 278727) @@ -1,42 +1,42 @@ # $FreeBSD$ # # The Marvell CPU cores # - Compliant with V5TE architecture # - Super scalar dual issue CPU # - Big/Little Endian # - MMU/MPU # - L1 Cache: Supports streaming and write allocate # - Variable pipeline stages # - Out-of-order execution # - Branch Prediction # - JTAG/ICE # - Vector Floating Point (VFP) unit # +arm/arm/bus_space_base.c standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_armv5_ec.S standard arm/arm/cpufunc_asm_armv7.S standard arm/arm/cpufunc_asm_sheeva.S standard arm/arm/cpufunc_asm_pj4b.S standard -arm/mv/bus_space.c standard arm/mv/gpio.c standard arm/mv/mv_common.c standard arm/mv/mv_localbus.c standard arm/mv/mv_machdep.c standard arm/mv/mv_pci.c optional pci arm/mv/mv_sata.c optional ata | atamvsata arm/mv/mv_ts.c standard arm/mv/timer.c standard arm/mv/twsi.c optional iicbus dev/cesa/cesa.c optional cesa dev/mge/if_mge.c optional mge dev/nand/nfc_mv.c optional nand dev/mvs/mvs_soc.c optional mvs dev/uart/uart_dev_ns8250.c optional uart dev/usb/controller/ehci_mv.c optional ehci kern/kern_clocksource.c standard Index: stable/10/sys/arm/rockchip/files.rk30xx =================================================================== --- stable/10/sys/arm/rockchip/files.rk30xx (revision 278726) +++ stable/10/sys/arm/rockchip/files.rk30xx (revision 278727) @@ -1,22 +1,22 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard arm/arm/gic.c standard arm/arm/mpcore_timer.c standard -arm/arm/bus_space-v6.c standard +arm/arm/bus_space_base.c standard arm/rockchip/rk30xx_common.c standard arm/rockchip/rk30xx_machdep.c standard arm/rockchip/rk30xx_pmu.c standard arm/rockchip/rk30xx_grf.c standard arm/rockchip/rk30xx_wdog.c standard arm/rockchip/rk30xx_gpio.c optional gpio dev/usb/controller/dwc_otg_fdt.c optional dwcotg arm/rockchip/rk30xx_mp.c optional smp Index: stable/10/sys/arm/samsung/exynos/files.exynos5 =================================================================== --- stable/10/sys/arm/samsung/exynos/files.exynos5 (revision 278726) +++ stable/10/sys/arm/samsung/exynos/files.exynos5 (revision 278727) @@ -1,31 +1,31 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/arm/bus_space_generic.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard -arm/arm/bus_space-v6.c standard +arm/arm/bus_space_base.c standard arm/arm/gic.c standard arm/arm/generic_timer.c standard arm/samsung/exynos/exynos5_mct.c standard arm/samsung/exynos/exynos5_mp.c optional smp arm/samsung/exynos/exynos5_common.c standard arm/samsung/exynos/exynos5_machdep.c standard arm/samsung/exynos/exynos5_combiner.c standard arm/samsung/exynos/exynos5_pad.c optional gpio arm/samsung/exynos/uart.c optional uart arm/samsung/exynos/exynos5_ehci.c optional ehci arm/samsung/exynos/exynos5_fimd.c optional vt arm/samsung/exynos/exynos5_i2c.c optional iicbus # chromebook drivers arm/samsung/exynos/chrome_ec.c optional chrome_ec arm/samsung/exynos/chrome_kb.c optional chrome_kb #dev/sdhci/sdhci_fdt.c optional sdhci Index: stable/10/sys/arm/samsung/s3c2xx0/s3c2xx0_space.c =================================================================== --- stable/10/sys/arm/samsung/s3c2xx0/s3c2xx0_space.c (revision 278726) +++ stable/10/sys/arm/samsung/s3c2xx0/s3c2xx0_space.c (nonexistent) @@ -1,165 +0,0 @@ -/* $NetBSD: s3c2xx0_space.c,v 1.7 2005/11/24 13:08:32 yamt Exp $ */ - -/* - * Copyright (c) 2002 Fujitsu Component Limited - * Copyright (c) 2002 Genetec Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of The Fujitsu Component Limited nor the name of - * Genetec corporation may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC - * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC - * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT - * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -/* derived from sa11x0_io.c */ - -/* - * Copyright (c) 1997 Mark Brinicombe. - * Copyright (c) 1997 Causality Limited. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Ichiro FUKUHARA. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Mark Brinicombe. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * bus_space functions for Samsung S3C2800/2400/2410. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); -bs_protos(generic_armv4); - -struct bus_space s3c2xx0_bs_tag = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - generic_bs_alloc, /* not implemented */ - generic_bs_free, /* not implemented */ - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - generic_bs_wr_1, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - generic_bs_sr_1, - generic_armv4_bs_sr_2, - NULL, - NULL, - - /* copy */ - NULL, - generic_armv4_bs_c_2, - NULL, - NULL, -}; - Property changes on: stable/10/sys/arm/samsung/s3c2xx0/s3c2xx0_space.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/samsung/s3c2xx0/files.s3c2xx0 =================================================================== --- stable/10/sys/arm/samsung/s3c2xx0/files.s3c2xx0 (revision 278726) +++ stable/10/sys/arm/samsung/s3c2xx0/files.s3c2xx0 (revision 278727) @@ -1,15 +1,15 @@ # $FreeBSD$ +arm/arm/bus_space_base.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_arm9.S standard arm/samsung/s3c2xx0/board_ln2410sbc.c optional board_ln2410sbc arm/samsung/s3c2xx0/s3c24x0_rtc.c standard arm/samsung/s3c2xx0/s3c24x0_machdep.c standard arm/samsung/s3c2xx0/s3c24x0.c standard -arm/samsung/s3c2xx0/s3c2xx0_space.c standard arm/samsung/s3c2xx0/s3c24x0_clk.c standard arm/samsung/s3c2xx0/uart_bus_s3c2410.c optional uart arm/samsung/s3c2xx0/uart_cpu_s3c2410.c optional uart arm/samsung/s3c2xx0/uart_dev_s3c2410.c optional uart dev/usb/controller/ohci_s3c24x0.c optional ohci Index: stable/10/sys/arm/samsung/s3c2xx0/s3c24x0.c =================================================================== --- stable/10/sys/arm/samsung/s3c2xx0/s3c24x0.c (revision 278726) +++ stable/10/sys/arm/samsung/s3c2xx0/s3c24x0.c (revision 278727) @@ -1,799 +1,802 @@ /* $NetBSD: s3c2410.c,v 1.4 2003/08/27 03:46:05 bsh Exp $ */ /* * Copyright (c) 2003 Genetec corporation. All rights reserved. * Written by Hiroyuki Bessho for Genetec corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of Genetec corporation may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define S3C2XX0_XTAL_CLK 12000000 +bus_space_tag_t s3c2xx0_bs_tag; + #define IPL_LEVELS 13 u_int irqmasks[IPL_LEVELS]; static struct { uint32_t idcode; const char *name; s3c2xx0_cpu cpu; } s3c2x0_cpu_id[] = { { CHIPID_S3C2410A, "S3C2410A", CPU_S3C2410 }, { CHIPID_S3C2440A, "S3C2440A", CPU_S3C2440 }, { CHIPID_S3C2442B, "S3C2442B", CPU_S3C2440 }, { 0, NULL } }; static struct { const char *name; int prio; int unit; struct { int type; u_long start; u_long count; } res[2]; } s3c24x0_children[] = { { "rtc", 0, -1, { { SYS_RES_IOPORT, S3C24X0_RTC_PA_BASE, S3C24X0_RTC_SIZE }, { 0 }, } }, { "timer", 0, -1, { { 0 }, } }, { "uart", 1, 0, { { SYS_RES_IRQ, S3C24X0_INT_UART0, 1 }, { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(0), S3C24X0_UART_BASE(1) - S3C24X0_UART_BASE(0) }, } }, { "uart", 1, 1, { { SYS_RES_IRQ, S3C24X0_INT_UART1, 1 }, { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(1), S3C24X0_UART_BASE(2) - S3C24X0_UART_BASE(1) }, } }, { "uart", 1, 2, { { SYS_RES_IRQ, S3C24X0_INT_UART2, 1 }, { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(2), S3C24X0_UART_BASE(3) - S3C24X0_UART_BASE(2) }, } }, { "ohci", 0, -1, { { SYS_RES_IRQ, S3C24X0_INT_USBH, 0 }, { SYS_RES_IOPORT, S3C24X0_USBHC_PA_BASE, S3C24X0_USBHC_SIZE }, } }, { NULL }, }; /* prototypes */ static device_t s3c24x0_add_child(device_t, int, const char *, int); static int s3c24x0_probe(device_t); static int s3c24x0_attach(device_t); static void s3c24x0_identify(driver_t *, device_t); static int s3c24x0_setup_intr(device_t, device_t, struct resource *, int, driver_filter_t *, driver_intr_t *, void *, void **); static int s3c24x0_teardown_intr(device_t, device_t, struct resource *, void *); static int s3c24x0_config_intr(device_t, int, enum intr_trigger, enum intr_polarity); static struct resource *s3c24x0_alloc_resource(device_t, device_t, int, int *, u_long, u_long, u_long, u_int); static int s3c24x0_activate_resource(device_t, device_t, int, int, struct resource *); static int s3c24x0_release_resource(device_t, device_t, int, int, struct resource *); static struct resource_list *s3c24x0_get_resource_list(device_t, device_t); static void s3c24x0_identify_cpu(device_t); static device_method_t s3c24x0_methods[] = { DEVMETHOD(device_probe, s3c24x0_probe), DEVMETHOD(device_attach, s3c24x0_attach), DEVMETHOD(device_identify, s3c24x0_identify), DEVMETHOD(bus_setup_intr, s3c24x0_setup_intr), DEVMETHOD(bus_teardown_intr, s3c24x0_teardown_intr), DEVMETHOD(bus_config_intr, s3c24x0_config_intr), DEVMETHOD(bus_alloc_resource, s3c24x0_alloc_resource), DEVMETHOD(bus_activate_resource, s3c24x0_activate_resource), DEVMETHOD(bus_release_resource, s3c24x0_release_resource), DEVMETHOD(bus_get_resource_list,s3c24x0_get_resource_list), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), {0, 0}, }; static driver_t s3c24x0_driver = { "s3c24x0", s3c24x0_methods, sizeof(struct s3c24x0_softc), }; static devclass_t s3c24x0_devclass; DRIVER_MODULE(s3c24x0, nexus, s3c24x0_driver, s3c24x0_devclass, 0, 0); struct s3c2xx0_softc *s3c2xx0_softc = NULL; static device_t s3c24x0_add_child(device_t bus, int prio, const char *name, int unit) { device_t child; struct s3c2xx0_ivar *ivar; child = device_add_child_ordered(bus, prio, name, unit); if (child == NULL) return (NULL); ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO); if (ivar == NULL) { device_delete_child(bus, child); printf("Can't add alloc ivar\n"); return (NULL); } device_set_ivars(child, ivar); resource_list_init(&ivar->resources); return (child); } static void s3c24x0_enable_ext_intr(unsigned int irq) { uint32_t reg, value; int offset; if (irq <= 7) { reg = GPIO_PFCON; offset = irq * 2; } else if (irq <= 23) { reg = GPIO_PGCON; offset = (irq - 8) * 2; } else return; /* Make the pin an interrupt source */ value = bus_space_read_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, reg); value &= ~(3 << offset); value |= 2 << offset; bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, reg, value); } static int s3c24x0_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error, irq; error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep); if (error != 0) return (error); for (irq = rman_get_start(ires); irq <= rman_get_end(ires); irq++) { if (irq >= S3C24X0_EXTIRQ_MIN && irq <= S3C24X0_EXTIRQ_MAX) { /* Enable the external interrupt pin */ s3c24x0_enable_ext_intr(irq - S3C24X0_EXTIRQ_MIN); } } return (0); } static int s3c24x0_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static int s3c24x0_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol) { uint32_t mask, reg, value; int offset; /* Only external interrupts can be configured */ if (irq < S3C24X0_EXTIRQ_MIN || irq > S3C24X0_EXTIRQ_MAX) return (EINVAL); /* There is no standard trigger or polarity for the bus */ if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) return (EINVAL); irq -= S3C24X0_EXTIRQ_MIN; /* Get the bits to set */ mask = 0; if (pol == INTR_POLARITY_LOW) { mask = 2; } else if (pol == INTR_POLARITY_HIGH) { mask = 4; } if (trig == INTR_TRIGGER_LEVEL) { mask >>= 2; } /* Get the register to set */ if (irq <= 7) { reg = GPIO_EXTINT(0); offset = irq * 4; } else if (irq <= 15) { reg = GPIO_EXTINT(1); offset = (irq - 8) * 4; } else if (irq <= 23) { reg = GPIO_EXTINT(2); offset = (irq - 16) * 4; } else { return (EINVAL); } /* Set the new signaling method */ value = bus_space_read_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, reg); value &= ~(7 << offset); value |= mask << offset; bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, reg, value); return (0); } static struct resource * s3c24x0_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct resource_list_entry *rle; struct s3c2xx0_ivar *ivar = device_get_ivars(child); struct resource_list *rl = &ivar->resources; struct resource *res = NULL; if (device_get_parent(child) != bus) return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, rid, start, end, count, flags)); rle = resource_list_find(rl, type, *rid); if (rle != NULL) { /* There is a resource list. Use it */ if (rle->res) panic("Resource rid %d type %d already in use", *rid, type); if (start == 0UL && end == ~0UL) { start = rle->start; count = ulmax(count, rle->count); end = ulmax(rle->end, start + count - 1); } /* * When allocating an irq with children irq's really * allocate the children as it is those we are interested * in receiving, not the parent. */ if (type == SYS_RES_IRQ && start == end) { switch (start) { case S3C24X0_INT_ADCTC: start = S3C24X0_INT_TC; end = S3C24X0_INT_ADC; break; #ifdef S3C2440_INT_CAM case S3C2440_INT_CAM: start = S3C2440_INT_CAM_C; end = S3C2440_INT_CAM_P; break; #endif default: break; } count = end - start + 1; } } switch (type) { case SYS_RES_IRQ: res = rman_reserve_resource( &s3c2xx0_softc->s3c2xx0_irq_rman, start, end, count, flags, child); break; case SYS_RES_IOPORT: case SYS_RES_MEMORY: res = rman_reserve_resource( &s3c2xx0_softc->s3c2xx0_mem_rman, start, end, count, flags, child); if (res == NULL) panic("Unable to map address space %#lX-%#lX", start, end); - rman_set_bustag(res, &s3c2xx0_bs_tag); + rman_set_bustag(res, s3c2xx0_bs_tag); rman_set_bushandle(res, start); if (flags & RF_ACTIVE) { if (bus_activate_resource(child, type, *rid, res)) { rman_release_resource(res); return (NULL); } } break; } if (res != NULL) { rman_set_rid(res, *rid); if (rle != NULL) { rle->res = res; rle->start = rman_get_start(res); rle->end = rman_get_end(res); rle->count = count; } } return (res); } static int s3c24x0_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { bus_space_handle_t p; int error; if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { error = bus_space_map(rman_get_bustag(r), rman_get_bushandle(r), rman_get_size(r), 0, &p); if (error) return (error); rman_set_bushandle(r, p); } return (rman_activate_resource(r)); } static int s3c24x0_release_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { struct s3c2xx0_ivar *ivar = device_get_ivars(child); struct resource_list *rl = &ivar->resources; struct resource_list_entry *rle; if (rl == NULL) return (EINVAL); rle = resource_list_find(rl, type, rid); if (rle == NULL) return (EINVAL); rman_release_resource(r); rle->res = NULL; return 0; } static struct resource_list * s3c24x0_get_resource_list(device_t dev, device_t child) { struct s3c2xx0_ivar *ivar; ivar = device_get_ivars(child); return (&(ivar->resources)); } void s3c24x0_identify(driver_t *driver, device_t parent) { BUS_ADD_CHILD(parent, 0, "s3c24x0", 0); } int s3c24x0_probe(device_t dev) { return (BUS_PROBE_NOWILDCARD); } int s3c24x0_attach(device_t dev) { struct s3c24x0_softc *sc = device_get_softc(dev); bus_space_tag_t iot; device_t child; unsigned int i, j; u_long irqmax; + s3c2xx0_bs_tag = arm_base_bs_tag; s3c2xx0_softc = &(sc->sc_sx); - sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag; + sc->sc_sx.sc_iot = iot = s3c2xx0_bs_tag; s3c2xx0_softc->s3c2xx0_irq_rman.rm_type = RMAN_ARRAY; s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C24X0 IRQs"; s3c2xx0_softc->s3c2xx0_mem_rman.rm_type = RMAN_ARRAY; s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C24X0 Device Registers"; /* Manage the registor memory space */ if ((rman_init(&s3c2xx0_softc->s3c2xx0_mem_rman) != 0) || (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman, S3C24X0_DEV_VA_OFFSET, S3C24X0_DEV_VA_OFFSET + S3C24X0_DEV_VA_SIZE) != 0) || (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman, S3C24X0_DEV_START, S3C24X0_DEV_STOP) != 0)) panic("s3c24x0_attach: failed to set up register rman"); /* These are needed for things without a proper device to attach to */ sc->sc_sx.sc_intctl_ioh = S3C24X0_INTCTL_BASE; sc->sc_sx.sc_gpio_ioh = S3C24X0_GPIO_BASE; sc->sc_sx.sc_clkman_ioh = S3C24X0_CLKMAN_BASE; sc->sc_sx.sc_wdt_ioh = S3C24X0_WDT_BASE; sc->sc_timer_ioh = S3C24X0_TIMER_BASE; /* * Identify the CPU */ s3c24x0_identify_cpu(dev); /* * Manage the interrupt space. * We need to put this after s3c24x0_identify_cpu as the avaliable * interrupts change depending on which CPU we have. */ if (sc->sc_sx.sc_cpu == CPU_S3C2410) irqmax = S3C2410_SUBIRQ_MAX; else irqmax = S3C2440_SUBIRQ_MAX; if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 || rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0, irqmax) != 0 || rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, S3C24X0_EXTIRQ_MIN, S3C24X0_EXTIRQ_MAX)) panic("s3c24x0_attach: failed to set up IRQ rman"); /* calculate current clock frequency */ s3c24x0_clock_freq(&sc->sc_sx); device_printf(dev, "fclk %d MHz hclk %d MHz pclk %d MHz\n", sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000, sc->sc_sx.sc_pclk / 1000000); /* * Attach children devices */ for (i = 0; s3c24x0_children[i].name != NULL; i++) { child = s3c24x0_add_child(dev, s3c24x0_children[i].prio, s3c24x0_children[i].name, s3c24x0_children[i].unit); for (j = 0; j < sizeof(s3c24x0_children[i].res) / sizeof(s3c24x0_children[i].res[0]) && s3c24x0_children[i].res[j].type != 0; j++) { bus_set_resource(child, s3c24x0_children[i].res[j].type, 0, s3c24x0_children[i].res[j].start, s3c24x0_children[i].res[j].count); } } bus_generic_probe(dev); bus_generic_attach(dev); return (0); } static void s3c24x0_identify_cpu(device_t dev) { struct s3c24x0_softc *sc = device_get_softc(dev); uint32_t idcode; int i; idcode = bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_gpio_ioh, GPIO_GSTATUS1); for (i = 0; s3c2x0_cpu_id[i].name != NULL; i++) { if (s3c2x0_cpu_id[i].idcode == idcode) break; } if (s3c2x0_cpu_id[i].name == NULL) panic("Unknown CPU detected ((Chip ID: %#X)", idcode); device_printf(dev, "Found %s CPU (Chip ID: %#X)\n", s3c2x0_cpu_id[i].name, idcode); sc->sc_sx.sc_cpu = s3c2x0_cpu_id[i].cpu; } /* * fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register. * * s3c24{1,4}0_clock_freq2() is meant to be called from kernel startup routines. * s3c24x0_clock_freq() is for after kernel initialization is done. * * Because they can be called before bus_space is available we need to use * volatile pointers rather than bus_space_read. */ void s3c2410_clock_freq2(vm_offset_t clkman_base, int *fclk, int *hclk, int *pclk) { uint32_t pllcon, divn; unsigned int mdiv, pdiv, sdiv; unsigned int f, h, p; pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON); divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN); mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT; sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT; f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)); h = f; if (divn & S3C2410_CLKDIVN_HDIVN) h /= 2; p = h; if (divn & CLKDIVN_PDIVN) p /= 2; if (fclk) *fclk = f; if (hclk) *hclk = h; if (pclk) *pclk = p; } void s3c2440_clock_freq2(vm_offset_t clkman_base, int *fclk, int *hclk, int *pclk) { uint32_t pllcon, divn, camdivn; unsigned int mdiv, pdiv, sdiv; unsigned int f, h, p; pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON); divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN); camdivn = *(volatile uint32_t *)(clkman_base + S3C2440_CLKMAN_CAMDIVN); mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT; sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT; f = (2 * (mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)); h = f; switch((divn >> 1) & 3) { case 0: break; case 1: h /= 2; break; case 2: if ((camdivn & S3C2440_CAMDIVN_HCLK4_HALF) == S3C2440_CAMDIVN_HCLK4_HALF) h /= 8; else h /= 4; break; case 3: if ((camdivn & S3C2440_CAMDIVN_HCLK3_HALF) == S3C2440_CAMDIVN_HCLK3_HALF) h /= 6; else h /= 3; break; } p = h; if (divn & CLKDIVN_PDIVN) p /= 2; if (fclk) *fclk = f; if (hclk) *hclk = h; if (pclk) *pclk = p; } void s3c24x0_clock_freq(struct s3c2xx0_softc *sc) { vm_offset_t va; va = sc->sc_clkman_ioh; switch(sc->sc_cpu) { case CPU_S3C2410: s3c2410_clock_freq2(va, &sc->sc_fclk, &sc->sc_hclk, &sc->sc_pclk); break; case CPU_S3C2440: s3c2440_clock_freq2(va, &sc->sc_fclk, &sc->sc_hclk, &sc->sc_pclk); break; } } void cpu_reset(void) { (void) disable_interrupts(PSR_I|PSR_F); - bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_wdt_ioh, WDT_WTCON, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_wdt_ioh, WDT_WTCON, WTCON_ENABLE | WTCON_CLKSEL_16 | WTCON_ENRST); for(;;); } void s3c24x0_sleep(int mode __unused) { int reg; - reg = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh, + reg = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh, CLKMAN_CLKCON); - bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh, CLKMAN_CLKCON, reg | CLKCON_IDLE); } int arm_get_next_irq(int last __unused) { uint32_t intpnd; int irq, subirq; - if ((irq = bus_space_read_4(&s3c2xx0_bs_tag, + if ((irq = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTOFFSET)) != 0) { /* Clear the pending bit */ - intpnd = bus_space_read_4(&s3c2xx0_bs_tag, + intpnd = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTPND); - bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_SRCPND, intpnd); - bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTPND, intpnd); switch (irq) { case S3C24X0_INT_ADCTC: case S3C24X0_INT_UART0: case S3C24X0_INT_UART1: case S3C24X0_INT_UART2: /* Find the sub IRQ */ subirq = 0x7ff; - subirq &= bus_space_read_4(&s3c2xx0_bs_tag, + subirq &= bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND); - subirq &= ~(bus_space_read_4(&s3c2xx0_bs_tag, + subirq &= ~(bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK)); if (subirq == 0) return (irq); subirq = ffs(subirq) - 1; /* Clear the sub irq pending bit */ - bus_space_write_4(&s3c2xx0_bs_tag, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND, (1 << subirq)); /* * Return the parent IRQ for UART * as it is all we ever need */ if (subirq <= 8) return (irq); return (S3C24X0_SUBIRQ_MIN + subirq); case S3C24X0_INT_0: case S3C24X0_INT_1: case S3C24X0_INT_2: case S3C24X0_INT_3: /* There is a 1:1 mapping to the IRQ we are handling */ return S3C24X0_INT_EXT(irq); case S3C24X0_INT_4_7: case S3C24X0_INT_8_23: /* Find the external interrupt being called */ subirq = 0x7fffff; - subirq &= bus_space_read_4(&s3c2xx0_bs_tag, + subirq &= bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND); - subirq &= ~bus_space_read_4(&s3c2xx0_bs_tag, + subirq &= ~bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK); if (subirq == 0) return (irq); subirq = ffs(subirq) - 1; /* Clear the external irq pending bit */ - bus_space_write_4(&s3c2xx0_bs_tag, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND, (1 << subirq)); return S3C24X0_INT_EXT(subirq); } return (irq); } return (-1); } void arm_mask_irq(uintptr_t irq) { u_int32_t mask; if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) { /* External interrupt 0..3 are directly mapped to irq 0..3 */ irq -= S3C24X0_EXTIRQ_MIN; } if (irq < S3C24X0_SUBIRQ_MIN) { - mask = bus_space_read_4(&s3c2xx0_bs_tag, + mask = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK); mask |= (1 << irq); - bus_space_write_4(&s3c2xx0_bs_tag, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask); } else if (irq < S3C24X0_EXTIRQ_MIN) { - mask = bus_space_read_4(&s3c2xx0_bs_tag, + mask = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK); mask |= (1 << (irq - S3C24X0_SUBIRQ_MIN)); - bus_space_write_4(&s3c2xx0_bs_tag, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask); } else { - mask = bus_space_read_4(&s3c2xx0_bs_tag, + mask = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK); mask |= (1 << (irq - S3C24X0_EXTIRQ_MIN)); - bus_space_write_4(&s3c2xx0_bs_tag, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask); } } void arm_unmask_irq(uintptr_t irq) { u_int32_t mask; if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) { /* External interrupt 0..3 are directly mapped to irq 0..3 */ irq -= S3C24X0_EXTIRQ_MIN; } if (irq < S3C24X0_SUBIRQ_MIN) { - mask = bus_space_read_4(&s3c2xx0_bs_tag, + mask = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK); mask &= ~(1 << irq); - bus_space_write_4(&s3c2xx0_bs_tag, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask); } else if (irq < S3C24X0_EXTIRQ_MIN) { - mask = bus_space_read_4(&s3c2xx0_bs_tag, + mask = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK); mask &= ~(1 << (irq - S3C24X0_SUBIRQ_MIN)); - bus_space_write_4(&s3c2xx0_bs_tag, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask); } else { - mask = bus_space_read_4(&s3c2xx0_bs_tag, + mask = bus_space_read_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK); mask &= ~(1 << (irq - S3C24X0_EXTIRQ_MIN)); - bus_space_write_4(&s3c2xx0_bs_tag, + bus_space_write_4(s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask); } } Index: stable/10/sys/arm/samsung/s3c2xx0/s3c2xx0var.h =================================================================== --- stable/10/sys/arm/samsung/s3c2xx0/s3c2xx0var.h (revision 278726) +++ stable/10/sys/arm/samsung/s3c2xx0/s3c2xx0var.h (revision 278727) @@ -1,84 +1,84 @@ /* $NetBSD: s3c2xx0var.h,v 1.3 2003/08/05 11:26:54 bsh Exp $ */ /*- * Copyright (c) 2002 Fujitsu Component Limited * Copyright (c) 2002 Genetec Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of The Fujitsu Component Limited nor the name of * Genetec corporation may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _ARM_S3C2XX0VAR_H_ #define _ARM_S3C2XX0VAR_H_ #include #include typedef enum { CPU_S3C2410, CPU_S3C2440, } s3c2xx0_cpu; struct s3c2xx0_softc { device_t sc_dev; s3c2xx0_cpu sc_cpu; bus_space_tag_t sc_iot; bus_space_handle_t sc_intctl_ioh; bus_space_handle_t sc_gpio_ioh; /* GPIO */ bus_space_handle_t sc_clkman_ioh; /* Clock manager */ bus_space_handle_t sc_wdt_ioh; /* Watchdog Timer */ bus_dma_tag_t sc_dmat; /* clock frequency */ int sc_fclk; /* CPU clock */ int sc_hclk; /* AHB bus clock */ int sc_pclk; /* peripheral clock */ struct rman s3c2xx0_irq_rman; struct rman s3c2xx0_mem_rman; }; struct s3c2xx0_ivar { struct resource_list resources; }; typedef void *s3c2xx0_chipset_tag_t; -extern struct bus_space s3c2xx0_bs_tag; +extern bus_space_tag_t s3c2xx0_bs_tag; extern struct s3c2xx0_softc *s3c2xx0_softc; extern struct arm32_bus_dma_tag s3c2xx0_bus_dma; /* Platform needs to provide this */ bus_dma_tag_t s3c2xx0_bus_dma_init(struct arm32_bus_dma_tag *); #endif /* _ARM_S3C2XX0VAR_H_ */ Index: stable/10/sys/arm/samsung/s3c2xx0/uart_cpu_s3c2410.c =================================================================== --- stable/10/sys/arm/samsung/s3c2xx0/uart_cpu_s3c2410.c (revision 278726) +++ stable/10/sys/arm/samsung/s3c2xx0/uart_cpu_s3c2410.c (revision 278727) @@ -1,76 +1,76 @@ /* * Copyright (c) 2003 Marcel Moolenaar * Copyright (c) 2007 Andrew Turner * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; extern struct uart_ops uart_s3c2410_ops; vm_offset_t s3c2410_uart_vaddr; unsigned int s3c2410_pclk; int uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) { return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); } int uart_cpu_getdev(int devtype, struct uart_devinfo *di) { if (devtype != UART_DEV_CONSOLE) return (ENXIO); di->ops = uart_getops(&uart_s3c2410_class); di->bas.chan = 0; - di->bas.bst = &s3c2xx0_bs_tag; + di->bas.bst = s3c2xx0_bs_tag; di->bas.bsh = s3c2410_uart_vaddr; di->bas.regshft = 0; di->bas.rclk = s3c2410_pclk; di->baudrate = 115200; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; - uart_bus_space_io = &s3c2xx0_bs_tag; + uart_bus_space_io = s3c2xx0_bs_tag; uart_bus_space_mem = NULL; return (0); } Index: stable/10/sys/arm/ti/files.ti =================================================================== --- stable/10/sys/arm/ti/files.ti (revision 278726) +++ stable/10/sys/arm/ti/files.ti (revision 278727) @@ -1,28 +1,28 @@ #$FreeBSD$ kern/kern_clocksource.c standard -arm/arm/bus_space-v6.c standard +arm/arm/bus_space_base.c standard arm/arm/bus_space_generic.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard arm/ti/ti_common.c standard arm/ti/ti_cpuid.c standard arm/ti/ti_machdep.c standard arm/ti/ti_prcm.c standard arm/ti/ti_scm.c standard dev/mbox/mbox_if.m optional ti_mbox arm/ti/ti_mbox.c optional ti_mbox arm/ti/ti_pruss.c optional ti_pruss arm/ti/ti_wdt.c optional ti_wdt arm/ti/ti_adc.c optional ti_adc arm/ti/ti_gpio.c optional gpio arm/ti/ti_i2c.c optional ti_i2c dev/uart/uart_dev_ti8250.c optional uart dev/uart/uart_dev_ns8250.c optional uart Index: stable/10/sys/arm/versatile/versatile_pci_bus_space.h =================================================================== --- stable/10/sys/arm/versatile/versatile_pci_bus_space.h (revision 278726) +++ stable/10/sys/arm/versatile/versatile_pci_bus_space.h (nonexistent) @@ -1,35 +0,0 @@ -/*- - * Copyright (c) 2009, Oleksandr Tymoshenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef __VERSATILE_PCI_BUS_SPACEH__ -#define __VERSATILE_PCI_BUS_SPACEH__ - -extern bus_space_tag_t versatile_bus_space_pcimem; - -#endif /* __VERSATILE_PCI_BUS_SPACEH__ */ Property changes on: stable/10/sys/arm/versatile/versatile_pci_bus_space.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/versatile/bus_space.c =================================================================== --- stable/10/sys/arm/versatile/bus_space.c (revision 278726) +++ stable/10/sys/arm/versatile/bus_space.c (nonexistent) @@ -1,115 +0,0 @@ -/*- - * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. - * All rights reserved. - * - * Developed by Semihalf. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of MARVELL nor the names of contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include - -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); -bs_protos(generic_armv4); - -struct bus_space _base_tag = { - /* cookie */ - .bs_cookie = (void *) 0, - - /* mapping/unmapping */ - .bs_map = generic_bs_map, - .bs_unmap = generic_bs_unmap, - .bs_subregion = generic_bs_subregion, - - /* allocation/deallocation */ - .bs_alloc = generic_bs_alloc, - .bs_free = generic_bs_free, - - /* barrier */ - .bs_barrier = generic_bs_barrier, - - /* read (single) */ - .bs_r_1 = generic_bs_r_1, - .bs_r_2 = generic_armv4_bs_r_2, - .bs_r_4 = generic_bs_r_4, - .bs_r_8 = NULL, - - /* read multiple */ - .bs_rm_1 = generic_bs_rm_1, - .bs_rm_2 = generic_armv4_bs_rm_2, - .bs_rm_4 = generic_bs_rm_4, - .bs_rm_8 = NULL, - - /* read region */ - .bs_rr_1 = generic_bs_rr_1, - .bs_rr_2 = generic_armv4_bs_rr_2, - .bs_rr_4 = generic_bs_rr_4, - .bs_rr_8 = NULL, - - /* write (single) */ - .bs_w_1 = generic_bs_w_1, - .bs_w_2 = generic_armv4_bs_w_2, - .bs_w_4 = generic_bs_w_4, - .bs_w_8 = NULL, - - /* write multiple */ - .bs_wm_1 = generic_bs_wm_1, - .bs_wm_2 = generic_armv4_bs_wm_2, - .bs_wm_4 = generic_bs_wm_4, - .bs_wm_8 = NULL, - - /* write region */ - .bs_wr_1 = generic_bs_wr_1, - .bs_wr_2 = generic_armv4_bs_wr_2, - .bs_wr_4 = generic_bs_wr_4, - .bs_wr_8 = NULL, - - /* set multiple */ - /* XXX not implemented */ - - /* set region */ - .bs_sr_1 = NULL, - .bs_sr_2 = generic_armv4_bs_sr_2, - .bs_sr_4 = generic_bs_sr_4, - .bs_sr_8 = NULL, - - /* copy */ - .bs_c_1 = NULL, - .bs_c_2 = generic_armv4_bs_c_2, - .bs_c_4 = NULL, - .bs_c_8 = NULL, -}; - -bus_space_tag_t fdtbus_bs_tag = &_base_tag; Property changes on: stable/10/sys/arm/versatile/bus_space.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/versatile/versatile_pci_bus_space.c =================================================================== --- stable/10/sys/arm/versatile/versatile_pci_bus_space.c (revision 278726) +++ stable/10/sys/arm/versatile/versatile_pci_bus_space.c (nonexistent) @@ -1,153 +0,0 @@ -/*- - * Copyright (c) 2009, Oleksandr Tymoshenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include - -#include -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); -bs_protos(generic_armv4); - -/* - * Bus space that handles offsets in word for 1/2 bytes read/write access. - * Byte order of values is handled by device drivers itself. - */ -static struct bus_space bus_space_pcimem = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - NULL, - NULL, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - generic_bs_wr_1, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - NULL, - generic_bs_sr_4, - NULL, - - /* copy */ - NULL, - NULL, - NULL, - NULL, - - /* read (single) stream */ - NULL, - NULL, - NULL, - NULL, - - /* read multiple stream */ - NULL, - NULL, - NULL, - NULL, - - /* read region stream */ - NULL, - NULL, - NULL, - NULL, - - /* write (single) stream */ - NULL, - NULL, - NULL, - NULL, - - /* write multiple stream */ - NULL, - NULL, - NULL, - NULL, - - /* write region stream */ - NULL, - NULL, - NULL, - NULL, -}; - -bus_space_tag_t versatile_bus_space_pcimem = &bus_space_pcimem; Property changes on: stable/10/sys/arm/versatile/versatile_pci_bus_space.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/10/sys/arm/versatile/files.versatile =================================================================== --- stable/10/sys/arm/versatile/files.versatile (revision 278726) +++ stable/10/sys/arm/versatile/files.versatile (revision 278727) @@ -1,22 +1,21 @@ # $FreeBSD$ +arm/arm/bus_space_base.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_arm11x6.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_armv6.S standard -arm/versatile/bus_space.c standard arm/versatile/pl050.c optional sc arm/versatile/sp804.c standard arm/versatile/versatile_machdep.c standard arm/versatile/versatile_clcd.c optional sc arm/versatile/versatile_common.c standard arm/versatile/versatile_pci.c optional pci -arm/versatile/versatile_pci_bus_space.c optional pci arm/versatile/versatile_sic.c standard arm/versatile/versatile_timer.c standard arm/versatile/if_smc_fdt.c optional smc kern/kern_clocksource.c standard Index: stable/10/sys/arm/versatile/versatile_pci.c =================================================================== --- stable/10/sys/arm/versatile/versatile_pci.c (revision 278726) +++ stable/10/sys/arm/versatile/versatile_pci.c (revision 278727) @@ -1,519 +1,517 @@ /* * Copyright (c) 2012 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #include #include #include #include #include #include -#include - #define MEM_SYS 0 #define MEM_CORE 1 #define MEM_BASE 2 #define MEM_CONF_BASE 3 #define MEM_REGIONS 4 #define SYS_PCICTL 0x00 #define PCI_CORE_IMAP0 0x00 #define PCI_CORE_IMAP1 0x04 #define PCI_CORE_IMAP2 0x08 #define PCI_CORE_SELFID 0x0C #define PCI_CORE_SMAP0 0x10 #define PCI_CORE_SMAP1 0x14 #define PCI_CORE_SMAP2 0x18 #define VERSATILE_PCI_DEV 0x030010ee #define VERSATILE_PCI_CLASS 0x0b400000 #define PCI_IO_WINDOW 0x44000000 #define PCI_IO_SIZE 0x0c000000 #define PCI_NPREFETCH_WINDOW 0x50000000 #define PCI_NPREFETCH_SIZE 0x10000000 #define PCI_PREFETCH_WINDOW 0x60000000 #define PCI_PREFETCH_SIZE 0x10000000 #define VERSATILE_PCI_IRQ_START 27 #define VERSATILE_PCI_IRQ_END 30 #ifdef DEBUG #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ printf(fmt,##args); } while (0) #else #define dprintf(fmt, args...) #endif #define versatile_pci_sys_read_4(reg) \ bus_read_4(sc->mem_res[MEM_SYS], (reg)) #define versatile_pci_sys_write_4(reg, val) \ bus_write_4(sc->mem_res[MEM_SYS], (reg), (val)) #define versatile_pci_core_read_4(reg) \ bus_read_4(sc->mem_res[MEM_CORE], (reg)) #define versatile_pci_core_write_4(reg, val) \ bus_write_4(sc->mem_res[MEM_CORE], (reg), (val)) #define versatile_pci_read_4(reg) \ bus_read_4(sc->mem_res[MEM_BASE], (reg)) #define versatile_pci_write_4(reg, val) \ bus_write_4(sc->mem_res[MEM_BASE], (reg), (val)) #define versatile_pci_conf_read_4(reg) \ bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg)) #define versatile_pci_conf_write_4(reg, val) \ bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val)) #define versatile_pci_conf_write_2(reg, val) \ bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val)) #define versatile_pci_conf_write_1(reg, val) \ bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val)) struct versatile_pci_softc { struct resource* mem_res[MEM_REGIONS]; struct resource* irq_res; void* intr_hl; int pcib_slot; /* Bus part */ int busno; struct rman io_rman; struct rman irq_rman; struct rman mem_rman; struct mtx mtx; }; static struct resource_spec versatile_pci_mem_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_MEMORY, 1, RF_ACTIVE }, { SYS_RES_MEMORY, 2, RF_ACTIVE }, { SYS_RES_MEMORY, 3, RF_ACTIVE }, { -1, 0, 0 } }; static int versatile_pci_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "versatile,pci")) { device_set_desc(dev, "Versatile PCI controller"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int versatile_pci_attach(device_t dev) { struct versatile_pci_softc *sc = device_get_softc(dev); int err; int slot; uint32_t vendordev_id, class_id; uint32_t val; /* Request memory resources */ err = bus_alloc_resources(dev, versatile_pci_mem_spec, sc->mem_res); if (err) { device_printf(dev, "Error: could not allocate memory resources\n"); return (ENXIO); } /* * Setup memory windows */ versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28)); versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28)); versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28)); /* * XXX: this is SDRAM offset >> 28 * Unused as of QEMU 1.5 */ versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28)); versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28)); versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28)); versatile_pci_sys_write_4(SYS_PCICTL, 1); for (slot = 0; slot <= PCI_SLOTMAX; slot++) { vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR); class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID); if ((vendordev_id == VERSATILE_PCI_DEV) && (class_id == VERSATILE_PCI_CLASS)) break; } if (slot == (PCI_SLOTMAX + 1)) { bus_release_resources(dev, versatile_pci_mem_spec, sc->mem_res); device_printf(dev, "Versatile PCI core not found\n"); return (ENXIO); } sc->pcib_slot = slot; device_printf(dev, "PCI core at slot #%d\n", slot); versatile_pci_core_write_4(PCI_CORE_SELFID, slot); val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND); val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN); versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val); /* Again SDRAM start >> 28 */ versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0); versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0); versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0); /* Prepare resource managers */ sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "versatile PCI memory window"; if (rman_init(&sc->mem_rman) != 0 || rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW, PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) { panic("versatile_pci_attach: failed to set up memory rman"); } bootverbose = 1; sc->io_rman.rm_type = RMAN_ARRAY; sc->io_rman.rm_descr = "versatile PCI IO window"; if (rman_init(&sc->io_rman) != 0 || rman_manage_region(&sc->io_rman, PCI_IO_WINDOW, PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) { panic("versatile_pci_attach: failed to set up I/O rman"); } sc->irq_rman.rm_type = RMAN_ARRAY; sc->irq_rman.rm_descr = "versatile PCI IRQs"; if (rman_init(&sc->irq_rman) != 0 || rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START, VERSATILE_PCI_IRQ_END) != 0) { panic("versatile_pci_attach: failed to set up IRQ rman"); } mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci", MTX_SPIN); val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND); for (slot = 0; slot <= PCI_SLOTMAX; slot++) { vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR); class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID); if (slot == sc->pcib_slot) continue; if ((vendordev_id == 0xffffffff) && (class_id == 0xffffffff)) continue; val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND); val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val); } device_add_child(dev, "pci", 0); return (bus_generic_attach(dev)); } static int versatile_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) { struct versatile_pci_softc *sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_DOMAIN: *result = 0; return (0); case PCIB_IVAR_BUS: *result = sc->busno; return (0); } return (ENOENT); } static int versatile_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result) { struct versatile_pci_softc * sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_BUS: sc->busno = result; return (0); } return (ENOENT); } static struct resource * versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct versatile_pci_softc *sc = device_get_softc(bus); struct resource *rv; struct rman *rm; dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count); switch (type) { case SYS_RES_IOPORT: rm = &sc->io_rman; break; case SYS_RES_IRQ: rm = &sc->irq_rman; break; case SYS_RES_MEMORY: rm = &sc->mem_rman; break; default: return (NULL); } rv = rman_reserve_resource(rm, start, end, count, flags, child); if (rv == NULL) return (NULL); rman_set_rid(rv, *rid); if (flags & RF_ACTIVE) { if (bus_activate_resource(child, type, *rid, rv)) { rman_release_resource(rv); return (NULL); } } return (rv); } static int versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { vm_offset_t vaddr; int res; switch(type) { case SYS_RES_MEMORY: case SYS_RES_IOPORT: vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r), rman_get_size(r)); rman_set_bushandle(r, vaddr); - rman_set_bustag(r, versatile_bus_space_pcimem); + rman_set_bustag(r, arm_base_bs_tag); res = rman_activate_resource(r); break; case SYS_RES_IRQ: res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, type, rid, r)); break; default: res = ENXIO; break; } return (res); } static int versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *handler, void *arg, void **cookiep) { return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags, filt, handler, arg, cookiep); } static int versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, void *cookie) { return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie); } static int versatile_pci_maxslots(device_t dev) { return (PCI_SLOTMAX); } static int versatile_pci_route_interrupt(device_t pcib, device_t device, int pin) { return (27 + ((pci_get_slot(device) + pin - 1) & 3)); } static uint32_t versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { struct versatile_pci_softc *sc = device_get_softc(dev); uint32_t data; uint32_t shift, mask; uint32_t addr; if (sc->pcib_slot == slot) { switch (bytes) { case 4: return (0xffffffff); break; case 2: return (0xffff); break; case 1: return (0xff); break; } } addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3); /* register access is 32-bit aligned */ shift = (reg & 3) * 8; /* Create a mask based on the width, post-shift */ if (bytes == 2) mask = 0xffff; else if (bytes == 1) mask = 0xff; else mask = 0xffffffff; dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, func, reg, bytes); mtx_lock_spin(&sc->mtx); data = versatile_pci_conf_read_4(addr); mtx_unlock_spin(&sc->mtx); /* get request bytes from 32-bit word */ data = (data >> shift) & mask; dprintf("%s: read 0x%x\n", __func__, data); return (data); } static void versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t data, int bytes) { struct versatile_pci_softc *sc = device_get_softc(dev); uint32_t addr; dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, func, reg, bytes); if (sc->pcib_slot == slot) return; addr = (bus << 16) | (slot << 11) | (func << 8) | reg; mtx_lock_spin(&sc->mtx); switch (bytes) { case 4: versatile_pci_conf_write_4(addr, data); break; case 2: versatile_pci_conf_write_2(addr, data); break; case 1: versatile_pci_conf_write_1(addr, data); break; } mtx_unlock_spin(&sc->mtx); } static device_method_t versatile_pci_methods[] = { DEVMETHOD(device_probe, versatile_pci_probe), DEVMETHOD(device_attach, versatile_pci_attach), /* Bus interface */ DEVMETHOD(bus_read_ivar, versatile_pci_read_ivar), DEVMETHOD(bus_write_ivar, versatile_pci_write_ivar), DEVMETHOD(bus_alloc_resource, versatile_pci_alloc_resource), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, versatile_pci_setup_intr), DEVMETHOD(bus_teardown_intr, versatile_pci_teardown_intr), /* pcib interface */ DEVMETHOD(pcib_maxslots, versatile_pci_maxslots), DEVMETHOD(pcib_read_config, versatile_pci_read_config), DEVMETHOD(pcib_write_config, versatile_pci_write_config), DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt), DEVMETHOD_END }; static driver_t versatile_pci_driver = { "pcib", versatile_pci_methods, sizeof(struct versatile_pci_softc), }; static devclass_t versatile_pci_devclass; DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0); Index: stable/10/sys/arm/xilinx/zy7_bus_space.c =================================================================== --- stable/10/sys/arm/xilinx/zy7_bus_space.c (revision 278726) +++ stable/10/sys/arm/xilinx/zy7_bus_space.c (nonexistent) @@ -1,115 +0,0 @@ -/*- - * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. - * All rights reserved. - * - * Developed by Semihalf. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of MARVELL nor the names of contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include - -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); -bs_protos(generic_armv4); - -struct bus_space _base_tag = { - /* cookie */ - .bs_cookie = (void *) 0, - - /* mapping/unmapping */ - .bs_map = generic_bs_map, - .bs_unmap = generic_bs_unmap, - .bs_subregion = generic_bs_subregion, - - /* allocation/deallocation */ - .bs_alloc = generic_bs_alloc, - .bs_free = generic_bs_free, - - /* barrier */ - .bs_barrier = generic_bs_barrier, - - /* read (single) */ - .bs_r_1 = generic_bs_r_1, - .bs_r_2 = generic_armv4_bs_r_2, - .bs_r_4 = generic_bs_r_4, - .bs_r_8 = NULL, - - /* read multiple */ - .bs_rm_1 = generic_bs_rm_1, - .bs_rm_2 = generic_armv4_bs_rm_2, - .bs_rm_4 = generic_bs_rm_4, - .bs_rm_8 = NULL, - - /* read region */ - .bs_rr_1 = generic_bs_rr_1, - .bs_rr_2 = generic_armv4_bs_rr_2, - .bs_rr_4 = generic_bs_rr_4, - .bs_rr_8 = NULL, - - /* write (single) */ - .bs_w_1 = generic_bs_w_1, - .bs_w_2 = generic_armv4_bs_w_2, - .bs_w_4 = generic_bs_w_4, - .bs_w_8 = NULL, - - /* write multiple */ - .bs_wm_1 = generic_bs_wm_1, - .bs_wm_2 = generic_armv4_bs_wm_2, - .bs_wm_4 = generic_bs_wm_4, - .bs_wm_8 = NULL, - - /* write region */ - .bs_wr_1 = generic_bs_wr_1, - .bs_wr_2 = generic_armv4_bs_wr_2, - .bs_wr_4 = generic_bs_wr_4, - .bs_wr_8 = NULL, - - /* set multiple */ - /* XXX not implemented */ - - /* set region */ - .bs_sr_1 = NULL, - .bs_sr_2 = generic_armv4_bs_sr_2, - .bs_sr_4 = generic_bs_sr_4, - .bs_sr_8 = NULL, - - /* copy */ - .bs_c_1 = NULL, - .bs_c_2 = generic_armv4_bs_c_2, - .bs_c_4 = NULL, - .bs_c_8 = NULL, -}; - -bus_space_tag_t fdtbus_bs_tag = &_base_tag; Property changes on: stable/10/sys/arm/xilinx/zy7_bus_space.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: stable/10/sys/arm/xilinx/files.zynq7 =================================================================== --- stable/10/sys/arm/xilinx/files.zynq7 (revision 278726) +++ stable/10/sys/arm/xilinx/files.zynq7 (revision 278727) @@ -1,31 +1,31 @@ # # files.zynq7 # # $FreeBSD$ kern/kern_clocksource.c standard +arm/arm/bus_space_base.c standard arm/arm/bus_space_generic.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard arm/arm/gic.c standard arm/arm/mpcore_timer.c standard arm/arm/pl310.c standard arm/xilinx/zy7_machdep.c standard arm/xilinx/zy7_l2cache.c standard -arm/xilinx/zy7_bus_space.c standard arm/xilinx/zy7_slcr.c standard arm/xilinx/zy7_devcfg.c standard arm/xilinx/zy7_mp.c optional smp dev/cadence/if_cgem.c optional cgem dev/sdhci/sdhci_fdt.c optional sdhci arm/xilinx/zy7_ehci.c optional ehci arm/xilinx/uart_dev_cdnc.c optional uart arm/xilinx/zy7_gpio.c optional gpio Index: stable/10/sys/arm/xscale/i80321/obio_space.c =================================================================== --- stable/10/sys/arm/xscale/i80321/obio_space.c (revision 278726) +++ stable/10/sys/arm/xscale/i80321/obio_space.c (nonexistent) @@ -1,128 +0,0 @@ -/* $NetBSD: obio_space.c,v 1.6 2003/07/15 00:25:05 lukem Exp $ */ - -/*- - * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * bus_space functions for IQ80321 on-board devices - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include - -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); -bs_protos(generic_armv4); - -/* - * The obio bus space tag. This is constant for all instances, so - * we never have to explicitly "create" it. - */ -struct bus_space obio_bs_tag = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - generic_bs_alloc, - generic_bs_free, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - NULL, - NULL, - NULL, - - /* read region */ - generic_bs_rr_1, - NULL, - NULL, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - NULL, - NULL, - NULL, - - /* write region */ - NULL, - NULL, - NULL, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - NULL, - NULL, - NULL, - - /* copy */ - NULL, - NULL, - NULL, - NULL, -}; Property changes on: stable/10/sys/arm/xscale/i80321/obio_space.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: stable/10/sys/arm/xscale/i80321/ep80219_machdep.c =================================================================== --- stable/10/sys/arm/xscale/i80321/ep80219_machdep.c (revision 278726) +++ stable/10/sys/arm/xscale/i80321/ep80219_machdep.c (revision 278727) @@ -1,396 +1,396 @@ /* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ /*- * Copyright (c) 1994-1998 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * machdep.c * * Machine dependant functions for kernel setup * * This file needs a lot of work. * * Created : 17/09/94 */ #include __FBSDID("$FreeBSD$"); #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ #define KERNEL_PT_IOPXS 1 #define KERNEL_PT_BEFOREKERN 2 #define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */ #define KERNEL_PT_AFKERNEL_NUM 9 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; /* Physical and virtual addresses for some global pages */ struct pv_addr systempage; struct pv_addr msgbufpv; struct pv_addr irqstack; struct pv_addr undstack; struct pv_addr abtstack; struct pv_addr kernelstack; struct pv_addr minidataclean; /* #define IQ80321_OBIO_BASE 0xfe800000UL */ /* #define IQ80321_OBIO_SIZE 0x00100000UL */ /* Static device mappings. */ static const struct arm_devmap_entry ep80219_devmap[] = { /* * Map the on-board devices VA == PA so that we can access them * with the MMU on or off. */ { IQ80321_OBIO_BASE, IQ80321_OBIO_BASE, IQ80321_OBIO_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { IQ80321_IOW_VBASE, VERDE_OUT_XLATE_IO_WIN0_BASE, VERDE_OUT_XLATE_IO_WIN_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { IQ80321_80321_VBASE, VERDE_PMMR_BASE, VERDE_PMMR_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { 0, 0, 0, 0, 0, } }; extern vm_offset_t xscale_cache_clean_addr; void * initarm(struct arm_boot_params *abp) { struct pv_addr kernel_l1pt; struct pv_addr dpcpu; int loop, i; u_int l1pagetable; vm_offset_t freemempos; vm_offset_t freemem_pt; vm_offset_t afterkern; vm_offset_t freemem_after; vm_offset_t lastaddr; uint32_t memsize, memstart; lastaddr = parse_boot_param(abp); arm_physmem_kernaddr = abp->abp_physaddr; set_cpufuncs(); pcpu_init(pcpup, 0, sizeof(struct pcpu)); PCPU_SET(curthread, &thread0); /* Do basic tuning, hz etc */ init_param1(); freemempos = 0xa0200000; /* Define a macro to simplify memory allocation */ #define valloc_pages(var, np) \ alloc_pages((var).pv_pa, (np)); \ (var).pv_va = (var).pv_pa + 0x20000000; #define alloc_pages(var, np) \ freemempos -= (np * PAGE_SIZE); \ (var) = freemempos; \ memset((char *)(var), 0, ((np) * PAGE_SIZE)); while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) freemempos -= PAGE_SIZE; valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { valloc_pages(kernel_pt_table[loop], L2_TABLE_SIZE / PAGE_SIZE); } else { kernel_pt_table[loop].pv_pa = freemempos + (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * L2_TABLE_SIZE_REAL; kernel_pt_table[loop].pv_va = kernel_pt_table[loop].pv_pa + 0x20000000; } } freemem_pt = freemempos; freemempos = 0xa0100000; /* * Allocate a page for the system page mapped to V0x00000000 * This page will just contain the system vectors and can be * shared by all processes. */ valloc_pages(systempage, 1); /* Allocate dynamic per-cpu area. */ valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); dpcpu_init((void *)dpcpu.pv_va, 0); /* Allocate stacks for all modes */ valloc_pages(irqstack, IRQ_STACK_SIZE); valloc_pages(abtstack, ABT_STACK_SIZE); valloc_pages(undstack, UND_STACK_SIZE); valloc_pages(kernelstack, KSTACK_PAGES); alloc_pages(minidataclean.pv_pa, 1); valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); /* * Allocate memory for the l1 and l2 page tables. The scheme to avoid * wasting memory by allocating the l1pt on the first 16k memory was * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for * this to work (which is supposed to be the case). */ /* * Now we start construction of the L1 page table * We start by mapping the L2 page tables into the L1. * This means that we can replace L1 mappings later on if necessary */ l1pagetable = kernel_l1pt.pv_va; /* Map the L2 pages tables in the L1 page table */ pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), &kernel_pt_table[KERNEL_PT_SYS]); pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE, &kernel_pt_table[KERNEL_PT_IOPXS]); pmap_link_l2pt(l1pagetable, KERNBASE, &kernel_pt_table[KERNEL_PT_BEFOREKERN]); pmap_map_chunk(l1pagetable, KERNBASE, IQ80321_SDRAM_START, 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, IQ80321_SDRAM_START + 0x100000, 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, IQ80321_SDRAM_START + 0x200000, (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1), VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1); afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1)); for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); } pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); /* Map the Mini-Data cache clean area. */ xscale_setup_minidata(l1pagetable, afterkern, minidataclean.pv_pa); /* Map the vector page. */ pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); arm_devmap_bootstrap(l1pagetable, ep80219_devmap); /* * Give the XScale global cache clean code an appropriately * sized chunk of unmapped VA space starting at 0xff000000 * (our device mappings end before this address). */ xscale_cache_clean_addr = 0xff000000U; cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); /* * Pages were allocated during the secondary bootstrap for the * stacks for different CPU modes. * We must now set the r13 registers in the different CPU modes to * point to these stacks. * Since the ARM stacks use STMFD etc. we must set r13 to the top end * of the stack memory. */ set_stackptrs(0); /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any * dirty data in the cache. This will have happened in setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. * After booting there are no gross relocations of the kernel thus * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); cpu_setup(""); /* * Fetch the SDRAM start/size from the i80321 SDRAM configration * registers. */ i80321_calibrate_delay(); - i80321_sdram_bounds(&obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE, + i80321_sdram_bounds(obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE, &memstart, &memsize); physmem = memsize / PAGE_SIZE; cninit(); undefined_init(); init_proc0(kernelstack.pv_va); /* Enable MMU, I-cache, D-cache, write buffer. */ arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); vm_max_kernel_address = 0xd0000000; pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); /* * Add the physical ram we have available. * * Exclude the kernel (and all the things we allocated which immediately * follow the kernel) from the VM allocation pool but not from crash * dumps. virtual_avail is a global variable which tracks the kva we've * "allocated" while setting up pmaps. * * Prepare the list of physical memory available to the vm subsystem. */ arm_physmem_hardware_region(IQ80321_SDRAM_START, memsize); arm_physmem_exclude_region(abp->abp_physaddr, virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC); arm_physmem_init_kernel_globals(); init_param2(physmem); kdb_init(); return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - sizeof(struct pcb))); } extern int machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin) { int bus; int device; int func; uint32_t busno; struct i80321_pci_softc *sc = device_get_softc(pcib); bus = pci_get_bus(dev); device = pci_get_slot(dev); func = pci_get_function(dev); busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); busno = PCIXSR_BUSNO(busno); if (busno == 0xff) busno = 0; if (bus != busno) goto no_mapping; switch (device) { /* EP80219 PCI */ case 1: /* Ethernet i82555 10/100 */ printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(0)); return (ICU_INT_XINT(0)); case 2: /* UART */ printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(1)); return (ICU_INT_XINT(1)); case 3: /* * The S-ATA chips are behind the bridge, and all of * the S-ATA interrupts are wired together. */ printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(2)); return (ICU_INT_XINT(2)); case 4: /* MINI-PIC_INT */ printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(3)); return( ICU_INT_XINT(3)); default: no_mapping: printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin); } return (0); } Index: stable/10/sys/arm/xscale/i80321/files.ep80219 =================================================================== --- stable/10/sys/arm/xscale/i80321/files.ep80219 (revision 278726) +++ stable/10/sys/arm/xscale/i80321/files.ep80219 (revision 278727) @@ -1,12 +1,11 @@ #$FreeBSD$ # # # EP80219 Board Specific # arm/xscale/i80321/iq80321.c standard arm/xscale/i80321/ep80219_machdep.c standard arm/xscale/i80321/obio.c standard -arm/xscale/i80321/obio_space.c standard arm/xscale/i80321/uart_cpu_i80321.c optional uart arm/xscale/i80321/uart_bus_i80321.c optional uart dev/uart/uart_dev_ns8250.c optional uart Index: stable/10/sys/arm/xscale/i80321/files.i80219 =================================================================== --- stable/10/sys/arm/xscale/i80321/files.i80219 (revision 278726) +++ stable/10/sys/arm/xscale/i80321/files.i80219 (revision 278727) @@ -1,13 +1,14 @@ #$FreeBSD$ # # IOP Specific # +arm/arm/bus_space_base.c standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_xscale.S standard arm/xscale/i80321/i80321.c standard arm/xscale/i80321/i80321_dma.c optional dma arm/xscale/i80321/i80321_mcu.c standard arm/xscale/i80321/i80321_pci.c optional pci arm/xscale/i80321/i80321_space.c standard arm/xscale/i80321/i80321_timer.c standard arm/xscale/i80321/i80321_wdog.c optional iopwdog Index: stable/10/sys/arm/xscale/i80321/files.i80321 =================================================================== --- stable/10/sys/arm/xscale/i80321/files.i80321 (revision 278726) +++ stable/10/sys/arm/xscale/i80321/files.i80321 (revision 278727) @@ -1,11 +1,12 @@ #$FreeBSD$ +arm/arm/bus_space_base.c standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_xscale.S standard arm/xscale/i80321/i80321.c standard arm/xscale/i80321/i80321_aau.c optional aau arm/xscale/i80321/i80321_dma.c optional dma arm/xscale/i80321/i80321_mcu.c standard arm/xscale/i80321/i80321_pci.c optional pci arm/xscale/i80321/i80321_space.c standard arm/xscale/i80321/i80321_timer.c standard arm/xscale/i80321/i80321_wdog.c optional iopwdog Index: stable/10/sys/arm/xscale/i80321/files.iq31244 =================================================================== --- stable/10/sys/arm/xscale/i80321/files.iq31244 (revision 278726) +++ stable/10/sys/arm/xscale/i80321/files.iq31244 (revision 278727) @@ -1,9 +1,8 @@ #$FreeBSD$ arm/xscale/i80321/iq80321.c standard arm/xscale/i80321/iq31244_machdep.c standard arm/xscale/i80321/iq31244_7seg.c optional iq31244_7seg arm/xscale/i80321/obio.c standard -arm/xscale/i80321/obio_space.c standard arm/xscale/i80321/uart_cpu_i80321.c optional uart arm/xscale/i80321/uart_bus_i80321.c optional uart dev/uart/uart_dev_ns8250.c optional uart Index: stable/10/sys/arm/xscale/i80321/i80321_space.c =================================================================== --- stable/10/sys/arm/xscale/i80321/i80321_space.c (revision 278726) +++ stable/10/sys/arm/xscale/i80321/i80321_space.c (revision 278727) @@ -1,332 +1,209 @@ /* $NetBSD: i80321_space.c,v 1.6 2003/10/06 15:43:35 thorpej Exp $ */ /*- * Copyright (c) 2001, 2002 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * bus_space functions for i80321 I/O Processor. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include /* Prototypes for all the bus_space structure functions */ bs_protos(i80321); bs_protos(i80321_io); bs_protos(i80321_mem); -bs_protos(generic); -bs_protos(generic_armv4); -/* - * Template bus_space -- copied, and the bits that are NULL are - * filled in. - */ -const struct bus_space i80321_bs_tag_template = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - NULL, - NULL, - i80321_bs_subregion, - - /* allocation/deallocation */ - NULL, - NULL, - - /* barrier */ - i80321_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - NULL, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - generic_armv4_bs_sr_2, - generic_bs_sr_4, - NULL, - - /* copy */ - NULL, - generic_armv4_bs_c_2, - NULL, - NULL, - - /* read (single) stream */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple stream */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region stream */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) stream */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple stream */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region stream */ - NULL, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, -}; - void i80321_bs_init(bus_space_tag_t bs, void *cookie) { - *bs = i80321_bs_tag_template; - bs->bs_cookie = cookie; + *bs = *arm_base_bs_tag; + bs->bs_privdata = cookie; } void i80321_io_bs_init(bus_space_tag_t bs, void *cookie) { - *bs = i80321_bs_tag_template; - bs->bs_cookie = cookie; + *bs = *arm_base_bs_tag; + bs->bs_privdata = cookie; bs->bs_map = i80321_io_bs_map; bs->bs_unmap = i80321_io_bs_unmap; bs->bs_alloc = i80321_io_bs_alloc; bs->bs_free = i80321_io_bs_free; } void i80321_mem_bs_init(bus_space_tag_t bs, void *cookie) { - *bs = i80321_bs_tag_template; - bs->bs_cookie = cookie; + *bs = *arm_base_bs_tag; + bs->bs_privdata = cookie; bs->bs_map = i80321_mem_bs_map; bs->bs_unmap = i80321_mem_bs_unmap; bs->bs_alloc = i80321_mem_bs_alloc; bs->bs_free = i80321_mem_bs_free; } /* *** Routines shared by i80321, PCI IO, and PCI MEM. *** */ int -i80321_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, +i80321_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) { *nbshp = bsh + offset; return (0); } void -i80321_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, +i80321_bs_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, bus_size_t len, int flags) { /* Nothing to do. */ } /* *** Routines for PCI IO. *** */ extern struct i80321_softc *i80321_softc; int -i80321_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, +i80321_io_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) { struct i80321_softc *sc = i80321_softc; vm_offset_t winvaddr; uint32_t busbase; if (bpa >= sc->sc_ioout_xlate && bpa < (sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE)) { busbase = sc->sc_ioout_xlate; winvaddr = sc->sc_iow_vaddr; } else return (EINVAL); if ((bpa + size) >= (busbase + VERDE_OUT_XLATE_IO_WIN_SIZE)) return (EINVAL); /* * Found the window -- PCI I/O space is mapped at a fixed * virtual address by board-specific code. Translate the * bus address to the virtual address. */ *bshp = winvaddr + (bpa - busbase); return (0); } void -i80321_io_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) +i80321_io_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) { /* Nothing to do. */ } int -i80321_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, +i80321_io_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) { panic("i80321_io_bs_alloc(): not implemented"); } void -i80321_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) +i80321_io_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) { panic("i80321_io_bs_free(): not implemented"); } /* *** Routines for PCI MEM. *** */ extern int badaddr_read(void *, int, void *); int -i80321_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, +i80321_mem_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) { - vm_paddr_t pa, endpa; - pa = trunc_page(bpa); - endpa = round_page(bpa + size); - - *bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa); - + *bshp = (vm_offset_t)pmap_mapdev(bpa, size); return (0); } void -i80321_mem_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) +i80321_mem_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) { - vm_offset_t va, endva; - va = trunc_page((vm_offset_t)t); - endva = va + round_page(size); - - /* Free the kernel virtual mapping. */ - kva_free(va, endva - va); + pmap_unmapdev((vm_offset_t)h, size); } int -i80321_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, +i80321_mem_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) { panic("i80321_mem_bs_alloc(): not implemented"); } void -i80321_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) +i80321_mem_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) { panic("i80321_mem_bs_free(): not implemented"); } Index: stable/10/sys/arm/xscale/i80321/iq31244_machdep.c =================================================================== --- stable/10/sys/arm/xscale/i80321/iq31244_machdep.c (revision 278726) +++ stable/10/sys/arm/xscale/i80321/iq31244_machdep.c (revision 278727) @@ -1,410 +1,410 @@ /* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ /*- * Copyright (c) 1994-1998 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * machdep.c * * Machine dependant functions for kernel setup * * This file needs a lot of work. * * Created : 17/09/94 */ #include __FBSDID("$FreeBSD$"); #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ #define KERNEL_PT_IOPXS 1 #define KERNEL_PT_BEFOREKERN 2 #define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */ #define KERNEL_PT_AFKERNEL_NUM 9 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; /* Physical and virtual addresses for some global pages */ struct pv_addr systempage; struct pv_addr msgbufpv; struct pv_addr irqstack; struct pv_addr undstack; struct pv_addr abtstack; struct pv_addr kernelstack; struct pv_addr minidataclean; #define IQ80321_OBIO_BASE 0xfe800000UL #define IQ80321_OBIO_SIZE 0x00100000UL /* Static device mappings. */ static const struct arm_devmap_entry iq80321_devmap[] = { /* * Map the on-board devices VA == PA so that we can access them * with the MMU on or off. */ { IQ80321_OBIO_BASE, IQ80321_OBIO_BASE, IQ80321_OBIO_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { IQ80321_IOW_VBASE, VERDE_OUT_XLATE_IO_WIN0_BASE, VERDE_OUT_XLATE_IO_WIN_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { IQ80321_80321_VBASE, VERDE_PMMR_BASE, VERDE_PMMR_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { 0, 0, 0, 0, 0, } }; #define SDRAM_START 0xa0000000 extern vm_offset_t xscale_cache_clean_addr; void * initarm(struct arm_boot_params *abp) { struct pv_addr kernel_l1pt; struct pv_addr dpcpu; int loop, i; u_int l1pagetable; vm_offset_t freemempos; vm_offset_t freemem_pt; vm_offset_t afterkern; vm_offset_t freemem_after; vm_offset_t lastaddr; uint32_t memsize, memstart; lastaddr = parse_boot_param(abp); arm_physmem_kernaddr = abp->abp_physaddr; set_cpufuncs(); pcpu_init(pcpup, 0, sizeof(struct pcpu)); PCPU_SET(curthread, &thread0); /* Do basic tuning, hz etc */ init_param1(); freemempos = 0xa0200000; /* Define a macro to simplify memory allocation */ #define valloc_pages(var, np) \ alloc_pages((var).pv_pa, (np)); \ (var).pv_va = (var).pv_pa + 0x20000000; #define alloc_pages(var, np) \ freemempos -= (np * PAGE_SIZE); \ (var) = freemempos; \ memset((char *)(var), 0, ((np) * PAGE_SIZE)); while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) freemempos -= PAGE_SIZE; valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { valloc_pages(kernel_pt_table[loop], L2_TABLE_SIZE / PAGE_SIZE); } else { kernel_pt_table[loop].pv_pa = freemempos + (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * L2_TABLE_SIZE_REAL; kernel_pt_table[loop].pv_va = kernel_pt_table[loop].pv_pa + 0x20000000; } } freemem_pt = freemempos; freemempos = 0xa0100000; /* * Allocate a page for the system page mapped to V0x00000000 * This page will just contain the system vectors and can be * shared by all processes. */ valloc_pages(systempage, 1); /* Allocate dynamic per-cpu area. */ valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); dpcpu_init((void *)dpcpu.pv_va, 0); /* Allocate stacks for all modes */ valloc_pages(irqstack, IRQ_STACK_SIZE); valloc_pages(abtstack, ABT_STACK_SIZE); valloc_pages(undstack, UND_STACK_SIZE); valloc_pages(kernelstack, KSTACK_PAGES); alloc_pages(minidataclean.pv_pa, 1); valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); /* * Allocate memory for the l1 and l2 page tables. The scheme to avoid * wasting memory by allocating the l1pt on the first 16k memory was * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for * this to work (which is supposed to be the case). */ /* * Now we start construction of the L1 page table * We start by mapping the L2 page tables into the L1. * This means that we can replace L1 mappings later on if necessary */ l1pagetable = kernel_l1pt.pv_va; /* Map the L2 pages tables in the L1 page table */ pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), &kernel_pt_table[KERNEL_PT_SYS]); pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE, &kernel_pt_table[KERNEL_PT_IOPXS]); pmap_link_l2pt(l1pagetable, KERNBASE, &kernel_pt_table[KERNEL_PT_BEFOREKERN]); pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000, 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000, (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1), VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1); afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1)); for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); } pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); /* Map the Mini-Data cache clean area. */ xscale_setup_minidata(l1pagetable, afterkern, minidataclean.pv_pa); /* Map the vector page. */ pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); arm_devmap_bootstrap(l1pagetable, iq80321_devmap); /* * Give the XScale global cache clean code an appropriately * sized chunk of unmapped VA space starting at 0xff000000 * (our device mappings end before this address). */ xscale_cache_clean_addr = 0xff000000U; cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); /* * Pages were allocated during the secondary bootstrap for the * stacks for different CPU modes. * We must now set the r13 registers in the different CPU modes to * point to these stacks. * Since the ARM stacks use STMFD etc. we must set r13 to the top end * of the stack memory. */ set_stackptrs(0); /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any * dirty data in the cache. This will have happened in setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. * After booting there are no gross relocations of the kernel thus * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); cpu_setup(""); /* * Fetch the SDRAM start/size from the i80321 SDRAM configration * registers. */ i80321_calibrate_delay(); - i80321_sdram_bounds(&obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE, + i80321_sdram_bounds(obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE, &memstart, &memsize); physmem = memsize / PAGE_SIZE; cninit(); undefined_init(); init_proc0(kernelstack.pv_va); /* Enable MMU, I-cache, D-cache, write buffer. */ arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); pmap_curmaxkvaddr = afterkern + PAGE_SIZE; vm_max_kernel_address = 0xd0000000; pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); /* * Add the physical ram we have available. * * Exclude the kernel (and all the things we allocated which immediately * follow the kernel) from the VM allocation pool but not from crash * dumps. virtual_avail is a global variable which tracks the kva we've * "allocated" while setting up pmaps. * * Prepare the list of physical memory available to the vm subsystem. */ arm_physmem_hardware_region(SDRAM_START, memsize); arm_physmem_exclude_region(abp->abp_physaddr, virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC); arm_physmem_init_kernel_globals(); init_param2(physmem); kdb_init(); return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - sizeof(struct pcb))); } extern int machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin) { int bus; int device; int func; uint32_t busno; struct i80321_pci_softc *sc = device_get_softc(pcib); bus = pci_get_bus(dev); device = pci_get_slot(dev); func = pci_get_function(dev); busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); busno = PCIXSR_BUSNO(busno); if (busno == 0xff) busno = 0; if (bus != busno) goto no_mapping; switch (device) { /* IQ31244 PCI */ case 1: /* PCIX-PCIX bridge */ /* * The S-ATA chips are behind the bridge, and all of * the S-ATA interrupts are wired together. */ return (ICU_INT_XINT(2)); case 2: /* PCI slot */ /* All pins are wired together. */ return (ICU_INT_XINT(3)); case 3: /* i82546 dual Gig-E */ if (pin == 1 || pin == 2) return (ICU_INT_XINT(0)); goto no_mapping; /* IQ80321 PCI */ case 4: /* i82544 Gig-E */ case 8: /* * Apparently you can set the device for the ethernet adapter * to 8 with a jumper, so handle that as well */ if (pin == 1) return (ICU_INT_XINT(0)); goto no_mapping; case 6: /* S-PCI-X slot */ if (pin == 1) return (ICU_INT_XINT(2)); if (pin == 2) return (ICU_INT_XINT(3)); goto no_mapping; default: no_mapping: printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin); } return (0); } Index: stable/10/sys/arm/xscale/i80321/obio.c =================================================================== --- stable/10/sys/arm/xscale/i80321/obio.c (revision 278726) +++ stable/10/sys/arm/xscale/i80321/obio.c (revision 278727) @@ -1,160 +1,163 @@ /* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */ /*- * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * On-board device autoconfiguration support for Intel IQ80321 * evaluation boards. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include +bus_space_tag_t obio_bs_tag; + int obio_probe(device_t); int obio_attach(device_t); int obio_probe(device_t dev) { return (0); } int obio_attach(device_t dev) { struct obio_softc *sc = device_get_softc(dev); - sc->oba_st = &obio_bs_tag; + obio_bs_tag = arm_base_bs_tag; + sc->oba_st = obio_bs_tag; sc->oba_addr = IQ80321_OBIO_BASE; sc->oba_size = IQ80321_OBIO_SIZE; sc->oba_rman.rm_type = RMAN_ARRAY; sc->oba_rman.rm_descr = "OBIO I/O"; if (rman_init(&sc->oba_rman) != 0 || rman_manage_region(&sc->oba_rman, sc->oba_addr, sc->oba_addr + sc->oba_size) != 0) panic("obio_attach: failed to set up I/O rman"); sc->oba_irq_rman.rm_type = RMAN_ARRAY; sc->oba_irq_rman.rm_descr = "OBIO IRQ"; if (rman_init(&sc->oba_irq_rman) != 0 || rman_manage_region(&sc->oba_irq_rman, 28, 28) != 0) panic("obio_attach: failed to set up IRQ rman"); device_add_child(dev, "uart", 0); bus_generic_probe(dev); bus_generic_attach(dev); return (0); } static struct resource * obio_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct resource *rv; struct rman *rm; bus_space_tag_t bt = NULL; bus_space_handle_t bh = 0; struct obio_softc *sc = device_get_softc(bus); switch (type) { case SYS_RES_IRQ: rm = &sc->oba_irq_rman; break; case SYS_RES_MEMORY: return (NULL); case SYS_RES_IOPORT: rm = &sc->oba_rman; bt = sc->oba_st; bh = sc->oba_addr; start = bh; break; default: return (NULL); } rv = rman_reserve_resource(rm, start, end, count, flags, child); if (rv == NULL) return (NULL); if (type == SYS_RES_IRQ) return (rv); rman_set_rid(rv, *rid); rman_set_bustag(rv, bt); rman_set_bushandle(rv, bh); return (rv); } static int obio_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { return (0); } static device_method_t obio_methods[] = { DEVMETHOD(device_probe, obio_probe), DEVMETHOD(device_attach, obio_attach), DEVMETHOD(bus_alloc_resource, obio_alloc_resource), DEVMETHOD(bus_activate_resource, obio_activate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), {0, 0}, }; static driver_t obio_driver = { "obio", obio_methods, sizeof(struct obio_softc), }; static devclass_t obio_devclass; DRIVER_MODULE(obio, iq, obio_driver, obio_devclass, 0, 0); Index: stable/10/sys/arm/xscale/i80321/obiovar.h =================================================================== --- stable/10/sys/arm/xscale/i80321/obiovar.h (revision 278726) +++ stable/10/sys/arm/xscale/i80321/obiovar.h (revision 278727) @@ -1,58 +1,58 @@ /* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */ /*- * Copyright (c) 2002, 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef _IQ80321_OBIOVAR_H_ #define _IQ80321_OBIOVAR_H_ #include struct obio_softc { bus_space_tag_t oba_st; /* bus space tag */ bus_addr_t oba_addr; /* address of device */ bus_size_t oba_size; /* size of device */ int oba_width; /* bus width */ int oba_irq; /* XINT interrupt bit # */ struct rman oba_rman; struct rman oba_irq_rman; }; -extern struct bus_space obio_bs_tag; +extern bus_space_tag_t obio_bs_tag; #endif /* _IQ80321_OBIOVAR_H_ */ Index: stable/10/sys/arm/xscale/i80321/uart_cpu_i80321.c =================================================================== --- stable/10/sys/arm/xscale/i80321/uart_cpu_i80321.c (revision 278726) +++ stable/10/sys/arm/xscale/i80321/uart_cpu_i80321.c (revision 278727) @@ -1,67 +1,67 @@ /*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; int uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) { return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); } int uart_cpu_getdev(int devtype, struct uart_devinfo *di) { di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; - di->bas.bst = &obio_bs_tag; + di->bas.bst = obio_bs_tag; di->bas.regshft = 0; di->bas.rclk = 0; di->baudrate = 115200; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; - uart_bus_space_io = &obio_bs_tag; + uart_bus_space_io = obio_bs_tag; uart_bus_space_mem = NULL; di->bas.bsh = 0xfe800000; return (0); } Index: stable/10/sys/arm/xscale/i8134x/obio_space.c =================================================================== --- stable/10/sys/arm/xscale/i8134x/obio_space.c (revision 278726) +++ stable/10/sys/arm/xscale/i8134x/obio_space.c (nonexistent) @@ -1,128 +0,0 @@ -/* $NetBSD: obio_space.c,v 1.6 2003/07/15 00:25:05 lukem Exp $ */ - -/*- - * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * bus_space functions for IQ80321 on-board devices - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include - -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); -bs_protos(generic_armv4); - -/* - * The obio bus space tag. This is constant for all instances, so - * we never have to explicitly "create" it. - */ -struct bus_space obio_bs_tag = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - generic_bs_alloc, - generic_bs_free, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - NULL, - NULL, - NULL, - - /* read region */ - generic_bs_rr_1, - NULL, - NULL, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - NULL, - NULL, - NULL, - - /* write region */ - NULL, - NULL, - NULL, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - NULL, - NULL, - NULL, - - /* copy */ - NULL, - NULL, - NULL, - NULL, -}; Property changes on: stable/10/sys/arm/xscale/i8134x/obio_space.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: stable/10/sys/arm/xscale/i8134x/crb_machdep.c =================================================================== --- stable/10/sys/arm/xscale/i8134x/crb_machdep.c (revision 278726) +++ stable/10/sys/arm/xscale/i8134x/crb_machdep.c (revision 278727) @@ -1,334 +1,334 @@ /* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ /*- * Copyright (c) 1994-1998 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * machdep.c * * Machine dependant functions for kernel setup * * This file needs a lot of work. * * Created : 17/09/94 */ #include __FBSDID("$FreeBSD$"); #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* For i80321_calibrate_delay() */ #include #include #include #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ #define KERNEL_PT_IOPXS 1 #define KERNEL_PT_BEFOREKERN 2 #define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */ #define KERNEL_PT_AFKERNEL_NUM 9 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; /* Physical and virtual addresses for some global pages */ struct pv_addr systempage; struct pv_addr msgbufpv; struct pv_addr irqstack; struct pv_addr undstack; struct pv_addr abtstack; struct pv_addr kernelstack; /* Static device mappings. */ static const struct arm_devmap_entry iq81342_devmap[] = { { IOP34X_VADDR, IOP34X_HWADDR, IOP34X_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { /* * Cheat and map a whole section, this will bring * both PCI-X and PCI-E outbound I/O */ IOP34X_PCIX_OIOBAR_VADDR &~ (0x100000 - 1), IOP34X_PCIX_OIOBAR &~ (0x100000 - 1), 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { IOP34X_PCE1_VADDR, IOP34X_PCE1, IOP34X_PCE1_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, }, { 0, 0, 0, 0, 0, } }; #define SDRAM_START 0x00000000 extern vm_offset_t xscale_cache_clean_addr; void * initarm(struct arm_boot_params *abp) { struct pv_addr kernel_l1pt; struct pv_addr dpcpu; int loop, i; u_int l1pagetable; vm_offset_t freemempos; vm_offset_t freemem_pt; vm_offset_t afterkern; vm_offset_t freemem_after; vm_offset_t lastaddr; uint32_t memsize, memstart; lastaddr = parse_boot_param(abp); arm_physmem_kernaddr = abp->abp_physaddr; set_cpufuncs(); pcpu_init(pcpup, 0, sizeof(struct pcpu)); PCPU_SET(curthread, &thread0); /* Do basic tuning, hz etc */ init_param1(); freemempos = 0x00200000; /* Define a macro to simplify memory allocation */ #define valloc_pages(var, np) \ alloc_pages((var).pv_pa, (np)); \ (var).pv_va = (var).pv_pa + 0xc0000000; #define alloc_pages(var, np) \ freemempos -= (np * PAGE_SIZE); \ (var) = freemempos; \ memset((char *)(var), 0, ((np) * PAGE_SIZE)); while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) freemempos -= PAGE_SIZE; valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { valloc_pages(kernel_pt_table[loop], L2_TABLE_SIZE / PAGE_SIZE); } else { kernel_pt_table[loop].pv_pa = freemempos + (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * L2_TABLE_SIZE_REAL; kernel_pt_table[loop].pv_va = kernel_pt_table[loop].pv_pa + 0xc0000000; } } freemem_pt = freemempos; freemempos = 0x00100000; /* * Allocate a page for the system page mapped to V0x00000000 * This page will just contain the system vectors and can be * shared by all processes. */ valloc_pages(systempage, 1); /* Allocate dynamic per-cpu area. */ valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); dpcpu_init((void *)dpcpu.pv_va, 0); /* Allocate stacks for all modes */ valloc_pages(irqstack, IRQ_STACK_SIZE); valloc_pages(abtstack, ABT_STACK_SIZE); valloc_pages(undstack, UND_STACK_SIZE); valloc_pages(kernelstack, KSTACK_PAGES); valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); /* * Now we start construction of the L1 page table * We start by mapping the L2 page tables into the L1. * This means that we can replace L1 mappings later on if necessary */ l1pagetable = kernel_l1pt.pv_va; /* Map the L2 pages tables in the L1 page table */ pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), &kernel_pt_table[KERNEL_PT_SYS]); pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000, 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000, (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1), VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1); afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1)); for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); } /* Map the vector page. */ pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); arm_devmap_bootstrap(l1pagetable, iq81342_devmap); /* * Give the XScale global cache clean code an appropriately * sized chunk of unmapped VA space starting at 0xff000000 * (our device mappings end before this address). */ xscale_cache_clean_addr = 0xff000000U; cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); /* * Pages were allocated during the secondary bootstrap for the * stacks for different CPU modes. * We must now set the r13 registers in the different CPU modes to * point to these stacks. * Since the ARM stacks use STMFD etc. we must set r13 to the top end * of the stack memory. */ set_stackptrs(0); /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any * dirty data in the cache. This will have happened in setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. * After booting there are no gross relocations of the kernel thus * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); cpu_setup(""); i80321_calibrate_delay(); - i81342_sdram_bounds(&obio_bs_tag, IOP34X_VADDR, &memstart, &memsize); + i81342_sdram_bounds(obio_bs_tag, IOP34X_VADDR, &memstart, &memsize); physmem = memsize / PAGE_SIZE; cninit(); /* Set stack for exception handlers */ undefined_init(); init_proc0(kernelstack.pv_va); arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); pmap_curmaxkvaddr = afterkern + PAGE_SIZE; vm_max_kernel_address = 0xd0000000; pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); /* * Add the physical ram we have available. * * Exclude the kernel (and all the things we allocated which immediately * follow the kernel) from the VM allocation pool but not from crash * dumps. virtual_avail is a global variable which tracks the kva we've * "allocated" while setting up pmaps. * * Prepare the list of physical memory available to the vm subsystem. */ arm_physmem_hardware_region(SDRAM_START, memsize); arm_physmem_exclude_region(abp->abp_physaddr, virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC); arm_physmem_init_kernel_globals(); init_param2(physmem); kdb_init(); return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - sizeof(struct pcb))); } Index: stable/10/sys/arm/xscale/i8134x/files.i81342 =================================================================== --- stable/10/sys/arm/xscale/i8134x/files.i81342 (revision 278726) +++ stable/10/sys/arm/xscale/i8134x/files.i81342 (revision 278727) @@ -1,15 +1,15 @@ # $FreeBSD$ +arm/arm/bus_space_base.c standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_xscale.S standard arm/arm/cpufunc_asm_xscale_c3.S standard arm/xscale/i80321/i80321_timer.c standard arm/xscale/i80321/i80321_wdog.c optional iopwdog arm/xscale/i8134x/i81342.c standard arm/xscale/i8134x/i81342_mcu.c standard arm/xscale/i8134x/i81342_pci.c optional pci arm/xscale/i8134x/i81342_space.c standard arm/xscale/i8134x/obio.c standard -arm/xscale/i8134x/obio_space.c standard arm/xscale/i8134x/uart_bus_i81342.c optional uart arm/xscale/i8134x/uart_cpu_i81342.c optional uart dev/uart/uart_dev_ns8250.c optional uart Index: stable/10/sys/arm/xscale/i8134x/i81342_space.c =================================================================== --- stable/10/sys/arm/xscale/i8134x/i81342_space.c (revision 278726) +++ stable/10/sys/arm/xscale/i8134x/i81342_space.c (revision 278727) @@ -1,345 +1,232 @@ /* $NetBSD: i80321_space.c,v 1.6 2003/10/06 15:43:35 thorpej Exp $ */ /*- * Copyright (c) 2001, 2002 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * bus_space functions for i81342 I/O Processor. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include /* Prototypes for all the bus_space structure functions */ bs_protos(i81342); bs_protos(i81342_io); bs_protos(i81342_mem); -bs_protos(generic); -bs_protos(generic_armv4); -/* - * Template bus_space -- copied, and the bits that are NULL are - * filled in. - */ -const struct bus_space i81342_bs_tag_template = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - NULL, - NULL, - i81342_bs_subregion, - - /* allocation/deallocation */ - NULL, - NULL, - - /* barrier */ - i81342_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - NULL, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - generic_armv4_bs_sr_2, - generic_bs_sr_4, - NULL, - - /* copy */ - NULL, - generic_armv4_bs_c_2, - NULL, - NULL, - - /* read (single) stream */ - generic_bs_r_1, - generic_armv4_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple stream */ - generic_bs_rm_1, - generic_armv4_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region stream */ - generic_bs_rr_1, - generic_armv4_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) stream */ - generic_bs_w_1, - generic_armv4_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple stream */ - generic_bs_wm_1, - generic_armv4_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region stream */ - NULL, - generic_armv4_bs_wr_2, - generic_bs_wr_4, - NULL, -}; - void i81342_bs_init(bus_space_tag_t bs, void *cookie) { - *bs = i81342_bs_tag_template; - bs->bs_cookie = cookie; + *bs = *arm_base_bs_tag; + bs->bs_privdata = cookie; } void i81342_io_bs_init(bus_space_tag_t bs, void *cookie) { - *bs = i81342_bs_tag_template; - bs->bs_cookie = cookie; + *bs = *arm_base_bs_tag; + bs->bs_privdata = cookie; bs->bs_map = i81342_io_bs_map; bs->bs_unmap = i81342_io_bs_unmap; bs->bs_alloc = i81342_io_bs_alloc; bs->bs_free = i81342_io_bs_free; } void i81342_mem_bs_init(bus_space_tag_t bs, void *cookie) { - *bs = i81342_bs_tag_template; - bs->bs_cookie = cookie; + *bs = *arm_base_bs_tag; + bs->bs_privdata = cookie; bs->bs_map = i81342_mem_bs_map; bs->bs_unmap = i81342_mem_bs_unmap; bs->bs_alloc = i81342_mem_bs_alloc; bs->bs_free = i81342_mem_bs_free; } /* *** Routines shared by i81342, PCI IO, and PCI MEM. *** */ int -i81342_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, +i81342_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) { *nbshp = bsh + offset; return (0); } void -i81342_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, +i81342_bs_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, bus_size_t len, int flags) { /* Nothing to do. */ } /* *** Routines for PCI IO. *** */ int -i81342_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, +i81342_io_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) { *bshp = bpa; return (0); } void -i81342_io_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) +i81342_io_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) { /* Nothing to do. */ } int -i81342_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, +i81342_io_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) { panic("i81342_io_bs_alloc(): not implemented"); } void -i81342_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) +i81342_io_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) { panic("i81342_io_bs_free(): not implemented"); } /* *** Routines for PCI MEM. *** */ extern int badaddr_read(void *, int, void *); static vm_offset_t allocable = 0xe1000000; int -i81342_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, +i81342_mem_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) { - struct i81342_pci_softc *sc = (struct i81342_pci_softc *)t; + struct i81342_pci_softc *sc = (struct i81342_pci_softc *)tag->bs_privdata; struct i81342_pci_map *tmp; vm_offset_t addr, endaddr; vm_paddr_t paddr; /* Lookup to see if we already have a mapping at this address. */ tmp = sc->sc_pci_mappings; while (tmp) { if (tmp->paddr <= bpa && tmp->paddr + tmp->size > bpa + size) { *bshp = bpa - tmp->paddr + tmp->vaddr; return (0); } tmp = tmp->next; } addr = allocable; endaddr = ((addr + size) &~ (0x1000000 - 1)) + 0x1000000; if (endaddr >= IOP34X_VADDR) panic("PCI virtual memory exhausted"); allocable = endaddr; tmp = malloc(sizeof(*tmp), M_DEVBUF, M_WAITOK); tmp->next = NULL; paddr = bpa &~ (0x100000 - 1); tmp->paddr = paddr; tmp->vaddr = addr; tmp->size = 0; while (addr < endaddr) { pmap_kenter_supersection(addr, paddr + (sc->sc_is_atux ? IOP34X_PCIX_OMBAR : IOP34X_PCIE_OMBAR), 0); addr += 0x1000000; paddr += 0x1000000; tmp->size += 0x1000000; } tmp->next = sc->sc_pci_mappings; sc->sc_pci_mappings = tmp; *bshp = bpa - tmp->paddr + tmp->vaddr; return (0); } void -i81342_mem_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) +i81342_mem_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) { #if 0 vm_offset_t va, endva; - va = trunc_page((vm_offset_t)t); + va = trunc_page((vm_offset_t)h); endva = va + round_page(size); /* Free the kernel virtual mapping. */ kva_free(va, endva - va); #endif } int -i81342_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, +i81342_mem_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) { panic("i81342_mem_bs_alloc(): not implemented"); } void -i81342_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) +i81342_mem_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) { panic("i81342_mem_bs_free(): not implemented"); } Index: stable/10/sys/arm/xscale/i8134x/obio.c =================================================================== --- stable/10/sys/arm/xscale/i8134x/obio.c (revision 278726) +++ stable/10/sys/arm/xscale/i8134x/obio.c (revision 278727) @@ -1,167 +1,169 @@ /* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */ /*- * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * On-board device autoconfiguration support for Intel IQ80321 * evaluation boards. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include +bus_space_tag_t obio_bs_tag; static int obio_probe(device_t dev) { return (0); } static int obio_attach(device_t dev) { struct obio_softc *sc = device_get_softc(dev); - sc->oba_st = &obio_bs_tag; + obio_bs_tag = arm_base_bs_tag; + sc->oba_st = obio_bs_tag; sc->oba_rman.rm_type = RMAN_ARRAY; sc->oba_rman.rm_descr = "OBIO I/O"; if (rman_init(&sc->oba_rman) != 0 || rman_manage_region(&sc->oba_rman, IOP34X_UART0_VADDR, IOP34X_UART1_VADDR + 0x40) != 0) panic("obio_attach: failed to set up I/O rman"); sc->oba_irq_rman.rm_type = RMAN_ARRAY; sc->oba_irq_rman.rm_descr = "OBIO IRQ"; if (rman_init(&sc->oba_irq_rman) != 0 || rman_manage_region(&sc->oba_irq_rman, ICU_INT_UART0, ICU_INT_UART1) != 0) panic("obio_attach: failed to set up IRQ rman"); device_add_child(dev, "uart", 0); device_add_child(dev, "uart", 1); bus_generic_probe(dev); bus_generic_attach(dev); return (0); } static struct resource * obio_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct resource *rv; struct rman *rm; bus_space_tag_t bt = NULL; bus_space_handle_t bh = 0; struct obio_softc *sc = device_get_softc(bus); int unit = device_get_unit(child); switch (type) { case SYS_RES_IRQ: rm = &sc->oba_irq_rman; if (unit == 0) start = end = ICU_INT_UART0; else start = end = ICU_INT_UART1; break; case SYS_RES_MEMORY: return (NULL); case SYS_RES_IOPORT: rm = &sc->oba_rman; bt = sc->oba_st; if (unit == 0) { bh = IOP34X_UART0_VADDR; start = bh; end = IOP34X_UART1_VADDR; } else { bh = IOP34X_UART1_VADDR; start = bh; end = start + 0x40; } break; default: return (NULL); } rv = rman_reserve_resource(rm, start, end, count, flags, child); if (rv == NULL) return (NULL); if (type == SYS_RES_IRQ) return (rv); rman_set_rid(rv, *rid); rman_set_bustag(rv, bt); rman_set_bushandle(rv, bh); return (rv); } static int obio_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { return (0); } static device_method_t obio_methods[] = { DEVMETHOD(device_probe, obio_probe), DEVMETHOD(device_attach, obio_attach), DEVMETHOD(bus_alloc_resource, obio_alloc_resource), DEVMETHOD(bus_activate_resource, obio_activate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), {0, 0}, }; static driver_t obio_driver = { "obio", obio_methods, sizeof(struct obio_softc), }; static devclass_t obio_devclass; DRIVER_MODULE(obio, iq, obio_driver, obio_devclass, 0, 0); Index: stable/10/sys/arm/xscale/i8134x/obiovar.h =================================================================== --- stable/10/sys/arm/xscale/i8134x/obiovar.h (revision 278726) +++ stable/10/sys/arm/xscale/i8134x/obiovar.h (revision 278727) @@ -1,55 +1,55 @@ /* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */ /*- * Copyright (c) 2002, 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef _IQ81342_OBIOVAR_H_ #define _IQ81342_OBIOVAR_H_ #include struct obio_softc { bus_space_tag_t oba_st; /* bus space tag */ int oba_irq; /* XINT interrupt bit # */ struct rman oba_rman; struct rman oba_irq_rman; }; -extern struct bus_space obio_bs_tag; +extern bus_space_tag_t obio_bs_tag; #endif /* _IQ80321_OBIOVAR_H_ */ Index: stable/10/sys/arm/xscale/i8134x/uart_cpu_i81342.c =================================================================== --- stable/10/sys/arm/xscale/i8134x/uart_cpu_i81342.c (revision 278726) +++ stable/10/sys/arm/xscale/i8134x/uart_cpu_i81342.c (revision 278727) @@ -1,68 +1,68 @@ /*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; int uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) { return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); } int uart_cpu_getdev(int devtype, struct uart_devinfo *di) { di->ops = uart_getops(&uart_ns8250_class); di->bas.chan = 0; - di->bas.bst = &obio_bs_tag; + di->bas.bst = obio_bs_tag; di->bas.regshft = 2; di->bas.rclk = 33334000; di->baudrate = 115200; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; - uart_bus_space_io = &obio_bs_tag; + uart_bus_space_io = obio_bs_tag; uart_bus_space_mem = NULL; di->bas.bsh = IOP34X_UART0_VADDR; return (0); } Index: stable/10/sys/arm/xscale/ixp425/avila_ata.c =================================================================== --- stable/10/sys/arm/xscale/ixp425/avila_ata.c (revision 278726) +++ stable/10/sys/arm/xscale/ixp425/avila_ata.c (revision 278727) @@ -1,553 +1,553 @@ /*- * Copyright (c) 2006 Sam Leffler, Errno Consulting * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * Compact Flash Support for the Avila Gateworks XScale boards. * The CF slot is operated in "True IDE" mode. Registers are on * the Expansion Bus connected to CS1 and CS2. Interrupts are * tied to GPIO pin 12. No DMA, just PIO. * * The ADI Pronghorn Metro is very similar. It use CS3 and CS4 and * GPIO pin 0 for interrupts. * * See also http://www.intel.com/design/network/applnots/302456.htm. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define AVILA_IDE_CTRL 0x06 struct ata_config { const char *desc; /* description for probe */ uint8_t gpin; /* GPIO pin */ uint8_t irq; /* IRQ */ uint32_t base16; /* CS base addr for 16-bit */ uint32_t size16; /* CS size for 16-bit */ uint32_t off16; /* CS offset for 16-bit */ uint32_t basealt; /* CS base addr for alt */ uint32_t sizealt; /* CS size for alt */ uint32_t offalt; /* CS offset for alt */ }; static const struct ata_config * ata_getconfig(struct ixp425_softc *sa) { static const struct ata_config configs[] = { { .desc = "Gateworks Avila IDE/CF Controller", .gpin = 12, .irq = IXP425_INT_GPIO_12, .base16 = IXP425_EXP_BUS_CS1_HWBASE, .size16 = IXP425_EXP_BUS_CS1_SIZE, .off16 = EXP_TIMING_CS1_OFFSET, .basealt = IXP425_EXP_BUS_CS2_HWBASE, .sizealt = IXP425_EXP_BUS_CS2_SIZE, .offalt = EXP_TIMING_CS2_OFFSET, }, { .desc = "Gateworks Cambria IDE/CF Controller", .gpin = 12, .irq = IXP425_INT_GPIO_12, .base16 = CAMBRIA_CFSEL0_HWBASE, .size16 = CAMBRIA_CFSEL0_SIZE, .off16 = EXP_TIMING_CS3_OFFSET, .basealt = CAMBRIA_CFSEL1_HWBASE, .sizealt = CAMBRIA_CFSEL1_SIZE, .offalt = EXP_TIMING_CS4_OFFSET, }, { .desc = "ADI Pronghorn Metro IDE/CF Controller", .gpin = 0, .irq = IXP425_INT_GPIO_0, .base16 = IXP425_EXP_BUS_CS3_HWBASE, .size16 = IXP425_EXP_BUS_CS3_SIZE, .off16 = EXP_TIMING_CS3_OFFSET, .basealt = IXP425_EXP_BUS_CS4_HWBASE, .sizealt = IXP425_EXP_BUS_CS4_SIZE, .offalt = EXP_TIMING_CS4_OFFSET, }, }; /* XXX honor hint? (but then no multi-board support) */ /* XXX total hack */ if (cpu_is_ixp43x()) return &configs[1]; /* Cambria */ if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0) return &configs[0]; /* Avila */ return &configs[2]; /* Pronghorn */ } struct ata_avila_softc { device_t sc_dev; bus_space_tag_t sc_iot; bus_space_handle_t sc_exp_ioh; /* Exp Bus config registers */ bus_space_handle_t sc_ioh; /* CS1/3 data registers */ bus_space_handle_t sc_alt_ioh; /* CS2/4 data registers */ struct bus_space sc_expbus_tag; struct resource sc_ata; /* hand-crafted for ATA */ struct resource sc_alt_ata; /* hand-crafted for ATA */ u_int32_t sc_16bit_off; /* EXP_TIMING_CSx_OFFSET */ int sc_rid; /* rid for IRQ */ struct resource *sc_irq; /* IRQ resource */ void *sc_ih; /* interrupt handler */ struct { void (*cb)(void *); void *arg; } sc_intr[1]; /* NB: 1/channel */ }; static void ata_avila_intr(void *); bs_protos(ata); -static void ata_bs_rm_2_s(void *, bus_space_handle_t, bus_size_t, +static void ata_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t *, bus_size_t); -static void ata_bs_wm_2_s(void *, bus_space_handle_t, bus_size_t, +static void ata_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, const u_int16_t *, bus_size_t); static int ata_avila_probe(device_t dev) { struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); const struct ata_config *config; config = ata_getconfig(sa); if (config != NULL) { device_set_desc_copy(dev, config->desc); return 0; } return ENXIO; } static int ata_avila_attach(device_t dev) { struct ata_avila_softc *sc = device_get_softc(dev); struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); const struct ata_config *config; config = ata_getconfig(sa); KASSERT(config != NULL, ("no board config")); sc->sc_dev = dev; /* NB: borrow from parent */ sc->sc_iot = sa->sc_iot; sc->sc_exp_ioh = sa->sc_exp_ioh; if (bus_space_map(sc->sc_iot, config->base16, config->size16, 0, &sc->sc_ioh)) panic("%s: cannot map 16-bit window (0x%x/0x%x)", __func__, config->base16, config->size16); if (bus_space_map(sc->sc_iot, config->basealt, config->sizealt, 0, &sc->sc_alt_ioh)) panic("%s: cannot map alt window (0x%x/0x%x)", __func__, config->basealt, config->sizealt); sc->sc_16bit_off = config->off16; if (config->base16 != CAMBRIA_CFSEL0_HWBASE) { /* * Craft special resource for ATA bus space ops * that go through the expansion bus and require * special hackery to ena/dis 16-bit operations. * * XXX probably should just make this generic for * accessing the expansion bus. */ - sc->sc_expbus_tag.bs_cookie = sc; /* NB: backpointer */ + sc->sc_expbus_tag.bs_privdata = sc; /* NB: backpointer */ /* read single */ sc->sc_expbus_tag.bs_r_1 = ata_bs_r_1, sc->sc_expbus_tag.bs_r_2 = ata_bs_r_2, /* read multiple */ sc->sc_expbus_tag.bs_rm_2 = ata_bs_rm_2, sc->sc_expbus_tag.bs_rm_2_s = ata_bs_rm_2_s, /* write (single) */ sc->sc_expbus_tag.bs_w_1 = ata_bs_w_1, sc->sc_expbus_tag.bs_w_2 = ata_bs_w_2, /* write multiple */ sc->sc_expbus_tag.bs_wm_2 = ata_bs_wm_2, sc->sc_expbus_tag.bs_wm_2_s = ata_bs_wm_2_s, rman_set_bustag(&sc->sc_ata, &sc->sc_expbus_tag); rman_set_bustag(&sc->sc_alt_ata, &sc->sc_expbus_tag); } else { /* * On Cambria use the shared CS3 expansion bus tag * that handles interlock for sharing access with the * optional UART's. */ rman_set_bustag(&sc->sc_ata, &cambria_exp_bs_tag); rman_set_bustag(&sc->sc_alt_ata, &cambria_exp_bs_tag); } rman_set_bushandle(&sc->sc_ata, sc->sc_ioh); rman_set_bushandle(&sc->sc_alt_ata, sc->sc_alt_ioh); ixp425_set_gpio(sa, config->gpin, GPIO_TYPE_EDG_RISING); /* configure CS1/3 window, leaving timing unchanged */ EXP_BUS_WRITE_4(sc, sc->sc_16bit_off, EXP_BUS_READ_4(sc, sc->sc_16bit_off) | EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN); /* configure CS2/4 window, leaving timing unchanged */ EXP_BUS_WRITE_4(sc, config->offalt, EXP_BUS_READ_4(sc, config->offalt) | EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN); /* setup interrupt */ sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid, config->irq, config->irq, 1, RF_ACTIVE); if (!sc->sc_irq) panic("Unable to allocate irq %u.\n", config->irq); bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY, NULL, ata_avila_intr, sc, &sc->sc_ih); /* attach channel on this controller */ device_add_child(dev, "ata", -1); bus_generic_attach(dev); return 0; } static int ata_avila_detach(device_t dev) { struct ata_avila_softc *sc = device_get_softc(dev); /* XXX quiesce gpio? */ /* detach & delete all children */ device_delete_children(dev); bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rid, sc->sc_irq); return 0; } static void ata_avila_intr(void *xsc) { struct ata_avila_softc *sc = xsc; if (sc->sc_intr[0].cb != NULL) sc->sc_intr[0].cb(sc->sc_intr[0].arg); } static struct resource * ata_avila_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct ata_avila_softc *sc = device_get_softc(dev); KASSERT(type == SYS_RES_IRQ && *rid == ATA_IRQ_RID, ("type %u rid %u start %lu end %lu count %lu flags %u", type, *rid, start, end, count, flags)); /* doesn't matter what we return so reuse the real thing */ return sc->sc_irq; } static int ata_avila_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { KASSERT(type == SYS_RES_IRQ && rid == ATA_IRQ_RID, ("type %u rid %u", type, rid)); return 0; } static int ata_avila_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, driver_filter_t *filt, driver_intr_t *function, void *argument, void **cookiep) { struct ata_avila_softc *sc = device_get_softc(dev); int unit = ((struct ata_channel *)device_get_softc(child))->unit; KASSERT(unit == 0, ("unit %d", unit)); sc->sc_intr[unit].cb = function; sc->sc_intr[unit].arg = argument; *cookiep = sc; return 0; } static int ata_avila_teardown_intr(device_t dev, device_t child, struct resource *irq, void *cookie) { struct ata_avila_softc *sc = device_get_softc(dev); int unit = ((struct ata_channel *)device_get_softc(child))->unit; KASSERT(unit == 0, ("unit %d", unit)); sc->sc_intr[unit].cb = NULL; sc->sc_intr[unit].arg = NULL; return 0; } /* * Bus space accessors for CF-IDE PIO operations. */ /* * Enable/disable 16-bit ops on the expansion bus. */ static __inline void enable_16(struct ata_avila_softc *sc) { EXP_BUS_WRITE_4(sc, sc->sc_16bit_off, EXP_BUS_READ_4(sc, sc->sc_16bit_off) &~ EXP_BYTE_EN); DELAY(100); /* XXX? */ } static __inline void disable_16(struct ata_avila_softc *sc) { DELAY(100); /* XXX? */ EXP_BUS_WRITE_4(sc, sc->sc_16bit_off, EXP_BUS_READ_4(sc, sc->sc_16bit_off) | EXP_BYTE_EN); } uint8_t -ata_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o) +ata_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) { - struct ata_avila_softc *sc = t; + struct ata_avila_softc *sc = tag->bs_privdata; return bus_space_read_1(sc->sc_iot, h, o); } void -ata_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v) +ata_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v) { - struct ata_avila_softc *sc = t; + struct ata_avila_softc *sc = tag->bs_privdata; bus_space_write_1(sc->sc_iot, h, o, v); } uint16_t -ata_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o) +ata_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) { - struct ata_avila_softc *sc = t; + struct ata_avila_softc *sc = tag->bs_privdata; uint16_t v; enable_16(sc); v = bus_space_read_2(sc->sc_iot, h, o); disable_16(sc); return v; } void -ata_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v) +ata_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v) { - struct ata_avila_softc *sc = t; + struct ata_avila_softc *sc = tag->bs_privdata; enable_16(sc); bus_space_write_2(sc->sc_iot, h, o, v); disable_16(sc); } void -ata_bs_rm_2(void *t, bus_space_handle_t h, bus_size_t o, +ata_bs_rm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int16_t *d, bus_size_t c) { - struct ata_avila_softc *sc = t; + struct ata_avila_softc *sc = tag->bs_privdata; enable_16(sc); bus_space_read_multi_2(sc->sc_iot, h, o, d, c); disable_16(sc); } void -ata_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o, +ata_bs_wm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, const u_int16_t *d, bus_size_t c) { - struct ata_avila_softc *sc = t; + struct ata_avila_softc *sc = tag->bs_privdata; enable_16(sc); bus_space_write_multi_2(sc->sc_iot, h, o, d, c); disable_16(sc); } /* XXX workaround ata driver by (incorrectly) byte swapping stream cases */ void -ata_bs_rm_2_s(void *t, bus_space_handle_t h, bus_size_t o, +ata_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int16_t *d, bus_size_t c) { - struct ata_avila_softc *sc = t; + struct ata_avila_softc *sc = tag->bs_privdata; uint16_t v; bus_size_t i; enable_16(sc); #if 1 for (i = 0; i < c; i++) { v = bus_space_read_2(sc->sc_iot, h, o); d[i] = bswap16(v); } #else bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c); #endif disable_16(sc); } void -ata_bs_wm_2_s(void *t, bus_space_handle_t h, bus_size_t o, +ata_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, const u_int16_t *d, bus_size_t c) { - struct ata_avila_softc *sc = t; + struct ata_avila_softc *sc = tag->bs_privdata; bus_size_t i; enable_16(sc); #if 1 for (i = 0; i < c; i++) bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i])); #else bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c); #endif disable_16(sc); } static device_method_t ata_avila_methods[] = { /* device interface */ DEVMETHOD(device_probe, ata_avila_probe), DEVMETHOD(device_attach, ata_avila_attach), DEVMETHOD(device_detach, ata_avila_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), /* bus methods */ DEVMETHOD(bus_alloc_resource, ata_avila_alloc_resource), DEVMETHOD(bus_release_resource, ata_avila_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, ata_avila_setup_intr), DEVMETHOD(bus_teardown_intr, ata_avila_teardown_intr), { 0, 0 } }; devclass_t ata_avila_devclass; static driver_t ata_avila_driver = { "ata_avila", ata_avila_methods, sizeof(struct ata_avila_softc), }; DRIVER_MODULE(ata_avila, ixp, ata_avila_driver, ata_avila_devclass, 0, 0); MODULE_VERSION(ata_avila, 1); MODULE_DEPEND(ata_avila, ata, 1, 1, 1); static int avila_channel_probe(device_t dev) { struct ata_channel *ch = device_get_softc(dev); ch->unit = 0; ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE; device_set_desc_copy(dev, "ATA channel 0"); return ata_probe(dev); } static int avila_channel_attach(device_t dev) { struct ata_avila_softc *sc = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); int i; for (i = 0; i < ATA_MAX_RES; i++) ch->r_io[i].res = &sc->sc_ata; ch->r_io[ATA_DATA].offset = ATA_DATA; ch->r_io[ATA_FEATURE].offset = ATA_FEATURE; ch->r_io[ATA_COUNT].offset = ATA_COUNT; ch->r_io[ATA_SECTOR].offset = ATA_SECTOR; ch->r_io[ATA_CYL_LSB].offset = ATA_CYL_LSB; ch->r_io[ATA_CYL_MSB].offset = ATA_CYL_MSB; ch->r_io[ATA_DRIVE].offset = ATA_DRIVE; ch->r_io[ATA_COMMAND].offset = ATA_COMMAND; ch->r_io[ATA_ERROR].offset = ATA_FEATURE; /* NB: should be used only for ATAPI devices */ ch->r_io[ATA_IREASON].offset = ATA_COUNT; ch->r_io[ATA_STATUS].offset = ATA_COMMAND; /* NB: the control and alt status registers are special */ ch->r_io[ATA_ALTSTAT].res = &sc->sc_alt_ata; ch->r_io[ATA_ALTSTAT].offset = AVILA_IDE_CTRL; ch->r_io[ATA_CONTROL].res = &sc->sc_alt_ata; ch->r_io[ATA_CONTROL].offset = AVILA_IDE_CTRL; /* NB: by convention this points at the base of registers */ ch->r_io[ATA_IDX_ADDR].offset = 0; ata_generic_hw(dev); return ata_attach(dev); } static device_method_t avila_channel_methods[] = { /* device interface */ DEVMETHOD(device_probe, avila_channel_probe), DEVMETHOD(device_attach, avila_channel_attach), DEVMETHOD(device_detach, ata_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, ata_suspend), DEVMETHOD(device_resume, ata_resume), { 0, 0 } }; driver_t avila_channel_driver = { "ata", avila_channel_methods, sizeof(struct ata_channel), }; DRIVER_MODULE(ata, ata_avila, avila_channel_driver, ata_devclass, 0, 0); Index: stable/10/sys/arm/xscale/ixp425/cambria_exp_space.c =================================================================== --- stable/10/sys/arm/xscale/ixp425/cambria_exp_space.c (revision 278726) +++ stable/10/sys/arm/xscale/ixp425/cambria_exp_space.c (revision 278727) @@ -1,258 +1,258 @@ /*- * Copyright (c) 2009 Sam Leffler. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Bus space tag for devices on the Cambria expansion bus. * This interlocks accesses to allow the optional GPS+RS485 UART's * to share access with the CF-IDE adapter. Note this does not * slow the timing UART r/w ops because the lock operation does * this implicitly for us. Also note we do not DELAY after byte/word * chip select changes; this doesn't seem necessary (as required * for IXP425/Avila boards). * * XXX should make this generic so all expansion bus devices can * use it but probably not until we eliminate the ATA hacks */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include /* Prototypes for all the bus_space structure functions */ bs_protos(exp); bs_protos(generic); struct expbus_softc { struct ixp425_softc *sc; /* bus space tag */ struct mtx lock; /* i/o interlock */ bus_size_t csoff; /* CS offset for 8/16 enable */ }; #define EXP_LOCK_INIT(exp) \ mtx_init(&(exp)->lock, "ExpBus", NULL, MTX_SPIN) #define EXP_LOCK_DESTROY(exp) \ mtx_destroy(&(exp)->lock) #define EXP_LOCK(exp) mtx_lock_spin(&(exp)->lock) #define EXP_UNLOCK(exp) mtx_unlock_spin(&(exp)->lock) /* * Enable/disable 16-bit ops on the expansion bus. */ static __inline void enable_16(struct ixp425_softc *sc, bus_size_t cs) { EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) &~ EXP_BYTE_EN); } static __inline void disable_16(struct ixp425_softc *sc, bus_size_t cs) { EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) | EXP_BYTE_EN); } static uint8_t -cambria_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o) +cambria_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) { - struct expbus_softc *exp = t; + struct expbus_softc *exp = tag->bs_privdata; struct ixp425_softc *sc = exp->sc; uint8_t v; EXP_LOCK(exp); v = bus_space_read_1(sc->sc_iot, h, o); EXP_UNLOCK(exp); return v; } static void -cambria_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v) +cambria_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v) { - struct expbus_softc *exp = t; + struct expbus_softc *exp = tag->bs_privdata; struct ixp425_softc *sc = exp->sc; EXP_LOCK(exp); bus_space_write_1(sc->sc_iot, h, o, v); EXP_UNLOCK(exp); } static uint16_t -cambria_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o) +cambria_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) { - struct expbus_softc *exp = t; + struct expbus_softc *exp = tag->bs_privdata; struct ixp425_softc *sc = exp->sc; uint16_t v; EXP_LOCK(exp); enable_16(sc, exp->csoff); v = bus_space_read_2(sc->sc_iot, h, o); disable_16(sc, exp->csoff); EXP_UNLOCK(exp); return v; } static void -cambria_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v) +cambria_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v) { - struct expbus_softc *exp = t; + struct expbus_softc *exp = tag->bs_privdata; struct ixp425_softc *sc = exp->sc; EXP_LOCK(exp); enable_16(sc, exp->csoff); bus_space_write_2(sc->sc_iot, h, o, v); disable_16(sc, exp->csoff); EXP_UNLOCK(exp); } static void -cambria_bs_rm_2(void *t, bus_space_handle_t h, bus_size_t o, +cambria_bs_rm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int16_t *d, bus_size_t c) { - struct expbus_softc *exp = t; + struct expbus_softc *exp = tag->bs_privdata; struct ixp425_softc *sc = exp->sc; EXP_LOCK(exp); enable_16(sc, exp->csoff); bus_space_read_multi_2(sc->sc_iot, h, o, d, c); disable_16(sc, exp->csoff); EXP_UNLOCK(exp); } static void -cambria_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o, +cambria_bs_wm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, const u_int16_t *d, bus_size_t c) { - struct expbus_softc *exp = t; + struct expbus_softc *exp = tag->bs_privdata; struct ixp425_softc *sc = exp->sc; EXP_LOCK(exp); enable_16(sc, exp->csoff); bus_space_write_multi_2(sc->sc_iot, h, o, d, c); disable_16(sc, exp->csoff); EXP_UNLOCK(exp); } /* XXX workaround ata driver by (incorrectly) byte swapping stream cases */ static void -cambria_bs_rm_2_s(void *t, bus_space_handle_t h, bus_size_t o, +cambria_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int16_t *d, bus_size_t c) { - struct expbus_softc *exp = t; + struct expbus_softc *exp = tag->bs_privdata; struct ixp425_softc *sc = exp->sc; uint16_t v; bus_size_t i; EXP_LOCK(exp); enable_16(sc, exp->csoff); #if 1 for (i = 0; i < c; i++) { v = bus_space_read_2(sc->sc_iot, h, o); d[i] = bswap16(v); } #else bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c); #endif disable_16(sc, exp->csoff); EXP_UNLOCK(exp); } static void -cambria_bs_wm_2_s(void *t, bus_space_handle_t h, bus_size_t o, +cambria_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, const u_int16_t *d, bus_size_t c) { - struct expbus_softc *exp = t; + struct expbus_softc *exp = tag->bs_privdata; struct ixp425_softc *sc = exp->sc; bus_size_t i; EXP_LOCK(exp); enable_16(sc, exp->csoff); #if 1 for (i = 0; i < c; i++) bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i])); #else bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c); #endif disable_16(sc, exp->csoff); EXP_UNLOCK(exp); } /* NB: we only define what's needed by ata+uart */ struct bus_space cambria_exp_bs_tag = { /* mapping/unmapping */ .bs_map = generic_bs_map, .bs_unmap = generic_bs_unmap, /* barrier */ .bs_barrier = generic_bs_barrier, /* read (single) */ .bs_r_1 = cambria_bs_r_1, .bs_r_2 = cambria_bs_r_2, /* write (single) */ .bs_w_1 = cambria_bs_w_1, .bs_w_2 = cambria_bs_w_2, /* read multiple */ .bs_rm_2 = cambria_bs_rm_2, .bs_rm_2_s = cambria_bs_rm_2_s, /* write multiple */ .bs_wm_2 = cambria_bs_wm_2, .bs_wm_2_s = cambria_bs_wm_2_s, }; void cambria_exp_bus_init(struct ixp425_softc *sc) { static struct expbus_softc c3; /* NB: no need to malloc */ uint32_t cs3; KASSERT(cpu_is_ixp43x(), ("wrong cpu type")); c3.sc = sc; c3.csoff = EXP_TIMING_CS3_OFFSET; EXP_LOCK_INIT(&c3); - cambria_exp_bs_tag.bs_cookie = &c3; + cambria_exp_bs_tag.bs_privdata = &c3; cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET); /* XXX force slowest possible timings and byte mode */ EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET, cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) | EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN); /* XXX force GPIO 3+4 for GPS+RS485 uarts */ ixp425_set_gpio(sc, 3, GPIO_TYPE_EDG_RISING); ixp425_set_gpio(sc, 4, GPIO_TYPE_EDG_RISING); } Index: stable/10/sys/arm/xscale/ixp425/ixp425_a4x_space.c =================================================================== --- stable/10/sys/arm/xscale/ixp425/ixp425_a4x_space.c (revision 278726) +++ stable/10/sys/arm/xscale/ixp425/ixp425_a4x_space.c (revision 278727) @@ -1,115 +1,114 @@ /* $NetBSD: ixp425_a4x_space.c,v 1.2 2005/12/11 12:16:51 christos Exp $ */ /* * Copyright 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Steve C. Woodford for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * Bus space tag for 8/16-bit devices on 32-bit bus. * all registers are located at the address of multiple of 4. * * Based on pxa2x0_a4x_space.c */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include /* Prototypes for all the bus_space structure functions */ bs_protos(a4x); bs_protos(generic); -bs_protos(generic_armv4); struct bus_space ixp425_a4x_bs_tag = { /* cookie */ - .bs_cookie = (void *) 0, + .bs_privdata = (void *) 0, /* mapping/unmapping */ .bs_map = generic_bs_map, .bs_unmap = generic_bs_unmap, .bs_subregion = generic_bs_subregion, /* allocation/deallocation */ .bs_alloc = generic_bs_alloc, /* XXX not implemented */ .bs_free = generic_bs_free, /* XXX not implemented */ /* barrier */ .bs_barrier = generic_bs_barrier, /* read (single) */ .bs_r_1 = a4x_bs_r_1, .bs_r_2 = a4x_bs_r_2, .bs_r_4 = a4x_bs_r_4, /* read multiple */ .bs_rm_1 = a4x_bs_rm_1, .bs_rm_2 = a4x_bs_rm_2, /* read region */ /* XXX not implemented */ /* write (single) */ .bs_w_1 = a4x_bs_w_1, .bs_w_2 = a4x_bs_w_2, .bs_w_4 = a4x_bs_w_4, /* write multiple */ .bs_wm_1 = a4x_bs_wm_1, .bs_wm_2 = a4x_bs_wm_2, /* write region */ /* XXX not implemented */ /* set multiple */ /* XXX not implemented */ /* set region */ /* XXX not implemented */ /* copy */ /* XXX not implemented */ }; Index: stable/10/sys/arm/xscale/ixp425/ixp425_pci_space.c =================================================================== --- stable/10/sys/arm/xscale/ixp425/ixp425_pci_space.c (revision 278726) +++ stable/10/sys/arm/xscale/ixp425/ixp425_pci_space.c (revision 278727) @@ -1,496 +1,485 @@ /* $NetBSD: ixp425_pci_space.c,v 1.6 2006/04/10 03:36:03 simonb Exp $ */ /* * Copyright (c) 2003 * Ichiro FUKUHARA . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Ichiro FUKUHARA. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * bus_space PCI functions for ixp425 */ #include #include #include #include #include #include #include #include #include #include #include #include #include /* * Macros to read/write registers */ #define CSR_READ_4(x) *(volatile uint32_t *) \ (IXP425_PCI_CSR_BASE + (x)) #define CSR_WRITE_4(x, v) *(volatile uint32_t *) \ (IXP425_PCI_CSR_BASE + (x)) = (v) /* Proto types for all the bus_space structure functions */ bs_protos(ixp425_pci); bs_protos(ixp425_pci_io); bs_protos(ixp425_pci_mem); /* special I/O functions */ -static u_int8_t _pci_io_bs_r_1(void *, bus_space_handle_t, bus_size_t); -static u_int16_t _pci_io_bs_r_2(void *, bus_space_handle_t, bus_size_t); -static u_int32_t _pci_io_bs_r_4(void *, bus_space_handle_t, bus_size_t); +static u_int8_t _pci_io_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static u_int16_t _pci_io_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static u_int32_t _pci_io_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static void _pci_io_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t); -static void _pci_io_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t); -static void _pci_io_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t); +static void _pci_io_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t); +static void _pci_io_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t); +static void _pci_io_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t); #ifdef __ARMEB__ -static u_int8_t _pci_io_bs_r_1_s(void *, bus_space_handle_t, bus_size_t); -static u_int16_t _pci_io_bs_r_2_s(void *, bus_space_handle_t, bus_size_t); -static u_int32_t _pci_io_bs_r_4_s(void *, bus_space_handle_t, bus_size_t); +static u_int8_t _pci_io_bs_r_1_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static u_int16_t _pci_io_bs_r_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static u_int32_t _pci_io_bs_r_4_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static void _pci_io_bs_w_1_s(void *, bus_space_handle_t, bus_size_t, u_int8_t); -static void _pci_io_bs_w_2_s(void *, bus_space_handle_t, bus_size_t, u_int16_t); -static void _pci_io_bs_w_4_s(void *, bus_space_handle_t, bus_size_t, u_int32_t); +static void _pci_io_bs_w_1_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t); +static void _pci_io_bs_w_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t); +static void _pci_io_bs_w_4_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t); -static u_int8_t _pci_mem_bs_r_1(void *, bus_space_handle_t, bus_size_t); -static u_int16_t _pci_mem_bs_r_2(void *, bus_space_handle_t, bus_size_t); -static u_int32_t _pci_mem_bs_r_4(void *, bus_space_handle_t, bus_size_t); +static u_int8_t _pci_mem_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static u_int16_t _pci_mem_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static u_int32_t _pci_mem_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static void _pci_mem_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t); -static void _pci_mem_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t); -static void _pci_mem_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t); +static void _pci_mem_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t); +static void _pci_mem_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t); +static void _pci_mem_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t); #endif struct bus_space ixp425_pci_io_bs_tag_template = { /* mapping/unmapping */ .bs_map = ixp425_pci_io_bs_map, .bs_unmap = ixp425_pci_io_bs_unmap, .bs_subregion = ixp425_pci_bs_subregion, .bs_alloc = ixp425_pci_io_bs_alloc, .bs_free = ixp425_pci_io_bs_free, /* barrier */ .bs_barrier = ixp425_pci_bs_barrier, /* * IXP425 processor does not have PCI I/O windows */ /* read (single) */ .bs_r_1 = _pci_io_bs_r_1, .bs_r_2 = _pci_io_bs_r_2, .bs_r_4 = _pci_io_bs_r_4, /* write (single) */ .bs_w_1 = _pci_io_bs_w_1, .bs_w_2 = _pci_io_bs_w_2, .bs_w_4 = _pci_io_bs_w_4, #ifdef __ARMEB__ .bs_r_1_s = _pci_io_bs_r_1_s, .bs_r_2_s = _pci_io_bs_r_2_s, .bs_r_4_s = _pci_io_bs_r_4_s, .bs_w_1_s = _pci_io_bs_w_1_s, .bs_w_2_s = _pci_io_bs_w_2_s, .bs_w_4_s = _pci_io_bs_w_4_s, #else .bs_r_1_s = _pci_io_bs_r_1, .bs_r_2_s = _pci_io_bs_r_2, .bs_r_4_s = _pci_io_bs_r_4, .bs_w_1_s = _pci_io_bs_w_1, .bs_w_2_s = _pci_io_bs_w_2, .bs_w_4_s = _pci_io_bs_w_4, #endif }; void ixp425_io_bs_init(bus_space_tag_t bs, void *cookie) { *bs = ixp425_pci_io_bs_tag_template; - bs->bs_cookie = cookie; + bs->bs_privdata = cookie; } struct bus_space ixp425_pci_mem_bs_tag_template = { /* mapping/unmapping */ .bs_map = ixp425_pci_mem_bs_map, .bs_unmap = ixp425_pci_mem_bs_unmap, .bs_subregion = ixp425_pci_bs_subregion, .bs_alloc = ixp425_pci_mem_bs_alloc, .bs_free = ixp425_pci_mem_bs_free, /* barrier */ .bs_barrier = ixp425_pci_bs_barrier, #ifdef __ARMEB__ /* read (single) */ .bs_r_1_s = _pci_mem_bs_r_1, .bs_r_2_s = _pci_mem_bs_r_2, .bs_r_4_s = _pci_mem_bs_r_4, .bs_r_1 = ixp425_pci_mem_bs_r_1, .bs_r_2 = ixp425_pci_mem_bs_r_2, .bs_r_4 = ixp425_pci_mem_bs_r_4, /* write (single) */ .bs_w_1_s = _pci_mem_bs_w_1, .bs_w_2_s = _pci_mem_bs_w_2, .bs_w_4_s = _pci_mem_bs_w_4, .bs_w_1 = ixp425_pci_mem_bs_w_1, .bs_w_2 = ixp425_pci_mem_bs_w_2, .bs_w_4 = ixp425_pci_mem_bs_w_4, #else /* read (single) */ .bs_r_1 = ixp425_pci_mem_bs_r_1, .bs_r_2 = ixp425_pci_mem_bs_r_2, .bs_r_4 = ixp425_pci_mem_bs_r_4, .bs_r_1_s = ixp425_pci_mem_bs_r_1, .bs_r_2_s = ixp425_pci_mem_bs_r_2, .bs_r_4_s = ixp425_pci_mem_bs_r_4, /* write (single) */ .bs_w_1 = ixp425_pci_mem_bs_w_1, .bs_w_2 = ixp425_pci_mem_bs_w_2, .bs_w_4 = ixp425_pci_mem_bs_w_4, .bs_w_1_s = ixp425_pci_mem_bs_w_1, .bs_w_2_s = ixp425_pci_mem_bs_w_2, .bs_w_4_s = ixp425_pci_mem_bs_w_4, #endif }; void ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie) { *bs = ixp425_pci_mem_bs_tag_template; - bs->bs_cookie = cookie; + bs->bs_privdata = cookie; } /* common routine */ int -ixp425_pci_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, +ixp425_pci_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) { *nbshp = bsh + offset; return (0); } void -ixp425_pci_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, +ixp425_pci_bs_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, bus_size_t len, int flags) { /* NULL */ } /* io bs */ int -ixp425_pci_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, +ixp425_pci_io_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp) { *bshp = bpa; return (0); } void -ixp425_pci_io_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) +ixp425_pci_io_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) { /* Nothing to do. */ } int -ixp425_pci_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, +ixp425_pci_io_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable, bus_addr_t *bpap, bus_space_handle_t *bshp) { panic("ixp425_pci_io_bs_alloc(): not implemented\n"); } void -ixp425_pci_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) +ixp425_pci_io_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) { panic("ixp425_pci_io_bs_free(): not implemented\n"); } /* special I/O functions */ static __inline u_int32_t -_bs_r(void *v, bus_space_handle_t ioh, bus_size_t off, u_int32_t be) +_bs_r(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int32_t be) { u_int32_t data; CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); data = CSR_READ_4(PCI_NP_RDATA); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); return data; } static u_int8_t -_pci_io_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_io_bs_r_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; - data = _bs_r(v, ioh, off, be); + data = _bs_r(tag, ioh, off, be); return data >> (8 * n); } static u_int16_t -_pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_io_bs_r_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; - data = _bs_r(v, ioh, off, be); + data = _bs_r(tag, ioh, off, be); return data >> (8 * n); } static u_int32_t -_pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_io_bs_r_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data; - data = _bs_r(v, ioh, off, 0); + data = _bs_r(tag, ioh, off, 0); return data; } #ifdef __ARMEB__ static u_int8_t -_pci_io_bs_r_1_s(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_io_bs_r_1_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; - data = _bs_r(v, ioh, off, be); + data = _bs_r(tag, ioh, off, be); return data >> (8 * n); } static u_int16_t -_pci_io_bs_r_2_s(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_io_bs_r_2_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; - data = _bs_r(v, ioh, off, be); + data = _bs_r(tag, ioh, off, be); return data >> (8 * n); } static u_int32_t -_pci_io_bs_r_4_s(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_io_bs_r_4_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data; - data = _bs_r(v, ioh, off, 0); + data = _bs_r(tag, ioh, off, 0); return le32toh(data); } #endif /* __ARMEB__ */ static __inline void -_bs_w(void *v, bus_space_handle_t ioh, bus_size_t off, +_bs_w(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int32_t be, u_int32_t data) { CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); CSR_WRITE_4(PCI_NP_WDATA, data); if (CSR_READ_4(PCI_ISR) & ISR_PFE) CSR_WRITE_4(PCI_ISR, ISR_PFE); } static void -_pci_io_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_io_bs_w_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int8_t val) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; data = val << (8 * n); - _bs_w(v, ioh, off, be, data); + _bs_w(tag, ioh, off, be, data); } static void -_pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_io_bs_w_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int16_t val) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; data = val << (8 * n); - _bs_w(v, ioh, off, be, data); + _bs_w(tag, ioh, off, be, data); } static void -_pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_io_bs_w_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int32_t val) { - _bs_w(v, ioh, off, 0, val); + _bs_w(tag, ioh, off, 0, val); } #ifdef __ARMEB__ static void -_pci_io_bs_w_1_s(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_io_bs_w_1_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int8_t val) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; data = val << (8 * n); - _bs_w(v, ioh, off, be, data); + _bs_w(tag, ioh, off, be, data); } static void -_pci_io_bs_w_2_s(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_io_bs_w_2_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int16_t val) { u_int32_t data, n, be; n = (ioh + off) % 4; be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; data = val << (8 * n); - _bs_w(v, ioh, off, be, data); + _bs_w(tag, ioh, off, be, data); } static void -_pci_io_bs_w_4_s(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_io_bs_w_4_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int32_t val) { - _bs_w(v, ioh, off, 0, htole32(val)); + _bs_w(tag, ioh, off, 0, htole32(val)); } #endif /* __ARMEB__ */ /* mem bs */ int -ixp425_pci_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, +ixp425_pci_mem_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp) { - vm_paddr_t pa, endpa; - - pa = trunc_page(bpa); - endpa = round_page(bpa + size); - - *bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa); - + *bshp = (vm_offset_t)pmap_mapdev(bpa, size); return (0); } void -ixp425_pci_mem_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) +ixp425_pci_mem_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) { - vm_offset_t va, endva; - va = trunc_page((vm_offset_t)t); - endva = va + round_page(size); - - /* Free the kernel virtual mapping. */ - kva_free(va, endva - va); + pmap_unmapdev((vm_offset_t)h, size); } int -ixp425_pci_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, +ixp425_pci_mem_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable, bus_addr_t *bpap, bus_space_handle_t *bshp) { panic("ixp425_mem_bs_alloc(): not implemented\n"); } void -ixp425_pci_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size) +ixp425_pci_mem_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) { panic("ixp425_mem_bs_free(): not implemented\n"); } #ifdef __ARMEB__ static u_int8_t -_pci_mem_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_mem_bs_r_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { - return ixp425_pci_mem_bs_r_1(v, ioh, off); + return ixp425_pci_mem_bs_r_1(tag, ioh, off); } static u_int16_t -_pci_mem_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_mem_bs_r_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { - return (ixp425_pci_mem_bs_r_2(v, ioh, off)); + return (ixp425_pci_mem_bs_r_2(tag, ioh, off)); } static u_int32_t -_pci_mem_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off) +_pci_mem_bs_r_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) { u_int32_t data; - data = ixp425_pci_mem_bs_r_4(v, ioh, off); + data = ixp425_pci_mem_bs_r_4(tag, ioh, off); return (le32toh(data)); } static void -_pci_mem_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_mem_bs_w_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int8_t val) { - ixp425_pci_mem_bs_w_1(v, ioh, off, val); + ixp425_pci_mem_bs_w_1(tag, ioh, off, val); } static void -_pci_mem_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_mem_bs_w_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int16_t val) { - ixp425_pci_mem_bs_w_2(v, ioh, off, val); + ixp425_pci_mem_bs_w_2(tag, ioh, off, val); } static void -_pci_mem_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off, +_pci_mem_bs_w_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int32_t val) { - ixp425_pci_mem_bs_w_4(v, ioh, off, htole32(val)); + ixp425_pci_mem_bs_w_4(tag, ioh, off, htole32(val)); } #endif /* __ARMEB__ */ /* End of ixp425_pci_space.c */ Index: stable/10/sys/arm/xscale/ixp425/ixp425_space.c =================================================================== --- stable/10/sys/arm/xscale/ixp425/ixp425_space.c (revision 278726) +++ stable/10/sys/arm/xscale/ixp425/ixp425_space.c (revision 278727) @@ -1,130 +1,129 @@ /* $NetBSD: ixp425_space.c,v 1.6 2006/04/10 03:36:03 simonb Exp $ */ /* * Copyright (c) 2003 * Ichiro FUKUHARA . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Ichiro FUKUHARA. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * bus_space I/O functions for ixp425 */ #include #include #include #include #include #include #include #include #include #include #include #include /* Proto types for all the bus_space structure functions */ bs_protos(generic); -bs_protos(generic_armv4); struct bus_space ixp425_bs_tag = { /* cookie */ - .bs_cookie = (void *) 0, + .bs_privdata = (void *) 0, /* mapping/unmapping */ .bs_map = generic_bs_map, .bs_unmap = generic_bs_unmap, .bs_subregion = generic_bs_subregion, /* allocation/deallocation */ .bs_alloc = generic_bs_alloc, .bs_free = generic_bs_free, /* barrier */ .bs_barrier = generic_bs_barrier, /* read (single) */ .bs_r_1 = generic_bs_r_1, - .bs_r_2 = generic_armv4_bs_r_2, + .bs_r_2 = generic_bs_r_2, .bs_r_4 = generic_bs_r_4, .bs_r_8 = NULL, /* read multiple */ .bs_rm_1 = generic_bs_rm_1, - .bs_rm_2 = generic_armv4_bs_rm_2, + .bs_rm_2 = generic_bs_rm_2, .bs_rm_4 = generic_bs_rm_4, .bs_rm_8 = NULL, /* read region */ .bs_rr_1 = generic_bs_rr_1, - .bs_rr_2 = generic_armv4_bs_rr_2, + .bs_rr_2 = generic_bs_rr_2, .bs_rr_4 = generic_bs_rr_4, .bs_rr_8 = NULL, /* write (single) */ .bs_w_1 = generic_bs_w_1, - .bs_w_2 = generic_armv4_bs_w_2, + .bs_w_2 = generic_bs_w_2, .bs_w_4 = generic_bs_w_4, .bs_w_8 = NULL, /* write multiple */ .bs_wm_1 = generic_bs_wm_1, - .bs_wm_2 = generic_armv4_bs_wm_2, + .bs_wm_2 = generic_bs_wm_2, .bs_wm_4 = generic_bs_wm_4, .bs_wm_8 = NULL, /* write region */ .bs_wr_1 = generic_bs_wr_1, - .bs_wr_2 = generic_armv4_bs_wr_2, + .bs_wr_2 = generic_bs_wr_2, .bs_wr_4 = generic_bs_wr_4, .bs_wr_8 = NULL, /* set multiple */ /* XXX not implemented */ /* set region */ .bs_sr_1 = NULL, - .bs_sr_2 = generic_armv4_bs_sr_2, + .bs_sr_2 = generic_bs_sr_2, .bs_sr_4 = generic_bs_sr_4, .bs_sr_8 = NULL, /* copy */ .bs_c_1 = NULL, - .bs_c_2 = generic_armv4_bs_c_2, + .bs_c_2 = generic_bs_c_2, .bs_c_4 = NULL, .bs_c_8 = NULL, }; Index: stable/10/sys/arm/xscale/pxa/pxa_space.c =================================================================== --- stable/10/sys/arm/xscale/pxa/pxa_space.c (revision 278726) +++ stable/10/sys/arm/xscale/pxa/pxa_space.c (revision 278727) @@ -1,233 +1,268 @@ /* $NetBSD: obio_space.c,v 1.6 2003/07/15 00:25:05 lukem Exp $ */ /*- * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * bus_space functions for PXA devices */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include static MALLOC_DEFINE(M_PXATAG, "PXA bus_space tags", "Bus_space tags for PXA"); /* Prototypes for all the bus_space structure functions */ bs_protos(generic); -bs_protos(generic_armv4); bs_protos(pxa); /* * The obio bus space tag. This is constant for all instances, so * we never have to explicitly "create" it. */ struct bus_space _base_tag = { /* cookie */ - (void *) 0, + .bs_privdata = NULL, /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, + .bs_map = generic_bs_map, + .bs_unmap = generic_bs_unmap, + .bs_subregion = generic_bs_subregion, /* allocation/deallocation */ - generic_bs_alloc, - generic_bs_free, + .bs_alloc = generic_bs_alloc, + .bs_free = generic_bs_free, /* barrier */ - generic_bs_barrier, + .bs_barrier = generic_bs_barrier, /* read (single) */ - pxa_bs_r_1, - pxa_bs_r_2, - pxa_bs_r_4, - NULL, + .bs_r_1 = pxa_bs_r_1, + .bs_r_2 = pxa_bs_r_2, + .bs_r_4 = pxa_bs_r_4, + .bs_r_8 = BS_UNIMPLEMENTED, /* read multiple */ - pxa_bs_rm_1, - pxa_bs_rm_2, - NULL, - NULL, + .bs_rm_1 = pxa_bs_rm_1, + .bs_rm_2 = pxa_bs_rm_2, + .bs_rm_4 = BS_UNIMPLEMENTED, + .bs_rm_8 = BS_UNIMPLEMENTED, /* read region */ - pxa_bs_rr_1, - NULL, - NULL, - NULL, + .bs_rr_1 = pxa_bs_rr_1, + .bs_rr_2 = BS_UNIMPLEMENTED, + .bs_rr_4 = BS_UNIMPLEMENTED, + .bs_rr_8 = BS_UNIMPLEMENTED, /* write (single) */ - pxa_bs_w_1, - pxa_bs_w_2, - pxa_bs_w_4, - NULL, + .bs_w_1 = pxa_bs_w_1, + .bs_w_2 = pxa_bs_w_2, + .bs_w_4 = pxa_bs_w_4, + .bs_w_8 = BS_UNIMPLEMENTED, /* write multiple */ - pxa_bs_wm_1, - pxa_bs_wm_2, - NULL, - NULL, + .bs_wm_1 = pxa_bs_wm_1, + .bs_wm_2 = pxa_bs_wm_2, + .bs_wm_4 = BS_UNIMPLEMENTED, + .bs_wm_8 = BS_UNIMPLEMENTED, /* write region */ - NULL, - NULL, - NULL, - NULL, + .bs_wr_1 = BS_UNIMPLEMENTED, + .bs_wr_2 = BS_UNIMPLEMENTED, + .bs_wr_4 = BS_UNIMPLEMENTED, + .bs_wr_8 = BS_UNIMPLEMENTED, /* set multiple */ - NULL, - NULL, - NULL, - NULL, + .bs_sm_1 = BS_UNIMPLEMENTED, + .bs_sm_2 = BS_UNIMPLEMENTED, + .bs_sm_4 = BS_UNIMPLEMENTED, + .bs_sm_8 = BS_UNIMPLEMENTED, /* set region */ - NULL, - NULL, - NULL, - NULL, + .bs_sr_1 = BS_UNIMPLEMENTED, + .bs_sr_2 = BS_UNIMPLEMENTED, + .bs_sr_4 = BS_UNIMPLEMENTED, + .bs_sr_8 = BS_UNIMPLEMENTED, /* copy */ - NULL, - NULL, - NULL, - NULL, + .bs_c_1 = BS_UNIMPLEMENTED, + .bs_c_2 = BS_UNIMPLEMENTED, + .bs_c_4 = BS_UNIMPLEMENTED, + .bs_c_8 = BS_UNIMPLEMENTED, + + /* read stream (single) */ + .bs_r_1_s = BS_UNIMPLEMENTED, + .bs_r_2_s = BS_UNIMPLEMENTED, + .bs_r_4_s = BS_UNIMPLEMENTED, + .bs_r_8_s = BS_UNIMPLEMENTED, + + /* read multiple stream */ + .bs_rm_1_s = BS_UNIMPLEMENTED, + .bs_rm_2_s = BS_UNIMPLEMENTED, + .bs_rm_4_s = BS_UNIMPLEMENTED, + .bs_rm_8_s = BS_UNIMPLEMENTED, + + /* read region stream */ + .bs_rr_1_s = BS_UNIMPLEMENTED, + .bs_rr_2_s = BS_UNIMPLEMENTED, + .bs_rr_4_s = BS_UNIMPLEMENTED, + .bs_rr_8_s = BS_UNIMPLEMENTED, + + /* write stream (single) */ + .bs_w_1_s = BS_UNIMPLEMENTED, + .bs_w_2_s = BS_UNIMPLEMENTED, + .bs_w_4_s = BS_UNIMPLEMENTED, + .bs_w_8_s = BS_UNIMPLEMENTED, + + /* write multiple stream */ + .bs_wm_1_s = BS_UNIMPLEMENTED, + .bs_wm_2_s = BS_UNIMPLEMENTED, + .bs_wm_4_s = BS_UNIMPLEMENTED, + .bs_wm_8_s = BS_UNIMPLEMENTED, + + /* write region stream */ + .bs_wr_1_s = BS_UNIMPLEMENTED, + .bs_wr_2_s = BS_UNIMPLEMENTED, + .bs_wr_4_s = BS_UNIMPLEMENTED, + .bs_wr_8_s = BS_UNIMPLEMENTED, }; static struct bus_space _obio_tag; bus_space_tag_t base_tag = &_base_tag; bus_space_tag_t obio_tag = NULL; void pxa_obio_tag_init() { bcopy(&_base_tag, &_obio_tag, sizeof(struct bus_space)); - _obio_tag.bs_cookie = (void *)PXA2X0_PERIPH_OFFSET; + _obio_tag.bs_privdata = (void *)PXA2X0_PERIPH_OFFSET; obio_tag = &_obio_tag; } bus_space_tag_t pxa_bus_tag_alloc(bus_addr_t offset) { struct bus_space *tag; tag = (struct bus_space *)malloc(sizeof(struct bus_space), M_PXATAG, M_WAITOK); if (tag == NULL) { return (NULL); } bcopy(&_base_tag, tag, sizeof(struct bus_space)); - tag->bs_cookie = (void *)offset; + tag->bs_privdata = (void *)offset; return ((bus_space_tag_t)tag); } #define READ_SINGLE(type, proto, base) \ type \ - proto(void *cookie, bus_space_handle_t bsh, bus_size_t offset) \ + proto(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset) \ { \ bus_addr_t tag_offset; \ type value; \ - tag_offset = (bus_addr_t)cookie; \ + tag_offset = (bus_addr_t)tag->bs_privdata; \ value = base(NULL, bsh + tag_offset, offset); \ return (value); \ } READ_SINGLE(u_int8_t, pxa_bs_r_1, generic_bs_r_1) -READ_SINGLE(u_int16_t, pxa_bs_r_2, generic_armv4_bs_r_2) +READ_SINGLE(u_int16_t, pxa_bs_r_2, generic_bs_r_2) READ_SINGLE(u_int32_t, pxa_bs_r_4, generic_bs_r_4) #undef READ_SINGLE #define WRITE_SINGLE(type, proto, base) \ void \ - proto(void *cookie, bus_space_handle_t bsh, bus_size_t offset, \ + proto(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, \ type value) \ { \ bus_addr_t tag_offset; \ - tag_offset = (bus_addr_t)cookie; \ + tag_offset = (bus_addr_t)tag->bs_privdata; \ base(NULL, bsh + tag_offset, offset, value); \ } WRITE_SINGLE(u_int8_t, pxa_bs_w_1, generic_bs_w_1) -WRITE_SINGLE(u_int16_t, pxa_bs_w_2, generic_armv4_bs_w_2) +WRITE_SINGLE(u_int16_t, pxa_bs_w_2, generic_bs_w_2) WRITE_SINGLE(u_int32_t, pxa_bs_w_4, generic_bs_w_4) #undef WRITE_SINGLE #define READ_MULTI(type, proto, base) \ void \ - proto(void *cookie, bus_space_handle_t bsh, bus_size_t offset, \ + proto(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, \ type *dest, bus_size_t count) \ { \ bus_addr_t tag_offset; \ - tag_offset = (bus_addr_t)cookie; \ + tag_offset = (bus_addr_t)tag->bs_privdata; \ base(NULL, bsh + tag_offset, offset, dest, count); \ } READ_MULTI(u_int8_t, pxa_bs_rm_1, generic_bs_rm_1) -READ_MULTI(u_int16_t, pxa_bs_rm_2, generic_armv4_bs_rm_2) +READ_MULTI(u_int16_t, pxa_bs_rm_2, generic_bs_rm_2) READ_MULTI(u_int8_t, pxa_bs_rr_1, generic_bs_rr_1) #undef READ_MULTI #define WRITE_MULTI(type, proto, base) \ void \ - proto(void *cookie, bus_space_handle_t bsh, bus_size_t offset, \ + proto(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, \ const type *src, bus_size_t count) \ { \ bus_addr_t tag_offset; \ - tag_offset = (bus_addr_t)cookie; \ + tag_offset = (bus_addr_t)tag->bs_privdata; \ base(NULL, bsh + tag_offset, offset, src, count); \ } WRITE_MULTI(u_int8_t, pxa_bs_wm_1, generic_bs_wm_1) -WRITE_MULTI(u_int16_t, pxa_bs_wm_2, generic_armv4_bs_wm_2) +WRITE_MULTI(u_int16_t, pxa_bs_wm_2, generic_bs_wm_2) #undef WRITE_MULTI Index: stable/10/sys/dev/usb/controller/ehci_ixp4xx.c =================================================================== --- stable/10/sys/dev/usb/controller/ehci_ixp4xx.c (revision 278726) +++ stable/10/sys/dev/usb/controller/ehci_ixp4xx.c (revision 278727) @@ -1,313 +1,313 @@ /*- * Copyright (c) 2008 Sam Leffler. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * IXP435 attachment driver for the USB Enhanced Host Controller. */ #include __FBSDID("$FreeBSD$"); #include "opt_bus.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define EHCI_VENDORID_IXP4XX 0x42fa05 #define EHCI_HC_DEVSTR "IXP4XX Integrated USB 2.0 controller" struct ixp_ehci_softc { ehci_softc_t base; /* storage for EHCI code */ bus_space_tag_t iot; bus_space_handle_t ioh; struct bus_space tag; /* tag for private bus space ops */ }; static device_attach_t ehci_ixp_attach; static device_detach_t ehci_ixp_detach; -static uint8_t ehci_bs_r_1(void *, bus_space_handle_t, bus_size_t); -static void ehci_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t); -static uint16_t ehci_bs_r_2(void *, bus_space_handle_t, bus_size_t); -static void ehci_bs_w_2(void *, bus_space_handle_t, bus_size_t, uint16_t); -static uint32_t ehci_bs_r_4(void *, bus_space_handle_t, bus_size_t); -static void ehci_bs_w_4(void *, bus_space_handle_t, bus_size_t, uint32_t); +static uint8_t ehci_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static void ehci_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t); +static uint16_t ehci_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static void ehci_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, uint16_t); +static uint32_t ehci_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); +static void ehci_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, uint32_t); static int ehci_ixp_probe(device_t self) { device_set_desc(self, EHCI_HC_DEVSTR); return (BUS_PROBE_DEFAULT); } static int ehci_ixp_attach(device_t self) { struct ixp_ehci_softc *isc = device_get_softc(self); ehci_softc_t *sc = &isc->base; int err; int rid; /* initialise some bus fields */ sc->sc_bus.parent = self; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; sc->sc_bus.dma_bits = 32; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) { return (ENOMEM); } /* NB: hints fix the memory location and irq */ rid = 0; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); goto error; } /* * Craft special resource for bus space ops that handle * byte-alignment of non-word addresses. Also, since * we're already intercepting bus space ops we handle * the register window offset that could otherwise be * done with bus_space_subregion. */ isc->iot = rman_get_bustag(sc->sc_io_res); - isc->tag.bs_cookie = isc->iot; + isc->tag.bs_privdata = isc->iot; /* read single */ isc->tag.bs_r_1 = ehci_bs_r_1, isc->tag.bs_r_2 = ehci_bs_r_2, isc->tag.bs_r_4 = ehci_bs_r_4, /* write (single) */ isc->tag.bs_w_1 = ehci_bs_w_1, isc->tag.bs_w_2 = ehci_bs_w_2, isc->tag.bs_w_4 = ehci_bs_w_4, sc->sc_io_tag = &isc->tag; sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = IXP435_USB1_SIZE - 0x100; rid = 0; sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(self, "Could not allocate irq\n"); goto error; } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (!sc->sc_bus.bdev) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR); sprintf(sc->sc_vendor, "Intel"); err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(self, "Could not setup irq, %d\n", err); sc->sc_intr_hdl = NULL; goto error; } /* * Arrange to force Host mode, select big-endian byte alignment, * and arrange to not terminate reset operations (the adapter * will ignore it if we do but might as well save a reg write). * Also, the controller has an embedded Transaction Translator * which means port speed must be read from the Port Status * register following a port enable. */ sc->sc_flags |= EHCI_SCFLG_TT | EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEDESC | EHCI_SCFLG_BIGEMMIO | EHCI_SCFLG_NORESTERM ; err = ehci_init(sc); if (!err) { err = device_probe_and_attach(sc->sc_bus.bdev); } if (err) { device_printf(self, "USB init failed err=%d\n", err); goto error; } return (0); error: ehci_ixp_detach(self); return (ENXIO); } static int ehci_ixp_detach(device_t self) { struct ixp_ehci_softc *isc = device_get_softc(self); ehci_softc_t *sc = &isc->base; device_t bdev; int err; if (sc->sc_bus.bdev) { bdev = sc->sc_bus.bdev; device_detach(bdev); device_delete_child(self, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { /* * only call ehci_detach() after ehci_init() */ ehci_detach(sc); err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); if (err) /* XXX or should we panic? */ device_printf(self, "Could not tear down irq, %d\n", err); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, 0, sc->sc_io_res); sc->sc_io_res = NULL; } usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc); return (0); } /* * Bus space accessors for PIO operations. */ static uint8_t -ehci_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o) +ehci_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) { - return bus_space_read_1((bus_space_tag_t) t, h, + return bus_space_read_1((bus_space_tag_t)tag->bs_privdata, h, 0x100 + (o &~ 3) + (3 - (o & 3))); } static void -ehci_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v) +ehci_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v) { panic("%s", __func__); } static uint16_t -ehci_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o) +ehci_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) { - return bus_space_read_2((bus_space_tag_t) t, h, + return bus_space_read_2((bus_space_tag_t)tag->bs_privdata, h, 0x100 + (o &~ 3) + (2 - (o & 3))); } static void -ehci_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v) +ehci_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v) { panic("%s", __func__); } static uint32_t -ehci_bs_r_4(void *t, bus_space_handle_t h, bus_size_t o) +ehci_bs_r_4(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) { - return bus_space_read_4((bus_space_tag_t) t, h, 0x100 + o); + return bus_space_read_4((bus_space_tag_t) tag->bs_privdata, h, 0x100 + o); } static void -ehci_bs_w_4(void *t, bus_space_handle_t h, bus_size_t o, uint32_t v) +ehci_bs_w_4(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint32_t v) { - bus_space_write_4((bus_space_tag_t) t, h, 0x100 + o, v); + bus_space_write_4((bus_space_tag_t) tag->bs_privdata, h, 0x100 + o, v); } static device_method_t ehci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ehci_ixp_probe), DEVMETHOD(device_attach, ehci_ixp_attach), DEVMETHOD(device_detach, ehci_ixp_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD_END }; static driver_t ehci_driver = { "ehci", ehci_methods, sizeof(struct ixp_ehci_softc), }; static devclass_t ehci_devclass; DRIVER_MODULE(ehci, ixp, ehci_driver, ehci_devclass, 0, 0); MODULE_DEPEND(ehci, usb, 1, 1, 1); Index: stable/10 =================================================================== --- stable/10 (revision 278726) +++ stable/10 (revision 278727) Property changes on: stable/10 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r277454,277460,277465-277467,277469-277480,277512,277516