Index: projects/pmac_pmu/sys/powerpc/powermac/macio.c =================================================================== --- projects/pmac_pmu/sys/powerpc/powermac/macio.c (revision 278123) +++ projects/pmac_pmu/sys/powerpc/powermac/macio.c (revision 278124) @@ -1,896 +1,964 @@ /*- * Copyright 2002 by Peter Grehan. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Driver for KeyLargo/Pangea, the MacPPC south bridge ASIC. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* * Macio softc */ struct macio_softc { phandle_t sc_node; vm_offset_t sc_base; vm_offset_t sc_size; struct rman sc_mem_rman; /* FCR registers */ int sc_memrid; struct resource *sc_memr; int sc_rev; int sc_devid; - uint32_t saved_fcrs[11]; - uint32_t saved_mbcr; + uint32_t sc_saved_fcrs[11]; + uint32_t sc_saved_mbcr; }; static MALLOC_DEFINE(M_MACIO, "macio", "macio device information"); static int macio_probe(device_t); static int macio_attach(device_t); static int macio_suspend(device_t); static int macio_resume(device_t); static int macio_print_child(device_t dev, device_t child); static void macio_probe_nomatch(device_t, device_t); static struct resource *macio_alloc_resource(device_t, device_t, int, int *, u_long, u_long, u_long, u_int); static int macio_activate_resource(device_t, device_t, int, int, struct resource *); static int macio_deactivate_resource(device_t, device_t, int, int, struct resource *); static int macio_release_resource(device_t, device_t, int, int, struct resource *); static struct resource_list *macio_get_resource_list (device_t, device_t); static ofw_bus_get_devinfo_t macio_get_devinfo; /* * Bus interface definition */ static device_method_t macio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, macio_probe), DEVMETHOD(device_attach, macio_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, macio_suspend), DEVMETHOD(device_resume, macio_resume), /* Bus interface */ DEVMETHOD(bus_print_child, macio_print_child), DEVMETHOD(bus_probe_nomatch, macio_probe_nomatch), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_alloc_resource, macio_alloc_resource), DEVMETHOD(bus_release_resource, macio_release_resource), DEVMETHOD(bus_activate_resource, macio_activate_resource), DEVMETHOD(bus_deactivate_resource, macio_deactivate_resource), DEVMETHOD(bus_get_resource_list, macio_get_resource_list), DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_devinfo, macio_get_devinfo), DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), { 0, 0 } }; static driver_t macio_pci_driver = { "macio", macio_methods, sizeof(struct macio_softc) }; devclass_t macio_devclass; EARLY_DRIVER_MODULE(macio, pci, macio_pci_driver, macio_devclass, 0, 0, BUS_PASS_BUS); /* * PCI ID search table */ static struct macio_pci_dev { u_int32_t mpd_devid; char *mpd_desc; } macio_pci_devlist[] = { { 0x0017106b, "Paddington I/O Controller" }, { 0x0022106b, "KeyLargo I/O Controller" }, { 0x0025106b, "Pangea I/O Controller" }, { 0x003e106b, "Intrepid I/O Controller" }, { 0x0041106b, "K2 KeyLargo I/O Controller" }, { 0x004f106b, "Shasta I/O Controller" }, { 0, NULL } }; /* * Devices to exclude from the probe * XXX some of these may be required in the future... */ #define MACIO_QUIRK_IGNORE 0x00000001 #define MACIO_QUIRK_CHILD_HAS_INTR 0x00000002 #define MACIO_QUIRK_USE_CHILD_REG 0x00000004 struct macio_quirk_entry { const char *mq_name; int mq_quirks; }; static struct macio_quirk_entry macio_quirks[] = { { "escc-legacy", MACIO_QUIRK_IGNORE }, { "timer", MACIO_QUIRK_IGNORE }, { "escc", MACIO_QUIRK_CHILD_HAS_INTR }, { "i2s", MACIO_QUIRK_CHILD_HAS_INTR | MACIO_QUIRK_USE_CHILD_REG }, { NULL, 0 } }; static int macio_get_quirks(const char *name) { struct macio_quirk_entry *mqe; for (mqe = macio_quirks; mqe->mq_name != NULL; mqe++) if (strcmp(name, mqe->mq_name) == 0) return (mqe->mq_quirks); return (0); } /* * Add an interrupt to the dev's resource list if present */ static void macio_add_intr(phandle_t devnode, struct macio_devinfo *dinfo) { phandle_t iparent; int *intr; int i, nintr; int icells; if (dinfo->mdi_ninterrupts >= 6) { printf("macio: device has more than 6 interrupts\n"); return; } nintr = OF_getprop_alloc(devnode, "interrupts", sizeof(*intr), (void **)&intr); if (nintr == -1) { nintr = OF_getprop_alloc(devnode, "AAPL,interrupts", sizeof(*intr), (void **)&intr); if (nintr == -1) return; } if (intr[0] == -1) return; if (OF_getprop(devnode, "interrupt-parent", &iparent, sizeof(iparent)) <= 0) panic("Interrupt but no interrupt parent!\n"); if (OF_getprop(OF_node_from_xref(iparent), "#interrupt-cells", &icells, sizeof(icells)) <= 0) icells = 1; for (i = 0; i < nintr; i+=icells) { u_int irq = MAP_IRQ(iparent, intr[i]); resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ, dinfo->mdi_ninterrupts, irq, irq, 1); dinfo->mdi_interrupts[dinfo->mdi_ninterrupts] = irq; dinfo->mdi_ninterrupts++; } } static void macio_add_reg(phandle_t devnode, struct macio_devinfo *dinfo) { struct macio_reg *reg, *regp; phandle_t child; char buf[8]; int i, layout_id = 0, nreg, res; nreg = OF_getprop_alloc(devnode, "reg", sizeof(*reg), (void **)®); if (nreg == -1) return; /* * Some G5's have broken properties in the i2s-a area. If so we try * to fix it. Right now we know of two different cases, one for * sound layout-id 36 and the other one for sound layout-id 76. * What is missing is the base address for the memory addresses. * We take them from the parent node (i2s) and use the size * information from the child. */ if (reg[0].mr_base == 0) { child = OF_child(devnode); while (child != 0) { res = OF_getprop(child, "name", buf, sizeof(buf)); if (res > 0 && strcmp(buf, "sound") == 0) break; child = OF_peer(child); } res = OF_getprop(child, "layout-id", &layout_id, sizeof(layout_id)); if (res > 0 && (layout_id == 36 || layout_id == 76)) { res = OF_getprop_alloc(OF_parent(devnode), "reg", sizeof(*regp), (void **)®p); reg[0] = regp[0]; reg[1].mr_base = regp[1].mr_base; reg[2].mr_base = regp[1].mr_base + reg[1].mr_size; } } for (i = 0; i < nreg; i++) { resource_list_add(&dinfo->mdi_resources, SYS_RES_MEMORY, i, reg[i].mr_base, reg[i].mr_base + reg[i].mr_size, reg[i].mr_size); } } /* * PCI probe */ static int macio_probe(device_t dev) { int i; u_int32_t devid; devid = pci_get_devid(dev); for (i = 0; macio_pci_devlist[i].mpd_desc != NULL; i++) { if (devid == macio_pci_devlist[i].mpd_devid) { device_set_desc(dev, macio_pci_devlist[i].mpd_desc); return (0); } } return (ENXIO); } /* * PCI attach: scan Open Firmware child nodes, and attach these as children * of the macio bus */ static int macio_attach(device_t dev) { struct macio_softc *sc; struct macio_devinfo *dinfo; phandle_t root; phandle_t child; phandle_t subchild; device_t cdev; u_int reg[3]; char compat[32]; int error, quirks; sc = device_get_softc(dev); root = sc->sc_node = ofw_bus_get_node(dev); /* * Locate the device node and it's base address */ if (OF_getprop(root, "assigned-addresses", reg, sizeof(reg)) < (ssize_t)sizeof(reg)) { return (ENXIO); } /* Used later to see if we have to enable the I2S part. */ OF_getprop(root, "compatible", compat, sizeof(compat)); sc->sc_base = reg[2]; sc->sc_size = MACIO_REG_SIZE; sc->sc_memrid = PCIR_BAR(0); sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_memrid, RF_ACTIVE); sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "MacIO Device Memory"; error = rman_init(&sc->sc_mem_rman); if (error) { device_printf(dev, "rman_init() failed. error = %d\n", error); return (error); } error = rman_manage_region(&sc->sc_mem_rman, 0, sc->sc_size); if (error) { device_printf(dev, "rman_manage_region() failed. error = %d\n", error); return (error); } /* * If possible, get the device ID and revision ID. */ OF_getprop(root, "revision-id", &sc->sc_rev, sizeof(sc->sc_rev)); OF_getprop(root, "device-id", &sc->sc_devid, sizeof(sc->sc_devid)); /* * Iterate through the sub-devices */ for (child = OF_child(root); child != 0; child = OF_peer(child)) { dinfo = malloc(sizeof(*dinfo), M_MACIO, M_WAITOK | M_ZERO); if (ofw_bus_gen_setup_devinfo(&dinfo->mdi_obdinfo, child) != 0) { free(dinfo, M_MACIO); continue; } quirks = macio_get_quirks(dinfo->mdi_obdinfo.obd_name); if ((quirks & MACIO_QUIRK_IGNORE) != 0) { ofw_bus_gen_destroy_devinfo(&dinfo->mdi_obdinfo); free(dinfo, M_MACIO); continue; } resource_list_init(&dinfo->mdi_resources); dinfo->mdi_ninterrupts = 0; macio_add_intr(child, dinfo); if ((quirks & MACIO_QUIRK_USE_CHILD_REG) != 0) macio_add_reg(OF_child(child), dinfo); else macio_add_reg(child, dinfo); if ((quirks & MACIO_QUIRK_CHILD_HAS_INTR) != 0) for (subchild = OF_child(child); subchild != 0; subchild = OF_peer(subchild)) macio_add_intr(subchild, dinfo); cdev = device_add_child(dev, NULL, -1); if (cdev == NULL) { device_printf(dev, "<%s>: device_add_child failed\n", dinfo->mdi_obdinfo.obd_name); resource_list_free(&dinfo->mdi_resources); ofw_bus_gen_destroy_devinfo(&dinfo->mdi_obdinfo); free(dinfo, M_MACIO); continue; } if (OF_getprop(child, "AAPL,bus-id", &dinfo->mdi_aapl_busid, sizeof(dinfo->mdi_aapl_busid)) == -1) dinfo->mdi_aapl_busid = -1; device_set_ivars(cdev, dinfo); /* Set FCRs to enable some devices */ if (sc->sc_memr == NULL) continue; if (strcmp(ofw_bus_get_name(cdev), "bmac") == 0 || strcmp(ofw_bus_get_compat(cdev), "bmac+") == 0) { uint32_t fcr; fcr = bus_read_4(sc->sc_memr, HEATHROW_FCR); fcr |= FCR_ENET_ENABLE & ~FCR_ENET_RESET; bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr); DELAY(50000); fcr |= FCR_ENET_RESET; bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr); DELAY(50000); fcr &= ~FCR_ENET_RESET; bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr); DELAY(50000); bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr); } /* * Make sure the I2S0 and the I2S0_CLK are enabled. * On certain G5's they are not. */ if ((strcmp(ofw_bus_get_name(cdev), "i2s") == 0) && (strcmp(compat, "K2-Keylargo") == 0)) { uint32_t fcr1; fcr1 = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); fcr1 |= FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE; bus_write_4(sc->sc_memr, KEYLARGO_FCR1, fcr1); } } return (bus_generic_attach(dev)); } static int macio_print_child(device_t dev, device_t child) { struct macio_devinfo *dinfo; struct resource_list *rl; int retval = 0; dinfo = device_get_ivars(child); rl = &dinfo->mdi_resources; retval += bus_print_child_header(dev, child); retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); retval += bus_print_child_footer(dev, child); return (retval); } static void macio_probe_nomatch(device_t dev, device_t child) { struct macio_devinfo *dinfo; struct resource_list *rl; const char *type; if (bootverbose) { dinfo = device_get_ivars(child); rl = &dinfo->mdi_resources; if ((type = ofw_bus_get_type(child)) == NULL) type = "(unknown)"; device_printf(dev, "<%s, %s>", type, ofw_bus_get_name(child)); resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); printf(" (no driver attached)\n"); } } static struct resource * macio_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct macio_softc *sc; int needactivate; struct resource *rv; struct rman *rm; u_long adjstart, adjend, adjcount; struct macio_devinfo *dinfo; struct resource_list_entry *rle; sc = device_get_softc(bus); dinfo = device_get_ivars(child); needactivate = flags & RF_ACTIVE; flags &= ~RF_ACTIVE; switch (type) { case SYS_RES_MEMORY: case SYS_RES_IOPORT: rle = resource_list_find(&dinfo->mdi_resources, SYS_RES_MEMORY, *rid); if (rle == NULL) { device_printf(bus, "no rle for %s memory %d\n", device_get_nameunit(child), *rid); return (NULL); } if (start < rle->start) adjstart = rle->start; else if (start > rle->end) adjstart = rle->end; else adjstart = start; if (end < rle->start) adjend = rle->start; else if (end > rle->end) adjend = rle->end; else adjend = end; adjcount = adjend - adjstart; rm = &sc->sc_mem_rman; break; case SYS_RES_IRQ: /* Check for passthrough from subattachments like macgpio */ if (device_get_parent(child) != bus) return BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, rid, start, end, count, flags); rle = resource_list_find(&dinfo->mdi_resources, SYS_RES_IRQ, *rid); if (rle == NULL) { if (dinfo->mdi_ninterrupts >= 6) { device_printf(bus, "%s has more than 6 interrupts\n", device_get_nameunit(child)); return (NULL); } resource_list_add(&dinfo->mdi_resources, SYS_RES_IRQ, dinfo->mdi_ninterrupts, start, start, 1); dinfo->mdi_interrupts[dinfo->mdi_ninterrupts] = start; dinfo->mdi_ninterrupts++; } return (resource_list_alloc(&dinfo->mdi_resources, bus, child, type, rid, start, end, count, flags)); default: device_printf(bus, "unknown resource request from %s\n", device_get_nameunit(child)); return (NULL); } rv = rman_reserve_resource(rm, adjstart, adjend, adjcount, flags, child); if (rv == NULL) { device_printf(bus, "failed to reserve resource %#lx - %#lx (%#lx) for %s\n", adjstart, adjend, adjcount, device_get_nameunit(child)); return (NULL); } rman_set_rid(rv, *rid); if (needactivate) { if (bus_activate_resource(child, type, *rid, rv) != 0) { device_printf(bus, "failed to activate resource for %s\n", device_get_nameunit(child)); rman_release_resource(rv); return (NULL); } } return (rv); } static int macio_release_resource(device_t bus, device_t child, int type, int rid, struct resource *res) { if (rman_get_flags(res) & RF_ACTIVE) { int error = bus_deactivate_resource(child, type, rid, res); if (error) return error; } return (rman_release_resource(res)); } static int macio_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *res) { struct macio_softc *sc; void *p; sc = device_get_softc(bus); if (type == SYS_RES_IRQ) return (bus_activate_resource(bus, type, rid, res)); if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) { p = pmap_mapdev((vm_offset_t)rman_get_start(res) + sc->sc_base, (vm_size_t)rman_get_size(res)); if (p == NULL) return (ENOMEM); rman_set_virtual(res, p); rman_set_bustag(res, &bs_le_tag); rman_set_bushandle(res, (u_long)p); } return (rman_activate_resource(res)); } static int macio_deactivate_resource(device_t bus, device_t child, int type, int rid, struct resource *res) { /* * If this is a memory resource, unmap it. */ if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) { u_int32_t psize; psize = rman_get_size(res); pmap_unmapdev((vm_offset_t)rman_get_virtual(res), psize); } return (rman_deactivate_resource(res)); } static struct resource_list * macio_get_resource_list (device_t dev, device_t child) { struct macio_devinfo *dinfo; dinfo = device_get_ivars(child); return (&dinfo->mdi_resources); } static const struct ofw_bus_devinfo * macio_get_devinfo(device_t dev, device_t child) { struct macio_devinfo *dinfo; dinfo = device_get_ivars(child); return (&dinfo->mdi_obdinfo); } int macio_enable_wireless(device_t dev, bool enable) { struct macio_softc *sc = device_get_softc(dev); uint32_t x; if (enable) { x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); x |= 0x4; bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x); /* Enable card slot. */ bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0f, 5); DELAY(1000); bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0f, 4); DELAY(1000); x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); x &= ~0x80000000; bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x); /* out8(gpio + 0x10, 4); */ bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0b, 0); bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0a, 0x28); bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0d, 0x28); bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0d, 0x28); bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0e, 0x28); bus_write_4(sc->sc_memr, 0x1c000, 0); /* Initialize the card. */ bus_write_4(sc->sc_memr, 0x1a3e0, 0x41); x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); x |= 0x80000000; bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x); } else { x = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); x &= ~0x4; bus_write_4(sc->sc_memr, KEYLARGO_FCR2, x); /* out8(gpio + 0x10, 0); */ } return (0); } -int macio_reset_ata(device_t atadev) +int +macio_reset_ata(device_t atadev) { device_t dev; struct macio_softc *sc; struct macio_devinfo *dinfo; uint32_t resetm,enablem,temp; dev = device_get_parent(atadev); sc = device_get_softc(dev); dinfo = device_get_ivars(atadev); KASSERT(dinfo->mdi_aapl_busid != -1, ("macio_reset_ata called on non-mac-io ATA device")); switch (dinfo->mdi_aapl_busid) { case 0: resetm = FCR1_EIDE0_RESET; enablem = FCR1_EIDE0_ENABLE; break; case 1: resetm = FCR1_EIDE1_RESET; enablem = FCR1_EIDE1_ENABLE; break; case 2: resetm = FCR1_UIDE_RESET; enablem = FCR1_UIDE_ENABLE; break; default: return (1); } temp = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); bus_write_4(sc->sc_memr, KEYLARGO_FCR1, temp & ~resetm); temp = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); bus_write_4(sc->sc_memr, KEYLARGO_FCR1, temp | enablem); temp = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); bus_write_4(sc->sc_memr, KEYLARGO_FCR1, temp | resetm); return (0); } -static int macio_suspend(device_t dev) +static int +macio_suspend_keylargo(device_t dev) { struct macio_softc *sc = device_get_softc(dev); uint32_t temp; - uint32_t fcr_bits[3][2]; - powerpc_sync(); - + temp = sc->sc_saved_fcrs[0]; if (sc->sc_devid == 0x22) { - fcr_bits[0][0] = KEYLARGO_FCR0_SLEEP_SET; - fcr_bits[0][1] = KEYLARGO_FCR0_SLEEP_CLR; - fcr_bits[1][0] = KEYLARGO_FCR1_SLEEP_SET; - fcr_bits[1][1] = KEYLARGO_FCR1_SLEEP_CLR; - fcr_bits[2][0] = KEYLARGO_FCR2_SLEEP_SET; - fcr_bits[2][0] = KEYLARGO_FCR2_SLEEP_SET; - fcr_bits[3][1] = KEYLARGO_FCR3_SLEEP_CLR; - fcr_bits[3][1] = KEYLARGO_FCR3_SLEEP_CLR; - } else if (sc->sc_devid == 0x25) { - fcr_bits[0][0] = PANGEA_FCR0_SLEEP_SET; - fcr_bits[0][1] = PANGEA_FCR0_SLEEP_CLR; - fcr_bits[1][0] = PANGEA_FCR1_SLEEP_SET; - fcr_bits[1][1] = PANGEA_FCR1_SLEEP_CLR; - fcr_bits[2][0] = PANGEA_FCR2_SLEEP_SET; - fcr_bits[2][0] = PANGEA_FCR2_SLEEP_SET; - fcr_bits[3][1] = PANGEA_FCR3_SLEEP_CLR; - fcr_bits[3][1] = PANGEA_FCR3_SLEEP_CLR; - } else if (sc->sc_devid == 0x3e) { - fcr_bits[0][0] = INTREPID_FCR0_SLEEP_SET; - fcr_bits[0][1] = INTREPID_FCR0_SLEEP_CLR; - fcr_bits[1][0] = INTREPID_FCR1_SLEEP_SET; - fcr_bits[1][1] = INTREPID_FCR1_SLEEP_CLR; - fcr_bits[2][0] = INTREPID_FCR2_SLEEP_SET; - fcr_bits[2][0] = INTREPID_FCR2_SLEEP_SET; - fcr_bits[3][1] = INTREPID_FCR3_SLEEP_CLR; - fcr_bits[3][1] = INTREPID_FCR3_SLEEP_CLR; - } else if (sc->sc_devid == 0x4f) { - fcr_bits[0][0] = K2_FCR0_SLEEP_SET; - fcr_bits[0][1] = K2_FCR0_SLEEP_CLR; - fcr_bits[1][0] = K2_FCR1_SLEEP_SET; - fcr_bits[1][1] = K2_FCR1_SLEEP_CLR; - fcr_bits[2][0] = K2_FCR2_SLEEP_SET; - fcr_bits[2][0] = K2_FCR2_SLEEP_SET; - fcr_bits[3][1] = K2_FCR3_SLEEP_CLR; - fcr_bits[3][1] = K2_FCR3_SLEEP_CLR; - } - - sc->saved_fcrs[0] = bus_read_4(sc->sc_memr, KEYLARGO_FCR0); - sc->saved_fcrs[1] = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); - sc->saved_fcrs[2] = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); - sc->saved_fcrs[3] = bus_read_4(sc->sc_memr, KEYLARGO_FCR3); - sc->saved_fcrs[4] = bus_read_4(sc->sc_memr, KEYLARGO_FCR4); - sc->saved_fcrs[5] = bus_read_4(sc->sc_memr, KEYLARGO_FCR5); - - if (sc->sc_devid == 0x4f) { - sc->saved_fcrs[6] = bus_read_4(sc->sc_memr, K2_FCR6); - sc->saved_fcrs[7] = bus_read_4(sc->sc_memr, K2_FCR7); - sc->saved_fcrs[8] = bus_read_4(sc->sc_memr, K2_FCR8); - sc->saved_fcrs[9] = bus_read_4(sc->sc_memr, K2_FCR9); - sc->saved_fcrs[10] = bus_read_4(sc->sc_memr, K2_FCR10); - } - - temp = sc->saved_fcrs[0]; - if (sc->sc_devid == 0x22) { temp |= FCR0_USB_REF_SUSPEND; bus_write_4(sc->sc_memr, KEYLARGO_FCR0, temp); eieio(); powerpc_sync(); DELAY(1000); } - temp |= fcr_bits[0][0]; - temp &= ~fcr_bits[0][1]; + temp = sc->sc_saved_fcrs[0]; + temp |= KEYLARGO_FCR0_SLEEP_SET; + temp &= KEYLARGO_FCR0_SLEEP_CLR; bus_write_4(sc->sc_memr, KEYLARGO_FCR0, temp); eieio(); powerpc_sync(); if (sc->sc_devid == 0x22) { temp = bus_read_4(sc->sc_memr, KEYLARGO_MEDIABAY); - sc->saved_mbcr = temp; + sc->sc_saved_mbcr = temp; temp |= KEYLARGO_MB0_DEV_ENABLE; bus_write_4(sc->sc_memr, KEYLARGO_MEDIABAY, temp); eieio(); powerpc_sync(); } - temp = sc->saved_fcrs[1]; - temp |= fcr_bits[1][0]; - temp &= ~fcr_bits[1][1]; + temp = sc->sc_saved_fcrs[1]; + temp |= KEYLARGO_FCR1_SLEEP_SET; + temp &= KEYLARGO_FCR1_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR1, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[2]; + temp |= KEYLARGO_FCR2_SLEEP_SET; + temp &= KEYLARGO_FCR2_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR2, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[3]; + temp |= KEYLARGO_FCR3_SLEEP_SET; + temp &= KEYLARGO_FCR3_SLEEP_CLR; + if (sc->sc_rev >= 2) + temp |= (FCR3_SHUTDOWN_PLL_2X | FCR3_SHUTDOWN_PLL_TOTAL); + bus_write_4(sc->sc_memr, KEYLARGO_FCR3, temp); + eieio(); powerpc_sync(); + return (0); +} + +static int +macio_suspend_pangea(device_t dev) +{ + struct macio_softc *sc = device_get_softc(dev); + uint32_t temp; + + temp = sc->sc_saved_fcrs[0]; + temp |= PANGEA_FCR0_SLEEP_SET; + temp &= PANGEA_FCR0_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR0, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[1]; + temp |= PANGEA_FCR1_SLEEP_SET; + temp &= PANGEA_FCR1_SLEEP_CLR; bus_write_4(sc->sc_memr, KEYLARGO_FCR1, temp); eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[2]; + temp |= PANGEA_FCR2_SLEEP_SET; + temp &= PANGEA_FCR2_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR2, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[3]; + temp |= PANGEA_FCR3_SLEEP_SET; + temp &= PANGEA_FCR3_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR3, temp); + eieio(); powerpc_sync(); - temp = sc->saved_fcrs[2]; - temp |= fcr_bits[2][0]; - temp &= ~fcr_bits[2][1]; + return (0); +} + +static int +macio_suspend_intrepid(device_t dev) +{ + struct macio_softc *sc = device_get_softc(dev); + uint32_t temp; + + temp = sc->sc_saved_fcrs[0]; + temp |= INTREPID_FCR0_SLEEP_SET; + temp &= INTREPID_FCR0_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR0, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[1]; + temp |= INTREPID_FCR1_SLEEP_SET; + temp &= INTREPID_FCR1_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR1, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[2]; + temp |= INTREPID_FCR2_SLEEP_SET; + temp &= INTREPID_FCR2_SLEEP_CLR; bus_write_4(sc->sc_memr, KEYLARGO_FCR2, temp); eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[3]; + temp |= INTREPID_FCR3_SLEEP_SET; + temp &= INTREPID_FCR3_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR3, temp); + eieio(); powerpc_sync(); - temp = sc->saved_fcrs[3]; - temp |= fcr_bits[3][0]; - temp &= ~fcr_bits[3][1]; - if (sc->sc_rev >= 2) - temp |= (FCR3_SHUTDOWN_PLL_2X | FCR3_SHUTDOWN_PLL_TOTAL); + return (0); +} + +static int +macio_suspend_k2(device_t dev) +{ + struct macio_softc *sc = device_get_softc(dev); + uint32_t temp; + + temp = sc->sc_saved_fcrs[0]; + temp |= K2_FCR0_SLEEP_SET; + temp &= K2_FCR0_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR0, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[1]; + temp |= K2_FCR1_SLEEP_SET; + temp &= K2_FCR1_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR1, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[2]; + temp |= K2_FCR2_SLEEP_SET; + temp &= K2_FCR2_SLEEP_CLR; + bus_write_4(sc->sc_memr, KEYLARGO_FCR2, temp); + eieio(); powerpc_sync(); + temp = sc->sc_saved_fcrs[3]; + temp |= K2_FCR3_SLEEP_SET; + temp &= K2_FCR3_SLEEP_CLR; bus_write_4(sc->sc_memr, KEYLARGO_FCR3, temp); eieio(); powerpc_sync(); - powerpc_sync(); + return (0); } -static int macio_resume(device_t dev) +static int +macio_suspend(device_t dev) { struct macio_softc *sc = device_get_softc(dev); + sc->sc_saved_fcrs[0] = bus_read_4(sc->sc_memr, KEYLARGO_FCR0); + sc->sc_saved_fcrs[1] = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); + sc->sc_saved_fcrs[2] = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); + sc->sc_saved_fcrs[3] = bus_read_4(sc->sc_memr, KEYLARGO_FCR3); + sc->sc_saved_fcrs[4] = bus_read_4(sc->sc_memr, KEYLARGO_FCR4); + sc->sc_saved_fcrs[5] = bus_read_4(sc->sc_memr, KEYLARGO_FCR5); + + if (sc->sc_devid == 0x4f) { + sc->sc_saved_fcrs[6] = bus_read_4(sc->sc_memr, K2_FCR6); + sc->sc_saved_fcrs[7] = bus_read_4(sc->sc_memr, K2_FCR7); + sc->sc_saved_fcrs[8] = bus_read_4(sc->sc_memr, K2_FCR8); + sc->sc_saved_fcrs[9] = bus_read_4(sc->sc_memr, K2_FCR9); + sc->sc_saved_fcrs[10] = bus_read_4(sc->sc_memr, K2_FCR10); + } + + if (sc->sc_devid == 0x22) { + return macio_suspend_keylargo(dev); + } else if (sc->sc_devid == 0x25) { + return macio_suspend_pangea(dev); + } else if (sc->sc_devid == 0x3e) { + return macio_suspend_intrepid(dev); + } else if (sc->sc_devid == 0x4f) { + return macio_suspend_k2(dev); + } + + return (0); +} + +static int +macio_resume(device_t dev) +{ + struct macio_softc *sc = device_get_softc(dev); + if (sc->sc_devid == 0x22) - bus_write_4(sc->sc_memr, KEYLARGO_MEDIABAY, sc->saved_mbcr); + bus_write_4(sc->sc_memr, KEYLARGO_MEDIABAY, sc->sc_saved_mbcr); - bus_write_4(sc->sc_memr, KEYLARGO_FCR0, sc->saved_fcrs[0]); - bus_write_4(sc->sc_memr, KEYLARGO_FCR1, sc->saved_fcrs[1]); - bus_write_4(sc->sc_memr, KEYLARGO_FCR2, sc->saved_fcrs[2]); - bus_write_4(sc->sc_memr, KEYLARGO_FCR3, sc->saved_fcrs[3]); - bus_write_4(sc->sc_memr, KEYLARGO_FCR4, sc->saved_fcrs[4]); - bus_write_4(sc->sc_memr, KEYLARGO_FCR5, sc->saved_fcrs[5]); + bus_write_4(sc->sc_memr, KEYLARGO_FCR0, sc->sc_saved_fcrs[0]); + bus_write_4(sc->sc_memr, KEYLARGO_FCR1, sc->sc_saved_fcrs[1]); + bus_write_4(sc->sc_memr, KEYLARGO_FCR2, sc->sc_saved_fcrs[2]); + bus_write_4(sc->sc_memr, KEYLARGO_FCR3, sc->sc_saved_fcrs[3]); + bus_write_4(sc->sc_memr, KEYLARGO_FCR4, sc->sc_saved_fcrs[4]); + bus_write_4(sc->sc_memr, KEYLARGO_FCR5, sc->sc_saved_fcrs[5]); if (sc->sc_devid == 0x4f) { - bus_write_4(sc->sc_memr, K2_FCR6, sc->saved_fcrs[6]); - bus_write_4(sc->sc_memr, K2_FCR7, sc->saved_fcrs[7]); - bus_write_4(sc->sc_memr, K2_FCR8, sc->saved_fcrs[8]); - bus_write_4(sc->sc_memr, K2_FCR9, sc->saved_fcrs[9]); - bus_write_4(sc->sc_memr, K2_FCR10, sc->saved_fcrs[10]); + bus_write_4(sc->sc_memr, K2_FCR6, sc->sc_saved_fcrs[6]); + bus_write_4(sc->sc_memr, K2_FCR7, sc->sc_saved_fcrs[7]); + bus_write_4(sc->sc_memr, K2_FCR8, sc->sc_saved_fcrs[8]); + bus_write_4(sc->sc_memr, K2_FCR9, sc->sc_saved_fcrs[9]); + bus_write_4(sc->sc_memr, K2_FCR10, sc->sc_saved_fcrs[10]); } /* Let things settle. */ DELAY(1000); return (0); } Index: projects/pmac_pmu/sys/powerpc/powermac/maciovar.h =================================================================== --- projects/pmac_pmu/sys/powerpc/powermac/maciovar.h (revision 278123) +++ projects/pmac_pmu/sys/powerpc/powermac/maciovar.h (revision 278124) @@ -1,392 +1,392 @@ /*- * Copyright 2002 by Peter Grehan. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACIO_MACIOVAR_H_ #define _MACIO_MACIOVAR_H_ /* * The addr space size * XXX it would be better if this could be determined by querying the * PCI device, but there isn't an access method for this */ #define MACIO_REG_SIZE 0x7ffff /* * Feature Control Registers (FCR) */ #define HEATHROW_FCR 0x38 #define KEYLARGO_FCR0 0x38 #define KEYLARGO_FCR1 0x3c #define KEYLARGO_FCR2 0x40 #define KEYLARGO_FCR3 0x44 #define KEYLARGO_FCR4 0x48 #define KEYLARGO_FCR5 0x4c #define K2_FCR10 0x24 #define K2_FCR9 0x28 #define K2_FCR8 0x2c #define K2_FCR7 0x30 #define K2_FCR6 0x34 #define FCR_ENET_ENABLE 0x60000000 #define FCR_ENET_RESET 0x80000000 /* Used only by macio_enable_wireless() for now. */ #define KEYLARGO_GPIO_BASE 0x6a #define KEYLARGO_EXTINT_GPIO_REG_BASE 0x58 #define KEYLARGO_MEDIABAY 0x34 #define KEYLARGO_MB0_DEV_ENABLE 0x00001000 #define KEYLARGO_MB0_DEV_POWER 0x00000400 #define KEYLARGO_MB0_DEV_RESET 0x00000200 #define KEYLARGO_MB0_ENABLE 0x00000100 #define KEYLARGO_MB1_DEV_ENABLE 0x10000000 #define KEYLARGO_MB1_DEV_POWER 0x04000000 #define KEYLARGO_MB1_DEV_RESET 0x02000000 #define KEYLARGO_MB1_ENABLE 0x01000000 #define FCR0_CHOOSE_SCCB 0x00000001 #define FCR0_CHOOSE_SCCA 0x00000002 #define FCR0_SLOW_SCC_PCLK 0x00000004 #define FCR0_RESET_SCC 0x00000008 #define FCR0_SCCA_ENABLE 0x00000010 #define FCR0_SCCB_ENABLE 0x00000020 #define FCR0_SCC_CELL_ENABLE 0x00000040 #define FCR0_CHOOSE_VIA 0x00000080 #define FCR0_HIGH_BAND_FOR_1MB 0x00000080 #define FCR0_USE_IR_SOURCE_2 0x00000200 /* KeyLargo */ #define FCR0_USE_IR_SOURCE_1 0x00000400 /* KeyLargo */ #define FCR0_USB0_PMI_ENABLE 0x00000400 /* Pangea and Intrepid */ #define FCR0_IRDA_SWRESET 0x00000800 /* KeyLargo */ #define FCR0_USB0_REF_SUSPEND_SEL 0x00000800 /* Pangea and Intrepid */ #define FCR0_IRDA_DEFAULT1 0x00001000 /* KeyLargo */ #define FCR0_USB0_REF_SUSPEND 0x00001000 /* Pangea and Intrepid */ #define FCR0_IRDA_DEFAULT0 0x00002000 /* KeyLargo */ #define FCR0_USB0_PAD_SUSPEND_SEL 0x00002000 /* Pangea and Intrepid */ #define FCR0_IRDA_FAST_CON 0x00004000 /* KeyLargo */ #define FCR0_USB1_PMI_ENABLE 0x00004000 /* Pangea and Intrepid */ #define FCR0_IRDA_ENABLE 0x00008000 #define FCR0_USB1_REF_SUSPEND_SEL 0x00008000 #define FCR0_IRDA_CLK32_ENABLE 0x00010000 #define FCR0_USB1_REF_SUSPEND 0x00010000 #define FCR0_IRDA_CLK19_ENABLE 0x00020000 #define FCR0_USB1_PAD_SUSPEND_SEL 0x00020000 #define FCR0_USB0_PAD_SUSPEND_0 0x00040000 #define FCR0_USB0_PAD_SUSPEND_1 0x00080000 #define FCR0_USB0_CELL_ENABLE 0x00100000 #define FCR0_USB1_PAD_SUSPEND_0 0x00400000 #define FCR0_USB1_PAD_SUSPEND_1 0x00800000 #define FCR0_USB1_CELL_ENABLE 0x01000000 #define FCR0_USB_REF_SUSPEND 0x10000000 #define FCR1_USB2_PMI_ENABLE 0x00000001 #define FCR1_AUDIO_SEL_22MCLK 0x00000002 #define FCR1_USB2_REF_SUSPEND_SEL 0x00000002 #define FCR1_USB2_REF_SUSPEND 0x00000002 #define FCR1_AUDIO_CLK_ENABLE 0x00000008 #define FCR1_USB2_PAD_SUSPEND_SEL 0x00000008 #define FCR1_USB2_PAD_SUSPEND0 0x00000010 #define FCR1_AUDIO_CLKOUT_ENABLE 0x00000020 #define FCR1_USB2_PAD_SUSPEND1 0x00000020 #define FCR1_AUDIO_CELL_ENABLE 0x00000040 #define FCR1_USB2_CELL_ENABLE 0x00000040 #define FCR1_CHOOSE_AUDIO 0x00000080 #define FCR1_CHOOSE_I2S0 0x00000400 #define FCR1_I2S0_CELL_ENABLE 0x00000400 #define FCR1_I2S0_CLK_ENABLE 0x00001000 #define FCR1_I2S0_ENABLE 0x00002000 #define FCR1_I2S1_CELL_ENABLE 0x00020000 #define FCR1_I2S1_CLK_ENABLE 0x00080000 #define FCR1_I2S1_ENABLE 0x00100000 #define FCR1_EIDE0_ENABLE 0x00800000 #define FCR1_EIDE0_RESET 0x01000000 #define FCR1_EIDE1_ENABLE 0x04000000 #define FCR1_EIDE1_RESET 0x08000000 #define FCR1_UIDE_ENABLE 0x20000000 #define FCR1_UIDE_RESET 0x40000000 #define FCR2_IOBUS_ENABLE 0x00000002 #define FCR2_SLEEP_STATE 0x00000100 #define FCR2_STOP_ALL_KL_CLOCKS 0x00000100 #define FCR2_MPIC_ENABLE 0x00020000 #define FCR2_CARD_SLOT_RESET 0x00040000 #define FCR2_ALT_DATA_OUT 0x02000000 #define FCR3_SHUTDOWN_PLL_TOTAL 0x00000001 #define FCR3_SHUTDOWN_PLL_KW6 0x00000002 #define FCR3_SHUTDOWN_PLL3 0x00000002 #define FCR3_SHUTDOWN_PLL_KW4 0x00000004 #define FCR3_SHUTDOWN_PLL2 0x00000004 #define FCR3_SHUTDOWN_PLL_KW35 0x00000008 #define FCR3_SHUTDOWN_PLL1 0x00000008 #define FCR3_SHUTDOWN_PLL_KW12 0x00000010 #define FCR3_ENABLE_PLL3_SHUTDOWN 0x00000010 #define FCR3_ENABLE_PLL2_SHUTDOWN 0x00000020 #define FCR3_ENABLE_PLL1_SHUTDOWN 0x00000040 #define FCR3_SHUTDOWN_PLL_2X 0x00000080 #define FCR3_CLK_66_ENABLE 0x00000100 #define FCR3_CLK_49_ENABLE 0x00000200 #define FCR3_CLK_45_ENABLE 0x00000400 #define FCR3_CLK_31_ENABLE 0x00000800 #define FCR3_TMR_CLK18_ENABLE 0x00001000 #define FCR3_I2S1_CLK18_ENABLE 0x00002000 #define FCR3_I2S0_CLK18_ENABLE 0x00004000 #define FCR3_VIA_CLK16_ENABLE 0x00008000 #define FCR3_VIA_CLK32_ENABLE 0x00008000 #define FCR3_PORT5_DISCONNECT_SELECT 0x00010000 #define FCR3_PORT5_CONNECT_SELECT 0x00020000 #define FCR3_PORT5_RESUME_SELECT 0x00040000 #define FCR3_PORT5_ENABLE 0x00080000 #define FCR3_STOPPING_33_ENABLED 0x00080000 #define FCR3_PLL_ENABLE_TEST 0x00080000 #define FCR3_PORT5_DISCONNECT 0x00100000 #define FCR3_PORT5_CONNECT 0x00200000 #define FCR3_PORT5_RESUME 0x00400000 #define FCR3_PORT6_DISCONNECT_SELECT 0x00800000 #define FCR3_PORT6_CONNECT_SELECT 0x02000000 #define FCR3_PORT6_RESUME_SELECT 0x04000000 #define FCR3_PORT6_ENABLE 0x08000000 #define FCR3_PORT6_DISCONNECT 0x10000000 #define FCR3_PORT6_CONNECT 0x20000000 #define FCR3_PORT6_RESUME 0x40000000 #define FCR4_PORT1_DISCONNECT_SELECT 0x00000001 #define FCR4_PORT1_CONNECT_SELECT 0x00000002 #define FCR4_PORT1_RESUME_SELECT 0x00000004 #define FCR4_PORT1_ENABLE 0x00000008 #define FCR4_PORT1_DISCONNECT 0x00000010 #define FCR4_PORT1_CONNECT 0x00000020 #define FCR4_PORT1_RESUME 0x00000040 #define FCR4_PORT2_DISCONNECT_SELECT 0x00000100 #define FCR4_PORT2_CONNECT_SELECT 0x00000200 #define FCR4_PORT2_RESUME_SELECT 0x00000400 #define FCR4_PORT2_ENABLE 0x00000800 #define FCR4_PORT2_DISCONNECT 0x00001000 #define FCR4_PORT2_CONNECT 0x00002000 #define FCR4_PORT2_RESUME 0x00004000 #define FCR4_PORT3_DISCONNECT_SELECT 0x00010000 #define FCR4_PORT3_CONNECT_SELECT 0x00020000 #define FCR4_PORT3_RESUME_SELECT 0x00040000 #define FCR4_PORT3_ENABLE 0x00080000 #define FCR4_PORT3_DISCONNECT 0x00100000 #define FCR4_PORT3_CONNECT 0x00200000 #define FCR4_PORT3_RESUME 0x00400000 #define FCR4_PORT4_DISCONNECT_SELECT 0x01000000 #define FCR4_PORT4_CONNECT_SELECT 0x02000000 #define FCR4_PORT4_RESUME_SELECT 0x04000000 #define FCR4_PORT4_ENABLE 0x08000000 #define FCR4_PORT4_DISCONNECT 0x10000000 #define FCR4_PORT4_CONNECT 0x20000000 #define FCR4_PORT4_RESUME 0x40000000 #define FCR5_VIA_USE_CLK31 0x00000001 #define FCR5_SCC_USE_CLK31 0x00000002 #define FCR5_PWM_CLK32_ENABLE 0x00000004 #define FCR5_CLK3_68_ENABLE 0x00000010 #define FCR5_CLK32_ENABLE 0x00000020 /* KeyLargo sleep bits */ #define KEYLARGO_FCR0_SLEEP_SET FCR0_USB_REF_SUSPEND #define KEYLARGO_FCR0_SLEEP_CLR (FCR0_SCCA_ENABLE | FCR0_SCCB_ENABLE | \ FCR0_SCC_CELL_ENABLE | FCR0_IRDA_ENABLE | FCR0_IRDA_CLK32_ENABLE | \ FCR0_IRDA_CLK19_ENABLE) #define KEYLARGO_FCR1_SLEEP_SET 0 #define KEYLARGO_FCR1_SLEEP_CLR (FCR1_AUDIO_SEL_22MCLK | FCR1_AUDIO_CLK_ENABLE | \ FCR1_AUDIO_CLKOUT_ENABLE | FCR1_AUDIO_CELL_ENABLE | \ FCR1_I2S0_CELL_ENABLE | FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE | \ FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | FCR1_I2S1_ENABLE | \ FCR1_EIDE0_ENABLE | FCR1_EIDE1_ENABLE | FCR1_UIDE_ENABLE | \ FCR1_EIDE0_RESET | FCR1_EIDE1_RESET) #define KEYLARGO_FCR2_SLEEP_SET 0 #define KEYLARGO_FCR2_SLEEP_CLR FCR2_IOBUS_ENABLE #define KEYLARGO_FCR3_SLEEP_SET (FCR3_SHUTDOWN_PLL_KW6 | FCR3_SHUTDOWN_PLL_KW4 | \ FCR3_SHUTDOWN_PLL_KW35 | FCR3_SHUTDOWN_PLL_KW12) #define KEYLARGO_FCR3_SLEEP_CLR (FCR3_CLK_66_ENABLE | FCR3_CLK_49_ENABLE | \ FCR3_CLK_45_ENABLE | FCR3_CLK_31_ENABLE | FCR3_TMR_CLK18_ENABLE | \ FCR3_I2S1_CLK18_ENABLE | FCR3_I2S0_CLK18_ENABLE | FCR3_VIA_CLK32_ENABLE) /* Pangea sleep bits */ #define PANGEA_FCR0_SLEEP_SET 0 #define PANGEA_FCR0_SLEEP_CLR (FCR0_USB1_CELL_ENABLE | FCR0_USB0_CELL_ENABLE | \ FCR0_SCC_CELL_ENABLE | FCR0_SCCB_ENABLE | FCR0_SCCA_ENABLE) #define PANGEA_FCR1_SLEEP_SET 0 #define PANGEA_FCR1_SLEEP_CLR (FCR1_AUDIO_SEL_22MCLK | FCR1_AUDIO_CLK_ENABLE | \ FCR1_AUDIO_CLKOUT_ENABLE | FCR1_AUDIO_CELL_ENABLE | \ FCR1_I2S0_CELL_ENABLE | FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE | \ FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | FCR1_I2S1_ENABLE | \ FCR1_UIDE_ENABLE) #define PANGEA_FCR2_SLEEP_SET FCR2_ALT_DATA_OUT #define PANGEA_FCR2_SLEEP_CLR 0 -#define PANGEEA_FCR3_SLEEP_SET (FCR3_SHUTDOWN_PLL_KW35 | \ +#define PANGEA_FCR3_SLEEP_SET (FCR3_SHUTDOWN_PLL_KW35 | \ FCR3_SHUTDOWN_PLL_KW4 | FCR3_SHUTDOWN_PLL_KW6) #define PANGEA_FCR3_SLEEP_CLR (FCR3_CLK_49_ENABLE | FCR3_CLK_45_ENABLE | \ FCR3_CLK_31_ENABLE | FCR3_TMR_CLK18_ENABLE | \ FCR3_I2S1_CLK18_ENABLE | FCR3_I2S0_CLK18_ENABLE | FCR3_VIA_CLK16_ENABLE) /* Intrepid sleep bits */ #define INTREPID_FCR0_SLEEP_SET 0 #define INTREPID_FCR0_SLEEP_CLR (FCR0_SCCA_ENABLE | FCR0_SCCB_ENABLE | \ FCR0_SCC_CELL_ENABLE) #define INTREPID_FCR1_SLEEP_SET 0 #define INTREPID_FCR1_SLEEP_CLR ( FCR1_I2S0_CELL_ENABLE | \ FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE | \ FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | \ FCR1_I2S1_ENABLE | FCR1_UIDE_ENABLE) #define INTREPID_FCR2_SLEEP_SET 0 #define INTREPID_FCR2_SLEEP_CLR 0 #define INTREPID_FCR3_SLEEP_SET 0 #define INTREPID_FCR3_SLEEP_CLR (FCR3_CLK_49_ENABLE | FCR3_CLK_45_ENABLE | \ FCR3_TMR_CLK18_ENABLE | \ FCR3_I2S1_CLK18_ENABLE | FCR3_I2S0_CLK18_ENABLE | FCR3_VIA_CLK16_ENABLE) /* * K2 FCRs. */ #define FCR0_K2_USB0_SWRESET 0x00200000 #define FCR0_K2_USB1_SWRESET 0x02000000 #define FCR0_K2_RING_PME_DISABLE 0x08000000 #define FCR1_K2_I2S2_CELL_ENABLE 0x00000010 #define FCR1_K2_I2S2_CLK_ENABLE 0x00000040 #define FCR1_K2_I2S2_ENABLE 0x00000080 #define FCR1_K2_PCI1_BUS_RESET 0x00000100 #define FCR1_K2_PCI1_SLEEP_RESET_EN 0x00000200 #define FCR1_K2_PCI1_CLK_ENABLE 0x00004000 #define FCR1_K2_FW_CLK_ENABLE 0x00008000 #define FCR1_K2_FW_RESET 0x00010000 #define FCR1_K2_I2S1_SWRESET 0x00040000 #define FCR1_K2_GB_CLK_ENABLE 0x00400000 #define FCR1_GB_PWR_DOWN 0x00800000 #define FCR1_K2_GB_RESET 0x01000000 #define FCR1_K2_SATA_CLK_ENABLE 0x02000000 #define FCR1_K2_SATA_PWR_DOWN 0x04000000 #define FCR1_K2_SATA_RESET 0x08000000 #define FCR1_K2_UATA_CLK_ENABLE 0x10000000 #define FCR1_K2_UATA_RESET 0x40000000 #define FCR1_K2_UATA_CHOOSE_CLK66 0x80000000 #define FCR2_K2_PWM0_AUTO_STOP_EN 0x00000010 #define FCR2_K2_PWM1_AUTO_STOP_EN 0x00000020 #define FCR2_K2_PWM2_AUTO_STOP_EN 0x00000040 #define FCR2_K2_PWM3_AUTO_STOP_EN 0x00000080 #define FCR2_K2_PWM0_OVER_TEMP_EN 0x00000100 #define FCR2_K2_PWM1_OVER_TEMP_EN 0x00000200 #define FCR2_K2_PWM2_OVER_TEMP_EN 0x00000400 #define FCR2_K2_PWM3_OVER_TEMP_EN 0x00000800 #define FCR2_K2_HT_ENABLE_INTERRUPTS 0x00008000 #define FCR2_K2_SB_MPIC_ENABLE_OUTPUTS 0x00010000 #define FCR2_K2_SB_MPIC_RESET 0x00010000 #define FCR2_K2_FW_LINK_ON_INT_EN 0x00040000 #define FCR2_K2_FW_ALT_LINK_ON_SEL 0x00080000 #define FCR2_K2_PWMS_EN 0x00100000 #define FCR2_K2_GB_WAKE_INT_EN 0x00200000 #define FCR2_K2_GB_ENERGY_INT_EN 0x00400000 #define FCR2_K2_BLOCK_EXT_GPIO1 0x00800000 #define FCR2_K2_PCI0_BRIDGE_INT 0x01000000 #define FCR2_K2_PCI1_BRIDGE_INT 0x02000000 #define FCR2_K2_PCI2_BRIDGE_INT 0x04000000 #define FCR2_K2_PCI3_BRIDGE_INT 0x08000000 #define FCR2_K2_PCI4_BRIDGE_INT 0x10000000 #define FCR2_K2_HT_NONFATAL_ERROR 0x40000000 #define FCR2_K2_HT_FATAL_ERROR 0x80000000 #define FCR3_K2_ENABLE_OSC25_SHUTDOWN 0x00000001 #define FCR3_K2_ENABLE_FW_PAD_PWRDOWN 0x00000002 #define FCR3_K2_ENABLE_GBPAD_PWRDOWN 0x00000004 #define FCR3_K2_ENABLE_PLL0_SHUTDOWN 0x00000080 #define FCR3_K2_ENABLE_PLL6_SHUTDOWN 0x00000100 #define FCR3_K2_DYN_CLK_STOP_ENABLE 0x00000800 #define FCR3_K2_I2S2_CLK18_ENABLE 0x00008000 #define FCR9_K2_PCI1_CLK66_IS_STOPPED 0x00000001 #define FCR9_K2_PCI2_CLK66_IS_STOPPED 0x00000002 #define FCR9_K2_FW_CLK66_IS_STOPPED 0x00000004 #define FCR9_K2_UATA_CLK66_IS_STOPPED 0x00000008 #define FCR9_K2_UATA_CLK100_IS_STOPPED 0x00000010 #define FCR9_K2_PCI3_CLK66_IS_STOPPED 0x00000020 #define FCR9_K2_GB_CLK66_IS_STOPPED 0x00000040 #define FCR9_K2_PCI4_CLK66_IS_STOPPED 0x00000080 #define FCR9_K2_SATA_CLK66_IS_STOPPED 0x00000100 #define FCR9_K2_USB0_CLK48_IS_STOPPED 0x00000200 #define FCR9_K2_USB1_CLK48_IS_STOPPED 0x00000400 #define FCR9_K2_CLK45_IS_STOPPED 0x00000800 #define FCR9_K2_CLK49_IS_STOPPED 0x00001000 #define FCR9_K2_OSC25_SHUTDOWN 0x00008000 /* K2 sleep bits */ #define K2_FCR0_SLEEP_SET 0 #define K2_FCR0_SLEEP_CLR (FCR0_USB1_CELL_ENABLE | FCR0_USB0_CELL_ENABLE | \ FCR0_SCC_CELL_ENABLE | FCR0_SCCB_ENABLE | FCR0_SCCA_ENABLE) #define K2_FCR1_SLEEP_SET 0 #define K2_FCR1_SLEEP_CLR ( FCR1_I2S0_CELL_ENABLE | \ FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE | \ FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | FCR1_I2S1_ENABLE | \ FCR1_K2_SATA_RESET | FCR1_K2_UATA_RESET | FCR1_K2_GB_CLK_ENABLE) #define K2_FCR2_SLEEP_SET 0 #define K2_FCR2_SLEEP_CLR FCR2_K2_SB_MPIC_ENABLE_OUTPUTS #define K2_FCR3_SLEEP_SET 0 #define K2_FCR3_SLEEP_CLR FCR3_K2_ENABLE_OSC25_SHUTDOWN /* * Format of a macio reg property entry. */ struct macio_reg { u_int32_t mr_base; u_int32_t mr_size; }; /* * Per macio device structure. */ struct macio_devinfo { int mdi_interrupts[6]; int mdi_ninterrupts; int mdi_base; int mdi_aapl_busid; struct ofw_bus_devinfo mdi_obdinfo; struct resource_list mdi_resources; }; extern int macio_enable_wireless(device_t dev, bool enable); extern int macio_reset_ata(device_t atadev); #endif /* _MACIO_MACIOVAR_H_ */