Index: head/sys/arm/arm/bus_space_base.c =================================================================== --- head/sys/arm/arm/bus_space_base.c (revision 277472) +++ head/sys/arm/arm/bus_space_base.c (revision 277473) @@ -1,157 +1,159 @@ /*- * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of MARVELL nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include "opt_platform.h" /* Prototypes for all the bus_space structure functions */ bs_protos(generic); /* * The bus space tag. This is constant for all instances, so * we never have to explicitly "create" it. */ -static struct bus_space arm_base_tag = { +static struct bus_space arm_base_bus_space = { /* privdata is whatever the implementer wants; unused in base tag */ .bs_privdata = NULL, /* mapping/unmapping */ .bs_map = generic_bs_map, .bs_unmap = generic_bs_unmap, .bs_subregion = generic_bs_subregion, /* allocation/deallocation */ .bs_alloc = generic_bs_alloc, .bs_free = generic_bs_free, /* barrier */ .bs_barrier = generic_bs_barrier, /* read (single) */ .bs_r_1 = NULL, /* Use inline code in bus.h */ .bs_r_2 = NULL, /* Use inline code in bus.h */ .bs_r_4 = NULL, /* Use inline code in bus.h */ .bs_r_8 = NULL, /* Use inline code in bus.h */ /* read multiple */ .bs_rm_1 = generic_bs_rm_1, .bs_rm_2 = generic_bs_rm_2, .bs_rm_4 = generic_bs_rm_4, .bs_rm_8 = BS_UNIMPLEMENTED, /* read region */ .bs_rr_1 = generic_bs_rr_1, .bs_rr_2 = generic_bs_rr_2, .bs_rr_4 = generic_bs_rr_4, .bs_rr_8 = BS_UNIMPLEMENTED, /* write (single) */ .bs_w_1 = NULL, /* Use inline code in bus.h */ .bs_w_2 = NULL, /* Use inline code in bus.h */ .bs_w_4 = NULL, /* Use inline code in bus.h */ .bs_w_8 = NULL, /* Use inline code in bus.h */ /* write multiple */ .bs_wm_1 = generic_bs_wm_1, .bs_wm_2 = generic_bs_wm_2, .bs_wm_4 = generic_bs_wm_4, .bs_wm_8 = BS_UNIMPLEMENTED, /* write region */ .bs_wr_1 = generic_bs_wr_1, .bs_wr_2 = generic_bs_wr_2, .bs_wr_4 = generic_bs_wr_4, .bs_wr_8 = BS_UNIMPLEMENTED, /* set multiple */ .bs_sm_1 = BS_UNIMPLEMENTED, .bs_sm_2 = BS_UNIMPLEMENTED, .bs_sm_4 = BS_UNIMPLEMENTED, .bs_sm_8 = BS_UNIMPLEMENTED, /* set region */ .bs_sr_1 = generic_bs_sr_1, .bs_sr_2 = generic_bs_sr_2, .bs_sr_4 = generic_bs_sr_4, .bs_sr_8 = BS_UNIMPLEMENTED, /* copy */ .bs_c_1 = BS_UNIMPLEMENTED, .bs_c_2 = generic_bs_c_2, .bs_c_4 = BS_UNIMPLEMENTED, .bs_c_8 = BS_UNIMPLEMENTED, /* read stream (single) */ .bs_r_1_s = NULL, /* Use inline code in bus.h */ .bs_r_2_s = NULL, /* Use inline code in bus.h */ .bs_r_4_s = NULL, /* Use inline code in bus.h */ .bs_r_8_s = NULL, /* Use inline code in bus.h */ /* read multiple stream */ .bs_rm_1_s = generic_bs_rm_1, .bs_rm_2_s = generic_bs_rm_2, .bs_rm_4_s = generic_bs_rm_4, .bs_rm_8_s = BS_UNIMPLEMENTED, /* read region stream */ .bs_rr_1_s = generic_bs_rr_1, .bs_rr_2_s = generic_bs_rr_2, .bs_rr_4_s = generic_bs_rr_4, .bs_rr_8_s = BS_UNIMPLEMENTED, /* write stream (single) */ .bs_w_1_s = NULL, /* Use inline code in bus.h */ .bs_w_2_s = NULL, /* Use inline code in bus.h */ .bs_w_4_s = NULL, /* Use inline code in bus.h */ .bs_w_8_s = NULL, /* Use inline code in bus.h */ /* write multiple stream */ .bs_wm_1_s = generic_bs_wm_1, .bs_wm_2_s = generic_bs_wm_2, .bs_wm_4_s = generic_bs_wm_4, .bs_wm_8_s = BS_UNIMPLEMENTED, /* write region stream */ .bs_wr_1_s = generic_bs_wr_1, .bs_wr_2_s = generic_bs_wr_2, .bs_wr_4_s = generic_bs_wr_4, .bs_wr_8_s = BS_UNIMPLEMENTED, }; #ifdef FDT -bus_space_tag_t fdtbus_bs_tag = &arm_base_tag; +bus_space_tag_t fdtbus_bs_tag = &arm_base_bus_space; #endif + +bus_space_tag_t arm_base_bs_tag = &arm_base_bus_space; Index: head/sys/arm/include/bus.h =================================================================== --- head/sys/arm/include/bus.h (revision 277472) +++ head/sys/arm/include/bus.h (revision 277473) @@ -1,757 +1,758 @@ /* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */ /*- * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, * NASA Ames Research Center. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 1996 Charles M. Hannum. All rights reserved. * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Christopher G. Demetriou * for the NetBSD Project. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_BUS_H_ #define _MACHINE_BUS_H_ #include /* * int bus_space_map (bus_space_tag_t t, bus_addr_t addr, * bus_size_t size, int flags, bus_space_handle_t *bshp); * * Map a region of bus space. */ #define BUS_SPACE_MAP_CACHEABLE 0x01 #define BUS_SPACE_MAP_LINEAR 0x02 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 struct bus_space { /* cookie */ void *bs_privdata; /* mapping/unmapping */ int (*bs_map) (bus_space_tag_t, bus_addr_t, bus_size_t, int, bus_space_handle_t *); void (*bs_unmap) (bus_space_tag_t, bus_space_handle_t, bus_size_t); int (*bs_subregion) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_size_t, bus_space_handle_t *); /* allocation/deallocation */ int (*bs_alloc) (bus_space_tag_t, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); void (*bs_free) (bus_space_tag_t, bus_space_handle_t, bus_size_t); /* get kernel virtual address */ /* barrier */ void (*bs_barrier) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_size_t, int); /* read (single) */ uint8_t (*bs_r_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t); uint16_t (*bs_r_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t); uint32_t (*bs_r_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t); uint64_t (*bs_r_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t); /* read multiple */ void (*bs_rm_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); void (*bs_rm_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); void (*bs_rm_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); void (*bs_rm_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); /* read region */ void (*bs_rr_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); void (*bs_rr_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); void (*bs_rr_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); void (*bs_rr_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); /* write (single) */ void (*bs_w_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t); void (*bs_w_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t); void (*bs_w_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t); void (*bs_w_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint64_t); /* write multiple */ void (*bs_wm_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint8_t *, bus_size_t); void (*bs_wm_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint16_t *, bus_size_t); void (*bs_wm_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint32_t *, bus_size_t); void (*bs_wm_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint64_t *, bus_size_t); /* write region */ void (*bs_wr_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint8_t *, bus_size_t); void (*bs_wr_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint16_t *, bus_size_t); void (*bs_wr_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint32_t *, bus_size_t); void (*bs_wr_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint64_t *, bus_size_t); /* set multiple */ void (*bs_sm_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); void (*bs_sm_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); void (*bs_sm_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); void (*bs_sm_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); /* set region */ void (*bs_sr_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); void (*bs_sr_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); void (*bs_sr_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); void (*bs_sr_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); /* copy */ void (*bs_c_1) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); void (*bs_c_2) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); void (*bs_c_4) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); void (*bs_c_8) (bus_space_tag_t, bus_space_handle_t, bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); /* read stream (single) */ uint8_t (*bs_r_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); uint16_t (*bs_r_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); uint32_t (*bs_r_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); uint64_t (*bs_r_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t); /* read multiple stream */ void (*bs_rm_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); void (*bs_rm_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); void (*bs_rm_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); void (*bs_rm_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); /* read region stream */ void (*bs_rr_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); void (*bs_rr_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); void (*bs_rr_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); void (*bs_rr_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); /* write stream (single) */ void (*bs_w_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint8_t); void (*bs_w_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint16_t); void (*bs_w_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint32_t); void (*bs_w_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, uint64_t); /* write multiple stream */ void (*bs_wm_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint8_t *, bus_size_t); void (*bs_wm_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint16_t *, bus_size_t); void (*bs_wm_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint32_t *, bus_size_t); void (*bs_wm_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint64_t *, bus_size_t); /* write region stream */ void (*bs_wr_1_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint8_t *, bus_size_t); void (*bs_wr_2_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint16_t *, bus_size_t); void (*bs_wr_4_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint32_t *, bus_size_t); void (*bs_wr_8_s) (bus_space_tag_t, bus_space_handle_t, bus_size_t, const uint64_t *, bus_size_t); }; +extern bus_space_tag_t arm_base_bs_tag; /* * Utility macros; INTERNAL USE ONLY. */ #define __bs_c(a,b) __CONCAT(a,b) #define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size) #define __bs_nonsingle(type, sz, t, h, o, a, c) \ (*(t)->__bs_opname(type,sz))((t), h, o, a, c) #define __bs_set(type, sz, t, h, o, v, c) \ (*(t)->__bs_opname(type,sz))((t), h, o, v, c) #define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \ (*(t)->__bs_opname(c,sz))((t), h1, o1, h2, o2, cnt) #define __bs_opname_s(op,size) __bs_c(__bs_c(__bs_c(__bs_c(bs_,op),_),size),_s) #define __bs_rs_s(sz, t, h, o) \ (*(t)->__bs_opname_s(r,sz))((t), h, o) #define __bs_ws_s(sz, t, h, o, v) \ (*(t)->__bs_opname_s(w,sz))((t), h, o, v) #define __bs_nonsingle_s(type, sz, t, h, o, a, c) \ (*(t)->__bs_opname_s(type,sz))((t), h, o, a, c) #define __generate_inline_bs_rs(IFN, MBR, TYP) \ static inline TYP \ IFN(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) \ { \ \ if (__predict_true(t->MBR == NULL)) \ return (*(volatile TYP *)(h + o)); \ else \ return (t->MBR(t, h, o)); \ } #define __generate_inline_bs_ws(IFN, MBR, TYP) \ static inline void \ IFN(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, TYP v)\ { \ \ if (__predict_true(t->MBR == NULL)) \ *(volatile TYP *)(h + o) = v; \ else \ t->MBR(t, h, o, v); \ } /* * Mapping and unmapping operations. */ #define bus_space_map(t, a, s, c, hp) \ (*(t)->bs_map)((t), (a), (s), (c), (hp)) #define bus_space_unmap(t, h, s) \ (*(t)->bs_unmap)((t), (h), (s)) #define bus_space_subregion(t, h, o, s, hp) \ (*(t)->bs_subregion)((t), (h), (o), (s), (hp)) /* * Allocation and deallocation operations. */ #define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \ (*(t)->bs_alloc)((t), (rs), (re), (s), (a), (b), \ (c), (ap), (hp)) #define bus_space_free(t, h, s) \ (*(t)->bs_free)((t), (h), (s)) /* * Bus barrier operations. */ #define bus_space_barrier(t, h, o, l, f) \ (*(t)->bs_barrier)((t), (h), (o), (l), (f)) #define BUS_SPACE_BARRIER_READ 0x01 #define BUS_SPACE_BARRIER_WRITE 0x02 /* * Bus read (single) operations. */ __generate_inline_bs_rs(bus_space_read_1, bs_r_1, uint8_t); __generate_inline_bs_rs(bus_space_read_2, bs_r_2, uint16_t); __generate_inline_bs_rs(bus_space_read_4, bs_r_4, uint32_t); __generate_inline_bs_rs(bus_space_read_8, bs_r_8, uint64_t); __generate_inline_bs_rs(bus_space_read_stream_1, bs_r_1_s, uint8_t); __generate_inline_bs_rs(bus_space_read_stream_2, bs_r_2_s, uint16_t); __generate_inline_bs_rs(bus_space_read_stream_4, bs_r_4_s, uint32_t); __generate_inline_bs_rs(bus_space_read_stream_8, bs_r_8_s, uint64_t); /* * Bus read multiple operations. */ #define bus_space_read_multi_1(t, h, o, a, c) \ __bs_nonsingle(rm,1,(t),(h),(o),(a),(c)) #define bus_space_read_multi_2(t, h, o, a, c) \ __bs_nonsingle(rm,2,(t),(h),(o),(a),(c)) #define bus_space_read_multi_4(t, h, o, a, c) \ __bs_nonsingle(rm,4,(t),(h),(o),(a),(c)) #define bus_space_read_multi_8(t, h, o, a, c) \ __bs_nonsingle(rm,8,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(rm,1,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(rm,2,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(rm,4,(t),(h),(o),(a),(c)) #define bus_space_read_multi_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(rm,8,(t),(h),(o),(a),(c)) /* * Bus read region operations. */ #define bus_space_read_region_1(t, h, o, a, c) \ __bs_nonsingle(rr,1,(t),(h),(o),(a),(c)) #define bus_space_read_region_2(t, h, o, a, c) \ __bs_nonsingle(rr,2,(t),(h),(o),(a),(c)) #define bus_space_read_region_4(t, h, o, a, c) \ __bs_nonsingle(rr,4,(t),(h),(o),(a),(c)) #define bus_space_read_region_8(t, h, o, a, c) \ __bs_nonsingle(rr,8,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(rr,1,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(rr,2,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(rr,4,(t),(h),(o),(a),(c)) #define bus_space_read_region_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(rr,8,(t),(h),(o),(a),(c)) /* * Bus write (single) operations. */ __generate_inline_bs_ws(bus_space_write_1, bs_w_1, uint8_t); __generate_inline_bs_ws(bus_space_write_2, bs_w_2, uint16_t); __generate_inline_bs_ws(bus_space_write_4, bs_w_4, uint32_t); __generate_inline_bs_ws(bus_space_write_8, bs_w_8, uint64_t); __generate_inline_bs_ws(bus_space_write_stream_1, bs_w_1_s, uint8_t); __generate_inline_bs_ws(bus_space_write_stream_2, bs_w_2_s, uint16_t); __generate_inline_bs_ws(bus_space_write_stream_4, bs_w_4_s, uint32_t); __generate_inline_bs_ws(bus_space_write_stream_8, bs_w_8_s, uint64_t); /* * Bus write multiple operations. */ #define bus_space_write_multi_1(t, h, o, a, c) \ __bs_nonsingle(wm,1,(t),(h),(o),(a),(c)) #define bus_space_write_multi_2(t, h, o, a, c) \ __bs_nonsingle(wm,2,(t),(h),(o),(a),(c)) #define bus_space_write_multi_4(t, h, o, a, c) \ __bs_nonsingle(wm,4,(t),(h),(o),(a),(c)) #define bus_space_write_multi_8(t, h, o, a, c) \ __bs_nonsingle(wm,8,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(wm,1,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(wm,2,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(wm,4,(t),(h),(o),(a),(c)) #define bus_space_write_multi_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(wm,8,(t),(h),(o),(a),(c)) /* * Bus write region operations. */ #define bus_space_write_region_1(t, h, o, a, c) \ __bs_nonsingle(wr,1,(t),(h),(o),(a),(c)) #define bus_space_write_region_2(t, h, o, a, c) \ __bs_nonsingle(wr,2,(t),(h),(o),(a),(c)) #define bus_space_write_region_4(t, h, o, a, c) \ __bs_nonsingle(wr,4,(t),(h),(o),(a),(c)) #define bus_space_write_region_8(t, h, o, a, c) \ __bs_nonsingle(wr,8,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_1(t, h, o, a, c) \ __bs_nonsingle_s(wr,1,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_2(t, h, o, a, c) \ __bs_nonsingle_s(wr,2,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_4(t, h, o, a, c) \ __bs_nonsingle_s(wr,4,(t),(h),(o),(a),(c)) #define bus_space_write_region_stream_8(t, h, o, a, c) \ __bs_nonsingle_s(wr,8,(t),(h),(o),(a),(c)) /* * Set multiple operations. */ #define bus_space_set_multi_1(t, h, o, v, c) \ __bs_set(sm,1,(t),(h),(o),(v),(c)) #define bus_space_set_multi_2(t, h, o, v, c) \ __bs_set(sm,2,(t),(h),(o),(v),(c)) #define bus_space_set_multi_4(t, h, o, v, c) \ __bs_set(sm,4,(t),(h),(o),(v),(c)) #define bus_space_set_multi_8(t, h, o, v, c) \ __bs_set(sm,8,(t),(h),(o),(v),(c)) /* * Set region operations. */ #define bus_space_set_region_1(t, h, o, v, c) \ __bs_set(sr,1,(t),(h),(o),(v),(c)) #define bus_space_set_region_2(t, h, o, v, c) \ __bs_set(sr,2,(t),(h),(o),(v),(c)) #define bus_space_set_region_4(t, h, o, v, c) \ __bs_set(sr,4,(t),(h),(o),(v),(c)) #define bus_space_set_region_8(t, h, o, v, c) \ __bs_set(sr,8,(t),(h),(o),(v),(c)) /* * Copy operations. */ #define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ __bs_copy(1, t, h1, o1, h2, o2, c) #define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ __bs_copy(2, t, h1, o1, h2, o2, c) #define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ __bs_copy(4, t, h1, o1, h2, o2, c) #define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ __bs_copy(8, t, h1, o1, h2, o2, c) /* * Macros to provide prototypes for all the functions used in the * bus_space structure */ #define bs_map_proto(f) \ int __bs_c(f,_bs_map) (bus_space_tag_t t, bus_addr_t addr, \ bus_size_t size, int cacheable, bus_space_handle_t *bshp); #define bs_unmap_proto(f) \ void __bs_c(f,_bs_unmap) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t size); #define bs_subregion_proto(f) \ int __bs_c(f,_bs_subregion) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, bus_size_t size, \ bus_space_handle_t *nbshp); #define bs_alloc_proto(f) \ int __bs_c(f,_bs_alloc) (bus_space_tag_t t, bus_addr_t rstart, \ bus_addr_t rend, bus_size_t size, bus_size_t align, \ bus_size_t boundary, int cacheable, bus_addr_t *addrp, \ bus_space_handle_t *bshp); #define bs_free_proto(f) \ void __bs_c(f,_bs_free) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t size); #define bs_mmap_proto(f) \ int __bs_c(f,_bs_mmap) (struct cdev *, vm_offset_t, vm_paddr_t *, int); #define bs_barrier_proto(f) \ void __bs_c(f,_bs_barrier) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, bus_size_t len, int flags); #define bs_r_1_proto(f) \ uint8_t __bs_c(f,_bs_r_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_2_proto(f) \ uint16_t __bs_c(f,_bs_r_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_4_proto(f) \ uint32_t __bs_c(f,_bs_r_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_8_proto(f) \ uint64_t __bs_c(f,_bs_r_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_1_s_proto(f) \ uint8_t __bs_c(f,_bs_r_1_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_2_s_proto(f) \ uint16_t __bs_c(f,_bs_r_2_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_r_4_s_proto(f) \ uint32_t __bs_c(f,_bs_r_4_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset); #define bs_w_1_proto(f) \ void __bs_c(f,_bs_w_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint8_t value); #define bs_w_2_proto(f) \ void __bs_c(f,_bs_w_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint16_t value); #define bs_w_4_proto(f) \ void __bs_c(f,_bs_w_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint32_t value); #define bs_w_8_proto(f) \ void __bs_c(f,_bs_w_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint64_t value); #define bs_w_1_s_proto(f) \ void __bs_c(f,_bs_w_1_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint8_t value); #define bs_w_2_s_proto(f) \ void __bs_c(f,_bs_w_2_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint16_t value); #define bs_w_4_s_proto(f) \ void __bs_c(f,_bs_w_4_s) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint32_t value); #define bs_rm_1_proto(f) \ void __bs_c(f,_bs_rm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint8_t *addr, bus_size_t count); #define bs_rm_2_proto(f) \ void __bs_c(f,_bs_rm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint16_t *addr, bus_size_t count); #define bs_rm_4_proto(f) \ void __bs_c(f,_bs_rm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint32_t *addr, bus_size_t count); #define bs_rm_8_proto(f) \ void __bs_c(f,_bs_rm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint64_t *addr, bus_size_t count); #define bs_wm_1_proto(f) \ void __bs_c(f,_bs_wm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, const uint8_t *addr, bus_size_t count); #define bs_wm_2_proto(f) \ void __bs_c(f,_bs_wm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, const uint16_t *addr, bus_size_t count); #define bs_wm_4_proto(f) \ void __bs_c(f,_bs_wm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, const uint32_t *addr, bus_size_t count); #define bs_wm_8_proto(f) \ void __bs_c(f,_bs_wm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, const uint64_t *addr, bus_size_t count); #define bs_rr_1_proto(f) \ void __bs_c(f, _bs_rr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint8_t *addr, bus_size_t count); #define bs_rr_2_proto(f) \ void __bs_c(f, _bs_rr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint16_t *addr, bus_size_t count); #define bs_rr_4_proto(f) \ void __bs_c(f, _bs_rr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint32_t *addr, bus_size_t count); #define bs_rr_8_proto(f) \ void __bs_c(f, _bs_rr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint64_t *addr, bus_size_t count); #define bs_wr_1_proto(f) \ void __bs_c(f, _bs_wr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, const uint8_t *addr, bus_size_t count); #define bs_wr_2_proto(f) \ void __bs_c(f, _bs_wr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, const uint16_t *addr, bus_size_t count); #define bs_wr_4_proto(f) \ void __bs_c(f, _bs_wr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, const uint32_t *addr, bus_size_t count); #define bs_wr_8_proto(f) \ void __bs_c(f, _bs_wr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, const uint64_t *addr, bus_size_t count); #define bs_sm_1_proto(f) \ void __bs_c(f,_bs_sm_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint8_t value, bus_size_t count); #define bs_sm_2_proto(f) \ void __bs_c(f,_bs_sm_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint16_t value, bus_size_t count); #define bs_sm_4_proto(f) \ void __bs_c(f,_bs_sm_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint32_t value, bus_size_t count); #define bs_sm_8_proto(f) \ void __bs_c(f,_bs_sm_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint64_t value, bus_size_t count); #define bs_sr_1_proto(f) \ void __bs_c(f,_bs_sr_1) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint8_t value, bus_size_t count); #define bs_sr_2_proto(f) \ void __bs_c(f,_bs_sr_2) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint16_t value, bus_size_t count); #define bs_sr_4_proto(f) \ void __bs_c(f,_bs_sr_4) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint32_t value, bus_size_t count); #define bs_sr_8_proto(f) \ void __bs_c(f,_bs_sr_8) (bus_space_tag_t t, bus_space_handle_t bsh, \ bus_size_t offset, uint64_t value, bus_size_t count); #define bs_c_1_proto(f) \ void __bs_c(f,_bs_c_1) (bus_space_tag_t t, bus_space_handle_t bsh1, \ bus_size_t offset1, bus_space_handle_t bsh2, \ bus_size_t offset2, bus_size_t count); #define bs_c_2_proto(f) \ void __bs_c(f,_bs_c_2) (bus_space_tag_t t, bus_space_handle_t bsh1, \ bus_size_t offset1, bus_space_handle_t bsh2, \ bus_size_t offset2, bus_size_t count); #define bs_c_4_proto(f) \ void __bs_c(f,_bs_c_4) (bus_space_tag_t t, bus_space_handle_t bsh1, \ bus_size_t offset1, bus_space_handle_t bsh2, \ bus_size_t offset2, bus_size_t count); #define bs_c_8_proto(f) \ void __bs_c(f,_bs_c_8) (bus_space_tag_t t, bus_space_handle_t bsh1, \ bus_size_t offset1, bus_space_handle_t bsh2, \ bus_size_t offset2, bus_size_t count); #define bs_protos(f) \ bs_map_proto(f); \ bs_unmap_proto(f); \ bs_subregion_proto(f); \ bs_alloc_proto(f); \ bs_free_proto(f); \ bs_mmap_proto(f); \ bs_barrier_proto(f); \ bs_r_1_proto(f); \ bs_r_2_proto(f); \ bs_r_4_proto(f); \ bs_r_8_proto(f); \ bs_r_1_s_proto(f); \ bs_r_2_s_proto(f); \ bs_r_4_s_proto(f); \ bs_w_1_proto(f); \ bs_w_2_proto(f); \ bs_w_4_proto(f); \ bs_w_8_proto(f); \ bs_w_1_s_proto(f); \ bs_w_2_s_proto(f); \ bs_w_4_s_proto(f); \ bs_rm_1_proto(f); \ bs_rm_2_proto(f); \ bs_rm_4_proto(f); \ bs_rm_8_proto(f); \ bs_wm_1_proto(f); \ bs_wm_2_proto(f); \ bs_wm_4_proto(f); \ bs_wm_8_proto(f); \ bs_rr_1_proto(f); \ bs_rr_2_proto(f); \ bs_rr_4_proto(f); \ bs_rr_8_proto(f); \ bs_wr_1_proto(f); \ bs_wr_2_proto(f); \ bs_wr_4_proto(f); \ bs_wr_8_proto(f); \ bs_sm_1_proto(f); \ bs_sm_2_proto(f); \ bs_sm_4_proto(f); \ bs_sm_8_proto(f); \ bs_sr_1_proto(f); \ bs_sr_2_proto(f); \ bs_sr_4_proto(f); \ bs_sr_8_proto(f); \ bs_c_1_proto(f); \ bs_c_2_proto(f); \ bs_c_4_proto(f); \ bs_c_8_proto(f); void generic_bs_unimplemented(void); #define BS_UNIMPLEMENTED (void *)generic_bs_unimplemented #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) #define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF #define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF #define BUS_SPACE_MAXADDR 0xFFFFFFFF #define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF #define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF #define BUS_SPACE_MAXSIZE 0xFFFFFFFF #define BUS_SPACE_UNRESTRICTED (~0) #include /* * Get the physical address of a bus space memory-mapped resource. * Doing this as a macro is a temporary solution until a more robust fix is * designed. It also serves to mark the locations needing that fix. */ #define BUS_SPACE_PHYSADDR(res, offs) \ ((u_int)(rman_get_start(res)+(offs))) #endif /* _MACHINE_BUS_H_ */ Index: head/sys/arm/versatile/versatile_pci_bus_space.h =================================================================== --- head/sys/arm/versatile/versatile_pci_bus_space.h (revision 277472) +++ head/sys/arm/versatile/versatile_pci_bus_space.h (nonexistent) @@ -1,35 +0,0 @@ -/*- - * Copyright (c) 2009, Oleksandr Tymoshenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef __VERSATILE_PCI_BUS_SPACEH__ -#define __VERSATILE_PCI_BUS_SPACEH__ - -extern bus_space_tag_t versatile_bus_space_pcimem; - -#endif /* __VERSATILE_PCI_BUS_SPACEH__ */ Property changes on: head/sys/arm/versatile/versatile_pci_bus_space.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm/versatile/bus_space.c =================================================================== --- head/sys/arm/versatile/bus_space.c (revision 277472) +++ head/sys/arm/versatile/bus_space.c (nonexistent) @@ -1,114 +0,0 @@ -/*- - * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. - * All rights reserved. - * - * Developed by Semihalf. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of MARVELL nor the names of contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include - -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); - -struct bus_space _base_tag = { - /* cookie */ - .bs_privdata = (void *) 0, - - /* mapping/unmapping */ - .bs_map = generic_bs_map, - .bs_unmap = generic_bs_unmap, - .bs_subregion = generic_bs_subregion, - - /* allocation/deallocation */ - .bs_alloc = generic_bs_alloc, - .bs_free = generic_bs_free, - - /* barrier */ - .bs_barrier = generic_bs_barrier, - - /* read (single) */ - .bs_r_1 = generic_bs_r_1, - .bs_r_2 = generic_bs_r_2, - .bs_r_4 = generic_bs_r_4, - .bs_r_8 = NULL, - - /* read multiple */ - .bs_rm_1 = generic_bs_rm_1, - .bs_rm_2 = generic_bs_rm_2, - .bs_rm_4 = generic_bs_rm_4, - .bs_rm_8 = NULL, - - /* read region */ - .bs_rr_1 = generic_bs_rr_1, - .bs_rr_2 = generic_bs_rr_2, - .bs_rr_4 = generic_bs_rr_4, - .bs_rr_8 = NULL, - - /* write (single) */ - .bs_w_1 = generic_bs_w_1, - .bs_w_2 = generic_bs_w_2, - .bs_w_4 = generic_bs_w_4, - .bs_w_8 = NULL, - - /* write multiple */ - .bs_wm_1 = generic_bs_wm_1, - .bs_wm_2 = generic_bs_wm_2, - .bs_wm_4 = generic_bs_wm_4, - .bs_wm_8 = NULL, - - /* write region */ - .bs_wr_1 = generic_bs_wr_1, - .bs_wr_2 = generic_bs_wr_2, - .bs_wr_4 = generic_bs_wr_4, - .bs_wr_8 = NULL, - - /* set multiple */ - /* XXX not implemented */ - - /* set region */ - .bs_sr_1 = NULL, - .bs_sr_2 = generic_bs_sr_2, - .bs_sr_4 = generic_bs_sr_4, - .bs_sr_8 = NULL, - - /* copy */ - .bs_c_1 = NULL, - .bs_c_2 = generic_bs_c_2, - .bs_c_4 = NULL, - .bs_c_8 = NULL, -}; - -bus_space_tag_t fdtbus_bs_tag = &_base_tag; Property changes on: head/sys/arm/versatile/bus_space.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm/versatile/versatile_pci_bus_space.c =================================================================== --- head/sys/arm/versatile/versatile_pci_bus_space.c (revision 277472) +++ head/sys/arm/versatile/versatile_pci_bus_space.c (nonexistent) @@ -1,152 +0,0 @@ -/*- - * Copyright (c) 2009, Oleksandr Tymoshenko - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include - -#include -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(generic); - -/* - * Bus space that handles offsets in word for 1/2 bytes read/write access. - * Byte order of values is handled by device drivers itself. - */ -static struct bus_space bus_space_pcimem = { - /* cookie */ - (void *) 0, - - /* mapping/unmapping */ - generic_bs_map, - generic_bs_unmap, - generic_bs_subregion, - - /* allocation/deallocation */ - NULL, - NULL, - - /* barrier */ - generic_bs_barrier, - - /* read (single) */ - generic_bs_r_1, - generic_bs_r_2, - generic_bs_r_4, - NULL, - - /* read multiple */ - generic_bs_rm_1, - generic_bs_rm_2, - generic_bs_rm_4, - NULL, - - /* read region */ - generic_bs_rr_1, - generic_bs_rr_2, - generic_bs_rr_4, - NULL, - - /* write (single) */ - generic_bs_w_1, - generic_bs_w_2, - generic_bs_w_4, - NULL, - - /* write multiple */ - generic_bs_wm_1, - generic_bs_wm_2, - generic_bs_wm_4, - NULL, - - /* write region */ - generic_bs_wr_1, - generic_bs_wr_2, - generic_bs_wr_4, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - NULL, - generic_bs_sr_4, - NULL, - - /* copy */ - NULL, - NULL, - NULL, - NULL, - - /* read (single) stream */ - NULL, - NULL, - NULL, - NULL, - - /* read multiple stream */ - NULL, - NULL, - NULL, - NULL, - - /* read region stream */ - NULL, - NULL, - NULL, - NULL, - - /* write (single) stream */ - NULL, - NULL, - NULL, - NULL, - - /* write multiple stream */ - NULL, - NULL, - NULL, - NULL, - - /* write region stream */ - NULL, - NULL, - NULL, - NULL, -}; - -bus_space_tag_t versatile_bus_space_pcimem = &bus_space_pcimem; Property changes on: head/sys/arm/versatile/versatile_pci_bus_space.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm/versatile/files.versatile =================================================================== --- head/sys/arm/versatile/files.versatile (revision 277472) +++ head/sys/arm/versatile/files.versatile (revision 277473) @@ -1,21 +1,20 @@ # $FreeBSD$ +arm/arm/bus_space_base.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_arm11x6.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_armv6.S standard -arm/versatile/bus_space.c standard arm/versatile/pl050.c optional sc arm/versatile/sp804.c standard arm/versatile/versatile_machdep.c standard arm/versatile/versatile_clcd.c optional sc arm/versatile/versatile_common.c standard arm/versatile/versatile_pci.c optional pci -arm/versatile/versatile_pci_bus_space.c optional pci arm/versatile/versatile_sic.c standard arm/versatile/versatile_timer.c standard kern/kern_clocksource.c standard Index: head/sys/arm/versatile/versatile_pci.c =================================================================== --- head/sys/arm/versatile/versatile_pci.c (revision 277472) +++ head/sys/arm/versatile/versatile_pci.c (revision 277473) @@ -1,519 +1,519 @@ /* * Copyright (c) 2012 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #include #include #include #include #include #include #include #define MEM_SYS 0 #define MEM_CORE 1 #define MEM_BASE 2 #define MEM_CONF_BASE 3 #define MEM_REGIONS 4 #define SYS_PCICTL 0x00 #define PCI_CORE_IMAP0 0x00 #define PCI_CORE_IMAP1 0x04 #define PCI_CORE_IMAP2 0x08 #define PCI_CORE_SELFID 0x0C #define PCI_CORE_SMAP0 0x10 #define PCI_CORE_SMAP1 0x14 #define PCI_CORE_SMAP2 0x18 #define VERSATILE_PCI_DEV 0x030010ee #define VERSATILE_PCI_CLASS 0x0b400000 #define PCI_IO_WINDOW 0x44000000 #define PCI_IO_SIZE 0x0c000000 #define PCI_NPREFETCH_WINDOW 0x50000000 #define PCI_NPREFETCH_SIZE 0x10000000 #define PCI_PREFETCH_WINDOW 0x60000000 #define PCI_PREFETCH_SIZE 0x10000000 #define VERSATILE_PCI_IRQ_START 27 #define VERSATILE_PCI_IRQ_END 30 #ifdef DEBUG #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ printf(fmt,##args); } while (0) #else #define dprintf(fmt, args...) #endif #define versatile_pci_sys_read_4(reg) \ bus_read_4(sc->mem_res[MEM_SYS], (reg)) #define versatile_pci_sys_write_4(reg, val) \ bus_write_4(sc->mem_res[MEM_SYS], (reg), (val)) #define versatile_pci_core_read_4(reg) \ bus_read_4(sc->mem_res[MEM_CORE], (reg)) #define versatile_pci_core_write_4(reg, val) \ bus_write_4(sc->mem_res[MEM_CORE], (reg), (val)) #define versatile_pci_read_4(reg) \ bus_read_4(sc->mem_res[MEM_BASE], (reg)) #define versatile_pci_write_4(reg, val) \ bus_write_4(sc->mem_res[MEM_BASE], (reg), (val)) #define versatile_pci_conf_read_4(reg) \ bus_read_4(sc->mem_res[MEM_CONF_BASE], (reg)) #define versatile_pci_conf_write_4(reg, val) \ bus_write_4(sc->mem_res[MEM_CONF_BASE], (reg), (val)) #define versatile_pci_conf_write_2(reg, val) \ bus_write_2(sc->mem_res[MEM_CONF_BASE], (reg), (val)) #define versatile_pci_conf_write_1(reg, val) \ bus_write_1(sc->mem_res[MEM_CONF_BASE], (reg), (val)) struct versatile_pci_softc { struct resource* mem_res[MEM_REGIONS]; struct resource* irq_res; void* intr_hl; int pcib_slot; /* Bus part */ int busno; struct rman io_rman; struct rman irq_rman; struct rman mem_rman; struct mtx mtx; }; static struct resource_spec versatile_pci_mem_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_MEMORY, 1, RF_ACTIVE }, { SYS_RES_MEMORY, 2, RF_ACTIVE }, { SYS_RES_MEMORY, 3, RF_ACTIVE }, { -1, 0, 0 } }; static int versatile_pci_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "versatile,pci")) { device_set_desc(dev, "Versatile PCI controller"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int versatile_pci_attach(device_t dev) { struct versatile_pci_softc *sc = device_get_softc(dev); int err; int slot; uint32_t vendordev_id, class_id; uint32_t val; /* Request memory resources */ err = bus_alloc_resources(dev, versatile_pci_mem_spec, sc->mem_res); if (err) { device_printf(dev, "Error: could not allocate memory resources\n"); return (ENXIO); } /* * Setup memory windows */ versatile_pci_core_write_4(PCI_CORE_IMAP0, (PCI_IO_WINDOW >> 28)); versatile_pci_core_write_4(PCI_CORE_IMAP1, (PCI_NPREFETCH_WINDOW >> 28)); versatile_pci_core_write_4(PCI_CORE_IMAP2, (PCI_PREFETCH_WINDOW >> 28)); /* * XXX: this is SDRAM offset >> 28 * Unused as of QEMU 1.5 */ versatile_pci_core_write_4(PCI_CORE_SMAP0, (PCI_IO_WINDOW >> 28)); versatile_pci_core_write_4(PCI_CORE_SMAP1, (PCI_NPREFETCH_WINDOW >> 28)); versatile_pci_core_write_4(PCI_CORE_SMAP2, (PCI_NPREFETCH_WINDOW >> 28)); versatile_pci_sys_write_4(SYS_PCICTL, 1); for (slot = 0; slot <= PCI_SLOTMAX; slot++) { vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR); class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID); if ((vendordev_id == VERSATILE_PCI_DEV) && (class_id == VERSATILE_PCI_CLASS)) break; } if (slot == (PCI_SLOTMAX + 1)) { bus_release_resources(dev, versatile_pci_mem_spec, sc->mem_res); device_printf(dev, "Versatile PCI core not found\n"); return (ENXIO); } sc->pcib_slot = slot; device_printf(dev, "PCI core at slot #%d\n", slot); versatile_pci_core_write_4(PCI_CORE_SELFID, slot); val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND); val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_MWRICEN); versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val); /* Again SDRAM start >> 28 */ versatile_pci_write_4((slot << 11) + PCIR_BAR(0), 0); versatile_pci_write_4((slot << 11) + PCIR_BAR(1), 0); versatile_pci_write_4((slot << 11) + PCIR_BAR(2), 0); /* Prepare resource managers */ sc->mem_rman.rm_type = RMAN_ARRAY; sc->mem_rman.rm_descr = "versatile PCI memory window"; if (rman_init(&sc->mem_rman) != 0 || rman_manage_region(&sc->mem_rman, PCI_NPREFETCH_WINDOW, PCI_NPREFETCH_WINDOW + PCI_NPREFETCH_SIZE - 1) != 0) { panic("versatile_pci_attach: failed to set up memory rman"); } bootverbose = 1; sc->io_rman.rm_type = RMAN_ARRAY; sc->io_rman.rm_descr = "versatile PCI IO window"; if (rman_init(&sc->io_rman) != 0 || rman_manage_region(&sc->io_rman, PCI_IO_WINDOW, PCI_IO_WINDOW + PCI_IO_SIZE - 1) != 0) { panic("versatile_pci_attach: failed to set up I/O rman"); } sc->irq_rman.rm_type = RMAN_ARRAY; sc->irq_rman.rm_descr = "versatile PCI IRQs"; if (rman_init(&sc->irq_rman) != 0 || rman_manage_region(&sc->irq_rman, VERSATILE_PCI_IRQ_START, VERSATILE_PCI_IRQ_END) != 0) { panic("versatile_pci_attach: failed to set up IRQ rman"); } mtx_init(&sc->mtx, device_get_nameunit(dev), "versatilepci", MTX_SPIN); val = versatile_pci_conf_read_4((12 << 11) + PCIR_COMMAND); for (slot = 0; slot <= PCI_SLOTMAX; slot++) { vendordev_id = versatile_pci_read_4((slot << 11) + PCIR_DEVVENDOR); class_id = versatile_pci_read_4((slot << 11) + PCIR_REVID); if (slot == sc->pcib_slot) continue; if ((vendordev_id == 0xffffffff) && (class_id == 0xffffffff)) continue; val = versatile_pci_conf_read_4((slot << 11) + PCIR_COMMAND); val |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; versatile_pci_conf_write_4((slot << 11) + PCIR_COMMAND, val); } device_add_child(dev, "pci", 0); return (bus_generic_attach(dev)); } static int versatile_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) { struct versatile_pci_softc *sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_DOMAIN: *result = 0; return (0); case PCIB_IVAR_BUS: *result = sc->busno; return (0); } return (ENOENT); } static int versatile_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result) { struct versatile_pci_softc * sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_BUS: sc->busno = result; return (0); } return (ENOENT); } static struct resource * versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct versatile_pci_softc *sc = device_get_softc(bus); struct resource *rv; struct rman *rm; dprintf("Alloc resources %d, %08lx..%08lx, %ld\n", type, start, end, count); switch (type) { case SYS_RES_IOPORT: rm = &sc->io_rman; break; case SYS_RES_IRQ: rm = &sc->irq_rman; break; case SYS_RES_MEMORY: rm = &sc->mem_rman; break; default: return (NULL); } rv = rman_reserve_resource(rm, start, end, count, flags, child); if (rv == NULL) return (NULL); rman_set_rid(rv, *rid); if (flags & RF_ACTIVE) { if (bus_activate_resource(child, type, *rid, rv)) { rman_release_resource(rv); return (NULL); } } return (rv); } static int versatile_pci_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { vm_offset_t vaddr; int res; switch(type) { case SYS_RES_MEMORY: case SYS_RES_IOPORT: vaddr = (vm_offset_t)pmap_mapdev(rman_get_start(r), rman_get_size(r)); rman_set_bushandle(r, vaddr); - rman_set_bustag(r, versatile_bus_space_pcimem); + rman_set_bustag(r, arm_base_bs_tag); res = rman_activate_resource(r); break; case SYS_RES_IRQ: res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, type, rid, r)); break; default: res = ENXIO; break; } return (res); } static int versatile_pci_setup_intr(device_t bus, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *handler, void *arg, void **cookiep) { return BUS_SETUP_INTR(device_get_parent(bus), bus, ires, flags, filt, handler, arg, cookiep); } static int versatile_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, void *cookie) { return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, ires, cookie); } static int versatile_pci_maxslots(device_t dev) { return (PCI_SLOTMAX); } static int versatile_pci_route_interrupt(device_t pcib, device_t device, int pin) { return (27 + ((pci_get_slot(device) + pin - 1) & 3)); } static uint32_t versatile_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { struct versatile_pci_softc *sc = device_get_softc(dev); uint32_t data; uint32_t shift, mask; uint32_t addr; if (sc->pcib_slot == slot) { switch (bytes) { case 4: return (0xffffffff); break; case 2: return (0xffff); break; case 1: return (0xff); break; } } addr = (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3); /* register access is 32-bit aligned */ shift = (reg & 3) * 8; /* Create a mask based on the width, post-shift */ if (bytes == 2) mask = 0xffff; else if (bytes == 1) mask = 0xff; else mask = 0xffffffff; dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, func, reg, bytes); mtx_lock_spin(&sc->mtx); data = versatile_pci_conf_read_4(addr); mtx_unlock_spin(&sc->mtx); /* get request bytes from 32-bit word */ data = (data >> shift) & mask; dprintf("%s: read 0x%x\n", __func__, data); return (data); } static void versatile_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t data, int bytes) { struct versatile_pci_softc *sc = device_get_softc(dev); uint32_t addr; dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, func, reg, bytes); if (sc->pcib_slot == slot) return; addr = (bus << 16) | (slot << 11) | (func << 8) | reg; mtx_lock_spin(&sc->mtx); switch (bytes) { case 4: versatile_pci_conf_write_4(addr, data); break; case 2: versatile_pci_conf_write_2(addr, data); break; case 1: versatile_pci_conf_write_1(addr, data); break; } mtx_unlock_spin(&sc->mtx); } static device_method_t versatile_pci_methods[] = { DEVMETHOD(device_probe, versatile_pci_probe), DEVMETHOD(device_attach, versatile_pci_attach), /* Bus interface */ DEVMETHOD(bus_read_ivar, versatile_pci_read_ivar), DEVMETHOD(bus_write_ivar, versatile_pci_write_ivar), DEVMETHOD(bus_alloc_resource, versatile_pci_alloc_resource), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, versatile_pci_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, versatile_pci_setup_intr), DEVMETHOD(bus_teardown_intr, versatile_pci_teardown_intr), /* pcib interface */ DEVMETHOD(pcib_maxslots, versatile_pci_maxslots), DEVMETHOD(pcib_read_config, versatile_pci_read_config), DEVMETHOD(pcib_write_config, versatile_pci_write_config), DEVMETHOD(pcib_route_interrupt, versatile_pci_route_interrupt), DEVMETHOD_END }; static driver_t versatile_pci_driver = { "pcib", versatile_pci_methods, sizeof(struct versatile_pci_softc), }; static devclass_t versatile_pci_devclass; DRIVER_MODULE(versatile_pci, simplebus, versatile_pci_driver, versatile_pci_devclass, 0, 0);