Index: head/sys/mips/atheros/ar71xx_setup.c =================================================================== --- head/sys/mips/atheros/ar71xx_setup.c (revision 276684) +++ head/sys/mips/atheros/ar71xx_setup.c (revision 276685) @@ -1,199 +1,217 @@ /*- * Copyright (c) 2010 Adrian Chadd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include +#include #define AR71XX_SYS_TYPE_LEN 128 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; enum ar71xx_soc_type ar71xx_soc; struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL; void ar71xx_detect_sys_type(void) { char *chip = "????"; uint32_t id; uint32_t major; uint32_t minor; uint32_t rev = 0; id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID); major = id & REV_ID_MAJOR_MASK; switch (major) { case REV_ID_MAJOR_AR71XX: minor = id & AR71XX_REV_ID_MINOR_MASK; rev = id >> AR71XX_REV_ID_REVISION_SHIFT; rev &= AR71XX_REV_ID_REVISION_MASK; ar71xx_cpu_ops = &ar71xx_chip_def; switch (minor) { case AR71XX_REV_ID_MINOR_AR7130: ar71xx_soc = AR71XX_SOC_AR7130; chip = "7130"; break; case AR71XX_REV_ID_MINOR_AR7141: ar71xx_soc = AR71XX_SOC_AR7141; chip = "7141"; break; case AR71XX_REV_ID_MINOR_AR7161: ar71xx_soc = AR71XX_SOC_AR7161; chip = "7161"; break; } break; case REV_ID_MAJOR_AR7240: ar71xx_soc = AR71XX_SOC_AR7240; chip = "7240"; ar71xx_cpu_ops = &ar724x_chip_def; rev = (id & AR724X_REV_ID_REVISION_MASK); break; case REV_ID_MAJOR_AR7241: ar71xx_soc = AR71XX_SOC_AR7241; chip = "7241"; ar71xx_cpu_ops = &ar724x_chip_def; rev = (id & AR724X_REV_ID_REVISION_MASK); break; case REV_ID_MAJOR_AR7242: ar71xx_soc = AR71XX_SOC_AR7242; chip = "7242"; ar71xx_cpu_ops = &ar724x_chip_def; rev = (id & AR724X_REV_ID_REVISION_MASK); break; case REV_ID_MAJOR_AR913X: minor = id & AR91XX_REV_ID_MINOR_MASK; rev = id >> AR91XX_REV_ID_REVISION_SHIFT; rev &= AR91XX_REV_ID_REVISION_MASK; ar71xx_cpu_ops = &ar91xx_chip_def; switch (minor) { case AR91XX_REV_ID_MINOR_AR9130: ar71xx_soc = AR71XX_SOC_AR9130; chip = "9130"; break; case AR91XX_REV_ID_MINOR_AR9132: ar71xx_soc = AR71XX_SOC_AR9132; chip = "9132"; break; } break; case REV_ID_MAJOR_AR9330: minor = 0; rev = (id & AR933X_REV_ID_REVISION_MASK); chip = "9330"; ar71xx_cpu_ops = &ar933x_chip_def; ar71xx_soc = AR71XX_SOC_AR9330; break; case REV_ID_MAJOR_AR9331: minor = 1; rev = (id & AR933X_REV_ID_REVISION_MASK); chip = "9331"; ar71xx_soc = AR71XX_SOC_AR9331; ar71xx_cpu_ops = &ar933x_chip_def; break; case REV_ID_MAJOR_AR9341: minor = 0; rev = (id & AR934X_REV_ID_REVISION_MASK); chip = "9341"; ar71xx_soc = AR71XX_SOC_AR9341; ar71xx_cpu_ops = &ar934x_chip_def; break; case REV_ID_MAJOR_AR9342: minor = 0; rev = (id & AR934X_REV_ID_REVISION_MASK); chip = "9342"; ar71xx_soc = AR71XX_SOC_AR9342; ar71xx_cpu_ops = &ar934x_chip_def; break; case REV_ID_MAJOR_AR9344: minor = 0; rev = (id & AR934X_REV_ID_REVISION_MASK); chip = "9344"; ar71xx_soc = AR71XX_SOC_AR9344; ar71xx_cpu_ops = &ar934x_chip_def; + break; + + case REV_ID_MAJOR_QCA9556: + minor = 0; + rev = (id & QCA955X_REV_ID_REVISION_MASK); + chip = "9556"; + ar71xx_soc = AR71XX_SOC_QCA9556; + ar71xx_cpu_ops = &qca955x_chip_def; + break; + + case REV_ID_MAJOR_QCA9558: + minor = 0; + rev = (id & QCA955X_REV_ID_REVISION_MASK); + chip = "9558"; + ar71xx_soc = AR71XX_SOC_QCA9558; + ar71xx_cpu_ops = &qca955x_chip_def; break; default: panic("ar71xx: unknown chip id:0x%08x\n", id); } sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); } const char * ar71xx_get_system_type(void) { return ar71xx_sys_type; } Index: head/sys/mips/atheros/files.ar71xx =================================================================== --- head/sys/mips/atheros/files.ar71xx (revision 276684) +++ head/sys/mips/atheros/files.ar71xx (revision 276685) @@ -1,31 +1,32 @@ # $FreeBSD$ mips/atheros/apb.c standard mips/atheros/ar71xx_gpio.c optional gpio mips/atheros/ar71xx_machdep.c standard mips/atheros/ar71xx_ehci.c optional ehci mips/atheros/ar71xx_ohci.c optional ohci mips/atheros/ar71xx_pci.c optional ar71xx_pci pci mips/atheros/ar724x_pci.c optional ar724x_pci pci mips/atheros/ar71xx_pci_bus_space.c optional pci mips/atheros/ar71xx_spi.c optional ar71xx_spi mips/atheros/pcf2123_rtc.c optional pcf2123_rtc ar71xx_spi mips/atheros/ar71xx_wdog.c optional ar71xx_wdog mips/atheros/if_arge.c optional arge mips/atheros/uart_bus_ar71xx.c optional uart_ar71xx mips/atheros/uart_cpu_ar71xx.c optional uart_ar71xx mips/atheros/uart_bus_ar933x.c optional uart_ar933x mips/atheros/uart_cpu_ar933x.c optional uart_ar933x mips/atheros/uart_dev_ar933x.c optional uart_ar933x mips/atheros/ar71xx_bus_space_reversed.c standard mips/mips/intr_machdep.c standard mips/mips/tick.c standard mips/atheros/ar71xx_setup.c standard mips/atheros/ar71xx_chip.c standard mips/atheros/ar724x_chip.c standard mips/atheros/ar91xx_chip.c standard mips/atheros/ar933x_chip.c standard mips/atheros/ar934x_chip.c standard +mips/atheros/qca955x_chip.c standard mips/atheros/ar71xx_fixup.c optional ar71xx_ath_eeprom dev/hwpmc/hwpmc_mips24k.c optional hwpmc_mips24k Index: head/sys/mips/atheros/qca955x_chip.c =================================================================== --- head/sys/mips/atheros/qca955x_chip.c (nonexistent) +++ head/sys/mips/atheros/qca955x_chip.c (revision 276685) @@ -0,0 +1,449 @@ +/*- + * Copyright (c) 2015 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_ddb.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +//#include +#include + +#include +#include + +#include + +#include + +static void +qca955x_chip_detect_mem_size(void) +{ +} + +static void +qca955x_chip_detect_sys_frequency(void) +{ + unsigned long ref_rate; + unsigned long cpu_rate; + unsigned long ddr_rate; + unsigned long ahb_rate; + uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; + uint32_t cpu_pll, ddr_pll; + uint32_t bootstrap; + + bootstrap = ATH_READ_REG(QCA955X_RESET_REG_BOOTSTRAP); + if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) + ref_rate = 40 * 1000 * 1000; + else + ref_rate = 25 * 1000 * 1000; + + pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG); + out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; + ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; + nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & + QCA955X_PLL_CPU_CONFIG_NINT_MASK; + frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; + + cpu_pll = nint * ref_rate / ref_div; + cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); + cpu_pll /= (1 << out_div); + + pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG); + out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; + ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; + nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & + QCA955X_PLL_DDR_CONFIG_NINT_MASK; + frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; + + ddr_pll = nint * ref_rate / ref_div; + ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); + ddr_pll /= (1 << out_div); + + clk_ctrl = ATH_READ_REG(QCA955X_PLL_CLK_CTRL_REG); + + postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & + QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; + + if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) + cpu_rate = ref_rate; + else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) + cpu_rate = ddr_pll / (postdiv + 1); + else + cpu_rate = cpu_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & + QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; + + if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) + ddr_rate = ref_rate; + else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) + ddr_rate = cpu_pll / (postdiv + 1); + else + ddr_rate = ddr_pll / (postdiv + 1); + + postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & + QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; + + if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) + ahb_rate = ref_rate; + else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) + ahb_rate = ddr_pll / (postdiv + 1); + else + ahb_rate = cpu_pll / (postdiv + 1); + +#if 0 + ath79_add_sys_clkdev("ref", ref_rate); + ath79_add_sys_clkdev("cpu", cpu_rate); + ath79_add_sys_clkdev("ddr", ddr_rate); + ath79_add_sys_clkdev("ahb", ahb_rate); + + clk_add_alias("wdt", NULL, "ref", NULL); + clk_add_alias("uart", NULL, "ref", NULL); +#endif + + u_ar71xx_ddr_freq = ddr_rate; + u_ar71xx_cpu_freq = cpu_rate; + u_ar71xx_ahb_freq = ahb_rate; + + u_ar71xx_wdt_freq = ref_rate; + u_ar71xx_uart_freq = ref_rate; + u_ar71xx_mdio_freq = ref_rate; + + +} + +static void +qca955x_chip_device_stop(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE); + ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg | mask); +} + +static void +qca955x_chip_device_start(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE); + ATH_WRITE_REG(QCA955X_RESET_REG_RESET_MODULE, reg & ~mask); +} + +static int +qca955x_chip_device_stopped(uint32_t mask) +{ + uint32_t reg; + + reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE); + return ((reg & mask) == mask); +} + +static void +qca955x_chip_set_mii_speed(uint32_t unit, uint32_t speed) +{ + + /* XXX TODO */ + return; +} + +/* + * XXX TODO !! + */ +static void +qca955x_chip_set_pll_ge(int unit, int speed, uint32_t pll) +{ +#if 0 + switch (unit) { + case 0: + ATH_WRITE_REG(AR934X_PLL_ETH_XMII_CONTROL_REG, pll); + break; + case 1: + /* XXX nothing */ + break; + default: + printf("%s: invalid PLL set for arge unit: %d\n", + __func__, unit); + return; + } +#endif +} + +static void +qca955x_chip_ddr_flush_ge(int unit) +{ +#if 0 + switch (unit) { + case 0: + ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0); + break; + case 1: + ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1); + break; + default: + printf("%s: invalid DDR flush for arge unit: %d\n", + __func__, unit); + return; + } +#endif +} + +static void +qca955x_chip_ddr_flush_ip2(void) +{ +#if 0 + ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC); +#endif +} + +static uint32_t +qca955x_chip_get_eth_pll(unsigned int mac, int speed) +{ +#if 0 + uint32_t pll; + + switch (speed) { + case 10: + pll = AR934X_PLL_VAL_10; + break; + case 100: + pll = AR934X_PLL_VAL_100; + break; + case 1000: + pll = AR934X_PLL_VAL_1000; + break; + default: + printf("%s%d: invalid speed %d\n", __func__, mac, speed); + pll = 0; + } + return (pll); +#else + return (0); +#endif +} + +static void +qca955x_chip_reset_ethernet_switch(void) +{ +#if 0 + ar71xx_device_stop(AR934X_RESET_ETH_SWITCH); + DELAY(100); + ar71xx_device_start(AR934X_RESET_ETH_SWITCH); + DELAY(100); +#endif +} + +#if 0 +static void +qca955x_configure_gmac(uint32_t gmac_cfg) +{ + uint32_t reg; + + reg = ATH_READ_REG(AR934X_GMAC_REG_ETH_CFG); + printf("%s: ETH_CFG=0x%08x\n", __func__, reg); + + reg &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 | + AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + reg |= gmac_cfg; + + ATH_WRITE_REG(AR934X_GMAC_REG_ETH_CFG, reg); +} +#endif + +static void +qca955x_chip_init_usb_peripheral(void) +{ +#if 0 + uint32_t reg; + + reg = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP); + if (reg & AR934X_BOOTSTRAP_USB_MODE_DEVICE) + return; + + ar71xx_device_stop(AR934X_RESET_USBSUS_OVERRIDE); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_USB_PHY); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_USB_PHY_ANALOG); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_USB_HOST); + DELAY(100); +#endif +} + +static void +qca955x_chip_set_mii_if(uint32_t unit, uint32_t mii_mode) +{ + + /* + * XXX ! + * + * Nothing to see here; although gmac0 can have its + * MII configuration changed, the register values + * are slightly different. + */ +} + +/* + * XXX TODO: fetch default MII divider configuration + */ + +static void +qca955x_chip_reset_wmac(void) +{ + + /* XXX TODO */ +} + +static void +qca955x_chip_init_gmac(void) +{ +#if 0 + long gmac_cfg; + + if (resource_long_value("ar934x_gmac", 0, "gmac_cfg", + &gmac_cfg) == 0) { + printf("%s: gmac_cfg=0x%08lx\n", + __func__, + (long) gmac_cfg); + ar934x_configure_gmac((uint32_t) gmac_cfg); + } +#endif +} + +/* + * Reset the NAND Flash Controller. + * + * + active=1 means "make it active". + * + active=0 means "make it inactive". + */ +static void +qca955x_chip_reset_nfc(int active) +{ +#if 0 + if (active) { + ar71xx_device_start(AR934X_RESET_NANDF); + DELAY(100); + + ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG); + DELAY(250); + } else { + ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG); + DELAY(250); + + ar71xx_device_stop(AR934X_RESET_NANDF); + DELAY(100); + } +#endif +} + +/* + * Configure the GPIO output mux setup. + * + * The AR934x introduced an output mux which allowed + * certain functions to be configured on any pin. + * Specifically, the switch PHY link LEDs and + * WMAC external RX LNA switches are not limited to + * a specific GPIO pin. + */ +static void +qca955x_chip_gpio_output_configure(int gpio, uint8_t func) +{ +#if 0 + uint32_t reg, s; + uint32_t t; + + if (gpio > QCA955X_GPIO_COUNT) + return; + + reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); + s = 8 * (gpio % 4); + + /* read-modify-write */ + t = ATH_READ_REG(AR71XX_GPIO_BASE + reg); + t &= ~(0xff << s); + t |= func << s; + ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t); + + /* flush write */ + ATH_READ_REG(AR71XX_GPIO_BASE + reg); +#endif +} + +struct ar71xx_cpu_def qca955x_chip_def = { + &qca955x_chip_detect_mem_size, + &qca955x_chip_detect_sys_frequency, + &qca955x_chip_device_stop, + &qca955x_chip_device_start, + &qca955x_chip_device_stopped, + &qca955x_chip_set_pll_ge, + &qca955x_chip_set_mii_speed, + &qca955x_chip_set_mii_if, + &qca955x_chip_ddr_flush_ge, + &qca955x_chip_get_eth_pll, + &qca955x_chip_ddr_flush_ip2, + &qca955x_chip_init_usb_peripheral, + &qca955x_chip_reset_ethernet_switch, + &qca955x_chip_reset_wmac, + &qca955x_chip_init_gmac, + &qca955x_chip_reset_nfc, + &qca955x_chip_gpio_output_configure, +}; Property changes on: head/sys/mips/atheros/qca955x_chip.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/mips/atheros/qca955x_chip.h =================================================================== --- head/sys/mips/atheros/qca955x_chip.h (nonexistent) +++ head/sys/mips/atheros/qca955x_chip.h (revision 276685) @@ -0,0 +1,34 @@ +/*- + * Copyright (c) 2015 Adrian Chadd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +#ifndef __QCA955X_CHIP_H__ +#define __QCA955X_CHIP_H__ + +extern struct ar71xx_cpu_def qca955x_chip_def; + +#endif Property changes on: head/sys/mips/atheros/qca955x_chip.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property