Index: head/sys/arm/arm/trap-v6.c =================================================================== --- head/sys/arm/arm/trap-v6.c (nonexistent) +++ head/sys/arm/arm/trap-v6.c (revision 276638) @@ -0,0 +1,655 @@ +/*- + * Copyright 2014 Olivier Houchard + * Copyright 2014 Svatopluk Kraus + * Copyright 2014 Michal Meloun + * Copyright 2014 Andrew Turner + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "opt_ktrace.h" + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef KTRACE +#include +#include +#endif + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#ifdef KDB +#include +#include +#endif + +extern char fusubailout[]; + +struct ksig { + int sig; + u_long code; + vm_offset_t addr; +}; + +typedef int abort_func_t(struct trapframe *, u_int, u_int, u_int, u_int, + struct thread *, struct ksig *); + +static abort_func_t abort_fatal; +static abort_func_t abort_align; +static abort_func_t abort_icache; + +struct abort { + abort_func_t *func; + const char *desc; +}; + +/* + * How are the aborts handled? + * + * Undefined Code: + * - Always fatal as we do not know what does it mean. + * Imprecise External Abort: + * - Always fatal, but can be handled somehow in the future. + * Now, due to PCIe buggy harware, ignored. + * Precise External Abort: + * - Always fatal, but who knows in the future??? + * Debug Event: + * - Special handling. + * External Translation Abort (L1 & L2) + * - Always fatal as something is screwed up in page tables or harware. + * Domain Fault (L1 & L2): + * - Always fatal as we do not play game with domains. + * Alignment Fault: + * - Everything should be aligned in kernel including user to kernel and + * vice versa data copying, so we ignore pcb_onfault, and it's always fatal. + * We generate signal in case of abort from user mode. + * Instruction cache maintenance: + * - According to manual, this is translation fault during cache maintenance + * operation. So, it could be really complex in SMP case and fuzzy too + * for cache operations working on virtual addresses. For now, we will + * consider this abort as fatal. In fact, no cache maintenance on + * not mapped virtual addresses should be called. As cache maintenance + * operation (except DMB, DSB, and Flush Prefetch Buffer) are priviledged, + * the abort is fatal for user mode as well for now. (This is good place to + * note that cache maintenance on virtual address fill TLB.) + * Acces Bit (L1 & L2): + * - Fast hardware emulation for kernel and user mode. + * Translation Fault (L1 & L2): + * - Standard fault mechanism is held including vm_fault(). + * Permission Fault (L1 & L2): + * - Fast harware emulation of modify bits and in other cases, standard + * fault mechanism is held including vm_fault(). + */ + +static const struct abort aborts[] = { + {abort_fatal, "Undefined Code (0x000)"}, + {abort_align, "Alignment Fault"}, + {abort_fatal, "Debug Event"}, + {NULL, "Access Bit (L1)"}, + {abort_icache, "Instruction cache maintenance"}, + {NULL, "Translation Fault (L1)"}, + {NULL, "Access Bit (L2)"}, + {NULL, "Translation Fault (L2)"}, + + {abort_fatal, "External Abort"}, + {abort_fatal, "Domain Fault (L1)"}, + {abort_fatal, "Undefined Code (0x00A)"}, + {abort_fatal, "Domain Fault (L2)"}, + {abort_fatal, "External Translation Abort (L1)"}, + {NULL, "Permission Fault (L1)"}, + {abort_fatal, "External Translation Abort (L2)"}, + {NULL, "Permission Fault (L2)"}, + + {abort_fatal, "TLB Conflict Abort"}, + {abort_fatal, "Undefined Code (0x401)"}, + {abort_fatal, "Undefined Code (0x402)"}, + {abort_fatal, "Undefined Code (0x403)"}, + {abort_fatal, "Undefined Code (0x404)"}, + {abort_fatal, "Undefined Code (0x405)"}, + {abort_fatal, "Asynchronous External Abort"}, + {abort_fatal, "Undefined Code (0x407)"}, + + {abort_fatal, "Asynchronous Parity Error on Memory Access"}, + {abort_fatal, "Parity Error on Memory Access"}, + {abort_fatal, "Undefined Code (0x40A)"}, + {abort_fatal, "Undefined Code (0x40B)"}, + {abort_fatal, "Parity Error on Translation (L1)"}, + {abort_fatal, "Undefined Code (0x40D)"}, + {abort_fatal, "Parity Error on Translation (L2)"}, + {abort_fatal, "Undefined Code (0x40F)"} +}; + + +static __inline void +call_trapsignal(struct thread *td, int sig, int code, vm_offset_t addr) +{ + ksiginfo_t ksi; + + CTR4(KTR_TRAP, "%s: addr: %#x, sig: %d, code: %d", + __func__, addr, sig, code); + + /* + * TODO: some info would be nice to know + * if we are serving data or prefetch abort. + */ + + ksiginfo_init_trap(&ksi); + ksi.ksi_signo = sig; + ksi.ksi_code = code; + ksi.ksi_addr = (void *)addr; + trapsignal(td, &ksi); +} + +/* + * abort_imprecise() handles the following abort: + * + * FAULT_EA_IMPREC - Imprecise External Abort + * + * The imprecise means that we don't know where the abort happened, + * thus FAR is undefined. The abort should not never fire, but hot + * plugging or accidental harware failure can be the cause of it. + * If the abort happens, it can even be on different (thread) context. + * Without any additional support, the abort is fatal, as we do not + * know what really happened. + * + * QQQ: Some additional functionality, like pcb_onfault but global, + * can be implemented. Imprecise handlers could be registered + * which tell us if the abort is caused by something they know + * about. They should return one of three codes like: + * FAULT_IS_MINE, + * FAULT_CAN_BE_MINE, + * FAULT_IS_NOT_MINE. + * The handlers should be called until some of them returns + * FAULT_IS_MINE value or all was called. If all handlers return + * FAULT_IS_NOT_MINE value, then the abort is fatal. + */ +static __inline void +abort_imprecise(struct trapframe *tf, u_int fsr, u_int prefetch, u_int usermode) +{ + /* XXXX We can got imprecise abort as result of access + * to not-present PCI/PCIe configuration space. + */ +#if 0 + goto out; +#endif + abort_fatal(tf, FAULT_EA_IMPREC, fsr, 0, prefetch, curthread, NULL); + + /* + * Returning from this function means that we ignore + * the abort for good reason. Note that imprecise abort + * could fire any time even in user mode. + */ + +#if 0 +out: + if (usermode) + userret(curthread, tf); +#endif +} + +/* + * abort_debug() handles the following abort: + * + * FAULT_DEBUG - Debug Event + * + */ +static __inline void +abort_debug(struct trapframe *tf, u_int fsr, u_int prefetch, u_int usermode, + u_int far) +{ + if (usermode) { + struct thread *td; + + td = curthread; + call_trapsignal(td, SIGTRAP, TRAP_BRKPT, far); + userret(td, tf); + } else { +#ifdef KDB + kdb_trap(T_BREAKPOINT, 0, tf); +#else + printf("No debugger in kernel.\n"); +#endif + } +} + +/* + * Abort handler. + * + * FAR, FSR, and everything what can be lost after enabling + * interrupts must be grabbed before the interrupts will be + * enabled. Note that when interrupts will be enabled, we + * could even migrate to another CPU ... + * + * TODO: move quick cases to ASM + */ +void +abort_handler(struct trapframe *tf, int prefetch) +{ + struct thread *td; + vm_offset_t far, va; + int idx, usermode; + uint32_t fsr; + struct ksig ksig; + struct proc *p; + struct pcb *pcb; + struct vm_map *map; + struct vmspace *vm; + vm_prot_t ftype; + int rv; +#ifdef INVARIANTS + void *onfault; +#endif + td = curthread; + fsr = (prefetch) ? cp15_ifsr_get(): cp15_dfsr_get(); + far = (prefetch) ? TRAPF_PC(tf) : cp15_dfar_get(); + + idx = FSR_TO_FAULT(fsr); + usermode = TRAPF_USERMODE(tf); /* Abort came from user mode? */ + if (usermode) + td->td_frame = tf; + + CTR4(KTR_TRAP, "abort_handler: fsr %#x (idx %u) far %#x prefetch %u", + fsr, idx, far, prefetch); + + /* + * Firstly, handle aborts that are not directly related to mapping. + */ + if (__predict_false(idx == FAULT_EA_IMPREC)) { + abort_imprecise(tf, fsr, prefetch, usermode); + return; + } + + if (__predict_false(idx == FAULT_DEBUG)) { + abort_debug(tf, fsr, prefetch, usermode, far); + return; + } + +#ifdef ARM_NEW_PMAP + rv = pmap_fault(PCPU_GET(curpmap), far, fsr, idx, usermode); + if (rv == 0) { + return; + } else if (rv == EFAULT) { + + call_trapsignal(td, SIGSEGV, SEGV_MAPERR, far); + userret(td, tf); + return; + } +#endif + /* + * Now, when we handled imprecise and debug aborts, the rest of + * aborts should be really related to mapping. + * + */ + + PCPU_INC(cnt.v_trap); + +#ifdef KDB + if (kdb_active) { + kdb_reenter(); + goto out; + } +#endif + if (__predict_false((td->td_pflags & TDP_NOFAULTING) != 0)) { + /* + * Due to both processor errata and lazy TLB invalidation when + * access restrictions are removed from virtual pages, memory + * accesses that are allowed by the physical mapping layer may + * nonetheless cause one spurious page fault per virtual page. + * When the thread is executing a "no faulting" section that + * is bracketed by vm_fault_{disable,enable}_pagefaults(), + * every page fault is treated as a spurious page fault, + * unless it accesses the same virtual address as the most + * recent page fault within the same "no faulting" section. + */ + if (td->td_md.md_spurflt_addr != far || + (td->td_pflags & TDP_RESETSPUR) != 0) { + td->td_md.md_spurflt_addr = far; + td->td_pflags &= ~TDP_RESETSPUR; + + tlb_flush_local(far & ~PAGE_MASK); + return; + } + } else { + /* + * If we get a page fault while in a critical section, then + * it is most likely a fatal kernel page fault. The kernel + * is already going to panic trying to get a sleep lock to + * do the VM lookup, so just consider it a fatal trap so the + * kernel can print out a useful trap message and even get + * to the debugger. + * + * If we get a page fault while holding a non-sleepable + * lock, then it is most likely a fatal kernel page fault. + * If WITNESS is enabled, then it's going to whine about + * bogus LORs with various VM locks, so just skip to the + * fatal trap handling directly. + */ + if (td->td_critnest != 0 || + WITNESS_CHECK(WARN_SLEEPOK | WARN_GIANTOK, NULL, + "Kernel page fault") != 0) { + abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig); + return; + } + } + + /* Re-enable interrupts if they were enabled previously. */ + if (td->td_md.md_spinlock_count == 0) { + if (__predict_true(tf->tf_spsr & PSR_I) == 0) + enable_interrupts(PSR_I); + if (__predict_true(tf->tf_spsr & PSR_F) == 0) + enable_interrupts(PSR_F); + } + + p = td->td_proc; + if (usermode) { + td->td_pticks = 0; + if (td->td_ucred != p->p_ucred) + cred_update_thread(td); + } + + /* Invoke the appropriate handler, if necessary. */ + if (__predict_false(aborts[idx].func != NULL)) { + if ((aborts[idx].func)(tf, idx, fsr, far, prefetch, td, &ksig)) + goto do_trapsignal; + goto out; + } + + /* + * At this point, we're dealing with one of the following aborts: + * + * FAULT_TRAN_xx - Translation + * FAULT_PERM_xx - Permission + * + * These are the main virtual memory-related faults signalled by + * the MMU. + */ + + /* fusubailout is used by [fs]uswintr to avoid page faulting */ + pcb = td->td_pcb; + if (__predict_false(pcb->pcb_onfault == fusubailout)) { + tf->tf_r0 = EFAULT; + tf->tf_pc = (register_t)pcb->pcb_onfault; + return; + } + + /* + * QQQ: ARM has a set of unprivileged load and store instructions + * (LDRT/LDRBT/STRT/STRBT ...) which are supposed to be used + * in other than user mode and OS should recognize their + * aborts and behaved appropriately. However, there is no way + * how to do that reasonably in general unless we restrict + * the handling somehow. One way is to limit the handling for + * aborts which come from undefined mode only. + * + * Anyhow, we do not use these instructions and do not implement + * any special handling for them. + */ + + va = trunc_page(far); + if (va >= KERNBASE) { + /* + * Don't allow user-mode faults in kernel address space. + */ + if (usermode) + goto nogo; + + map = kernel_map; + } else { + /* + * This is a fault on non-kernel virtual memory. If curproc + * is NULL or curproc->p_vmspace is NULL the fault is fatal. + */ + vm = (p != NULL) ? p->p_vmspace : NULL; + if (vm == NULL) + goto nogo; + + map = &vm->vm_map; + if (!usermode && (td->td_intr_nesting_level != 0 || + pcb->pcb_onfault == NULL)) { + abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig); + return; + } + } + + ftype = (fsr & FSR_WNR) ? VM_PROT_WRITE : VM_PROT_READ; + if (prefetch) + ftype |= VM_PROT_EXECUTE; + +#ifndef ARM_NEW_PMAP + if (pmap_fault_fixup(vmspace_pmap(td->td_proc->p_vmspace), va, ftype, + usermode)) { + goto out; + } +#endif + +#ifdef INVARIANTS + onfault = pcb->pcb_onfault; + pcb->pcb_onfault = NULL; +#endif + if (map != kernel_map) { + /* + * Keep swapout from messing with us during this + * critical time. + */ + PROC_LOCK(p); + ++p->p_lock; + PROC_UNLOCK(p); + + /* Fault in the user page: */ + rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL); + + PROC_LOCK(p); + --p->p_lock; + PROC_UNLOCK(p); + } else { + /* + * Don't have to worry about process locking or stacks in the + * kernel. + */ + rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL); + } + +#ifdef INVARIANTS + pcb->pcb_onfault = onfault; +#endif + + if (__predict_true(rv == KERN_SUCCESS)) + goto out; +nogo: + if (!usermode) { + if (td->td_intr_nesting_level == 0 && + pcb->pcb_onfault != NULL) { + tf->tf_r0 = rv; + tf->tf_pc = (int)pcb->pcb_onfault; + return; + } + CTR2(KTR_TRAP, "%s: vm_fault() failed with %d", __func__, rv); + abort_fatal(tf, idx, fsr, far, prefetch, td, &ksig); + return; + } + + ksig.sig = (rv == KERN_PROTECTION_FAILURE) ? SIGBUS : SIGSEGV; + ksig.code = 0; + ksig.addr = far; + +do_trapsignal: + call_trapsignal(td, ksig.sig, ksig.code, ksig.addr); +out: + if (usermode) + userret(td, tf); +} + +/* + * abort_fatal() handles the following data aborts: + + * FAULT_DEBUG - Debug Event + * FAULT_ACCESS_xx - Acces Bit + * FAULT_EA_PREC - Precise External Abort + * FAULT_DOMAIN_xx - Domain Fault + * FAULT_EA_TRAN_xx - External Translation Abort + * FAULT_EA_IMPREC - Imprecise External Abort + * + all undefined codes for ABORT + * + * We should never see these on a properly functioning system. + * + * This function is also called by the other handlers if they + * detect a fatal problem. + * + * Note: If 'l' is NULL, we assume we're dealing with a prefetch abort. + */ +static int +abort_fatal(struct trapframe *tf, u_int idx, u_int fsr, u_int far, u_int prefetch, + struct thread *td, struct ksig *ksig) +{ + u_int usermode; + const char *mode; + const char *rw_mode; + + usermode = TRAPF_USERMODE(tf); + mode = usermode ? "user" : "kernel"; + rw_mode = fsr & FSR_WNR ? "write" : "read"; + disable_interrupts(PSR_I|PSR_F); + + if (td != NULL) { + printf("Fatal %s mode data abort: '%s' on %s\n", mode, + aborts[idx].desc, rw_mode); + printf("trapframe: %p\nFSR=%08x, FAR=", tf, fsr); + if (idx != FAULT_EA_IMPREC) + printf("%08x, ", far); + else + printf("Invalid, "); + printf("spsr=%08x\n", tf->tf_spsr); + } else { + printf("Fatal %s mode prefetch abort at 0x%08x\n", + mode, tf->tf_pc); + printf("trapframe: %p, spsr=%08x\n", tf, tf->tf_spsr); + } + + printf("r0 =%08x, r1 =%08x, r2 =%08x, r3 =%08x\n", + tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3); + printf("r4 =%08x, r5 =%08x, r6 =%08x, r7 =%08x\n", + tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7); + printf("r8 =%08x, r9 =%08x, r10=%08x, r11=%08x\n", + tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11); + printf("r12=%08x, ", tf->tf_r12); + + if (usermode) + printf("usp=%08x, ulr=%08x", + tf->tf_usr_sp, tf->tf_usr_lr); + else + printf("ssp=%08x, slr=%08x", + tf->tf_svc_sp, tf->tf_svc_lr); + printf(", pc =%08x\n\n", tf->tf_pc); + +#ifdef KDB + if (debugger_on_panic || kdb_active) + kdb_trap(fsr, 0, tf); +#endif + panic("Fatal abort"); + /*NOTREACHED*/ +} + +/* + * abort_align() handles the following data abort: + * + * FAULT_ALIGN - Alignment fault + * + * Every memory access should be correctly aligned in kernel including + * user to kernel and vice versa data copying, so we ignore pcb_onfault, + * and it's always fatal. We generate a signal in case of abort from user mode. + */ +static int +abort_align(struct trapframe *tf, u_int idx, u_int fsr, u_int far, u_int prefetch, + struct thread *td, struct ksig *ksig) +{ + u_int usermode; + + usermode = TRAPF_USERMODE(tf); + + /* + * Alignment faults are always fatal if they occur in any but user mode. + * + * XXX The old trap code handles pcb fault even for alignment traps. + * Unfortunately, we don't known why and if is this need. + */ + if (!usermode) { + if (td->td_intr_nesting_level == 0 && td != NULL && + td->td_pcb->pcb_onfault != NULL) { + printf("%s: Got alignment fault with pcb_onfault set" + ", please report this issue\n", __func__); + tf->tf_r0 = EFAULT;; + tf->tf_pc = (int)td->td_pcb->pcb_onfault; + return (0); + } + abort_fatal(tf, idx, fsr, far, prefetch, td, ksig); + } + /* Deliver a bus error signal to the process */ + ksig->code = 0; + ksig->sig = SIGBUS; + ksig->addr = far; + return (1); +} + +/* + * abort_icache() handles the following data abort: + * + * FAULT_ICACHE - Instruction cache maintenance + * + * According to manual, FAULT_ICACHE is translation fault during cache + * maintenance operation. In fact, no cache maintenance operation on + * not mapped virtual addresses should be called. As cache maintenance + * operation (except DMB, DSB, and Flush Prefetch Buffer) are priviledged, + * the abort is concider as fatal for now. However, all the matter with + * cache maintenance operation on virtual addresses could be really complex + * and fuzzy in SMP case, so maybe in future standard fault mechanism + * should be held here including vm_fault() calling. + */ +static int +abort_icache(struct trapframe *tf, u_int idx, u_int fsr, u_int far, u_int prefetch, + struct thread *td, struct ksig *ksig) +{ + abort_fatal(tf, idx, fsr, far, prefetch, td, ksig); + return(0); +} Property changes on: head/sys/arm/arm/trap-v6.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/include/armreg.h =================================================================== --- head/sys/arm/include/armreg.h (revision 276637) +++ head/sys/arm/include/armreg.h (revision 276638) @@ -1,417 +1,441 @@ /* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ /*- * Copyright (c) 1998, 2001 Ben Harris * Copyright (c) 1994-1996 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef MACHINE_ARMREG_H #define MACHINE_ARMREG_H +#include + #define INSN_SIZE 4 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ #define PSR_MODE 0x0000001f /* mode mask */ #define PSR_USR32_MODE 0x00000010 #define PSR_FIQ32_MODE 0x00000011 #define PSR_IRQ32_MODE 0x00000012 #define PSR_SVC32_MODE 0x00000013 #define PSR_MON32_MODE 0x00000016 #define PSR_ABT32_MODE 0x00000017 #define PSR_HYP32_MODE 0x0000001a #define PSR_UND32_MODE 0x0000001b #define PSR_SYS32_MODE 0x0000001f #define PSR_32_MODE 0x00000010 #define PSR_T 0x00000020 /* Instruction set bit */ #define PSR_F 0x00000040 /* FIQ disable bit */ #define PSR_I 0x00000080 /* IRQ disable bit */ #define PSR_A 0x00000100 /* Imprecise abort bit */ #define PSR_E 0x00000200 /* Data endianess bit */ #define PSR_GE 0x000f0000 /* Greater than or equal to bits */ #define PSR_J 0x01000000 /* Java bit */ #define PSR_Q 0x08000000 /* Sticky overflow bit */ #define PSR_V 0x10000000 /* Overflow bit */ #define PSR_C 0x20000000 /* Carry bit */ #define PSR_Z 0x40000000 /* Zero bit */ #define PSR_N 0x80000000 /* Negative bit */ #define PSR_FLAGS 0xf0000000 /* Flags mask. */ /* The high-order byte is always the implementor */ #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ #define CPU_ID_DEC 0x44000000 /* 'D' */ #define CPU_ID_INTEL 0x69000000 /* 'i' */ #define CPU_ID_TI 0x54000000 /* 'T' */ #define CPU_ID_FARADAY 0x66000000 /* 'f' */ /* How to decide what format the CPUID is in. */ #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) /* On recent ARMs this byte holds the architecture and variant (sub-model) */ #define CPU_ID_ARCH_MASK 0x000f0000 #define CPU_ID_ARCH_V3 0x00000000 #define CPU_ID_ARCH_V4 0x00010000 #define CPU_ID_ARCH_V4T 0x00020000 #define CPU_ID_ARCH_V5 0x00030000 #define CPU_ID_ARCH_V5T 0x00040000 #define CPU_ID_ARCH_V5TE 0x00050000 #define CPU_ID_ARCH_V5TEJ 0x00060000 #define CPU_ID_ARCH_V6 0x00070000 #define CPU_ID_CPUID_SCHEME 0x000f0000 #define CPU_ID_VARIANT_MASK 0x00f00000 /* Next three nybbles are part number */ #define CPU_ID_PARTNO_MASK 0x0000fff0 /* Intel XScale has sub fields in part number */ #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ /* And finally, the revision number. */ #define CPU_ID_REVISION_MASK 0x0000000f /* Individual CPUs are probably best IDed by everything but the revision. */ #define CPU_ID_CPU_MASK 0xfffffff0 /* ARM9 and later CPUs */ #define CPU_ID_ARM920T 0x41129200 #define CPU_ID_ARM920T_ALT 0x41009200 #define CPU_ID_ARM922T 0x41029220 #define CPU_ID_ARM926EJS 0x41069260 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ #define CPU_ID_ARM1022ES 0x4105a220 #define CPU_ID_ARM1026EJS 0x4106a260 #define CPU_ID_ARM1136JS 0x4107b360 #define CPU_ID_ARM1136JSR1 0x4117b360 #define CPU_ID_ARM1176JZS 0x410fb760 #define CPU_ID_CORTEXA5 0x410fc050 #define CPU_ID_CORTEXA7 0x410fc070 #define CPU_ID_CORTEXA8R1 0x411fc080 #define CPU_ID_CORTEXA8R2 0x412fc080 #define CPU_ID_CORTEXA8R3 0x413fc080 #define CPU_ID_CORTEXA9R1 0x411fc090 #define CPU_ID_CORTEXA9R2 0x412fc090 #define CPU_ID_CORTEXA9R3 0x413fc090 #define CPU_ID_CORTEXA15R0 0x410fc0f0 #define CPU_ID_CORTEXA15R1 0x411fc0f0 #define CPU_ID_CORTEXA15R2 0x412fc0f0 #define CPU_ID_CORTEXA15R3 0x413fc0f0 #define CPU_ID_KRAIT 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ #define CPU_ID_TI925T 0x54029250 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ #define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ #define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ /* * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. */ #ifdef SOC_MV_LOKIPLUS #define CPU_ID_MV88FR571_41 0x00000000 #else #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ #endif #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ #define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ /* Marvell's CPUIDs with ARM ID in implementor field */ #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ #define CPU_ID_FA526 0x66015260 #define CPU_ID_FA626TE 0x66056260 #define CPU_ID_80200 0x69052000 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ #define CPU_ID_PXA210 0x69052120 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ #define CPU_ID_PXA27X 0x69054110 #define CPU_ID_80321_400 0x69052420 #define CPU_ID_80321_600 0x69052430 #define CPU_ID_80321_400_B0 0x69052c20 #define CPU_ID_80321_600_B0 0x69052c30 #define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ #define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ #define CPU_ID_81342 0x69056810 #define CPU_ID_IXP425 0x690541c0 #define CPU_ID_IXP425_533 0x690541c0 #define CPU_ID_IXP425_400 0x690541d0 #define CPU_ID_IXP425_266 0x690541f0 #define CPU_ID_IXP435 0x69054040 #define CPU_ID_IXP465 0x69054200 /* CPUID registers */ #define ARM_PFR0_ARM_ISA_MASK 0x0000000f #define ARM_PFR0_THUMB_MASK 0x000000f0 #define ARM_PFR0_THUMB 0x10 #define ARM_PFR0_THUMB2 0x30 #define ARM_PFR0_JAZELLE_MASK 0x00000f00 #define ARM_PFR0_THUMBEE_MASK 0x0000f000 #define ARM_PFR1_ARMV4_MASK 0x0000000f #define ARM_PFR1_SEC_EXT_MASK 0x000000f0 #define ARM_PFR1_MICROCTRL_MASK 0x00000f00 /* * Post-ARM3 CP15 registers: * * 1 Control register * * 2 Translation Table Base * * 3 Domain Access Control * * 4 Reserved * * 5 Fault Status * * 6 Fault Address * * 7 Cache/write-buffer Control * * 8 TLB Control * * 9 Cache Lockdown * * 10 TLB Lockdown * * 11 Reserved * * 12 Reserved * * 13 Process ID (for FCSE) * * 14 Reserved * * 15 Implementation Dependent */ /* Some of the definitions below need cleaning up for V3/V4 architectures */ /* CPU control register (CP15 register 1) */ #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ #define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */ #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ #define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */ #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ #define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ #define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/ #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */ #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE /* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ /* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ /* This is an undocumented flag * used to work around a cache bug * in r0 steppings. See errata * 364296. */ /* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ /* Note: XSCale core 3 uses those for LLR DCcahce attributes */ #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ #define XSCALE_AUXCTL_MD_MASK 0x00000030 /* Xscale Core 3 only */ #define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ /* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ #define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ #define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ #define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ #define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ #define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ #define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ #define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ #define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ #define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ #define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ /* Cache type register definitions */ #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ #define CPU_CT_S (1U << 24) /* split cache */ #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ #define CPU_CT_FORMAT(x) ((x) >> 29) #define CPU_CT_CTYPE_WT 0 /* write-through */ #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ #define CPU_CT_ARMV7 0x4 /* ARM v7 Cache type definitions */ #define CPUV7_CT_CTYPE_WT (1U << 31) #define CPUV7_CT_CTYPE_WB (1 << 30) #define CPUV7_CT_CTYPE_RA (1 << 29) #define CPUV7_CT_CTYPE_WA (1 << 28) #define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ #define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ #define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ #define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) #define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) #define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) #define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) #define CACHE_ICACHE 1 #define CACHE_DCACHE 2 #define CACHE_SEP_CACHE 3 #define CACHE_UNI_CACHE 4 /* Fault status register definitions */ - -#define FAULT_TYPE_MASK 0x0f #define FAULT_USER 0x10 +#if __ARM_ARCH < 6 +#define FAULT_TYPE_MASK 0x0f #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ #define FAULT_ALIGN_0 0x01 /* Alignment */ #define FAULT_ALIGN_1 0x03 /* Alignment */ #define FAULT_TRANS_S 0x05 /* Translation -- Section */ #define FAULT_TRANS_F 0x06 /* Translation -- Flag */ #define FAULT_TRANS_P 0x07 /* Translation -- Page */ #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ #define FAULT_PERM_S 0x0d /* Permission -- Section */ #define FAULT_PERM_P 0x0f /* Permission -- Page */ #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ #define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ #define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ -/* Fault status register definitions - v6+ */ -#define FSR_STATUS_TO_IDX(fsr) (((fsr) & 0xF) | \ - (((fsr) & (1 << 10)>> (10 - 4)))) -#define FSR_LPAE (1 << 9) /* LPAE indicator */ -#define FSR_WNR (1 << 11) /* Write-not-Read access */ -#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ -#define FSR_CM (1 << 13) /* Cache maintenance fault */ +#else /* __ARM_ARCH < 6 */ +#define FAULT_ALIGN 0x001 /* Alignment Fault */ +#define FAULT_DEBUG 0x002 /* Debug Event */ +#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */ +#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */ +#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */ +#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */ +#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */ +#define FAULT_EA_PREC 0x008 /* External Abort */ +#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */ +#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */ +#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */ +#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */ +#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */ +#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */ +#define FAULT_TLB_CONFLICT 0x010 /* Permission Fault (L2) */ +#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */ +#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */ +#define FAULT_PARITY 0x019 /* Parity Error */ +#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */ +#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */ + +#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \ + ((((fsr) & (1 << 10)) >> (10 - 4)))) +#define FSR_LPAE (1 << 9) /* LPAE indicator */ +#define FSR_WNR (1 << 11) /* Write-not-Read access */ +#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ +#define FSR_CM (1 << 13) /* Cache maintenance fault */ +#endif /* !__ARM_ARCH < 6 */ /* * Address of the vector page, low and high versions. */ #ifndef __ASSEMBLER__ #define ARM_VECTORS_LOW 0x00000000U #define ARM_VECTORS_HIGH 0xffff0000U #else #define ARM_VECTORS_LOW 0 #define ARM_VECTORS_HIGH 0xffff0000 #endif /* * ARM Instructions * * 3 3 2 2 2 * 1 0 9 8 7 0 * +-------+-------------------------------------------------------+ * | cond | instruction dependant | * |c c c c| | * +-------+-------------------------------------------------------+ */ #define INSN_SIZE 4 /* Always 4 bytes */ #define INSN_COND_MASK 0xf0000000 /* Condition mask */ #define INSN_COND_AL 0xe0000000 /* Always condition */ #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ #endif /* !MACHINE_ARMREG_H */ Index: head/sys/arm/include/proc.h =================================================================== --- head/sys/arm/include/proc.h (revision 276637) +++ head/sys/arm/include/proc.h (revision 276638) @@ -1,81 +1,82 @@ /*- * Copyright (c) 1991 Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)proc.h 7.1 (Berkeley) 5/15/91 * from: FreeBSD: src/sys/i386/include/proc.h,v 1.11 2001/06/29 * $FreeBSD$ */ #ifndef _MACHINE_PROC_H_ #define _MACHINE_PROC_H_ #include struct md_utrap { utrap_entry_t *ut_precise[UT_MAX]; /* must be first */ int ut_refcnt; }; struct mdthread { int md_spinlock_count; /* (k) */ register_t md_saved_cspr; /* (k) */ + register_t md_spurflt_addr; /* (k) Spurious page fault address. */ int md_ptrace_instr; int md_ptrace_addr; register_t md_tp; void *md_ras_start; void *md_ras_end; }; struct mdproc { struct md_utrap *md_utrap; void *md_sigtramp; }; #ifdef __ARM_EABI__ #define KINFO_PROC_SIZE 816 #else #define KINFO_PROC_SIZE 792 #endif #define MAXARGS 8 struct syscall_args { u_int code; struct sysent *callp; register_t args[MAXARGS]; int narg; u_int nap; #ifndef __ARM_EABI__ u_int32_t insn; #endif }; #endif /* !_MACHINE_PROC_H_ */ Index: head/sys/conf/files.arm =================================================================== --- head/sys/conf/files.arm (revision 276637) +++ head/sys/conf/files.arm (revision 276638) @@ -1,105 +1,106 @@ # $FreeBSD$ arm/arm/autoconf.c standard arm/arm/bcopy_page.S standard arm/arm/bcopyinout.S standard arm/arm/blockio.S standard arm/arm/bootconfig.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/busdma_machdep.c optional !armv6 arm/arm/busdma_machdep-v6.c optional armv6 arm/arm/copystr.S standard arm/arm/cpufunc.c standard arm/arm/cpufunc_asm.S standard arm/arm/cpufunc_asm_armv4.S standard arm/arm/cpuinfo.c standard arm/arm/cpu_asm-v6.S optional armv6 arm/arm/db_disasm.c optional ddb arm/arm/db_interface.c optional ddb arm/arm/db_trace.c optional ddb arm/arm/devmap.c standard arm/arm/disassem.c optional ddb arm/arm/dump_machdep.c standard arm/arm/elf_machdep.c standard arm/arm/elf_note.S standard arm/arm/exception.S standard arm/arm/fiq.c standard arm/arm/fiq_subr.S standard arm/arm/fusu.S standard arm/arm/gdb_machdep.c optional gdb arm/arm/identcpu.c standard arm/arm/in_cksum.c optional inet | inet6 arm/arm/in_cksum_arm.S optional inet | inet6 arm/arm/intr.c standard arm/arm/locore.S standard no-obj arm/arm/machdep.c standard arm/arm/mem.c optional mem arm/arm/minidump_machdep.c optional mem arm/arm/mp_machdep.c optional smp arm/arm/nexus.c standard arm/arm/physmem.c standard arm/arm/pl190.c optional pl190 arm/arm/pl310.c optional pl310 arm/arm/platform.c optional platform arm/arm/platform_if.m optional platform arm/arm/pmap.c optional !armv6 arm/arm/pmap-v6.c optional armv6 arm/arm/sc_machdep.c optional sc arm/arm/setcpsr.S standard arm/arm/setstack.s standard arm/arm/stack_machdep.c optional ddb | stack arm/arm/stdatomic.c standard \ compile-with "${NORMAL_C:N-Wmissing-prototypes}" arm/arm/support.S standard arm/arm/swtch.S standard arm/arm/sys_machdep.c standard arm/arm/syscall.c standard -arm/arm/trap.c standard +arm/arm/trap.c optional !armv6 +arm/arm/trap-v6.c optional armv6 arm/arm/uio_machdep.c standard arm/arm/undefined.c standard arm/arm/vm_machdep.c standard arm/arm/vfp.c standard board_id.h standard \ dependency "$S/arm/conf/genboardid.awk $S/arm/conf/mach-types" \ compile-with "${AWK} -f $S/arm/conf/genboardid.awk $S/arm/conf/mach-types > board_id.h" \ no-obj no-implicit-rule before-depend \ clean "board_id.h" cddl/compat/opensolaris/kern/opensolaris_atomic.c optional zfs compile-with "${ZFS_C}" crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb dev/fb/fb.c optional sc dev/fdt/fdt_arm_platform.c optional platform fdt dev/hwpmc/hwpmc_arm.c optional hwpmc dev/kbd/kbd.c optional sc | vt dev/syscons/scgfbrndr.c optional sc dev/syscons/scterm-teken.c optional sc dev/syscons/scvtb.c optional sc dev/uart/uart_cpu_fdt.c optional uart fdt font.h optional sc \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" kern/subr_busdma_bufalloc.c standard kern/subr_dummy_vdso_tc.c standard kern/subr_sfbuf.c standard libkern/arm/aeabi_unwind.c standard libkern/arm/divsi3.S standard libkern/arm/ffs.S standard libkern/arm/ldivmod.S standard libkern/arm/ldivmod_helper.c standard libkern/arm/memcpy.S standard libkern/arm/memset.S standard libkern/arm/muldi3.c standard libkern/ashldi3.c standard libkern/ashrdi3.c standard libkern/divdi3.c standard libkern/ffsl.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/lshrdi3.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard