Index: head/sys/amd64/amd64/apic_vector.S =================================================================== --- head/sys/amd64/amd64/apic_vector.S (revision 27516) +++ head/sys/amd64/amd64/apic_vector.S (revision 27517) @@ -1,431 +1,415 @@ /* * from: vector.s, 386BSD 0.1 unknown origin - * $Id: apic_vector.s,v 1.7 1997/07/15 02:49:21 fsmp Exp $ + * $Id: apic_vector.s,v 1.12 1997/07/18 19:47:13 smp Exp smp $ */ -#include /** TEST_CPUSTOP */ +#include /** various counters */ +#include "i386/isa/intr_machdep.h" /* convert an absolute IRQ# into a bitmask */ #define IRQ_BIT(irq_num) (1 << (irq_num)) /* make an index into the IO APIC from the IRQ# */ #define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2)) /* * 'lazy masking' code suggested by Bruce Evans */ #define MAYBE_MASK_IRQ(irq_num) \ testl $IRQ_BIT(irq_num),iactive ; /* lazy masking */ \ je 1f ; /* NOT currently active */ \ orl $IRQ_BIT(irq_num),_imen ; /* set the mask bit */ \ movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ orl $IOART_INTMASK,%eax ; /* set the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ movl $0, lapic_eoi ; \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ popl %ds ; \ popal ; \ addl $4+4,%esp ; \ iret ; \ ; \ ALIGN_TEXT ; \ 1: ; \ orl $IRQ_BIT(irq_num),iactive #define MAYBE_UNMASK_IRQ(irq_num) \ cli ; /* must unmask _imen and icu atomically */ \ andl $~IRQ_BIT(irq_num),iactive ; \ testl $IRQ_BIT(irq_num),_imen ; \ je 2f ; \ andl $~IRQ_BIT(irq_num),_imen ; /* clear mask bit */ \ movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ andl $~IOART_INTMASK,%eax ; /* clear the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ 2: ; \ sti ; /* XXX _doreti repeats the cli/sti */ /* * Macros for interrupt interrupt entry, call to handler, and exit. */ #define FAST_INTR(irq_num, vec_name) \ .text ; \ SUPERALIGN_TEXT ; \ IDTVEC(vec_name) ; \ pushl %eax ; /* save only call-used registers */ \ pushl %ecx ; \ pushl %edx ; \ pushl %ds ; \ MAYBE_PUSHL_ES ; \ movl $KDSEL,%eax ; \ movl %ax,%ds ; \ MAYBE_MOVW_AX_ES ; \ FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \ GET_MPLOCK ; /* SMP Spin lock */ \ pushl _intr_unit + (irq_num) * 4 ; \ call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \ movl $0, lapic_eoi ; \ addl $4,%esp ; \ incl _cnt+V_INTR ; /* book-keeping can wait */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ incl (%eax) ; \ movl _cpl,%eax ; /* unmasking pending HWIs or SWIs? */ \ notl %eax ; \ andl _ipending,%eax ; \ jne 2f ; /* yes, maybe handle them */ \ 1: ; \ MEXITCOUNT ; \ REL_MPLOCK ; /* SMP release global lock */ \ MAYBE_POPL_ES ; \ popl %ds ; \ popl %edx ; \ popl %ecx ; \ popl %eax ; \ iret ; \ ; \ ALIGN_TEXT ; \ 2: ; \ cmpb $3,_intr_nesting_level ; /* enough stack? */ \ jae 1b ; /* no, return */ \ movl _cpl,%eax ; \ /* XXX next line is probably unnecessary now. */ \ movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \ incb _intr_nesting_level ; /* ... really limit it ... */ \ sti ; /* to do this as early as possible */ \ MAYBE_POPL_ES ; /* discard most of thin frame ... */ \ popl %ecx ; /* ... original %ds ... */ \ popl %edx ; \ xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \ pushal ; /* build fat frame (grrr) ... */ \ pushl %ecx ; /* ... actually %ds ... */ \ pushl %es ; \ movl $KDSEL,%eax ; \ movl %ax,%es ; \ movl (2+8+0)*4(%esp),%ecx ; /* %ecx from thin frame ... */ \ movl %ecx,(2+6)*4(%esp) ; /* ... to fat frame ... */ \ movl (2+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \ pushl %eax ; \ subl $4,%esp ; /* junk for unit number */ \ MEXITCOUNT ; \ jmp _doreti #define INTR(irq_num, vec_name) \ .text ; \ SUPERALIGN_TEXT ; \ IDTVEC(vec_name) ; \ pushl $0 ; /* dummy error code */ \ pushl $0 ; /* dummy trap type */ \ pushal ; \ pushl %ds ; /* save data and extra segments ... */ \ pushl %es ; \ movl $KDSEL,%eax ; /* ... and reload with kernel's ... */ \ movl %ax,%ds ; /* ... early for obsolete reasons */ \ movl %ax,%es ; \ GET_MPLOCK ; /* SMP Spin lock */ \ MAYBE_MASK_IRQ(irq_num) ; \ movl $0, lapic_eoi ; \ movl _cpl,%eax ; \ testl $IRQ_BIT(irq_num), %eax ; \ jne 3f ; \ incb _intr_nesting_level ; \ __CONCAT(Xresume,irq_num): ; \ FAKE_MCOUNT(12*4(%esp)) ; /* XXX late to avoid dbl cnt */ \ incl _cnt+V_INTR ; /* tally interrupts */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ incl (%eax) ; \ movl _cpl,%eax ; \ pushl %eax ; \ pushl _intr_unit + (irq_num) * 4 ; \ orl _intr_mask + (irq_num) * 4,%eax ; \ movl %eax,_cpl ; \ sti ; \ call *_intr_handler + (irq_num) * 4 ; \ MAYBE_UNMASK_IRQ(irq_num) ; \ MEXITCOUNT ; \ jmp _doreti ; \ ; \ ALIGN_TEXT ; \ 3: ; \ /* XXX skip mcounting here to avoid double count */ \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ popl %ds ; \ popal ; \ addl $4+4,%esp ; \ iret /* * Handle "spurious INTerrupts". * Notes: * This is different than the "spurious INTerrupt" generated by an * 8259 PIC for missing INTs. See the APIC documentation for details. * This routine should NOT do an 'EOI' cycle. */ .text SUPERALIGN_TEXT .globl _Xspuriousint _Xspuriousint: #ifdef COUNT_SPURIOUS_INTS ss incl _sihits #endif /* No EOI cycle used here */ iret /* * Handle TLB shootdowns. */ .text SUPERALIGN_TEXT .globl _Xinvltlb _Xinvltlb: pushl %eax #ifdef COUNT_XINVLTLB_HITS ss movl _cpuid, %eax ss incl _xhits(,%eax,4) #endif /* COUNT_XINVLTLB_HITS */ movl %cr3, %eax /* invalidate the TLB */ movl %eax, %cr3 ss /* stack segment, avoid %ds load */ movl $0, lapic_eoi /* End Of Interrupt to APIC */ popl %eax iret -#ifdef TEST_CPUSTOP - -#include "i386/isa/intr_machdep.h" - /* * Executed by a CPU when it receives an Xcpustop IPI from another CPU, * * - Signals its receipt. * - Waits for permission to restart. * - Signals its restart. */ .text SUPERALIGN_TEXT .globl _Xcpustop _Xcpustop: pushl %eax pushl %ds /* save current data segment */ movl $KDSEL, %eax movl %ax, %ds /* use KERNEL data segment */ movl _cpuid, %eax #ifdef COUNT_CSHITS incl _cshits(,%eax,4) #endif /* COUNT_CSHITS */ ASMPOSTCODE_HI(0x1) lock btsl %eax, _stopped_cpus /* stopped_cpus |= (1< #include #include #include #include #include #include #include #ifdef SMP #include -#include /** TEST_CPUSTOP */ +#include /** CPUSTOP_ON_DDBBREAK */ #endif #include #include #include #include #include static jmp_buf *db_nofault = 0; extern jmp_buf db_jmpbuf; extern void gdb_handle_exception __P((db_regs_t *, int, int)); db_regs_t ddb_regs; static jmp_buf db_global_jmpbuf; static int db_global_jmpbuf_valid; #ifdef __GNUC__ #define rss() ({u_short ss; __asm __volatile("movl %%ss,%0" : "=r" (ss)); ss;}) #endif /* * kdb_trap - field a TRACE or BPT trap */ int kdb_trap(type, code, regs) int type, code; register struct i386_saved_state *regs; { int ddb_mode = !(boothowto & RB_GDB); /* * XXX try to do nothing if the console is in graphics mode. * Handle trace traps (and hardware breakpoints...) by ignoring * them except for forgetting about them. Return 0 for other * traps to say that we haven't done anything. The trap handler * will usually panic. We should handle breakpoint traps for * our breakpoints by disarming our breakpoints and fixing up * %eip. */ if (cons_unavail && ddb_mode) { if (type == T_TRCTRAP) { regs->tf_eflags &= ~PSL_T; return (1); } return (0); } switch (type) { case T_BPTFLT: /* breakpoint */ case T_TRCTRAP: /* debug exception */ break; default: /* * XXX this is almost useless now. In most cases, * trap_fatal() has already printed a much more verbose * message. However, it is dangerous to print things in * trap_fatal() - printf() might be reentered and trap. * The debugger should be given control first. */ if (ddb_mode) db_printf("kernel: type %d trap, code=%x\n", type, code); if (db_nofault) { jmp_buf *no_fault = db_nofault; db_nofault = 0; longjmp(*no_fault, 1); } } /* * This handles unexpected traps in ddb commands, including calls to * non-ddb functions. db_nofault only applies to memory accesses by * internal ddb commands. */ if (db_global_jmpbuf_valid) longjmp(db_global_jmpbuf, 1); /* * XXX We really should switch to a local stack here. */ ddb_regs = *regs; /* * If in kernel mode, esp and ss are not saved, so dummy them up. */ if (ISPL(regs->tf_cs) == 0) { ddb_regs.tf_esp = (int)®s->tf_esp; ddb_regs.tf_ss = rss(); } cnpollc(TRUE); -#if defined(SMP) && defined(TEST_CPUSTOP) - /* XXX FIXME: we stop all CPUs except ourselves (obviously) */ +#ifdef SMP +#ifdef CPUSTOP_ON_DDBBREAK + +#if defined(VERBOSE_CPUSTOP_ON_DDBBREAK) + db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, other_cpus); +#endif /* VERBOSE_CPUSTOP_ON_DDBBREAK */ + + /* We stop all CPUs except ourselves (obviously) */ stop_cpus(other_cpus); -#endif /** SMP && TEST_CPUSTOP */ +#if defined(VERBOSE_CPUSTOP_ON_DDBBREAK) + db_printf(" stopped\n"); +#endif /* VERBOSE_CPUSTOP_ON_DDBBREAK */ + +#endif /* CPUSTOP_ON_DDBBREAK */ +#endif /* SMP */ + (void) setjmp(db_global_jmpbuf); db_global_jmpbuf_valid = TRUE; if (ddb_mode) db_trap(type, code); else gdb_handle_exception(&ddb_regs, type, code); db_global_jmpbuf_valid = FALSE; -#if defined(SMP) && defined(TEST_CPUSTOP) - /* XXX FIXME: restart all the CPUs we previously stopped */ +#ifdef SMP +#ifdef CPUSTOP_ON_DDBBREAK + +#if defined(VERBOSE_CPUSTOP_ON_DDBBREAK) + db_printf("\nCPU%d restarting CPUs: 0x%08x\n", cpuid, stopped_cpus); +#endif /* VERBOSE_CPUSTOP_ON_DDBBREAK */ + + /* Restart all the CPUs we previously stopped */ if (stopped_cpus != other_cpus) { db_printf("whoa, other_cpus: 0x%08x, stopped_cpus: 0x%08x\n", - other_cpus, stopped_cpus); - cngetc(); + other_cpus, stopped_cpus); + panic("stop_cpus() failed"); } restart_cpus(stopped_cpus); -#endif /** SMP && TEST_CPUSTOP */ + +#if defined(VERBOSE_CPUSTOP_ON_DDBBREAK) + db_printf(" restarted\n"); +#endif /* VERBOSE_CPUSTOP_ON_DDBBREAK */ + +#endif /* CPUSTOP_ON_DDBBREAK */ +#endif /* SMP */ cnpollc(FALSE); regs->tf_eip = ddb_regs.tf_eip; regs->tf_eflags = ddb_regs.tf_eflags; regs->tf_eax = ddb_regs.tf_eax; regs->tf_ecx = ddb_regs.tf_ecx; regs->tf_edx = ddb_regs.tf_edx; regs->tf_ebx = ddb_regs.tf_ebx; /* * If in user mode, the saved ESP and SS were valid, restore them. */ if (ISPL(regs->tf_cs)) { regs->tf_esp = ddb_regs.tf_esp; regs->tf_ss = ddb_regs.tf_ss & 0xffff; } regs->tf_ebp = ddb_regs.tf_ebp; regs->tf_esi = ddb_regs.tf_esi; regs->tf_edi = ddb_regs.tf_edi; regs->tf_es = ddb_regs.tf_es & 0xffff; regs->tf_cs = ddb_regs.tf_cs & 0xffff; regs->tf_ds = ddb_regs.tf_ds & 0xffff; return (1); } /* * Read bytes from kernel address space for debugger. */ void db_read_bytes(addr, size, data) vm_offset_t addr; register int size; register char *data; { register char *src; db_nofault = &db_jmpbuf; src = (char *)addr; while (--size >= 0) *data++ = *src++; db_nofault = 0; } /* * Write bytes to kernel address space for debugger. */ void db_write_bytes(addr, size, data) vm_offset_t addr; register int size; register char *data; { register char *dst; unsigned *ptep0 = NULL; unsigned oldmap0 = 0; vm_offset_t addr1; unsigned *ptep1 = NULL; unsigned oldmap1 = 0; db_nofault = &db_jmpbuf; if (addr >= VM_MIN_KERNEL_ADDRESS && addr <= round_page((vm_offset_t)&etext)) { ptep0 = pmap_pte(kernel_pmap, addr); oldmap0 = *ptep0; *ptep0 |= PG_RW; addr1 = trunc_page(addr + size - 1); /* Map another page if the data crosses a page boundary. */ if (trunc_page(addr) != addr1) { ptep1 = pmap_pte(kernel_pmap, addr1); oldmap1 = *ptep1; *ptep1 |= PG_RW; } invltlb(); } dst = (char *)addr; while (--size >= 0) *dst++ = *data++; db_nofault = 0; if (ptep0) { *ptep0 = oldmap0; if (ptep1) *ptep1 = oldmap1; invltlb(); } } /* * XXX * Move this to machdep.c and allow it to be called if any debugger is * installed. */ void Debugger(msg) const char *msg; { static volatile u_char in_Debugger; /* * XXX * Do nothing if the console is in graphics mode. This is * OK if the call is for the debugger hotkey but not if the call * is a weak form of panicing. */ if (cons_unavail && !(boothowto & RB_GDB)) return; if (!in_Debugger) { in_Debugger = 1; db_printf("Debugger(\"%s\")\n", msg); breakpoint(); in_Debugger = 0; } } Index: head/sys/amd64/amd64/mp_machdep.c =================================================================== --- head/sys/amd64/amd64/mp_machdep.c (revision 27516) +++ head/sys/amd64/amd64/mp_machdep.c (revision 27517) @@ -1,1834 +1,1803 @@ /* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: mp_machdep.c,v 1.28 1997/07/17 19:44:56 dyson Exp $ + * $Id: mp_machdep.c,v 1.16 1997/07/18 19:45:41 smp Exp smp $ */ #include "opt_smp.h" #include /* for KERNBASE */ #include #include #include #include #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include #include #include #include #include #include #include -#include /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP _TEST1 */ +#include /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ #include #include #include /* cngetc() */ #if defined(APIC_IO) #include /* setidt() */ #include /* IPIs */ #include /* IPIs */ #endif /* APIC_IO */ #define WARMBOOT_TARGET 0 #define WARMBOOT_OFF (KERNBASE + 0x0467) #define WARMBOOT_SEG (KERNBASE + 0x0469) #define BIOS_BASE (0xf0000) #define BIOS_SIZE (0x10000) #define BIOS_COUNT (BIOS_SIZE/4) #define CMOS_REG (0x70) #define CMOS_DATA (0x71) #define BIOS_RESET (0x0f) #define BIOS_WARM (0x0a) #define PROCENTRY_FLAG_EN 0x01 #define PROCENTRY_FLAG_BP 0x02 #define IOAPICENTRY_FLAG_EN 0x01 /* MP Floating Pointer Structure */ typedef struct MPFPS { char signature[4]; void *pap; u_char length; u_char spec_rev; u_char checksum; u_char mpfb1; u_char mpfb2; u_char mpfb3; u_char mpfb4; u_char mpfb5; } *mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { char signature[4]; u_short base_table_length; u_char spec_rev; u_char checksum; u_char oem_id[8]; u_char product_id[12]; void *oem_table_pointer; u_short oem_table_size; u_short entry_count; void *apic_address; u_short extended_table_length; u_char extended_table_checksum; u_char reserved; } *mpcth_t; typedef struct PROCENTRY { u_char type; u_char apic_id; u_char apic_version; u_char cpu_flags; u_long cpu_signature; u_long feature_flags; u_long reserved1; u_long reserved2; } *proc_entry_ptr; typedef struct BUSENTRY { u_char type; u_char bus_id; char bus_type[6]; } *bus_entry_ptr; typedef struct IOAPICENTRY { u_char type; u_char apic_id; u_char apic_version; u_char apic_flags; void *apic_address; } *io_apic_entry_ptr; typedef struct INTENTRY { u_char type; u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } *int_entry_ptr; /* descriptions of MP basetable entries */ typedef struct BASETABLE_ENTRY { u_char type; u_char length; char name[16]; } basetable_entry; /* * this code MUST be enabled here and in mpboot.s. * it follows the very early stages of AP boot by placing values in CMOS ram. * it NORMALLY will never be needed and thus the primitive method for enabling. * #define CHECK_POINTS */ #if defined(CHECK_POINTS) #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) #define CHECK_INIT(D); \ CHECK_WRITE(0x34, (D)); \ CHECK_WRITE(0x35, (D)); \ CHECK_WRITE(0x36, (D)); \ CHECK_WRITE(0x37, (D)); \ CHECK_WRITE(0x38, (D)); \ CHECK_WRITE(0x39, (D)); #define CHECK_PRINT(S); \ printf("%s: %d, %d, %d, %d, %d, %d\n", \ (S), \ CHECK_READ(0x34), \ CHECK_READ(0x35), \ CHECK_READ(0x36), \ CHECK_READ(0x37), \ CHECK_READ(0x38), \ CHECK_READ(0x39)); #else /* CHECK_POINTS */ #define CHECK_INIT(D) #define CHECK_PRINT(S) #endif /* CHECK_POINTS */ /* * Values to send to the POST hardware. */ #define MP_BOOTADDRESS_POST 0x10 #define MP_PROBE_POST 0x11 #define MP_START_POST 0x12 #define MP_ANNOUNCE_POST 0x13 #define MPTABLE_PASS1_POST 0x14 #define MPTABLE_PASS2_POST 0x15 #define MP_ENABLE_POST 0x16 #define START_ALL_APS_POST 0x17 #define INSTALL_AP_TRAMP_POST 0x18 #define START_AP_POST 0x19 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ int current_postcode; /** XXX FIXME: what system files declare these??? */ extern struct region_descriptor r_gdt, r_idt; int mp_ncpus; /* # of CPUs, including BSP */ int mp_naps; /* # of Applications processors */ int mp_nbusses; /* # of busses */ int mp_napics; /* # of IO APICs */ int boot_cpu_id; /* designated BSP */ vm_offset_t cpu_apic_address; vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ u_int32_t cpu_apic_versions[NCPU]; u_int32_t io_apic_versions[NAPIC]; /* * APIC ID logical/physical mapping structures. * We oversize these to simplify boot-time config. */ int cpu_num_to_apic_id[NAPICID]; int io_num_to_apic_id[NAPICID]; int apic_id_to_logical[NAPICID]; /* Bitmap of all available CPUs */ u_int all_cpus; /* Boot of AP uses this PTD */ u_int *bootPTD; /* Hotwire a 0->4MB V==P mapping */ extern pt_entry_t KPTphys; /* Virtual address of per-cpu common_tss */ extern struct i386tss common_tss; /* * Local data and functions. */ static int mp_capable; static u_int boot_address; static u_int base_memory; static int picmode; /* 0: virtual wire mode, 1: PIC mode */ static mpfps_t mpfps; static int search_for_sig(u_int32_t target, int count); static void mp_enable(u_int boot_addr); static int mptable_pass1(void); static int mptable_pass2(void); static void default_mp_table(int type); static int start_all_aps(u_int boot_addr); static void install_ap_tramp(u_int boot_addr); static int start_ap(int logicalCpu, u_int boot_addr); /* * Calculate usable address in base memory for AP trampoline code. */ u_int mp_bootaddress(u_int basemem) { POSTCODE(MP_BOOTADDRESS_POST); base_memory = basemem * 1024; /* convert to bytes */ boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ if ((base_memory - boot_address) < bootMP_size) boot_address -= 4096; /* not enough, lower by 4k */ return boot_address; } /* * Look for an Intel MP spec table (ie, SMP capable hardware). */ int mp_probe(void) { int x; u_long segment; u_int32_t target; POSTCODE(MP_PROBE_POST); /* see if EBDA exists */ if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { /* search first 1K of EBDA */ target = (u_int32_t) (segment << 4); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } else { /* last 1K of base memory, effective 'top of base' passed in */ target = (u_int32_t) (base_memory - 0x400); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } /* search the BIOS */ target = (u_int32_t) BIOS_BASE; if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) goto found; /* nothing found */ mpfps = (mpfps_t)0; mp_capable = 0; return 0; found: /* calculate needed resources */ mpfps = (mpfps_t)x; if (mptable_pass1()) panic("you must reconfigure your kernel"); /* flag fact that we are running multiple processors */ mp_capable = 1; return 1; } /* * Startup the SMP processors. */ void mp_start(void) { POSTCODE(MP_START_POST); /* look for MP capable motherboard */ if (mp_capable) mp_enable(boot_address); else panic("MP hardware not found!"); } /* * Print various information about the SMP system hardware and setup. */ void mp_announce(void) { int x; POSTCODE(MP_ANNOUNCE_POST); printf("FreeBSD/SMP: Multiprocessor motherboard\n"); printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); printf(", version: 0x%08x", cpu_apic_versions[0]); printf(", at 0x%08x\n", cpu_apic_address); for (x = 1; x <= mp_naps; ++x) { printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); printf(", version: 0x%08x", cpu_apic_versions[x]); printf(", at 0x%08x\n", cpu_apic_address); } #if defined(APIC_IO) for (x = 0; x < mp_napics; ++x) { printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); printf(", version: 0x%08x", io_apic_versions[x]); printf(", at 0x%08x\n", io_apic_address[x]); } #else printf(" Warning: APIC I/O disabled\n"); #endif /* APIC_IO */ } /* * AP cpu's call this to sync up protected mode. */ void init_secondary(void) { int gsel_tss, slot; r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; r_gdt.rd_base = (int) gdt; lgdt(&r_gdt); /* does magic intra-segment return */ lidt(&r_idt); lldt(_default_ldt); slot = NGDT + cpuid; gsel_tss = GSEL(slot, SEL_KPL); gdt[slot].sd.sd_type = SDT_SYS386TSS; common_tss.tss_esp0 = 0; /* not used until after switch */ common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); common_tss.tss_ioopt = (sizeof common_tss) << 16; ltr(gsel_tss); load_cr0(0x8005003b); /* XXX! */ PTD[0] = 0; pmap_set_opt((unsigned *)PTD); invltlb(); } #if defined(APIC_IO) /* * Final configuration of the BSP's local APIC: * - disable 'pic mode'. * - disable 'virtual wire mode'. * - enable NMI. */ void bsp_apic_configure(void) { u_char byte; u_int32_t temp; /* leave 'pic mode' if necessary */ if (picmode) { outb(0x22, 0x70); /* select IMCR */ byte = inb(0x23); /* current contents */ byte |= 0x01; /* mask external INTR */ outb(0x23, byte); /* disconnect 8259s/NMI */ } /* mask lint0 (the 8259 'virtual wire' connection) */ temp = lapic.lvt_lint0; temp |= APIC_LVT_M; /* set the mask */ lapic.lvt_lint0 = temp; /* setup lint1 to handle NMI */ temp = lapic.lvt_lint1; temp &= ~APIC_LVT_M; /* clear the mask */ lapic.lvt_lint1 = temp; if (bootverbose) apic_dump(); } #endif /* APIC_IO */ /******************************************************************* * local functions and data */ /* * start the SMP system */ static void mp_enable(u_int boot_addr) { int x; #if defined(APIC_IO) int apic; u_int ux; #endif /* APIC_IO */ POSTCODE(MP_ENABLE_POST); /* turn on 4MB of V == P addressing so we can get to MP table */ *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); invltlb(); /* examine the MP table for needed info, uses physical addresses */ x = mptable_pass2(); *(int *)PTD = 0; invltlb(); /* can't process default configs till the CPU APIC is pmapped */ if (x) default_mp_table(x); #if defined(APIC_IO) /* fill the LOGICAL io_apic_versions table */ for (apic = 0; apic < mp_napics; ++apic) { ux = io_apic_read(apic, IOAPIC_VER); io_apic_versions[apic] = ux; } /* program each IO APIC in the system */ for (apic = 0; apic < mp_napics; ++apic) if (io_apic_setup(apic) < 0) panic("IO APIC setup failure"); /* install a 'Spurious INTerrupt' vector */ setidt(XSPURIOUSINT_OFFSET, Xspuriousint, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); /* install an inter-CPU IPI for TLB invalidation */ setidt(XINVLTLB_OFFSET, Xinvltlb, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#if defined(TEST_CPUSTOP) /* install an inter-CPU IPI for CPU stop/restart */ setidt(XCPUSTOP_OFFSET, Xcpustop, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#endif /** TEST_CPUSTOP */ #if defined(TEST_TEST1) - /* install a 'Spurious INTerrupt' vector */ + /* install a "fake hardware INTerrupt" vector */ setidt(XTEST1_OFFSET, Xtest1, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /** TEST_TEST1 */ #endif /* APIC_IO */ /* start each Application Processor */ start_all_aps(boot_addr); /* * The init process might be started on a different CPU now, * and the boot CPU might not call prepare_usermode to get * cr0 correctly configured. Thus we initialize cr0 here. */ load_cr0(rcr0() | CR0_WP | CR0_AM); } /* * look for the MP spec signature */ /* string defined by the Intel MP Spec as identifying the MP table */ #define MP_SIG 0x5f504d5f /* _MP_ */ #define NEXT(X) ((X) += 4) static int search_for_sig(u_int32_t target, int count) { int x; u_int32_t *addr = (u_int32_t *) (KERNBASE + target); for (x = 0; x < count; NEXT(x)) if (addr[x] == MP_SIG) /* make array index a byte index */ return (target + (x * sizeof(u_int32_t))); return -1; } static basetable_entry basetable_entry_types[] = { {0, 20, "Processor"}, {1, 8, "Bus"}, {2, 8, "I/O APIC"}, {3, 8, "I/O INT"}, {4, 8, "Local INT"} }; typedef struct BUSDATA { u_char bus_id; enum busTypes bus_type; } bus_datum; typedef struct INTDATA { u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } io_int, local_int; typedef struct BUSTYPENAME { u_char type; char name[7]; } bus_type_name; static bus_type_name bus_type_table[] = { {CBUS, "CBUS"}, {CBUSII, "CBUSII"}, {EISA, "EISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {ISA, "ISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {PCI, "PCI"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {XPRESS, "XPRESS"}, {UNKNOWN_BUSTYPE, "---"} }; /* from MP spec v1.4, table 5-1 */ static int default_data[7][5] = { /* nbus, id0, type0, id1, type1 */ {1, 0, ISA, 255, 255}, {1, 0, EISA, 255, 255}, {1, 0, EISA, 255, 255}, {0, 255, 255, 255, 255},/* MCA not supported */ {2, 0, ISA, 1, PCI}, {2, 0, EISA, 1, PCI}, {0, 255, 255, 255, 255} /* MCA not supported */ }; /* the bus data */ bus_datum bus_data[NBUS]; /* the IO INT data, one entry per possible APIC INTerrupt */ io_int io_apic_ints[NINTR]; static int nintrs; static void fix_mp_table __P((void)); static int processor_entry __P((proc_entry_ptr entry, int cpu)); static int bus_entry __P((bus_entry_ptr entry, int bus)); static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); static int int_entry __P((int_entry_ptr entry, int intr)); static int lookup_bus_type __P((char *name)); /* * 1st pass on motherboard's Intel MP specification table. * * initializes: * mp_ncpus = 1 * * determines: * cpu_apic_address (common to all CPUs) * io_apic_address[N] * mp_naps * mp_nbusses * mp_napics * nintrs */ static int mptable_pass1(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int mustpanic; POSTCODE(MPTABLE_PASS1_POST); mustpanic = 0; /* clear various tables */ for (x = 0; x < NAPICID; ++x) { io_apic_address[x] = ~0; /* IO APIC address table */ } /* init everything to empty */ mp_naps = 0; mp_nbusses = 0; mp_napics = 0; nintrs = 0; /* check for use of 'default' configuration */ if (mpfps->mpfb1 != 0) { /* use default addresses */ cpu_apic_address = DEFAULT_APIC_BASE; io_apic_address[0] = DEFAULT_IO_APIC_BASE; /* fill in with defaults */ mp_naps = 2; /* includes BSP */ mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; #if defined(APIC_IO) mp_napics = 1; nintrs = 16; #endif /* APIC_IO */ } else { if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); cpu_apic_address = (vm_offset_t) cth->apic_address; /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; while (count--) { switch (type = *(u_char *) position) { case 0: /* processor_entry */ if (((proc_entry_ptr)position)->cpu_flags & PROCENTRY_FLAG_EN) ++mp_naps; break; case 1: /* bus_entry */ ++mp_nbusses; break; case 2: /* io_apic_entry */ if (((io_apic_entry_ptr)position)->apic_flags & IOAPICENTRY_FLAG_EN) io_apic_address[mp_napics++] = (vm_offset_t)((io_apic_entry_ptr) position)->apic_address; break; case 3: /* int_entry */ ++nintrs; break; case 4: /* int_entry */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char*)position += basetable_entry_types[type].length; } } /* qualify the numbers */ if (mp_naps > NCPU) printf("Warning: only using %d of %d available CPUs!\n", NCPU, mp_naps); #if 0 /** XXX we consider this legal now (but should we?) */ mustpanic = 1; #endif if (mp_nbusses > NBUS) { printf("found %d busses, increase NBUS\n", mp_nbusses); mustpanic = 1; } if (mp_napics > NAPIC) { printf("found %d apics, increase NAPIC\n", mp_napics); mustpanic = 1; } if (nintrs > NINTR) { printf("found %d intrs, increase NINTR\n", nintrs); mustpanic = 1; } /* * Count the BSP. * This is also used as a counter while starting the APs. */ mp_ncpus = 1; --mp_naps; /* subtract the BSP */ return mustpanic; } /* * 2nd pass on motherboard's Intel MP specification table. * * sets: * boot_cpu_id * ID_TO_IO(N), phy APIC ID to log CPU/IO table * CPU_TO_ID(N), logical CPU to APIC ID table * IO_TO_ID(N), logical IO to APIC ID table * bus_data[N] * io_apic_ints[N] */ static int mptable_pass2(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int apic, bus, cpu, intr; POSTCODE(MPTABLE_PASS2_POST); /* clear various tables */ for (x = 0; x < NAPICID; ++x) { ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ } /* clear bus data table */ for (x = 0; x < NBUS; ++x) bus_data[x].bus_id = 0xff; /* clear IO APIC INT table */ for (x = 0; x < NINTR; ++x) io_apic_ints[x].int_type = 0xff; /* setup the cpu/apic mapping arrays */ boot_cpu_id = -1; /* record whether PIC or virtual-wire mode */ picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; /* check for use of 'default' configuration */ #if defined(TEST_DEFAULT_CONFIG) return TEST_DEFAULT_CONFIG; #else if (mpfps->mpfb1 != 0) return mpfps->mpfb1; /* return default configuration type */ #endif /* TEST_DEFAULT_CONFIG */ if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; apic = bus = intr = 0; cpu = 1; /* pre-count the BSP */ while (count--) { switch (type = *(u_char *) position) { case 0: if (processor_entry(position, cpu)) ++cpu; break; case 1: if (bus_entry(position, bus)) ++bus; break; case 2: if (io_apic_entry(position, apic)) ++apic; break; case 3: if (int_entry(position, intr)) ++intr; break; case 4: /* int_entry(position); */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char *) position += basetable_entry_types[type].length; } if (boot_cpu_id == -1) panic("NO BSP found!"); /* post scan cleanup */ fix_mp_table(); /* report fact that its NOT a default configuration */ return 0; } /* * parse an Intel MP specification table */ static void fix_mp_table(void) { int x; int id; int bus_0; int bus_pci; int num_pci_bus; /* * Fix mis-numbering of the PCI bus and its INT entries if the BIOS * did it wrong. The MP spec says that when more than 1 PCI bus * exists the BIOS must begin with bus entries for the PCI bus and use * actual PCI bus numbering. This implies that when only 1 PCI bus * exists the BIOS can choose to ignore this ordering, and indeed many * MP motherboards do ignore it. This causes a problem when the PCI * sub-system makes requests of the MP sub-system based on PCI bus * numbers. So here we look for the situation and renumber the * busses and associated INTs in an effort to "make it right". */ /* find bus 0, PCI bus, count the number of PCI busses */ for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_id == 0) { bus_0 = x; } if (bus_data[x].bus_type == PCI) { ++num_pci_bus; bus_pci = x; } } /* * bus_0 == slot of bus with ID of 0 * bus_pci == slot of last PCI bus encountered */ /* check the 1 PCI bus case for sanity */ if (num_pci_bus == 1) { /* if it is number 0 all is well */ if (bus_data[bus_pci].bus_id == 0) return; /* mis-numbered, swap with whichever bus uses slot 0 */ /* swap the bus entry types */ bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; bus_data[bus_0].bus_type = PCI; /* swap each relavant INTerrupt entry */ id = bus_data[bus_pci].bus_id; for (x = 0; x < nintrs; ++x) { if (io_apic_ints[x].src_bus_id == id) { io_apic_ints[x].src_bus_id = 0; } else if (io_apic_ints[x].src_bus_id == 0) { io_apic_ints[x].src_bus_id = id; } } } /* sanity check if more than 1 PCI bus */ else if (num_pci_bus > 1) { for (x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_type != PCI) continue; if (bus_data[x].bus_id >= num_pci_bus) panic("bad PCI bus numbering"); } } } static int processor_entry(proc_entry_ptr entry, int cpu) { /* check for usability */ if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) return 0; /* check for BSP flag */ if (entry->cpu_flags & PROCENTRY_FLAG_BP) { boot_cpu_id = entry->apic_id; CPU_TO_ID(0) = entry->apic_id; ID_TO_CPU(entry->apic_id) = 0; return 0; /* its already been counted */ } /* add another AP to list, if less than max number of CPUs */ else { CPU_TO_ID(cpu) = entry->apic_id; ID_TO_CPU(entry->apic_id) = cpu; return 1; } } static int bus_entry(bus_entry_ptr entry, int bus) { int x; char c, name[8]; /* encode the name into an index */ for (x = 0; x < 6; ++x) { if ((c = entry->bus_type[x]) == ' ') break; name[x] = c; } name[x] = '\0'; if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) panic("unknown bus type: '%s'", name); bus_data[bus].bus_id = entry->bus_id; bus_data[bus].bus_type = x; return 1; } static int io_apic_entry(io_apic_entry_ptr entry, int apic) { if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) return 0; IO_TO_ID(apic) = entry->apic_id; ID_TO_IO(entry->apic_id) = apic; return 1; } static int lookup_bus_type(char *name) { int x; for (x = 0; x < MAX_BUSTYPE; ++x) if (strcmp(bus_type_table[x].name, name) == 0) return bus_type_table[x].type; return UNKNOWN_BUSTYPE; } static int int_entry(int_entry_ptr entry, int intr) { io_apic_ints[intr].int_type = entry->int_type; io_apic_ints[intr].int_flags = entry->int_flags; io_apic_ints[intr].src_bus_id = entry->src_bus_id; io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; return 1; } static int apic_int_is_bus_type(int intr, int bus_type) { int bus; for (bus = 0; bus < mp_nbusses; ++bus) if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) && ((int) bus_data[bus].bus_type == bus_type)) return 1; return 0; } /* * Given a traditional ISA INT mask, return an APIC mask. */ u_int isa_apic_mask(u_int isa_mask) { int isa_irq; int apic_pin; #if defined(SKIP_IRQ15_REDIRECT) if (isa_mask == (1 << 15)) { printf("skipping ISA IRQ15 redirect\n"); return isa_mask; } #endif /* SKIP_IRQ15_REDIRECT */ isa_irq = ffs(isa_mask); /* find its bit position */ if (isa_irq == 0) /* doesn't exist */ return 0; --isa_irq; /* make it zero based */ apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ if (apic_pin == -1) return 0; return (1 << apic_pin); /* convert pin# to a mask */ } /* * Determine which APIC pin an ISA/EISA INT is attached to. */ #define INTTYPE(I) (io_apic_ints[(I)].int_type) #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) int isa_apic_pin(int isa_irq) { int intr; #if defined(SMP_TIMER_NC) if (isa_irq == 0) return -1; #endif /* SMP_TIMER_NC */ for (intr = 0; intr < nintrs; ++intr) { /* check each record */ if (INTTYPE(intr) == 0) { /* standard INT */ if (SRCBUSIRQ(intr) == isa_irq) { if (apic_int_is_bus_type(intr, ISA) || apic_int_is_bus_type(intr, EISA)) return INTPIN(intr); /* found */ } } } return -1; /* NOT found */ } #undef SRCBUSIRQ /* * Determine which APIC pin a PCI INT is attached to. */ #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) int pci_apic_pin(int pciBus, int pciDevice, int pciInt) { int intr; --pciInt; /* zero based */ for (intr = 0; intr < nintrs; ++intr) /* check each record */ if ((INTTYPE(intr) == 0) /* standard INT */ && (SRCBUSID(intr) == pciBus) && (SRCBUSDEVICE(intr) == pciDevice) && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ if (apic_int_is_bus_type(intr, PCI)) return INTPIN(intr); /* exact match */ return -1; /* NOT found */ } #undef SRCBUSLINE #undef SRCBUSDEVICE #undef SRCBUSID #undef INTPIN #undef INTTYPE /* * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. * * XXX FIXME: * Exactly what this means is unclear at this point. It is a solution * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard * could route any of the ISA INTs to upper (>15) IRQ values. But most would * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an * option. */ int undirect_isa_irq(int rirq) { #if defined(READY) printf("Freeing redirected ISA irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); return 0; #endif /* READY */ } /* * Reprogram the MB chipset to NOT redirect a PCI INTerrupt */ int undirect_pci_irq(int rirq) { #if defined(READY) if (bootverbose) printf("Freeing redirected PCI irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else if (bootverbose) printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); return 0; #endif /* READY */ } /* * given a bus ID, return: * the bus type if found * -1 if NOT found */ int apic_bus_type(int id) { int x; for (x = 0; x < mp_nbusses; ++x) if (bus_data[x].bus_id == id) return bus_data[x].bus_type; return -1; } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus ID if found * -1 if NOT found */ int apic_src_bus_id(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_id); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus IRQ if found * -1 if NOT found */ int apic_src_bus_irq(int apic, int pin) { int x; for (x = 0; x < nintrs; x++) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_irq); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated INTerrupt type if found * -1 if NOT found */ int apic_int_type(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_type); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated trigger mode if found * -1 if NOT found */ int apic_trigger(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return ((io_apic_ints[x].int_flags >> 2) & 0x03); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated 'active' level if found * -1 if NOT found */ int apic_polarity(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_flags & 0x03); return -1; /* NOT found */ } /* * set data according to MP defaults * FIXME: probably not complete yet... */ static void default_mp_table(int type) { int ap_cpu_id; #if defined(APIC_IO) u_int32_t ux; int io_apic_id; int pin; #endif /* APIC_IO */ #if 0 printf(" MP default config type: %d\n", type); switch (type) { case 1: printf(" bus: ISA, APIC: 82489DX\n"); break; case 2: printf(" bus: EISA, APIC: 82489DX\n"); break; case 3: printf(" bus: EISA, APIC: 82489DX\n"); break; case 4: printf(" bus: MCA, APIC: 82489DX\n"); break; case 5: printf(" bus: ISA+PCI, APIC: Integrated\n"); break; case 6: printf(" bus: EISA+PCI, APIC: Integrated\n"); break; case 7: printf(" bus: MCA+PCI, APIC: Integrated\n"); break; default: printf(" future type\n"); break; /* NOTREACHED */ } #endif /* 0 */ boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; /* BSP */ CPU_TO_ID(0) = boot_cpu_id; ID_TO_CPU(boot_cpu_id) = 0; /* one and only AP */ CPU_TO_ID(1) = ap_cpu_id; ID_TO_CPU(ap_cpu_id) = 1; #if defined(APIC_IO) /* one and only IO APIC */ io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; /* * sanity check, refer to MP spec section 3.6.6, last paragraph * necessary as some hardware isn't properly setting up the IO APIC */ #if defined(REALLY_ANAL_IOAPICID_VALUE) if (io_apic_id != 2) { #else if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { #endif /* REALLY_ANAL_IOAPICID_VALUE */ ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ ux &= ~APIC_ID_MASK; /* clear the ID field */ ux |= 0x02000000; /* set it to '2' */ io_apic_write(0, IOAPIC_ID, ux); /* write new value */ ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ if ((ux & APIC_ID_MASK) != 0x02000000) panic("can't control IO APIC ID, reg: 0x%08x", ux); io_apic_id = 2; } IO_TO_ID(0) = io_apic_id; ID_TO_IO(io_apic_id) = 0; #endif /* APIC_IO */ /* fill out bus entries */ switch (type) { case 1: case 2: case 3: case 5: case 6: bus_data[0].bus_id = default_data[type - 1][1]; bus_data[0].bus_type = default_data[type - 1][2]; bus_data[1].bus_id = default_data[type - 1][3]; bus_data[1].bus_type = default_data[type - 1][4]; break; /* case 4: case 7: MCA NOT supported */ default: /* illegal/reserved */ panic("BAD default MP config: %d", type); /* NOTREACHED */ } #if defined(APIC_IO) /* general cases from MP v1.4, table 5-2 */ for (pin = 0; pin < 16; ++pin) { io_apic_ints[pin].int_type = 0; io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ io_apic_ints[pin].src_bus_id = 0; io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ io_apic_ints[pin].dst_apic_id = io_apic_id; io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ } /* special cases from MP v1.4, table 5-2 */ if (type == 2) { io_apic_ints[2].int_type = 0xff; /* N/C */ io_apic_ints[13].int_type = 0xff; /* N/C */ #if !defined(APIC_MIXED_MODE) /** FIXME: ??? */ panic("sorry, can't support type 2 default yet"); #endif /* APIC_MIXED_MODE */ } else io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ if (type == 7) io_apic_ints[0].int_type = 0xff; /* N/C */ else io_apic_ints[0].int_type = 3; /* vectored 8259 */ #endif /* APIC_IO */ } /* * start each AP in our list */ static int start_all_aps(u_int boot_addr) { int x, i; u_char mpbiosreason; u_long mpbioswarmvec; pd_entry_t newptd; pt_entry_t newpt; int *newpp; POSTCODE(START_ALL_APS_POST); /** * NOTE: this needs further thought: * where does it get released? * should it be set to empy? * * get the initial mp_lock with a count of 1 for the BSP */ mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ /* initialize BSP's local APIC */ apic_initialize(); /* install the AP 1st level boot code */ install_ap_tramp(boot_addr); /* save the current value of the warm-start vector */ mpbioswarmvec = *((u_long *) WARMBOOT_OFF); outb(CMOS_REG, BIOS_RESET); mpbiosreason = inb(CMOS_DATA); /* record BSP in CPU map */ all_cpus = 1; /* start each AP */ for (x = 1; x <= mp_naps; ++x) { /* HACK HACK HACK !!! */ /* alloc new page table directory */ newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* clone currently active one (ie: IdlePTD) */ bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ /* set up 0 -> 4MB P==V mapping for AP boot */ newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); /* store PTD for this AP */ bootPTD = (pd_entry_t)vtophys(newptd); /* alloc new page table page */ newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* set the new PTD's private page to point there */ newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); /* install self referential entry */ newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); /* get a new private data page */ newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); /* wire it into the private page table page */ newpt[0] = PG_V | PG_RW | vtophys(newpp); /* wire the ptp into itself for access */ newpt[1] = PG_V | PG_RW | vtophys(newpt); /* and the local apic */ newpt[2] = SMP_prvpt[2]; /* and the IO apic mapping[s] */ for (i = 16; i < 32; i++) newpt[i] = SMP_prvpt[i]; /* prime data page for it to use */ newpp[0] = x; /* cpuid */ newpp[1] = 0; /* curproc */ newpp[2] = 0; /* curpcb */ newpp[3] = 0; /* npxproc */ newpp[4] = 0; /* runtime.tv_sec */ newpp[5] = 0; /* runtime.tv_usec */ newpp[6] = x << 24; /* cpu_lockid */ /* XXX NOTE: ABANDON bootPTD for now!!!! */ /* END REVOLTING HACKERY */ /* setup a vector to our boot code */ *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ /* attempt to start the Application Processor */ CHECK_INIT(99); /* setup checkpoints */ if (!start_ap(x, boot_addr)) { printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); CHECK_PRINT("trace"); /* show checkpoints */ /* better panic as the AP may be running loose */ printf("panic y/n? [y] "); if (cngetc() != 'n') panic("bye-bye"); } CHECK_PRINT("trace"); /* show checkpoints */ /* record its version info */ cpu_apic_versions[x] = cpu_apic_versions[0]; all_cpus |= (1 << x); /* record AP in CPU map */ } /* build our map of 'other' CPUs */ other_cpus = all_cpus & ~(1 << cpuid); /* fill in our (BSP) APIC version */ cpu_apic_versions[0] = lapic.version; /* restore the warmstart vector */ *(u_long *) WARMBOOT_OFF = mpbioswarmvec; outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, mpbiosreason); pmap_set_opt_bsp(); /* number of APs actually started */ return mp_ncpus - 1; } /* * load the 1st level AP boot code into base memory. */ /* targets for relocation */ extern void bigJump(void); extern void bootCodeSeg(void); extern void bootDataSeg(void); extern void MPentry(void); extern u_int MP_GDT; extern u_int mp_gdtbase; static void install_ap_tramp(u_int boot_addr) { int x; int size = *(int *) ((u_long) & bootMP_size); u_char *src = (u_char *) ((u_long) bootMP); u_char *dst = (u_char *) boot_addr + KERNBASE; u_int boot_base = (u_int) bootMP; u_int8_t *dst8; u_int16_t *dst16; u_int32_t *dst32; POSTCODE(INSTALL_AP_TRAMP_POST); for (x = 0; x < size; ++x) *dst++ = *src++; /* * modify addresses in code we just moved to basemem. unfortunately we * need fairly detailed info about mpboot.s for this to work. changes * to mpboot.s might require changes here. */ /* boot code is located in KERNEL space */ dst = (u_char *) boot_addr + KERNBASE; /* modify the lgdt arg */ dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); /* modify the ljmp target for MPentry() */ dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); *dst32 = ((u_int) MPentry - KERNBASE); /* modify the target for boot code segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; /* modify the target for boot data segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; } /* * this function starts the AP (application processor) identified * by the APIC ID 'physicalCpu'. It does quite a "song and dance" * to accomplish this. This is necessary because of the nuances * of the different hardware we might encounter. It ain't pretty, * but it seems to work. */ static int start_ap(int logical_cpu, u_int boot_addr) { int physical_cpu; int vector; int cpus; u_long icr_lo, icr_hi; POSTCODE(START_AP_POST); /* get the PHYSICAL APIC ID# */ physical_cpu = CPU_TO_ID(logical_cpu); /* calculate the vector */ vector = (boot_addr >> 12) & 0xff; /* used as a watchpoint to signal AP startup */ cpus = mp_ncpus; /* * first we do an INIT/RESET IPI this INIT IPI might be run, reseting * and running the target CPU. OR this INIT IPI might be latched (P5 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be * ignored. */ /* setup the address for the target AP */ icr_hi = lapic.icr_hi & ~APIC_ID_MASK; icr_hi |= (physical_cpu << 24); lapic.icr_hi = icr_hi; /* do an INIT IPI: assert RESET */ icr_lo = lapic.icr_lo & 0xfff00000; lapic.icr_lo = icr_lo | 0x0000c500; /* wait for pending status end */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* do an INIT IPI: deassert RESET */ lapic.icr_lo = icr_lo | 0x00008500; /* wait for pending status end */ u_sleep(10000); /* wait ~10mS */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* * next we do a STARTUP IPI: the previous INIT IPI might still be * latched, (P5 bug) this 1st STARTUP would then terminate * immediately, and the previously started INIT IPI would continue. OR * the previous INIT IPI has already run. and this STARTUP IPI will * run. OR the previous INIT IPI was ignored. and this STARTUP IPI * will run. */ /* do a STARTUP IPI */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is * recognized after hardware RESET or INIT IPI. */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* wait for it to start */ set_apic_timer(5000000);/* == 5 seconds */ while (read_apic_timer()) if (mp_ncpus > cpus) return 1; /* return SUCCESS */ return 0; /* return FAILURE */ } /* * Flush the TLB on all other CPU's * * XXX: Needs to handshake and wait for completion before proceding. */ void smp_invltlb(void) { #if defined(APIC_IO) if (smp_active && invltlb_ok) all_but_self_ipi(XINVLTLB_OFFSET); #endif /* APIC_IO */ } void invlpg(u_int addr) { __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); /* send a message to the other CPUs */ smp_invltlb(); } void invltlb(void) { u_long temp; /* * This should be implemented as load_cr3(rcr3()) when load_cr3() is * inlined. */ __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); /* send a message to the other CPUs */ smp_invltlb(); } -#if defined(TEST_CPUSTOP) - -#if defined(DEBUG_CPUSTOP) -void db_printf __P((const char *fmt, ...)); -#endif /* DEBUG_CPUSTOP */ - /* * When called the executing CPU will send an IPI to all other CPUs * requesting that they halt execution. * * Usually (but not necessarily) called with 'other_cpus' as its arg. * * - Signals all CPUs in map to stop. * - Waits for each to stop. * * Returns: * -1: error * 0: NA * 1: ok * * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs * from executing at same time. */ int stop_cpus( u_int map ) { if (!smp_active) return 0; /* send IPI to all CPUs in map */ -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); -#endif /* DEBUG_CPUSTOP */ - stopped_cpus = 0; /* send the Xcpustop IPI to all CPUs in map */ selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); -#if defined(DEBUG_CPUSTOP) - db_printf(" spin\n"); -#endif /* DEBUG_CPUSTOP */ - while (stopped_cpus != map) /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" spun\nstopped\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } /* * Called by a CPU to restart stopped CPUs. * * Usually (but not necessarily) called with 'stopped_cpus' as its arg. * * - Signals all CPUs in map to restart. * - Waits for each to restart. * * Returns: * -1: error * 0: NA * 1: ok */ int restart_cpus( u_int map ) { if (!smp_active) return 0; -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", - cpuid, map, stopped_cpus); -#endif /* DEBUG_CPUSTOP */ - started_cpus = map; /* signal other cpus to restart */ while (started_cpus) /* wait for each to clear its bit */ /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" restarted\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } - -#endif /** TEST_CPUSTOP */ Index: head/sys/amd64/amd64/mptable.c =================================================================== --- head/sys/amd64/amd64/mptable.c (revision 27516) +++ head/sys/amd64/amd64/mptable.c (revision 27517) @@ -1,1834 +1,1803 @@ /* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: mp_machdep.c,v 1.28 1997/07/17 19:44:56 dyson Exp $ + * $Id: mp_machdep.c,v 1.16 1997/07/18 19:45:41 smp Exp smp $ */ #include "opt_smp.h" #include /* for KERNBASE */ #include #include #include #include #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include #include #include #include #include #include #include -#include /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP _TEST1 */ +#include /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ #include #include #include /* cngetc() */ #if defined(APIC_IO) #include /* setidt() */ #include /* IPIs */ #include /* IPIs */ #endif /* APIC_IO */ #define WARMBOOT_TARGET 0 #define WARMBOOT_OFF (KERNBASE + 0x0467) #define WARMBOOT_SEG (KERNBASE + 0x0469) #define BIOS_BASE (0xf0000) #define BIOS_SIZE (0x10000) #define BIOS_COUNT (BIOS_SIZE/4) #define CMOS_REG (0x70) #define CMOS_DATA (0x71) #define BIOS_RESET (0x0f) #define BIOS_WARM (0x0a) #define PROCENTRY_FLAG_EN 0x01 #define PROCENTRY_FLAG_BP 0x02 #define IOAPICENTRY_FLAG_EN 0x01 /* MP Floating Pointer Structure */ typedef struct MPFPS { char signature[4]; void *pap; u_char length; u_char spec_rev; u_char checksum; u_char mpfb1; u_char mpfb2; u_char mpfb3; u_char mpfb4; u_char mpfb5; } *mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { char signature[4]; u_short base_table_length; u_char spec_rev; u_char checksum; u_char oem_id[8]; u_char product_id[12]; void *oem_table_pointer; u_short oem_table_size; u_short entry_count; void *apic_address; u_short extended_table_length; u_char extended_table_checksum; u_char reserved; } *mpcth_t; typedef struct PROCENTRY { u_char type; u_char apic_id; u_char apic_version; u_char cpu_flags; u_long cpu_signature; u_long feature_flags; u_long reserved1; u_long reserved2; } *proc_entry_ptr; typedef struct BUSENTRY { u_char type; u_char bus_id; char bus_type[6]; } *bus_entry_ptr; typedef struct IOAPICENTRY { u_char type; u_char apic_id; u_char apic_version; u_char apic_flags; void *apic_address; } *io_apic_entry_ptr; typedef struct INTENTRY { u_char type; u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } *int_entry_ptr; /* descriptions of MP basetable entries */ typedef struct BASETABLE_ENTRY { u_char type; u_char length; char name[16]; } basetable_entry; /* * this code MUST be enabled here and in mpboot.s. * it follows the very early stages of AP boot by placing values in CMOS ram. * it NORMALLY will never be needed and thus the primitive method for enabling. * #define CHECK_POINTS */ #if defined(CHECK_POINTS) #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) #define CHECK_INIT(D); \ CHECK_WRITE(0x34, (D)); \ CHECK_WRITE(0x35, (D)); \ CHECK_WRITE(0x36, (D)); \ CHECK_WRITE(0x37, (D)); \ CHECK_WRITE(0x38, (D)); \ CHECK_WRITE(0x39, (D)); #define CHECK_PRINT(S); \ printf("%s: %d, %d, %d, %d, %d, %d\n", \ (S), \ CHECK_READ(0x34), \ CHECK_READ(0x35), \ CHECK_READ(0x36), \ CHECK_READ(0x37), \ CHECK_READ(0x38), \ CHECK_READ(0x39)); #else /* CHECK_POINTS */ #define CHECK_INIT(D) #define CHECK_PRINT(S) #endif /* CHECK_POINTS */ /* * Values to send to the POST hardware. */ #define MP_BOOTADDRESS_POST 0x10 #define MP_PROBE_POST 0x11 #define MP_START_POST 0x12 #define MP_ANNOUNCE_POST 0x13 #define MPTABLE_PASS1_POST 0x14 #define MPTABLE_PASS2_POST 0x15 #define MP_ENABLE_POST 0x16 #define START_ALL_APS_POST 0x17 #define INSTALL_AP_TRAMP_POST 0x18 #define START_AP_POST 0x19 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ int current_postcode; /** XXX FIXME: what system files declare these??? */ extern struct region_descriptor r_gdt, r_idt; int mp_ncpus; /* # of CPUs, including BSP */ int mp_naps; /* # of Applications processors */ int mp_nbusses; /* # of busses */ int mp_napics; /* # of IO APICs */ int boot_cpu_id; /* designated BSP */ vm_offset_t cpu_apic_address; vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ u_int32_t cpu_apic_versions[NCPU]; u_int32_t io_apic_versions[NAPIC]; /* * APIC ID logical/physical mapping structures. * We oversize these to simplify boot-time config. */ int cpu_num_to_apic_id[NAPICID]; int io_num_to_apic_id[NAPICID]; int apic_id_to_logical[NAPICID]; /* Bitmap of all available CPUs */ u_int all_cpus; /* Boot of AP uses this PTD */ u_int *bootPTD; /* Hotwire a 0->4MB V==P mapping */ extern pt_entry_t KPTphys; /* Virtual address of per-cpu common_tss */ extern struct i386tss common_tss; /* * Local data and functions. */ static int mp_capable; static u_int boot_address; static u_int base_memory; static int picmode; /* 0: virtual wire mode, 1: PIC mode */ static mpfps_t mpfps; static int search_for_sig(u_int32_t target, int count); static void mp_enable(u_int boot_addr); static int mptable_pass1(void); static int mptable_pass2(void); static void default_mp_table(int type); static int start_all_aps(u_int boot_addr); static void install_ap_tramp(u_int boot_addr); static int start_ap(int logicalCpu, u_int boot_addr); /* * Calculate usable address in base memory for AP trampoline code. */ u_int mp_bootaddress(u_int basemem) { POSTCODE(MP_BOOTADDRESS_POST); base_memory = basemem * 1024; /* convert to bytes */ boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ if ((base_memory - boot_address) < bootMP_size) boot_address -= 4096; /* not enough, lower by 4k */ return boot_address; } /* * Look for an Intel MP spec table (ie, SMP capable hardware). */ int mp_probe(void) { int x; u_long segment; u_int32_t target; POSTCODE(MP_PROBE_POST); /* see if EBDA exists */ if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { /* search first 1K of EBDA */ target = (u_int32_t) (segment << 4); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } else { /* last 1K of base memory, effective 'top of base' passed in */ target = (u_int32_t) (base_memory - 0x400); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } /* search the BIOS */ target = (u_int32_t) BIOS_BASE; if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) goto found; /* nothing found */ mpfps = (mpfps_t)0; mp_capable = 0; return 0; found: /* calculate needed resources */ mpfps = (mpfps_t)x; if (mptable_pass1()) panic("you must reconfigure your kernel"); /* flag fact that we are running multiple processors */ mp_capable = 1; return 1; } /* * Startup the SMP processors. */ void mp_start(void) { POSTCODE(MP_START_POST); /* look for MP capable motherboard */ if (mp_capable) mp_enable(boot_address); else panic("MP hardware not found!"); } /* * Print various information about the SMP system hardware and setup. */ void mp_announce(void) { int x; POSTCODE(MP_ANNOUNCE_POST); printf("FreeBSD/SMP: Multiprocessor motherboard\n"); printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); printf(", version: 0x%08x", cpu_apic_versions[0]); printf(", at 0x%08x\n", cpu_apic_address); for (x = 1; x <= mp_naps; ++x) { printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); printf(", version: 0x%08x", cpu_apic_versions[x]); printf(", at 0x%08x\n", cpu_apic_address); } #if defined(APIC_IO) for (x = 0; x < mp_napics; ++x) { printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); printf(", version: 0x%08x", io_apic_versions[x]); printf(", at 0x%08x\n", io_apic_address[x]); } #else printf(" Warning: APIC I/O disabled\n"); #endif /* APIC_IO */ } /* * AP cpu's call this to sync up protected mode. */ void init_secondary(void) { int gsel_tss, slot; r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; r_gdt.rd_base = (int) gdt; lgdt(&r_gdt); /* does magic intra-segment return */ lidt(&r_idt); lldt(_default_ldt); slot = NGDT + cpuid; gsel_tss = GSEL(slot, SEL_KPL); gdt[slot].sd.sd_type = SDT_SYS386TSS; common_tss.tss_esp0 = 0; /* not used until after switch */ common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); common_tss.tss_ioopt = (sizeof common_tss) << 16; ltr(gsel_tss); load_cr0(0x8005003b); /* XXX! */ PTD[0] = 0; pmap_set_opt((unsigned *)PTD); invltlb(); } #if defined(APIC_IO) /* * Final configuration of the BSP's local APIC: * - disable 'pic mode'. * - disable 'virtual wire mode'. * - enable NMI. */ void bsp_apic_configure(void) { u_char byte; u_int32_t temp; /* leave 'pic mode' if necessary */ if (picmode) { outb(0x22, 0x70); /* select IMCR */ byte = inb(0x23); /* current contents */ byte |= 0x01; /* mask external INTR */ outb(0x23, byte); /* disconnect 8259s/NMI */ } /* mask lint0 (the 8259 'virtual wire' connection) */ temp = lapic.lvt_lint0; temp |= APIC_LVT_M; /* set the mask */ lapic.lvt_lint0 = temp; /* setup lint1 to handle NMI */ temp = lapic.lvt_lint1; temp &= ~APIC_LVT_M; /* clear the mask */ lapic.lvt_lint1 = temp; if (bootverbose) apic_dump(); } #endif /* APIC_IO */ /******************************************************************* * local functions and data */ /* * start the SMP system */ static void mp_enable(u_int boot_addr) { int x; #if defined(APIC_IO) int apic; u_int ux; #endif /* APIC_IO */ POSTCODE(MP_ENABLE_POST); /* turn on 4MB of V == P addressing so we can get to MP table */ *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); invltlb(); /* examine the MP table for needed info, uses physical addresses */ x = mptable_pass2(); *(int *)PTD = 0; invltlb(); /* can't process default configs till the CPU APIC is pmapped */ if (x) default_mp_table(x); #if defined(APIC_IO) /* fill the LOGICAL io_apic_versions table */ for (apic = 0; apic < mp_napics; ++apic) { ux = io_apic_read(apic, IOAPIC_VER); io_apic_versions[apic] = ux; } /* program each IO APIC in the system */ for (apic = 0; apic < mp_napics; ++apic) if (io_apic_setup(apic) < 0) panic("IO APIC setup failure"); /* install a 'Spurious INTerrupt' vector */ setidt(XSPURIOUSINT_OFFSET, Xspuriousint, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); /* install an inter-CPU IPI for TLB invalidation */ setidt(XINVLTLB_OFFSET, Xinvltlb, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#if defined(TEST_CPUSTOP) /* install an inter-CPU IPI for CPU stop/restart */ setidt(XCPUSTOP_OFFSET, Xcpustop, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#endif /** TEST_CPUSTOP */ #if defined(TEST_TEST1) - /* install a 'Spurious INTerrupt' vector */ + /* install a "fake hardware INTerrupt" vector */ setidt(XTEST1_OFFSET, Xtest1, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /** TEST_TEST1 */ #endif /* APIC_IO */ /* start each Application Processor */ start_all_aps(boot_addr); /* * The init process might be started on a different CPU now, * and the boot CPU might not call prepare_usermode to get * cr0 correctly configured. Thus we initialize cr0 here. */ load_cr0(rcr0() | CR0_WP | CR0_AM); } /* * look for the MP spec signature */ /* string defined by the Intel MP Spec as identifying the MP table */ #define MP_SIG 0x5f504d5f /* _MP_ */ #define NEXT(X) ((X) += 4) static int search_for_sig(u_int32_t target, int count) { int x; u_int32_t *addr = (u_int32_t *) (KERNBASE + target); for (x = 0; x < count; NEXT(x)) if (addr[x] == MP_SIG) /* make array index a byte index */ return (target + (x * sizeof(u_int32_t))); return -1; } static basetable_entry basetable_entry_types[] = { {0, 20, "Processor"}, {1, 8, "Bus"}, {2, 8, "I/O APIC"}, {3, 8, "I/O INT"}, {4, 8, "Local INT"} }; typedef struct BUSDATA { u_char bus_id; enum busTypes bus_type; } bus_datum; typedef struct INTDATA { u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } io_int, local_int; typedef struct BUSTYPENAME { u_char type; char name[7]; } bus_type_name; static bus_type_name bus_type_table[] = { {CBUS, "CBUS"}, {CBUSII, "CBUSII"}, {EISA, "EISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {ISA, "ISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {PCI, "PCI"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {XPRESS, "XPRESS"}, {UNKNOWN_BUSTYPE, "---"} }; /* from MP spec v1.4, table 5-1 */ static int default_data[7][5] = { /* nbus, id0, type0, id1, type1 */ {1, 0, ISA, 255, 255}, {1, 0, EISA, 255, 255}, {1, 0, EISA, 255, 255}, {0, 255, 255, 255, 255},/* MCA not supported */ {2, 0, ISA, 1, PCI}, {2, 0, EISA, 1, PCI}, {0, 255, 255, 255, 255} /* MCA not supported */ }; /* the bus data */ bus_datum bus_data[NBUS]; /* the IO INT data, one entry per possible APIC INTerrupt */ io_int io_apic_ints[NINTR]; static int nintrs; static void fix_mp_table __P((void)); static int processor_entry __P((proc_entry_ptr entry, int cpu)); static int bus_entry __P((bus_entry_ptr entry, int bus)); static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); static int int_entry __P((int_entry_ptr entry, int intr)); static int lookup_bus_type __P((char *name)); /* * 1st pass on motherboard's Intel MP specification table. * * initializes: * mp_ncpus = 1 * * determines: * cpu_apic_address (common to all CPUs) * io_apic_address[N] * mp_naps * mp_nbusses * mp_napics * nintrs */ static int mptable_pass1(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int mustpanic; POSTCODE(MPTABLE_PASS1_POST); mustpanic = 0; /* clear various tables */ for (x = 0; x < NAPICID; ++x) { io_apic_address[x] = ~0; /* IO APIC address table */ } /* init everything to empty */ mp_naps = 0; mp_nbusses = 0; mp_napics = 0; nintrs = 0; /* check for use of 'default' configuration */ if (mpfps->mpfb1 != 0) { /* use default addresses */ cpu_apic_address = DEFAULT_APIC_BASE; io_apic_address[0] = DEFAULT_IO_APIC_BASE; /* fill in with defaults */ mp_naps = 2; /* includes BSP */ mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; #if defined(APIC_IO) mp_napics = 1; nintrs = 16; #endif /* APIC_IO */ } else { if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); cpu_apic_address = (vm_offset_t) cth->apic_address; /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; while (count--) { switch (type = *(u_char *) position) { case 0: /* processor_entry */ if (((proc_entry_ptr)position)->cpu_flags & PROCENTRY_FLAG_EN) ++mp_naps; break; case 1: /* bus_entry */ ++mp_nbusses; break; case 2: /* io_apic_entry */ if (((io_apic_entry_ptr)position)->apic_flags & IOAPICENTRY_FLAG_EN) io_apic_address[mp_napics++] = (vm_offset_t)((io_apic_entry_ptr) position)->apic_address; break; case 3: /* int_entry */ ++nintrs; break; case 4: /* int_entry */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char*)position += basetable_entry_types[type].length; } } /* qualify the numbers */ if (mp_naps > NCPU) printf("Warning: only using %d of %d available CPUs!\n", NCPU, mp_naps); #if 0 /** XXX we consider this legal now (but should we?) */ mustpanic = 1; #endif if (mp_nbusses > NBUS) { printf("found %d busses, increase NBUS\n", mp_nbusses); mustpanic = 1; } if (mp_napics > NAPIC) { printf("found %d apics, increase NAPIC\n", mp_napics); mustpanic = 1; } if (nintrs > NINTR) { printf("found %d intrs, increase NINTR\n", nintrs); mustpanic = 1; } /* * Count the BSP. * This is also used as a counter while starting the APs. */ mp_ncpus = 1; --mp_naps; /* subtract the BSP */ return mustpanic; } /* * 2nd pass on motherboard's Intel MP specification table. * * sets: * boot_cpu_id * ID_TO_IO(N), phy APIC ID to log CPU/IO table * CPU_TO_ID(N), logical CPU to APIC ID table * IO_TO_ID(N), logical IO to APIC ID table * bus_data[N] * io_apic_ints[N] */ static int mptable_pass2(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int apic, bus, cpu, intr; POSTCODE(MPTABLE_PASS2_POST); /* clear various tables */ for (x = 0; x < NAPICID; ++x) { ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ } /* clear bus data table */ for (x = 0; x < NBUS; ++x) bus_data[x].bus_id = 0xff; /* clear IO APIC INT table */ for (x = 0; x < NINTR; ++x) io_apic_ints[x].int_type = 0xff; /* setup the cpu/apic mapping arrays */ boot_cpu_id = -1; /* record whether PIC or virtual-wire mode */ picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; /* check for use of 'default' configuration */ #if defined(TEST_DEFAULT_CONFIG) return TEST_DEFAULT_CONFIG; #else if (mpfps->mpfb1 != 0) return mpfps->mpfb1; /* return default configuration type */ #endif /* TEST_DEFAULT_CONFIG */ if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; apic = bus = intr = 0; cpu = 1; /* pre-count the BSP */ while (count--) { switch (type = *(u_char *) position) { case 0: if (processor_entry(position, cpu)) ++cpu; break; case 1: if (bus_entry(position, bus)) ++bus; break; case 2: if (io_apic_entry(position, apic)) ++apic; break; case 3: if (int_entry(position, intr)) ++intr; break; case 4: /* int_entry(position); */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char *) position += basetable_entry_types[type].length; } if (boot_cpu_id == -1) panic("NO BSP found!"); /* post scan cleanup */ fix_mp_table(); /* report fact that its NOT a default configuration */ return 0; } /* * parse an Intel MP specification table */ static void fix_mp_table(void) { int x; int id; int bus_0; int bus_pci; int num_pci_bus; /* * Fix mis-numbering of the PCI bus and its INT entries if the BIOS * did it wrong. The MP spec says that when more than 1 PCI bus * exists the BIOS must begin with bus entries for the PCI bus and use * actual PCI bus numbering. This implies that when only 1 PCI bus * exists the BIOS can choose to ignore this ordering, and indeed many * MP motherboards do ignore it. This causes a problem when the PCI * sub-system makes requests of the MP sub-system based on PCI bus * numbers. So here we look for the situation and renumber the * busses and associated INTs in an effort to "make it right". */ /* find bus 0, PCI bus, count the number of PCI busses */ for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_id == 0) { bus_0 = x; } if (bus_data[x].bus_type == PCI) { ++num_pci_bus; bus_pci = x; } } /* * bus_0 == slot of bus with ID of 0 * bus_pci == slot of last PCI bus encountered */ /* check the 1 PCI bus case for sanity */ if (num_pci_bus == 1) { /* if it is number 0 all is well */ if (bus_data[bus_pci].bus_id == 0) return; /* mis-numbered, swap with whichever bus uses slot 0 */ /* swap the bus entry types */ bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; bus_data[bus_0].bus_type = PCI; /* swap each relavant INTerrupt entry */ id = bus_data[bus_pci].bus_id; for (x = 0; x < nintrs; ++x) { if (io_apic_ints[x].src_bus_id == id) { io_apic_ints[x].src_bus_id = 0; } else if (io_apic_ints[x].src_bus_id == 0) { io_apic_ints[x].src_bus_id = id; } } } /* sanity check if more than 1 PCI bus */ else if (num_pci_bus > 1) { for (x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_type != PCI) continue; if (bus_data[x].bus_id >= num_pci_bus) panic("bad PCI bus numbering"); } } } static int processor_entry(proc_entry_ptr entry, int cpu) { /* check for usability */ if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) return 0; /* check for BSP flag */ if (entry->cpu_flags & PROCENTRY_FLAG_BP) { boot_cpu_id = entry->apic_id; CPU_TO_ID(0) = entry->apic_id; ID_TO_CPU(entry->apic_id) = 0; return 0; /* its already been counted */ } /* add another AP to list, if less than max number of CPUs */ else { CPU_TO_ID(cpu) = entry->apic_id; ID_TO_CPU(entry->apic_id) = cpu; return 1; } } static int bus_entry(bus_entry_ptr entry, int bus) { int x; char c, name[8]; /* encode the name into an index */ for (x = 0; x < 6; ++x) { if ((c = entry->bus_type[x]) == ' ') break; name[x] = c; } name[x] = '\0'; if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) panic("unknown bus type: '%s'", name); bus_data[bus].bus_id = entry->bus_id; bus_data[bus].bus_type = x; return 1; } static int io_apic_entry(io_apic_entry_ptr entry, int apic) { if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) return 0; IO_TO_ID(apic) = entry->apic_id; ID_TO_IO(entry->apic_id) = apic; return 1; } static int lookup_bus_type(char *name) { int x; for (x = 0; x < MAX_BUSTYPE; ++x) if (strcmp(bus_type_table[x].name, name) == 0) return bus_type_table[x].type; return UNKNOWN_BUSTYPE; } static int int_entry(int_entry_ptr entry, int intr) { io_apic_ints[intr].int_type = entry->int_type; io_apic_ints[intr].int_flags = entry->int_flags; io_apic_ints[intr].src_bus_id = entry->src_bus_id; io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; return 1; } static int apic_int_is_bus_type(int intr, int bus_type) { int bus; for (bus = 0; bus < mp_nbusses; ++bus) if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) && ((int) bus_data[bus].bus_type == bus_type)) return 1; return 0; } /* * Given a traditional ISA INT mask, return an APIC mask. */ u_int isa_apic_mask(u_int isa_mask) { int isa_irq; int apic_pin; #if defined(SKIP_IRQ15_REDIRECT) if (isa_mask == (1 << 15)) { printf("skipping ISA IRQ15 redirect\n"); return isa_mask; } #endif /* SKIP_IRQ15_REDIRECT */ isa_irq = ffs(isa_mask); /* find its bit position */ if (isa_irq == 0) /* doesn't exist */ return 0; --isa_irq; /* make it zero based */ apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ if (apic_pin == -1) return 0; return (1 << apic_pin); /* convert pin# to a mask */ } /* * Determine which APIC pin an ISA/EISA INT is attached to. */ #define INTTYPE(I) (io_apic_ints[(I)].int_type) #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) int isa_apic_pin(int isa_irq) { int intr; #if defined(SMP_TIMER_NC) if (isa_irq == 0) return -1; #endif /* SMP_TIMER_NC */ for (intr = 0; intr < nintrs; ++intr) { /* check each record */ if (INTTYPE(intr) == 0) { /* standard INT */ if (SRCBUSIRQ(intr) == isa_irq) { if (apic_int_is_bus_type(intr, ISA) || apic_int_is_bus_type(intr, EISA)) return INTPIN(intr); /* found */ } } } return -1; /* NOT found */ } #undef SRCBUSIRQ /* * Determine which APIC pin a PCI INT is attached to. */ #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) int pci_apic_pin(int pciBus, int pciDevice, int pciInt) { int intr; --pciInt; /* zero based */ for (intr = 0; intr < nintrs; ++intr) /* check each record */ if ((INTTYPE(intr) == 0) /* standard INT */ && (SRCBUSID(intr) == pciBus) && (SRCBUSDEVICE(intr) == pciDevice) && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ if (apic_int_is_bus_type(intr, PCI)) return INTPIN(intr); /* exact match */ return -1; /* NOT found */ } #undef SRCBUSLINE #undef SRCBUSDEVICE #undef SRCBUSID #undef INTPIN #undef INTTYPE /* * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. * * XXX FIXME: * Exactly what this means is unclear at this point. It is a solution * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard * could route any of the ISA INTs to upper (>15) IRQ values. But most would * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an * option. */ int undirect_isa_irq(int rirq) { #if defined(READY) printf("Freeing redirected ISA irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); return 0; #endif /* READY */ } /* * Reprogram the MB chipset to NOT redirect a PCI INTerrupt */ int undirect_pci_irq(int rirq) { #if defined(READY) if (bootverbose) printf("Freeing redirected PCI irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else if (bootverbose) printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); return 0; #endif /* READY */ } /* * given a bus ID, return: * the bus type if found * -1 if NOT found */ int apic_bus_type(int id) { int x; for (x = 0; x < mp_nbusses; ++x) if (bus_data[x].bus_id == id) return bus_data[x].bus_type; return -1; } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus ID if found * -1 if NOT found */ int apic_src_bus_id(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_id); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus IRQ if found * -1 if NOT found */ int apic_src_bus_irq(int apic, int pin) { int x; for (x = 0; x < nintrs; x++) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_irq); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated INTerrupt type if found * -1 if NOT found */ int apic_int_type(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_type); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated trigger mode if found * -1 if NOT found */ int apic_trigger(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return ((io_apic_ints[x].int_flags >> 2) & 0x03); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated 'active' level if found * -1 if NOT found */ int apic_polarity(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_flags & 0x03); return -1; /* NOT found */ } /* * set data according to MP defaults * FIXME: probably not complete yet... */ static void default_mp_table(int type) { int ap_cpu_id; #if defined(APIC_IO) u_int32_t ux; int io_apic_id; int pin; #endif /* APIC_IO */ #if 0 printf(" MP default config type: %d\n", type); switch (type) { case 1: printf(" bus: ISA, APIC: 82489DX\n"); break; case 2: printf(" bus: EISA, APIC: 82489DX\n"); break; case 3: printf(" bus: EISA, APIC: 82489DX\n"); break; case 4: printf(" bus: MCA, APIC: 82489DX\n"); break; case 5: printf(" bus: ISA+PCI, APIC: Integrated\n"); break; case 6: printf(" bus: EISA+PCI, APIC: Integrated\n"); break; case 7: printf(" bus: MCA+PCI, APIC: Integrated\n"); break; default: printf(" future type\n"); break; /* NOTREACHED */ } #endif /* 0 */ boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; /* BSP */ CPU_TO_ID(0) = boot_cpu_id; ID_TO_CPU(boot_cpu_id) = 0; /* one and only AP */ CPU_TO_ID(1) = ap_cpu_id; ID_TO_CPU(ap_cpu_id) = 1; #if defined(APIC_IO) /* one and only IO APIC */ io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; /* * sanity check, refer to MP spec section 3.6.6, last paragraph * necessary as some hardware isn't properly setting up the IO APIC */ #if defined(REALLY_ANAL_IOAPICID_VALUE) if (io_apic_id != 2) { #else if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { #endif /* REALLY_ANAL_IOAPICID_VALUE */ ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ ux &= ~APIC_ID_MASK; /* clear the ID field */ ux |= 0x02000000; /* set it to '2' */ io_apic_write(0, IOAPIC_ID, ux); /* write new value */ ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ if ((ux & APIC_ID_MASK) != 0x02000000) panic("can't control IO APIC ID, reg: 0x%08x", ux); io_apic_id = 2; } IO_TO_ID(0) = io_apic_id; ID_TO_IO(io_apic_id) = 0; #endif /* APIC_IO */ /* fill out bus entries */ switch (type) { case 1: case 2: case 3: case 5: case 6: bus_data[0].bus_id = default_data[type - 1][1]; bus_data[0].bus_type = default_data[type - 1][2]; bus_data[1].bus_id = default_data[type - 1][3]; bus_data[1].bus_type = default_data[type - 1][4]; break; /* case 4: case 7: MCA NOT supported */ default: /* illegal/reserved */ panic("BAD default MP config: %d", type); /* NOTREACHED */ } #if defined(APIC_IO) /* general cases from MP v1.4, table 5-2 */ for (pin = 0; pin < 16; ++pin) { io_apic_ints[pin].int_type = 0; io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ io_apic_ints[pin].src_bus_id = 0; io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ io_apic_ints[pin].dst_apic_id = io_apic_id; io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ } /* special cases from MP v1.4, table 5-2 */ if (type == 2) { io_apic_ints[2].int_type = 0xff; /* N/C */ io_apic_ints[13].int_type = 0xff; /* N/C */ #if !defined(APIC_MIXED_MODE) /** FIXME: ??? */ panic("sorry, can't support type 2 default yet"); #endif /* APIC_MIXED_MODE */ } else io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ if (type == 7) io_apic_ints[0].int_type = 0xff; /* N/C */ else io_apic_ints[0].int_type = 3; /* vectored 8259 */ #endif /* APIC_IO */ } /* * start each AP in our list */ static int start_all_aps(u_int boot_addr) { int x, i; u_char mpbiosreason; u_long mpbioswarmvec; pd_entry_t newptd; pt_entry_t newpt; int *newpp; POSTCODE(START_ALL_APS_POST); /** * NOTE: this needs further thought: * where does it get released? * should it be set to empy? * * get the initial mp_lock with a count of 1 for the BSP */ mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ /* initialize BSP's local APIC */ apic_initialize(); /* install the AP 1st level boot code */ install_ap_tramp(boot_addr); /* save the current value of the warm-start vector */ mpbioswarmvec = *((u_long *) WARMBOOT_OFF); outb(CMOS_REG, BIOS_RESET); mpbiosreason = inb(CMOS_DATA); /* record BSP in CPU map */ all_cpus = 1; /* start each AP */ for (x = 1; x <= mp_naps; ++x) { /* HACK HACK HACK !!! */ /* alloc new page table directory */ newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* clone currently active one (ie: IdlePTD) */ bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ /* set up 0 -> 4MB P==V mapping for AP boot */ newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); /* store PTD for this AP */ bootPTD = (pd_entry_t)vtophys(newptd); /* alloc new page table page */ newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* set the new PTD's private page to point there */ newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); /* install self referential entry */ newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); /* get a new private data page */ newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); /* wire it into the private page table page */ newpt[0] = PG_V | PG_RW | vtophys(newpp); /* wire the ptp into itself for access */ newpt[1] = PG_V | PG_RW | vtophys(newpt); /* and the local apic */ newpt[2] = SMP_prvpt[2]; /* and the IO apic mapping[s] */ for (i = 16; i < 32; i++) newpt[i] = SMP_prvpt[i]; /* prime data page for it to use */ newpp[0] = x; /* cpuid */ newpp[1] = 0; /* curproc */ newpp[2] = 0; /* curpcb */ newpp[3] = 0; /* npxproc */ newpp[4] = 0; /* runtime.tv_sec */ newpp[5] = 0; /* runtime.tv_usec */ newpp[6] = x << 24; /* cpu_lockid */ /* XXX NOTE: ABANDON bootPTD for now!!!! */ /* END REVOLTING HACKERY */ /* setup a vector to our boot code */ *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ /* attempt to start the Application Processor */ CHECK_INIT(99); /* setup checkpoints */ if (!start_ap(x, boot_addr)) { printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); CHECK_PRINT("trace"); /* show checkpoints */ /* better panic as the AP may be running loose */ printf("panic y/n? [y] "); if (cngetc() != 'n') panic("bye-bye"); } CHECK_PRINT("trace"); /* show checkpoints */ /* record its version info */ cpu_apic_versions[x] = cpu_apic_versions[0]; all_cpus |= (1 << x); /* record AP in CPU map */ } /* build our map of 'other' CPUs */ other_cpus = all_cpus & ~(1 << cpuid); /* fill in our (BSP) APIC version */ cpu_apic_versions[0] = lapic.version; /* restore the warmstart vector */ *(u_long *) WARMBOOT_OFF = mpbioswarmvec; outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, mpbiosreason); pmap_set_opt_bsp(); /* number of APs actually started */ return mp_ncpus - 1; } /* * load the 1st level AP boot code into base memory. */ /* targets for relocation */ extern void bigJump(void); extern void bootCodeSeg(void); extern void bootDataSeg(void); extern void MPentry(void); extern u_int MP_GDT; extern u_int mp_gdtbase; static void install_ap_tramp(u_int boot_addr) { int x; int size = *(int *) ((u_long) & bootMP_size); u_char *src = (u_char *) ((u_long) bootMP); u_char *dst = (u_char *) boot_addr + KERNBASE; u_int boot_base = (u_int) bootMP; u_int8_t *dst8; u_int16_t *dst16; u_int32_t *dst32; POSTCODE(INSTALL_AP_TRAMP_POST); for (x = 0; x < size; ++x) *dst++ = *src++; /* * modify addresses in code we just moved to basemem. unfortunately we * need fairly detailed info about mpboot.s for this to work. changes * to mpboot.s might require changes here. */ /* boot code is located in KERNEL space */ dst = (u_char *) boot_addr + KERNBASE; /* modify the lgdt arg */ dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); /* modify the ljmp target for MPentry() */ dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); *dst32 = ((u_int) MPentry - KERNBASE); /* modify the target for boot code segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; /* modify the target for boot data segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; } /* * this function starts the AP (application processor) identified * by the APIC ID 'physicalCpu'. It does quite a "song and dance" * to accomplish this. This is necessary because of the nuances * of the different hardware we might encounter. It ain't pretty, * but it seems to work. */ static int start_ap(int logical_cpu, u_int boot_addr) { int physical_cpu; int vector; int cpus; u_long icr_lo, icr_hi; POSTCODE(START_AP_POST); /* get the PHYSICAL APIC ID# */ physical_cpu = CPU_TO_ID(logical_cpu); /* calculate the vector */ vector = (boot_addr >> 12) & 0xff; /* used as a watchpoint to signal AP startup */ cpus = mp_ncpus; /* * first we do an INIT/RESET IPI this INIT IPI might be run, reseting * and running the target CPU. OR this INIT IPI might be latched (P5 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be * ignored. */ /* setup the address for the target AP */ icr_hi = lapic.icr_hi & ~APIC_ID_MASK; icr_hi |= (physical_cpu << 24); lapic.icr_hi = icr_hi; /* do an INIT IPI: assert RESET */ icr_lo = lapic.icr_lo & 0xfff00000; lapic.icr_lo = icr_lo | 0x0000c500; /* wait for pending status end */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* do an INIT IPI: deassert RESET */ lapic.icr_lo = icr_lo | 0x00008500; /* wait for pending status end */ u_sleep(10000); /* wait ~10mS */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* * next we do a STARTUP IPI: the previous INIT IPI might still be * latched, (P5 bug) this 1st STARTUP would then terminate * immediately, and the previously started INIT IPI would continue. OR * the previous INIT IPI has already run. and this STARTUP IPI will * run. OR the previous INIT IPI was ignored. and this STARTUP IPI * will run. */ /* do a STARTUP IPI */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is * recognized after hardware RESET or INIT IPI. */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* wait for it to start */ set_apic_timer(5000000);/* == 5 seconds */ while (read_apic_timer()) if (mp_ncpus > cpus) return 1; /* return SUCCESS */ return 0; /* return FAILURE */ } /* * Flush the TLB on all other CPU's * * XXX: Needs to handshake and wait for completion before proceding. */ void smp_invltlb(void) { #if defined(APIC_IO) if (smp_active && invltlb_ok) all_but_self_ipi(XINVLTLB_OFFSET); #endif /* APIC_IO */ } void invlpg(u_int addr) { __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); /* send a message to the other CPUs */ smp_invltlb(); } void invltlb(void) { u_long temp; /* * This should be implemented as load_cr3(rcr3()) when load_cr3() is * inlined. */ __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); /* send a message to the other CPUs */ smp_invltlb(); } -#if defined(TEST_CPUSTOP) - -#if defined(DEBUG_CPUSTOP) -void db_printf __P((const char *fmt, ...)); -#endif /* DEBUG_CPUSTOP */ - /* * When called the executing CPU will send an IPI to all other CPUs * requesting that they halt execution. * * Usually (but not necessarily) called with 'other_cpus' as its arg. * * - Signals all CPUs in map to stop. * - Waits for each to stop. * * Returns: * -1: error * 0: NA * 1: ok * * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs * from executing at same time. */ int stop_cpus( u_int map ) { if (!smp_active) return 0; /* send IPI to all CPUs in map */ -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); -#endif /* DEBUG_CPUSTOP */ - stopped_cpus = 0; /* send the Xcpustop IPI to all CPUs in map */ selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); -#if defined(DEBUG_CPUSTOP) - db_printf(" spin\n"); -#endif /* DEBUG_CPUSTOP */ - while (stopped_cpus != map) /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" spun\nstopped\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } /* * Called by a CPU to restart stopped CPUs. * * Usually (but not necessarily) called with 'stopped_cpus' as its arg. * * - Signals all CPUs in map to restart. * - Waits for each to restart. * * Returns: * -1: error * 0: NA * 1: ok */ int restart_cpus( u_int map ) { if (!smp_active) return 0; -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", - cpuid, map, stopped_cpus); -#endif /* DEBUG_CPUSTOP */ - started_cpus = map; /* signal other cpus to restart */ while (started_cpus) /* wait for each to clear its bit */ /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" restarted\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } - -#endif /** TEST_CPUSTOP */ Index: head/sys/amd64/include/apicreg.h =================================================================== --- head/sys/amd64/include/apicreg.h (revision 27516) +++ head/sys/amd64/include/apicreg.h (revision 27517) @@ -1,466 +1,469 @@ /* * Copyright (c) 1996, by Peter Wemm and Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: apic.h,v 1.7 1997/07/15 02:47:52 fsmp Exp $ + * $Id: apic.h,v 1.5 1997/07/18 19:47:48 smp Exp smp $ */ #ifndef _MACHINE_APIC_H_ #define _MACHINE_APIC_H_ /* * Local && I/O APIC definitions. */ /* * Pentium P54C+ Build-in APIC * (Advanced programmable Interrupt Controller) * * Base Address of Build-in APIC in memory location * is 0xfee00000. * * Map of APIC REgisters: * * Offset (hex) Description Read/Write state * 000 Reserved * 010 Reserved * 020 ID Local APIC ID R/W * 030 VER Local APIC Version R * 040 Reserved * 050 Reserved * 060 Reserved * 070 Reserved * 080 Task Priority Register R/W * 090 Arbitration Priority Register R * 0A0 Processor Priority Register R * 0B0 EOI Register W * 0C0 RRR Remote read R * 0D0 Logical Destination R/W * 0E0 Destination Format Register 0..27 R; 28..31 R/W * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W * 100 ISR 000-031 R * 110 ISR 032-063 R * 120 ISR 064-095 R * 130 ISR 095-128 R * 140 ISR 128-159 R * 150 ISR 160-191 R * 160 ISR 192-223 R * 170 ISR 224-255 R * 180 TMR 000-031 R * 190 TMR 032-063 R * 1A0 TMR 064-095 R * 1B0 TMR 095-128 R * 1C0 TMR 128-159 R * 1D0 TMR 160-191 R * 1E0 TMR 192-223 R * 1F0 TMR 224-255 R * 200 IRR 000-031 R * 210 IRR 032-063 R * 220 IRR 064-095 R * 230 IRR 095-128 R * 240 IRR 128-159 R * 250 IRR 160-191 R * 260 IRR 192-223 R * 270 IRR 224-255 R * 280 Error Status Register R * 290 Reserved * 2A0 Reserved * 2B0 Reserved * 2C0 Reserved * 2D0 Reserved * 2E0 Reserved * 2F0 Reserved * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W * 310 ICR_HI Interrupt Command Reg. (32-63) R/W * 320 Local Vector Table (Timer) R/W * 330 Reserved * 340 Reserved * 350 LVT1 Local Vector Table (LINT0) R/W * 360 LVT2 Local Vector Table (LINT1) R/W * 370 LVT3 Local Vector Table (ERROR) R/W * 380 Initial Count Reg. for Timer R/W * 390 Current Count of Timer R * 3A0 Reserved * 3B0 Reserved * 3C0 Reserved * 3D0 Reserved * 3E0 Timer Divide Configuration Reg. R/W * 3F0 Reserved */ /****************************************************************************** * global defines, etc. */ /** * this enables code concerned with handling more than one IO APIC. * Note: this is NOT READY for use! * #define MULTIPLE_IOAPICS */ /****************************************************************************** * LOCAL APIC structure */ #ifndef LOCORE #include #define PAD3 int : 32; int : 32; int : 32 #define PAD4 int : 32; int : 32; int : 32; int : 32 struct LAPIC { /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t id; PAD3; u_int32_t version; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t tpr; PAD3; u_int32_t apr; PAD3; u_int32_t ppr; PAD3; u_int32_t eoi; PAD3; /* reserved */ PAD4; u_int32_t ldr; PAD3; u_int32_t dfr; PAD3; u_int32_t svr; PAD3; u_int32_t isr0; PAD3; u_int32_t isr1; PAD3; u_int32_t isr2; PAD3; u_int32_t isr3; PAD3; u_int32_t isr4; PAD3; u_int32_t isr5; PAD3; u_int32_t isr6; PAD3; u_int32_t isr7; PAD3; u_int32_t tmr0; PAD3; u_int32_t tmr1; PAD3; u_int32_t tmr2; PAD3; u_int32_t tmr3; PAD3; u_int32_t tmr4; PAD3; u_int32_t tmr5; PAD3; u_int32_t tmr6; PAD3; u_int32_t tmr7; PAD3; u_int32_t irr0; PAD3; u_int32_t irr1; PAD3; u_int32_t irr2; PAD3; u_int32_t irr3; PAD3; u_int32_t irr4; PAD3; u_int32_t irr5; PAD3; u_int32_t irr6; PAD3; u_int32_t irr7; PAD3; u_int32_t esr; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t icr_lo; PAD3; u_int32_t icr_hi; PAD3; u_int32_t lvt_timer; PAD3; /* reserved */ PAD4; u_int32_t lvt_pcint; PAD3; u_int32_t lvt_lint0; PAD3; u_int32_t lvt_lint1; PAD3; u_int32_t lvt_error; PAD3; u_int32_t icr_timer; PAD3; u_int32_t ccr_timer; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t dcr_timer; PAD3; /* reserved */ PAD4; }; typedef struct LAPIC lapic_t; /****************************************************************************** * I/O APIC structure */ struct IOAPIC { u_int32_t ioregsel; PAD3; u_int32_t iowin; PAD3; }; typedef struct IOAPIC ioapic_t; #undef PAD4 #undef PAD3 #endif /* !LOCORE */ /****************************************************************************** * various code 'logical' values */ +#ifdef TEST_LOPRIO #define LOPRIO_LEVEL 0x00000010 /* TPR of CPUs accepting INT */ +#define ALLHWI_LEVEL 0x00000000 /* TPR of CPU grabbing INTs */ +#endif /** TEST_LOPRIO */ /* XXX these 2 don't really belong here... */ #define COUNT_FIELD 0x00ffffff /* count portion of the lock */ #define FREE_LOCK 0xffffffff /* value of lock when free */ /* * XXX This code assummes that the reserved field of the * local APIC TPR can be written with all 0s. * This saves quite a few memory accesses. * If the silicon ever changes then things will break! * It affects mplock.s, swtch.s, and possibly other files. */ #define CHEAP_TPR /****************************************************************************** * LOCAL APIC defines */ /* default physical locations of LOCAL (CPU) APICs */ #define DEFAULT_APIC_BASE 0xfee00000 /* fields in VER */ #define APIC_VER_VERSION 0x000000ff #define APIC_VER_MAXLVT 0x00ff0000 #define MAXLVTSHIFT 16 /* fields in SVR */ #define APIC_SVR_VECTOR 0x000000ff #define APIC_SVR_VEC_PROG 0x000000f0 #define APIC_SVR_VEC_FIX 0x0000000f #define APIC_SVR_ENABLE 0x00000100 # define APIC_SVR_SWDIS 0x00000000 # define APIC_SVR_SWEN 0x00000100 #define APIC_SVR_FOCUS 0x00000200 # define APIC_SVR_FEN 0x00000000 # define APIC_SVR_FDIS 0x00000200 /* fields in TPR */ #define APIC_TPR_PRIO 0x000000ff # define APIC_TPR_INT 0x000000f0 # define APIC_TPR_SUB 0x0000000f /* fields in ICR_LOW */ #define APIC_VECTOR_MASK 0x000000ff #define APIC_DELMODE_MASK 0x00000700 # define APIC_DELMODE_FIXED 0x00000000 # define APIC_DELMODE_LOWPRIO 0x00000100 # define APIC_DELMODE_SMI 0x00000200 # define APIC_DELMODE_RR 0x00000300 # define APIC_DELMODE_NMI 0x00000400 # define APIC_DELMODE_INIT 0x00000500 # define APIC_DELMODE_STARTUP 0x00000600 # define APIC_DELMODE_RESV 0x00000700 #define APIC_DESTMODE_MASK 0x00000800 # define APIC_DESTMODE_PHY 0x00000000 # define APIC_DESTMODE_LOG 0x00000800 #define APIC_DELSTAT_MASK 0x00001000 # define APIC_DELSTAT_IDLE 0x00000000 # define APIC_DELSTAT_PEND 0x00001000 #define APIC_RESV1_MASK 0x00002000 #define APIC_LEVEL_MASK 0x00004000 # define APIC_LEVEL_DEASSERT 0x00000000 # define APIC_LEVEL_ASSERT 0x00004000 #define APIC_TRIGMOD_MASK 0x00008000 # define APIC_TRIGMOD_EDGE 0x00000000 # define APIC_TRIGMOD_LEVEL 0x00008000 #define APIC_RRSTAT_MASK 0x00030000 # define APIC_RRSTAT_INVALID 0x00000000 # define APIC_RRSTAT_INPROG 0x00010000 # define APIC_RRSTAT_VALID 0x00020000 # define APIC_RRSTAT_RESV 0x00030000 #define APIC_DEST_MASK 0x000c0000 # define APIC_DEST_DESTFLD 0x00000000 # define APIC_DEST_SELF 0x00040000 # define APIC_DEST_ALLISELF 0x00080000 # define APIC_DEST_ALLESELF 0x000c0000 #define APIC_RESV2_MASK 0xfff00000 /* fields in ICR_HIGH */ #define APIC_ID_MASK 0x0f000000 /* fields in LVT1/2 */ #define APIC_LVT_VECTOR 0x000000ff #define APIC_LVT_DM 0x00000700 # define APIC_LVT_DM_FIXED 0x00000000 # define APIC_LVT_DM_NMI 0x00000400 # define APIC_LVT_DM_EXTINT 0x00000700 #define APIC_LVT_DS 0x00001000 #define APIC_LVT_IIPP 0x00002000 #define APIC_LVT_IIPP_INTALO 0x00002000 #define APIC_LVT_IIPP_INTAHI 0x00000000 #define APIC_LVT_RIRR 0x00004000 #define APIC_LVT_TM 0x00008000 #define APIC_LVT_M 0x00010000 /* fields in LVT Timer */ #define APIC_LVTT_VECTOR 0x000000ff #define APIC_LVTT_DS 0x00001000 #define APIC_LVTT_M 0x00010000 #define APIC_LVTT_TM 0x00020000 /* fields in TDCR */ #define APIC_TDCR_2 0x00 #define APIC_TDCR_4 0x01 #define APIC_TDCR_8 0x02 #define APIC_TDCR_16 0x03 #define APIC_TDCR_32 0x08 #define APIC_TDCR_64 0x09 #define APIC_TDCR_128 0x0a #define APIC_TDCR_1 0x0b /* * fields in IRR * ISA INTerrupts are in bits 16-31 of the 1st IRR register. * these masks DON'T EQUAL the isa IRQs of the same name. */ #define APIC_IRQ0 0x00000001 #define APIC_IRQ1 0x00000002 #define APIC_IRQ2 0x00000004 #define APIC_IRQ3 0x00000008 #define APIC_IRQ4 0x00000010 #define APIC_IRQ5 0x00000020 #define APIC_IRQ6 0x00000040 #define APIC_IRQ7 0x00000080 #define APIC_IRQ8 0x00000100 #define APIC_IRQ9 0x00000200 #define APIC_IRQ10 0x00000400 #define APIC_IRQ11 0x00000800 #define APIC_IRQ12 0x00001000 #define APIC_IRQ13 0x00002000 #define APIC_IRQ14 0x00004000 #define APIC_IRQ15 0x00008000 #define APIC_IRQ16 0x00010000 #define APIC_IRQ17 0x00020000 #define APIC_IRQ18 0x00040000 #define APIC_IRQ19 0x00080000 #define APIC_IRQ20 0x00100000 #define APIC_IRQ21 0x00200000 #define APIC_IRQ22 0x00400000 #define APIC_IRQ23 0x00800000 /****************************************************************************** * I/O APIC defines */ /* default physical locations of an IO APIC */ #define DEFAULT_IO_APIC_BASE 0xfec00000 /* window register offset */ #define IOAPIC_WINDOW 0x10 /* indexes into IO APIC */ #define IOAPIC_ID 0x00 #define IOAPIC_VER 0x01 #define IOAPIC_ARB 0x02 #define IOAPIC_REDTBL 0x10 #define IOAPIC_REDTBL0 IOAPIC_REDTBL #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) /* fields in VER */ #define IOART_VER_VERSION 0x000000ff #define IOART_VER_MAXREDIR 0x00ff0000 #define MAXREDIRSHIFT 16 /* * fields in the IO APIC's redirection table entries */ #define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */ #define IOART_RESV 0x00fe0000 /* reserved */ #define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */ # define IOART_INTMCLR 0x00000000 /* clear, allow INTs */ # define IOART_INTMSET 0x00010000 /* set, inhibit INTs */ #define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */ # define IOART_TRGREDG 0x00000000 /* edge */ # define IOART_TRGRLVL 0x00008000 /* level */ #define IOART_REM_IRR 0x00004000 /* RO: remote IRR */ #define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */ # define IOART_INTAHI 0x00000000 /* active high */ # define IOART_INTALO 0x00002000 /* active low */ #define IOART_DELIVS 0x00001000 /* RO: delivery status */ #define IOART_DESTMOD 0x00000800 /* R/W: destination mode */ # define IOART_DESTPHY 0x00000000 /* physical */ # define IOART_DESTLOG 0x00000800 /* logical */ #define IOART_DELMOD 0x00000700 /* R/W: delivery mode */ # define IOART_DELFIXED 0x00000000 /* fixed */ # define IOART_DELLOPRI 0x00000100 /* lowest priority */ # define IOART_DELSMI 0x00000200 /* System Management INT */ # define IOART_DELRSV1 0x00000300 /* reserved */ # define IOART_DELNMI 0x00000400 /* NMI signal */ # define IOART_DELINIT 0x00000500 /* INIT signal */ # define IOART_DELRSV2 0x00000600 /* reserved */ # define IOART_DELEXINT 0x00000700 /* External INTerrupt */ #define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */ #endif /* _MACHINE_APIC_H_ */ Index: head/sys/amd64/include/mptable.h =================================================================== --- head/sys/amd64/include/mptable.h (revision 27516) +++ head/sys/amd64/include/mptable.h (revision 27517) @@ -1,1834 +1,1803 @@ /* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: mp_machdep.c,v 1.28 1997/07/17 19:44:56 dyson Exp $ + * $Id: mp_machdep.c,v 1.16 1997/07/18 19:45:41 smp Exp smp $ */ #include "opt_smp.h" #include /* for KERNBASE */ #include #include #include #include #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include #include #include #include #include #include #include -#include /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP _TEST1 */ +#include /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ #include #include #include /* cngetc() */ #if defined(APIC_IO) #include /* setidt() */ #include /* IPIs */ #include /* IPIs */ #endif /* APIC_IO */ #define WARMBOOT_TARGET 0 #define WARMBOOT_OFF (KERNBASE + 0x0467) #define WARMBOOT_SEG (KERNBASE + 0x0469) #define BIOS_BASE (0xf0000) #define BIOS_SIZE (0x10000) #define BIOS_COUNT (BIOS_SIZE/4) #define CMOS_REG (0x70) #define CMOS_DATA (0x71) #define BIOS_RESET (0x0f) #define BIOS_WARM (0x0a) #define PROCENTRY_FLAG_EN 0x01 #define PROCENTRY_FLAG_BP 0x02 #define IOAPICENTRY_FLAG_EN 0x01 /* MP Floating Pointer Structure */ typedef struct MPFPS { char signature[4]; void *pap; u_char length; u_char spec_rev; u_char checksum; u_char mpfb1; u_char mpfb2; u_char mpfb3; u_char mpfb4; u_char mpfb5; } *mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { char signature[4]; u_short base_table_length; u_char spec_rev; u_char checksum; u_char oem_id[8]; u_char product_id[12]; void *oem_table_pointer; u_short oem_table_size; u_short entry_count; void *apic_address; u_short extended_table_length; u_char extended_table_checksum; u_char reserved; } *mpcth_t; typedef struct PROCENTRY { u_char type; u_char apic_id; u_char apic_version; u_char cpu_flags; u_long cpu_signature; u_long feature_flags; u_long reserved1; u_long reserved2; } *proc_entry_ptr; typedef struct BUSENTRY { u_char type; u_char bus_id; char bus_type[6]; } *bus_entry_ptr; typedef struct IOAPICENTRY { u_char type; u_char apic_id; u_char apic_version; u_char apic_flags; void *apic_address; } *io_apic_entry_ptr; typedef struct INTENTRY { u_char type; u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } *int_entry_ptr; /* descriptions of MP basetable entries */ typedef struct BASETABLE_ENTRY { u_char type; u_char length; char name[16]; } basetable_entry; /* * this code MUST be enabled here and in mpboot.s. * it follows the very early stages of AP boot by placing values in CMOS ram. * it NORMALLY will never be needed and thus the primitive method for enabling. * #define CHECK_POINTS */ #if defined(CHECK_POINTS) #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) #define CHECK_INIT(D); \ CHECK_WRITE(0x34, (D)); \ CHECK_WRITE(0x35, (D)); \ CHECK_WRITE(0x36, (D)); \ CHECK_WRITE(0x37, (D)); \ CHECK_WRITE(0x38, (D)); \ CHECK_WRITE(0x39, (D)); #define CHECK_PRINT(S); \ printf("%s: %d, %d, %d, %d, %d, %d\n", \ (S), \ CHECK_READ(0x34), \ CHECK_READ(0x35), \ CHECK_READ(0x36), \ CHECK_READ(0x37), \ CHECK_READ(0x38), \ CHECK_READ(0x39)); #else /* CHECK_POINTS */ #define CHECK_INIT(D) #define CHECK_PRINT(S) #endif /* CHECK_POINTS */ /* * Values to send to the POST hardware. */ #define MP_BOOTADDRESS_POST 0x10 #define MP_PROBE_POST 0x11 #define MP_START_POST 0x12 #define MP_ANNOUNCE_POST 0x13 #define MPTABLE_PASS1_POST 0x14 #define MPTABLE_PASS2_POST 0x15 #define MP_ENABLE_POST 0x16 #define START_ALL_APS_POST 0x17 #define INSTALL_AP_TRAMP_POST 0x18 #define START_AP_POST 0x19 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ int current_postcode; /** XXX FIXME: what system files declare these??? */ extern struct region_descriptor r_gdt, r_idt; int mp_ncpus; /* # of CPUs, including BSP */ int mp_naps; /* # of Applications processors */ int mp_nbusses; /* # of busses */ int mp_napics; /* # of IO APICs */ int boot_cpu_id; /* designated BSP */ vm_offset_t cpu_apic_address; vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ u_int32_t cpu_apic_versions[NCPU]; u_int32_t io_apic_versions[NAPIC]; /* * APIC ID logical/physical mapping structures. * We oversize these to simplify boot-time config. */ int cpu_num_to_apic_id[NAPICID]; int io_num_to_apic_id[NAPICID]; int apic_id_to_logical[NAPICID]; /* Bitmap of all available CPUs */ u_int all_cpus; /* Boot of AP uses this PTD */ u_int *bootPTD; /* Hotwire a 0->4MB V==P mapping */ extern pt_entry_t KPTphys; /* Virtual address of per-cpu common_tss */ extern struct i386tss common_tss; /* * Local data and functions. */ static int mp_capable; static u_int boot_address; static u_int base_memory; static int picmode; /* 0: virtual wire mode, 1: PIC mode */ static mpfps_t mpfps; static int search_for_sig(u_int32_t target, int count); static void mp_enable(u_int boot_addr); static int mptable_pass1(void); static int mptable_pass2(void); static void default_mp_table(int type); static int start_all_aps(u_int boot_addr); static void install_ap_tramp(u_int boot_addr); static int start_ap(int logicalCpu, u_int boot_addr); /* * Calculate usable address in base memory for AP trampoline code. */ u_int mp_bootaddress(u_int basemem) { POSTCODE(MP_BOOTADDRESS_POST); base_memory = basemem * 1024; /* convert to bytes */ boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ if ((base_memory - boot_address) < bootMP_size) boot_address -= 4096; /* not enough, lower by 4k */ return boot_address; } /* * Look for an Intel MP spec table (ie, SMP capable hardware). */ int mp_probe(void) { int x; u_long segment; u_int32_t target; POSTCODE(MP_PROBE_POST); /* see if EBDA exists */ if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { /* search first 1K of EBDA */ target = (u_int32_t) (segment << 4); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } else { /* last 1K of base memory, effective 'top of base' passed in */ target = (u_int32_t) (base_memory - 0x400); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } /* search the BIOS */ target = (u_int32_t) BIOS_BASE; if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) goto found; /* nothing found */ mpfps = (mpfps_t)0; mp_capable = 0; return 0; found: /* calculate needed resources */ mpfps = (mpfps_t)x; if (mptable_pass1()) panic("you must reconfigure your kernel"); /* flag fact that we are running multiple processors */ mp_capable = 1; return 1; } /* * Startup the SMP processors. */ void mp_start(void) { POSTCODE(MP_START_POST); /* look for MP capable motherboard */ if (mp_capable) mp_enable(boot_address); else panic("MP hardware not found!"); } /* * Print various information about the SMP system hardware and setup. */ void mp_announce(void) { int x; POSTCODE(MP_ANNOUNCE_POST); printf("FreeBSD/SMP: Multiprocessor motherboard\n"); printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); printf(", version: 0x%08x", cpu_apic_versions[0]); printf(", at 0x%08x\n", cpu_apic_address); for (x = 1; x <= mp_naps; ++x) { printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); printf(", version: 0x%08x", cpu_apic_versions[x]); printf(", at 0x%08x\n", cpu_apic_address); } #if defined(APIC_IO) for (x = 0; x < mp_napics; ++x) { printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); printf(", version: 0x%08x", io_apic_versions[x]); printf(", at 0x%08x\n", io_apic_address[x]); } #else printf(" Warning: APIC I/O disabled\n"); #endif /* APIC_IO */ } /* * AP cpu's call this to sync up protected mode. */ void init_secondary(void) { int gsel_tss, slot; r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; r_gdt.rd_base = (int) gdt; lgdt(&r_gdt); /* does magic intra-segment return */ lidt(&r_idt); lldt(_default_ldt); slot = NGDT + cpuid; gsel_tss = GSEL(slot, SEL_KPL); gdt[slot].sd.sd_type = SDT_SYS386TSS; common_tss.tss_esp0 = 0; /* not used until after switch */ common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); common_tss.tss_ioopt = (sizeof common_tss) << 16; ltr(gsel_tss); load_cr0(0x8005003b); /* XXX! */ PTD[0] = 0; pmap_set_opt((unsigned *)PTD); invltlb(); } #if defined(APIC_IO) /* * Final configuration of the BSP's local APIC: * - disable 'pic mode'. * - disable 'virtual wire mode'. * - enable NMI. */ void bsp_apic_configure(void) { u_char byte; u_int32_t temp; /* leave 'pic mode' if necessary */ if (picmode) { outb(0x22, 0x70); /* select IMCR */ byte = inb(0x23); /* current contents */ byte |= 0x01; /* mask external INTR */ outb(0x23, byte); /* disconnect 8259s/NMI */ } /* mask lint0 (the 8259 'virtual wire' connection) */ temp = lapic.lvt_lint0; temp |= APIC_LVT_M; /* set the mask */ lapic.lvt_lint0 = temp; /* setup lint1 to handle NMI */ temp = lapic.lvt_lint1; temp &= ~APIC_LVT_M; /* clear the mask */ lapic.lvt_lint1 = temp; if (bootverbose) apic_dump(); } #endif /* APIC_IO */ /******************************************************************* * local functions and data */ /* * start the SMP system */ static void mp_enable(u_int boot_addr) { int x; #if defined(APIC_IO) int apic; u_int ux; #endif /* APIC_IO */ POSTCODE(MP_ENABLE_POST); /* turn on 4MB of V == P addressing so we can get to MP table */ *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); invltlb(); /* examine the MP table for needed info, uses physical addresses */ x = mptable_pass2(); *(int *)PTD = 0; invltlb(); /* can't process default configs till the CPU APIC is pmapped */ if (x) default_mp_table(x); #if defined(APIC_IO) /* fill the LOGICAL io_apic_versions table */ for (apic = 0; apic < mp_napics; ++apic) { ux = io_apic_read(apic, IOAPIC_VER); io_apic_versions[apic] = ux; } /* program each IO APIC in the system */ for (apic = 0; apic < mp_napics; ++apic) if (io_apic_setup(apic) < 0) panic("IO APIC setup failure"); /* install a 'Spurious INTerrupt' vector */ setidt(XSPURIOUSINT_OFFSET, Xspuriousint, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); /* install an inter-CPU IPI for TLB invalidation */ setidt(XINVLTLB_OFFSET, Xinvltlb, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#if defined(TEST_CPUSTOP) /* install an inter-CPU IPI for CPU stop/restart */ setidt(XCPUSTOP_OFFSET, Xcpustop, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#endif /** TEST_CPUSTOP */ #if defined(TEST_TEST1) - /* install a 'Spurious INTerrupt' vector */ + /* install a "fake hardware INTerrupt" vector */ setidt(XTEST1_OFFSET, Xtest1, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /** TEST_TEST1 */ #endif /* APIC_IO */ /* start each Application Processor */ start_all_aps(boot_addr); /* * The init process might be started on a different CPU now, * and the boot CPU might not call prepare_usermode to get * cr0 correctly configured. Thus we initialize cr0 here. */ load_cr0(rcr0() | CR0_WP | CR0_AM); } /* * look for the MP spec signature */ /* string defined by the Intel MP Spec as identifying the MP table */ #define MP_SIG 0x5f504d5f /* _MP_ */ #define NEXT(X) ((X) += 4) static int search_for_sig(u_int32_t target, int count) { int x; u_int32_t *addr = (u_int32_t *) (KERNBASE + target); for (x = 0; x < count; NEXT(x)) if (addr[x] == MP_SIG) /* make array index a byte index */ return (target + (x * sizeof(u_int32_t))); return -1; } static basetable_entry basetable_entry_types[] = { {0, 20, "Processor"}, {1, 8, "Bus"}, {2, 8, "I/O APIC"}, {3, 8, "I/O INT"}, {4, 8, "Local INT"} }; typedef struct BUSDATA { u_char bus_id; enum busTypes bus_type; } bus_datum; typedef struct INTDATA { u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } io_int, local_int; typedef struct BUSTYPENAME { u_char type; char name[7]; } bus_type_name; static bus_type_name bus_type_table[] = { {CBUS, "CBUS"}, {CBUSII, "CBUSII"}, {EISA, "EISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {ISA, "ISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {PCI, "PCI"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {XPRESS, "XPRESS"}, {UNKNOWN_BUSTYPE, "---"} }; /* from MP spec v1.4, table 5-1 */ static int default_data[7][5] = { /* nbus, id0, type0, id1, type1 */ {1, 0, ISA, 255, 255}, {1, 0, EISA, 255, 255}, {1, 0, EISA, 255, 255}, {0, 255, 255, 255, 255},/* MCA not supported */ {2, 0, ISA, 1, PCI}, {2, 0, EISA, 1, PCI}, {0, 255, 255, 255, 255} /* MCA not supported */ }; /* the bus data */ bus_datum bus_data[NBUS]; /* the IO INT data, one entry per possible APIC INTerrupt */ io_int io_apic_ints[NINTR]; static int nintrs; static void fix_mp_table __P((void)); static int processor_entry __P((proc_entry_ptr entry, int cpu)); static int bus_entry __P((bus_entry_ptr entry, int bus)); static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); static int int_entry __P((int_entry_ptr entry, int intr)); static int lookup_bus_type __P((char *name)); /* * 1st pass on motherboard's Intel MP specification table. * * initializes: * mp_ncpus = 1 * * determines: * cpu_apic_address (common to all CPUs) * io_apic_address[N] * mp_naps * mp_nbusses * mp_napics * nintrs */ static int mptable_pass1(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int mustpanic; POSTCODE(MPTABLE_PASS1_POST); mustpanic = 0; /* clear various tables */ for (x = 0; x < NAPICID; ++x) { io_apic_address[x] = ~0; /* IO APIC address table */ } /* init everything to empty */ mp_naps = 0; mp_nbusses = 0; mp_napics = 0; nintrs = 0; /* check for use of 'default' configuration */ if (mpfps->mpfb1 != 0) { /* use default addresses */ cpu_apic_address = DEFAULT_APIC_BASE; io_apic_address[0] = DEFAULT_IO_APIC_BASE; /* fill in with defaults */ mp_naps = 2; /* includes BSP */ mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; #if defined(APIC_IO) mp_napics = 1; nintrs = 16; #endif /* APIC_IO */ } else { if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); cpu_apic_address = (vm_offset_t) cth->apic_address; /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; while (count--) { switch (type = *(u_char *) position) { case 0: /* processor_entry */ if (((proc_entry_ptr)position)->cpu_flags & PROCENTRY_FLAG_EN) ++mp_naps; break; case 1: /* bus_entry */ ++mp_nbusses; break; case 2: /* io_apic_entry */ if (((io_apic_entry_ptr)position)->apic_flags & IOAPICENTRY_FLAG_EN) io_apic_address[mp_napics++] = (vm_offset_t)((io_apic_entry_ptr) position)->apic_address; break; case 3: /* int_entry */ ++nintrs; break; case 4: /* int_entry */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char*)position += basetable_entry_types[type].length; } } /* qualify the numbers */ if (mp_naps > NCPU) printf("Warning: only using %d of %d available CPUs!\n", NCPU, mp_naps); #if 0 /** XXX we consider this legal now (but should we?) */ mustpanic = 1; #endif if (mp_nbusses > NBUS) { printf("found %d busses, increase NBUS\n", mp_nbusses); mustpanic = 1; } if (mp_napics > NAPIC) { printf("found %d apics, increase NAPIC\n", mp_napics); mustpanic = 1; } if (nintrs > NINTR) { printf("found %d intrs, increase NINTR\n", nintrs); mustpanic = 1; } /* * Count the BSP. * This is also used as a counter while starting the APs. */ mp_ncpus = 1; --mp_naps; /* subtract the BSP */ return mustpanic; } /* * 2nd pass on motherboard's Intel MP specification table. * * sets: * boot_cpu_id * ID_TO_IO(N), phy APIC ID to log CPU/IO table * CPU_TO_ID(N), logical CPU to APIC ID table * IO_TO_ID(N), logical IO to APIC ID table * bus_data[N] * io_apic_ints[N] */ static int mptable_pass2(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int apic, bus, cpu, intr; POSTCODE(MPTABLE_PASS2_POST); /* clear various tables */ for (x = 0; x < NAPICID; ++x) { ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ } /* clear bus data table */ for (x = 0; x < NBUS; ++x) bus_data[x].bus_id = 0xff; /* clear IO APIC INT table */ for (x = 0; x < NINTR; ++x) io_apic_ints[x].int_type = 0xff; /* setup the cpu/apic mapping arrays */ boot_cpu_id = -1; /* record whether PIC or virtual-wire mode */ picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; /* check for use of 'default' configuration */ #if defined(TEST_DEFAULT_CONFIG) return TEST_DEFAULT_CONFIG; #else if (mpfps->mpfb1 != 0) return mpfps->mpfb1; /* return default configuration type */ #endif /* TEST_DEFAULT_CONFIG */ if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; apic = bus = intr = 0; cpu = 1; /* pre-count the BSP */ while (count--) { switch (type = *(u_char *) position) { case 0: if (processor_entry(position, cpu)) ++cpu; break; case 1: if (bus_entry(position, bus)) ++bus; break; case 2: if (io_apic_entry(position, apic)) ++apic; break; case 3: if (int_entry(position, intr)) ++intr; break; case 4: /* int_entry(position); */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char *) position += basetable_entry_types[type].length; } if (boot_cpu_id == -1) panic("NO BSP found!"); /* post scan cleanup */ fix_mp_table(); /* report fact that its NOT a default configuration */ return 0; } /* * parse an Intel MP specification table */ static void fix_mp_table(void) { int x; int id; int bus_0; int bus_pci; int num_pci_bus; /* * Fix mis-numbering of the PCI bus and its INT entries if the BIOS * did it wrong. The MP spec says that when more than 1 PCI bus * exists the BIOS must begin with bus entries for the PCI bus and use * actual PCI bus numbering. This implies that when only 1 PCI bus * exists the BIOS can choose to ignore this ordering, and indeed many * MP motherboards do ignore it. This causes a problem when the PCI * sub-system makes requests of the MP sub-system based on PCI bus * numbers. So here we look for the situation and renumber the * busses and associated INTs in an effort to "make it right". */ /* find bus 0, PCI bus, count the number of PCI busses */ for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_id == 0) { bus_0 = x; } if (bus_data[x].bus_type == PCI) { ++num_pci_bus; bus_pci = x; } } /* * bus_0 == slot of bus with ID of 0 * bus_pci == slot of last PCI bus encountered */ /* check the 1 PCI bus case for sanity */ if (num_pci_bus == 1) { /* if it is number 0 all is well */ if (bus_data[bus_pci].bus_id == 0) return; /* mis-numbered, swap with whichever bus uses slot 0 */ /* swap the bus entry types */ bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; bus_data[bus_0].bus_type = PCI; /* swap each relavant INTerrupt entry */ id = bus_data[bus_pci].bus_id; for (x = 0; x < nintrs; ++x) { if (io_apic_ints[x].src_bus_id == id) { io_apic_ints[x].src_bus_id = 0; } else if (io_apic_ints[x].src_bus_id == 0) { io_apic_ints[x].src_bus_id = id; } } } /* sanity check if more than 1 PCI bus */ else if (num_pci_bus > 1) { for (x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_type != PCI) continue; if (bus_data[x].bus_id >= num_pci_bus) panic("bad PCI bus numbering"); } } } static int processor_entry(proc_entry_ptr entry, int cpu) { /* check for usability */ if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) return 0; /* check for BSP flag */ if (entry->cpu_flags & PROCENTRY_FLAG_BP) { boot_cpu_id = entry->apic_id; CPU_TO_ID(0) = entry->apic_id; ID_TO_CPU(entry->apic_id) = 0; return 0; /* its already been counted */ } /* add another AP to list, if less than max number of CPUs */ else { CPU_TO_ID(cpu) = entry->apic_id; ID_TO_CPU(entry->apic_id) = cpu; return 1; } } static int bus_entry(bus_entry_ptr entry, int bus) { int x; char c, name[8]; /* encode the name into an index */ for (x = 0; x < 6; ++x) { if ((c = entry->bus_type[x]) == ' ') break; name[x] = c; } name[x] = '\0'; if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) panic("unknown bus type: '%s'", name); bus_data[bus].bus_id = entry->bus_id; bus_data[bus].bus_type = x; return 1; } static int io_apic_entry(io_apic_entry_ptr entry, int apic) { if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) return 0; IO_TO_ID(apic) = entry->apic_id; ID_TO_IO(entry->apic_id) = apic; return 1; } static int lookup_bus_type(char *name) { int x; for (x = 0; x < MAX_BUSTYPE; ++x) if (strcmp(bus_type_table[x].name, name) == 0) return bus_type_table[x].type; return UNKNOWN_BUSTYPE; } static int int_entry(int_entry_ptr entry, int intr) { io_apic_ints[intr].int_type = entry->int_type; io_apic_ints[intr].int_flags = entry->int_flags; io_apic_ints[intr].src_bus_id = entry->src_bus_id; io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; return 1; } static int apic_int_is_bus_type(int intr, int bus_type) { int bus; for (bus = 0; bus < mp_nbusses; ++bus) if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) && ((int) bus_data[bus].bus_type == bus_type)) return 1; return 0; } /* * Given a traditional ISA INT mask, return an APIC mask. */ u_int isa_apic_mask(u_int isa_mask) { int isa_irq; int apic_pin; #if defined(SKIP_IRQ15_REDIRECT) if (isa_mask == (1 << 15)) { printf("skipping ISA IRQ15 redirect\n"); return isa_mask; } #endif /* SKIP_IRQ15_REDIRECT */ isa_irq = ffs(isa_mask); /* find its bit position */ if (isa_irq == 0) /* doesn't exist */ return 0; --isa_irq; /* make it zero based */ apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ if (apic_pin == -1) return 0; return (1 << apic_pin); /* convert pin# to a mask */ } /* * Determine which APIC pin an ISA/EISA INT is attached to. */ #define INTTYPE(I) (io_apic_ints[(I)].int_type) #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) int isa_apic_pin(int isa_irq) { int intr; #if defined(SMP_TIMER_NC) if (isa_irq == 0) return -1; #endif /* SMP_TIMER_NC */ for (intr = 0; intr < nintrs; ++intr) { /* check each record */ if (INTTYPE(intr) == 0) { /* standard INT */ if (SRCBUSIRQ(intr) == isa_irq) { if (apic_int_is_bus_type(intr, ISA) || apic_int_is_bus_type(intr, EISA)) return INTPIN(intr); /* found */ } } } return -1; /* NOT found */ } #undef SRCBUSIRQ /* * Determine which APIC pin a PCI INT is attached to. */ #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) int pci_apic_pin(int pciBus, int pciDevice, int pciInt) { int intr; --pciInt; /* zero based */ for (intr = 0; intr < nintrs; ++intr) /* check each record */ if ((INTTYPE(intr) == 0) /* standard INT */ && (SRCBUSID(intr) == pciBus) && (SRCBUSDEVICE(intr) == pciDevice) && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ if (apic_int_is_bus_type(intr, PCI)) return INTPIN(intr); /* exact match */ return -1; /* NOT found */ } #undef SRCBUSLINE #undef SRCBUSDEVICE #undef SRCBUSID #undef INTPIN #undef INTTYPE /* * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. * * XXX FIXME: * Exactly what this means is unclear at this point. It is a solution * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard * could route any of the ISA INTs to upper (>15) IRQ values. But most would * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an * option. */ int undirect_isa_irq(int rirq) { #if defined(READY) printf("Freeing redirected ISA irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); return 0; #endif /* READY */ } /* * Reprogram the MB chipset to NOT redirect a PCI INTerrupt */ int undirect_pci_irq(int rirq) { #if defined(READY) if (bootverbose) printf("Freeing redirected PCI irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else if (bootverbose) printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); return 0; #endif /* READY */ } /* * given a bus ID, return: * the bus type if found * -1 if NOT found */ int apic_bus_type(int id) { int x; for (x = 0; x < mp_nbusses; ++x) if (bus_data[x].bus_id == id) return bus_data[x].bus_type; return -1; } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus ID if found * -1 if NOT found */ int apic_src_bus_id(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_id); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus IRQ if found * -1 if NOT found */ int apic_src_bus_irq(int apic, int pin) { int x; for (x = 0; x < nintrs; x++) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_irq); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated INTerrupt type if found * -1 if NOT found */ int apic_int_type(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_type); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated trigger mode if found * -1 if NOT found */ int apic_trigger(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return ((io_apic_ints[x].int_flags >> 2) & 0x03); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated 'active' level if found * -1 if NOT found */ int apic_polarity(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_flags & 0x03); return -1; /* NOT found */ } /* * set data according to MP defaults * FIXME: probably not complete yet... */ static void default_mp_table(int type) { int ap_cpu_id; #if defined(APIC_IO) u_int32_t ux; int io_apic_id; int pin; #endif /* APIC_IO */ #if 0 printf(" MP default config type: %d\n", type); switch (type) { case 1: printf(" bus: ISA, APIC: 82489DX\n"); break; case 2: printf(" bus: EISA, APIC: 82489DX\n"); break; case 3: printf(" bus: EISA, APIC: 82489DX\n"); break; case 4: printf(" bus: MCA, APIC: 82489DX\n"); break; case 5: printf(" bus: ISA+PCI, APIC: Integrated\n"); break; case 6: printf(" bus: EISA+PCI, APIC: Integrated\n"); break; case 7: printf(" bus: MCA+PCI, APIC: Integrated\n"); break; default: printf(" future type\n"); break; /* NOTREACHED */ } #endif /* 0 */ boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; /* BSP */ CPU_TO_ID(0) = boot_cpu_id; ID_TO_CPU(boot_cpu_id) = 0; /* one and only AP */ CPU_TO_ID(1) = ap_cpu_id; ID_TO_CPU(ap_cpu_id) = 1; #if defined(APIC_IO) /* one and only IO APIC */ io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; /* * sanity check, refer to MP spec section 3.6.6, last paragraph * necessary as some hardware isn't properly setting up the IO APIC */ #if defined(REALLY_ANAL_IOAPICID_VALUE) if (io_apic_id != 2) { #else if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { #endif /* REALLY_ANAL_IOAPICID_VALUE */ ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ ux &= ~APIC_ID_MASK; /* clear the ID field */ ux |= 0x02000000; /* set it to '2' */ io_apic_write(0, IOAPIC_ID, ux); /* write new value */ ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ if ((ux & APIC_ID_MASK) != 0x02000000) panic("can't control IO APIC ID, reg: 0x%08x", ux); io_apic_id = 2; } IO_TO_ID(0) = io_apic_id; ID_TO_IO(io_apic_id) = 0; #endif /* APIC_IO */ /* fill out bus entries */ switch (type) { case 1: case 2: case 3: case 5: case 6: bus_data[0].bus_id = default_data[type - 1][1]; bus_data[0].bus_type = default_data[type - 1][2]; bus_data[1].bus_id = default_data[type - 1][3]; bus_data[1].bus_type = default_data[type - 1][4]; break; /* case 4: case 7: MCA NOT supported */ default: /* illegal/reserved */ panic("BAD default MP config: %d", type); /* NOTREACHED */ } #if defined(APIC_IO) /* general cases from MP v1.4, table 5-2 */ for (pin = 0; pin < 16; ++pin) { io_apic_ints[pin].int_type = 0; io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ io_apic_ints[pin].src_bus_id = 0; io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ io_apic_ints[pin].dst_apic_id = io_apic_id; io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ } /* special cases from MP v1.4, table 5-2 */ if (type == 2) { io_apic_ints[2].int_type = 0xff; /* N/C */ io_apic_ints[13].int_type = 0xff; /* N/C */ #if !defined(APIC_MIXED_MODE) /** FIXME: ??? */ panic("sorry, can't support type 2 default yet"); #endif /* APIC_MIXED_MODE */ } else io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ if (type == 7) io_apic_ints[0].int_type = 0xff; /* N/C */ else io_apic_ints[0].int_type = 3; /* vectored 8259 */ #endif /* APIC_IO */ } /* * start each AP in our list */ static int start_all_aps(u_int boot_addr) { int x, i; u_char mpbiosreason; u_long mpbioswarmvec; pd_entry_t newptd; pt_entry_t newpt; int *newpp; POSTCODE(START_ALL_APS_POST); /** * NOTE: this needs further thought: * where does it get released? * should it be set to empy? * * get the initial mp_lock with a count of 1 for the BSP */ mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ /* initialize BSP's local APIC */ apic_initialize(); /* install the AP 1st level boot code */ install_ap_tramp(boot_addr); /* save the current value of the warm-start vector */ mpbioswarmvec = *((u_long *) WARMBOOT_OFF); outb(CMOS_REG, BIOS_RESET); mpbiosreason = inb(CMOS_DATA); /* record BSP in CPU map */ all_cpus = 1; /* start each AP */ for (x = 1; x <= mp_naps; ++x) { /* HACK HACK HACK !!! */ /* alloc new page table directory */ newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* clone currently active one (ie: IdlePTD) */ bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ /* set up 0 -> 4MB P==V mapping for AP boot */ newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); /* store PTD for this AP */ bootPTD = (pd_entry_t)vtophys(newptd); /* alloc new page table page */ newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* set the new PTD's private page to point there */ newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); /* install self referential entry */ newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); /* get a new private data page */ newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); /* wire it into the private page table page */ newpt[0] = PG_V | PG_RW | vtophys(newpp); /* wire the ptp into itself for access */ newpt[1] = PG_V | PG_RW | vtophys(newpt); /* and the local apic */ newpt[2] = SMP_prvpt[2]; /* and the IO apic mapping[s] */ for (i = 16; i < 32; i++) newpt[i] = SMP_prvpt[i]; /* prime data page for it to use */ newpp[0] = x; /* cpuid */ newpp[1] = 0; /* curproc */ newpp[2] = 0; /* curpcb */ newpp[3] = 0; /* npxproc */ newpp[4] = 0; /* runtime.tv_sec */ newpp[5] = 0; /* runtime.tv_usec */ newpp[6] = x << 24; /* cpu_lockid */ /* XXX NOTE: ABANDON bootPTD for now!!!! */ /* END REVOLTING HACKERY */ /* setup a vector to our boot code */ *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ /* attempt to start the Application Processor */ CHECK_INIT(99); /* setup checkpoints */ if (!start_ap(x, boot_addr)) { printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); CHECK_PRINT("trace"); /* show checkpoints */ /* better panic as the AP may be running loose */ printf("panic y/n? [y] "); if (cngetc() != 'n') panic("bye-bye"); } CHECK_PRINT("trace"); /* show checkpoints */ /* record its version info */ cpu_apic_versions[x] = cpu_apic_versions[0]; all_cpus |= (1 << x); /* record AP in CPU map */ } /* build our map of 'other' CPUs */ other_cpus = all_cpus & ~(1 << cpuid); /* fill in our (BSP) APIC version */ cpu_apic_versions[0] = lapic.version; /* restore the warmstart vector */ *(u_long *) WARMBOOT_OFF = mpbioswarmvec; outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, mpbiosreason); pmap_set_opt_bsp(); /* number of APs actually started */ return mp_ncpus - 1; } /* * load the 1st level AP boot code into base memory. */ /* targets for relocation */ extern void bigJump(void); extern void bootCodeSeg(void); extern void bootDataSeg(void); extern void MPentry(void); extern u_int MP_GDT; extern u_int mp_gdtbase; static void install_ap_tramp(u_int boot_addr) { int x; int size = *(int *) ((u_long) & bootMP_size); u_char *src = (u_char *) ((u_long) bootMP); u_char *dst = (u_char *) boot_addr + KERNBASE; u_int boot_base = (u_int) bootMP; u_int8_t *dst8; u_int16_t *dst16; u_int32_t *dst32; POSTCODE(INSTALL_AP_TRAMP_POST); for (x = 0; x < size; ++x) *dst++ = *src++; /* * modify addresses in code we just moved to basemem. unfortunately we * need fairly detailed info about mpboot.s for this to work. changes * to mpboot.s might require changes here. */ /* boot code is located in KERNEL space */ dst = (u_char *) boot_addr + KERNBASE; /* modify the lgdt arg */ dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); /* modify the ljmp target for MPentry() */ dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); *dst32 = ((u_int) MPentry - KERNBASE); /* modify the target for boot code segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; /* modify the target for boot data segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; } /* * this function starts the AP (application processor) identified * by the APIC ID 'physicalCpu'. It does quite a "song and dance" * to accomplish this. This is necessary because of the nuances * of the different hardware we might encounter. It ain't pretty, * but it seems to work. */ static int start_ap(int logical_cpu, u_int boot_addr) { int physical_cpu; int vector; int cpus; u_long icr_lo, icr_hi; POSTCODE(START_AP_POST); /* get the PHYSICAL APIC ID# */ physical_cpu = CPU_TO_ID(logical_cpu); /* calculate the vector */ vector = (boot_addr >> 12) & 0xff; /* used as a watchpoint to signal AP startup */ cpus = mp_ncpus; /* * first we do an INIT/RESET IPI this INIT IPI might be run, reseting * and running the target CPU. OR this INIT IPI might be latched (P5 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be * ignored. */ /* setup the address for the target AP */ icr_hi = lapic.icr_hi & ~APIC_ID_MASK; icr_hi |= (physical_cpu << 24); lapic.icr_hi = icr_hi; /* do an INIT IPI: assert RESET */ icr_lo = lapic.icr_lo & 0xfff00000; lapic.icr_lo = icr_lo | 0x0000c500; /* wait for pending status end */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* do an INIT IPI: deassert RESET */ lapic.icr_lo = icr_lo | 0x00008500; /* wait for pending status end */ u_sleep(10000); /* wait ~10mS */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* * next we do a STARTUP IPI: the previous INIT IPI might still be * latched, (P5 bug) this 1st STARTUP would then terminate * immediately, and the previously started INIT IPI would continue. OR * the previous INIT IPI has already run. and this STARTUP IPI will * run. OR the previous INIT IPI was ignored. and this STARTUP IPI * will run. */ /* do a STARTUP IPI */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is * recognized after hardware RESET or INIT IPI. */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* wait for it to start */ set_apic_timer(5000000);/* == 5 seconds */ while (read_apic_timer()) if (mp_ncpus > cpus) return 1; /* return SUCCESS */ return 0; /* return FAILURE */ } /* * Flush the TLB on all other CPU's * * XXX: Needs to handshake and wait for completion before proceding. */ void smp_invltlb(void) { #if defined(APIC_IO) if (smp_active && invltlb_ok) all_but_self_ipi(XINVLTLB_OFFSET); #endif /* APIC_IO */ } void invlpg(u_int addr) { __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); /* send a message to the other CPUs */ smp_invltlb(); } void invltlb(void) { u_long temp; /* * This should be implemented as load_cr3(rcr3()) when load_cr3() is * inlined. */ __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); /* send a message to the other CPUs */ smp_invltlb(); } -#if defined(TEST_CPUSTOP) - -#if defined(DEBUG_CPUSTOP) -void db_printf __P((const char *fmt, ...)); -#endif /* DEBUG_CPUSTOP */ - /* * When called the executing CPU will send an IPI to all other CPUs * requesting that they halt execution. * * Usually (but not necessarily) called with 'other_cpus' as its arg. * * - Signals all CPUs in map to stop. * - Waits for each to stop. * * Returns: * -1: error * 0: NA * 1: ok * * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs * from executing at same time. */ int stop_cpus( u_int map ) { if (!smp_active) return 0; /* send IPI to all CPUs in map */ -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); -#endif /* DEBUG_CPUSTOP */ - stopped_cpus = 0; /* send the Xcpustop IPI to all CPUs in map */ selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); -#if defined(DEBUG_CPUSTOP) - db_printf(" spin\n"); -#endif /* DEBUG_CPUSTOP */ - while (stopped_cpus != map) /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" spun\nstopped\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } /* * Called by a CPU to restart stopped CPUs. * * Usually (but not necessarily) called with 'stopped_cpus' as its arg. * * - Signals all CPUs in map to restart. * - Waits for each to restart. * * Returns: * -1: error * 0: NA * 1: ok */ int restart_cpus( u_int map ) { if (!smp_active) return 0; -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", - cpuid, map, stopped_cpus); -#endif /* DEBUG_CPUSTOP */ - started_cpus = map; /* signal other cpus to restart */ while (started_cpus) /* wait for each to clear its bit */ /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" restarted\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } - -#endif /** TEST_CPUSTOP */ Index: head/sys/amd64/isa/intr_machdep.h =================================================================== --- head/sys/amd64/isa/intr_machdep.h (revision 27516) +++ head/sys/amd64/isa/intr_machdep.h (revision 27517) @@ -1,185 +1,179 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)isa_device.h 7.1 (Berkeley) 5/9/91 - * $Id: intr_machdep.h,v 1.6 1997/07/13 00:18:33 smp Exp smp $ + * $Id: intr_machdep.h,v 1.7 1997/07/18 19:47:13 smp Exp smp $ */ #ifndef _I386_ISA_INTR_MACHDEP_H_ #define _I386_ISA_INTR_MACHDEP_H_ /* * Low level interrupt code. */ #ifdef KERNEL /* * XXX FIXME: rethink location for all IPI vectors. */ /* APIC TPR priority vector levels: 0xff (255) +------------+ | | 15 (highest) 0xf0 (240) +------------+ | | 14 0xe0 (224) +------------+ | | 13 0xd0 (208) +------------+ | | 12 0xc0 (192) +------------+ | | 11 0xb0 (176) +------------+ | | 10 0xa0 (160) +------------+ | | 9 0x90 (144) +------------+ | | 8 0x80 (128) +------------+ | | 7 0x70 (112) +------------+ | | 6 (IPIs: Xspuriousint) 0x60 (96) +------------+ | | 5 (IPIs: Xcpustop) 0x50 (80) +------------+ | | 4 (IPIs: Xinvltlb) 0x40 (64) +------------+ | | 3 (extended APIC hardware INTs: PCI) 0x30 (48) +------------+ | | 2 (start of hardware INTs: ISA) 0x20 (32) +------------+ | | 1 (lowest) 0x10 (16) +------------+ | | 0 0x00 (0) +------------+ */ #define TPR_BLOCK_HWI 0x3f /* block hardware INTs via APIC TPR */ #define TPR_BLOCK_XINVLTLB 0x4f /* block ? via APIC TPR */ #define TPR_BLOCK_XCPUSTOP 0x5f /* block ? via APIC TPR */ /* * Note: this vector MUST be xxxx1111, 32 + 79 = 111 = 0x6f: * also remember i386/include/segments.h: #define NIDT 129 */ #define XSPURIOUSINT_OFFSET (ICU_OFFSET + 79) /* TLB shootdowns */ #define XINVLTLB_OFFSET (ICU_OFFSET + 32) -#if defined(TEST_CPUSTOP) /* IPI to signal CPUs to stop and wait for another CPU to restart them */ #define XCPUSTOP_OFFSET (ICU_OFFSET + 48) -#endif /** TEST_CPUSTOP */ -#if defined(TEST_TEST1) +#ifdef TEST_TEST1 /* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */ #define XTEST1_OFFSET (ICU_OFFSET + 31) -#endif /** TEST_TEST1 */ +#endif /** TEST_TEST1 */ #ifndef LOCORE /* * Type of the first (asm) part of an interrupt handler. */ typedef void inthand_t __P((u_int cs, u_int ef, u_int esp, u_int ss)); #define IDTVEC(name) __CONCAT(X,name) extern char eintrnames[]; /* end of intrnames[] */ extern u_long intrcnt[]; /* counts for for each device and stray */ extern char intrnames[]; /* string table containing device names */ extern u_long *intr_countp[]; /* pointers into intrcnt[] */ extern inthand2_t *intr_handler[]; /* C entry points of intr handlers */ extern u_int intr_mask[]; /* sets of intrs masked during handling of 1 */ extern int intr_unit[]; /* cookies to pass to intr handlers */ inthand_t IDTVEC(fastintr0), IDTVEC(fastintr1), IDTVEC(fastintr2), IDTVEC(fastintr3), IDTVEC(fastintr4), IDTVEC(fastintr5), IDTVEC(fastintr6), IDTVEC(fastintr7), IDTVEC(fastintr8), IDTVEC(fastintr9), IDTVEC(fastintr10), IDTVEC(fastintr11), IDTVEC(fastintr12), IDTVEC(fastintr13), IDTVEC(fastintr14), IDTVEC(fastintr15); inthand_t IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3), IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7), IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11), IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15); /* these functions ONLY exist in an SMP/APIC_IO kernel: */ inthand_t IDTVEC(fastintr16), IDTVEC(fastintr17), IDTVEC(fastintr18), IDTVEC(fastintr19), IDTVEC(fastintr20), IDTVEC(fastintr21), IDTVEC(fastintr22), IDTVEC(fastintr23); inthand_t IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19), IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23); inthand_t - Xinvltlb, - Xspuriousint; - -#if defined(TEST_CPUSTOP) -inthand_t + Xinvltlb, /* TLB shootdowns */ + Xspuriousint, /* handle APIC "spurious INTs" */ Xcpustop; /* stop & wait for another CPU to restart it */ -#endif /** TEST_CPUSTOP */ -#if defined(TEST_CPUSTOP) +#ifdef TEST_TEST1 inthand_t Xtest1; /* 'fake' HWI in top of APIC prio 0x3x, 32+31 = 0x3f */ -#endif /** TEST_TEST1 */ +#endif /** TEST_TEST1 */ struct isa_device; void isa_defaultirq __P((void)); int isa_irq_pending __P((struct isa_device *dvp)); int icu_irq_pending __P((struct isa_device *dvp)); /* APIC_IO kernel */ int isa_nmi __P((int cd)); void update_intrname __P((int intr, int device_id)); int icu_setup __P((int intr, inthand2_t *func, void *arg, u_int *maskptr, int flags)); int icu_unset __P((int intr, inthand2_t *handler)); int update_intr_masks __P((void)); void register_imask __P((struct isa_device *dvp, u_int mask)); #endif /* LOCORE */ #endif /* KERNEL */ #endif /* !_I386_ISA_INTR_MACHDEP_H_ */ Index: head/sys/i386/i386/apic_vector.s =================================================================== --- head/sys/i386/i386/apic_vector.s (revision 27516) +++ head/sys/i386/i386/apic_vector.s (revision 27517) @@ -1,431 +1,415 @@ /* * from: vector.s, 386BSD 0.1 unknown origin - * $Id: apic_vector.s,v 1.7 1997/07/15 02:49:21 fsmp Exp $ + * $Id: apic_vector.s,v 1.12 1997/07/18 19:47:13 smp Exp smp $ */ -#include /** TEST_CPUSTOP */ +#include /** various counters */ +#include "i386/isa/intr_machdep.h" /* convert an absolute IRQ# into a bitmask */ #define IRQ_BIT(irq_num) (1 << (irq_num)) /* make an index into the IO APIC from the IRQ# */ #define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2)) /* * 'lazy masking' code suggested by Bruce Evans */ #define MAYBE_MASK_IRQ(irq_num) \ testl $IRQ_BIT(irq_num),iactive ; /* lazy masking */ \ je 1f ; /* NOT currently active */ \ orl $IRQ_BIT(irq_num),_imen ; /* set the mask bit */ \ movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ orl $IOART_INTMASK,%eax ; /* set the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ movl $0, lapic_eoi ; \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ popl %ds ; \ popal ; \ addl $4+4,%esp ; \ iret ; \ ; \ ALIGN_TEXT ; \ 1: ; \ orl $IRQ_BIT(irq_num),iactive #define MAYBE_UNMASK_IRQ(irq_num) \ cli ; /* must unmask _imen and icu atomically */ \ andl $~IRQ_BIT(irq_num),iactive ; \ testl $IRQ_BIT(irq_num),_imen ; \ je 2f ; \ andl $~IRQ_BIT(irq_num),_imen ; /* clear mask bit */ \ movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ andl $~IOART_INTMASK,%eax ; /* clear the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ 2: ; \ sti ; /* XXX _doreti repeats the cli/sti */ /* * Macros for interrupt interrupt entry, call to handler, and exit. */ #define FAST_INTR(irq_num, vec_name) \ .text ; \ SUPERALIGN_TEXT ; \ IDTVEC(vec_name) ; \ pushl %eax ; /* save only call-used registers */ \ pushl %ecx ; \ pushl %edx ; \ pushl %ds ; \ MAYBE_PUSHL_ES ; \ movl $KDSEL,%eax ; \ movl %ax,%ds ; \ MAYBE_MOVW_AX_ES ; \ FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \ GET_MPLOCK ; /* SMP Spin lock */ \ pushl _intr_unit + (irq_num) * 4 ; \ call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \ movl $0, lapic_eoi ; \ addl $4,%esp ; \ incl _cnt+V_INTR ; /* book-keeping can wait */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ incl (%eax) ; \ movl _cpl,%eax ; /* unmasking pending HWIs or SWIs? */ \ notl %eax ; \ andl _ipending,%eax ; \ jne 2f ; /* yes, maybe handle them */ \ 1: ; \ MEXITCOUNT ; \ REL_MPLOCK ; /* SMP release global lock */ \ MAYBE_POPL_ES ; \ popl %ds ; \ popl %edx ; \ popl %ecx ; \ popl %eax ; \ iret ; \ ; \ ALIGN_TEXT ; \ 2: ; \ cmpb $3,_intr_nesting_level ; /* enough stack? */ \ jae 1b ; /* no, return */ \ movl _cpl,%eax ; \ /* XXX next line is probably unnecessary now. */ \ movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \ incb _intr_nesting_level ; /* ... really limit it ... */ \ sti ; /* to do this as early as possible */ \ MAYBE_POPL_ES ; /* discard most of thin frame ... */ \ popl %ecx ; /* ... original %ds ... */ \ popl %edx ; \ xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \ pushal ; /* build fat frame (grrr) ... */ \ pushl %ecx ; /* ... actually %ds ... */ \ pushl %es ; \ movl $KDSEL,%eax ; \ movl %ax,%es ; \ movl (2+8+0)*4(%esp),%ecx ; /* %ecx from thin frame ... */ \ movl %ecx,(2+6)*4(%esp) ; /* ... to fat frame ... */ \ movl (2+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \ pushl %eax ; \ subl $4,%esp ; /* junk for unit number */ \ MEXITCOUNT ; \ jmp _doreti #define INTR(irq_num, vec_name) \ .text ; \ SUPERALIGN_TEXT ; \ IDTVEC(vec_name) ; \ pushl $0 ; /* dummy error code */ \ pushl $0 ; /* dummy trap type */ \ pushal ; \ pushl %ds ; /* save data and extra segments ... */ \ pushl %es ; \ movl $KDSEL,%eax ; /* ... and reload with kernel's ... */ \ movl %ax,%ds ; /* ... early for obsolete reasons */ \ movl %ax,%es ; \ GET_MPLOCK ; /* SMP Spin lock */ \ MAYBE_MASK_IRQ(irq_num) ; \ movl $0, lapic_eoi ; \ movl _cpl,%eax ; \ testl $IRQ_BIT(irq_num), %eax ; \ jne 3f ; \ incb _intr_nesting_level ; \ __CONCAT(Xresume,irq_num): ; \ FAKE_MCOUNT(12*4(%esp)) ; /* XXX late to avoid dbl cnt */ \ incl _cnt+V_INTR ; /* tally interrupts */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ incl (%eax) ; \ movl _cpl,%eax ; \ pushl %eax ; \ pushl _intr_unit + (irq_num) * 4 ; \ orl _intr_mask + (irq_num) * 4,%eax ; \ movl %eax,_cpl ; \ sti ; \ call *_intr_handler + (irq_num) * 4 ; \ MAYBE_UNMASK_IRQ(irq_num) ; \ MEXITCOUNT ; \ jmp _doreti ; \ ; \ ALIGN_TEXT ; \ 3: ; \ /* XXX skip mcounting here to avoid double count */ \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ popl %ds ; \ popal ; \ addl $4+4,%esp ; \ iret /* * Handle "spurious INTerrupts". * Notes: * This is different than the "spurious INTerrupt" generated by an * 8259 PIC for missing INTs. See the APIC documentation for details. * This routine should NOT do an 'EOI' cycle. */ .text SUPERALIGN_TEXT .globl _Xspuriousint _Xspuriousint: #ifdef COUNT_SPURIOUS_INTS ss incl _sihits #endif /* No EOI cycle used here */ iret /* * Handle TLB shootdowns. */ .text SUPERALIGN_TEXT .globl _Xinvltlb _Xinvltlb: pushl %eax #ifdef COUNT_XINVLTLB_HITS ss movl _cpuid, %eax ss incl _xhits(,%eax,4) #endif /* COUNT_XINVLTLB_HITS */ movl %cr3, %eax /* invalidate the TLB */ movl %eax, %cr3 ss /* stack segment, avoid %ds load */ movl $0, lapic_eoi /* End Of Interrupt to APIC */ popl %eax iret -#ifdef TEST_CPUSTOP - -#include "i386/isa/intr_machdep.h" - /* * Executed by a CPU when it receives an Xcpustop IPI from another CPU, * * - Signals its receipt. * - Waits for permission to restart. * - Signals its restart. */ .text SUPERALIGN_TEXT .globl _Xcpustop _Xcpustop: pushl %eax pushl %ds /* save current data segment */ movl $KDSEL, %eax movl %ax, %ds /* use KERNEL data segment */ movl _cpuid, %eax #ifdef COUNT_CSHITS incl _cshits(,%eax,4) #endif /* COUNT_CSHITS */ ASMPOSTCODE_HI(0x1) lock btsl %eax, _stopped_cpus /* stopped_cpus |= (1< #include #include #include #include #include #include #include #ifdef SMP #include -#include /** TEST_CPUSTOP */ +#include /** CPUSTOP_ON_DDBBREAK */ #endif #include #include #include #include #include static jmp_buf *db_nofault = 0; extern jmp_buf db_jmpbuf; extern void gdb_handle_exception __P((db_regs_t *, int, int)); db_regs_t ddb_regs; static jmp_buf db_global_jmpbuf; static int db_global_jmpbuf_valid; #ifdef __GNUC__ #define rss() ({u_short ss; __asm __volatile("movl %%ss,%0" : "=r" (ss)); ss;}) #endif /* * kdb_trap - field a TRACE or BPT trap */ int kdb_trap(type, code, regs) int type, code; register struct i386_saved_state *regs; { int ddb_mode = !(boothowto & RB_GDB); /* * XXX try to do nothing if the console is in graphics mode. * Handle trace traps (and hardware breakpoints...) by ignoring * them except for forgetting about them. Return 0 for other * traps to say that we haven't done anything. The trap handler * will usually panic. We should handle breakpoint traps for * our breakpoints by disarming our breakpoints and fixing up * %eip. */ if (cons_unavail && ddb_mode) { if (type == T_TRCTRAP) { regs->tf_eflags &= ~PSL_T; return (1); } return (0); } switch (type) { case T_BPTFLT: /* breakpoint */ case T_TRCTRAP: /* debug exception */ break; default: /* * XXX this is almost useless now. In most cases, * trap_fatal() has already printed a much more verbose * message. However, it is dangerous to print things in * trap_fatal() - printf() might be reentered and trap. * The debugger should be given control first. */ if (ddb_mode) db_printf("kernel: type %d trap, code=%x\n", type, code); if (db_nofault) { jmp_buf *no_fault = db_nofault; db_nofault = 0; longjmp(*no_fault, 1); } } /* * This handles unexpected traps in ddb commands, including calls to * non-ddb functions. db_nofault only applies to memory accesses by * internal ddb commands. */ if (db_global_jmpbuf_valid) longjmp(db_global_jmpbuf, 1); /* * XXX We really should switch to a local stack here. */ ddb_regs = *regs; /* * If in kernel mode, esp and ss are not saved, so dummy them up. */ if (ISPL(regs->tf_cs) == 0) { ddb_regs.tf_esp = (int)®s->tf_esp; ddb_regs.tf_ss = rss(); } cnpollc(TRUE); -#if defined(SMP) && defined(TEST_CPUSTOP) - /* XXX FIXME: we stop all CPUs except ourselves (obviously) */ +#ifdef SMP +#ifdef CPUSTOP_ON_DDBBREAK + +#if defined(VERBOSE_CPUSTOP_ON_DDBBREAK) + db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, other_cpus); +#endif /* VERBOSE_CPUSTOP_ON_DDBBREAK */ + + /* We stop all CPUs except ourselves (obviously) */ stop_cpus(other_cpus); -#endif /** SMP && TEST_CPUSTOP */ +#if defined(VERBOSE_CPUSTOP_ON_DDBBREAK) + db_printf(" stopped\n"); +#endif /* VERBOSE_CPUSTOP_ON_DDBBREAK */ + +#endif /* CPUSTOP_ON_DDBBREAK */ +#endif /* SMP */ + (void) setjmp(db_global_jmpbuf); db_global_jmpbuf_valid = TRUE; if (ddb_mode) db_trap(type, code); else gdb_handle_exception(&ddb_regs, type, code); db_global_jmpbuf_valid = FALSE; -#if defined(SMP) && defined(TEST_CPUSTOP) - /* XXX FIXME: restart all the CPUs we previously stopped */ +#ifdef SMP +#ifdef CPUSTOP_ON_DDBBREAK + +#if defined(VERBOSE_CPUSTOP_ON_DDBBREAK) + db_printf("\nCPU%d restarting CPUs: 0x%08x\n", cpuid, stopped_cpus); +#endif /* VERBOSE_CPUSTOP_ON_DDBBREAK */ + + /* Restart all the CPUs we previously stopped */ if (stopped_cpus != other_cpus) { db_printf("whoa, other_cpus: 0x%08x, stopped_cpus: 0x%08x\n", - other_cpus, stopped_cpus); - cngetc(); + other_cpus, stopped_cpus); + panic("stop_cpus() failed"); } restart_cpus(stopped_cpus); -#endif /** SMP && TEST_CPUSTOP */ + +#if defined(VERBOSE_CPUSTOP_ON_DDBBREAK) + db_printf(" restarted\n"); +#endif /* VERBOSE_CPUSTOP_ON_DDBBREAK */ + +#endif /* CPUSTOP_ON_DDBBREAK */ +#endif /* SMP */ cnpollc(FALSE); regs->tf_eip = ddb_regs.tf_eip; regs->tf_eflags = ddb_regs.tf_eflags; regs->tf_eax = ddb_regs.tf_eax; regs->tf_ecx = ddb_regs.tf_ecx; regs->tf_edx = ddb_regs.tf_edx; regs->tf_ebx = ddb_regs.tf_ebx; /* * If in user mode, the saved ESP and SS were valid, restore them. */ if (ISPL(regs->tf_cs)) { regs->tf_esp = ddb_regs.tf_esp; regs->tf_ss = ddb_regs.tf_ss & 0xffff; } regs->tf_ebp = ddb_regs.tf_ebp; regs->tf_esi = ddb_regs.tf_esi; regs->tf_edi = ddb_regs.tf_edi; regs->tf_es = ddb_regs.tf_es & 0xffff; regs->tf_cs = ddb_regs.tf_cs & 0xffff; regs->tf_ds = ddb_regs.tf_ds & 0xffff; return (1); } /* * Read bytes from kernel address space for debugger. */ void db_read_bytes(addr, size, data) vm_offset_t addr; register int size; register char *data; { register char *src; db_nofault = &db_jmpbuf; src = (char *)addr; while (--size >= 0) *data++ = *src++; db_nofault = 0; } /* * Write bytes to kernel address space for debugger. */ void db_write_bytes(addr, size, data) vm_offset_t addr; register int size; register char *data; { register char *dst; unsigned *ptep0 = NULL; unsigned oldmap0 = 0; vm_offset_t addr1; unsigned *ptep1 = NULL; unsigned oldmap1 = 0; db_nofault = &db_jmpbuf; if (addr >= VM_MIN_KERNEL_ADDRESS && addr <= round_page((vm_offset_t)&etext)) { ptep0 = pmap_pte(kernel_pmap, addr); oldmap0 = *ptep0; *ptep0 |= PG_RW; addr1 = trunc_page(addr + size - 1); /* Map another page if the data crosses a page boundary. */ if (trunc_page(addr) != addr1) { ptep1 = pmap_pte(kernel_pmap, addr1); oldmap1 = *ptep1; *ptep1 |= PG_RW; } invltlb(); } dst = (char *)addr; while (--size >= 0) *dst++ = *data++; db_nofault = 0; if (ptep0) { *ptep0 = oldmap0; if (ptep1) *ptep1 = oldmap1; invltlb(); } } /* * XXX * Move this to machdep.c and allow it to be called if any debugger is * installed. */ void Debugger(msg) const char *msg; { static volatile u_char in_Debugger; /* * XXX * Do nothing if the console is in graphics mode. This is * OK if the call is for the debugger hotkey but not if the call * is a weak form of panicing. */ if (cons_unavail && !(boothowto & RB_GDB)) return; if (!in_Debugger) { in_Debugger = 1; db_printf("Debugger(\"%s\")\n", msg); breakpoint(); in_Debugger = 0; } } Index: head/sys/i386/i386/mp_machdep.c =================================================================== --- head/sys/i386/i386/mp_machdep.c (revision 27516) +++ head/sys/i386/i386/mp_machdep.c (revision 27517) @@ -1,1834 +1,1803 @@ /* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: mp_machdep.c,v 1.28 1997/07/17 19:44:56 dyson Exp $ + * $Id: mp_machdep.c,v 1.16 1997/07/18 19:45:41 smp Exp smp $ */ #include "opt_smp.h" #include /* for KERNBASE */ #include #include #include #include #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include #include #include #include #include #include #include -#include /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP _TEST1 */ +#include /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ #include #include #include /* cngetc() */ #if defined(APIC_IO) #include /* setidt() */ #include /* IPIs */ #include /* IPIs */ #endif /* APIC_IO */ #define WARMBOOT_TARGET 0 #define WARMBOOT_OFF (KERNBASE + 0x0467) #define WARMBOOT_SEG (KERNBASE + 0x0469) #define BIOS_BASE (0xf0000) #define BIOS_SIZE (0x10000) #define BIOS_COUNT (BIOS_SIZE/4) #define CMOS_REG (0x70) #define CMOS_DATA (0x71) #define BIOS_RESET (0x0f) #define BIOS_WARM (0x0a) #define PROCENTRY_FLAG_EN 0x01 #define PROCENTRY_FLAG_BP 0x02 #define IOAPICENTRY_FLAG_EN 0x01 /* MP Floating Pointer Structure */ typedef struct MPFPS { char signature[4]; void *pap; u_char length; u_char spec_rev; u_char checksum; u_char mpfb1; u_char mpfb2; u_char mpfb3; u_char mpfb4; u_char mpfb5; } *mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { char signature[4]; u_short base_table_length; u_char spec_rev; u_char checksum; u_char oem_id[8]; u_char product_id[12]; void *oem_table_pointer; u_short oem_table_size; u_short entry_count; void *apic_address; u_short extended_table_length; u_char extended_table_checksum; u_char reserved; } *mpcth_t; typedef struct PROCENTRY { u_char type; u_char apic_id; u_char apic_version; u_char cpu_flags; u_long cpu_signature; u_long feature_flags; u_long reserved1; u_long reserved2; } *proc_entry_ptr; typedef struct BUSENTRY { u_char type; u_char bus_id; char bus_type[6]; } *bus_entry_ptr; typedef struct IOAPICENTRY { u_char type; u_char apic_id; u_char apic_version; u_char apic_flags; void *apic_address; } *io_apic_entry_ptr; typedef struct INTENTRY { u_char type; u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } *int_entry_ptr; /* descriptions of MP basetable entries */ typedef struct BASETABLE_ENTRY { u_char type; u_char length; char name[16]; } basetable_entry; /* * this code MUST be enabled here and in mpboot.s. * it follows the very early stages of AP boot by placing values in CMOS ram. * it NORMALLY will never be needed and thus the primitive method for enabling. * #define CHECK_POINTS */ #if defined(CHECK_POINTS) #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) #define CHECK_INIT(D); \ CHECK_WRITE(0x34, (D)); \ CHECK_WRITE(0x35, (D)); \ CHECK_WRITE(0x36, (D)); \ CHECK_WRITE(0x37, (D)); \ CHECK_WRITE(0x38, (D)); \ CHECK_WRITE(0x39, (D)); #define CHECK_PRINT(S); \ printf("%s: %d, %d, %d, %d, %d, %d\n", \ (S), \ CHECK_READ(0x34), \ CHECK_READ(0x35), \ CHECK_READ(0x36), \ CHECK_READ(0x37), \ CHECK_READ(0x38), \ CHECK_READ(0x39)); #else /* CHECK_POINTS */ #define CHECK_INIT(D) #define CHECK_PRINT(S) #endif /* CHECK_POINTS */ /* * Values to send to the POST hardware. */ #define MP_BOOTADDRESS_POST 0x10 #define MP_PROBE_POST 0x11 #define MP_START_POST 0x12 #define MP_ANNOUNCE_POST 0x13 #define MPTABLE_PASS1_POST 0x14 #define MPTABLE_PASS2_POST 0x15 #define MP_ENABLE_POST 0x16 #define START_ALL_APS_POST 0x17 #define INSTALL_AP_TRAMP_POST 0x18 #define START_AP_POST 0x19 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ int current_postcode; /** XXX FIXME: what system files declare these??? */ extern struct region_descriptor r_gdt, r_idt; int mp_ncpus; /* # of CPUs, including BSP */ int mp_naps; /* # of Applications processors */ int mp_nbusses; /* # of busses */ int mp_napics; /* # of IO APICs */ int boot_cpu_id; /* designated BSP */ vm_offset_t cpu_apic_address; vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ u_int32_t cpu_apic_versions[NCPU]; u_int32_t io_apic_versions[NAPIC]; /* * APIC ID logical/physical mapping structures. * We oversize these to simplify boot-time config. */ int cpu_num_to_apic_id[NAPICID]; int io_num_to_apic_id[NAPICID]; int apic_id_to_logical[NAPICID]; /* Bitmap of all available CPUs */ u_int all_cpus; /* Boot of AP uses this PTD */ u_int *bootPTD; /* Hotwire a 0->4MB V==P mapping */ extern pt_entry_t KPTphys; /* Virtual address of per-cpu common_tss */ extern struct i386tss common_tss; /* * Local data and functions. */ static int mp_capable; static u_int boot_address; static u_int base_memory; static int picmode; /* 0: virtual wire mode, 1: PIC mode */ static mpfps_t mpfps; static int search_for_sig(u_int32_t target, int count); static void mp_enable(u_int boot_addr); static int mptable_pass1(void); static int mptable_pass2(void); static void default_mp_table(int type); static int start_all_aps(u_int boot_addr); static void install_ap_tramp(u_int boot_addr); static int start_ap(int logicalCpu, u_int boot_addr); /* * Calculate usable address in base memory for AP trampoline code. */ u_int mp_bootaddress(u_int basemem) { POSTCODE(MP_BOOTADDRESS_POST); base_memory = basemem * 1024; /* convert to bytes */ boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ if ((base_memory - boot_address) < bootMP_size) boot_address -= 4096; /* not enough, lower by 4k */ return boot_address; } /* * Look for an Intel MP spec table (ie, SMP capable hardware). */ int mp_probe(void) { int x; u_long segment; u_int32_t target; POSTCODE(MP_PROBE_POST); /* see if EBDA exists */ if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { /* search first 1K of EBDA */ target = (u_int32_t) (segment << 4); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } else { /* last 1K of base memory, effective 'top of base' passed in */ target = (u_int32_t) (base_memory - 0x400); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } /* search the BIOS */ target = (u_int32_t) BIOS_BASE; if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) goto found; /* nothing found */ mpfps = (mpfps_t)0; mp_capable = 0; return 0; found: /* calculate needed resources */ mpfps = (mpfps_t)x; if (mptable_pass1()) panic("you must reconfigure your kernel"); /* flag fact that we are running multiple processors */ mp_capable = 1; return 1; } /* * Startup the SMP processors. */ void mp_start(void) { POSTCODE(MP_START_POST); /* look for MP capable motherboard */ if (mp_capable) mp_enable(boot_address); else panic("MP hardware not found!"); } /* * Print various information about the SMP system hardware and setup. */ void mp_announce(void) { int x; POSTCODE(MP_ANNOUNCE_POST); printf("FreeBSD/SMP: Multiprocessor motherboard\n"); printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); printf(", version: 0x%08x", cpu_apic_versions[0]); printf(", at 0x%08x\n", cpu_apic_address); for (x = 1; x <= mp_naps; ++x) { printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); printf(", version: 0x%08x", cpu_apic_versions[x]); printf(", at 0x%08x\n", cpu_apic_address); } #if defined(APIC_IO) for (x = 0; x < mp_napics; ++x) { printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); printf(", version: 0x%08x", io_apic_versions[x]); printf(", at 0x%08x\n", io_apic_address[x]); } #else printf(" Warning: APIC I/O disabled\n"); #endif /* APIC_IO */ } /* * AP cpu's call this to sync up protected mode. */ void init_secondary(void) { int gsel_tss, slot; r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; r_gdt.rd_base = (int) gdt; lgdt(&r_gdt); /* does magic intra-segment return */ lidt(&r_idt); lldt(_default_ldt); slot = NGDT + cpuid; gsel_tss = GSEL(slot, SEL_KPL); gdt[slot].sd.sd_type = SDT_SYS386TSS; common_tss.tss_esp0 = 0; /* not used until after switch */ common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); common_tss.tss_ioopt = (sizeof common_tss) << 16; ltr(gsel_tss); load_cr0(0x8005003b); /* XXX! */ PTD[0] = 0; pmap_set_opt((unsigned *)PTD); invltlb(); } #if defined(APIC_IO) /* * Final configuration of the BSP's local APIC: * - disable 'pic mode'. * - disable 'virtual wire mode'. * - enable NMI. */ void bsp_apic_configure(void) { u_char byte; u_int32_t temp; /* leave 'pic mode' if necessary */ if (picmode) { outb(0x22, 0x70); /* select IMCR */ byte = inb(0x23); /* current contents */ byte |= 0x01; /* mask external INTR */ outb(0x23, byte); /* disconnect 8259s/NMI */ } /* mask lint0 (the 8259 'virtual wire' connection) */ temp = lapic.lvt_lint0; temp |= APIC_LVT_M; /* set the mask */ lapic.lvt_lint0 = temp; /* setup lint1 to handle NMI */ temp = lapic.lvt_lint1; temp &= ~APIC_LVT_M; /* clear the mask */ lapic.lvt_lint1 = temp; if (bootverbose) apic_dump(); } #endif /* APIC_IO */ /******************************************************************* * local functions and data */ /* * start the SMP system */ static void mp_enable(u_int boot_addr) { int x; #if defined(APIC_IO) int apic; u_int ux; #endif /* APIC_IO */ POSTCODE(MP_ENABLE_POST); /* turn on 4MB of V == P addressing so we can get to MP table */ *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); invltlb(); /* examine the MP table for needed info, uses physical addresses */ x = mptable_pass2(); *(int *)PTD = 0; invltlb(); /* can't process default configs till the CPU APIC is pmapped */ if (x) default_mp_table(x); #if defined(APIC_IO) /* fill the LOGICAL io_apic_versions table */ for (apic = 0; apic < mp_napics; ++apic) { ux = io_apic_read(apic, IOAPIC_VER); io_apic_versions[apic] = ux; } /* program each IO APIC in the system */ for (apic = 0; apic < mp_napics; ++apic) if (io_apic_setup(apic) < 0) panic("IO APIC setup failure"); /* install a 'Spurious INTerrupt' vector */ setidt(XSPURIOUSINT_OFFSET, Xspuriousint, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); /* install an inter-CPU IPI for TLB invalidation */ setidt(XINVLTLB_OFFSET, Xinvltlb, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#if defined(TEST_CPUSTOP) /* install an inter-CPU IPI for CPU stop/restart */ setidt(XCPUSTOP_OFFSET, Xcpustop, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#endif /** TEST_CPUSTOP */ #if defined(TEST_TEST1) - /* install a 'Spurious INTerrupt' vector */ + /* install a "fake hardware INTerrupt" vector */ setidt(XTEST1_OFFSET, Xtest1, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /** TEST_TEST1 */ #endif /* APIC_IO */ /* start each Application Processor */ start_all_aps(boot_addr); /* * The init process might be started on a different CPU now, * and the boot CPU might not call prepare_usermode to get * cr0 correctly configured. Thus we initialize cr0 here. */ load_cr0(rcr0() | CR0_WP | CR0_AM); } /* * look for the MP spec signature */ /* string defined by the Intel MP Spec as identifying the MP table */ #define MP_SIG 0x5f504d5f /* _MP_ */ #define NEXT(X) ((X) += 4) static int search_for_sig(u_int32_t target, int count) { int x; u_int32_t *addr = (u_int32_t *) (KERNBASE + target); for (x = 0; x < count; NEXT(x)) if (addr[x] == MP_SIG) /* make array index a byte index */ return (target + (x * sizeof(u_int32_t))); return -1; } static basetable_entry basetable_entry_types[] = { {0, 20, "Processor"}, {1, 8, "Bus"}, {2, 8, "I/O APIC"}, {3, 8, "I/O INT"}, {4, 8, "Local INT"} }; typedef struct BUSDATA { u_char bus_id; enum busTypes bus_type; } bus_datum; typedef struct INTDATA { u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } io_int, local_int; typedef struct BUSTYPENAME { u_char type; char name[7]; } bus_type_name; static bus_type_name bus_type_table[] = { {CBUS, "CBUS"}, {CBUSII, "CBUSII"}, {EISA, "EISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {ISA, "ISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {PCI, "PCI"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {XPRESS, "XPRESS"}, {UNKNOWN_BUSTYPE, "---"} }; /* from MP spec v1.4, table 5-1 */ static int default_data[7][5] = { /* nbus, id0, type0, id1, type1 */ {1, 0, ISA, 255, 255}, {1, 0, EISA, 255, 255}, {1, 0, EISA, 255, 255}, {0, 255, 255, 255, 255},/* MCA not supported */ {2, 0, ISA, 1, PCI}, {2, 0, EISA, 1, PCI}, {0, 255, 255, 255, 255} /* MCA not supported */ }; /* the bus data */ bus_datum bus_data[NBUS]; /* the IO INT data, one entry per possible APIC INTerrupt */ io_int io_apic_ints[NINTR]; static int nintrs; static void fix_mp_table __P((void)); static int processor_entry __P((proc_entry_ptr entry, int cpu)); static int bus_entry __P((bus_entry_ptr entry, int bus)); static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); static int int_entry __P((int_entry_ptr entry, int intr)); static int lookup_bus_type __P((char *name)); /* * 1st pass on motherboard's Intel MP specification table. * * initializes: * mp_ncpus = 1 * * determines: * cpu_apic_address (common to all CPUs) * io_apic_address[N] * mp_naps * mp_nbusses * mp_napics * nintrs */ static int mptable_pass1(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int mustpanic; POSTCODE(MPTABLE_PASS1_POST); mustpanic = 0; /* clear various tables */ for (x = 0; x < NAPICID; ++x) { io_apic_address[x] = ~0; /* IO APIC address table */ } /* init everything to empty */ mp_naps = 0; mp_nbusses = 0; mp_napics = 0; nintrs = 0; /* check for use of 'default' configuration */ if (mpfps->mpfb1 != 0) { /* use default addresses */ cpu_apic_address = DEFAULT_APIC_BASE; io_apic_address[0] = DEFAULT_IO_APIC_BASE; /* fill in with defaults */ mp_naps = 2; /* includes BSP */ mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; #if defined(APIC_IO) mp_napics = 1; nintrs = 16; #endif /* APIC_IO */ } else { if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); cpu_apic_address = (vm_offset_t) cth->apic_address; /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; while (count--) { switch (type = *(u_char *) position) { case 0: /* processor_entry */ if (((proc_entry_ptr)position)->cpu_flags & PROCENTRY_FLAG_EN) ++mp_naps; break; case 1: /* bus_entry */ ++mp_nbusses; break; case 2: /* io_apic_entry */ if (((io_apic_entry_ptr)position)->apic_flags & IOAPICENTRY_FLAG_EN) io_apic_address[mp_napics++] = (vm_offset_t)((io_apic_entry_ptr) position)->apic_address; break; case 3: /* int_entry */ ++nintrs; break; case 4: /* int_entry */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char*)position += basetable_entry_types[type].length; } } /* qualify the numbers */ if (mp_naps > NCPU) printf("Warning: only using %d of %d available CPUs!\n", NCPU, mp_naps); #if 0 /** XXX we consider this legal now (but should we?) */ mustpanic = 1; #endif if (mp_nbusses > NBUS) { printf("found %d busses, increase NBUS\n", mp_nbusses); mustpanic = 1; } if (mp_napics > NAPIC) { printf("found %d apics, increase NAPIC\n", mp_napics); mustpanic = 1; } if (nintrs > NINTR) { printf("found %d intrs, increase NINTR\n", nintrs); mustpanic = 1; } /* * Count the BSP. * This is also used as a counter while starting the APs. */ mp_ncpus = 1; --mp_naps; /* subtract the BSP */ return mustpanic; } /* * 2nd pass on motherboard's Intel MP specification table. * * sets: * boot_cpu_id * ID_TO_IO(N), phy APIC ID to log CPU/IO table * CPU_TO_ID(N), logical CPU to APIC ID table * IO_TO_ID(N), logical IO to APIC ID table * bus_data[N] * io_apic_ints[N] */ static int mptable_pass2(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int apic, bus, cpu, intr; POSTCODE(MPTABLE_PASS2_POST); /* clear various tables */ for (x = 0; x < NAPICID; ++x) { ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ } /* clear bus data table */ for (x = 0; x < NBUS; ++x) bus_data[x].bus_id = 0xff; /* clear IO APIC INT table */ for (x = 0; x < NINTR; ++x) io_apic_ints[x].int_type = 0xff; /* setup the cpu/apic mapping arrays */ boot_cpu_id = -1; /* record whether PIC or virtual-wire mode */ picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; /* check for use of 'default' configuration */ #if defined(TEST_DEFAULT_CONFIG) return TEST_DEFAULT_CONFIG; #else if (mpfps->mpfb1 != 0) return mpfps->mpfb1; /* return default configuration type */ #endif /* TEST_DEFAULT_CONFIG */ if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; apic = bus = intr = 0; cpu = 1; /* pre-count the BSP */ while (count--) { switch (type = *(u_char *) position) { case 0: if (processor_entry(position, cpu)) ++cpu; break; case 1: if (bus_entry(position, bus)) ++bus; break; case 2: if (io_apic_entry(position, apic)) ++apic; break; case 3: if (int_entry(position, intr)) ++intr; break; case 4: /* int_entry(position); */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char *) position += basetable_entry_types[type].length; } if (boot_cpu_id == -1) panic("NO BSP found!"); /* post scan cleanup */ fix_mp_table(); /* report fact that its NOT a default configuration */ return 0; } /* * parse an Intel MP specification table */ static void fix_mp_table(void) { int x; int id; int bus_0; int bus_pci; int num_pci_bus; /* * Fix mis-numbering of the PCI bus and its INT entries if the BIOS * did it wrong. The MP spec says that when more than 1 PCI bus * exists the BIOS must begin with bus entries for the PCI bus and use * actual PCI bus numbering. This implies that when only 1 PCI bus * exists the BIOS can choose to ignore this ordering, and indeed many * MP motherboards do ignore it. This causes a problem when the PCI * sub-system makes requests of the MP sub-system based on PCI bus * numbers. So here we look for the situation and renumber the * busses and associated INTs in an effort to "make it right". */ /* find bus 0, PCI bus, count the number of PCI busses */ for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_id == 0) { bus_0 = x; } if (bus_data[x].bus_type == PCI) { ++num_pci_bus; bus_pci = x; } } /* * bus_0 == slot of bus with ID of 0 * bus_pci == slot of last PCI bus encountered */ /* check the 1 PCI bus case for sanity */ if (num_pci_bus == 1) { /* if it is number 0 all is well */ if (bus_data[bus_pci].bus_id == 0) return; /* mis-numbered, swap with whichever bus uses slot 0 */ /* swap the bus entry types */ bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; bus_data[bus_0].bus_type = PCI; /* swap each relavant INTerrupt entry */ id = bus_data[bus_pci].bus_id; for (x = 0; x < nintrs; ++x) { if (io_apic_ints[x].src_bus_id == id) { io_apic_ints[x].src_bus_id = 0; } else if (io_apic_ints[x].src_bus_id == 0) { io_apic_ints[x].src_bus_id = id; } } } /* sanity check if more than 1 PCI bus */ else if (num_pci_bus > 1) { for (x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_type != PCI) continue; if (bus_data[x].bus_id >= num_pci_bus) panic("bad PCI bus numbering"); } } } static int processor_entry(proc_entry_ptr entry, int cpu) { /* check for usability */ if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) return 0; /* check for BSP flag */ if (entry->cpu_flags & PROCENTRY_FLAG_BP) { boot_cpu_id = entry->apic_id; CPU_TO_ID(0) = entry->apic_id; ID_TO_CPU(entry->apic_id) = 0; return 0; /* its already been counted */ } /* add another AP to list, if less than max number of CPUs */ else { CPU_TO_ID(cpu) = entry->apic_id; ID_TO_CPU(entry->apic_id) = cpu; return 1; } } static int bus_entry(bus_entry_ptr entry, int bus) { int x; char c, name[8]; /* encode the name into an index */ for (x = 0; x < 6; ++x) { if ((c = entry->bus_type[x]) == ' ') break; name[x] = c; } name[x] = '\0'; if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) panic("unknown bus type: '%s'", name); bus_data[bus].bus_id = entry->bus_id; bus_data[bus].bus_type = x; return 1; } static int io_apic_entry(io_apic_entry_ptr entry, int apic) { if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) return 0; IO_TO_ID(apic) = entry->apic_id; ID_TO_IO(entry->apic_id) = apic; return 1; } static int lookup_bus_type(char *name) { int x; for (x = 0; x < MAX_BUSTYPE; ++x) if (strcmp(bus_type_table[x].name, name) == 0) return bus_type_table[x].type; return UNKNOWN_BUSTYPE; } static int int_entry(int_entry_ptr entry, int intr) { io_apic_ints[intr].int_type = entry->int_type; io_apic_ints[intr].int_flags = entry->int_flags; io_apic_ints[intr].src_bus_id = entry->src_bus_id; io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; return 1; } static int apic_int_is_bus_type(int intr, int bus_type) { int bus; for (bus = 0; bus < mp_nbusses; ++bus) if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) && ((int) bus_data[bus].bus_type == bus_type)) return 1; return 0; } /* * Given a traditional ISA INT mask, return an APIC mask. */ u_int isa_apic_mask(u_int isa_mask) { int isa_irq; int apic_pin; #if defined(SKIP_IRQ15_REDIRECT) if (isa_mask == (1 << 15)) { printf("skipping ISA IRQ15 redirect\n"); return isa_mask; } #endif /* SKIP_IRQ15_REDIRECT */ isa_irq = ffs(isa_mask); /* find its bit position */ if (isa_irq == 0) /* doesn't exist */ return 0; --isa_irq; /* make it zero based */ apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ if (apic_pin == -1) return 0; return (1 << apic_pin); /* convert pin# to a mask */ } /* * Determine which APIC pin an ISA/EISA INT is attached to. */ #define INTTYPE(I) (io_apic_ints[(I)].int_type) #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) int isa_apic_pin(int isa_irq) { int intr; #if defined(SMP_TIMER_NC) if (isa_irq == 0) return -1; #endif /* SMP_TIMER_NC */ for (intr = 0; intr < nintrs; ++intr) { /* check each record */ if (INTTYPE(intr) == 0) { /* standard INT */ if (SRCBUSIRQ(intr) == isa_irq) { if (apic_int_is_bus_type(intr, ISA) || apic_int_is_bus_type(intr, EISA)) return INTPIN(intr); /* found */ } } } return -1; /* NOT found */ } #undef SRCBUSIRQ /* * Determine which APIC pin a PCI INT is attached to. */ #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) int pci_apic_pin(int pciBus, int pciDevice, int pciInt) { int intr; --pciInt; /* zero based */ for (intr = 0; intr < nintrs; ++intr) /* check each record */ if ((INTTYPE(intr) == 0) /* standard INT */ && (SRCBUSID(intr) == pciBus) && (SRCBUSDEVICE(intr) == pciDevice) && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ if (apic_int_is_bus_type(intr, PCI)) return INTPIN(intr); /* exact match */ return -1; /* NOT found */ } #undef SRCBUSLINE #undef SRCBUSDEVICE #undef SRCBUSID #undef INTPIN #undef INTTYPE /* * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. * * XXX FIXME: * Exactly what this means is unclear at this point. It is a solution * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard * could route any of the ISA INTs to upper (>15) IRQ values. But most would * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an * option. */ int undirect_isa_irq(int rirq) { #if defined(READY) printf("Freeing redirected ISA irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); return 0; #endif /* READY */ } /* * Reprogram the MB chipset to NOT redirect a PCI INTerrupt */ int undirect_pci_irq(int rirq) { #if defined(READY) if (bootverbose) printf("Freeing redirected PCI irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else if (bootverbose) printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); return 0; #endif /* READY */ } /* * given a bus ID, return: * the bus type if found * -1 if NOT found */ int apic_bus_type(int id) { int x; for (x = 0; x < mp_nbusses; ++x) if (bus_data[x].bus_id == id) return bus_data[x].bus_type; return -1; } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus ID if found * -1 if NOT found */ int apic_src_bus_id(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_id); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus IRQ if found * -1 if NOT found */ int apic_src_bus_irq(int apic, int pin) { int x; for (x = 0; x < nintrs; x++) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_irq); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated INTerrupt type if found * -1 if NOT found */ int apic_int_type(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_type); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated trigger mode if found * -1 if NOT found */ int apic_trigger(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return ((io_apic_ints[x].int_flags >> 2) & 0x03); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated 'active' level if found * -1 if NOT found */ int apic_polarity(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_flags & 0x03); return -1; /* NOT found */ } /* * set data according to MP defaults * FIXME: probably not complete yet... */ static void default_mp_table(int type) { int ap_cpu_id; #if defined(APIC_IO) u_int32_t ux; int io_apic_id; int pin; #endif /* APIC_IO */ #if 0 printf(" MP default config type: %d\n", type); switch (type) { case 1: printf(" bus: ISA, APIC: 82489DX\n"); break; case 2: printf(" bus: EISA, APIC: 82489DX\n"); break; case 3: printf(" bus: EISA, APIC: 82489DX\n"); break; case 4: printf(" bus: MCA, APIC: 82489DX\n"); break; case 5: printf(" bus: ISA+PCI, APIC: Integrated\n"); break; case 6: printf(" bus: EISA+PCI, APIC: Integrated\n"); break; case 7: printf(" bus: MCA+PCI, APIC: Integrated\n"); break; default: printf(" future type\n"); break; /* NOTREACHED */ } #endif /* 0 */ boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; /* BSP */ CPU_TO_ID(0) = boot_cpu_id; ID_TO_CPU(boot_cpu_id) = 0; /* one and only AP */ CPU_TO_ID(1) = ap_cpu_id; ID_TO_CPU(ap_cpu_id) = 1; #if defined(APIC_IO) /* one and only IO APIC */ io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; /* * sanity check, refer to MP spec section 3.6.6, last paragraph * necessary as some hardware isn't properly setting up the IO APIC */ #if defined(REALLY_ANAL_IOAPICID_VALUE) if (io_apic_id != 2) { #else if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { #endif /* REALLY_ANAL_IOAPICID_VALUE */ ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ ux &= ~APIC_ID_MASK; /* clear the ID field */ ux |= 0x02000000; /* set it to '2' */ io_apic_write(0, IOAPIC_ID, ux); /* write new value */ ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ if ((ux & APIC_ID_MASK) != 0x02000000) panic("can't control IO APIC ID, reg: 0x%08x", ux); io_apic_id = 2; } IO_TO_ID(0) = io_apic_id; ID_TO_IO(io_apic_id) = 0; #endif /* APIC_IO */ /* fill out bus entries */ switch (type) { case 1: case 2: case 3: case 5: case 6: bus_data[0].bus_id = default_data[type - 1][1]; bus_data[0].bus_type = default_data[type - 1][2]; bus_data[1].bus_id = default_data[type - 1][3]; bus_data[1].bus_type = default_data[type - 1][4]; break; /* case 4: case 7: MCA NOT supported */ default: /* illegal/reserved */ panic("BAD default MP config: %d", type); /* NOTREACHED */ } #if defined(APIC_IO) /* general cases from MP v1.4, table 5-2 */ for (pin = 0; pin < 16; ++pin) { io_apic_ints[pin].int_type = 0; io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ io_apic_ints[pin].src_bus_id = 0; io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ io_apic_ints[pin].dst_apic_id = io_apic_id; io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ } /* special cases from MP v1.4, table 5-2 */ if (type == 2) { io_apic_ints[2].int_type = 0xff; /* N/C */ io_apic_ints[13].int_type = 0xff; /* N/C */ #if !defined(APIC_MIXED_MODE) /** FIXME: ??? */ panic("sorry, can't support type 2 default yet"); #endif /* APIC_MIXED_MODE */ } else io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ if (type == 7) io_apic_ints[0].int_type = 0xff; /* N/C */ else io_apic_ints[0].int_type = 3; /* vectored 8259 */ #endif /* APIC_IO */ } /* * start each AP in our list */ static int start_all_aps(u_int boot_addr) { int x, i; u_char mpbiosreason; u_long mpbioswarmvec; pd_entry_t newptd; pt_entry_t newpt; int *newpp; POSTCODE(START_ALL_APS_POST); /** * NOTE: this needs further thought: * where does it get released? * should it be set to empy? * * get the initial mp_lock with a count of 1 for the BSP */ mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ /* initialize BSP's local APIC */ apic_initialize(); /* install the AP 1st level boot code */ install_ap_tramp(boot_addr); /* save the current value of the warm-start vector */ mpbioswarmvec = *((u_long *) WARMBOOT_OFF); outb(CMOS_REG, BIOS_RESET); mpbiosreason = inb(CMOS_DATA); /* record BSP in CPU map */ all_cpus = 1; /* start each AP */ for (x = 1; x <= mp_naps; ++x) { /* HACK HACK HACK !!! */ /* alloc new page table directory */ newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* clone currently active one (ie: IdlePTD) */ bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ /* set up 0 -> 4MB P==V mapping for AP boot */ newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); /* store PTD for this AP */ bootPTD = (pd_entry_t)vtophys(newptd); /* alloc new page table page */ newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* set the new PTD's private page to point there */ newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); /* install self referential entry */ newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); /* get a new private data page */ newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); /* wire it into the private page table page */ newpt[0] = PG_V | PG_RW | vtophys(newpp); /* wire the ptp into itself for access */ newpt[1] = PG_V | PG_RW | vtophys(newpt); /* and the local apic */ newpt[2] = SMP_prvpt[2]; /* and the IO apic mapping[s] */ for (i = 16; i < 32; i++) newpt[i] = SMP_prvpt[i]; /* prime data page for it to use */ newpp[0] = x; /* cpuid */ newpp[1] = 0; /* curproc */ newpp[2] = 0; /* curpcb */ newpp[3] = 0; /* npxproc */ newpp[4] = 0; /* runtime.tv_sec */ newpp[5] = 0; /* runtime.tv_usec */ newpp[6] = x << 24; /* cpu_lockid */ /* XXX NOTE: ABANDON bootPTD for now!!!! */ /* END REVOLTING HACKERY */ /* setup a vector to our boot code */ *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ /* attempt to start the Application Processor */ CHECK_INIT(99); /* setup checkpoints */ if (!start_ap(x, boot_addr)) { printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); CHECK_PRINT("trace"); /* show checkpoints */ /* better panic as the AP may be running loose */ printf("panic y/n? [y] "); if (cngetc() != 'n') panic("bye-bye"); } CHECK_PRINT("trace"); /* show checkpoints */ /* record its version info */ cpu_apic_versions[x] = cpu_apic_versions[0]; all_cpus |= (1 << x); /* record AP in CPU map */ } /* build our map of 'other' CPUs */ other_cpus = all_cpus & ~(1 << cpuid); /* fill in our (BSP) APIC version */ cpu_apic_versions[0] = lapic.version; /* restore the warmstart vector */ *(u_long *) WARMBOOT_OFF = mpbioswarmvec; outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, mpbiosreason); pmap_set_opt_bsp(); /* number of APs actually started */ return mp_ncpus - 1; } /* * load the 1st level AP boot code into base memory. */ /* targets for relocation */ extern void bigJump(void); extern void bootCodeSeg(void); extern void bootDataSeg(void); extern void MPentry(void); extern u_int MP_GDT; extern u_int mp_gdtbase; static void install_ap_tramp(u_int boot_addr) { int x; int size = *(int *) ((u_long) & bootMP_size); u_char *src = (u_char *) ((u_long) bootMP); u_char *dst = (u_char *) boot_addr + KERNBASE; u_int boot_base = (u_int) bootMP; u_int8_t *dst8; u_int16_t *dst16; u_int32_t *dst32; POSTCODE(INSTALL_AP_TRAMP_POST); for (x = 0; x < size; ++x) *dst++ = *src++; /* * modify addresses in code we just moved to basemem. unfortunately we * need fairly detailed info about mpboot.s for this to work. changes * to mpboot.s might require changes here. */ /* boot code is located in KERNEL space */ dst = (u_char *) boot_addr + KERNBASE; /* modify the lgdt arg */ dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); /* modify the ljmp target for MPentry() */ dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); *dst32 = ((u_int) MPentry - KERNBASE); /* modify the target for boot code segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; /* modify the target for boot data segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; } /* * this function starts the AP (application processor) identified * by the APIC ID 'physicalCpu'. It does quite a "song and dance" * to accomplish this. This is necessary because of the nuances * of the different hardware we might encounter. It ain't pretty, * but it seems to work. */ static int start_ap(int logical_cpu, u_int boot_addr) { int physical_cpu; int vector; int cpus; u_long icr_lo, icr_hi; POSTCODE(START_AP_POST); /* get the PHYSICAL APIC ID# */ physical_cpu = CPU_TO_ID(logical_cpu); /* calculate the vector */ vector = (boot_addr >> 12) & 0xff; /* used as a watchpoint to signal AP startup */ cpus = mp_ncpus; /* * first we do an INIT/RESET IPI this INIT IPI might be run, reseting * and running the target CPU. OR this INIT IPI might be latched (P5 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be * ignored. */ /* setup the address for the target AP */ icr_hi = lapic.icr_hi & ~APIC_ID_MASK; icr_hi |= (physical_cpu << 24); lapic.icr_hi = icr_hi; /* do an INIT IPI: assert RESET */ icr_lo = lapic.icr_lo & 0xfff00000; lapic.icr_lo = icr_lo | 0x0000c500; /* wait for pending status end */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* do an INIT IPI: deassert RESET */ lapic.icr_lo = icr_lo | 0x00008500; /* wait for pending status end */ u_sleep(10000); /* wait ~10mS */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* * next we do a STARTUP IPI: the previous INIT IPI might still be * latched, (P5 bug) this 1st STARTUP would then terminate * immediately, and the previously started INIT IPI would continue. OR * the previous INIT IPI has already run. and this STARTUP IPI will * run. OR the previous INIT IPI was ignored. and this STARTUP IPI * will run. */ /* do a STARTUP IPI */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is * recognized after hardware RESET or INIT IPI. */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* wait for it to start */ set_apic_timer(5000000);/* == 5 seconds */ while (read_apic_timer()) if (mp_ncpus > cpus) return 1; /* return SUCCESS */ return 0; /* return FAILURE */ } /* * Flush the TLB on all other CPU's * * XXX: Needs to handshake and wait for completion before proceding. */ void smp_invltlb(void) { #if defined(APIC_IO) if (smp_active && invltlb_ok) all_but_self_ipi(XINVLTLB_OFFSET); #endif /* APIC_IO */ } void invlpg(u_int addr) { __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); /* send a message to the other CPUs */ smp_invltlb(); } void invltlb(void) { u_long temp; /* * This should be implemented as load_cr3(rcr3()) when load_cr3() is * inlined. */ __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); /* send a message to the other CPUs */ smp_invltlb(); } -#if defined(TEST_CPUSTOP) - -#if defined(DEBUG_CPUSTOP) -void db_printf __P((const char *fmt, ...)); -#endif /* DEBUG_CPUSTOP */ - /* * When called the executing CPU will send an IPI to all other CPUs * requesting that they halt execution. * * Usually (but not necessarily) called with 'other_cpus' as its arg. * * - Signals all CPUs in map to stop. * - Waits for each to stop. * * Returns: * -1: error * 0: NA * 1: ok * * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs * from executing at same time. */ int stop_cpus( u_int map ) { if (!smp_active) return 0; /* send IPI to all CPUs in map */ -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); -#endif /* DEBUG_CPUSTOP */ - stopped_cpus = 0; /* send the Xcpustop IPI to all CPUs in map */ selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); -#if defined(DEBUG_CPUSTOP) - db_printf(" spin\n"); -#endif /* DEBUG_CPUSTOP */ - while (stopped_cpus != map) /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" spun\nstopped\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } /* * Called by a CPU to restart stopped CPUs. * * Usually (but not necessarily) called with 'stopped_cpus' as its arg. * * - Signals all CPUs in map to restart. * - Waits for each to restart. * * Returns: * -1: error * 0: NA * 1: ok */ int restart_cpus( u_int map ) { if (!smp_active) return 0; -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", - cpuid, map, stopped_cpus); -#endif /* DEBUG_CPUSTOP */ - started_cpus = map; /* signal other cpus to restart */ while (started_cpus) /* wait for each to clear its bit */ /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" restarted\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } - -#endif /** TEST_CPUSTOP */ Index: head/sys/i386/i386/mpapic.c =================================================================== --- head/sys/i386/i386/mpapic.c (revision 27516) +++ head/sys/i386/i386/mpapic.c (revision 27517) @@ -1,811 +1,811 @@ /* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: mpapic.c,v 1.12 1997/07/15 02:51:19 fsmp Exp $ + * $Id: mpapic.c,v 1.13 1997/07/18 19:45:41 smp Exp smp $ */ #include "opt_smp.h" #include #include #include +#include /** TEST_LOPRIO, TEST_IPI, TEST_ALTTIMER */ #include #include -#include /** TEST_LOPRIO, TEST_IPI, TEST_CPUSTOP, TEST_ALTTIMER */ #include #include #include /* Xspuriousint() */ /* EISA Edge/Level trigger control registers */ #define ELCR0 0x4d0 /* eisa irq 0-7 */ #define ELCR1 0x4d1 /* eisa irq 8-15 */ /* * pointers to pmapped apic hardware. */ #if defined(APIC_IO) volatile ioapic_t *ioapic[NAPIC]; #endif /* APIC_IO */ /* * Enable APIC, configure interrupts. */ void apic_initialize(void) { u_int temp; /* setup LVT1 as ExtINT */ temp = lapic.lvt_lint0; temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM); if (cpuid == 0) temp |= 0x00000700; /* process ExtInts */ else temp |= 0x00010700; /* mask ExtInts */ lapic.lvt_lint0 = temp; /* setup LVT2 as NMI, masked till later... */ temp = lapic.lvt_lint1; temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM); temp |= 0x00010400; /* masked, edge trigger, active hi */ lapic.lvt_lint1 = temp; /* set the Task Priority Register as needed */ temp = lapic.tpr; temp &= ~APIC_TPR_PRIO; /* clear priority field */ #if defined(TEST_LOPRIO) temp |= LOPRIO_LEVEL; /* allow INT arbitration */ #endif /* TEST_LOPRIO */ lapic.tpr = temp; /* enable the local APIC */ temp = lapic.svr; temp |= APIC_SVR_SWEN; /* software enable APIC */ temp &= ~APIC_SVR_FOCUS; /* enable 'focus processor' */ /* set the 'spurious INT' vector */ if ((XSPURIOUSINT_OFFSET & APIC_SVR_VEC_FIX) != APIC_SVR_VEC_FIX) panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET); temp &= ~APIC_SVR_VEC_PROG; /* clear (programmable) vector field */ temp |= (XSPURIOUSINT_OFFSET & APIC_SVR_VEC_PROG); #if defined(TEST_TEST1) if (cpuid == GUARD_CPU) { temp &= ~APIC_SVR_SWEN; /* software DISABLE APIC */ } #endif /** TEST_TEST1 */ lapic.svr = temp; if (bootverbose) apic_dump(); } /* * dump contents of local APIC registers */ void apic_dump(void) { printf("SMP: CPU%02d bsp_apic_configure() lint0: 0x%08x\n", cpuid, lapic.lvt_lint0); printf(" lint1: 0x%08x\n", lapic.lvt_lint1); printf(" TPR: 0x%08x\n", lapic.tpr); printf(" SVR: 0x%08x\n", lapic.svr); } #if defined(APIC_IO) /* * IO APIC code, */ #define IOAPIC_ISA_INTS 16 #define REDIRCNT_IOAPIC(A) \ ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1) static int trigger __P((int apic, int pin, u_int32_t * flags)); static void polarity __P((int apic, int pin, u_int32_t * flags, int level)); #if defined(TEST_LOPRIO) #define DEFAULT_FLAGS \ ((u_int32_t) \ (IOART_INTMSET | \ IOART_DESTPHY | \ IOART_DELLOPRI)) #define DEFAULT_ISA_FLAGS \ ((u_int32_t) \ (IOART_INTMSET | \ IOART_TRGREDG | \ IOART_INTAHI | \ IOART_DESTPHY | \ IOART_DELLOPRI)) #else #define DEFAULT_FLAGS \ ((u_int32_t) \ (IOART_INTMSET | \ IOART_DESTPHY | \ IOART_DELFIXED)) #define DEFAULT_ISA_FLAGS \ ((u_int32_t) \ (IOART_INTMSET | \ IOART_TRGREDG | \ IOART_INTAHI | \ IOART_DESTPHY | \ IOART_DELFIXED)) #endif /* TEST_LOPRIO */ /* * Setup the IO APIC. */ int io_apic_setup(int apic) { int maxpin; u_char select; /* the select register is 8 bits */ u_int32_t flags; /* the window register is 32 bits */ u_int32_t target; /* the window register is 32 bits */ u_int32_t vector; /* the window register is 32 bits */ int pin, level; #if defined(TEST_LOPRIO) target = IOART_DEST; #else target = boot_cpu_id << 24; #endif /* TEST_LOPRIO */ if (apic == 0) { maxpin = REDIRCNT_IOAPIC(apic); /* pins-1 in APIC */ for (pin = 0; pin < maxpin; ++pin) { int bus, bustype; /* we only deal with vectored INTs here */ if (apic_int_type(apic, pin) != 0) continue; /* determine the bus type for this pin */ bus = apic_src_bus_id(apic, pin); if (bus == -1) continue; bustype = apic_bus_type(bus); /* the "ISA" type INTerrupts */ if ((bustype == ISA) || (bustype == EISA)) { flags = DEFAULT_ISA_FLAGS; } /* PCI or other bus */ else { flags = DEFAULT_FLAGS; level = trigger(apic, pin, &flags); polarity(apic, pin, &flags, level); } /* program the appropriate registers */ select = pin * 2 + IOAPIC_REDTBL0; /* register */ vector = NRSVIDT + pin; /* IDT vec */ io_apic_write(apic, select, flags | vector); io_apic_write(apic, select + 1, target); } } /* program entry according to MP table. */ else { #if defined(MULTIPLE_IOAPICS) #error MULTIPLE_IOAPICSXXX #else panic("io_apic_setup: apic #%d", apic); #endif/* MULTIPLE_IOAPICS */ } /* return GOOD status */ return 0; } #undef DEFAULT_ISA_FLAGS #undef DEFAULT_FLAGS #if defined(TEST_ALTTIMER) #if defined(TIMER_ALL) #define DEL_MODE IOART_DELLOPRI #else #define DEL_MODE IOART_DELFIXED #endif /** TIMER_ALL */ #else #define DEL_MODE IOART_DELEXINT #endif /** TEST_ALTTIMER */ #define DEFAULT_EXTINT_FLAGS \ ((u_int32_t) \ (IOART_INTMSET | \ IOART_TRGREDG | \ IOART_INTAHI | \ IOART_DESTPHY | \ DEL_MODE)) /* * Setup the source of External INTerrupts. */ int ext_int_setup(int apic, int intr) { u_char select; /* the select register is 8 bits */ u_int32_t flags; /* the window register is 32 bits */ u_int32_t target; /* the window register is 32 bits */ u_int32_t vector; /* the window register is 32 bits */ if (apic_int_type(apic, intr) != 3) return -1; /** XXX FIXME: changed on 970708, make default if no complaints */ #if defined(TIMER_ALL) target = IOART_DEST; #else target = boot_cpu_id << 24; #endif /* TIMER_ALL */ select = IOAPIC_REDTBL0 + (2 * intr); vector = NRSVIDT + intr; flags = DEFAULT_EXTINT_FLAGS; io_apic_write(apic, select, flags | vector); io_apic_write(apic, select + 1, target); #if defined(TEST_ALTTIMER) printf("SMP: using ALT timer setup\n"); #endif /** TEST_ALTTIMER */ return 0; } #undef DEL_MODE #undef DEFAULT_EXTINT_FLAGS /* * Set the trigger level for an IO APIC pin. */ static int trigger(int apic, int pin, u_int32_t * flags) { int id; int eirq; int level; static int intcontrol = -1; switch (apic_trigger(apic, pin)) { case 0x00: break; case 0x01: *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */ return 0; case 0x03: *flags |= IOART_TRGRLVL; return 1; case -1: default: goto bad; } if ((id = apic_src_bus_id(apic, pin)) == -1) goto bad; switch (apic_bus_type(id)) { case ISA: *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */ return 0; case EISA: eirq = apic_src_bus_irq(apic, pin); if (eirq < 0 || eirq > 15) { printf("EISA IRQ %d?!?!\n", eirq); goto bad; } if (intcontrol == -1) { intcontrol = inb(ELCR1) << 8; intcontrol |= inb(ELCR0); printf("EISA INTCONTROL = %08x\n", intcontrol); } /* * EISA IRQ's are identical to ISA irq's, regardless of * whether they are edge or level since they go through * the level/polarity converter gadget. */ level = 0; if (level) *flags |= IOART_TRGRLVL; else *flags &= ~IOART_TRGRLVL; return level; case PCI: *flags |= IOART_TRGRLVL; return 1; case -1: default: goto bad; } bad: panic("bad APIC IO INT flags"); } /* * Set the polarity value for an IO APIC pin. */ static void polarity(int apic, int pin, u_int32_t * flags, int level) { int id; int eirq; int pol; switch (apic_polarity(apic, pin)) { case 0x00: break; case 0x01: *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */ return; case 0x03: *flags |= IOART_INTALO; return; case -1: default: goto bad; } if ((id = apic_src_bus_id(apic, pin)) == -1) goto bad; switch (apic_bus_type(id)) { case ISA: *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */ return; case EISA: eirq = apic_src_bus_irq(apic, pin); if (eirq < 0 || eirq > 15) { printf("EISA POL: IRQ %d??\n", eirq); goto bad; } /* XXX EISA IRQ's are identical to ISA irq's, regardless of * whether they are edge or level since they go through the * level/polarity converter gadget. */ if (level == 1) /* XXX Always false */ pol = 0; /* if level, active low */ else pol = 1; /* if edge, high edge */ if (pol == 0) *flags |= IOART_INTALO; else *flags &= ~IOART_INTALO; return; case PCI: *flags |= IOART_INTALO; return; case -1: default: goto bad; } bad: panic("bad APIC IO INT flags"); } /* * Set INT mask bit for each bit set in 'mask'. * Clear INT mask bit for all others. * Only consider lower 24 bits in mask. */ #if defined(MULTIPLE_IOAPICS) #error MULTIPLE_IOAPICSXXX #else #define IO_MASK (imen & 0x00ffffff) #define IO_FIELD 0x00ffffff void write_io_apic_mask24(int apic, u_int32_t mask) { int x, y; u_char select; /* the select register is 8 bits */ u_int32_t low_reg; /* the window register is 32 bits */ u_int32_t diffs; mask &= IO_FIELD; /* safety valve, only use 24 bits */ if (mask == IO_MASK) /* check for same value as current */ return; diffs = mask ^ IO_MASK; /* record differences */ for (x = 0, y = REDIRCNT_IOAPIC(apic); x < y; ++x) { if (!(diffs & (1 << x))) continue; /* no change, skip */ select = IOAPIC_REDTBL + (x * 2); /* calculate addr */ low_reg = io_apic_read(apic, select); /* read contents */ if (mask & (1 << x)) low_reg |= IOART_INTMASK; /* set mask */ else low_reg &= ~IOART_INTMASK; /* clear mask */ io_apic_write(apic, select, low_reg); /* new value */ } } #endif /* MULTIPLE_IOAPICS */ #if defined(READY) /* * Read current IRQ0 -IRQ23 masks. */ #if defined(MULTIPLE_IOAPICS) #error MULTIPLE_IOAPICSXXX #else static __inline u_int32_t read_io_apic_mask24(int apic) { } #endif /* MULTIPLE_IOAPICS */ #endif /* READY */ #if defined(READY) /* * Set INT mask bit for each bit set in 'mask'. * Ignore INT mask bit for all others. * Only consider lower 24 bits in mask. */ void set_io_apic_mask24(apic, u_int32_t bits) { int x, y; u_char select; /* the select register is 8 bits */ u_int32_t low_reg; /* the window register is 32 bits */ u_int32_t diffs; bits &= IO_FIELD; /* safety valve, only use 24 bits */ diffs = bits & ~IO_MASK; /* clear AND needing 'set'ing */ if (!diffs) return; #error imen/io_apic_mask NOT merged in set_io_apic_mask24() for (x = 0, y = REDIRCNT_IOAPIC(apic); x < y; ++x) { if (!(diffs & (1 << x))) continue; /* no change, skip */ select = IOAPIC_REDTBL + (x * 2); /* calculate addr */ low_reg = io_apic_read(apic, select); /* read contents */ lowReg |= IOART_INTMASK; /* set mask */ io_apic_write(apic, select, low_reg); /* new value */ } } #endif /* READY */ #if defined(READY) /* * Clear INT mask bit for each bit set in 'mask'. * Ignore INT mask bit for all others. * Only consider lower 24 bits in mask. */ void clr_io_apic_mask24(int apic, u_int32_t bits) { int x, y; u_char select; /* the select register is 8 bits */ u_int32_t low_reg; /* the window register is 32 bits */ u_int32_t diffs; bits &= IO_FIELD; /* safety valve, only use 24 bits */ diffs = bits & IO_MASK; /* set AND needing 'clr'ing */ if (!diffs) return; #error imen/io_apic_mask NOT merged in clr_io_apic_mask24() for (x = 0, y = REDIRCNT_IOAPIC(apic); x < y; ++x) { if (!(diffs & (1 << x))) continue; /* no change, skip */ select = IOAPIC_REDTBL + (x * 2); /* calculate addr */ low_reg = io_apic_read(apic, select); /* read contents */ low_reg &= ~IOART_INTMASK; /* clear mask */ io_apic_write(apic, select, low_reg); /* new value */ } } #endif /* READY */ #undef IO_FIELD #undef IO_MASK /* * Inter Processor Interrupt functions. */ /* * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'. * * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF * vector is any valid SYSTEM INT vector * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO */ #define DETECT_DEADLOCK int apic_ipi(int dest_type, int vector, int delivery_mode) { u_long icr_lo; #if defined(DETECT_DEADLOCK) #define MAX_SPIN1 10000000 #define MAX_SPIN2 1000 int x; /* "lazy delivery", ie we only barf if they stack up on us... */ for (x = MAX_SPIN1; x; --x) { if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0) break; } if (x == 0) panic("apic_ipi was stuck"); #endif /* DETECT_DEADLOCK */ /* build IRC_LOW */ icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) | dest_type | delivery_mode | vector; /* write APIC ICR */ lapic.icr_lo = icr_lo; /* wait for pending status end */ #if defined(DETECT_DEADLOCK) for (x = MAX_SPIN2; x; --x) { if ((lapic.icr_lo & APIC_DELSTAT_MASK) == 0) break; } if (x == 0) printf("apic_ipi might be stuck\n"); #undef MAX_SPIN2 #undef MAX_SPIN1 #else while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; #endif /* DETECT_DEADLOCK */ /** XXX FIXME: return result */ return 0; } /* * Send APIC IPI 'vector' to 'target's via 'delivery_mode'. * * target contains a bitfield with a bit set for selected APICs. * vector is any valid SYSTEM INT vector * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO */ int selected_apic_ipi(u_int target, int vector, int delivery_mode) { int x; int status; u_long icr_hi; if (target & ~0x7fff) return -1; /* only 15 targets allowed */ for (status = 0, x = 0; x <= 14; ++x) if (target & (1 << x)) { /* write the destination field for the target AP */ icr_hi = lapic.icr_hi & ~APIC_ID_MASK; icr_hi |= (CPU_TO_ID(x) << 24); lapic.icr_hi = icr_hi; /* send the IPI */ if (apic_ipi(APIC_DEST_DESTFLD, vector, delivery_mode) == -1) status |= (1 << x); } return status; } #if defined(READY) /* * Send an IPI INTerrupt containing 'vector' to CPU 'target' * NOTE: target is a LOGICAL APIC ID */ int selected_proc_ipi(int target, int vector) { u_long icr_lo; u_long icr_hi; /* write the destination field for the target AP */ icr_hi = (lapic.icr_hi & ~APIC_ID_MASK) | (cpu_num_to_apic_id[target] << 24); lapic.icr_hi = icr_hi; /* write command */ icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) | APIC_DEST_DESTFLD | APIC_DELMODE_FIXED | vector; lapic.icr_lo = icr_lo; /* wait for pending status end */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; return 0; /** XXX FIXME: return result */ } #endif /* READY */ #endif /* APIC_IO */ /* * Timer code, in development... * - suggested by rgrimes@gndrsh.aac.dev.com */ /** XXX FIXME: temp hack till we can determin bus clock */ #ifndef BUS_CLOCK #define BUS_CLOCK 66000000 #define bus_clock() 66000000 #endif #if defined(READY) int acquire_apic_timer __P((void)); int release_apic_timer __P((void)); /* * Acquire the APIC timer for exclusive use. */ int acquire_apic_timer(void) { #if 1 return 0; #else /** XXX FIXME: make this really do something */ panic("APIC timer in use when attempting to aquire"); #endif } /* * Return the APIC timer. */ int release_apic_timer(void) { #if 1 return 0; #else /** XXX FIXME: make this really do something */ panic("APIC timer was already released"); #endif } #endif /* READY */ /* * Load a 'downcount time' in uSeconds. */ void set_apic_timer(int value) { u_long lvtt; long ticks_per_microsec; /* * Calculate divisor and count from value: * * timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128] * value == time in uS */ lapic.dcr_timer = APIC_TDCR_1; ticks_per_microsec = bus_clock() / 1000000; /* configure timer as one-shot */ lvtt = lapic.lvt_timer; lvtt &= ~(APIC_LVTT_VECTOR | APIC_LVTT_DS | APIC_LVTT_M | APIC_LVTT_TM); lvtt |= APIC_LVTT_M; /* no INT, one-shot */ lapic.lvt_timer = lvtt; /* */ lapic.icr_timer = value * ticks_per_microsec; } /* * Read remaining time in timer. */ int read_apic_timer(void) { #if 0 /** XXX FIXME: we need to return the actual remaining time, * for now we just return the remaining count. */ #else return lapic.ccr_timer; #endif } /* * Spin-style delay, set delay time in uS, spin till it drains. */ void u_sleep(int count) { set_apic_timer(count); while (read_apic_timer()) /* spin */ ; } Index: head/sys/i386/i386/mplock.s =================================================================== --- head/sys/i386/i386/mplock.s (revision 27516) +++ head/sys/i386/i386/mplock.s (revision 27517) @@ -1,249 +1,250 @@ /* * ---------------------------------------------------------------------------- * "THE BEER-WARE LICENSE" (Revision 42): * wrote this file. As long as you retain this notice you * can do whatever you want with this stuff. If we meet some day, and you think * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp * ---------------------------------------------------------------------------- * - * $Id: mplock.s,v 1.8 1997/07/15 00:09:53 smp Exp smp $ + * $Id: mplock.s,v 1.9 1997/07/18 19:45:41 smp Exp smp $ * * Functions for locking between CPUs in a SMP system. * * This is an "exclusive counting semaphore". This means that it can be * free (0xffffffff) or be owned by a CPU (0xXXYYYYYY where XX is CPU-id * and YYYYYY is the count). * * Contrary to most implementations around, this one is entirely atomic: * The attempt to seize/release the semaphore and the increment/decrement * is done in one atomic operation. This way we are safe from all kinds * of weird reentrancy situations. * */ #include "opt_ddb.h" #include "assym.s" /* system definitions */ #include /* x86 special registers */ #include /* miscellaneous asm macros */ -#include /** TEST_LOPRIO, TEST_CPUSTOP */ -#ifdef TEST_CPUSTOP -#include -#endif +#include /** TEST_LOPRIO */ #include +#include + + /* * claim LOW PRIO, ie. accept ALL INTerrupts */ #ifdef TEST_LOPRIO -#ifdef TEST_CPUSTOP +/* location of saved TPR on stack */ #define TPR_TARGET 20(%esp) -#else -#define TPR_TARGET lapic_tpr -#endif /** TEST_CPUSTOP */ +/* we assumme that the 'reserved bits' can be written with zeros */ #ifdef CHEAP_TPR -#define ACCEPT_INTS \ - movl $0, TPR_TARGET /* clear TPR */ -#else -#define ACCEPT_INTS \ - andl $~APIC_TPR_PRIO, TPR_TARGET /* clear TPR */ + +/* after 1st acquire of lock we attempt to grab all hardware INTs */ +#define GRAB_HWI \ + movl $ALLHWI_LEVEL, TPR_TARGET /* task prio to 'all HWI' */ + +/* after last release of lock give up LOW PRIO (ie, arbitrate INTerrupts) */ +#define ARB_HWI \ + movl $LOPRIO_LEVEL, lapic_tpr /* task prio to 'arbitrate' */ + +#else /** CHEAP_TPR */ + +#define GRAB_HWI \ + andl $~APIC_TPR_PRIO, TPR_TARGET /* task prio to 'all HWI' */ + +#define ARB_HWI \ + movl lapic_tpr, %eax ; /* TPR */ \ + andl $~APIC_TPR_PRIO, %eax ; /* clear TPR field */ \ + orl $LOPRIO_LEVEL, %eax ; /* prio to arbitrate */ \ + movl %eax, lapic_tpr ; /* set it */ \ + movl (%edx), %eax /* reload %eax with lock */ + #endif /** CHEAP_TPR */ -#else +#else /** TEST_LOPRIO */ -#define ACCEPT_INTS +#define GRAB_HWI /* nop */ +#define ARB_HWI /* nop */ #endif /** TEST_LOPRIO */ + .text /*********************************************************************** * void MPgetlock(unsigned int *lock) * ---------------------------------- * Destroys %eax, %ecx and %edx. */ NON_GPROF_ENTRY(MPgetlock) 1: movl 4(%esp), %edx /* Get the address of the lock */ movl (%edx), %eax /* Try to see if we have it already */ andl $COUNT_FIELD, %eax /* - get count */ movl _cpu_lockid, %ecx /* - get pre-shifted logical cpu id */ orl %ecx, %eax /* - combine them */ movl %eax, %ecx incl %ecx /* - new count is one more */ lock cmpxchg %ecx, (%edx) /* - try it atomically */ jne 2f /* - miss */ ret 2: movl $FREE_LOCK, %eax /* Assume it's free */ movl _cpu_lockid, %ecx /* - get pre-shifted logical cpu id */ incl %ecx /* - new count is one */ lock cmpxchg %ecx, (%edx) /* - try it atomically */ jne 3f /* ...do not collect $200 */ - ACCEPT_INTS /* 1st acquire, accept INTs */ + GRAB_HWI /* 1st acquire, grab hw INTs */ ret 3: cmpl $FREE_LOCK, (%edx) /* Wait for it to become free */ jne 3b jmp 2b /* XXX 1b ? */ /*********************************************************************** * int MPtrylock(unsigned int *lock) * --------------------------------- * Destroys %eax, %ecx and %edx. * Returns 1 if lock was successfull */ NON_GPROF_ENTRY(MPtrylock) 1: movl 4(%esp), %edx /* Get the address of the lock */ movl (%edx), %eax /* Try to see if we have it already */ andl $COUNT_FIELD, %eax /* - get count */ movl _cpu_lockid, %ecx /* - get pre-shifted logical cpu id */ orl %ecx, %eax /* - combine them */ movl %eax, %ecx incl %ecx /* - new count is one more */ lock cmpxchg %ecx, (%edx) /* - try it atomically */ jne 2f /* - miss */ movl $1, %eax ret 2: movl $FREE_LOCK, %eax /* Assume it's free */ movl _cpu_lockid, %ecx /* - get pre-shifted logical cpu id */ incl %ecx /* - new count is one */ lock cmpxchg %ecx, (%edx) /* - try it atomically */ jne 3f /* ...do not collect $200 */ - ACCEPT_INTS /* 1st acquire, accept INTs */ + GRAB_HWI /* 1st acquire, grab hw INTs */ movl $1, %eax ret 3: movl $0, %eax ret /*********************************************************************** * void MPrellock(unsigned int *lock) * ---------------------------------- * Destroys %eax, %ecx and %edx. */ NON_GPROF_ENTRY(MPrellock) 1: movl 4(%esp), %edx /* Get the address of the lock */ movl (%edx), %eax /* - get the value */ movl %eax,%ecx decl %ecx /* - new count is one less */ testl $COUNT_FIELD, %ecx /* - Unless it's zero... */ jnz 2f -#if defined(TEST_LOPRIO) - /* last release, give up LOW PRIO (ie, arbitrate INTerrupts) */ -#ifdef CHEAP_TPR - movl $LOPRIO_LEVEL, lapic_tpr /* task prio to 'arbitrate' */ -#else - movl lapic_tpr, %eax /* Task Priority Register */ - andl $~APIC_TPR_PRIO, %eax /* clear task priority field */ - orl $LOPRIO_LEVEL, %eax /* set task priority to 'arbitrate' */ - movl %eax, lapic_tpr /* set it */ - movl (%edx), %eax /* - get the value AGAIN */ -#endif /* CHEAP_TPR */ -#endif /** TEST_LOPRIO */ + ARB_HWI /* last release, arbitrate hw INTs */ movl $FREE_LOCK, %ecx /* - In which case we release it */ 2: lock cmpxchg %ecx, (%edx) /* - try it atomically */ jne 1b /* ...do not collect $200 */ ret /*********************************************************************** * void get_mplock() * ----------------- * All registers preserved * * Stack (after call to _MPgetlock): * * &mp_lock 4(%esp) * edx 8(%esp) * ecx 12(%esp) * EFLAGS 16(%esp) * local APIC TPR 20(%esp) * eax 24(%esp) */ NON_GPROF_ENTRY(get_mplock) pushl %eax -#ifdef TEST_CPUSTOP + /* block all HW INTs via Task Priority Register */ #ifdef CHEAP_TPR pushl lapic_tpr /* save current TPR */ pushfl /* save current EFLAGS */ btl $9, (%esp) /* test EI bit */ jc 1f /* INTs currently enabled */ - movl $TPR_BLOCK_HWI, lapic_tpr /* set it */ + movl $TPR_BLOCK_HWI, lapic_tpr #else movl lapic_tpr, %eax /* get current TPR */ pushl %eax /* save current TPR */ pushfl /* save current EFLAGS */ btl $9, (%esp) /* test EI bit */ jc 1f /* INTs currently enabled */ andl $~APIC_TPR_PRIO, %eax /* clear task priority field */ - orl $TPR_BLOCK_HWI, %eax /* only allow IPIs - movl %eax, lapic_tpr /* set it */ -#endif /* CHEAP_TPR */ - sti /* allow IPI (and only IPI) INTS */ + orl $TPR_BLOCK_HWI, %eax /* only allow IPIs */ + movl %eax, lapic_tpr +#endif /** CHEAP_TPR */ + sti /* allow (IPI and only IPI) INTs */ 1: -#endif /* TEST_CPUSTOP */ pushl %ecx pushl %edx pushl $_mp_lock call _MPgetlock add $4, %esp popl %edx popl %ecx -#ifdef TEST_CPUSTOP popfl /* restore original EFLAGS */ popl lapic_tpr /* restore TPR */ -#endif /* TEST_CPUSTOP */ - popl %eax /* restore scratch */ ret /*********************************************************************** * void try_mplock() * ----------------- * reg %eax == 1 if success */ NON_GPROF_ENTRY(try_mplock) pushl %ecx pushl %edx pushl $_mp_lock call _MPtrylock add $4, %esp popl %edx popl %ecx ret /*********************************************************************** * void rel_mplock() * ----------------- * All registers preserved */ NON_GPROF_ENTRY(rel_mplock) pushl %eax pushl %ecx pushl %edx pushl $_mp_lock call _MPrellock add $4, %esp popl %edx popl %ecx popl %eax ret .data .globl _mp_lock - .align 2 /* mp_lock SHALL be aligned on i386 */ + .align 4 /* mp_lock aligned on int boundary */ _mp_lock: .long 0 Index: head/sys/i386/i386/mptable.c =================================================================== --- head/sys/i386/i386/mptable.c (revision 27516) +++ head/sys/i386/i386/mptable.c (revision 27517) @@ -1,1834 +1,1803 @@ /* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: mp_machdep.c,v 1.28 1997/07/17 19:44:56 dyson Exp $ + * $Id: mp_machdep.c,v 1.16 1997/07/18 19:45:41 smp Exp smp $ */ #include "opt_smp.h" #include /* for KERNBASE */ #include #include #include #include #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include #include #include #include #include #include #include -#include /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP _TEST1 */ +#include /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ #include #include #include /* cngetc() */ #if defined(APIC_IO) #include /* setidt() */ #include /* IPIs */ #include /* IPIs */ #endif /* APIC_IO */ #define WARMBOOT_TARGET 0 #define WARMBOOT_OFF (KERNBASE + 0x0467) #define WARMBOOT_SEG (KERNBASE + 0x0469) #define BIOS_BASE (0xf0000) #define BIOS_SIZE (0x10000) #define BIOS_COUNT (BIOS_SIZE/4) #define CMOS_REG (0x70) #define CMOS_DATA (0x71) #define BIOS_RESET (0x0f) #define BIOS_WARM (0x0a) #define PROCENTRY_FLAG_EN 0x01 #define PROCENTRY_FLAG_BP 0x02 #define IOAPICENTRY_FLAG_EN 0x01 /* MP Floating Pointer Structure */ typedef struct MPFPS { char signature[4]; void *pap; u_char length; u_char spec_rev; u_char checksum; u_char mpfb1; u_char mpfb2; u_char mpfb3; u_char mpfb4; u_char mpfb5; } *mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { char signature[4]; u_short base_table_length; u_char spec_rev; u_char checksum; u_char oem_id[8]; u_char product_id[12]; void *oem_table_pointer; u_short oem_table_size; u_short entry_count; void *apic_address; u_short extended_table_length; u_char extended_table_checksum; u_char reserved; } *mpcth_t; typedef struct PROCENTRY { u_char type; u_char apic_id; u_char apic_version; u_char cpu_flags; u_long cpu_signature; u_long feature_flags; u_long reserved1; u_long reserved2; } *proc_entry_ptr; typedef struct BUSENTRY { u_char type; u_char bus_id; char bus_type[6]; } *bus_entry_ptr; typedef struct IOAPICENTRY { u_char type; u_char apic_id; u_char apic_version; u_char apic_flags; void *apic_address; } *io_apic_entry_ptr; typedef struct INTENTRY { u_char type; u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } *int_entry_ptr; /* descriptions of MP basetable entries */ typedef struct BASETABLE_ENTRY { u_char type; u_char length; char name[16]; } basetable_entry; /* * this code MUST be enabled here and in mpboot.s. * it follows the very early stages of AP boot by placing values in CMOS ram. * it NORMALLY will never be needed and thus the primitive method for enabling. * #define CHECK_POINTS */ #if defined(CHECK_POINTS) #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) #define CHECK_INIT(D); \ CHECK_WRITE(0x34, (D)); \ CHECK_WRITE(0x35, (D)); \ CHECK_WRITE(0x36, (D)); \ CHECK_WRITE(0x37, (D)); \ CHECK_WRITE(0x38, (D)); \ CHECK_WRITE(0x39, (D)); #define CHECK_PRINT(S); \ printf("%s: %d, %d, %d, %d, %d, %d\n", \ (S), \ CHECK_READ(0x34), \ CHECK_READ(0x35), \ CHECK_READ(0x36), \ CHECK_READ(0x37), \ CHECK_READ(0x38), \ CHECK_READ(0x39)); #else /* CHECK_POINTS */ #define CHECK_INIT(D) #define CHECK_PRINT(S) #endif /* CHECK_POINTS */ /* * Values to send to the POST hardware. */ #define MP_BOOTADDRESS_POST 0x10 #define MP_PROBE_POST 0x11 #define MP_START_POST 0x12 #define MP_ANNOUNCE_POST 0x13 #define MPTABLE_PASS1_POST 0x14 #define MPTABLE_PASS2_POST 0x15 #define MP_ENABLE_POST 0x16 #define START_ALL_APS_POST 0x17 #define INSTALL_AP_TRAMP_POST 0x18 #define START_AP_POST 0x19 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ int current_postcode; /** XXX FIXME: what system files declare these??? */ extern struct region_descriptor r_gdt, r_idt; int mp_ncpus; /* # of CPUs, including BSP */ int mp_naps; /* # of Applications processors */ int mp_nbusses; /* # of busses */ int mp_napics; /* # of IO APICs */ int boot_cpu_id; /* designated BSP */ vm_offset_t cpu_apic_address; vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ u_int32_t cpu_apic_versions[NCPU]; u_int32_t io_apic_versions[NAPIC]; /* * APIC ID logical/physical mapping structures. * We oversize these to simplify boot-time config. */ int cpu_num_to_apic_id[NAPICID]; int io_num_to_apic_id[NAPICID]; int apic_id_to_logical[NAPICID]; /* Bitmap of all available CPUs */ u_int all_cpus; /* Boot of AP uses this PTD */ u_int *bootPTD; /* Hotwire a 0->4MB V==P mapping */ extern pt_entry_t KPTphys; /* Virtual address of per-cpu common_tss */ extern struct i386tss common_tss; /* * Local data and functions. */ static int mp_capable; static u_int boot_address; static u_int base_memory; static int picmode; /* 0: virtual wire mode, 1: PIC mode */ static mpfps_t mpfps; static int search_for_sig(u_int32_t target, int count); static void mp_enable(u_int boot_addr); static int mptable_pass1(void); static int mptable_pass2(void); static void default_mp_table(int type); static int start_all_aps(u_int boot_addr); static void install_ap_tramp(u_int boot_addr); static int start_ap(int logicalCpu, u_int boot_addr); /* * Calculate usable address in base memory for AP trampoline code. */ u_int mp_bootaddress(u_int basemem) { POSTCODE(MP_BOOTADDRESS_POST); base_memory = basemem * 1024; /* convert to bytes */ boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ if ((base_memory - boot_address) < bootMP_size) boot_address -= 4096; /* not enough, lower by 4k */ return boot_address; } /* * Look for an Intel MP spec table (ie, SMP capable hardware). */ int mp_probe(void) { int x; u_long segment; u_int32_t target; POSTCODE(MP_PROBE_POST); /* see if EBDA exists */ if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { /* search first 1K of EBDA */ target = (u_int32_t) (segment << 4); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } else { /* last 1K of base memory, effective 'top of base' passed in */ target = (u_int32_t) (base_memory - 0x400); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } /* search the BIOS */ target = (u_int32_t) BIOS_BASE; if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) goto found; /* nothing found */ mpfps = (mpfps_t)0; mp_capable = 0; return 0; found: /* calculate needed resources */ mpfps = (mpfps_t)x; if (mptable_pass1()) panic("you must reconfigure your kernel"); /* flag fact that we are running multiple processors */ mp_capable = 1; return 1; } /* * Startup the SMP processors. */ void mp_start(void) { POSTCODE(MP_START_POST); /* look for MP capable motherboard */ if (mp_capable) mp_enable(boot_address); else panic("MP hardware not found!"); } /* * Print various information about the SMP system hardware and setup. */ void mp_announce(void) { int x; POSTCODE(MP_ANNOUNCE_POST); printf("FreeBSD/SMP: Multiprocessor motherboard\n"); printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); printf(", version: 0x%08x", cpu_apic_versions[0]); printf(", at 0x%08x\n", cpu_apic_address); for (x = 1; x <= mp_naps; ++x) { printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); printf(", version: 0x%08x", cpu_apic_versions[x]); printf(", at 0x%08x\n", cpu_apic_address); } #if defined(APIC_IO) for (x = 0; x < mp_napics; ++x) { printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); printf(", version: 0x%08x", io_apic_versions[x]); printf(", at 0x%08x\n", io_apic_address[x]); } #else printf(" Warning: APIC I/O disabled\n"); #endif /* APIC_IO */ } /* * AP cpu's call this to sync up protected mode. */ void init_secondary(void) { int gsel_tss, slot; r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; r_gdt.rd_base = (int) gdt; lgdt(&r_gdt); /* does magic intra-segment return */ lidt(&r_idt); lldt(_default_ldt); slot = NGDT + cpuid; gsel_tss = GSEL(slot, SEL_KPL); gdt[slot].sd.sd_type = SDT_SYS386TSS; common_tss.tss_esp0 = 0; /* not used until after switch */ common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); common_tss.tss_ioopt = (sizeof common_tss) << 16; ltr(gsel_tss); load_cr0(0x8005003b); /* XXX! */ PTD[0] = 0; pmap_set_opt((unsigned *)PTD); invltlb(); } #if defined(APIC_IO) /* * Final configuration of the BSP's local APIC: * - disable 'pic mode'. * - disable 'virtual wire mode'. * - enable NMI. */ void bsp_apic_configure(void) { u_char byte; u_int32_t temp; /* leave 'pic mode' if necessary */ if (picmode) { outb(0x22, 0x70); /* select IMCR */ byte = inb(0x23); /* current contents */ byte |= 0x01; /* mask external INTR */ outb(0x23, byte); /* disconnect 8259s/NMI */ } /* mask lint0 (the 8259 'virtual wire' connection) */ temp = lapic.lvt_lint0; temp |= APIC_LVT_M; /* set the mask */ lapic.lvt_lint0 = temp; /* setup lint1 to handle NMI */ temp = lapic.lvt_lint1; temp &= ~APIC_LVT_M; /* clear the mask */ lapic.lvt_lint1 = temp; if (bootverbose) apic_dump(); } #endif /* APIC_IO */ /******************************************************************* * local functions and data */ /* * start the SMP system */ static void mp_enable(u_int boot_addr) { int x; #if defined(APIC_IO) int apic; u_int ux; #endif /* APIC_IO */ POSTCODE(MP_ENABLE_POST); /* turn on 4MB of V == P addressing so we can get to MP table */ *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); invltlb(); /* examine the MP table for needed info, uses physical addresses */ x = mptable_pass2(); *(int *)PTD = 0; invltlb(); /* can't process default configs till the CPU APIC is pmapped */ if (x) default_mp_table(x); #if defined(APIC_IO) /* fill the LOGICAL io_apic_versions table */ for (apic = 0; apic < mp_napics; ++apic) { ux = io_apic_read(apic, IOAPIC_VER); io_apic_versions[apic] = ux; } /* program each IO APIC in the system */ for (apic = 0; apic < mp_napics; ++apic) if (io_apic_setup(apic) < 0) panic("IO APIC setup failure"); /* install a 'Spurious INTerrupt' vector */ setidt(XSPURIOUSINT_OFFSET, Xspuriousint, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); /* install an inter-CPU IPI for TLB invalidation */ setidt(XINVLTLB_OFFSET, Xinvltlb, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#if defined(TEST_CPUSTOP) /* install an inter-CPU IPI for CPU stop/restart */ setidt(XCPUSTOP_OFFSET, Xcpustop, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#endif /** TEST_CPUSTOP */ #if defined(TEST_TEST1) - /* install a 'Spurious INTerrupt' vector */ + /* install a "fake hardware INTerrupt" vector */ setidt(XTEST1_OFFSET, Xtest1, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /** TEST_TEST1 */ #endif /* APIC_IO */ /* start each Application Processor */ start_all_aps(boot_addr); /* * The init process might be started on a different CPU now, * and the boot CPU might not call prepare_usermode to get * cr0 correctly configured. Thus we initialize cr0 here. */ load_cr0(rcr0() | CR0_WP | CR0_AM); } /* * look for the MP spec signature */ /* string defined by the Intel MP Spec as identifying the MP table */ #define MP_SIG 0x5f504d5f /* _MP_ */ #define NEXT(X) ((X) += 4) static int search_for_sig(u_int32_t target, int count) { int x; u_int32_t *addr = (u_int32_t *) (KERNBASE + target); for (x = 0; x < count; NEXT(x)) if (addr[x] == MP_SIG) /* make array index a byte index */ return (target + (x * sizeof(u_int32_t))); return -1; } static basetable_entry basetable_entry_types[] = { {0, 20, "Processor"}, {1, 8, "Bus"}, {2, 8, "I/O APIC"}, {3, 8, "I/O INT"}, {4, 8, "Local INT"} }; typedef struct BUSDATA { u_char bus_id; enum busTypes bus_type; } bus_datum; typedef struct INTDATA { u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } io_int, local_int; typedef struct BUSTYPENAME { u_char type; char name[7]; } bus_type_name; static bus_type_name bus_type_table[] = { {CBUS, "CBUS"}, {CBUSII, "CBUSII"}, {EISA, "EISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {ISA, "ISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {PCI, "PCI"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {XPRESS, "XPRESS"}, {UNKNOWN_BUSTYPE, "---"} }; /* from MP spec v1.4, table 5-1 */ static int default_data[7][5] = { /* nbus, id0, type0, id1, type1 */ {1, 0, ISA, 255, 255}, {1, 0, EISA, 255, 255}, {1, 0, EISA, 255, 255}, {0, 255, 255, 255, 255},/* MCA not supported */ {2, 0, ISA, 1, PCI}, {2, 0, EISA, 1, PCI}, {0, 255, 255, 255, 255} /* MCA not supported */ }; /* the bus data */ bus_datum bus_data[NBUS]; /* the IO INT data, one entry per possible APIC INTerrupt */ io_int io_apic_ints[NINTR]; static int nintrs; static void fix_mp_table __P((void)); static int processor_entry __P((proc_entry_ptr entry, int cpu)); static int bus_entry __P((bus_entry_ptr entry, int bus)); static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); static int int_entry __P((int_entry_ptr entry, int intr)); static int lookup_bus_type __P((char *name)); /* * 1st pass on motherboard's Intel MP specification table. * * initializes: * mp_ncpus = 1 * * determines: * cpu_apic_address (common to all CPUs) * io_apic_address[N] * mp_naps * mp_nbusses * mp_napics * nintrs */ static int mptable_pass1(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int mustpanic; POSTCODE(MPTABLE_PASS1_POST); mustpanic = 0; /* clear various tables */ for (x = 0; x < NAPICID; ++x) { io_apic_address[x] = ~0; /* IO APIC address table */ } /* init everything to empty */ mp_naps = 0; mp_nbusses = 0; mp_napics = 0; nintrs = 0; /* check for use of 'default' configuration */ if (mpfps->mpfb1 != 0) { /* use default addresses */ cpu_apic_address = DEFAULT_APIC_BASE; io_apic_address[0] = DEFAULT_IO_APIC_BASE; /* fill in with defaults */ mp_naps = 2; /* includes BSP */ mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; #if defined(APIC_IO) mp_napics = 1; nintrs = 16; #endif /* APIC_IO */ } else { if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); cpu_apic_address = (vm_offset_t) cth->apic_address; /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; while (count--) { switch (type = *(u_char *) position) { case 0: /* processor_entry */ if (((proc_entry_ptr)position)->cpu_flags & PROCENTRY_FLAG_EN) ++mp_naps; break; case 1: /* bus_entry */ ++mp_nbusses; break; case 2: /* io_apic_entry */ if (((io_apic_entry_ptr)position)->apic_flags & IOAPICENTRY_FLAG_EN) io_apic_address[mp_napics++] = (vm_offset_t)((io_apic_entry_ptr) position)->apic_address; break; case 3: /* int_entry */ ++nintrs; break; case 4: /* int_entry */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char*)position += basetable_entry_types[type].length; } } /* qualify the numbers */ if (mp_naps > NCPU) printf("Warning: only using %d of %d available CPUs!\n", NCPU, mp_naps); #if 0 /** XXX we consider this legal now (but should we?) */ mustpanic = 1; #endif if (mp_nbusses > NBUS) { printf("found %d busses, increase NBUS\n", mp_nbusses); mustpanic = 1; } if (mp_napics > NAPIC) { printf("found %d apics, increase NAPIC\n", mp_napics); mustpanic = 1; } if (nintrs > NINTR) { printf("found %d intrs, increase NINTR\n", nintrs); mustpanic = 1; } /* * Count the BSP. * This is also used as a counter while starting the APs. */ mp_ncpus = 1; --mp_naps; /* subtract the BSP */ return mustpanic; } /* * 2nd pass on motherboard's Intel MP specification table. * * sets: * boot_cpu_id * ID_TO_IO(N), phy APIC ID to log CPU/IO table * CPU_TO_ID(N), logical CPU to APIC ID table * IO_TO_ID(N), logical IO to APIC ID table * bus_data[N] * io_apic_ints[N] */ static int mptable_pass2(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int apic, bus, cpu, intr; POSTCODE(MPTABLE_PASS2_POST); /* clear various tables */ for (x = 0; x < NAPICID; ++x) { ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ } /* clear bus data table */ for (x = 0; x < NBUS; ++x) bus_data[x].bus_id = 0xff; /* clear IO APIC INT table */ for (x = 0; x < NINTR; ++x) io_apic_ints[x].int_type = 0xff; /* setup the cpu/apic mapping arrays */ boot_cpu_id = -1; /* record whether PIC or virtual-wire mode */ picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; /* check for use of 'default' configuration */ #if defined(TEST_DEFAULT_CONFIG) return TEST_DEFAULT_CONFIG; #else if (mpfps->mpfb1 != 0) return mpfps->mpfb1; /* return default configuration type */ #endif /* TEST_DEFAULT_CONFIG */ if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; apic = bus = intr = 0; cpu = 1; /* pre-count the BSP */ while (count--) { switch (type = *(u_char *) position) { case 0: if (processor_entry(position, cpu)) ++cpu; break; case 1: if (bus_entry(position, bus)) ++bus; break; case 2: if (io_apic_entry(position, apic)) ++apic; break; case 3: if (int_entry(position, intr)) ++intr; break; case 4: /* int_entry(position); */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char *) position += basetable_entry_types[type].length; } if (boot_cpu_id == -1) panic("NO BSP found!"); /* post scan cleanup */ fix_mp_table(); /* report fact that its NOT a default configuration */ return 0; } /* * parse an Intel MP specification table */ static void fix_mp_table(void) { int x; int id; int bus_0; int bus_pci; int num_pci_bus; /* * Fix mis-numbering of the PCI bus and its INT entries if the BIOS * did it wrong. The MP spec says that when more than 1 PCI bus * exists the BIOS must begin with bus entries for the PCI bus and use * actual PCI bus numbering. This implies that when only 1 PCI bus * exists the BIOS can choose to ignore this ordering, and indeed many * MP motherboards do ignore it. This causes a problem when the PCI * sub-system makes requests of the MP sub-system based on PCI bus * numbers. So here we look for the situation and renumber the * busses and associated INTs in an effort to "make it right". */ /* find bus 0, PCI bus, count the number of PCI busses */ for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_id == 0) { bus_0 = x; } if (bus_data[x].bus_type == PCI) { ++num_pci_bus; bus_pci = x; } } /* * bus_0 == slot of bus with ID of 0 * bus_pci == slot of last PCI bus encountered */ /* check the 1 PCI bus case for sanity */ if (num_pci_bus == 1) { /* if it is number 0 all is well */ if (bus_data[bus_pci].bus_id == 0) return; /* mis-numbered, swap with whichever bus uses slot 0 */ /* swap the bus entry types */ bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; bus_data[bus_0].bus_type = PCI; /* swap each relavant INTerrupt entry */ id = bus_data[bus_pci].bus_id; for (x = 0; x < nintrs; ++x) { if (io_apic_ints[x].src_bus_id == id) { io_apic_ints[x].src_bus_id = 0; } else if (io_apic_ints[x].src_bus_id == 0) { io_apic_ints[x].src_bus_id = id; } } } /* sanity check if more than 1 PCI bus */ else if (num_pci_bus > 1) { for (x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_type != PCI) continue; if (bus_data[x].bus_id >= num_pci_bus) panic("bad PCI bus numbering"); } } } static int processor_entry(proc_entry_ptr entry, int cpu) { /* check for usability */ if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) return 0; /* check for BSP flag */ if (entry->cpu_flags & PROCENTRY_FLAG_BP) { boot_cpu_id = entry->apic_id; CPU_TO_ID(0) = entry->apic_id; ID_TO_CPU(entry->apic_id) = 0; return 0; /* its already been counted */ } /* add another AP to list, if less than max number of CPUs */ else { CPU_TO_ID(cpu) = entry->apic_id; ID_TO_CPU(entry->apic_id) = cpu; return 1; } } static int bus_entry(bus_entry_ptr entry, int bus) { int x; char c, name[8]; /* encode the name into an index */ for (x = 0; x < 6; ++x) { if ((c = entry->bus_type[x]) == ' ') break; name[x] = c; } name[x] = '\0'; if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) panic("unknown bus type: '%s'", name); bus_data[bus].bus_id = entry->bus_id; bus_data[bus].bus_type = x; return 1; } static int io_apic_entry(io_apic_entry_ptr entry, int apic) { if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) return 0; IO_TO_ID(apic) = entry->apic_id; ID_TO_IO(entry->apic_id) = apic; return 1; } static int lookup_bus_type(char *name) { int x; for (x = 0; x < MAX_BUSTYPE; ++x) if (strcmp(bus_type_table[x].name, name) == 0) return bus_type_table[x].type; return UNKNOWN_BUSTYPE; } static int int_entry(int_entry_ptr entry, int intr) { io_apic_ints[intr].int_type = entry->int_type; io_apic_ints[intr].int_flags = entry->int_flags; io_apic_ints[intr].src_bus_id = entry->src_bus_id; io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; return 1; } static int apic_int_is_bus_type(int intr, int bus_type) { int bus; for (bus = 0; bus < mp_nbusses; ++bus) if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) && ((int) bus_data[bus].bus_type == bus_type)) return 1; return 0; } /* * Given a traditional ISA INT mask, return an APIC mask. */ u_int isa_apic_mask(u_int isa_mask) { int isa_irq; int apic_pin; #if defined(SKIP_IRQ15_REDIRECT) if (isa_mask == (1 << 15)) { printf("skipping ISA IRQ15 redirect\n"); return isa_mask; } #endif /* SKIP_IRQ15_REDIRECT */ isa_irq = ffs(isa_mask); /* find its bit position */ if (isa_irq == 0) /* doesn't exist */ return 0; --isa_irq; /* make it zero based */ apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ if (apic_pin == -1) return 0; return (1 << apic_pin); /* convert pin# to a mask */ } /* * Determine which APIC pin an ISA/EISA INT is attached to. */ #define INTTYPE(I) (io_apic_ints[(I)].int_type) #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) int isa_apic_pin(int isa_irq) { int intr; #if defined(SMP_TIMER_NC) if (isa_irq == 0) return -1; #endif /* SMP_TIMER_NC */ for (intr = 0; intr < nintrs; ++intr) { /* check each record */ if (INTTYPE(intr) == 0) { /* standard INT */ if (SRCBUSIRQ(intr) == isa_irq) { if (apic_int_is_bus_type(intr, ISA) || apic_int_is_bus_type(intr, EISA)) return INTPIN(intr); /* found */ } } } return -1; /* NOT found */ } #undef SRCBUSIRQ /* * Determine which APIC pin a PCI INT is attached to. */ #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) int pci_apic_pin(int pciBus, int pciDevice, int pciInt) { int intr; --pciInt; /* zero based */ for (intr = 0; intr < nintrs; ++intr) /* check each record */ if ((INTTYPE(intr) == 0) /* standard INT */ && (SRCBUSID(intr) == pciBus) && (SRCBUSDEVICE(intr) == pciDevice) && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ if (apic_int_is_bus_type(intr, PCI)) return INTPIN(intr); /* exact match */ return -1; /* NOT found */ } #undef SRCBUSLINE #undef SRCBUSDEVICE #undef SRCBUSID #undef INTPIN #undef INTTYPE /* * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. * * XXX FIXME: * Exactly what this means is unclear at this point. It is a solution * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard * could route any of the ISA INTs to upper (>15) IRQ values. But most would * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an * option. */ int undirect_isa_irq(int rirq) { #if defined(READY) printf("Freeing redirected ISA irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); return 0; #endif /* READY */ } /* * Reprogram the MB chipset to NOT redirect a PCI INTerrupt */ int undirect_pci_irq(int rirq) { #if defined(READY) if (bootverbose) printf("Freeing redirected PCI irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else if (bootverbose) printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); return 0; #endif /* READY */ } /* * given a bus ID, return: * the bus type if found * -1 if NOT found */ int apic_bus_type(int id) { int x; for (x = 0; x < mp_nbusses; ++x) if (bus_data[x].bus_id == id) return bus_data[x].bus_type; return -1; } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus ID if found * -1 if NOT found */ int apic_src_bus_id(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_id); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus IRQ if found * -1 if NOT found */ int apic_src_bus_irq(int apic, int pin) { int x; for (x = 0; x < nintrs; x++) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_irq); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated INTerrupt type if found * -1 if NOT found */ int apic_int_type(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_type); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated trigger mode if found * -1 if NOT found */ int apic_trigger(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return ((io_apic_ints[x].int_flags >> 2) & 0x03); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated 'active' level if found * -1 if NOT found */ int apic_polarity(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_flags & 0x03); return -1; /* NOT found */ } /* * set data according to MP defaults * FIXME: probably not complete yet... */ static void default_mp_table(int type) { int ap_cpu_id; #if defined(APIC_IO) u_int32_t ux; int io_apic_id; int pin; #endif /* APIC_IO */ #if 0 printf(" MP default config type: %d\n", type); switch (type) { case 1: printf(" bus: ISA, APIC: 82489DX\n"); break; case 2: printf(" bus: EISA, APIC: 82489DX\n"); break; case 3: printf(" bus: EISA, APIC: 82489DX\n"); break; case 4: printf(" bus: MCA, APIC: 82489DX\n"); break; case 5: printf(" bus: ISA+PCI, APIC: Integrated\n"); break; case 6: printf(" bus: EISA+PCI, APIC: Integrated\n"); break; case 7: printf(" bus: MCA+PCI, APIC: Integrated\n"); break; default: printf(" future type\n"); break; /* NOTREACHED */ } #endif /* 0 */ boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; /* BSP */ CPU_TO_ID(0) = boot_cpu_id; ID_TO_CPU(boot_cpu_id) = 0; /* one and only AP */ CPU_TO_ID(1) = ap_cpu_id; ID_TO_CPU(ap_cpu_id) = 1; #if defined(APIC_IO) /* one and only IO APIC */ io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; /* * sanity check, refer to MP spec section 3.6.6, last paragraph * necessary as some hardware isn't properly setting up the IO APIC */ #if defined(REALLY_ANAL_IOAPICID_VALUE) if (io_apic_id != 2) { #else if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { #endif /* REALLY_ANAL_IOAPICID_VALUE */ ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ ux &= ~APIC_ID_MASK; /* clear the ID field */ ux |= 0x02000000; /* set it to '2' */ io_apic_write(0, IOAPIC_ID, ux); /* write new value */ ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ if ((ux & APIC_ID_MASK) != 0x02000000) panic("can't control IO APIC ID, reg: 0x%08x", ux); io_apic_id = 2; } IO_TO_ID(0) = io_apic_id; ID_TO_IO(io_apic_id) = 0; #endif /* APIC_IO */ /* fill out bus entries */ switch (type) { case 1: case 2: case 3: case 5: case 6: bus_data[0].bus_id = default_data[type - 1][1]; bus_data[0].bus_type = default_data[type - 1][2]; bus_data[1].bus_id = default_data[type - 1][3]; bus_data[1].bus_type = default_data[type - 1][4]; break; /* case 4: case 7: MCA NOT supported */ default: /* illegal/reserved */ panic("BAD default MP config: %d", type); /* NOTREACHED */ } #if defined(APIC_IO) /* general cases from MP v1.4, table 5-2 */ for (pin = 0; pin < 16; ++pin) { io_apic_ints[pin].int_type = 0; io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ io_apic_ints[pin].src_bus_id = 0; io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ io_apic_ints[pin].dst_apic_id = io_apic_id; io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ } /* special cases from MP v1.4, table 5-2 */ if (type == 2) { io_apic_ints[2].int_type = 0xff; /* N/C */ io_apic_ints[13].int_type = 0xff; /* N/C */ #if !defined(APIC_MIXED_MODE) /** FIXME: ??? */ panic("sorry, can't support type 2 default yet"); #endif /* APIC_MIXED_MODE */ } else io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ if (type == 7) io_apic_ints[0].int_type = 0xff; /* N/C */ else io_apic_ints[0].int_type = 3; /* vectored 8259 */ #endif /* APIC_IO */ } /* * start each AP in our list */ static int start_all_aps(u_int boot_addr) { int x, i; u_char mpbiosreason; u_long mpbioswarmvec; pd_entry_t newptd; pt_entry_t newpt; int *newpp; POSTCODE(START_ALL_APS_POST); /** * NOTE: this needs further thought: * where does it get released? * should it be set to empy? * * get the initial mp_lock with a count of 1 for the BSP */ mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ /* initialize BSP's local APIC */ apic_initialize(); /* install the AP 1st level boot code */ install_ap_tramp(boot_addr); /* save the current value of the warm-start vector */ mpbioswarmvec = *((u_long *) WARMBOOT_OFF); outb(CMOS_REG, BIOS_RESET); mpbiosreason = inb(CMOS_DATA); /* record BSP in CPU map */ all_cpus = 1; /* start each AP */ for (x = 1; x <= mp_naps; ++x) { /* HACK HACK HACK !!! */ /* alloc new page table directory */ newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* clone currently active one (ie: IdlePTD) */ bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ /* set up 0 -> 4MB P==V mapping for AP boot */ newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); /* store PTD for this AP */ bootPTD = (pd_entry_t)vtophys(newptd); /* alloc new page table page */ newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* set the new PTD's private page to point there */ newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); /* install self referential entry */ newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); /* get a new private data page */ newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); /* wire it into the private page table page */ newpt[0] = PG_V | PG_RW | vtophys(newpp); /* wire the ptp into itself for access */ newpt[1] = PG_V | PG_RW | vtophys(newpt); /* and the local apic */ newpt[2] = SMP_prvpt[2]; /* and the IO apic mapping[s] */ for (i = 16; i < 32; i++) newpt[i] = SMP_prvpt[i]; /* prime data page for it to use */ newpp[0] = x; /* cpuid */ newpp[1] = 0; /* curproc */ newpp[2] = 0; /* curpcb */ newpp[3] = 0; /* npxproc */ newpp[4] = 0; /* runtime.tv_sec */ newpp[5] = 0; /* runtime.tv_usec */ newpp[6] = x << 24; /* cpu_lockid */ /* XXX NOTE: ABANDON bootPTD for now!!!! */ /* END REVOLTING HACKERY */ /* setup a vector to our boot code */ *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ /* attempt to start the Application Processor */ CHECK_INIT(99); /* setup checkpoints */ if (!start_ap(x, boot_addr)) { printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); CHECK_PRINT("trace"); /* show checkpoints */ /* better panic as the AP may be running loose */ printf("panic y/n? [y] "); if (cngetc() != 'n') panic("bye-bye"); } CHECK_PRINT("trace"); /* show checkpoints */ /* record its version info */ cpu_apic_versions[x] = cpu_apic_versions[0]; all_cpus |= (1 << x); /* record AP in CPU map */ } /* build our map of 'other' CPUs */ other_cpus = all_cpus & ~(1 << cpuid); /* fill in our (BSP) APIC version */ cpu_apic_versions[0] = lapic.version; /* restore the warmstart vector */ *(u_long *) WARMBOOT_OFF = mpbioswarmvec; outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, mpbiosreason); pmap_set_opt_bsp(); /* number of APs actually started */ return mp_ncpus - 1; } /* * load the 1st level AP boot code into base memory. */ /* targets for relocation */ extern void bigJump(void); extern void bootCodeSeg(void); extern void bootDataSeg(void); extern void MPentry(void); extern u_int MP_GDT; extern u_int mp_gdtbase; static void install_ap_tramp(u_int boot_addr) { int x; int size = *(int *) ((u_long) & bootMP_size); u_char *src = (u_char *) ((u_long) bootMP); u_char *dst = (u_char *) boot_addr + KERNBASE; u_int boot_base = (u_int) bootMP; u_int8_t *dst8; u_int16_t *dst16; u_int32_t *dst32; POSTCODE(INSTALL_AP_TRAMP_POST); for (x = 0; x < size; ++x) *dst++ = *src++; /* * modify addresses in code we just moved to basemem. unfortunately we * need fairly detailed info about mpboot.s for this to work. changes * to mpboot.s might require changes here. */ /* boot code is located in KERNEL space */ dst = (u_char *) boot_addr + KERNBASE; /* modify the lgdt arg */ dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); /* modify the ljmp target for MPentry() */ dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); *dst32 = ((u_int) MPentry - KERNBASE); /* modify the target for boot code segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; /* modify the target for boot data segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; } /* * this function starts the AP (application processor) identified * by the APIC ID 'physicalCpu'. It does quite a "song and dance" * to accomplish this. This is necessary because of the nuances * of the different hardware we might encounter. It ain't pretty, * but it seems to work. */ static int start_ap(int logical_cpu, u_int boot_addr) { int physical_cpu; int vector; int cpus; u_long icr_lo, icr_hi; POSTCODE(START_AP_POST); /* get the PHYSICAL APIC ID# */ physical_cpu = CPU_TO_ID(logical_cpu); /* calculate the vector */ vector = (boot_addr >> 12) & 0xff; /* used as a watchpoint to signal AP startup */ cpus = mp_ncpus; /* * first we do an INIT/RESET IPI this INIT IPI might be run, reseting * and running the target CPU. OR this INIT IPI might be latched (P5 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be * ignored. */ /* setup the address for the target AP */ icr_hi = lapic.icr_hi & ~APIC_ID_MASK; icr_hi |= (physical_cpu << 24); lapic.icr_hi = icr_hi; /* do an INIT IPI: assert RESET */ icr_lo = lapic.icr_lo & 0xfff00000; lapic.icr_lo = icr_lo | 0x0000c500; /* wait for pending status end */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* do an INIT IPI: deassert RESET */ lapic.icr_lo = icr_lo | 0x00008500; /* wait for pending status end */ u_sleep(10000); /* wait ~10mS */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* * next we do a STARTUP IPI: the previous INIT IPI might still be * latched, (P5 bug) this 1st STARTUP would then terminate * immediately, and the previously started INIT IPI would continue. OR * the previous INIT IPI has already run. and this STARTUP IPI will * run. OR the previous INIT IPI was ignored. and this STARTUP IPI * will run. */ /* do a STARTUP IPI */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is * recognized after hardware RESET or INIT IPI. */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* wait for it to start */ set_apic_timer(5000000);/* == 5 seconds */ while (read_apic_timer()) if (mp_ncpus > cpus) return 1; /* return SUCCESS */ return 0; /* return FAILURE */ } /* * Flush the TLB on all other CPU's * * XXX: Needs to handshake and wait for completion before proceding. */ void smp_invltlb(void) { #if defined(APIC_IO) if (smp_active && invltlb_ok) all_but_self_ipi(XINVLTLB_OFFSET); #endif /* APIC_IO */ } void invlpg(u_int addr) { __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); /* send a message to the other CPUs */ smp_invltlb(); } void invltlb(void) { u_long temp; /* * This should be implemented as load_cr3(rcr3()) when load_cr3() is * inlined. */ __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); /* send a message to the other CPUs */ smp_invltlb(); } -#if defined(TEST_CPUSTOP) - -#if defined(DEBUG_CPUSTOP) -void db_printf __P((const char *fmt, ...)); -#endif /* DEBUG_CPUSTOP */ - /* * When called the executing CPU will send an IPI to all other CPUs * requesting that they halt execution. * * Usually (but not necessarily) called with 'other_cpus' as its arg. * * - Signals all CPUs in map to stop. * - Waits for each to stop. * * Returns: * -1: error * 0: NA * 1: ok * * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs * from executing at same time. */ int stop_cpus( u_int map ) { if (!smp_active) return 0; /* send IPI to all CPUs in map */ -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); -#endif /* DEBUG_CPUSTOP */ - stopped_cpus = 0; /* send the Xcpustop IPI to all CPUs in map */ selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); -#if defined(DEBUG_CPUSTOP) - db_printf(" spin\n"); -#endif /* DEBUG_CPUSTOP */ - while (stopped_cpus != map) /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" spun\nstopped\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } /* * Called by a CPU to restart stopped CPUs. * * Usually (but not necessarily) called with 'stopped_cpus' as its arg. * * - Signals all CPUs in map to restart. * - Waits for each to restart. * * Returns: * -1: error * 0: NA * 1: ok */ int restart_cpus( u_int map ) { if (!smp_active) return 0; -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", - cpuid, map, stopped_cpus); -#endif /* DEBUG_CPUSTOP */ - started_cpus = map; /* signal other cpus to restart */ while (started_cpus) /* wait for each to clear its bit */ /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" restarted\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } - -#endif /** TEST_CPUSTOP */ Index: head/sys/i386/include/apic.h =================================================================== --- head/sys/i386/include/apic.h (revision 27516) +++ head/sys/i386/include/apic.h (revision 27517) @@ -1,466 +1,469 @@ /* * Copyright (c) 1996, by Peter Wemm and Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: apic.h,v 1.7 1997/07/15 02:47:52 fsmp Exp $ + * $Id: apic.h,v 1.5 1997/07/18 19:47:48 smp Exp smp $ */ #ifndef _MACHINE_APIC_H_ #define _MACHINE_APIC_H_ /* * Local && I/O APIC definitions. */ /* * Pentium P54C+ Build-in APIC * (Advanced programmable Interrupt Controller) * * Base Address of Build-in APIC in memory location * is 0xfee00000. * * Map of APIC REgisters: * * Offset (hex) Description Read/Write state * 000 Reserved * 010 Reserved * 020 ID Local APIC ID R/W * 030 VER Local APIC Version R * 040 Reserved * 050 Reserved * 060 Reserved * 070 Reserved * 080 Task Priority Register R/W * 090 Arbitration Priority Register R * 0A0 Processor Priority Register R * 0B0 EOI Register W * 0C0 RRR Remote read R * 0D0 Logical Destination R/W * 0E0 Destination Format Register 0..27 R; 28..31 R/W * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W * 100 ISR 000-031 R * 110 ISR 032-063 R * 120 ISR 064-095 R * 130 ISR 095-128 R * 140 ISR 128-159 R * 150 ISR 160-191 R * 160 ISR 192-223 R * 170 ISR 224-255 R * 180 TMR 000-031 R * 190 TMR 032-063 R * 1A0 TMR 064-095 R * 1B0 TMR 095-128 R * 1C0 TMR 128-159 R * 1D0 TMR 160-191 R * 1E0 TMR 192-223 R * 1F0 TMR 224-255 R * 200 IRR 000-031 R * 210 IRR 032-063 R * 220 IRR 064-095 R * 230 IRR 095-128 R * 240 IRR 128-159 R * 250 IRR 160-191 R * 260 IRR 192-223 R * 270 IRR 224-255 R * 280 Error Status Register R * 290 Reserved * 2A0 Reserved * 2B0 Reserved * 2C0 Reserved * 2D0 Reserved * 2E0 Reserved * 2F0 Reserved * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W * 310 ICR_HI Interrupt Command Reg. (32-63) R/W * 320 Local Vector Table (Timer) R/W * 330 Reserved * 340 Reserved * 350 LVT1 Local Vector Table (LINT0) R/W * 360 LVT2 Local Vector Table (LINT1) R/W * 370 LVT3 Local Vector Table (ERROR) R/W * 380 Initial Count Reg. for Timer R/W * 390 Current Count of Timer R * 3A0 Reserved * 3B0 Reserved * 3C0 Reserved * 3D0 Reserved * 3E0 Timer Divide Configuration Reg. R/W * 3F0 Reserved */ /****************************************************************************** * global defines, etc. */ /** * this enables code concerned with handling more than one IO APIC. * Note: this is NOT READY for use! * #define MULTIPLE_IOAPICS */ /****************************************************************************** * LOCAL APIC structure */ #ifndef LOCORE #include #define PAD3 int : 32; int : 32; int : 32 #define PAD4 int : 32; int : 32; int : 32; int : 32 struct LAPIC { /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t id; PAD3; u_int32_t version; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t tpr; PAD3; u_int32_t apr; PAD3; u_int32_t ppr; PAD3; u_int32_t eoi; PAD3; /* reserved */ PAD4; u_int32_t ldr; PAD3; u_int32_t dfr; PAD3; u_int32_t svr; PAD3; u_int32_t isr0; PAD3; u_int32_t isr1; PAD3; u_int32_t isr2; PAD3; u_int32_t isr3; PAD3; u_int32_t isr4; PAD3; u_int32_t isr5; PAD3; u_int32_t isr6; PAD3; u_int32_t isr7; PAD3; u_int32_t tmr0; PAD3; u_int32_t tmr1; PAD3; u_int32_t tmr2; PAD3; u_int32_t tmr3; PAD3; u_int32_t tmr4; PAD3; u_int32_t tmr5; PAD3; u_int32_t tmr6; PAD3; u_int32_t tmr7; PAD3; u_int32_t irr0; PAD3; u_int32_t irr1; PAD3; u_int32_t irr2; PAD3; u_int32_t irr3; PAD3; u_int32_t irr4; PAD3; u_int32_t irr5; PAD3; u_int32_t irr6; PAD3; u_int32_t irr7; PAD3; u_int32_t esr; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t icr_lo; PAD3; u_int32_t icr_hi; PAD3; u_int32_t lvt_timer; PAD3; /* reserved */ PAD4; u_int32_t lvt_pcint; PAD3; u_int32_t lvt_lint0; PAD3; u_int32_t lvt_lint1; PAD3; u_int32_t lvt_error; PAD3; u_int32_t icr_timer; PAD3; u_int32_t ccr_timer; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t dcr_timer; PAD3; /* reserved */ PAD4; }; typedef struct LAPIC lapic_t; /****************************************************************************** * I/O APIC structure */ struct IOAPIC { u_int32_t ioregsel; PAD3; u_int32_t iowin; PAD3; }; typedef struct IOAPIC ioapic_t; #undef PAD4 #undef PAD3 #endif /* !LOCORE */ /****************************************************************************** * various code 'logical' values */ +#ifdef TEST_LOPRIO #define LOPRIO_LEVEL 0x00000010 /* TPR of CPUs accepting INT */ +#define ALLHWI_LEVEL 0x00000000 /* TPR of CPU grabbing INTs */ +#endif /** TEST_LOPRIO */ /* XXX these 2 don't really belong here... */ #define COUNT_FIELD 0x00ffffff /* count portion of the lock */ #define FREE_LOCK 0xffffffff /* value of lock when free */ /* * XXX This code assummes that the reserved field of the * local APIC TPR can be written with all 0s. * This saves quite a few memory accesses. * If the silicon ever changes then things will break! * It affects mplock.s, swtch.s, and possibly other files. */ #define CHEAP_TPR /****************************************************************************** * LOCAL APIC defines */ /* default physical locations of LOCAL (CPU) APICs */ #define DEFAULT_APIC_BASE 0xfee00000 /* fields in VER */ #define APIC_VER_VERSION 0x000000ff #define APIC_VER_MAXLVT 0x00ff0000 #define MAXLVTSHIFT 16 /* fields in SVR */ #define APIC_SVR_VECTOR 0x000000ff #define APIC_SVR_VEC_PROG 0x000000f0 #define APIC_SVR_VEC_FIX 0x0000000f #define APIC_SVR_ENABLE 0x00000100 # define APIC_SVR_SWDIS 0x00000000 # define APIC_SVR_SWEN 0x00000100 #define APIC_SVR_FOCUS 0x00000200 # define APIC_SVR_FEN 0x00000000 # define APIC_SVR_FDIS 0x00000200 /* fields in TPR */ #define APIC_TPR_PRIO 0x000000ff # define APIC_TPR_INT 0x000000f0 # define APIC_TPR_SUB 0x0000000f /* fields in ICR_LOW */ #define APIC_VECTOR_MASK 0x000000ff #define APIC_DELMODE_MASK 0x00000700 # define APIC_DELMODE_FIXED 0x00000000 # define APIC_DELMODE_LOWPRIO 0x00000100 # define APIC_DELMODE_SMI 0x00000200 # define APIC_DELMODE_RR 0x00000300 # define APIC_DELMODE_NMI 0x00000400 # define APIC_DELMODE_INIT 0x00000500 # define APIC_DELMODE_STARTUP 0x00000600 # define APIC_DELMODE_RESV 0x00000700 #define APIC_DESTMODE_MASK 0x00000800 # define APIC_DESTMODE_PHY 0x00000000 # define APIC_DESTMODE_LOG 0x00000800 #define APIC_DELSTAT_MASK 0x00001000 # define APIC_DELSTAT_IDLE 0x00000000 # define APIC_DELSTAT_PEND 0x00001000 #define APIC_RESV1_MASK 0x00002000 #define APIC_LEVEL_MASK 0x00004000 # define APIC_LEVEL_DEASSERT 0x00000000 # define APIC_LEVEL_ASSERT 0x00004000 #define APIC_TRIGMOD_MASK 0x00008000 # define APIC_TRIGMOD_EDGE 0x00000000 # define APIC_TRIGMOD_LEVEL 0x00008000 #define APIC_RRSTAT_MASK 0x00030000 # define APIC_RRSTAT_INVALID 0x00000000 # define APIC_RRSTAT_INPROG 0x00010000 # define APIC_RRSTAT_VALID 0x00020000 # define APIC_RRSTAT_RESV 0x00030000 #define APIC_DEST_MASK 0x000c0000 # define APIC_DEST_DESTFLD 0x00000000 # define APIC_DEST_SELF 0x00040000 # define APIC_DEST_ALLISELF 0x00080000 # define APIC_DEST_ALLESELF 0x000c0000 #define APIC_RESV2_MASK 0xfff00000 /* fields in ICR_HIGH */ #define APIC_ID_MASK 0x0f000000 /* fields in LVT1/2 */ #define APIC_LVT_VECTOR 0x000000ff #define APIC_LVT_DM 0x00000700 # define APIC_LVT_DM_FIXED 0x00000000 # define APIC_LVT_DM_NMI 0x00000400 # define APIC_LVT_DM_EXTINT 0x00000700 #define APIC_LVT_DS 0x00001000 #define APIC_LVT_IIPP 0x00002000 #define APIC_LVT_IIPP_INTALO 0x00002000 #define APIC_LVT_IIPP_INTAHI 0x00000000 #define APIC_LVT_RIRR 0x00004000 #define APIC_LVT_TM 0x00008000 #define APIC_LVT_M 0x00010000 /* fields in LVT Timer */ #define APIC_LVTT_VECTOR 0x000000ff #define APIC_LVTT_DS 0x00001000 #define APIC_LVTT_M 0x00010000 #define APIC_LVTT_TM 0x00020000 /* fields in TDCR */ #define APIC_TDCR_2 0x00 #define APIC_TDCR_4 0x01 #define APIC_TDCR_8 0x02 #define APIC_TDCR_16 0x03 #define APIC_TDCR_32 0x08 #define APIC_TDCR_64 0x09 #define APIC_TDCR_128 0x0a #define APIC_TDCR_1 0x0b /* * fields in IRR * ISA INTerrupts are in bits 16-31 of the 1st IRR register. * these masks DON'T EQUAL the isa IRQs of the same name. */ #define APIC_IRQ0 0x00000001 #define APIC_IRQ1 0x00000002 #define APIC_IRQ2 0x00000004 #define APIC_IRQ3 0x00000008 #define APIC_IRQ4 0x00000010 #define APIC_IRQ5 0x00000020 #define APIC_IRQ6 0x00000040 #define APIC_IRQ7 0x00000080 #define APIC_IRQ8 0x00000100 #define APIC_IRQ9 0x00000200 #define APIC_IRQ10 0x00000400 #define APIC_IRQ11 0x00000800 #define APIC_IRQ12 0x00001000 #define APIC_IRQ13 0x00002000 #define APIC_IRQ14 0x00004000 #define APIC_IRQ15 0x00008000 #define APIC_IRQ16 0x00010000 #define APIC_IRQ17 0x00020000 #define APIC_IRQ18 0x00040000 #define APIC_IRQ19 0x00080000 #define APIC_IRQ20 0x00100000 #define APIC_IRQ21 0x00200000 #define APIC_IRQ22 0x00400000 #define APIC_IRQ23 0x00800000 /****************************************************************************** * I/O APIC defines */ /* default physical locations of an IO APIC */ #define DEFAULT_IO_APIC_BASE 0xfec00000 /* window register offset */ #define IOAPIC_WINDOW 0x10 /* indexes into IO APIC */ #define IOAPIC_ID 0x00 #define IOAPIC_VER 0x01 #define IOAPIC_ARB 0x02 #define IOAPIC_REDTBL 0x10 #define IOAPIC_REDTBL0 IOAPIC_REDTBL #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) /* fields in VER */ #define IOART_VER_VERSION 0x000000ff #define IOART_VER_MAXREDIR 0x00ff0000 #define MAXREDIRSHIFT 16 /* * fields in the IO APIC's redirection table entries */ #define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */ #define IOART_RESV 0x00fe0000 /* reserved */ #define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */ # define IOART_INTMCLR 0x00000000 /* clear, allow INTs */ # define IOART_INTMSET 0x00010000 /* set, inhibit INTs */ #define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */ # define IOART_TRGREDG 0x00000000 /* edge */ # define IOART_TRGRLVL 0x00008000 /* level */ #define IOART_REM_IRR 0x00004000 /* RO: remote IRR */ #define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */ # define IOART_INTAHI 0x00000000 /* active high */ # define IOART_INTALO 0x00002000 /* active low */ #define IOART_DELIVS 0x00001000 /* RO: delivery status */ #define IOART_DESTMOD 0x00000800 /* R/W: destination mode */ # define IOART_DESTPHY 0x00000000 /* physical */ # define IOART_DESTLOG 0x00000800 /* logical */ #define IOART_DELMOD 0x00000700 /* R/W: delivery mode */ # define IOART_DELFIXED 0x00000000 /* fixed */ # define IOART_DELLOPRI 0x00000100 /* lowest priority */ # define IOART_DELSMI 0x00000200 /* System Management INT */ # define IOART_DELRSV1 0x00000300 /* reserved */ # define IOART_DELNMI 0x00000400 /* NMI signal */ # define IOART_DELINIT 0x00000500 /* INIT signal */ # define IOART_DELRSV2 0x00000600 /* reserved */ # define IOART_DELEXINT 0x00000700 /* External INTerrupt */ #define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */ #endif /* _MACHINE_APIC_H_ */ Index: head/sys/i386/include/apicreg.h =================================================================== --- head/sys/i386/include/apicreg.h (revision 27516) +++ head/sys/i386/include/apicreg.h (revision 27517) @@ -1,466 +1,469 @@ /* * Copyright (c) 1996, by Peter Wemm and Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: apic.h,v 1.7 1997/07/15 02:47:52 fsmp Exp $ + * $Id: apic.h,v 1.5 1997/07/18 19:47:48 smp Exp smp $ */ #ifndef _MACHINE_APIC_H_ #define _MACHINE_APIC_H_ /* * Local && I/O APIC definitions. */ /* * Pentium P54C+ Build-in APIC * (Advanced programmable Interrupt Controller) * * Base Address of Build-in APIC in memory location * is 0xfee00000. * * Map of APIC REgisters: * * Offset (hex) Description Read/Write state * 000 Reserved * 010 Reserved * 020 ID Local APIC ID R/W * 030 VER Local APIC Version R * 040 Reserved * 050 Reserved * 060 Reserved * 070 Reserved * 080 Task Priority Register R/W * 090 Arbitration Priority Register R * 0A0 Processor Priority Register R * 0B0 EOI Register W * 0C0 RRR Remote read R * 0D0 Logical Destination R/W * 0E0 Destination Format Register 0..27 R; 28..31 R/W * 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W * 100 ISR 000-031 R * 110 ISR 032-063 R * 120 ISR 064-095 R * 130 ISR 095-128 R * 140 ISR 128-159 R * 150 ISR 160-191 R * 160 ISR 192-223 R * 170 ISR 224-255 R * 180 TMR 000-031 R * 190 TMR 032-063 R * 1A0 TMR 064-095 R * 1B0 TMR 095-128 R * 1C0 TMR 128-159 R * 1D0 TMR 160-191 R * 1E0 TMR 192-223 R * 1F0 TMR 224-255 R * 200 IRR 000-031 R * 210 IRR 032-063 R * 220 IRR 064-095 R * 230 IRR 095-128 R * 240 IRR 128-159 R * 250 IRR 160-191 R * 260 IRR 192-223 R * 270 IRR 224-255 R * 280 Error Status Register R * 290 Reserved * 2A0 Reserved * 2B0 Reserved * 2C0 Reserved * 2D0 Reserved * 2E0 Reserved * 2F0 Reserved * 300 ICR_LOW Interrupt Command Reg. (0-31) R/W * 310 ICR_HI Interrupt Command Reg. (32-63) R/W * 320 Local Vector Table (Timer) R/W * 330 Reserved * 340 Reserved * 350 LVT1 Local Vector Table (LINT0) R/W * 360 LVT2 Local Vector Table (LINT1) R/W * 370 LVT3 Local Vector Table (ERROR) R/W * 380 Initial Count Reg. for Timer R/W * 390 Current Count of Timer R * 3A0 Reserved * 3B0 Reserved * 3C0 Reserved * 3D0 Reserved * 3E0 Timer Divide Configuration Reg. R/W * 3F0 Reserved */ /****************************************************************************** * global defines, etc. */ /** * this enables code concerned with handling more than one IO APIC. * Note: this is NOT READY for use! * #define MULTIPLE_IOAPICS */ /****************************************************************************** * LOCAL APIC structure */ #ifndef LOCORE #include #define PAD3 int : 32; int : 32; int : 32 #define PAD4 int : 32; int : 32; int : 32; int : 32 struct LAPIC { /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t id; PAD3; u_int32_t version; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t tpr; PAD3; u_int32_t apr; PAD3; u_int32_t ppr; PAD3; u_int32_t eoi; PAD3; /* reserved */ PAD4; u_int32_t ldr; PAD3; u_int32_t dfr; PAD3; u_int32_t svr; PAD3; u_int32_t isr0; PAD3; u_int32_t isr1; PAD3; u_int32_t isr2; PAD3; u_int32_t isr3; PAD3; u_int32_t isr4; PAD3; u_int32_t isr5; PAD3; u_int32_t isr6; PAD3; u_int32_t isr7; PAD3; u_int32_t tmr0; PAD3; u_int32_t tmr1; PAD3; u_int32_t tmr2; PAD3; u_int32_t tmr3; PAD3; u_int32_t tmr4; PAD3; u_int32_t tmr5; PAD3; u_int32_t tmr6; PAD3; u_int32_t tmr7; PAD3; u_int32_t irr0; PAD3; u_int32_t irr1; PAD3; u_int32_t irr2; PAD3; u_int32_t irr3; PAD3; u_int32_t irr4; PAD3; u_int32_t irr5; PAD3; u_int32_t irr6; PAD3; u_int32_t irr7; PAD3; u_int32_t esr; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t icr_lo; PAD3; u_int32_t icr_hi; PAD3; u_int32_t lvt_timer; PAD3; /* reserved */ PAD4; u_int32_t lvt_pcint; PAD3; u_int32_t lvt_lint0; PAD3; u_int32_t lvt_lint1; PAD3; u_int32_t lvt_error; PAD3; u_int32_t icr_timer; PAD3; u_int32_t ccr_timer; PAD3; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; /* reserved */ PAD4; u_int32_t dcr_timer; PAD3; /* reserved */ PAD4; }; typedef struct LAPIC lapic_t; /****************************************************************************** * I/O APIC structure */ struct IOAPIC { u_int32_t ioregsel; PAD3; u_int32_t iowin; PAD3; }; typedef struct IOAPIC ioapic_t; #undef PAD4 #undef PAD3 #endif /* !LOCORE */ /****************************************************************************** * various code 'logical' values */ +#ifdef TEST_LOPRIO #define LOPRIO_LEVEL 0x00000010 /* TPR of CPUs accepting INT */ +#define ALLHWI_LEVEL 0x00000000 /* TPR of CPU grabbing INTs */ +#endif /** TEST_LOPRIO */ /* XXX these 2 don't really belong here... */ #define COUNT_FIELD 0x00ffffff /* count portion of the lock */ #define FREE_LOCK 0xffffffff /* value of lock when free */ /* * XXX This code assummes that the reserved field of the * local APIC TPR can be written with all 0s. * This saves quite a few memory accesses. * If the silicon ever changes then things will break! * It affects mplock.s, swtch.s, and possibly other files. */ #define CHEAP_TPR /****************************************************************************** * LOCAL APIC defines */ /* default physical locations of LOCAL (CPU) APICs */ #define DEFAULT_APIC_BASE 0xfee00000 /* fields in VER */ #define APIC_VER_VERSION 0x000000ff #define APIC_VER_MAXLVT 0x00ff0000 #define MAXLVTSHIFT 16 /* fields in SVR */ #define APIC_SVR_VECTOR 0x000000ff #define APIC_SVR_VEC_PROG 0x000000f0 #define APIC_SVR_VEC_FIX 0x0000000f #define APIC_SVR_ENABLE 0x00000100 # define APIC_SVR_SWDIS 0x00000000 # define APIC_SVR_SWEN 0x00000100 #define APIC_SVR_FOCUS 0x00000200 # define APIC_SVR_FEN 0x00000000 # define APIC_SVR_FDIS 0x00000200 /* fields in TPR */ #define APIC_TPR_PRIO 0x000000ff # define APIC_TPR_INT 0x000000f0 # define APIC_TPR_SUB 0x0000000f /* fields in ICR_LOW */ #define APIC_VECTOR_MASK 0x000000ff #define APIC_DELMODE_MASK 0x00000700 # define APIC_DELMODE_FIXED 0x00000000 # define APIC_DELMODE_LOWPRIO 0x00000100 # define APIC_DELMODE_SMI 0x00000200 # define APIC_DELMODE_RR 0x00000300 # define APIC_DELMODE_NMI 0x00000400 # define APIC_DELMODE_INIT 0x00000500 # define APIC_DELMODE_STARTUP 0x00000600 # define APIC_DELMODE_RESV 0x00000700 #define APIC_DESTMODE_MASK 0x00000800 # define APIC_DESTMODE_PHY 0x00000000 # define APIC_DESTMODE_LOG 0x00000800 #define APIC_DELSTAT_MASK 0x00001000 # define APIC_DELSTAT_IDLE 0x00000000 # define APIC_DELSTAT_PEND 0x00001000 #define APIC_RESV1_MASK 0x00002000 #define APIC_LEVEL_MASK 0x00004000 # define APIC_LEVEL_DEASSERT 0x00000000 # define APIC_LEVEL_ASSERT 0x00004000 #define APIC_TRIGMOD_MASK 0x00008000 # define APIC_TRIGMOD_EDGE 0x00000000 # define APIC_TRIGMOD_LEVEL 0x00008000 #define APIC_RRSTAT_MASK 0x00030000 # define APIC_RRSTAT_INVALID 0x00000000 # define APIC_RRSTAT_INPROG 0x00010000 # define APIC_RRSTAT_VALID 0x00020000 # define APIC_RRSTAT_RESV 0x00030000 #define APIC_DEST_MASK 0x000c0000 # define APIC_DEST_DESTFLD 0x00000000 # define APIC_DEST_SELF 0x00040000 # define APIC_DEST_ALLISELF 0x00080000 # define APIC_DEST_ALLESELF 0x000c0000 #define APIC_RESV2_MASK 0xfff00000 /* fields in ICR_HIGH */ #define APIC_ID_MASK 0x0f000000 /* fields in LVT1/2 */ #define APIC_LVT_VECTOR 0x000000ff #define APIC_LVT_DM 0x00000700 # define APIC_LVT_DM_FIXED 0x00000000 # define APIC_LVT_DM_NMI 0x00000400 # define APIC_LVT_DM_EXTINT 0x00000700 #define APIC_LVT_DS 0x00001000 #define APIC_LVT_IIPP 0x00002000 #define APIC_LVT_IIPP_INTALO 0x00002000 #define APIC_LVT_IIPP_INTAHI 0x00000000 #define APIC_LVT_RIRR 0x00004000 #define APIC_LVT_TM 0x00008000 #define APIC_LVT_M 0x00010000 /* fields in LVT Timer */ #define APIC_LVTT_VECTOR 0x000000ff #define APIC_LVTT_DS 0x00001000 #define APIC_LVTT_M 0x00010000 #define APIC_LVTT_TM 0x00020000 /* fields in TDCR */ #define APIC_TDCR_2 0x00 #define APIC_TDCR_4 0x01 #define APIC_TDCR_8 0x02 #define APIC_TDCR_16 0x03 #define APIC_TDCR_32 0x08 #define APIC_TDCR_64 0x09 #define APIC_TDCR_128 0x0a #define APIC_TDCR_1 0x0b /* * fields in IRR * ISA INTerrupts are in bits 16-31 of the 1st IRR register. * these masks DON'T EQUAL the isa IRQs of the same name. */ #define APIC_IRQ0 0x00000001 #define APIC_IRQ1 0x00000002 #define APIC_IRQ2 0x00000004 #define APIC_IRQ3 0x00000008 #define APIC_IRQ4 0x00000010 #define APIC_IRQ5 0x00000020 #define APIC_IRQ6 0x00000040 #define APIC_IRQ7 0x00000080 #define APIC_IRQ8 0x00000100 #define APIC_IRQ9 0x00000200 #define APIC_IRQ10 0x00000400 #define APIC_IRQ11 0x00000800 #define APIC_IRQ12 0x00001000 #define APIC_IRQ13 0x00002000 #define APIC_IRQ14 0x00004000 #define APIC_IRQ15 0x00008000 #define APIC_IRQ16 0x00010000 #define APIC_IRQ17 0x00020000 #define APIC_IRQ18 0x00040000 #define APIC_IRQ19 0x00080000 #define APIC_IRQ20 0x00100000 #define APIC_IRQ21 0x00200000 #define APIC_IRQ22 0x00400000 #define APIC_IRQ23 0x00800000 /****************************************************************************** * I/O APIC defines */ /* default physical locations of an IO APIC */ #define DEFAULT_IO_APIC_BASE 0xfec00000 /* window register offset */ #define IOAPIC_WINDOW 0x10 /* indexes into IO APIC */ #define IOAPIC_ID 0x00 #define IOAPIC_VER 0x01 #define IOAPIC_ARB 0x02 #define IOAPIC_REDTBL 0x10 #define IOAPIC_REDTBL0 IOAPIC_REDTBL #define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02) #define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04) #define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06) #define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08) #define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a) #define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c) #define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e) #define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10) #define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12) #define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14) #define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16) #define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18) #define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a) #define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c) #define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e) #define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20) #define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22) #define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24) #define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26) #define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28) #define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a) #define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c) #define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e) /* fields in VER */ #define IOART_VER_VERSION 0x000000ff #define IOART_VER_MAXREDIR 0x00ff0000 #define MAXREDIRSHIFT 16 /* * fields in the IO APIC's redirection table entries */ #define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */ #define IOART_RESV 0x00fe0000 /* reserved */ #define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */ # define IOART_INTMCLR 0x00000000 /* clear, allow INTs */ # define IOART_INTMSET 0x00010000 /* set, inhibit INTs */ #define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */ # define IOART_TRGREDG 0x00000000 /* edge */ # define IOART_TRGRLVL 0x00008000 /* level */ #define IOART_REM_IRR 0x00004000 /* RO: remote IRR */ #define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */ # define IOART_INTAHI 0x00000000 /* active high */ # define IOART_INTALO 0x00002000 /* active low */ #define IOART_DELIVS 0x00001000 /* RO: delivery status */ #define IOART_DESTMOD 0x00000800 /* R/W: destination mode */ # define IOART_DESTPHY 0x00000000 /* physical */ # define IOART_DESTLOG 0x00000800 /* logical */ #define IOART_DELMOD 0x00000700 /* R/W: delivery mode */ # define IOART_DELFIXED 0x00000000 /* fixed */ # define IOART_DELLOPRI 0x00000100 /* lowest priority */ # define IOART_DELSMI 0x00000200 /* System Management INT */ # define IOART_DELRSV1 0x00000300 /* reserved */ # define IOART_DELNMI 0x00000400 /* NMI signal */ # define IOART_DELINIT 0x00000500 /* INIT signal */ # define IOART_DELRSV2 0x00000600 /* reserved */ # define IOART_DELEXINT 0x00000700 /* External INTerrupt */ #define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */ #endif /* _MACHINE_APIC_H_ */ Index: head/sys/i386/include/mptable.h =================================================================== --- head/sys/i386/include/mptable.h (revision 27516) +++ head/sys/i386/include/mptable.h (revision 27517) @@ -1,1834 +1,1803 @@ /* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: mp_machdep.c,v 1.28 1997/07/17 19:44:56 dyson Exp $ + * $Id: mp_machdep.c,v 1.16 1997/07/18 19:45:41 smp Exp smp $ */ #include "opt_smp.h" #include /* for KERNBASE */ #include #include #include #include #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include #include #include #include #include #include #include -#include /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP _TEST1 */ +#include /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ #include #include #include /* cngetc() */ #if defined(APIC_IO) #include /* setidt() */ #include /* IPIs */ #include /* IPIs */ #endif /* APIC_IO */ #define WARMBOOT_TARGET 0 #define WARMBOOT_OFF (KERNBASE + 0x0467) #define WARMBOOT_SEG (KERNBASE + 0x0469) #define BIOS_BASE (0xf0000) #define BIOS_SIZE (0x10000) #define BIOS_COUNT (BIOS_SIZE/4) #define CMOS_REG (0x70) #define CMOS_DATA (0x71) #define BIOS_RESET (0x0f) #define BIOS_WARM (0x0a) #define PROCENTRY_FLAG_EN 0x01 #define PROCENTRY_FLAG_BP 0x02 #define IOAPICENTRY_FLAG_EN 0x01 /* MP Floating Pointer Structure */ typedef struct MPFPS { char signature[4]; void *pap; u_char length; u_char spec_rev; u_char checksum; u_char mpfb1; u_char mpfb2; u_char mpfb3; u_char mpfb4; u_char mpfb5; } *mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { char signature[4]; u_short base_table_length; u_char spec_rev; u_char checksum; u_char oem_id[8]; u_char product_id[12]; void *oem_table_pointer; u_short oem_table_size; u_short entry_count; void *apic_address; u_short extended_table_length; u_char extended_table_checksum; u_char reserved; } *mpcth_t; typedef struct PROCENTRY { u_char type; u_char apic_id; u_char apic_version; u_char cpu_flags; u_long cpu_signature; u_long feature_flags; u_long reserved1; u_long reserved2; } *proc_entry_ptr; typedef struct BUSENTRY { u_char type; u_char bus_id; char bus_type[6]; } *bus_entry_ptr; typedef struct IOAPICENTRY { u_char type; u_char apic_id; u_char apic_version; u_char apic_flags; void *apic_address; } *io_apic_entry_ptr; typedef struct INTENTRY { u_char type; u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } *int_entry_ptr; /* descriptions of MP basetable entries */ typedef struct BASETABLE_ENTRY { u_char type; u_char length; char name[16]; } basetable_entry; /* * this code MUST be enabled here and in mpboot.s. * it follows the very early stages of AP boot by placing values in CMOS ram. * it NORMALLY will never be needed and thus the primitive method for enabling. * #define CHECK_POINTS */ #if defined(CHECK_POINTS) #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) #define CHECK_INIT(D); \ CHECK_WRITE(0x34, (D)); \ CHECK_WRITE(0x35, (D)); \ CHECK_WRITE(0x36, (D)); \ CHECK_WRITE(0x37, (D)); \ CHECK_WRITE(0x38, (D)); \ CHECK_WRITE(0x39, (D)); #define CHECK_PRINT(S); \ printf("%s: %d, %d, %d, %d, %d, %d\n", \ (S), \ CHECK_READ(0x34), \ CHECK_READ(0x35), \ CHECK_READ(0x36), \ CHECK_READ(0x37), \ CHECK_READ(0x38), \ CHECK_READ(0x39)); #else /* CHECK_POINTS */ #define CHECK_INIT(D) #define CHECK_PRINT(S) #endif /* CHECK_POINTS */ /* * Values to send to the POST hardware. */ #define MP_BOOTADDRESS_POST 0x10 #define MP_PROBE_POST 0x11 #define MP_START_POST 0x12 #define MP_ANNOUNCE_POST 0x13 #define MPTABLE_PASS1_POST 0x14 #define MPTABLE_PASS2_POST 0x15 #define MP_ENABLE_POST 0x16 #define START_ALL_APS_POST 0x17 #define INSTALL_AP_TRAMP_POST 0x18 #define START_AP_POST 0x19 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ int current_postcode; /** XXX FIXME: what system files declare these??? */ extern struct region_descriptor r_gdt, r_idt; int mp_ncpus; /* # of CPUs, including BSP */ int mp_naps; /* # of Applications processors */ int mp_nbusses; /* # of busses */ int mp_napics; /* # of IO APICs */ int boot_cpu_id; /* designated BSP */ vm_offset_t cpu_apic_address; vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ u_int32_t cpu_apic_versions[NCPU]; u_int32_t io_apic_versions[NAPIC]; /* * APIC ID logical/physical mapping structures. * We oversize these to simplify boot-time config. */ int cpu_num_to_apic_id[NAPICID]; int io_num_to_apic_id[NAPICID]; int apic_id_to_logical[NAPICID]; /* Bitmap of all available CPUs */ u_int all_cpus; /* Boot of AP uses this PTD */ u_int *bootPTD; /* Hotwire a 0->4MB V==P mapping */ extern pt_entry_t KPTphys; /* Virtual address of per-cpu common_tss */ extern struct i386tss common_tss; /* * Local data and functions. */ static int mp_capable; static u_int boot_address; static u_int base_memory; static int picmode; /* 0: virtual wire mode, 1: PIC mode */ static mpfps_t mpfps; static int search_for_sig(u_int32_t target, int count); static void mp_enable(u_int boot_addr); static int mptable_pass1(void); static int mptable_pass2(void); static void default_mp_table(int type); static int start_all_aps(u_int boot_addr); static void install_ap_tramp(u_int boot_addr); static int start_ap(int logicalCpu, u_int boot_addr); /* * Calculate usable address in base memory for AP trampoline code. */ u_int mp_bootaddress(u_int basemem) { POSTCODE(MP_BOOTADDRESS_POST); base_memory = basemem * 1024; /* convert to bytes */ boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ if ((base_memory - boot_address) < bootMP_size) boot_address -= 4096; /* not enough, lower by 4k */ return boot_address; } /* * Look for an Intel MP spec table (ie, SMP capable hardware). */ int mp_probe(void) { int x; u_long segment; u_int32_t target; POSTCODE(MP_PROBE_POST); /* see if EBDA exists */ if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { /* search first 1K of EBDA */ target = (u_int32_t) (segment << 4); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } else { /* last 1K of base memory, effective 'top of base' passed in */ target = (u_int32_t) (base_memory - 0x400); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } /* search the BIOS */ target = (u_int32_t) BIOS_BASE; if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) goto found; /* nothing found */ mpfps = (mpfps_t)0; mp_capable = 0; return 0; found: /* calculate needed resources */ mpfps = (mpfps_t)x; if (mptable_pass1()) panic("you must reconfigure your kernel"); /* flag fact that we are running multiple processors */ mp_capable = 1; return 1; } /* * Startup the SMP processors. */ void mp_start(void) { POSTCODE(MP_START_POST); /* look for MP capable motherboard */ if (mp_capable) mp_enable(boot_address); else panic("MP hardware not found!"); } /* * Print various information about the SMP system hardware and setup. */ void mp_announce(void) { int x; POSTCODE(MP_ANNOUNCE_POST); printf("FreeBSD/SMP: Multiprocessor motherboard\n"); printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); printf(", version: 0x%08x", cpu_apic_versions[0]); printf(", at 0x%08x\n", cpu_apic_address); for (x = 1; x <= mp_naps; ++x) { printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); printf(", version: 0x%08x", cpu_apic_versions[x]); printf(", at 0x%08x\n", cpu_apic_address); } #if defined(APIC_IO) for (x = 0; x < mp_napics; ++x) { printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); printf(", version: 0x%08x", io_apic_versions[x]); printf(", at 0x%08x\n", io_apic_address[x]); } #else printf(" Warning: APIC I/O disabled\n"); #endif /* APIC_IO */ } /* * AP cpu's call this to sync up protected mode. */ void init_secondary(void) { int gsel_tss, slot; r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; r_gdt.rd_base = (int) gdt; lgdt(&r_gdt); /* does magic intra-segment return */ lidt(&r_idt); lldt(_default_ldt); slot = NGDT + cpuid; gsel_tss = GSEL(slot, SEL_KPL); gdt[slot].sd.sd_type = SDT_SYS386TSS; common_tss.tss_esp0 = 0; /* not used until after switch */ common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); common_tss.tss_ioopt = (sizeof common_tss) << 16; ltr(gsel_tss); load_cr0(0x8005003b); /* XXX! */ PTD[0] = 0; pmap_set_opt((unsigned *)PTD); invltlb(); } #if defined(APIC_IO) /* * Final configuration of the BSP's local APIC: * - disable 'pic mode'. * - disable 'virtual wire mode'. * - enable NMI. */ void bsp_apic_configure(void) { u_char byte; u_int32_t temp; /* leave 'pic mode' if necessary */ if (picmode) { outb(0x22, 0x70); /* select IMCR */ byte = inb(0x23); /* current contents */ byte |= 0x01; /* mask external INTR */ outb(0x23, byte); /* disconnect 8259s/NMI */ } /* mask lint0 (the 8259 'virtual wire' connection) */ temp = lapic.lvt_lint0; temp |= APIC_LVT_M; /* set the mask */ lapic.lvt_lint0 = temp; /* setup lint1 to handle NMI */ temp = lapic.lvt_lint1; temp &= ~APIC_LVT_M; /* clear the mask */ lapic.lvt_lint1 = temp; if (bootverbose) apic_dump(); } #endif /* APIC_IO */ /******************************************************************* * local functions and data */ /* * start the SMP system */ static void mp_enable(u_int boot_addr) { int x; #if defined(APIC_IO) int apic; u_int ux; #endif /* APIC_IO */ POSTCODE(MP_ENABLE_POST); /* turn on 4MB of V == P addressing so we can get to MP table */ *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); invltlb(); /* examine the MP table for needed info, uses physical addresses */ x = mptable_pass2(); *(int *)PTD = 0; invltlb(); /* can't process default configs till the CPU APIC is pmapped */ if (x) default_mp_table(x); #if defined(APIC_IO) /* fill the LOGICAL io_apic_versions table */ for (apic = 0; apic < mp_napics; ++apic) { ux = io_apic_read(apic, IOAPIC_VER); io_apic_versions[apic] = ux; } /* program each IO APIC in the system */ for (apic = 0; apic < mp_napics; ++apic) if (io_apic_setup(apic) < 0) panic("IO APIC setup failure"); /* install a 'Spurious INTerrupt' vector */ setidt(XSPURIOUSINT_OFFSET, Xspuriousint, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); /* install an inter-CPU IPI for TLB invalidation */ setidt(XINVLTLB_OFFSET, Xinvltlb, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#if defined(TEST_CPUSTOP) /* install an inter-CPU IPI for CPU stop/restart */ setidt(XCPUSTOP_OFFSET, Xcpustop, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#endif /** TEST_CPUSTOP */ #if defined(TEST_TEST1) - /* install a 'Spurious INTerrupt' vector */ + /* install a "fake hardware INTerrupt" vector */ setidt(XTEST1_OFFSET, Xtest1, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /** TEST_TEST1 */ #endif /* APIC_IO */ /* start each Application Processor */ start_all_aps(boot_addr); /* * The init process might be started on a different CPU now, * and the boot CPU might not call prepare_usermode to get * cr0 correctly configured. Thus we initialize cr0 here. */ load_cr0(rcr0() | CR0_WP | CR0_AM); } /* * look for the MP spec signature */ /* string defined by the Intel MP Spec as identifying the MP table */ #define MP_SIG 0x5f504d5f /* _MP_ */ #define NEXT(X) ((X) += 4) static int search_for_sig(u_int32_t target, int count) { int x; u_int32_t *addr = (u_int32_t *) (KERNBASE + target); for (x = 0; x < count; NEXT(x)) if (addr[x] == MP_SIG) /* make array index a byte index */ return (target + (x * sizeof(u_int32_t))); return -1; } static basetable_entry basetable_entry_types[] = { {0, 20, "Processor"}, {1, 8, "Bus"}, {2, 8, "I/O APIC"}, {3, 8, "I/O INT"}, {4, 8, "Local INT"} }; typedef struct BUSDATA { u_char bus_id; enum busTypes bus_type; } bus_datum; typedef struct INTDATA { u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } io_int, local_int; typedef struct BUSTYPENAME { u_char type; char name[7]; } bus_type_name; static bus_type_name bus_type_table[] = { {CBUS, "CBUS"}, {CBUSII, "CBUSII"}, {EISA, "EISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {ISA, "ISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {PCI, "PCI"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {XPRESS, "XPRESS"}, {UNKNOWN_BUSTYPE, "---"} }; /* from MP spec v1.4, table 5-1 */ static int default_data[7][5] = { /* nbus, id0, type0, id1, type1 */ {1, 0, ISA, 255, 255}, {1, 0, EISA, 255, 255}, {1, 0, EISA, 255, 255}, {0, 255, 255, 255, 255},/* MCA not supported */ {2, 0, ISA, 1, PCI}, {2, 0, EISA, 1, PCI}, {0, 255, 255, 255, 255} /* MCA not supported */ }; /* the bus data */ bus_datum bus_data[NBUS]; /* the IO INT data, one entry per possible APIC INTerrupt */ io_int io_apic_ints[NINTR]; static int nintrs; static void fix_mp_table __P((void)); static int processor_entry __P((proc_entry_ptr entry, int cpu)); static int bus_entry __P((bus_entry_ptr entry, int bus)); static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); static int int_entry __P((int_entry_ptr entry, int intr)); static int lookup_bus_type __P((char *name)); /* * 1st pass on motherboard's Intel MP specification table. * * initializes: * mp_ncpus = 1 * * determines: * cpu_apic_address (common to all CPUs) * io_apic_address[N] * mp_naps * mp_nbusses * mp_napics * nintrs */ static int mptable_pass1(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int mustpanic; POSTCODE(MPTABLE_PASS1_POST); mustpanic = 0; /* clear various tables */ for (x = 0; x < NAPICID; ++x) { io_apic_address[x] = ~0; /* IO APIC address table */ } /* init everything to empty */ mp_naps = 0; mp_nbusses = 0; mp_napics = 0; nintrs = 0; /* check for use of 'default' configuration */ if (mpfps->mpfb1 != 0) { /* use default addresses */ cpu_apic_address = DEFAULT_APIC_BASE; io_apic_address[0] = DEFAULT_IO_APIC_BASE; /* fill in with defaults */ mp_naps = 2; /* includes BSP */ mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; #if defined(APIC_IO) mp_napics = 1; nintrs = 16; #endif /* APIC_IO */ } else { if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); cpu_apic_address = (vm_offset_t) cth->apic_address; /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; while (count--) { switch (type = *(u_char *) position) { case 0: /* processor_entry */ if (((proc_entry_ptr)position)->cpu_flags & PROCENTRY_FLAG_EN) ++mp_naps; break; case 1: /* bus_entry */ ++mp_nbusses; break; case 2: /* io_apic_entry */ if (((io_apic_entry_ptr)position)->apic_flags & IOAPICENTRY_FLAG_EN) io_apic_address[mp_napics++] = (vm_offset_t)((io_apic_entry_ptr) position)->apic_address; break; case 3: /* int_entry */ ++nintrs; break; case 4: /* int_entry */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char*)position += basetable_entry_types[type].length; } } /* qualify the numbers */ if (mp_naps > NCPU) printf("Warning: only using %d of %d available CPUs!\n", NCPU, mp_naps); #if 0 /** XXX we consider this legal now (but should we?) */ mustpanic = 1; #endif if (mp_nbusses > NBUS) { printf("found %d busses, increase NBUS\n", mp_nbusses); mustpanic = 1; } if (mp_napics > NAPIC) { printf("found %d apics, increase NAPIC\n", mp_napics); mustpanic = 1; } if (nintrs > NINTR) { printf("found %d intrs, increase NINTR\n", nintrs); mustpanic = 1; } /* * Count the BSP. * This is also used as a counter while starting the APs. */ mp_ncpus = 1; --mp_naps; /* subtract the BSP */ return mustpanic; } /* * 2nd pass on motherboard's Intel MP specification table. * * sets: * boot_cpu_id * ID_TO_IO(N), phy APIC ID to log CPU/IO table * CPU_TO_ID(N), logical CPU to APIC ID table * IO_TO_ID(N), logical IO to APIC ID table * bus_data[N] * io_apic_ints[N] */ static int mptable_pass2(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int apic, bus, cpu, intr; POSTCODE(MPTABLE_PASS2_POST); /* clear various tables */ for (x = 0; x < NAPICID; ++x) { ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ } /* clear bus data table */ for (x = 0; x < NBUS; ++x) bus_data[x].bus_id = 0xff; /* clear IO APIC INT table */ for (x = 0; x < NINTR; ++x) io_apic_ints[x].int_type = 0xff; /* setup the cpu/apic mapping arrays */ boot_cpu_id = -1; /* record whether PIC or virtual-wire mode */ picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; /* check for use of 'default' configuration */ #if defined(TEST_DEFAULT_CONFIG) return TEST_DEFAULT_CONFIG; #else if (mpfps->mpfb1 != 0) return mpfps->mpfb1; /* return default configuration type */ #endif /* TEST_DEFAULT_CONFIG */ if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; apic = bus = intr = 0; cpu = 1; /* pre-count the BSP */ while (count--) { switch (type = *(u_char *) position) { case 0: if (processor_entry(position, cpu)) ++cpu; break; case 1: if (bus_entry(position, bus)) ++bus; break; case 2: if (io_apic_entry(position, apic)) ++apic; break; case 3: if (int_entry(position, intr)) ++intr; break; case 4: /* int_entry(position); */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char *) position += basetable_entry_types[type].length; } if (boot_cpu_id == -1) panic("NO BSP found!"); /* post scan cleanup */ fix_mp_table(); /* report fact that its NOT a default configuration */ return 0; } /* * parse an Intel MP specification table */ static void fix_mp_table(void) { int x; int id; int bus_0; int bus_pci; int num_pci_bus; /* * Fix mis-numbering of the PCI bus and its INT entries if the BIOS * did it wrong. The MP spec says that when more than 1 PCI bus * exists the BIOS must begin with bus entries for the PCI bus and use * actual PCI bus numbering. This implies that when only 1 PCI bus * exists the BIOS can choose to ignore this ordering, and indeed many * MP motherboards do ignore it. This causes a problem when the PCI * sub-system makes requests of the MP sub-system based on PCI bus * numbers. So here we look for the situation and renumber the * busses and associated INTs in an effort to "make it right". */ /* find bus 0, PCI bus, count the number of PCI busses */ for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_id == 0) { bus_0 = x; } if (bus_data[x].bus_type == PCI) { ++num_pci_bus; bus_pci = x; } } /* * bus_0 == slot of bus with ID of 0 * bus_pci == slot of last PCI bus encountered */ /* check the 1 PCI bus case for sanity */ if (num_pci_bus == 1) { /* if it is number 0 all is well */ if (bus_data[bus_pci].bus_id == 0) return; /* mis-numbered, swap with whichever bus uses slot 0 */ /* swap the bus entry types */ bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; bus_data[bus_0].bus_type = PCI; /* swap each relavant INTerrupt entry */ id = bus_data[bus_pci].bus_id; for (x = 0; x < nintrs; ++x) { if (io_apic_ints[x].src_bus_id == id) { io_apic_ints[x].src_bus_id = 0; } else if (io_apic_ints[x].src_bus_id == 0) { io_apic_ints[x].src_bus_id = id; } } } /* sanity check if more than 1 PCI bus */ else if (num_pci_bus > 1) { for (x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_type != PCI) continue; if (bus_data[x].bus_id >= num_pci_bus) panic("bad PCI bus numbering"); } } } static int processor_entry(proc_entry_ptr entry, int cpu) { /* check for usability */ if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) return 0; /* check for BSP flag */ if (entry->cpu_flags & PROCENTRY_FLAG_BP) { boot_cpu_id = entry->apic_id; CPU_TO_ID(0) = entry->apic_id; ID_TO_CPU(entry->apic_id) = 0; return 0; /* its already been counted */ } /* add another AP to list, if less than max number of CPUs */ else { CPU_TO_ID(cpu) = entry->apic_id; ID_TO_CPU(entry->apic_id) = cpu; return 1; } } static int bus_entry(bus_entry_ptr entry, int bus) { int x; char c, name[8]; /* encode the name into an index */ for (x = 0; x < 6; ++x) { if ((c = entry->bus_type[x]) == ' ') break; name[x] = c; } name[x] = '\0'; if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) panic("unknown bus type: '%s'", name); bus_data[bus].bus_id = entry->bus_id; bus_data[bus].bus_type = x; return 1; } static int io_apic_entry(io_apic_entry_ptr entry, int apic) { if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) return 0; IO_TO_ID(apic) = entry->apic_id; ID_TO_IO(entry->apic_id) = apic; return 1; } static int lookup_bus_type(char *name) { int x; for (x = 0; x < MAX_BUSTYPE; ++x) if (strcmp(bus_type_table[x].name, name) == 0) return bus_type_table[x].type; return UNKNOWN_BUSTYPE; } static int int_entry(int_entry_ptr entry, int intr) { io_apic_ints[intr].int_type = entry->int_type; io_apic_ints[intr].int_flags = entry->int_flags; io_apic_ints[intr].src_bus_id = entry->src_bus_id; io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; return 1; } static int apic_int_is_bus_type(int intr, int bus_type) { int bus; for (bus = 0; bus < mp_nbusses; ++bus) if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) && ((int) bus_data[bus].bus_type == bus_type)) return 1; return 0; } /* * Given a traditional ISA INT mask, return an APIC mask. */ u_int isa_apic_mask(u_int isa_mask) { int isa_irq; int apic_pin; #if defined(SKIP_IRQ15_REDIRECT) if (isa_mask == (1 << 15)) { printf("skipping ISA IRQ15 redirect\n"); return isa_mask; } #endif /* SKIP_IRQ15_REDIRECT */ isa_irq = ffs(isa_mask); /* find its bit position */ if (isa_irq == 0) /* doesn't exist */ return 0; --isa_irq; /* make it zero based */ apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ if (apic_pin == -1) return 0; return (1 << apic_pin); /* convert pin# to a mask */ } /* * Determine which APIC pin an ISA/EISA INT is attached to. */ #define INTTYPE(I) (io_apic_ints[(I)].int_type) #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) int isa_apic_pin(int isa_irq) { int intr; #if defined(SMP_TIMER_NC) if (isa_irq == 0) return -1; #endif /* SMP_TIMER_NC */ for (intr = 0; intr < nintrs; ++intr) { /* check each record */ if (INTTYPE(intr) == 0) { /* standard INT */ if (SRCBUSIRQ(intr) == isa_irq) { if (apic_int_is_bus_type(intr, ISA) || apic_int_is_bus_type(intr, EISA)) return INTPIN(intr); /* found */ } } } return -1; /* NOT found */ } #undef SRCBUSIRQ /* * Determine which APIC pin a PCI INT is attached to. */ #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) int pci_apic_pin(int pciBus, int pciDevice, int pciInt) { int intr; --pciInt; /* zero based */ for (intr = 0; intr < nintrs; ++intr) /* check each record */ if ((INTTYPE(intr) == 0) /* standard INT */ && (SRCBUSID(intr) == pciBus) && (SRCBUSDEVICE(intr) == pciDevice) && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ if (apic_int_is_bus_type(intr, PCI)) return INTPIN(intr); /* exact match */ return -1; /* NOT found */ } #undef SRCBUSLINE #undef SRCBUSDEVICE #undef SRCBUSID #undef INTPIN #undef INTTYPE /* * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. * * XXX FIXME: * Exactly what this means is unclear at this point. It is a solution * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard * could route any of the ISA INTs to upper (>15) IRQ values. But most would * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an * option. */ int undirect_isa_irq(int rirq) { #if defined(READY) printf("Freeing redirected ISA irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); return 0; #endif /* READY */ } /* * Reprogram the MB chipset to NOT redirect a PCI INTerrupt */ int undirect_pci_irq(int rirq) { #if defined(READY) if (bootverbose) printf("Freeing redirected PCI irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else if (bootverbose) printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); return 0; #endif /* READY */ } /* * given a bus ID, return: * the bus type if found * -1 if NOT found */ int apic_bus_type(int id) { int x; for (x = 0; x < mp_nbusses; ++x) if (bus_data[x].bus_id == id) return bus_data[x].bus_type; return -1; } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus ID if found * -1 if NOT found */ int apic_src_bus_id(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_id); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus IRQ if found * -1 if NOT found */ int apic_src_bus_irq(int apic, int pin) { int x; for (x = 0; x < nintrs; x++) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_irq); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated INTerrupt type if found * -1 if NOT found */ int apic_int_type(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_type); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated trigger mode if found * -1 if NOT found */ int apic_trigger(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return ((io_apic_ints[x].int_flags >> 2) & 0x03); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated 'active' level if found * -1 if NOT found */ int apic_polarity(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_flags & 0x03); return -1; /* NOT found */ } /* * set data according to MP defaults * FIXME: probably not complete yet... */ static void default_mp_table(int type) { int ap_cpu_id; #if defined(APIC_IO) u_int32_t ux; int io_apic_id; int pin; #endif /* APIC_IO */ #if 0 printf(" MP default config type: %d\n", type); switch (type) { case 1: printf(" bus: ISA, APIC: 82489DX\n"); break; case 2: printf(" bus: EISA, APIC: 82489DX\n"); break; case 3: printf(" bus: EISA, APIC: 82489DX\n"); break; case 4: printf(" bus: MCA, APIC: 82489DX\n"); break; case 5: printf(" bus: ISA+PCI, APIC: Integrated\n"); break; case 6: printf(" bus: EISA+PCI, APIC: Integrated\n"); break; case 7: printf(" bus: MCA+PCI, APIC: Integrated\n"); break; default: printf(" future type\n"); break; /* NOTREACHED */ } #endif /* 0 */ boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; /* BSP */ CPU_TO_ID(0) = boot_cpu_id; ID_TO_CPU(boot_cpu_id) = 0; /* one and only AP */ CPU_TO_ID(1) = ap_cpu_id; ID_TO_CPU(ap_cpu_id) = 1; #if defined(APIC_IO) /* one and only IO APIC */ io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; /* * sanity check, refer to MP spec section 3.6.6, last paragraph * necessary as some hardware isn't properly setting up the IO APIC */ #if defined(REALLY_ANAL_IOAPICID_VALUE) if (io_apic_id != 2) { #else if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { #endif /* REALLY_ANAL_IOAPICID_VALUE */ ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ ux &= ~APIC_ID_MASK; /* clear the ID field */ ux |= 0x02000000; /* set it to '2' */ io_apic_write(0, IOAPIC_ID, ux); /* write new value */ ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ if ((ux & APIC_ID_MASK) != 0x02000000) panic("can't control IO APIC ID, reg: 0x%08x", ux); io_apic_id = 2; } IO_TO_ID(0) = io_apic_id; ID_TO_IO(io_apic_id) = 0; #endif /* APIC_IO */ /* fill out bus entries */ switch (type) { case 1: case 2: case 3: case 5: case 6: bus_data[0].bus_id = default_data[type - 1][1]; bus_data[0].bus_type = default_data[type - 1][2]; bus_data[1].bus_id = default_data[type - 1][3]; bus_data[1].bus_type = default_data[type - 1][4]; break; /* case 4: case 7: MCA NOT supported */ default: /* illegal/reserved */ panic("BAD default MP config: %d", type); /* NOTREACHED */ } #if defined(APIC_IO) /* general cases from MP v1.4, table 5-2 */ for (pin = 0; pin < 16; ++pin) { io_apic_ints[pin].int_type = 0; io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ io_apic_ints[pin].src_bus_id = 0; io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ io_apic_ints[pin].dst_apic_id = io_apic_id; io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ } /* special cases from MP v1.4, table 5-2 */ if (type == 2) { io_apic_ints[2].int_type = 0xff; /* N/C */ io_apic_ints[13].int_type = 0xff; /* N/C */ #if !defined(APIC_MIXED_MODE) /** FIXME: ??? */ panic("sorry, can't support type 2 default yet"); #endif /* APIC_MIXED_MODE */ } else io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ if (type == 7) io_apic_ints[0].int_type = 0xff; /* N/C */ else io_apic_ints[0].int_type = 3; /* vectored 8259 */ #endif /* APIC_IO */ } /* * start each AP in our list */ static int start_all_aps(u_int boot_addr) { int x, i; u_char mpbiosreason; u_long mpbioswarmvec; pd_entry_t newptd; pt_entry_t newpt; int *newpp; POSTCODE(START_ALL_APS_POST); /** * NOTE: this needs further thought: * where does it get released? * should it be set to empy? * * get the initial mp_lock with a count of 1 for the BSP */ mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ /* initialize BSP's local APIC */ apic_initialize(); /* install the AP 1st level boot code */ install_ap_tramp(boot_addr); /* save the current value of the warm-start vector */ mpbioswarmvec = *((u_long *) WARMBOOT_OFF); outb(CMOS_REG, BIOS_RESET); mpbiosreason = inb(CMOS_DATA); /* record BSP in CPU map */ all_cpus = 1; /* start each AP */ for (x = 1; x <= mp_naps; ++x) { /* HACK HACK HACK !!! */ /* alloc new page table directory */ newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* clone currently active one (ie: IdlePTD) */ bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ /* set up 0 -> 4MB P==V mapping for AP boot */ newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); /* store PTD for this AP */ bootPTD = (pd_entry_t)vtophys(newptd); /* alloc new page table page */ newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* set the new PTD's private page to point there */ newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); /* install self referential entry */ newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); /* get a new private data page */ newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); /* wire it into the private page table page */ newpt[0] = PG_V | PG_RW | vtophys(newpp); /* wire the ptp into itself for access */ newpt[1] = PG_V | PG_RW | vtophys(newpt); /* and the local apic */ newpt[2] = SMP_prvpt[2]; /* and the IO apic mapping[s] */ for (i = 16; i < 32; i++) newpt[i] = SMP_prvpt[i]; /* prime data page for it to use */ newpp[0] = x; /* cpuid */ newpp[1] = 0; /* curproc */ newpp[2] = 0; /* curpcb */ newpp[3] = 0; /* npxproc */ newpp[4] = 0; /* runtime.tv_sec */ newpp[5] = 0; /* runtime.tv_usec */ newpp[6] = x << 24; /* cpu_lockid */ /* XXX NOTE: ABANDON bootPTD for now!!!! */ /* END REVOLTING HACKERY */ /* setup a vector to our boot code */ *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ /* attempt to start the Application Processor */ CHECK_INIT(99); /* setup checkpoints */ if (!start_ap(x, boot_addr)) { printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); CHECK_PRINT("trace"); /* show checkpoints */ /* better panic as the AP may be running loose */ printf("panic y/n? [y] "); if (cngetc() != 'n') panic("bye-bye"); } CHECK_PRINT("trace"); /* show checkpoints */ /* record its version info */ cpu_apic_versions[x] = cpu_apic_versions[0]; all_cpus |= (1 << x); /* record AP in CPU map */ } /* build our map of 'other' CPUs */ other_cpus = all_cpus & ~(1 << cpuid); /* fill in our (BSP) APIC version */ cpu_apic_versions[0] = lapic.version; /* restore the warmstart vector */ *(u_long *) WARMBOOT_OFF = mpbioswarmvec; outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, mpbiosreason); pmap_set_opt_bsp(); /* number of APs actually started */ return mp_ncpus - 1; } /* * load the 1st level AP boot code into base memory. */ /* targets for relocation */ extern void bigJump(void); extern void bootCodeSeg(void); extern void bootDataSeg(void); extern void MPentry(void); extern u_int MP_GDT; extern u_int mp_gdtbase; static void install_ap_tramp(u_int boot_addr) { int x; int size = *(int *) ((u_long) & bootMP_size); u_char *src = (u_char *) ((u_long) bootMP); u_char *dst = (u_char *) boot_addr + KERNBASE; u_int boot_base = (u_int) bootMP; u_int8_t *dst8; u_int16_t *dst16; u_int32_t *dst32; POSTCODE(INSTALL_AP_TRAMP_POST); for (x = 0; x < size; ++x) *dst++ = *src++; /* * modify addresses in code we just moved to basemem. unfortunately we * need fairly detailed info about mpboot.s for this to work. changes * to mpboot.s might require changes here. */ /* boot code is located in KERNEL space */ dst = (u_char *) boot_addr + KERNBASE; /* modify the lgdt arg */ dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); /* modify the ljmp target for MPentry() */ dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); *dst32 = ((u_int) MPentry - KERNBASE); /* modify the target for boot code segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; /* modify the target for boot data segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; } /* * this function starts the AP (application processor) identified * by the APIC ID 'physicalCpu'. It does quite a "song and dance" * to accomplish this. This is necessary because of the nuances * of the different hardware we might encounter. It ain't pretty, * but it seems to work. */ static int start_ap(int logical_cpu, u_int boot_addr) { int physical_cpu; int vector; int cpus; u_long icr_lo, icr_hi; POSTCODE(START_AP_POST); /* get the PHYSICAL APIC ID# */ physical_cpu = CPU_TO_ID(logical_cpu); /* calculate the vector */ vector = (boot_addr >> 12) & 0xff; /* used as a watchpoint to signal AP startup */ cpus = mp_ncpus; /* * first we do an INIT/RESET IPI this INIT IPI might be run, reseting * and running the target CPU. OR this INIT IPI might be latched (P5 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be * ignored. */ /* setup the address for the target AP */ icr_hi = lapic.icr_hi & ~APIC_ID_MASK; icr_hi |= (physical_cpu << 24); lapic.icr_hi = icr_hi; /* do an INIT IPI: assert RESET */ icr_lo = lapic.icr_lo & 0xfff00000; lapic.icr_lo = icr_lo | 0x0000c500; /* wait for pending status end */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* do an INIT IPI: deassert RESET */ lapic.icr_lo = icr_lo | 0x00008500; /* wait for pending status end */ u_sleep(10000); /* wait ~10mS */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* * next we do a STARTUP IPI: the previous INIT IPI might still be * latched, (P5 bug) this 1st STARTUP would then terminate * immediately, and the previously started INIT IPI would continue. OR * the previous INIT IPI has already run. and this STARTUP IPI will * run. OR the previous INIT IPI was ignored. and this STARTUP IPI * will run. */ /* do a STARTUP IPI */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is * recognized after hardware RESET or INIT IPI. */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* wait for it to start */ set_apic_timer(5000000);/* == 5 seconds */ while (read_apic_timer()) if (mp_ncpus > cpus) return 1; /* return SUCCESS */ return 0; /* return FAILURE */ } /* * Flush the TLB on all other CPU's * * XXX: Needs to handshake and wait for completion before proceding. */ void smp_invltlb(void) { #if defined(APIC_IO) if (smp_active && invltlb_ok) all_but_self_ipi(XINVLTLB_OFFSET); #endif /* APIC_IO */ } void invlpg(u_int addr) { __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); /* send a message to the other CPUs */ smp_invltlb(); } void invltlb(void) { u_long temp; /* * This should be implemented as load_cr3(rcr3()) when load_cr3() is * inlined. */ __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); /* send a message to the other CPUs */ smp_invltlb(); } -#if defined(TEST_CPUSTOP) - -#if defined(DEBUG_CPUSTOP) -void db_printf __P((const char *fmt, ...)); -#endif /* DEBUG_CPUSTOP */ - /* * When called the executing CPU will send an IPI to all other CPUs * requesting that they halt execution. * * Usually (but not necessarily) called with 'other_cpus' as its arg. * * - Signals all CPUs in map to stop. * - Waits for each to stop. * * Returns: * -1: error * 0: NA * 1: ok * * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs * from executing at same time. */ int stop_cpus( u_int map ) { if (!smp_active) return 0; /* send IPI to all CPUs in map */ -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); -#endif /* DEBUG_CPUSTOP */ - stopped_cpus = 0; /* send the Xcpustop IPI to all CPUs in map */ selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); -#if defined(DEBUG_CPUSTOP) - db_printf(" spin\n"); -#endif /* DEBUG_CPUSTOP */ - while (stopped_cpus != map) /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" spun\nstopped\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } /* * Called by a CPU to restart stopped CPUs. * * Usually (but not necessarily) called with 'stopped_cpus' as its arg. * * - Signals all CPUs in map to restart. * - Waits for each to restart. * * Returns: * -1: error * 0: NA * 1: ok */ int restart_cpus( u_int map ) { if (!smp_active) return 0; -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", - cpuid, map, stopped_cpus); -#endif /* DEBUG_CPUSTOP */ - started_cpus = map; /* signal other cpus to restart */ while (started_cpus) /* wait for each to clear its bit */ /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" restarted\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } - -#endif /** TEST_CPUSTOP */ Index: head/sys/i386/include/smptests.h =================================================================== --- head/sys/i386/include/smptests.h (revision 27516) +++ head/sys/i386/include/smptests.h (revision 27517) @@ -1,201 +1,204 @@ /* * Copyright (c) 1996, by Steve Passe * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. The name of the developer may NOT be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: smptests.h,v 1.10 1997/07/15 03:27:12 fsmp Exp $ + * $Id: smptests.h,v 1.15 1997/07/18 19:47:48 smp Exp smp $ */ #ifndef _MACHINE_SMPTESTS_H_ #define _MACHINE_SMPTESTS_H_ /* * various 'tests in progress' */ /* - * address of POST hardware port + * Address of POST hardware port. + * Defining this enables POSTCODE macros. * #define POST_ADDR 0x80 */ /* * Use non 'ExtInt' method of external (non-conected) 8254 timer * See "Intel I486 Microprocessors and Related Products", page 4-292: * 82489DX/8259A DUAL MODE CONNECTION * */ #define TEST_ALTTIMER /* - * send 8254 timer INTs to all CPUs in LOPRIO mode + * Send 8254 timer INTs to all CPUs in LOPRIO mode. * */ #define TIMER_ALL /* - * IPI for stop/restart of other CPUs + * Send CPUSTOP IPI for stop/restart of other CPUs on DDB break. * -#define COUNT_CSHITS -#define DEBUG_CPUSTOP */ -#define TEST_CPUSTOP +#define CPUSTOP_ON_DDBBREAK +#define VERBOSE_CPUSTOP_ON_DDBBREAK /* * Bracket code/comments relevant to the current 'giant lock' model. * Everything is now the 'giant lock' model, but we will use this as * we start to "push down" the lock. */ #define GIANT_LOCK /* * use 'lowest priority' for sending IRQs to CPUs * * i386/i386/mplock.s, i386/i386/mpapic.c, kern/init_main.c * */ #define TEST_LOPRIO /* * deal with broken smp_idleloop() */ #define IGNORE_IDLEPROCS /* * misc. counters * #define COUNT_XINVLTLB_HITS #define COUNT_SPURIOUS_INTS +#define COUNT_CSHITS */ /** * hack to "fake-out" kernel into thinking it is running on a 'default config' * * value == default type #define TEST_DEFAULT_CONFIG 6 */ /* * simple test code for IPI interaction, save for future... * #define TEST_TEST1 #define IPI_TARGET_TEST1 1 */ /* * POST hardware macros. */ #ifdef POST_ADDR #define ASMPOSTCODE_INC \ pushl %eax ; \ movl _current_postcode, %eax ; \ incl %eax ; \ andl $0xff, %eax ; \ movl %eax, _current_postcode ; \ outb %al, $POST_ADDR ; \ popl %eax /* * Overwrite the current_postcode value. */ #define ASMPOSTCODE(X) \ pushl %eax ; \ movl $X, %eax ; \ movl %eax, _current_postcode ; \ outb %al, $POST_ADDR ; \ popl %eax /* * Overwrite the current_postcode low nibble. */ #define ASMPOSTCODE_LO(X) \ pushl %eax ; \ movl _current_postcode, %eax ; \ andl $0xf0, %eax ; \ orl $X, %eax ; \ movl %eax, _current_postcode ; \ outb %al, $POST_ADDR ; \ popl %eax /* * Overwrite the current_postcode high nibble. */ #define ASMPOSTCODE_HI(X) \ pushl %eax ; \ movl _current_postcode, %eax ; \ andl $0x0f, %eax ; \ orl $(X<<4), %eax ; \ movl %eax, _current_postcode ; \ outb %al, $POST_ADDR ; \ popl %eax #else #define ASMPOSTCODE_INC #define ASMPOSTCODE(X) #define ASMPOSTCODE_LO(X) #define ASMPOSTCODE_HI(X) #endif /* POST_ADDR */ /* - * these are all temps for debugging CPUSTOP code in mplock.s - * they will (hopefully) go away soon... + * these are all temps for debugging... * #define GUARD_INTS */ +/* + * This macro traps unexpected INTs to a specific CPU, eg. GUARD_CPU. + */ #ifdef GUARD_INTS #define GUARD_CPU 1 #define MAYBE_PANIC(irq_num) \ cmpl $GUARD_CPU, _cpuid ; \ jne 9f ; \ cmpl $1, _ok_test1 ; \ jne 9f ; \ pushl lapic_isr3 ; \ pushl lapic_isr2 ; \ pushl lapic_isr1 ; \ pushl lapic_isr0 ; \ pushl lapic_irr3 ; \ pushl lapic_irr2 ; \ pushl lapic_irr1 ; \ pushl lapic_irr0 ; \ pushl $irq_num ; \ pushl _cpuid ; \ pushl $panic_msg ; \ call _printf ; \ addl $44, %esp ; \ 9: #else #define MAYBE_PANIC(irq_num) #endif /* GUARD_INTS */ #endif /* _MACHINE_SMPTESTS_H_ */ Index: head/sys/i386/isa/apic_vector.s =================================================================== --- head/sys/i386/isa/apic_vector.s (revision 27516) +++ head/sys/i386/isa/apic_vector.s (revision 27517) @@ -1,431 +1,415 @@ /* * from: vector.s, 386BSD 0.1 unknown origin - * $Id: apic_vector.s,v 1.7 1997/07/15 02:49:21 fsmp Exp $ + * $Id: apic_vector.s,v 1.12 1997/07/18 19:47:13 smp Exp smp $ */ -#include /** TEST_CPUSTOP */ +#include /** various counters */ +#include "i386/isa/intr_machdep.h" /* convert an absolute IRQ# into a bitmask */ #define IRQ_BIT(irq_num) (1 << (irq_num)) /* make an index into the IO APIC from the IRQ# */ #define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2)) /* * 'lazy masking' code suggested by Bruce Evans */ #define MAYBE_MASK_IRQ(irq_num) \ testl $IRQ_BIT(irq_num),iactive ; /* lazy masking */ \ je 1f ; /* NOT currently active */ \ orl $IRQ_BIT(irq_num),_imen ; /* set the mask bit */ \ movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ orl $IOART_INTMASK,%eax ; /* set the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ movl $0, lapic_eoi ; \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ popl %ds ; \ popal ; \ addl $4+4,%esp ; \ iret ; \ ; \ ALIGN_TEXT ; \ 1: ; \ orl $IRQ_BIT(irq_num),iactive #define MAYBE_UNMASK_IRQ(irq_num) \ cli ; /* must unmask _imen and icu atomically */ \ andl $~IRQ_BIT(irq_num),iactive ; \ testl $IRQ_BIT(irq_num),_imen ; \ je 2f ; \ andl $~IRQ_BIT(irq_num),_imen ; /* clear mask bit */ \ movl _ioapic,%ecx ; /* ioapic[0]addr */ \ movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \ movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \ andl $~IOART_INTMASK,%eax ; /* clear the mask */ \ movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */ \ 2: ; \ sti ; /* XXX _doreti repeats the cli/sti */ /* * Macros for interrupt interrupt entry, call to handler, and exit. */ #define FAST_INTR(irq_num, vec_name) \ .text ; \ SUPERALIGN_TEXT ; \ IDTVEC(vec_name) ; \ pushl %eax ; /* save only call-used registers */ \ pushl %ecx ; \ pushl %edx ; \ pushl %ds ; \ MAYBE_PUSHL_ES ; \ movl $KDSEL,%eax ; \ movl %ax,%ds ; \ MAYBE_MOVW_AX_ES ; \ FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \ GET_MPLOCK ; /* SMP Spin lock */ \ pushl _intr_unit + (irq_num) * 4 ; \ call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \ movl $0, lapic_eoi ; \ addl $4,%esp ; \ incl _cnt+V_INTR ; /* book-keeping can wait */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ incl (%eax) ; \ movl _cpl,%eax ; /* unmasking pending HWIs or SWIs? */ \ notl %eax ; \ andl _ipending,%eax ; \ jne 2f ; /* yes, maybe handle them */ \ 1: ; \ MEXITCOUNT ; \ REL_MPLOCK ; /* SMP release global lock */ \ MAYBE_POPL_ES ; \ popl %ds ; \ popl %edx ; \ popl %ecx ; \ popl %eax ; \ iret ; \ ; \ ALIGN_TEXT ; \ 2: ; \ cmpb $3,_intr_nesting_level ; /* enough stack? */ \ jae 1b ; /* no, return */ \ movl _cpl,%eax ; \ /* XXX next line is probably unnecessary now. */ \ movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \ incb _intr_nesting_level ; /* ... really limit it ... */ \ sti ; /* to do this as early as possible */ \ MAYBE_POPL_ES ; /* discard most of thin frame ... */ \ popl %ecx ; /* ... original %ds ... */ \ popl %edx ; \ xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \ pushal ; /* build fat frame (grrr) ... */ \ pushl %ecx ; /* ... actually %ds ... */ \ pushl %es ; \ movl $KDSEL,%eax ; \ movl %ax,%es ; \ movl (2+8+0)*4(%esp),%ecx ; /* %ecx from thin frame ... */ \ movl %ecx,(2+6)*4(%esp) ; /* ... to fat frame ... */ \ movl (2+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \ pushl %eax ; \ subl $4,%esp ; /* junk for unit number */ \ MEXITCOUNT ; \ jmp _doreti #define INTR(irq_num, vec_name) \ .text ; \ SUPERALIGN_TEXT ; \ IDTVEC(vec_name) ; \ pushl $0 ; /* dummy error code */ \ pushl $0 ; /* dummy trap type */ \ pushal ; \ pushl %ds ; /* save data and extra segments ... */ \ pushl %es ; \ movl $KDSEL,%eax ; /* ... and reload with kernel's ... */ \ movl %ax,%ds ; /* ... early for obsolete reasons */ \ movl %ax,%es ; \ GET_MPLOCK ; /* SMP Spin lock */ \ MAYBE_MASK_IRQ(irq_num) ; \ movl $0, lapic_eoi ; \ movl _cpl,%eax ; \ testl $IRQ_BIT(irq_num), %eax ; \ jne 3f ; \ incb _intr_nesting_level ; \ __CONCAT(Xresume,irq_num): ; \ FAKE_MCOUNT(12*4(%esp)) ; /* XXX late to avoid dbl cnt */ \ incl _cnt+V_INTR ; /* tally interrupts */ \ movl _intr_countp + (irq_num) * 4,%eax ; \ incl (%eax) ; \ movl _cpl,%eax ; \ pushl %eax ; \ pushl _intr_unit + (irq_num) * 4 ; \ orl _intr_mask + (irq_num) * 4,%eax ; \ movl %eax,_cpl ; \ sti ; \ call *_intr_handler + (irq_num) * 4 ; \ MAYBE_UNMASK_IRQ(irq_num) ; \ MEXITCOUNT ; \ jmp _doreti ; \ ; \ ALIGN_TEXT ; \ 3: ; \ /* XXX skip mcounting here to avoid double count */ \ orl $IRQ_BIT(irq_num), _ipending ; \ REL_MPLOCK ; /* SMP release global lock */ \ popl %es ; \ popl %ds ; \ popal ; \ addl $4+4,%esp ; \ iret /* * Handle "spurious INTerrupts". * Notes: * This is different than the "spurious INTerrupt" generated by an * 8259 PIC for missing INTs. See the APIC documentation for details. * This routine should NOT do an 'EOI' cycle. */ .text SUPERALIGN_TEXT .globl _Xspuriousint _Xspuriousint: #ifdef COUNT_SPURIOUS_INTS ss incl _sihits #endif /* No EOI cycle used here */ iret /* * Handle TLB shootdowns. */ .text SUPERALIGN_TEXT .globl _Xinvltlb _Xinvltlb: pushl %eax #ifdef COUNT_XINVLTLB_HITS ss movl _cpuid, %eax ss incl _xhits(,%eax,4) #endif /* COUNT_XINVLTLB_HITS */ movl %cr3, %eax /* invalidate the TLB */ movl %eax, %cr3 ss /* stack segment, avoid %ds load */ movl $0, lapic_eoi /* End Of Interrupt to APIC */ popl %eax iret -#ifdef TEST_CPUSTOP - -#include "i386/isa/intr_machdep.h" - /* * Executed by a CPU when it receives an Xcpustop IPI from another CPU, * * - Signals its receipt. * - Waits for permission to restart. * - Signals its restart. */ .text SUPERALIGN_TEXT .globl _Xcpustop _Xcpustop: pushl %eax pushl %ds /* save current data segment */ movl $KDSEL, %eax movl %ax, %ds /* use KERNEL data segment */ movl _cpuid, %eax #ifdef COUNT_CSHITS incl _cshits(,%eax,4) #endif /* COUNT_CSHITS */ ASMPOSTCODE_HI(0x1) lock btsl %eax, _stopped_cpus /* stopped_cpus |= (1< /* for KERNBASE */ #include #include #include #include #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include /* for KERNBASE */ #include #include #include #include #include #include #include -#include /** TEST_DEFAULT_CONFIG, TEST_CPUSTOP _TEST1 */ +#include /** TEST_DEFAULT_CONFIG, TEST_TEST1 */ #include #include #include /* cngetc() */ #if defined(APIC_IO) #include /* setidt() */ #include /* IPIs */ #include /* IPIs */ #endif /* APIC_IO */ #define WARMBOOT_TARGET 0 #define WARMBOOT_OFF (KERNBASE + 0x0467) #define WARMBOOT_SEG (KERNBASE + 0x0469) #define BIOS_BASE (0xf0000) #define BIOS_SIZE (0x10000) #define BIOS_COUNT (BIOS_SIZE/4) #define CMOS_REG (0x70) #define CMOS_DATA (0x71) #define BIOS_RESET (0x0f) #define BIOS_WARM (0x0a) #define PROCENTRY_FLAG_EN 0x01 #define PROCENTRY_FLAG_BP 0x02 #define IOAPICENTRY_FLAG_EN 0x01 /* MP Floating Pointer Structure */ typedef struct MPFPS { char signature[4]; void *pap; u_char length; u_char spec_rev; u_char checksum; u_char mpfb1; u_char mpfb2; u_char mpfb3; u_char mpfb4; u_char mpfb5; } *mpfps_t; /* MP Configuration Table Header */ typedef struct MPCTH { char signature[4]; u_short base_table_length; u_char spec_rev; u_char checksum; u_char oem_id[8]; u_char product_id[12]; void *oem_table_pointer; u_short oem_table_size; u_short entry_count; void *apic_address; u_short extended_table_length; u_char extended_table_checksum; u_char reserved; } *mpcth_t; typedef struct PROCENTRY { u_char type; u_char apic_id; u_char apic_version; u_char cpu_flags; u_long cpu_signature; u_long feature_flags; u_long reserved1; u_long reserved2; } *proc_entry_ptr; typedef struct BUSENTRY { u_char type; u_char bus_id; char bus_type[6]; } *bus_entry_ptr; typedef struct IOAPICENTRY { u_char type; u_char apic_id; u_char apic_version; u_char apic_flags; void *apic_address; } *io_apic_entry_ptr; typedef struct INTENTRY { u_char type; u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } *int_entry_ptr; /* descriptions of MP basetable entries */ typedef struct BASETABLE_ENTRY { u_char type; u_char length; char name[16]; } basetable_entry; /* * this code MUST be enabled here and in mpboot.s. * it follows the very early stages of AP boot by placing values in CMOS ram. * it NORMALLY will never be needed and thus the primitive method for enabling. * #define CHECK_POINTS */ #if defined(CHECK_POINTS) #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) #define CHECK_INIT(D); \ CHECK_WRITE(0x34, (D)); \ CHECK_WRITE(0x35, (D)); \ CHECK_WRITE(0x36, (D)); \ CHECK_WRITE(0x37, (D)); \ CHECK_WRITE(0x38, (D)); \ CHECK_WRITE(0x39, (D)); #define CHECK_PRINT(S); \ printf("%s: %d, %d, %d, %d, %d, %d\n", \ (S), \ CHECK_READ(0x34), \ CHECK_READ(0x35), \ CHECK_READ(0x36), \ CHECK_READ(0x37), \ CHECK_READ(0x38), \ CHECK_READ(0x39)); #else /* CHECK_POINTS */ #define CHECK_INIT(D) #define CHECK_PRINT(S) #endif /* CHECK_POINTS */ /* * Values to send to the POST hardware. */ #define MP_BOOTADDRESS_POST 0x10 #define MP_PROBE_POST 0x11 #define MP_START_POST 0x12 #define MP_ANNOUNCE_POST 0x13 #define MPTABLE_PASS1_POST 0x14 #define MPTABLE_PASS2_POST 0x15 #define MP_ENABLE_POST 0x16 #define START_ALL_APS_POST 0x17 #define INSTALL_AP_TRAMP_POST 0x18 #define START_AP_POST 0x19 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */ int current_postcode; /** XXX FIXME: what system files declare these??? */ extern struct region_descriptor r_gdt, r_idt; int mp_ncpus; /* # of CPUs, including BSP */ int mp_naps; /* # of Applications processors */ int mp_nbusses; /* # of busses */ int mp_napics; /* # of IO APICs */ int boot_cpu_id; /* designated BSP */ vm_offset_t cpu_apic_address; vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */ u_int32_t cpu_apic_versions[NCPU]; u_int32_t io_apic_versions[NAPIC]; /* * APIC ID logical/physical mapping structures. * We oversize these to simplify boot-time config. */ int cpu_num_to_apic_id[NAPICID]; int io_num_to_apic_id[NAPICID]; int apic_id_to_logical[NAPICID]; /* Bitmap of all available CPUs */ u_int all_cpus; /* Boot of AP uses this PTD */ u_int *bootPTD; /* Hotwire a 0->4MB V==P mapping */ extern pt_entry_t KPTphys; /* Virtual address of per-cpu common_tss */ extern struct i386tss common_tss; /* * Local data and functions. */ static int mp_capable; static u_int boot_address; static u_int base_memory; static int picmode; /* 0: virtual wire mode, 1: PIC mode */ static mpfps_t mpfps; static int search_for_sig(u_int32_t target, int count); static void mp_enable(u_int boot_addr); static int mptable_pass1(void); static int mptable_pass2(void); static void default_mp_table(int type); static int start_all_aps(u_int boot_addr); static void install_ap_tramp(u_int boot_addr); static int start_ap(int logicalCpu, u_int boot_addr); /* * Calculate usable address in base memory for AP trampoline code. */ u_int mp_bootaddress(u_int basemem) { POSTCODE(MP_BOOTADDRESS_POST); base_memory = basemem * 1024; /* convert to bytes */ boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ if ((base_memory - boot_address) < bootMP_size) boot_address -= 4096; /* not enough, lower by 4k */ return boot_address; } /* * Look for an Intel MP spec table (ie, SMP capable hardware). */ int mp_probe(void) { int x; u_long segment; u_int32_t target; POSTCODE(MP_PROBE_POST); /* see if EBDA exists */ if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { /* search first 1K of EBDA */ target = (u_int32_t) (segment << 4); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } else { /* last 1K of base memory, effective 'top of base' passed in */ target = (u_int32_t) (base_memory - 0x400); if ((x = search_for_sig(target, 1024 / 4)) >= 0) goto found; } /* search the BIOS */ target = (u_int32_t) BIOS_BASE; if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) goto found; /* nothing found */ mpfps = (mpfps_t)0; mp_capable = 0; return 0; found: /* calculate needed resources */ mpfps = (mpfps_t)x; if (mptable_pass1()) panic("you must reconfigure your kernel"); /* flag fact that we are running multiple processors */ mp_capable = 1; return 1; } /* * Startup the SMP processors. */ void mp_start(void) { POSTCODE(MP_START_POST); /* look for MP capable motherboard */ if (mp_capable) mp_enable(boot_address); else panic("MP hardware not found!"); } /* * Print various information about the SMP system hardware and setup. */ void mp_announce(void) { int x; POSTCODE(MP_ANNOUNCE_POST); printf("FreeBSD/SMP: Multiprocessor motherboard\n"); printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0)); printf(", version: 0x%08x", cpu_apic_versions[0]); printf(", at 0x%08x\n", cpu_apic_address); for (x = 1; x <= mp_naps; ++x) { printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); printf(", version: 0x%08x", cpu_apic_versions[x]); printf(", at 0x%08x\n", cpu_apic_address); } #if defined(APIC_IO) for (x = 0; x < mp_napics; ++x) { printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x)); printf(", version: 0x%08x", io_apic_versions[x]); printf(", at 0x%08x\n", io_apic_address[x]); } #else printf(" Warning: APIC I/O disabled\n"); #endif /* APIC_IO */ } /* * AP cpu's call this to sync up protected mode. */ void init_secondary(void) { int gsel_tss, slot; r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; r_gdt.rd_base = (int) gdt; lgdt(&r_gdt); /* does magic intra-segment return */ lidt(&r_idt); lldt(_default_ldt); slot = NGDT + cpuid; gsel_tss = GSEL(slot, SEL_KPL); gdt[slot].sd.sd_type = SDT_SYS386TSS; common_tss.tss_esp0 = 0; /* not used until after switch */ common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); common_tss.tss_ioopt = (sizeof common_tss) << 16; ltr(gsel_tss); load_cr0(0x8005003b); /* XXX! */ PTD[0] = 0; pmap_set_opt((unsigned *)PTD); invltlb(); } #if defined(APIC_IO) /* * Final configuration of the BSP's local APIC: * - disable 'pic mode'. * - disable 'virtual wire mode'. * - enable NMI. */ void bsp_apic_configure(void) { u_char byte; u_int32_t temp; /* leave 'pic mode' if necessary */ if (picmode) { outb(0x22, 0x70); /* select IMCR */ byte = inb(0x23); /* current contents */ byte |= 0x01; /* mask external INTR */ outb(0x23, byte); /* disconnect 8259s/NMI */ } /* mask lint0 (the 8259 'virtual wire' connection) */ temp = lapic.lvt_lint0; temp |= APIC_LVT_M; /* set the mask */ lapic.lvt_lint0 = temp; /* setup lint1 to handle NMI */ temp = lapic.lvt_lint1; temp &= ~APIC_LVT_M; /* clear the mask */ lapic.lvt_lint1 = temp; if (bootverbose) apic_dump(); } #endif /* APIC_IO */ /******************************************************************* * local functions and data */ /* * start the SMP system */ static void mp_enable(u_int boot_addr) { int x; #if defined(APIC_IO) int apic; u_int ux; #endif /* APIC_IO */ POSTCODE(MP_ENABLE_POST); /* turn on 4MB of V == P addressing so we can get to MP table */ *(int *)PTD = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); invltlb(); /* examine the MP table for needed info, uses physical addresses */ x = mptable_pass2(); *(int *)PTD = 0; invltlb(); /* can't process default configs till the CPU APIC is pmapped */ if (x) default_mp_table(x); #if defined(APIC_IO) /* fill the LOGICAL io_apic_versions table */ for (apic = 0; apic < mp_napics; ++apic) { ux = io_apic_read(apic, IOAPIC_VER); io_apic_versions[apic] = ux; } /* program each IO APIC in the system */ for (apic = 0; apic < mp_napics; ++apic) if (io_apic_setup(apic) < 0) panic("IO APIC setup failure"); /* install a 'Spurious INTerrupt' vector */ setidt(XSPURIOUSINT_OFFSET, Xspuriousint, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); /* install an inter-CPU IPI for TLB invalidation */ setidt(XINVLTLB_OFFSET, Xinvltlb, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#if defined(TEST_CPUSTOP) /* install an inter-CPU IPI for CPU stop/restart */ setidt(XCPUSTOP_OFFSET, Xcpustop, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); -#endif /** TEST_CPUSTOP */ #if defined(TEST_TEST1) - /* install a 'Spurious INTerrupt' vector */ + /* install a "fake hardware INTerrupt" vector */ setidt(XTEST1_OFFSET, Xtest1, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); #endif /** TEST_TEST1 */ #endif /* APIC_IO */ /* start each Application Processor */ start_all_aps(boot_addr); /* * The init process might be started on a different CPU now, * and the boot CPU might not call prepare_usermode to get * cr0 correctly configured. Thus we initialize cr0 here. */ load_cr0(rcr0() | CR0_WP | CR0_AM); } /* * look for the MP spec signature */ /* string defined by the Intel MP Spec as identifying the MP table */ #define MP_SIG 0x5f504d5f /* _MP_ */ #define NEXT(X) ((X) += 4) static int search_for_sig(u_int32_t target, int count) { int x; u_int32_t *addr = (u_int32_t *) (KERNBASE + target); for (x = 0; x < count; NEXT(x)) if (addr[x] == MP_SIG) /* make array index a byte index */ return (target + (x * sizeof(u_int32_t))); return -1; } static basetable_entry basetable_entry_types[] = { {0, 20, "Processor"}, {1, 8, "Bus"}, {2, 8, "I/O APIC"}, {3, 8, "I/O INT"}, {4, 8, "Local INT"} }; typedef struct BUSDATA { u_char bus_id; enum busTypes bus_type; } bus_datum; typedef struct INTDATA { u_char int_type; u_short int_flags; u_char src_bus_id; u_char src_bus_irq; u_char dst_apic_id; u_char dst_apic_int; } io_int, local_int; typedef struct BUSTYPENAME { u_char type; char name[7]; } bus_type_name; static bus_type_name bus_type_table[] = { {CBUS, "CBUS"}, {CBUSII, "CBUSII"}, {EISA, "EISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {ISA, "ISA"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {PCI, "PCI"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {UNKNOWN_BUSTYPE, "---"}, {XPRESS, "XPRESS"}, {UNKNOWN_BUSTYPE, "---"} }; /* from MP spec v1.4, table 5-1 */ static int default_data[7][5] = { /* nbus, id0, type0, id1, type1 */ {1, 0, ISA, 255, 255}, {1, 0, EISA, 255, 255}, {1, 0, EISA, 255, 255}, {0, 255, 255, 255, 255},/* MCA not supported */ {2, 0, ISA, 1, PCI}, {2, 0, EISA, 1, PCI}, {0, 255, 255, 255, 255} /* MCA not supported */ }; /* the bus data */ bus_datum bus_data[NBUS]; /* the IO INT data, one entry per possible APIC INTerrupt */ io_int io_apic_ints[NINTR]; static int nintrs; static void fix_mp_table __P((void)); static int processor_entry __P((proc_entry_ptr entry, int cpu)); static int bus_entry __P((bus_entry_ptr entry, int bus)); static int io_apic_entry __P((io_apic_entry_ptr entry, int apic)); static int int_entry __P((int_entry_ptr entry, int intr)); static int lookup_bus_type __P((char *name)); /* * 1st pass on motherboard's Intel MP specification table. * * initializes: * mp_ncpus = 1 * * determines: * cpu_apic_address (common to all CPUs) * io_apic_address[N] * mp_naps * mp_nbusses * mp_napics * nintrs */ static int mptable_pass1(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int mustpanic; POSTCODE(MPTABLE_PASS1_POST); mustpanic = 0; /* clear various tables */ for (x = 0; x < NAPICID; ++x) { io_apic_address[x] = ~0; /* IO APIC address table */ } /* init everything to empty */ mp_naps = 0; mp_nbusses = 0; mp_napics = 0; nintrs = 0; /* check for use of 'default' configuration */ if (mpfps->mpfb1 != 0) { /* use default addresses */ cpu_apic_address = DEFAULT_APIC_BASE; io_apic_address[0] = DEFAULT_IO_APIC_BASE; /* fill in with defaults */ mp_naps = 2; /* includes BSP */ mp_nbusses = default_data[mpfps->mpfb1 - 1][0]; #if defined(APIC_IO) mp_napics = 1; nintrs = 16; #endif /* APIC_IO */ } else { if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); cpu_apic_address = (vm_offset_t) cth->apic_address; /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; while (count--) { switch (type = *(u_char *) position) { case 0: /* processor_entry */ if (((proc_entry_ptr)position)->cpu_flags & PROCENTRY_FLAG_EN) ++mp_naps; break; case 1: /* bus_entry */ ++mp_nbusses; break; case 2: /* io_apic_entry */ if (((io_apic_entry_ptr)position)->apic_flags & IOAPICENTRY_FLAG_EN) io_apic_address[mp_napics++] = (vm_offset_t)((io_apic_entry_ptr) position)->apic_address; break; case 3: /* int_entry */ ++nintrs; break; case 4: /* int_entry */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char*)position += basetable_entry_types[type].length; } } /* qualify the numbers */ if (mp_naps > NCPU) printf("Warning: only using %d of %d available CPUs!\n", NCPU, mp_naps); #if 0 /** XXX we consider this legal now (but should we?) */ mustpanic = 1; #endif if (mp_nbusses > NBUS) { printf("found %d busses, increase NBUS\n", mp_nbusses); mustpanic = 1; } if (mp_napics > NAPIC) { printf("found %d apics, increase NAPIC\n", mp_napics); mustpanic = 1; } if (nintrs > NINTR) { printf("found %d intrs, increase NINTR\n", nintrs); mustpanic = 1; } /* * Count the BSP. * This is also used as a counter while starting the APs. */ mp_ncpus = 1; --mp_naps; /* subtract the BSP */ return mustpanic; } /* * 2nd pass on motherboard's Intel MP specification table. * * sets: * boot_cpu_id * ID_TO_IO(N), phy APIC ID to log CPU/IO table * CPU_TO_ID(N), logical CPU to APIC ID table * IO_TO_ID(N), logical IO to APIC ID table * bus_data[N] * io_apic_ints[N] */ static int mptable_pass2(void) { int x; mpcth_t cth; int totalSize; void* position; int count; int type; int apic, bus, cpu, intr; POSTCODE(MPTABLE_PASS2_POST); /* clear various tables */ for (x = 0; x < NAPICID; ++x) { ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */ CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */ IO_TO_ID(x) = -1; /* logical IO to APIC ID table */ } /* clear bus data table */ for (x = 0; x < NBUS; ++x) bus_data[x].bus_id = 0xff; /* clear IO APIC INT table */ for (x = 0; x < NINTR; ++x) io_apic_ints[x].int_type = 0xff; /* setup the cpu/apic mapping arrays */ boot_cpu_id = -1; /* record whether PIC or virtual-wire mode */ picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0; /* check for use of 'default' configuration */ #if defined(TEST_DEFAULT_CONFIG) return TEST_DEFAULT_CONFIG; #else if (mpfps->mpfb1 != 0) return mpfps->mpfb1; /* return default configuration type */ #endif /* TEST_DEFAULT_CONFIG */ if ((cth = mpfps->pap) == 0) panic("MP Configuration Table Header MISSING!"); /* walk the table, recording info of interest */ totalSize = cth->base_table_length - sizeof(struct MPCTH); position = (u_char *) cth + sizeof(struct MPCTH); count = cth->entry_count; apic = bus = intr = 0; cpu = 1; /* pre-count the BSP */ while (count--) { switch (type = *(u_char *) position) { case 0: if (processor_entry(position, cpu)) ++cpu; break; case 1: if (bus_entry(position, bus)) ++bus; break; case 2: if (io_apic_entry(position, apic)) ++apic; break; case 3: if (int_entry(position, intr)) ++intr; break; case 4: /* int_entry(position); */ break; default: panic("mpfps Base Table HOSED!"); /* NOTREACHED */ } totalSize -= basetable_entry_types[type].length; (u_char *) position += basetable_entry_types[type].length; } if (boot_cpu_id == -1) panic("NO BSP found!"); /* post scan cleanup */ fix_mp_table(); /* report fact that its NOT a default configuration */ return 0; } /* * parse an Intel MP specification table */ static void fix_mp_table(void) { int x; int id; int bus_0; int bus_pci; int num_pci_bus; /* * Fix mis-numbering of the PCI bus and its INT entries if the BIOS * did it wrong. The MP spec says that when more than 1 PCI bus * exists the BIOS must begin with bus entries for the PCI bus and use * actual PCI bus numbering. This implies that when only 1 PCI bus * exists the BIOS can choose to ignore this ordering, and indeed many * MP motherboards do ignore it. This causes a problem when the PCI * sub-system makes requests of the MP sub-system based on PCI bus * numbers. So here we look for the situation and renumber the * busses and associated INTs in an effort to "make it right". */ /* find bus 0, PCI bus, count the number of PCI busses */ for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_id == 0) { bus_0 = x; } if (bus_data[x].bus_type == PCI) { ++num_pci_bus; bus_pci = x; } } /* * bus_0 == slot of bus with ID of 0 * bus_pci == slot of last PCI bus encountered */ /* check the 1 PCI bus case for sanity */ if (num_pci_bus == 1) { /* if it is number 0 all is well */ if (bus_data[bus_pci].bus_id == 0) return; /* mis-numbered, swap with whichever bus uses slot 0 */ /* swap the bus entry types */ bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; bus_data[bus_0].bus_type = PCI; /* swap each relavant INTerrupt entry */ id = bus_data[bus_pci].bus_id; for (x = 0; x < nintrs; ++x) { if (io_apic_ints[x].src_bus_id == id) { io_apic_ints[x].src_bus_id = 0; } else if (io_apic_ints[x].src_bus_id == 0) { io_apic_ints[x].src_bus_id = id; } } } /* sanity check if more than 1 PCI bus */ else if (num_pci_bus > 1) { for (x = 0; x < mp_nbusses; ++x) { if (bus_data[x].bus_type != PCI) continue; if (bus_data[x].bus_id >= num_pci_bus) panic("bad PCI bus numbering"); } } } static int processor_entry(proc_entry_ptr entry, int cpu) { /* check for usability */ if ((cpu >= NCPU) || !(entry->cpu_flags & PROCENTRY_FLAG_EN)) return 0; /* check for BSP flag */ if (entry->cpu_flags & PROCENTRY_FLAG_BP) { boot_cpu_id = entry->apic_id; CPU_TO_ID(0) = entry->apic_id; ID_TO_CPU(entry->apic_id) = 0; return 0; /* its already been counted */ } /* add another AP to list, if less than max number of CPUs */ else { CPU_TO_ID(cpu) = entry->apic_id; ID_TO_CPU(entry->apic_id) = cpu; return 1; } } static int bus_entry(bus_entry_ptr entry, int bus) { int x; char c, name[8]; /* encode the name into an index */ for (x = 0; x < 6; ++x) { if ((c = entry->bus_type[x]) == ' ') break; name[x] = c; } name[x] = '\0'; if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) panic("unknown bus type: '%s'", name); bus_data[bus].bus_id = entry->bus_id; bus_data[bus].bus_type = x; return 1; } static int io_apic_entry(io_apic_entry_ptr entry, int apic) { if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) return 0; IO_TO_ID(apic) = entry->apic_id; ID_TO_IO(entry->apic_id) = apic; return 1; } static int lookup_bus_type(char *name) { int x; for (x = 0; x < MAX_BUSTYPE; ++x) if (strcmp(bus_type_table[x].name, name) == 0) return bus_type_table[x].type; return UNKNOWN_BUSTYPE; } static int int_entry(int_entry_ptr entry, int intr) { io_apic_ints[intr].int_type = entry->int_type; io_apic_ints[intr].int_flags = entry->int_flags; io_apic_ints[intr].src_bus_id = entry->src_bus_id; io_apic_ints[intr].src_bus_irq = entry->src_bus_irq; io_apic_ints[intr].dst_apic_id = entry->dst_apic_id; io_apic_ints[intr].dst_apic_int = entry->dst_apic_int; return 1; } static int apic_int_is_bus_type(int intr, int bus_type) { int bus; for (bus = 0; bus < mp_nbusses; ++bus) if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) && ((int) bus_data[bus].bus_type == bus_type)) return 1; return 0; } /* * Given a traditional ISA INT mask, return an APIC mask. */ u_int isa_apic_mask(u_int isa_mask) { int isa_irq; int apic_pin; #if defined(SKIP_IRQ15_REDIRECT) if (isa_mask == (1 << 15)) { printf("skipping ISA IRQ15 redirect\n"); return isa_mask; } #endif /* SKIP_IRQ15_REDIRECT */ isa_irq = ffs(isa_mask); /* find its bit position */ if (isa_irq == 0) /* doesn't exist */ return 0; --isa_irq; /* make it zero based */ apic_pin = isa_apic_pin(isa_irq); /* look for APIC connection */ if (apic_pin == -1) return 0; return (1 << apic_pin); /* convert pin# to a mask */ } /* * Determine which APIC pin an ISA/EISA INT is attached to. */ #define INTTYPE(I) (io_apic_ints[(I)].int_type) #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) int isa_apic_pin(int isa_irq) { int intr; #if defined(SMP_TIMER_NC) if (isa_irq == 0) return -1; #endif /* SMP_TIMER_NC */ for (intr = 0; intr < nintrs; ++intr) { /* check each record */ if (INTTYPE(intr) == 0) { /* standard INT */ if (SRCBUSIRQ(intr) == isa_irq) { if (apic_int_is_bus_type(intr, ISA) || apic_int_is_bus_type(intr, EISA)) return INTPIN(intr); /* found */ } } } return -1; /* NOT found */ } #undef SRCBUSIRQ /* * Determine which APIC pin a PCI INT is attached to. */ #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) int pci_apic_pin(int pciBus, int pciDevice, int pciInt) { int intr; --pciInt; /* zero based */ for (intr = 0; intr < nintrs; ++intr) /* check each record */ if ((INTTYPE(intr) == 0) /* standard INT */ && (SRCBUSID(intr) == pciBus) && (SRCBUSDEVICE(intr) == pciDevice) && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ if (apic_int_is_bus_type(intr, PCI)) return INTPIN(intr); /* exact match */ return -1; /* NOT found */ } #undef SRCBUSLINE #undef SRCBUSDEVICE #undef SRCBUSID #undef INTPIN #undef INTTYPE /* * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. * * XXX FIXME: * Exactly what this means is unclear at this point. It is a solution * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard * could route any of the ISA INTs to upper (>15) IRQ values. But most would * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an * option. */ int undirect_isa_irq(int rirq) { #if defined(READY) printf("Freeing redirected ISA irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); return 0; #endif /* READY */ } /* * Reprogram the MB chipset to NOT redirect a PCI INTerrupt */ int undirect_pci_irq(int rirq) { #if defined(READY) if (bootverbose) printf("Freeing redirected PCI irq %d.\n", rirq); /** FIXME: tickle the MB redirector chip */ return ???; #else if (bootverbose) printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); return 0; #endif /* READY */ } /* * given a bus ID, return: * the bus type if found * -1 if NOT found */ int apic_bus_type(int id) { int x; for (x = 0; x < mp_nbusses; ++x) if (bus_data[x].bus_id == id) return bus_data[x].bus_type; return -1; } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus ID if found * -1 if NOT found */ int apic_src_bus_id(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_id); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated src bus IRQ if found * -1 if NOT found */ int apic_src_bus_irq(int apic, int pin) { int x; for (x = 0; x < nintrs; x++) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].src_bus_irq); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated INTerrupt type if found * -1 if NOT found */ int apic_int_type(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_type); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated trigger mode if found * -1 if NOT found */ int apic_trigger(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return ((io_apic_ints[x].int_flags >> 2) & 0x03); return -1; /* NOT found */ } /* * given a LOGICAL APIC# and pin#, return: * the associated 'active' level if found * -1 if NOT found */ int apic_polarity(int apic, int pin) { int x; /* search each of the possible INTerrupt sources */ for (x = 0; x < nintrs; ++x) if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && (pin == io_apic_ints[x].dst_apic_int)) return (io_apic_ints[x].int_flags & 0x03); return -1; /* NOT found */ } /* * set data according to MP defaults * FIXME: probably not complete yet... */ static void default_mp_table(int type) { int ap_cpu_id; #if defined(APIC_IO) u_int32_t ux; int io_apic_id; int pin; #endif /* APIC_IO */ #if 0 printf(" MP default config type: %d\n", type); switch (type) { case 1: printf(" bus: ISA, APIC: 82489DX\n"); break; case 2: printf(" bus: EISA, APIC: 82489DX\n"); break; case 3: printf(" bus: EISA, APIC: 82489DX\n"); break; case 4: printf(" bus: MCA, APIC: 82489DX\n"); break; case 5: printf(" bus: ISA+PCI, APIC: Integrated\n"); break; case 6: printf(" bus: EISA+PCI, APIC: Integrated\n"); break; case 7: printf(" bus: MCA+PCI, APIC: Integrated\n"); break; default: printf(" future type\n"); break; /* NOTREACHED */ } #endif /* 0 */ boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24; ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; /* BSP */ CPU_TO_ID(0) = boot_cpu_id; ID_TO_CPU(boot_cpu_id) = 0; /* one and only AP */ CPU_TO_ID(1) = ap_cpu_id; ID_TO_CPU(ap_cpu_id) = 1; #if defined(APIC_IO) /* one and only IO APIC */ io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; /* * sanity check, refer to MP spec section 3.6.6, last paragraph * necessary as some hardware isn't properly setting up the IO APIC */ #if defined(REALLY_ANAL_IOAPICID_VALUE) if (io_apic_id != 2) { #else if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { #endif /* REALLY_ANAL_IOAPICID_VALUE */ ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ ux &= ~APIC_ID_MASK; /* clear the ID field */ ux |= 0x02000000; /* set it to '2' */ io_apic_write(0, IOAPIC_ID, ux); /* write new value */ ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ if ((ux & APIC_ID_MASK) != 0x02000000) panic("can't control IO APIC ID, reg: 0x%08x", ux); io_apic_id = 2; } IO_TO_ID(0) = io_apic_id; ID_TO_IO(io_apic_id) = 0; #endif /* APIC_IO */ /* fill out bus entries */ switch (type) { case 1: case 2: case 3: case 5: case 6: bus_data[0].bus_id = default_data[type - 1][1]; bus_data[0].bus_type = default_data[type - 1][2]; bus_data[1].bus_id = default_data[type - 1][3]; bus_data[1].bus_type = default_data[type - 1][4]; break; /* case 4: case 7: MCA NOT supported */ default: /* illegal/reserved */ panic("BAD default MP config: %d", type); /* NOTREACHED */ } #if defined(APIC_IO) /* general cases from MP v1.4, table 5-2 */ for (pin = 0; pin < 16; ++pin) { io_apic_ints[pin].int_type = 0; io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ io_apic_ints[pin].src_bus_id = 0; io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ io_apic_ints[pin].dst_apic_id = io_apic_id; io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ } /* special cases from MP v1.4, table 5-2 */ if (type == 2) { io_apic_ints[2].int_type = 0xff; /* N/C */ io_apic_ints[13].int_type = 0xff; /* N/C */ #if !defined(APIC_MIXED_MODE) /** FIXME: ??? */ panic("sorry, can't support type 2 default yet"); #endif /* APIC_MIXED_MODE */ } else io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ if (type == 7) io_apic_ints[0].int_type = 0xff; /* N/C */ else io_apic_ints[0].int_type = 3; /* vectored 8259 */ #endif /* APIC_IO */ } /* * start each AP in our list */ static int start_all_aps(u_int boot_addr) { int x, i; u_char mpbiosreason; u_long mpbioswarmvec; pd_entry_t newptd; pt_entry_t newpt; int *newpp; POSTCODE(START_ALL_APS_POST); /** * NOTE: this needs further thought: * where does it get released? * should it be set to empy? * * get the initial mp_lock with a count of 1 for the BSP */ mp_lock = 1; /* this uses a LOGICAL cpu ID, ie BSP == 0 */ /* initialize BSP's local APIC */ apic_initialize(); /* install the AP 1st level boot code */ install_ap_tramp(boot_addr); /* save the current value of the warm-start vector */ mpbioswarmvec = *((u_long *) WARMBOOT_OFF); outb(CMOS_REG, BIOS_RESET); mpbiosreason = inb(CMOS_DATA); /* record BSP in CPU map */ all_cpus = 1; /* start each AP */ for (x = 1; x <= mp_naps; ++x) { /* HACK HACK HACK !!! */ /* alloc new page table directory */ newptd = (pd_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* clone currently active one (ie: IdlePTD) */ bcopy(PTD, newptd, PAGE_SIZE); /* inc prv page pde */ /* set up 0 -> 4MB P==V mapping for AP boot */ newptd[0] = PG_V | PG_RW | ((u_long)KPTphys & PG_FRAME); /* store PTD for this AP */ bootPTD = (pd_entry_t)vtophys(newptd); /* alloc new page table page */ newpt = (pt_entry_t)(kmem_alloc(kernel_map, PAGE_SIZE)); /* set the new PTD's private page to point there */ newptd[MPPTDI] = PG_V | PG_RW | vtophys(newpt); /* install self referential entry */ newptd[PTDPTDI] = PG_V | PG_RW | vtophys(newptd); /* get a new private data page */ newpp = (int *)kmem_alloc(kernel_map, PAGE_SIZE); /* wire it into the private page table page */ newpt[0] = PG_V | PG_RW | vtophys(newpp); /* wire the ptp into itself for access */ newpt[1] = PG_V | PG_RW | vtophys(newpt); /* and the local apic */ newpt[2] = SMP_prvpt[2]; /* and the IO apic mapping[s] */ for (i = 16; i < 32; i++) newpt[i] = SMP_prvpt[i]; /* prime data page for it to use */ newpp[0] = x; /* cpuid */ newpp[1] = 0; /* curproc */ newpp[2] = 0; /* curpcb */ newpp[3] = 0; /* npxproc */ newpp[4] = 0; /* runtime.tv_sec */ newpp[5] = 0; /* runtime.tv_usec */ newpp[6] = x << 24; /* cpu_lockid */ /* XXX NOTE: ABANDON bootPTD for now!!!! */ /* END REVOLTING HACKERY */ /* setup a vector to our boot code */ *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ /* attempt to start the Application Processor */ CHECK_INIT(99); /* setup checkpoints */ if (!start_ap(x, boot_addr)) { printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); CHECK_PRINT("trace"); /* show checkpoints */ /* better panic as the AP may be running loose */ printf("panic y/n? [y] "); if (cngetc() != 'n') panic("bye-bye"); } CHECK_PRINT("trace"); /* show checkpoints */ /* record its version info */ cpu_apic_versions[x] = cpu_apic_versions[0]; all_cpus |= (1 << x); /* record AP in CPU map */ } /* build our map of 'other' CPUs */ other_cpus = all_cpus & ~(1 << cpuid); /* fill in our (BSP) APIC version */ cpu_apic_versions[0] = lapic.version; /* restore the warmstart vector */ *(u_long *) WARMBOOT_OFF = mpbioswarmvec; outb(CMOS_REG, BIOS_RESET); outb(CMOS_DATA, mpbiosreason); pmap_set_opt_bsp(); /* number of APs actually started */ return mp_ncpus - 1; } /* * load the 1st level AP boot code into base memory. */ /* targets for relocation */ extern void bigJump(void); extern void bootCodeSeg(void); extern void bootDataSeg(void); extern void MPentry(void); extern u_int MP_GDT; extern u_int mp_gdtbase; static void install_ap_tramp(u_int boot_addr) { int x; int size = *(int *) ((u_long) & bootMP_size); u_char *src = (u_char *) ((u_long) bootMP); u_char *dst = (u_char *) boot_addr + KERNBASE; u_int boot_base = (u_int) bootMP; u_int8_t *dst8; u_int16_t *dst16; u_int32_t *dst32; POSTCODE(INSTALL_AP_TRAMP_POST); for (x = 0; x < size; ++x) *dst++ = *src++; /* * modify addresses in code we just moved to basemem. unfortunately we * need fairly detailed info about mpboot.s for this to work. changes * to mpboot.s might require changes here. */ /* boot code is located in KERNEL space */ dst = (u_char *) boot_addr + KERNBASE; /* modify the lgdt arg */ dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); /* modify the ljmp target for MPentry() */ dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); *dst32 = ((u_int) MPentry - KERNBASE); /* modify the target for boot code segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; /* modify the target for boot data segment */ dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); dst8 = (u_int8_t *) (dst16 + 1); *dst16 = (u_int) boot_addr & 0xffff; *dst8 = ((u_int) boot_addr >> 16) & 0xff; } /* * this function starts the AP (application processor) identified * by the APIC ID 'physicalCpu'. It does quite a "song and dance" * to accomplish this. This is necessary because of the nuances * of the different hardware we might encounter. It ain't pretty, * but it seems to work. */ static int start_ap(int logical_cpu, u_int boot_addr) { int physical_cpu; int vector; int cpus; u_long icr_lo, icr_hi; POSTCODE(START_AP_POST); /* get the PHYSICAL APIC ID# */ physical_cpu = CPU_TO_ID(logical_cpu); /* calculate the vector */ vector = (boot_addr >> 12) & 0xff; /* used as a watchpoint to signal AP startup */ cpus = mp_ncpus; /* * first we do an INIT/RESET IPI this INIT IPI might be run, reseting * and running the target CPU. OR this INIT IPI might be latched (P5 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be * ignored. */ /* setup the address for the target AP */ icr_hi = lapic.icr_hi & ~APIC_ID_MASK; icr_hi |= (physical_cpu << 24); lapic.icr_hi = icr_hi; /* do an INIT IPI: assert RESET */ icr_lo = lapic.icr_lo & 0xfff00000; lapic.icr_lo = icr_lo | 0x0000c500; /* wait for pending status end */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* do an INIT IPI: deassert RESET */ lapic.icr_lo = icr_lo | 0x00008500; /* wait for pending status end */ u_sleep(10000); /* wait ~10mS */ while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; /* * next we do a STARTUP IPI: the previous INIT IPI might still be * latched, (P5 bug) this 1st STARTUP would then terminate * immediately, and the previously started INIT IPI would continue. OR * the previous INIT IPI has already run. and this STARTUP IPI will * run. OR the previous INIT IPI was ignored. and this STARTUP IPI * will run. */ /* do a STARTUP IPI */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is * recognized after hardware RESET or INIT IPI. */ lapic.icr_lo = icr_lo | 0x00000600 | vector; while (lapic.icr_lo & APIC_DELSTAT_MASK) /* spin */ ; u_sleep(200); /* wait ~200uS */ /* wait for it to start */ set_apic_timer(5000000);/* == 5 seconds */ while (read_apic_timer()) if (mp_ncpus > cpus) return 1; /* return SUCCESS */ return 0; /* return FAILURE */ } /* * Flush the TLB on all other CPU's * * XXX: Needs to handshake and wait for completion before proceding. */ void smp_invltlb(void) { #if defined(APIC_IO) if (smp_active && invltlb_ok) all_but_self_ipi(XINVLTLB_OFFSET); #endif /* APIC_IO */ } void invlpg(u_int addr) { __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); /* send a message to the other CPUs */ smp_invltlb(); } void invltlb(void) { u_long temp; /* * This should be implemented as load_cr3(rcr3()) when load_cr3() is * inlined. */ __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); /* send a message to the other CPUs */ smp_invltlb(); } -#if defined(TEST_CPUSTOP) - -#if defined(DEBUG_CPUSTOP) -void db_printf __P((const char *fmt, ...)); -#endif /* DEBUG_CPUSTOP */ - /* * When called the executing CPU will send an IPI to all other CPUs * requesting that they halt execution. * * Usually (but not necessarily) called with 'other_cpus' as its arg. * * - Signals all CPUs in map to stop. * - Waits for each to stop. * * Returns: * -1: error * 0: NA * 1: ok * * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs * from executing at same time. */ int stop_cpus( u_int map ) { if (!smp_active) return 0; /* send IPI to all CPUs in map */ -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d stopping CPUs: 0x%08x\n", cpuid, map); -#endif /* DEBUG_CPUSTOP */ - stopped_cpus = 0; /* send the Xcpustop IPI to all CPUs in map */ selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED); -#if defined(DEBUG_CPUSTOP) - db_printf(" spin\n"); -#endif /* DEBUG_CPUSTOP */ - while (stopped_cpus != map) /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" spun\nstopped\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } /* * Called by a CPU to restart stopped CPUs. * * Usually (but not necessarily) called with 'stopped_cpus' as its arg. * * - Signals all CPUs in map to restart. * - Waits for each to restart. * * Returns: * -1: error * 0: NA * 1: ok */ int restart_cpus( u_int map ) { if (!smp_active) return 0; -#if defined(DEBUG_CPUSTOP) - db_printf("\nCPU%d restarting CPUs: 0x%08x (0x%08x)\n", - cpuid, map, stopped_cpus); -#endif /* DEBUG_CPUSTOP */ - started_cpus = map; /* signal other cpus to restart */ while (started_cpus) /* wait for each to clear its bit */ /* spin */ ; -#if defined(DEBUG_CPUSTOP) - db_printf(" restarted\n"); -#endif /* DEBUG_CPUSTOP */ - return 1; } - -#endif /** TEST_CPUSTOP */