Index: head/sys/arm/altera/socfpga/socfpga_machdep.c =================================================================== --- head/sys/arm/altera/socfpga/socfpga_machdep.c (revision 275048) +++ head/sys/arm/altera/socfpga/socfpga_machdep.c (revision 275049) @@ -1,113 +1,116 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_ddb.h" #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include #include #include vm_offset_t platform_lastaddr(void) { return (arm_devmap_lastaddr()); } void platform_probe_and_attach(void) { } void platform_gpio_init(void) { } void platform_late_init(void) { } int platform_devmap_init(void) { /* UART */ arm_devmap_add_entry(0xffc00000, 0x100000); /* * USB OTG * * We use static device map for USB due to some bug in the Altera * which throws Translation Fault (P) exception on high load. * It might be caused due to some power save options being turned * on or something else. */ arm_devmap_add_entry(0xffb00000, 0x100000); /* dwmmc */ arm_devmap_add_entry(0xff700000, 0x100000); /* scu */ arm_devmap_add_entry(0xfff00000, 0x100000); + /* FPGA memory window, 256MB */ + arm_devmap_add_entry(0xd0000000, 0x10000000); + return (0); } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } int bus_dma_get_range_nb(void) { return (0); } Index: head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts (revision 275048) +++ head/sys/boot/fdt/dts/arm/socfpga-sockit-beri.dts (revision 275049) @@ -1,124 +1,151 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /dts-v1/; /include/ "socfpga.dtsi" / { model = "Terasic SoCKit"; compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - /* Reserve first page for secondary CPU trampoline code */ - memreserve = < 0x00000000 0x1000 >; + memreserve = < 0x00000000 0x1000 >, /* SMP trampoline */ + < 0x00001000 0x1000 >; /* virtio block */ memory { device_type = "memory"; reg = < 0x00000000 0x40000000 >; /* 1G RAM */ }; SOC: socfpga { serial0: serial@ffc02000 { status = "okay"; }; usb1: usb@ffb40000 { status = "okay"; }; gmac1: ethernet@ff702000 { status = "okay"; rxd0-skew-ps = <0>; rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; txen-skew-ps = <0>; txc-skew-ps = <2600>; rxdv-skew-ps = <0>; rxc-skew-ps = <2000>; }; mmc: dwmmc@ff704000 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; num-slots = <1>; supports-highspeed; broken-cd; bus-frequency = <25000000>; slot@0 { reg = <0>; bus-width = <4>; }; }; - beri_mem: mem@d0000000 { + beri_mem0: mem@d0000000 { compatible = "sri-cambridge,beri-mem"; - reg = <0xd0000000 0x10000000>; + reg = <0xd0000000 0x10000000>; /* 256mb */ + status = "okay"; + }; + + pio0: pio@c0020000 { + compatible = "altr,pio"; + reg = <0xc0020000 0x1000>; /* recv */ + interrupts = < 76 >; + interrupt-parent = <&GIC>; + status = "okay"; + }; + + pio1: pio@c0021000 { + compatible = "altr,pio"; + reg = <0xc0021000 0x1000>; /* send */ + interrupts = < 82 >; /* not in use on arm side */ + interrupt-parent = <&GIC>; + status = "okay"; + }; + + beri_vtblk: vtblk@00001000 { + compatible = "sri-cambridge,beri-vtblk"; + reg = <0x00001000 0x1000>; + pio-recv = <&pio0>; + pio-send = <&pio1>; + beri-mem = <&beri_mem0>; status = "okay"; }; beri_debug: ring@c0000000 { compatible = "sri-cambridge,beri-ring"; reg = <0xc0000000 0x3000>; interrupts = < 72 73 >; interrupt-parent = <&GIC>; device_name = "beri_debug"; data_size = <0x1000>; data_read = <0x0>; data_write = <0x1000>; control_read = <0x2000>; control_write = <0x2010>; status = "okay"; }; beri_console: ring@c0004000 { compatible = "sri-cambridge,beri-ring"; reg = <0xc0004000 0x3000>; interrupts = < 74 75 >; interrupt-parent = <&GIC>; device_name = "beri_console"; data_size = <0x1000>; data_read = <0x0>; data_write = <0x1000>; control_read = <0x2000>; control_write = <0x2010>; status = "okay"; }; }; chosen { bootargs = "-v"; stdin = "serial0"; stdout = "serial0"; }; }; Index: head/sys/dev/beri/virtio/virtio.h =================================================================== --- head/sys/dev/beri/virtio/virtio.h (revision 275048) +++ head/sys/dev/beri/virtio/virtio.h (revision 275049) @@ -1,72 +1,72 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #define READ2(_sc, _reg) \ bus_read_2((_sc)->res[0], _reg) #define READ4(_sc, _reg) \ bus_read_4((_sc)->res[0], _reg) #define WRITE2(_sc, _reg, _val) \ bus_write_2((_sc)->res[0], _reg, _val) #define WRITE4(_sc, _reg, _val) \ bus_write_4((_sc)->res[0], _reg, _val) -#define PAGE_SHIFT 12 +#define PAGE_SHIFT 12 #define VRING_ALIGN 4096 #define NUM_QUEUES 1 #define VQ_ALLOC 0x01 /* set once we have a pfn */ #define VQ_MAX_DESCRIPTORS 512 #define VTBLK_BLK_ID_BYTES 20 #define VTBLK_MAXSEGS 256 struct vqueue_info { uint16_t vq_qsize; /* size of this queue (a power of 2) */ uint16_t vq_num; uint16_t vq_flags; uint16_t vq_last_avail; /* a recent value of vq_avail->va_idx */ uint16_t vq_save_used; /* saved vq_used->vu_idx; see vq_endchains */ uint32_t vq_pfn; /* PFN of virt queue (not shifted!) */ volatile struct vring_desc *vq_desc; /* descriptor array */ volatile struct vring_avail *vq_avail; /* the "avail" ring */ volatile struct vring_used *vq_used; /* the "used" ring */ }; int vq_ring_ready(struct vqueue_info *vq); int vq_has_descs(struct vqueue_info *vq); void * paddr_map(uint32_t offset, uint32_t phys, uint32_t size); void paddr_unmap(void *phys, uint32_t size); int vq_getchain(uint32_t beri_mem_offset, struct vqueue_info *vq, struct iovec *iov, int n_iov, uint16_t *flags); void vq_relchain(struct vqueue_info *vq, struct iovec *iov, int n, uint32_t iolen);