Index: head/sys/dev/drm2/drm_agpsupport.c =================================================================== --- head/sys/dev/drm2/drm_agpsupport.c (revision 273861) +++ head/sys/dev/drm2/drm_agpsupport.c (revision 273862) @@ -1,434 +1,434 @@ /*- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Author: * Rickard E. (Rik) Faith * Gareth Hughes * */ #include __FBSDID("$FreeBSD$"); /** @file drm_agpsupport.c * Support code for tying the kernel AGP support to DRM drivers and * the DRM's AGP ioctls. */ #include #include #include /* Returns 1 if AGP or 0 if not. */ static int drm_device_find_capability(struct drm_device *dev, int cap) { return (pci_find_cap(dev->device, cap, NULL) == 0); } int drm_device_is_agp(struct drm_device *dev) { if (dev->driver->device_is_agp != NULL) { int ret; /* device_is_agp returns a tristate, 0 = not AGP, 1 = definitely * AGP, 2 = fall back to PCI capability */ ret = (*dev->driver->device_is_agp)(dev); if (ret != DRM_MIGHT_BE_AGP) return ret; } return (drm_device_find_capability(dev, PCIY_AGP)); } int drm_device_is_pcie(struct drm_device *dev) { return (drm_device_find_capability(dev, PCIY_EXPRESS)); } int drm_agp_info(struct drm_device * dev, struct drm_agp_info *info) { struct agp_info *kern; if (!dev->agp || !dev->agp->acquired) return EINVAL; kern = &dev->agp->info; agp_get_info(dev->agp->agpdev, kern); info->agp_version_major = 1; info->agp_version_minor = 0; info->mode = kern->ai_mode; info->aperture_base = kern->ai_aperture_base; info->aperture_size = kern->ai_aperture_size; info->memory_allowed = kern->ai_memory_allowed; info->memory_used = kern->ai_memory_used; info->id_vendor = kern->ai_devid & 0xffff; info->id_device = kern->ai_devid >> 16; return 0; } int drm_agp_info_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { int err; struct drm_agp_info info; err = drm_agp_info(dev, &info); if (err != 0) return err; *(struct drm_agp_info *) data = info; return 0; } int drm_agp_acquire_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { return drm_agp_acquire(dev); } int drm_agp_acquire(struct drm_device *dev) { int retcode; if (!dev->agp || dev->agp->acquired) return EINVAL; retcode = agp_acquire(dev->agp->agpdev); if (retcode) return retcode; dev->agp->acquired = 1; return 0; } int drm_agp_release_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { return drm_agp_release(dev); } int drm_agp_release(struct drm_device * dev) { if (!dev->agp || !dev->agp->acquired) return EINVAL; agp_release(dev->agp->agpdev); dev->agp->acquired = 0; return 0; } int drm_agp_enable(struct drm_device *dev, struct drm_agp_mode mode) { if (!dev->agp || !dev->agp->acquired) return EINVAL; dev->agp->mode = mode.mode; agp_enable(dev->agp->agpdev, mode.mode); dev->agp->enabled = 1; return 0; } int drm_agp_enable_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_agp_mode mode; mode = *(struct drm_agp_mode *) data; return drm_agp_enable(dev, mode); } int drm_agp_alloc(struct drm_device *dev, struct drm_agp_buffer *request) { drm_agp_mem_t *entry; void *handle; unsigned long pages; u_int32_t type; struct agp_memory_info info; if (!dev->agp || !dev->agp->acquired) return EINVAL; entry = malloc(sizeof(*entry), DRM_MEM_AGPLISTS, M_NOWAIT | M_ZERO); if (entry == NULL) return ENOMEM; pages = (request->size + PAGE_SIZE - 1) / PAGE_SIZE; type = (u_int32_t) request->type; DRM_UNLOCK(dev); handle = drm_agp_allocate_memory(pages, type); DRM_LOCK(dev); if (handle == NULL) { free(entry, DRM_MEM_AGPLISTS); return ENOMEM; } entry->handle = handle; entry->bound = 0; entry->pages = pages; entry->prev = NULL; entry->next = dev->agp->memory; if (dev->agp->memory) dev->agp->memory->prev = entry; dev->agp->memory = entry; agp_memory_info(dev->agp->agpdev, entry->handle, &info); request->handle = (unsigned long) entry->handle; request->physical = info.ami_physical; return 0; } int drm_agp_alloc_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_agp_buffer request; int retcode; request = *(struct drm_agp_buffer *) data; DRM_LOCK(dev); retcode = drm_agp_alloc(dev, &request); DRM_UNLOCK(dev); *(struct drm_agp_buffer *) data = request; return retcode; } static drm_agp_mem_t * drm_agp_lookup_entry(struct drm_device *dev, void *handle) { drm_agp_mem_t *entry; for (entry = dev->agp->memory; entry; entry = entry->next) { if (entry->handle == handle) return entry; } return NULL; } int drm_agp_unbind(struct drm_device *dev, struct drm_agp_binding *request) { drm_agp_mem_t *entry; int retcode; if (!dev->agp || !dev->agp->acquired) return EINVAL; entry = drm_agp_lookup_entry(dev, (void *)request->handle); if (entry == NULL || !entry->bound) return EINVAL; DRM_UNLOCK(dev); retcode = drm_agp_unbind_memory(entry->handle); DRM_LOCK(dev); if (retcode == 0) entry->bound = 0; return retcode; } int drm_agp_unbind_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_agp_binding request; int retcode; request = *(struct drm_agp_binding *) data; DRM_LOCK(dev); retcode = drm_agp_unbind(dev, &request); DRM_UNLOCK(dev); return retcode; } int drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request) { drm_agp_mem_t *entry; int retcode; int page; if (!dev->agp || !dev->agp->acquired) return EINVAL; DRM_DEBUG("agp_bind, page_size=%x\n", (int)PAGE_SIZE); entry = drm_agp_lookup_entry(dev, (void *)request->handle); if (entry == NULL || entry->bound) return EINVAL; page = (request->offset + PAGE_SIZE - 1) / PAGE_SIZE; DRM_UNLOCK(dev); retcode = drm_agp_bind_memory(entry->handle, page); DRM_LOCK(dev); if (retcode == 0) entry->bound = dev->agp->base + (page << PAGE_SHIFT); return retcode; } int drm_agp_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_agp_binding request; int retcode; request = *(struct drm_agp_binding *) data; DRM_LOCK(dev); retcode = drm_agp_bind(dev, &request); DRM_UNLOCK(dev); return retcode; } int drm_agp_free(struct drm_device *dev, struct drm_agp_buffer *request) { drm_agp_mem_t *entry; if (!dev->agp || !dev->agp->acquired) return EINVAL; entry = drm_agp_lookup_entry(dev, (void*)request->handle); if (entry == NULL) return EINVAL; if (entry->prev) entry->prev->next = entry->next; else dev->agp->memory = entry->next; if (entry->next) entry->next->prev = entry->prev; DRM_UNLOCK(dev); if (entry->bound) drm_agp_unbind_memory(entry->handle); drm_agp_free_memory(entry->handle); DRM_LOCK(dev); free(entry, DRM_MEM_AGPLISTS); return 0; } int drm_agp_free_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_agp_buffer request; int retcode; request = *(struct drm_agp_buffer *) data; DRM_LOCK(dev); retcode = drm_agp_free(dev, &request); DRM_UNLOCK(dev); return retcode; } drm_agp_head_t *drm_agp_init(void) { device_t agpdev; drm_agp_head_t *head = NULL; int agp_available = 1; agpdev = DRM_AGP_FIND_DEVICE(); if (!agpdev) agp_available = 0; DRM_DEBUG("agp_available = %d\n", agp_available); if (agp_available) { head = malloc(sizeof(*head), DRM_MEM_AGPLISTS, M_NOWAIT | M_ZERO); if (head == NULL) return NULL; head->agpdev = agpdev; agp_get_info(agpdev, &head->info); head->base = head->info.ai_aperture_base; head->memory = NULL; DRM_INFO("AGP at 0x%08lx %dMB\n", (long)head->info.ai_aperture_base, (int)(head->info.ai_aperture_size >> 20)); } return head; } void *drm_agp_allocate_memory(size_t pages, u32 type) { device_t agpdev; agpdev = DRM_AGP_FIND_DEVICE(); if (!agpdev) return NULL; - return agp_alloc_memory(agpdev, type, pages << AGP_PAGE_SHIFT); + return agp_alloc_memory(agpdev, type, pages << PAGE_SHIFT); } int drm_agp_free_memory(void *handle) { device_t agpdev; agpdev = DRM_AGP_FIND_DEVICE(); if (!agpdev || !handle) return 0; agp_free_memory(agpdev, handle); return 1; } int drm_agp_bind_memory(void *handle, off_t start) { device_t agpdev; agpdev = DRM_AGP_FIND_DEVICE(); if (!agpdev || !handle) return EINVAL; return agp_bind_memory(agpdev, handle, start * PAGE_SIZE); } int drm_agp_unbind_memory(void *handle) { device_t agpdev; agpdev = DRM_AGP_FIND_DEVICE(); if (!agpdev || !handle) return EINVAL; return agp_unbind_memory(agpdev, handle); } Index: head/sys/dev/drm2/radeon/radeon.h =================================================================== --- head/sys/dev/drm2/radeon/radeon.h (revision 273861) +++ head/sys/dev/drm2/radeon/radeon.h (revision 273862) @@ -1,2053 +1,2054 @@ /* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include __FBSDID("$FreeBSD$"); #ifndef __RADEON_H__ #define __RADEON_H__ /* TODO: Here are things that needs to be done : * - surface allocator & initializer : (bit like scratch reg) should * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings * related to surface * - WB : write back stuff (do it bit like scratch reg things) * - Vblank : look at Jesse's rework and what we should do * - r600/r700: gart & cp * - cs : clean cs ioctl use bitmap & things like that. * - power management stuff * - Barrier in gart code * - Unmappabled vram ? * - TESTING, TESTING, TESTING */ /* Initialization path: * We expect that acceleration initialization might fail for various * reasons even thought we work hard to make it works on most * configurations. In order to still have a working userspace in such * situation the init path must succeed up to the memory controller * initialization point. Failure before this point are considered as * fatal error. Here is the init callchain : * radeon_device_init perform common structure, mutex initialization * asic_init setup the GPU memory layout and perform all * one time initialization (failure in this * function are considered fatal) * asic_startup setup the GPU acceleration, in order to * follow guideline the first thing this * function should do is setting the GPU * memory controller (only MC setup failure * are considered as fatal) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include "radeon_family.h" #include "radeon_mode.h" #include "radeon_reg.h" /* * Modules parameters. */ extern int radeon_no_wb; extern int radeon_modeset; extern int radeon_dynclks; extern int radeon_r4xx_atom; extern int radeon_agpmode; extern int radeon_vram_limit; extern int radeon_gart_size; extern int radeon_benchmarking; extern int radeon_testing; extern int radeon_connector_table; extern int radeon_tv; extern int radeon_audio; extern int radeon_disp_priority; extern int radeon_hw_i2c; extern int radeon_pcie_gen2; extern int radeon_msi; extern int radeon_lockup_timeout; /* * Copy from radeon_drv.h so we don't have to include both and have conflicting * symbol; */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ #define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2) /* RADEON_IB_POOL_SIZE must be a power of 2 */ #define RADEON_IB_POOL_SIZE 16 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 #define RADEONFB_CONN_LIMIT 4 #define RADEON_BIOS_NUM_SCRATCH 8 /* max number of rings */ #define RADEON_NUM_RINGS 5 /* fence seq are set to this number when signaled */ #define RADEON_FENCE_SIGNALED_SEQ 0LL /* internal ring indices */ /* r1xx+ has gfx CP ring */ #define RADEON_RING_TYPE_GFX_INDEX 0 /* cayman has 2 compute CP rings */ #define CAYMAN_RING_TYPE_CP1_INDEX 1 #define CAYMAN_RING_TYPE_CP2_INDEX 2 /* R600+ has an async dma ring */ #define R600_RING_TYPE_DMA_INDEX 3 /* cayman add a second async dma ring */ #define CAYMAN_RING_TYPE_DMA1_INDEX 4 /* hardcode those limit for now */ #define RADEON_VA_IB_OFFSET (1 << 20) #define RADEON_VA_RESERVED_SIZE (8 << 20) #define RADEON_IB_VM_MAX_SIZE (64 << 10) /* reset flags */ #define RADEON_RESET_GFX (1 << 0) #define RADEON_RESET_COMPUTE (1 << 1) #define RADEON_RESET_DMA (1 << 2) /* * Errata workarounds. */ enum radeon_pll_errata { CHIP_ERRATA_R300_CG = 0x00000001, CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, CHIP_ERRATA_PLL_DELAY = 0x00000004 }; struct radeon_device; /* * BIOS. */ bool radeon_get_bios(struct radeon_device *rdev); /* * Dummy page */ struct radeon_dummy_page { drm_dma_handle_t *dmah; dma_addr_t addr; }; int radeon_dummy_page_init(struct radeon_device *rdev); void radeon_dummy_page_fini(struct radeon_device *rdev); /* * Clocks */ struct radeon_clock { struct radeon_pll p1pll; struct radeon_pll p2pll; struct radeon_pll dcpll; struct radeon_pll spll; struct radeon_pll mpll; /* 10 Khz units */ uint32_t default_mclk; uint32_t default_sclk; uint32_t default_dispclk; uint32_t dp_extclk; uint32_t max_pixel_clock; }; /* * Power management */ int radeon_pm_init(struct radeon_device *rdev); void radeon_pm_fini(struct radeon_device *rdev); void radeon_pm_compute_clocks(struct radeon_device *rdev); void radeon_pm_suspend(struct radeon_device *rdev); void radeon_pm_resume(struct radeon_device *rdev); void radeon_combios_get_power_modes(struct radeon_device *rdev); void radeon_atombios_get_power_modes(struct radeon_device *rdev); void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); void rs690_pm_info(struct radeon_device *rdev); extern int rv6xx_get_temp(struct radeon_device *rdev); extern int rv770_get_temp(struct radeon_device *rdev); extern int evergreen_get_temp(struct radeon_device *rdev); extern int sumo_get_temp(struct radeon_device *rdev); extern int si_get_temp(struct radeon_device *rdev); extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, unsigned *bankh, unsigned *mtaspect, unsigned *tile_split); /* * Fences. */ struct radeon_fence_driver { uint32_t scratch_reg; uint64_t gpu_addr; volatile uint32_t *cpu_addr; /* sync_seq is protected by ring emission lock */ uint64_t sync_seq[RADEON_NUM_RINGS]; atomic64_t last_seq; unsigned long last_activity; bool initialized; }; struct radeon_fence { struct radeon_device *rdev; unsigned int kref; /* protected by radeon_fence.lock */ uint64_t seq; /* RB, DMA, etc. */ unsigned ring; }; int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); int radeon_fence_driver_init(struct radeon_device *rdev); void radeon_fence_driver_fini(struct radeon_device *rdev); void radeon_fence_driver_force_completion(struct radeon_device *rdev); int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); void radeon_fence_process(struct radeon_device *rdev, int ring); bool radeon_fence_signaled(struct radeon_fence *fence); int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); int radeon_fence_wait_any(struct radeon_device *rdev, struct radeon_fence **fences, bool intr); struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); void radeon_fence_unref(struct radeon_fence **fence); unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); void radeon_fence_note_sync(struct radeon_fence *fence, int ring); static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, struct radeon_fence *b) { if (!a) { return b; } if (!b) { return a; } KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); if (a->seq > b->seq) { return a; } else { return b; } } static inline bool radeon_fence_is_earlier(struct radeon_fence *a, struct radeon_fence *b) { if (!a) { return false; } if (!b) { return true; } KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings")); return a->seq < b->seq; } /* * Tiling registers */ struct radeon_surface_reg { struct radeon_bo *bo; }; #define RADEON_GEM_MAX_SURFACES 8 /* * TTM. */ struct radeon_mman { struct ttm_bo_global_ref bo_global_ref; struct drm_global_reference mem_global_ref; struct ttm_bo_device bdev; bool mem_global_referenced; bool initialized; }; /* bo virtual address in a specific vm */ struct radeon_bo_va { /* protected by bo being reserved */ struct list_head bo_list; uint64_t soffset; uint64_t eoffset; uint32_t flags; bool valid; unsigned ref_count; /* protected by vm mutex */ struct list_head vm_list; /* constant after initialization */ struct radeon_vm *vm; struct radeon_bo *bo; }; struct radeon_bo { /* Protected by gem.mutex */ struct list_head list; /* Protected by tbo.reserved */ u32 placements[3]; struct ttm_placement placement; struct ttm_buffer_object tbo; struct ttm_bo_kmap_obj kmap; unsigned pin_count; void *kptr; u32 tiling_flags; u32 pitch; int surface_reg; /* list of all virtual address to which this bo * is associated to */ struct list_head va; /* Constant after initialization */ struct radeon_device *rdev; struct drm_gem_object gem_base; struct ttm_bo_kmap_obj dma_buf_vmap; int vmapping_count; }; #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) struct radeon_bo_list { struct ttm_validate_buffer tv; struct radeon_bo *bo; uint64_t gpu_offset; unsigned rdomain; unsigned wdomain; u32 tiling_flags; }; /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver * like the indirect buffer or semaphore, which both have their * locking. * * Principe is simple, we keep a list of sub allocation in offset * order (first entry has offset == 0, last entry has the highest * offset). * * When allocating new object we first check if there is room at * the end total_size - (last_object_offset + last_object_size) >= * alloc_size. If so we allocate new object there. * * When there is not enough room at the end, we start waiting for * each sub object until we reach object_offset+object_size >= * alloc_size, this object then become the sub object we return. * * Alignment can't be bigger than page size. * * Hole are not considered for allocation to keep things simple. * Assumption is that there won't be hole (all object on same * alignment). */ struct radeon_sa_manager { struct cv wq; struct sx wq_lock; struct radeon_bo *bo; struct list_head *hole; struct list_head flist[RADEON_NUM_RINGS]; struct list_head olist; unsigned size; uint64_t gpu_addr; void *cpu_ptr; uint32_t domain; }; struct radeon_sa_bo; /* sub-allocation buffer */ struct radeon_sa_bo { struct list_head olist; struct list_head flist; struct radeon_sa_manager *manager; unsigned soffset; unsigned eoffset; struct radeon_fence *fence; }; /* * GEM objects. */ struct radeon_gem { struct sx mutex; struct list_head objects; }; int radeon_gem_init(struct radeon_device *rdev); void radeon_gem_fini(struct radeon_device *rdev); int radeon_gem_object_create(struct radeon_device *rdev, int size, int alignment, int initial_domain, bool discardable, bool kernel, struct drm_gem_object **obj); int radeon_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, struct drm_mode_create_dumb *args); int radeon_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p); int radeon_mode_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, uint32_t handle); /* * Semaphores. */ /* everything here is constant */ struct radeon_semaphore { struct radeon_sa_bo *sa_bo; signed waiters; uint64_t gpu_addr; }; int radeon_semaphore_create(struct radeon_device *rdev, struct radeon_semaphore **semaphore); void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, struct radeon_semaphore *semaphore); void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, struct radeon_semaphore *semaphore); int radeon_semaphore_sync_rings(struct radeon_device *rdev, struct radeon_semaphore *semaphore, int signaler, int waiter); void radeon_semaphore_free(struct radeon_device *rdev, struct radeon_semaphore **semaphore, struct radeon_fence *fence); /* * GART structures, functions & helpers */ struct radeon_mc; #define RADEON_GPU_PAGE_SIZE 4096 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) #define RADEON_GPU_PAGE_SHIFT 12 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) struct radeon_gart { drm_dma_handle_t *dmah; dma_addr_t table_addr; struct radeon_bo *robj; void *ptr; unsigned num_gpu_pages; unsigned num_cpu_pages; unsigned table_size; vm_page_t *pages; dma_addr_t *pages_addr; bool ready; }; int radeon_gart_table_ram_alloc(struct radeon_device *rdev); void radeon_gart_table_ram_free(struct radeon_device *rdev); int radeon_gart_table_vram_alloc(struct radeon_device *rdev); void radeon_gart_table_vram_free(struct radeon_device *rdev); int radeon_gart_table_vram_pin(struct radeon_device *rdev); void radeon_gart_table_vram_unpin(struct radeon_device *rdev); int radeon_gart_init(struct radeon_device *rdev); void radeon_gart_fini(struct radeon_device *rdev); void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, int pages); int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, int pages, vm_page_t *pagelist, dma_addr_t *dma_addr); void radeon_gart_restore(struct radeon_device *rdev); /* * GPU MC structures, functions & helpers */ struct radeon_mc { resource_size_t aper_size; resource_size_t aper_base; resource_size_t agp_base; /* for some chips with <= 32MB we need to lie * about vram size near mc fb location */ u64 mc_vram_size; u64 visible_vram_size; u64 gtt_size; u64 gtt_start; u64 gtt_end; u64 vram_start; u64 vram_end; unsigned vram_width; u64 real_vram_size; int vram_mtrr; bool vram_is_ddr; bool igp_sideport_enabled; u64 gtt_base_align; }; bool radeon_combios_sideport_present(struct radeon_device *rdev); bool radeon_atombios_sideport_present(struct radeon_device *rdev); /* * GPU scratch registers structures, functions & helpers */ struct radeon_scratch { unsigned num_reg; uint32_t reg_base; bool free[32]; uint32_t reg[32]; }; int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); /* * IRQS. */ struct radeon_unpin_work { struct task work; struct radeon_device *rdev; int crtc_id; struct radeon_fence *fence; struct drm_pending_vblank_event *event; struct radeon_bo *old_rbo; u64 new_crtc_base; }; struct r500_irq_stat_regs { u32 disp_int; u32 hdmi0_status; }; struct r600_irq_stat_regs { u32 disp_int; u32 disp_int_cont; u32 disp_int_cont2; u32 d1grph_int; u32 d2grph_int; u32 hdmi0_status; u32 hdmi1_status; }; struct evergreen_irq_stat_regs { u32 disp_int; u32 disp_int_cont; u32 disp_int_cont2; u32 disp_int_cont3; u32 disp_int_cont4; u32 disp_int_cont5; u32 d1grph_int; u32 d2grph_int; u32 d3grph_int; u32 d4grph_int; u32 d5grph_int; u32 d6grph_int; u32 afmt_status1; u32 afmt_status2; u32 afmt_status3; u32 afmt_status4; u32 afmt_status5; u32 afmt_status6; }; union radeon_irq_stat_regs { struct r500_irq_stat_regs r500; struct r600_irq_stat_regs r600; struct evergreen_irq_stat_regs evergreen; }; #define RADEON_MAX_HPD_PINS 6 #define RADEON_MAX_CRTCS 6 #define RADEON_MAX_AFMT_BLOCKS 6 struct radeon_irq { bool installed; struct mtx lock; atomic_t ring_int[RADEON_NUM_RINGS]; bool crtc_vblank_int[RADEON_MAX_CRTCS]; atomic_t pflip[RADEON_MAX_CRTCS]; wait_queue_head_t vblank_queue; bool hpd[RADEON_MAX_HPD_PINS]; bool afmt[RADEON_MAX_AFMT_BLOCKS]; union radeon_irq_stat_regs stat_regs; }; int radeon_irq_kms_init(struct radeon_device *rdev); void radeon_irq_kms_fini(struct radeon_device *rdev); void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); /* * CP & rings. */ struct radeon_ib { struct radeon_sa_bo *sa_bo; uint32_t length_dw; uint64_t gpu_addr; uint32_t *ptr; int ring; struct radeon_fence *fence; struct radeon_vm *vm; bool is_const_ib; struct radeon_fence *sync_to[RADEON_NUM_RINGS]; struct radeon_semaphore *semaphore; }; struct radeon_ring { struct radeon_bo *ring_obj; volatile uint32_t *ring; unsigned rptr; unsigned rptr_offs; unsigned rptr_reg; unsigned rptr_save_reg; u64 next_rptr_gpu_addr; volatile u32 *next_rptr_cpu_addr; unsigned wptr; unsigned wptr_old; unsigned wptr_reg; unsigned ring_size; unsigned ring_free_dw; int count_dw; unsigned long last_activity; unsigned last_rptr; uint64_t gpu_addr; uint32_t align_mask; uint32_t ptr_mask; bool ready; u32 ptr_reg_shift; u32 ptr_reg_mask; u32 nop; u32 idx; u64 last_semaphore_signal_addr; u64 last_semaphore_wait_addr; }; /* * VM */ /* maximum number of VMIDs */ #define RADEON_NUM_VM 16 /* defines number of bits in page table versus page directory, * a page is 4KB so we have 12 bits offset, 9 bits in the page * table and the remaining 19 bits are in the page directory */ #define RADEON_VM_BLOCK_SIZE 9 /* number of entries in page table */ #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) struct radeon_vm { struct list_head list; struct list_head va; unsigned id; /* contains the page directory */ struct radeon_sa_bo *page_directory; uint64_t pd_gpu_addr; /* array of page tables, one for each page directory entry */ struct radeon_sa_bo **page_tables; struct sx mutex; /* last fence for cs using this vm */ struct radeon_fence *fence; /* last flush or NULL if we still need to flush */ struct radeon_fence *last_flush; }; struct radeon_vm_manager { struct sx lock; struct list_head lru_vm; struct radeon_fence *active[RADEON_NUM_VM]; struct radeon_sa_manager sa_manager; uint32_t max_pfn; /* number of VMIDs */ unsigned nvm; /* vram base address for page table entry */ u64 vram_base_offset; /* is vm enabled? */ bool enabled; }; /* * file private structure */ struct radeon_fpriv { struct radeon_vm vm; }; /* * R6xx+ IH ring */ struct r600_ih { struct radeon_bo *ring_obj; volatile uint32_t *ring; unsigned rptr; unsigned ring_size; uint64_t gpu_addr; uint32_t ptr_mask; atomic_t lock; bool enabled; }; struct r600_blit_cp_primitives { void (*set_render_target)(struct radeon_device *rdev, int format, int w, int h, u64 gpu_addr); void (*cp_set_surface_sync)(struct radeon_device *rdev, u32 sync_type, u32 size, u64 mc_addr); void (*set_shaders)(struct radeon_device *rdev); void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); void (*set_tex_resource)(struct radeon_device *rdev, int format, int w, int h, int pitch, u64 gpu_addr, u32 size); void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, int x2, int y2); void (*draw_auto)(struct radeon_device *rdev); void (*set_default_state)(struct radeon_device *rdev); }; struct r600_blit { struct radeon_bo *shader_obj; struct r600_blit_cp_primitives primitives; int max_dim; int ring_size_common; int ring_size_per_loop; u64 shader_gpu_addr; u32 vs_offset, ps_offset; u32 state_offset; u32 state_len; }; /* * SI RLC stuff */ struct si_rlc { /* for power gating */ struct radeon_bo *save_restore_obj; uint64_t save_restore_gpu_addr; /* for clear state */ struct radeon_bo *clear_state_obj; uint64_t clear_state_gpu_addr; }; int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib *ib, struct radeon_vm *vm, unsigned size); void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, struct radeon_ib *const_ib); int radeon_ib_pool_init(struct radeon_device *rdev); void radeon_ib_pool_fini(struct radeon_device *rdev); int radeon_ib_ring_tests(struct radeon_device *rdev); /* Ring access between begin & end cannot sleep */ bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, struct radeon_ring *ring); void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); void radeon_ring_undo(struct radeon_ring *ring); void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); void radeon_ring_lockup_update(struct radeon_ring *ring); bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, uint32_t **data); int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, unsigned size, uint32_t *data); int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); /* r600 async dma */ void r600_dma_stop(struct radeon_device *rdev); int r600_dma_resume(struct radeon_device *rdev); void r600_dma_fini(struct radeon_device *rdev); void cayman_dma_stop(struct radeon_device *rdev); int cayman_dma_resume(struct radeon_device *rdev); void cayman_dma_fini(struct radeon_device *rdev); /* * CS. */ struct radeon_cs_reloc { struct drm_gem_object *gobj; struct radeon_bo *robj; struct radeon_bo_list lobj; uint32_t handle; uint32_t flags; }; struct radeon_cs_chunk { uint32_t chunk_id; uint32_t length_dw; int kpage_idx[2]; uint32_t *kpage[2]; uint32_t *kdata; void __user *user_ptr; int last_copied_page; int last_page_index; }; struct radeon_cs_parser { device_t dev; struct radeon_device *rdev; struct drm_file *filp; /* chunks */ unsigned nchunks; struct radeon_cs_chunk *chunks; uint64_t *chunks_array; /* IB */ unsigned idx; /* relocations */ unsigned nrelocs; struct radeon_cs_reloc *relocs; struct radeon_cs_reloc **relocs_ptr; struct list_head validated; unsigned dma_reloc_idx; /* indices of various chunks */ int chunk_ib_idx; int chunk_relocs_idx; int chunk_flags_idx; int chunk_const_ib_idx; struct radeon_ib ib; struct radeon_ib const_ib; void *track; unsigned family; int parser_error; u32 cs_flags; u32 ring; s32 priority; }; extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); struct radeon_cs_packet { unsigned idx; unsigned type; unsigned reg; unsigned opcode; int count; unsigned one_reg_wr; }; typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx, unsigned reg); typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt); /* * AGP */ int radeon_agp_init(struct radeon_device *rdev); void radeon_agp_resume(struct radeon_device *rdev); void radeon_agp_suspend(struct radeon_device *rdev); void radeon_agp_fini(struct radeon_device *rdev); /* * Writeback */ struct radeon_wb { struct radeon_bo *wb_obj; volatile uint32_t *wb; uint64_t gpu_addr; bool enabled; bool use_event; }; #define RADEON_WB_SCRATCH_OFFSET 0 #define RADEON_WB_RING0_NEXT_RPTR 256 #define RADEON_WB_CP_RPTR_OFFSET 1024 #define RADEON_WB_CP1_RPTR_OFFSET 1280 #define RADEON_WB_CP2_RPTR_OFFSET 1536 #define R600_WB_DMA_RPTR_OFFSET 1792 #define R600_WB_IH_WPTR_OFFSET 2048 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 #define R600_WB_EVENT_OFFSET 3072 /** * struct radeon_pm - power management datas * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) * @sclk: GPU clock Mhz (core bandwidth depends of this clock) * @needed_bandwidth: current bandwidth needs * * It keeps track of various data needed to take powermanagement decision. * Bandwidth need is used to determine minimun clock of the GPU and memory. * Equation between gpu/memory clock and available bandwidth is hw dependent * (type of memory, bus size, efficiency, ...) */ enum radeon_pm_method { PM_METHOD_PROFILE, PM_METHOD_DYNPM, }; enum radeon_dynpm_state { DYNPM_STATE_DISABLED, DYNPM_STATE_MINIMUM, DYNPM_STATE_PAUSED, DYNPM_STATE_ACTIVE, DYNPM_STATE_SUSPENDED, }; enum radeon_dynpm_action { DYNPM_ACTION_NONE, DYNPM_ACTION_MINIMUM, DYNPM_ACTION_DOWNCLOCK, DYNPM_ACTION_UPCLOCK, DYNPM_ACTION_DEFAULT }; enum radeon_voltage_type { VOLTAGE_NONE = 0, VOLTAGE_GPIO, VOLTAGE_VDDC, VOLTAGE_SW }; enum radeon_pm_state_type { POWER_STATE_TYPE_DEFAULT, POWER_STATE_TYPE_POWERSAVE, POWER_STATE_TYPE_BATTERY, POWER_STATE_TYPE_BALANCED, POWER_STATE_TYPE_PERFORMANCE, }; enum radeon_pm_profile_type { PM_PROFILE_DEFAULT, PM_PROFILE_AUTO, PM_PROFILE_LOW, PM_PROFILE_MID, PM_PROFILE_HIGH, }; #define PM_PROFILE_DEFAULT_IDX 0 #define PM_PROFILE_LOW_SH_IDX 1 #define PM_PROFILE_MID_SH_IDX 2 #define PM_PROFILE_HIGH_SH_IDX 3 #define PM_PROFILE_LOW_MH_IDX 4 #define PM_PROFILE_MID_MH_IDX 5 #define PM_PROFILE_HIGH_MH_IDX 6 #define PM_PROFILE_MAX 7 struct radeon_pm_profile { int dpms_off_ps_idx; int dpms_on_ps_idx; int dpms_off_cm_idx; int dpms_on_cm_idx; }; enum radeon_int_thermal_type { THERMAL_TYPE_NONE, THERMAL_TYPE_RV6XX, THERMAL_TYPE_RV770, THERMAL_TYPE_EVERGREEN, THERMAL_TYPE_SUMO, THERMAL_TYPE_NI, THERMAL_TYPE_SI, }; struct radeon_voltage { enum radeon_voltage_type type; /* gpio voltage */ struct radeon_gpio_rec gpio; u32 delay; /* delay in usec from voltage drop to sclk change */ bool active_high; /* voltage drop is active when bit is high */ /* VDDC voltage */ u8 vddc_id; /* index into vddc voltage table */ u8 vddci_id; /* index into vddci voltage table */ bool vddci_enabled; /* r6xx+ sw */ u16 voltage; /* evergreen+ vddci */ u16 vddci; }; /* clock mode flags */ #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) struct radeon_pm_clock_info { /* memory clock */ u32 mclk; /* engine clock */ u32 sclk; /* voltage info */ struct radeon_voltage voltage; /* standardized clock flags */ u32 flags; }; /* state flags */ #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) struct radeon_power_state { enum radeon_pm_state_type type; struct radeon_pm_clock_info *clock_info; /* number of valid clock modes in this power state */ int num_clock_modes; struct radeon_pm_clock_info *default_clock_mode; /* standardized state flags */ u32 flags; u32 misc; /* vbios specific flags */ u32 misc2; /* vbios specific flags */ int pcie_lanes; /* pcie lanes */ }; /* * Some modes are overclocked by very low value, accept them */ #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ struct radeon_pm { struct sx mutex; /* write locked while reprogramming mclk */ struct sx mclk_lock; u32 active_crtcs; int active_crtc_count; int req_vblank; bool vblank_sync; fixed20_12 max_bandwidth; fixed20_12 igp_sideport_mclk; fixed20_12 igp_system_mclk; fixed20_12 igp_ht_link_clk; fixed20_12 igp_ht_link_width; fixed20_12 k8_bandwidth; fixed20_12 sideport_bandwidth; fixed20_12 ht_bandwidth; fixed20_12 core_bandwidth; fixed20_12 sclk; fixed20_12 mclk; fixed20_12 needed_bandwidth; struct radeon_power_state *power_state; /* number of valid power states */ int num_power_states; int current_power_state_index; int current_clock_mode_index; int requested_power_state_index; int requested_clock_mode_index; int default_power_state_index; u32 current_sclk; u32 current_mclk; u16 current_vddc; u16 current_vddci; u32 default_sclk; u32 default_mclk; u16 default_vddc; u16 default_vddci; struct radeon_i2c_chan *i2c_bus; /* selected pm method */ enum radeon_pm_method pm_method; /* dynpm power management */ #ifdef DUMBBELL_WIP struct delayed_work dynpm_idle_work; #endif /* DUMBBELL_WIP */ enum radeon_dynpm_state dynpm_state; enum radeon_dynpm_action dynpm_planned_action; unsigned long dynpm_action_timeout; bool dynpm_can_upclock; bool dynpm_can_downclock; /* profile-based power management */ enum radeon_pm_profile_type profile; int profile_index; struct radeon_pm_profile profiles[PM_PROFILE_MAX]; /* internal thermal controller on rv6xx+ */ enum radeon_int_thermal_type int_thermal_type; #ifdef DUMBBELL_WIP struct device *int_hwmon_dev; #endif /* DUMBBELL_WIP */ }; int radeon_pm_get_type_index(struct radeon_device *rdev, enum radeon_pm_state_type ps_type, int instance); struct r600_audio { int channels; int rate; int bits_per_sample; u8 status_bits; u8 category_code; }; /* * Benchmarking */ void radeon_benchmark(struct radeon_device *rdev, int test_number); /* * Testing */ void radeon_test_moves(struct radeon_device *rdev); void radeon_test_ring_sync(struct radeon_device *rdev, struct radeon_ring *cpA, struct radeon_ring *cpB); void radeon_test_syncing(struct radeon_device *rdev); /* * Debugfs */ struct radeon_debugfs { struct drm_info_list *files; unsigned num_files; }; int radeon_debugfs_add_files(struct radeon_device *rdev, struct drm_info_list *files, unsigned nfiles); int radeon_debugfs_fence_init(struct radeon_device *rdev); /* * ASIC specific functions. */ struct radeon_asic { int (*init)(struct radeon_device *rdev); void (*fini)(struct radeon_device *rdev); int (*resume)(struct radeon_device *rdev); int (*suspend)(struct radeon_device *rdev); void (*vga_set_state)(struct radeon_device *rdev, bool state); int (*asic_reset)(struct radeon_device *rdev); /* ioctl hw specific callback. Some hw might want to perform special * operation on specific ioctl. For instance on wait idle some hw * might want to perform and HDP flush through MMIO as it seems that * some R6XX/R7XX hw doesn't take HDP flush into account if programmed * through ring. */ void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); /* check if 3D engine is idle */ bool (*gui_idle)(struct radeon_device *rdev); /* wait for mc_idle */ int (*mc_wait_for_idle)(struct radeon_device *rdev); /* gart */ struct { void (*tlb_flush)(struct radeon_device *rdev); int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); } gart; struct { int (*init)(struct radeon_device *rdev); void (*fini)(struct radeon_device *rdev); u32 pt_ring_index; void (*set_page)(struct radeon_device *rdev, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags); } vm; /* ring specific callbacks */ struct { void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, struct radeon_semaphore *semaphore, bool emit_wait); int (*cs_parse)(struct radeon_cs_parser *p); void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); } ring[RADEON_NUM_RINGS]; /* irqs */ struct { int (*set)(struct radeon_device *rdev); irqreturn_t (*process)(struct radeon_device *rdev); } irq; /* displays */ struct { /* display watermarks */ void (*bandwidth_update)(struct radeon_device *rdev); /* get frame count */ u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); /* wait for vblank */ void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); /* set backlight level */ void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); /* get backlight level */ u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); } display; /* copy functions for bo handling */ struct { int (*blit)(struct radeon_device *rdev, uint64_t src_offset, uint64_t dst_offset, unsigned num_gpu_pages, struct radeon_fence **fence); u32 blit_ring_index; int (*dma)(struct radeon_device *rdev, uint64_t src_offset, uint64_t dst_offset, unsigned num_gpu_pages, struct radeon_fence **fence); u32 dma_ring_index; /* method used for bo copy */ int (*copy)(struct radeon_device *rdev, uint64_t src_offset, uint64_t dst_offset, unsigned num_gpu_pages, struct radeon_fence **fence); /* ring used for bo copies */ u32 copy_ring_index; } copy; /* surfaces */ struct { int (*set_reg)(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size); void (*clear_reg)(struct radeon_device *rdev, int reg); } surface; /* hotplug detect */ struct { void (*init)(struct radeon_device *rdev); void (*fini)(struct radeon_device *rdev); bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); } hpd; /* power management */ struct { void (*misc)(struct radeon_device *rdev); void (*prepare)(struct radeon_device *rdev); void (*finish)(struct radeon_device *rdev); void (*init_profile)(struct radeon_device *rdev); void (*get_dynpm_state)(struct radeon_device *rdev); uint32_t (*get_engine_clock)(struct radeon_device *rdev); void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); uint32_t (*get_memory_clock)(struct radeon_device *rdev); void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); int (*get_pcie_lanes)(struct radeon_device *rdev); void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); void (*set_clock_gating)(struct radeon_device *rdev, int enable); } pm; /* pageflipping */ struct { void (*pre_page_flip)(struct radeon_device *rdev, int crtc); u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); void (*post_page_flip)(struct radeon_device *rdev, int crtc); } pflip; }; /* * Asic structures */ struct r100_asic { const unsigned *reg_safe_bm; unsigned reg_safe_bm_size; u32 hdp_cntl; }; struct r300_asic { const unsigned *reg_safe_bm; unsigned reg_safe_bm_size; u32 resync_scratch; u32 hdp_cntl; }; struct r600_asic { unsigned max_pipes; unsigned max_tile_pipes; unsigned max_simds; unsigned max_backends; unsigned max_gprs; unsigned max_threads; unsigned max_stack_entries; unsigned max_hw_contexts; unsigned max_gs_threads; unsigned sx_max_export_size; unsigned sx_max_export_pos_size; unsigned sx_max_export_smx_size; unsigned sq_num_cf_insts; unsigned tiling_nbanks; unsigned tiling_npipes; unsigned tiling_group_size; unsigned tile_config; unsigned backend_map; }; struct rv770_asic { unsigned max_pipes; unsigned max_tile_pipes; unsigned max_simds; unsigned max_backends; unsigned max_gprs; unsigned max_threads; unsigned max_stack_entries; unsigned max_hw_contexts; unsigned max_gs_threads; unsigned sx_max_export_size; unsigned sx_max_export_pos_size; unsigned sx_max_export_smx_size; unsigned sq_num_cf_insts; unsigned sx_num_of_sets; unsigned sc_prim_fifo_size; unsigned sc_hiz_tile_fifo_size; unsigned sc_earlyz_tile_fifo_fize; unsigned tiling_nbanks; unsigned tiling_npipes; unsigned tiling_group_size; unsigned tile_config; unsigned backend_map; }; struct evergreen_asic { unsigned num_ses; unsigned max_pipes; unsigned max_tile_pipes; unsigned max_simds; unsigned max_backends; unsigned max_gprs; unsigned max_threads; unsigned max_stack_entries; unsigned max_hw_contexts; unsigned max_gs_threads; unsigned sx_max_export_size; unsigned sx_max_export_pos_size; unsigned sx_max_export_smx_size; unsigned sq_num_cf_insts; unsigned sx_num_of_sets; unsigned sc_prim_fifo_size; unsigned sc_hiz_tile_fifo_size; unsigned sc_earlyz_tile_fifo_size; unsigned tiling_nbanks; unsigned tiling_npipes; unsigned tiling_group_size; unsigned tile_config; unsigned backend_map; }; struct cayman_asic { unsigned max_shader_engines; unsigned max_pipes_per_simd; unsigned max_tile_pipes; unsigned max_simds_per_se; unsigned max_backends_per_se; unsigned max_texture_channel_caches; unsigned max_gprs; unsigned max_threads; unsigned max_gs_threads; unsigned max_stack_entries; unsigned sx_num_of_sets; unsigned sx_max_export_size; unsigned sx_max_export_pos_size; unsigned sx_max_export_smx_size; unsigned max_hw_contexts; unsigned sq_num_cf_insts; unsigned sc_prim_fifo_size; unsigned sc_hiz_tile_fifo_size; unsigned sc_earlyz_tile_fifo_size; unsigned num_shader_engines; unsigned num_shader_pipes_per_simd; unsigned num_tile_pipes; unsigned num_simds_per_se; unsigned num_backends_per_se; unsigned backend_disable_mask_per_asic; unsigned backend_map; unsigned num_texture_channel_caches; unsigned mem_max_burst_length_bytes; unsigned mem_row_size_in_kb; unsigned shader_engine_tile_size; unsigned num_gpus; unsigned multi_gpu_tile_size; unsigned tile_config; }; struct si_asic { unsigned max_shader_engines; unsigned max_tile_pipes; unsigned max_cu_per_sh; unsigned max_sh_per_se; unsigned max_backends_per_se; unsigned max_texture_channel_caches; unsigned max_gprs; unsigned max_gs_threads; unsigned max_hw_contexts; unsigned sc_prim_fifo_size_frontend; unsigned sc_prim_fifo_size_backend; unsigned sc_hiz_tile_fifo_size; unsigned sc_earlyz_tile_fifo_size; unsigned num_tile_pipes; unsigned num_backends_per_se; unsigned backend_disable_mask_per_asic; unsigned backend_map; unsigned num_texture_channel_caches; unsigned mem_max_burst_length_bytes; unsigned mem_row_size_in_kb; unsigned shader_engine_tile_size; unsigned num_gpus; unsigned multi_gpu_tile_size; unsigned tile_config; }; union radeon_asic_config { struct r300_asic r300; struct r100_asic r100; struct r600_asic r600; struct rv770_asic rv770; struct evergreen_asic evergreen; struct cayman_asic cayman; struct si_asic si; }; /* * asic initizalization from radeon_asic.c */ int radeon_asic_init(struct radeon_device *rdev); /* * IOCTL. */ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); /* VRAM scratch page for HDP bug, default vram page */ struct r600_vram_scratch { struct radeon_bo *robj; volatile uint32_t *ptr; u64 gpu_addr; }; /* * ACPI */ struct radeon_atif_notification_cfg { bool enabled; int command_code; }; struct radeon_atif_notifications { bool display_switch; bool expansion_mode_change; bool thermal_state; bool forced_power_state; bool system_power_state; bool display_conf_change; bool px_gfx_switch; bool brightness_change; bool dgpu_display_event; }; struct radeon_atif_functions { bool system_params; bool sbios_requests; bool select_active_disp; bool lid_state; bool get_tv_standard; bool set_tv_standard; bool get_panel_expansion_mode; bool set_panel_expansion_mode; bool temperature_change; bool graphics_device_types; }; struct radeon_atif { struct radeon_atif_notifications notifications; struct radeon_atif_functions functions; struct radeon_atif_notification_cfg notification_cfg; struct radeon_encoder *encoder_for_bl; }; struct radeon_atcs_functions { bool get_ext_state; bool pcie_perf_req; bool pcie_dev_rdy; bool pcie_bus_width; }; struct radeon_atcs { struct radeon_atcs_functions functions; }; /* * Core structure, functions and helpers. */ typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); struct radeon_device { device_t dev; struct drm_device *ddev; struct sx exclusive_lock; /* ASIC */ union radeon_asic_config config; enum radeon_family family; unsigned long flags; int usec_timeout; enum radeon_pll_errata pll_errata; int num_gb_pipes; int num_z_pipes; int disp_priority; /* BIOS */ uint8_t *bios; bool is_atom_bios; uint16_t bios_header_start; struct radeon_bo *stollen_vga_memory; /* Register mmio */ resource_size_t rmmio_base; resource_size_t rmmio_size; /* protects concurrent MM_INDEX/DATA based register access */ struct mtx mmio_idx_lock; int rmmio_rid; struct resource *rmmio; radeon_rreg_t mc_rreg; radeon_wreg_t mc_wreg; radeon_rreg_t pll_rreg; radeon_wreg_t pll_wreg; uint32_t pcie_reg_mask; radeon_rreg_t pciep_rreg; radeon_wreg_t pciep_wreg; /* io port */ int rio_rid; struct resource *rio_mem; resource_size_t rio_mem_size; struct radeon_clock clock; struct radeon_mc mc; struct radeon_gart gart; struct radeon_mode_info mode_info; struct radeon_scratch scratch; struct radeon_mman mman; struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; struct cv fence_queue; struct mtx fence_queue_mtx; struct sx ring_lock; struct radeon_ring ring[RADEON_NUM_RINGS]; bool ib_pool_ready; struct radeon_sa_manager ring_tmp_bo; struct radeon_irq irq; struct radeon_asic *asic; struct radeon_gem gem; struct radeon_pm pm; uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; struct radeon_wb wb; struct radeon_dummy_page dummy_page; bool shutdown; bool suspend; bool need_dma32; bool accel_working; bool fictitious_range_registered; + bool fictitious_agp_range_registered; struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; const struct firmware *me_fw; /* all family ME firmware */ const struct firmware *pfp_fw; /* r6/700 PFP firmware */ const struct firmware *rlc_fw; /* r6/700 RLC firmware */ const struct firmware *mc_fw; /* NI MC firmware */ const struct firmware *ce_fw; /* SI CE firmware */ struct r600_blit r600_blit; struct r600_vram_scratch vram_scratch; int msi_enabled; /* msi enabled */ struct r600_ih ih; /* r6/700 interrupt ring */ struct si_rlc rlc; struct taskqueue *tq; struct task hotplug_work; struct task audio_work; int num_crtc; /* number of crtcs */ struct sx dc_hw_i2c_mutex; /* display controller hw i2c mutex */ bool audio_enabled; struct r600_audio audio_status; /* audio stuff */ struct { ACPI_HANDLE handle; ACPI_NOTIFY_HANDLER notifier_call; } acpi; /* only one userspace can use Hyperz features or CMASK at a time */ struct drm_file *hyperz_filp; struct drm_file *cmask_filp; /* i2c buses */ struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; /* debugfs */ struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; unsigned debugfs_count; /* virtual memory */ struct radeon_vm_manager vm_manager; struct sx gpu_clock_mutex; /* ACPI interface */ struct radeon_atif atif; struct radeon_atcs atcs; }; int radeon_device_init(struct radeon_device *rdev, struct drm_device *ddev, uint32_t flags); void radeon_device_fini(struct radeon_device *rdev); int radeon_gpu_wait_for_idle(struct radeon_device *rdev); uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, bool always_indirect); void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, bool always_indirect); u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); /* * Cast helper */ #define to_radeon_fence(p) ((struct radeon_fence *)(p)) /* * Registers read & write functions. */ #define RREG8(reg) bus_read_1((rdev->rmmio), (reg)) #define WREG8(reg, v) bus_write_1((rdev->rmmio), (reg), v) #define RREG16(reg) bus_read_2((rdev->rmmio), (reg)) #define WREG16(reg, v) bus_write_2((rdev->rmmio), (reg), v) #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) #define DREG32(reg) DRM_INFO("REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ tmp_ &= (mask); \ tmp_ |= ((val) & ~(mask)); \ WREG32(reg, tmp_); \ } while (0) #define WREG32_PLL_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32_PLL(reg); \ tmp_ &= (mask); \ tmp_ |= ((val) & ~(mask)); \ WREG32_PLL(reg, tmp_); \ } while (0) #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) /* * Indirect registers accessor */ static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) { uint32_t r; WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); r = RREG32(RADEON_PCIE_DATA); return r; } static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) { WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); WREG32(RADEON_PCIE_DATA, (v)); } void r100_pll_errata_after_index(struct radeon_device *rdev); /* * ASICs helpers. */ #define ASIC_IS_RN50(rdev) ((rdev->ddev->pci_device == 0x515e) || \ (rdev->ddev->pci_device == 0x5969)) #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ (rdev->family == CHIP_RV200) || \ (rdev->family == CHIP_RS100) || \ (rdev->family == CHIP_RS200) || \ (rdev->family == CHIP_RV250) || \ (rdev->family == CHIP_RV280) || \ (rdev->family == CHIP_RS300)) #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ (rdev->family == CHIP_RV350) || \ (rdev->family == CHIP_R350) || \ (rdev->family == CHIP_RV380) || \ (rdev->family == CHIP_R420) || \ (rdev->family == CHIP_R423) || \ (rdev->family == CHIP_RV410) || \ (rdev->family == CHIP_RS400) || \ (rdev->family == CHIP_RS480)) #define ASIC_IS_X2(rdev) ((rdev->ddev->pci_device == 0x9441) || \ (rdev->ddev->pci_device == 0x9443) || \ (rdev->ddev->pci_device == 0x944B) || \ (rdev->ddev->pci_device == 0x9506) || \ (rdev->ddev->pci_device == 0x9509) || \ (rdev->ddev->pci_device == 0x950F) || \ (rdev->ddev->pci_device == 0x689C) || \ (rdev->ddev->pci_device == 0x689D)) #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ (rdev->family == CHIP_RS690) || \ (rdev->family == CHIP_RS740) || \ (rdev->family >= CHIP_R600)) #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ (rdev->flags & RADEON_IS_IGP)) #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ (rdev->flags & RADEON_IS_IGP)) /* * BIOS helpers. */ #define RBIOS8(i) (rdev->bios[i]) #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) int radeon_combios_init(struct radeon_device *rdev); void radeon_combios_fini(struct radeon_device *rdev); int radeon_atombios_init(struct radeon_device *rdev); void radeon_atombios_fini(struct radeon_device *rdev); /* * RING helpers. */ #if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) { ring->ring[ring->wptr++] = v; ring->wptr &= ring->ptr_mask; ring->count_dw--; ring->ring_free_dw--; } #else /* With debugging this is just too big to inline */ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); #endif /* * ASICs macro. */ #define radeon_init(rdev) (rdev)->asic->init((rdev)) #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) /* Common functions */ /* AGP */ extern int radeon_gpu_reset(struct radeon_device *rdev); extern void radeon_agp_disable(struct radeon_device *rdev); extern int radeon_modeset_init(struct radeon_device *rdev); extern void radeon_modeset_fini(struct radeon_device *rdev); extern bool radeon_card_posted(struct radeon_device *rdev); extern void radeon_update_bandwidth_info(struct radeon_device *rdev); extern void radeon_update_display_priority(struct radeon_device *rdev); extern bool radeon_boot_test_post_card(struct radeon_device *rdev); extern void radeon_scratch_init(struct radeon_device *rdev); extern void radeon_wb_fini(struct radeon_device *rdev); extern int radeon_wb_init(struct radeon_device *rdev); extern void radeon_wb_disable(struct radeon_device *rdev); extern void radeon_surface_init(struct radeon_device *rdev); extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); extern int radeon_resume_kms(struct drm_device *dev); extern int radeon_suspend_kms(struct drm_device *dev); extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); /* * vm */ int radeon_vm_manager_init(struct radeon_device *rdev); void radeon_vm_manager_fini(struct radeon_device *rdev); void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, struct radeon_vm *vm, int ring); void radeon_vm_fence(struct radeon_device *rdev, struct radeon_vm *vm, struct radeon_fence *fence); uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); int radeon_vm_bo_update_pte(struct radeon_device *rdev, struct radeon_vm *vm, struct radeon_bo *bo, struct ttm_mem_reg *mem); void radeon_vm_bo_invalidate(struct radeon_device *rdev, struct radeon_bo *bo); struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, struct radeon_bo *bo); struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, struct radeon_vm *vm, struct radeon_bo *bo); int radeon_vm_bo_set_addr(struct radeon_device *rdev, struct radeon_bo_va *bo_va, uint64_t offset, uint32_t flags); int radeon_vm_bo_rmv(struct radeon_device *rdev, struct radeon_bo_va *bo_va); /* audio */ void r600_audio_update_hdmi(void *arg, int pending); /* * R600 vram scratch functions */ int r600_vram_scratch_init(struct radeon_device *rdev); void r600_vram_scratch_fini(struct radeon_device *rdev); /* * r600 cs checking helper */ unsigned r600_mip_minify(unsigned size, unsigned level); bool r600_fmt_is_valid_color(u32 format); bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); int r600_fmt_get_blocksize(u32 format); int r600_fmt_get_nblocksx(u32 format, u32 w); int r600_fmt_get_nblocksy(u32 format, u32 h); /* * r600 functions used by radeon_encoder.c */ struct radeon_hdmi_acr { u32 clock; int n_32khz; int cts_32khz; int n_44_1khz; int cts_44_1khz; int n_48khz; int cts_48khz; }; extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); extern void r600_hdmi_enable(struct drm_encoder *encoder); extern void r600_hdmi_disable(struct drm_encoder *encoder); extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, u32 tiling_pipe_num, u32 max_rb_num, u32 total_max_rb_num, u32 enabled_rb_mask); /* * evergreen functions used by radeon_encoder.c */ extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); extern int ni_init_microcode(struct radeon_device *rdev); extern int ni_mc_load_microcode(struct radeon_device *rdev); extern void ni_fini_microcode(struct radeon_device *rdev); /* radeon_acpi.c */ extern int radeon_acpi_init(struct radeon_device *rdev); extern void radeon_acpi_fini(struct radeon_device *rdev); /* Prototypes added by @dumbbell. */ /* atombios_encoders.c */ void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, struct drm_connector *drm_connector); void radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device, u16 caps); /* radeon_atombios.c */ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, struct drm_display_mode *mode); /* radeon_combios.c */ void radeon_combios_connected_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder, bool connected); /* radeon_connectors.c */ void radeon_atombios_connected_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder, bool connected); void radeon_add_legacy_connector(struct drm_device *dev, uint32_t connector_id, uint32_t supported_device, int connector_type, struct radeon_i2c_bus_rec *i2c_bus, uint16_t connector_object_id, struct radeon_hpd *hpd); void radeon_add_atom_connector(struct drm_device *dev, uint32_t connector_id, uint32_t supported_device, int connector_type, struct radeon_i2c_bus_rec *i2c_bus, uint32_t igp_lane_info, uint16_t connector_object_id, struct radeon_hpd *hpd, struct radeon_router *router); /* radeon_encoders.c */ uint32_t radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac); void radeon_link_encoder_connector(struct drm_device *dev); /* radeon_legacy_encoders.c */ void radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device); void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, struct drm_connector *drm_connector); /* radeon_pm.c */ void radeon_pm_acpi_event_handler(struct radeon_device *rdev); /* radeon_ttm.c */ int radeon_ttm_init(struct radeon_device *rdev); void radeon_ttm_fini(struct radeon_device *rdev); /* radeon_fb.c */ struct fb_info * radeon_fb_helper_getinfo(device_t kdev); /* r600.c */ int r600_ih_ring_alloc(struct radeon_device *rdev); void r600_ih_ring_fini(struct radeon_device *rdev); #include "radeon_object.h" #endif Index: head/sys/dev/drm2/radeon/radeon_device.c =================================================================== --- head/sys/dev/drm2/radeon/radeon_device.c (revision 273861) +++ head/sys/dev/drm2/radeon/radeon_device.c (revision 273862) @@ -1,1551 +1,1577 @@ /* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include __FBSDID("$FreeBSD$"); #include #include #include #include "radeon_reg.h" #include "radeon.h" #include "atom.h" static const char radeon_family_name[][16] = { "R100", "RV100", "RS100", "RV200", "RS200", "R200", "RV250", "RS300", "RV280", "R300", "R350", "RV350", "RV380", "R420", "R423", "RV410", "RS400", "RS480", "RS600", "RS690", "RS740", "RV515", "R520", "RV530", "RV560", "RV570", "R580", "R600", "RV610", "RV630", "RV670", "RV620", "RV635", "RS780", "RS880", "RV770", "RV730", "RV710", "RV740", "CEDAR", "REDWOOD", "JUNIPER", "CYPRESS", "HEMLOCK", "PALM", "SUMO", "SUMO2", "BARTS", "TURKS", "CAICOS", "CAYMAN", "ARUBA", "TAHITI", "PITCAIRN", "VERDE", "LAST", }; /** * radeon_surface_init - Clear GPU surface registers. * * @rdev: radeon_device pointer * * Clear GPU surface registers (r1xx-r5xx). */ void radeon_surface_init(struct radeon_device *rdev) { /* FIXME: check this out */ if (rdev->family < CHIP_R600) { int i; for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { if (rdev->surface_regs[i].bo) radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); else radeon_clear_surface_reg(rdev, i); } /* enable surfaces */ WREG32(RADEON_SURFACE_CNTL, 0); } } /* * GPU scratch registers helpers function. */ /** * radeon_scratch_init - Init scratch register driver information. * * @rdev: radeon_device pointer * * Init CP scratch register driver information (r1xx-r5xx) */ void radeon_scratch_init(struct radeon_device *rdev) { int i; /* FIXME: check this out */ if (rdev->family < CHIP_R300) { rdev->scratch.num_reg = 5; } else { rdev->scratch.num_reg = 7; } rdev->scratch.reg_base = RADEON_SCRATCH_REG0; for (i = 0; i < rdev->scratch.num_reg; i++) { rdev->scratch.free[i] = true; rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); } } /** * radeon_scratch_get - Allocate a scratch register * * @rdev: radeon_device pointer * @reg: scratch register mmio offset * * Allocate a CP scratch register for use by the driver (all asics). * Returns 0 on success or -EINVAL on failure. */ int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) { int i; for (i = 0; i < rdev->scratch.num_reg; i++) { if (rdev->scratch.free[i]) { rdev->scratch.free[i] = false; *reg = rdev->scratch.reg[i]; return 0; } } return -EINVAL; } /** * radeon_scratch_free - Free a scratch register * * @rdev: radeon_device pointer * @reg: scratch register mmio offset * * Free a CP scratch register allocated for use by the driver (all asics) */ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) { int i; for (i = 0; i < rdev->scratch.num_reg; i++) { if (rdev->scratch.reg[i] == reg) { rdev->scratch.free[i] = true; return; } } } /* * radeon_wb_*() * Writeback is the the method by which the the GPU updates special pages * in memory with the status of certain GPU events (fences, ring pointers, * etc.). */ /** * radeon_wb_disable - Disable Writeback * * @rdev: radeon_device pointer * * Disables Writeback (all asics). Used for suspend. */ void radeon_wb_disable(struct radeon_device *rdev) { int r; if (rdev->wb.wb_obj) { r = radeon_bo_reserve(rdev->wb.wb_obj, false); if (unlikely(r != 0)) return; radeon_bo_kunmap(rdev->wb.wb_obj); radeon_bo_unpin(rdev->wb.wb_obj); radeon_bo_unreserve(rdev->wb.wb_obj); } rdev->wb.enabled = false; } /** * radeon_wb_fini - Disable Writeback and free memory * * @rdev: radeon_device pointer * * Disables Writeback and frees the Writeback memory (all asics). * Used at driver shutdown. */ void radeon_wb_fini(struct radeon_device *rdev) { radeon_wb_disable(rdev); if (rdev->wb.wb_obj) { radeon_bo_unref(&rdev->wb.wb_obj); rdev->wb.wb = NULL; rdev->wb.wb_obj = NULL; } } /** * radeon_wb_init- Init Writeback driver info and allocate memory * * @rdev: radeon_device pointer * * Disables Writeback and frees the Writeback memory (all asics). * Used at driver startup. * Returns 0 on success or an -error on failure. */ int radeon_wb_init(struct radeon_device *rdev) { int r; void *wb_ptr; if (rdev->wb.wb_obj == NULL) { r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); if (r) { dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); return r; } } r = radeon_bo_reserve(rdev->wb.wb_obj, false); if (unlikely(r != 0)) { radeon_wb_fini(rdev); return r; } r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, &rdev->wb.gpu_addr); if (r) { radeon_bo_unreserve(rdev->wb.wb_obj); dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); radeon_wb_fini(rdev); return r; } wb_ptr = &rdev->wb.wb; r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr); radeon_bo_unreserve(rdev->wb.wb_obj); if (r) { dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); radeon_wb_fini(rdev); return r; } /* clear wb memory */ memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE); /* disable event_write fences */ rdev->wb.use_event = false; /* disabled via module param */ if (radeon_no_wb == 1) { rdev->wb.enabled = false; } else { if (rdev->flags & RADEON_IS_AGP) { /* often unreliable on AGP */ rdev->wb.enabled = false; } else if (rdev->family < CHIP_R300) { /* often unreliable on pre-r300 */ rdev->wb.enabled = false; } else { rdev->wb.enabled = true; /* event_write fences are only available on r600+ */ if (rdev->family >= CHIP_R600) { rdev->wb.use_event = true; } } } /* always use writeback/events on NI, APUs */ if (rdev->family >= CHIP_PALM) { rdev->wb.enabled = true; rdev->wb.use_event = true; } dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); return 0; } /** * radeon_vram_location - try to find VRAM location * @rdev: radeon device structure holding all necessary informations * @mc: memory controller structure holding memory informations * @base: base address at which to put VRAM * * Function will place try to place VRAM at base address provided * as parameter (which is so far either PCI aperture address or * for IGP TOM base address). * * If there is not enough space to fit the unvisible VRAM in the 32bits * address space then we limit the VRAM size to the aperture. * * If we are using AGP and if the AGP aperture doesn't allow us to have * room for all the VRAM than we restrict the VRAM to the PCI aperture * size and print a warning. * * This function will never fails, worst case are limiting VRAM. * * Note: GTT start, end, size should be initialized before calling this * function on AGP platform. * * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, * this shouldn't be a problem as we are using the PCI aperture as a reference. * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but * not IGP. * * Note: we use mc_vram_size as on some board we need to program the mc to * cover the whole aperture even if VRAM size is inferior to aperture size * Novell bug 204882 + along with lots of ubuntu ones * * Note: when limiting vram it's safe to overwritte real_vram_size because * we are not in case where real_vram_size is inferior to mc_vram_size (ie * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu * ones) * * Note: IGP TOM addr should be the same as the aperture addr, we don't * explicitly check for that thought. * * FIXME: when reducing VRAM size align new size on power of 2. */ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) { uint64_t limit = (uint64_t)radeon_vram_limit << 20; mc->vram_start = base; if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); mc->real_vram_size = mc->aper_size; mc->mc_vram_size = mc->aper_size; } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); mc->real_vram_size = mc->aper_size; mc->mc_vram_size = mc->aper_size; } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; if (limit && limit < mc->real_vram_size) mc->real_vram_size = limit; dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n", (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start, (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20); } /** * radeon_gtt_location - try to find GTT location * @rdev: radeon device structure holding all necessary informations * @mc: memory controller structure holding memory informations * * Function will place try to place GTT before or after VRAM. * * If GTT size is bigger than space left then we ajust GTT size. * Thus function will never fails. * * FIXME: when reducing GTT size align new size on power of 2. */ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) { u64 size_af, size_bf; size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; size_bf = mc->vram_start & ~mc->gtt_base_align; if (size_bf > size_af) { if (mc->gtt_size > size_bf) { dev_warn(rdev->dev, "limiting GTT\n"); mc->gtt_size = size_bf; } mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; } else { if (mc->gtt_size > size_af) { dev_warn(rdev->dev, "limiting GTT\n"); mc->gtt_size = size_af; } mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; } mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n", (uintmax_t)mc->gtt_size >> 20, (uintmax_t)mc->gtt_start, (uintmax_t)mc->gtt_end); } /* * GPU helpers function. */ /** * radeon_card_posted - check if the hw has already been initialized * * @rdev: radeon_device pointer * * Check if the asic has been initialized (all asics). * Used at driver startup. * Returns true if initialized or false if not. */ bool radeon_card_posted(struct radeon_device *rdev) { uint32_t reg; #ifdef DUMBBELL_WIP if (efi_enabled(EFI_BOOT) && rdev->dev->pci_subvendor == PCI_VENDOR_ID_APPLE) return false; #endif /* DUMBBELL_WIP */ /* first check CRTCs */ if (ASIC_IS_DCE41(rdev)) { reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); if (reg & EVERGREEN_CRTC_MASTER_EN) return true; } else if (ASIC_IS_DCE4(rdev)) { reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); if (reg & EVERGREEN_CRTC_MASTER_EN) return true; } else if (ASIC_IS_AVIVO(rdev)) { reg = RREG32(AVIVO_D1CRTC_CONTROL) | RREG32(AVIVO_D2CRTC_CONTROL); if (reg & AVIVO_CRTC_EN) { return true; } } else { reg = RREG32(RADEON_CRTC_GEN_CNTL) | RREG32(RADEON_CRTC2_GEN_CNTL); if (reg & RADEON_CRTC_EN) { return true; } } /* then check MEM_SIZE, in case the crtcs are off */ if (rdev->family >= CHIP_R600) reg = RREG32(R600_CONFIG_MEMSIZE); else reg = RREG32(RADEON_CONFIG_MEMSIZE); if (reg) return true; return false; } /** * radeon_update_bandwidth_info - update display bandwidth params * * @rdev: radeon_device pointer * * Used when sclk/mclk are switched or display modes are set. * params are used to calculate display watermarks (all asics) */ void radeon_update_bandwidth_info(struct radeon_device *rdev) { fixed20_12 a; u32 sclk = rdev->pm.current_sclk; u32 mclk = rdev->pm.current_mclk; /* sclk/mclk in Mhz */ a.full = dfixed_const(100); rdev->pm.sclk.full = dfixed_const(sclk); rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); rdev->pm.mclk.full = dfixed_const(mclk); rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); if (rdev->flags & RADEON_IS_IGP) { a.full = dfixed_const(16); /* core_bandwidth = sclk(Mhz) * 16 */ rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); } } /** * radeon_boot_test_post_card - check and possibly initialize the hw * * @rdev: radeon_device pointer * * Check if the asic is initialized and if not, attempt to initialize * it (all asics). * Returns true if initialized or false if not. */ bool radeon_boot_test_post_card(struct radeon_device *rdev) { if (radeon_card_posted(rdev)) return true; if (rdev->bios) { DRM_INFO("GPU not posted. posting now...\n"); if (rdev->is_atom_bios) atom_asic_init(rdev->mode_info.atom_context); else radeon_combios_asic_init(rdev->ddev); return true; } else { dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); return false; } } /** * radeon_dummy_page_init - init dummy page used by the driver * * @rdev: radeon_device pointer * * Allocate the dummy page used by the driver (all asics). * This dummy page is used by the driver as a filler for gart entries * when pages are taken out of the GART * Returns 0 on sucess, -ENOMEM on failure. */ int radeon_dummy_page_init(struct radeon_device *rdev) { if (rdev->dummy_page.dmah) return 0; rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev, PAGE_SIZE, PAGE_SIZE, BUS_SPACE_MAXSIZE_32BIT); if (rdev->dummy_page.dmah == NULL) return -ENOMEM; rdev->dummy_page.addr = rdev->dummy_page.dmah->busaddr; return 0; } /** * radeon_dummy_page_fini - free dummy page used by the driver * * @rdev: radeon_device pointer * * Frees the dummy page used by the driver (all asics). */ void radeon_dummy_page_fini(struct radeon_device *rdev) { if (rdev->dummy_page.dmah == NULL) return; drm_pci_free(rdev->ddev, rdev->dummy_page.dmah); rdev->dummy_page.dmah = NULL; rdev->dummy_page.addr = 0; } /* ATOM accessor methods */ /* * ATOM is an interpreted byte code stored in tables in the vbios. The * driver registers callbacks to access registers and the interpreter * in the driver parses the tables and executes then to program specific * actions (set display modes, asic init, etc.). See radeon_atombios.c, * atombios.h, and atom.c */ /** * cail_pll_read - read PLL register * * @info: atom card_info pointer * @reg: PLL register offset * * Provides a PLL register accessor for the atom interpreter (r4xx+). * Returns the value of the PLL register. */ static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) { struct radeon_device *rdev = info->dev->dev_private; uint32_t r; r = rdev->pll_rreg(rdev, reg); return r; } /** * cail_pll_write - write PLL register * * @info: atom card_info pointer * @reg: PLL register offset * @val: value to write to the pll register * * Provides a PLL register accessor for the atom interpreter (r4xx+). */ static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) { struct radeon_device *rdev = info->dev->dev_private; rdev->pll_wreg(rdev, reg, val); } /** * cail_mc_read - read MC (Memory Controller) register * * @info: atom card_info pointer * @reg: MC register offset * * Provides an MC register accessor for the atom interpreter (r4xx+). * Returns the value of the MC register. */ static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) { struct radeon_device *rdev = info->dev->dev_private; uint32_t r; r = rdev->mc_rreg(rdev, reg); return r; } /** * cail_mc_write - write MC (Memory Controller) register * * @info: atom card_info pointer * @reg: MC register offset * @val: value to write to the pll register * * Provides a MC register accessor for the atom interpreter (r4xx+). */ static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) { struct radeon_device *rdev = info->dev->dev_private; rdev->mc_wreg(rdev, reg, val); } /** * cail_reg_write - write MMIO register * * @info: atom card_info pointer * @reg: MMIO register offset * @val: value to write to the pll register * * Provides a MMIO register accessor for the atom interpreter (r4xx+). */ static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) { struct radeon_device *rdev = info->dev->dev_private; WREG32(reg*4, val); } /** * cail_reg_read - read MMIO register * * @info: atom card_info pointer * @reg: MMIO register offset * * Provides an MMIO register accessor for the atom interpreter (r4xx+). * Returns the value of the MMIO register. */ static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) { struct radeon_device *rdev = info->dev->dev_private; uint32_t r; r = RREG32(reg*4); return r; } /** * cail_ioreg_write - write IO register * * @info: atom card_info pointer * @reg: IO register offset * @val: value to write to the pll register * * Provides a IO register accessor for the atom interpreter (r4xx+). */ static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) { struct radeon_device *rdev = info->dev->dev_private; WREG32_IO(reg*4, val); } /** * cail_ioreg_read - read IO register * * @info: atom card_info pointer * @reg: IO register offset * * Provides an IO register accessor for the atom interpreter (r4xx+). * Returns the value of the IO register. */ static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) { struct radeon_device *rdev = info->dev->dev_private; uint32_t r; r = RREG32_IO(reg*4); return r; } /** * radeon_atombios_init - init the driver info and callbacks for atombios * * @rdev: radeon_device pointer * * Initializes the driver info and register access callbacks for the * ATOM interpreter (r4xx+). * Returns 0 on sucess, -ENOMEM on failure. * Called at driver startup. */ int radeon_atombios_init(struct radeon_device *rdev) { struct card_info *atom_card_info = malloc(sizeof(struct card_info), DRM_MEM_DRIVER, M_ZERO | M_WAITOK); if (!atom_card_info) return -ENOMEM; rdev->mode_info.atom_card_info = atom_card_info; atom_card_info->dev = rdev->ddev; atom_card_info->reg_read = cail_reg_read; atom_card_info->reg_write = cail_reg_write; /* needed for iio ops */ if (rdev->rio_mem) { atom_card_info->ioreg_read = cail_ioreg_read; atom_card_info->ioreg_write = cail_ioreg_write; } else { DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); atom_card_info->ioreg_read = cail_reg_read; atom_card_info->ioreg_write = cail_reg_write; } atom_card_info->mc_read = cail_mc_read; atom_card_info->mc_write = cail_mc_write; atom_card_info->pll_read = cail_pll_read; atom_card_info->pll_write = cail_pll_write; rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); sx_init(&rdev->mode_info.atom_context->mutex, "drm__radeon_device__mode_info__atom_context__mutex"); radeon_atom_initialize_bios_scratch_regs(rdev->ddev); atom_allocate_fb_scratch(rdev->mode_info.atom_context); return 0; } /** * radeon_atombios_fini - free the driver info and callbacks for atombios * * @rdev: radeon_device pointer * * Frees the driver info and register access callbacks for the ATOM * interpreter (r4xx+). * Called at driver shutdown. */ void radeon_atombios_fini(struct radeon_device *rdev) { if (rdev->mode_info.atom_context) { free(rdev->mode_info.atom_context->scratch, DRM_MEM_DRIVER); atom_destroy(rdev->mode_info.atom_context); } free(rdev->mode_info.atom_card_info, DRM_MEM_DRIVER); } /* COMBIOS */ /* * COMBIOS is the bios format prior to ATOM. It provides * command tables similar to ATOM, but doesn't have a unified * parser. See radeon_combios.c */ /** * radeon_combios_init - init the driver info for combios * * @rdev: radeon_device pointer * * Initializes the driver info for combios (r1xx-r3xx). * Returns 0 on sucess. * Called at driver startup. */ int radeon_combios_init(struct radeon_device *rdev) { radeon_combios_initialize_bios_scratch_regs(rdev->ddev); return 0; } /** * radeon_combios_fini - free the driver info for combios * * @rdev: radeon_device pointer * * Frees the driver info for combios (r1xx-r3xx). * Called at driver shutdown. */ void radeon_combios_fini(struct radeon_device *rdev) { } #ifdef DUMBBELL_WIP /* if we get transitioned to only one device, take VGA back */ /** * radeon_vga_set_decode - enable/disable vga decode * * @cookie: radeon_device pointer * @state: enable/disable vga decode * * Enable/disable vga decode (all asics). * Returns VGA resource flags. */ static unsigned int radeon_vga_set_decode(void *cookie, bool state) { struct radeon_device *rdev = cookie; radeon_vga_set_state(rdev, state); if (state) return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; else return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; } #endif /* DUMBBELL_WIP */ /** * radeon_check_pot_argument - check that argument is a power of two * * @arg: value to check * * Validates that a certain argument is a power of two (all asics). * Returns true if argument is valid. */ static bool radeon_check_pot_argument(int arg) { return (arg & (arg - 1)) == 0; } /** * radeon_check_arguments - validate module params * * @rdev: radeon_device pointer * * Validates certain module parameters and updates * the associated values used by the driver (all asics). */ static void radeon_check_arguments(struct radeon_device *rdev) { /* vramlimit must be a power of two */ if (!radeon_check_pot_argument(radeon_vram_limit)) { dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", radeon_vram_limit); radeon_vram_limit = 0; } /* gtt size must be power of two and greater or equal to 32M */ if (radeon_gart_size < 32) { dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", radeon_gart_size); radeon_gart_size = 512; } else if (!radeon_check_pot_argument(radeon_gart_size)) { dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", radeon_gart_size); radeon_gart_size = 512; } rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; /* AGP mode can only be -1, 1, 2, 4, 8 */ switch (radeon_agpmode) { case -1: case 0: case 1: case 2: case 4: case 8: break; default: dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); radeon_agpmode = 0; break; } } /** * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is * needed for waking up. * * @pdev: pci dev pointer */ #ifdef DUMBBELL_WIP static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev) { /* 6600m in a macbook pro */ if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && pdev->subsystem_device == 0x00e2) { printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n"); return true; } return false; } #endif /* DUMBBELL_WIP */ /** * radeon_switcheroo_set_state - set switcheroo state * * @pdev: pci dev pointer * @state: vga switcheroo state * * Callback for the switcheroo driver. Suspends or resumes the * the asics before or after it is powered up using ACPI methods. */ #ifdef DUMBBELL_WIP static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) { struct drm_device *dev = pci_get_drvdata(pdev); pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; if (state == VGA_SWITCHEROO_ON) { unsigned d3_delay = dev->pdev->d3_delay; printk(KERN_INFO "radeon: switched on\n"); /* don't suspend or resume card normally */ dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev)) dev->pdev->d3_delay = 20; radeon_resume_kms(dev); dev->pdev->d3_delay = d3_delay; dev->switch_power_state = DRM_SWITCH_POWER_ON; drm_kms_helper_poll_enable(dev); } else { printk(KERN_INFO "radeon: switched off\n"); drm_kms_helper_poll_disable(dev); dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; radeon_suspend_kms(dev, pmm); dev->switch_power_state = DRM_SWITCH_POWER_OFF; } } #endif /* DUMBBELL_WIP */ /** * radeon_switcheroo_can_switch - see if switcheroo state can change * * @pdev: pci dev pointer * * Callback for the switcheroo driver. Check of the switcheroo * state can be changed. * Returns true if the state can be changed, false if not. */ #ifdef DUMBBELL_WIP static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) { struct drm_device *dev = pci_get_drvdata(pdev); bool can_switch; spin_lock(&dev->count_lock); can_switch = (dev->open_count == 0); spin_unlock(&dev->count_lock); return can_switch; } static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { .set_gpu_state = radeon_switcheroo_set_state, .reprobe = NULL, .can_switch = radeon_switcheroo_can_switch, }; #endif /* DUMBBELL_WIP */ /** * radeon_device_init - initialize the driver * * @rdev: radeon_device pointer * @pdev: drm dev pointer * @flags: driver flags * * Initializes the driver info and hw (all asics). * Returns 0 for success or an error on failure. * Called at driver startup. */ int radeon_device_init(struct radeon_device *rdev, struct drm_device *ddev, uint32_t flags) { int r, i; int dma_bits; rdev->shutdown = false; rdev->dev = ddev->device; rdev->ddev = ddev; rdev->flags = flags; rdev->family = flags & RADEON_FAMILY_MASK; rdev->is_atom_bios = false; rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; rdev->accel_working = false; rdev->fictitious_range_registered = false; + rdev->fictitious_agp_range_registered = false; /* set up ring ids */ for (i = 0; i < RADEON_NUM_RINGS; i++) { rdev->ring[i].idx = i; } DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", radeon_family_name[rdev->family], ddev->pci_vendor, ddev->pci_device, ddev->pci_subvendor, ddev->pci_subdevice); /* mutex initialization are all done here so we * can recall function without having locking issues */ sx_init(&rdev->ring_lock, "drm__radeon_device__ring_lock"); sx_init(&rdev->dc_hw_i2c_mutex, "drm__radeon_device__dc_hw_i2c_mutex"); atomic_set(&rdev->ih.lock, 0); sx_init(&rdev->gem.mutex, "drm__radeon_device__gem__mutex"); sx_init(&rdev->pm.mutex, "drm__radeon_device__pm__mutex"); sx_init(&rdev->gpu_clock_mutex, "drm__radeon_device__gpu_clock_mutex"); sx_init(&rdev->pm.mclk_lock, "drm__radeon_device__pm__mclk_lock"); sx_init(&rdev->exclusive_lock, "drm__radeon_device__exclusive_lock"); DRM_INIT_WAITQUEUE(&rdev->irq.vblank_queue); r = radeon_gem_init(rdev); if (r) return r; /* initialize vm here */ sx_init(&rdev->vm_manager.lock, "drm__radeon_device__vm_manager__lock"); /* Adjust VM size here. * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ rdev->vm_manager.max_pfn = 1 << 20; INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); /* Set asic functions */ r = radeon_asic_init(rdev); if (r) return r; radeon_check_arguments(rdev); /* all of the newer IGP chips have an internal gart * However some rs4xx report as AGP, so remove that here. */ if ((rdev->family >= CHIP_RS400) && (rdev->flags & RADEON_IS_IGP)) { rdev->flags &= ~RADEON_IS_AGP; } if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { radeon_agp_disable(rdev); } /* set DMA mask + need_dma32 flags. * PCIE - can handle 40-bits. * IGP - can handle 40-bits * AGP - generally dma32 is safest * PCI - dma32 for legacy pci gart, 40 bits on newer asics */ rdev->need_dma32 = false; if (rdev->flags & RADEON_IS_AGP) rdev->need_dma32 = true; if ((rdev->flags & RADEON_IS_PCI) && (rdev->family <= CHIP_RS740)) rdev->need_dma32 = true; dma_bits = rdev->need_dma32 ? 32 : 40; #ifdef DUMBBELL_WIP r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); if (r) { rdev->need_dma32 = true; dma_bits = 32; printk(KERN_WARNING "radeon: No suitable DMA available.\n"); } r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); if (r) { pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); printk(KERN_WARNING "radeon: No coherent DMA available.\n"); } #endif /* DUMBBELL_WIP */ /* Registers mapping */ /* TODO: block userspace mapping of io register */ DRM_SPININIT(&rdev->mmio_idx_lock, "drm__radeon_device__mmio_idx_lock"); rdev->rmmio_rid = PCIR_BAR(2); rdev->rmmio = bus_alloc_resource_any(rdev->dev, SYS_RES_MEMORY, &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE); if (rdev->rmmio == NULL) { return -ENOMEM; } rdev->rmmio_base = rman_get_start(rdev->rmmio); rdev->rmmio_size = rman_get_size(rdev->rmmio); DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); /* io port mapping */ for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) { uint32_t data; data = pci_read_config(rdev->dev, PCIR_BAR(i), 4); if (PCI_BAR_IO(data)) { rdev->rio_rid = PCIR_BAR(i); rdev->rio_mem = bus_alloc_resource_any(rdev->dev, SYS_RES_IOPORT, &rdev->rio_rid, RF_ACTIVE | RF_SHAREABLE); break; } } if (rdev->rio_mem == NULL) DRM_ERROR("Unable to find PCI I/O BAR\n"); rdev->tq = taskqueue_create("radeonkms", M_WAITOK, taskqueue_thread_enqueue, &rdev->tq); taskqueue_start_threads(&rdev->tq, 1, PWAIT, "radeon taskq"); #ifdef DUMBBELL_WIP /* if we have > 1 VGA cards, then disable the radeon VGA resources */ /* this will fail for cards that aren't VGA class devices, just * ignore it */ vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops); #endif /* DUMBBELL_WIP */ r = radeon_init(rdev); if (r) return r; r = radeon_ib_ring_tests(rdev); if (r) DRM_ERROR("ib ring test failed (%d).\n", r); if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { /* Acceleration not working on AGP card try again * with fallback to PCI or PCIE GART */ radeon_asic_reset(rdev); radeon_fini(rdev); radeon_agp_disable(rdev); r = radeon_init(rdev); if (r) return r; } DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n", __func__, (uintmax_t)rdev->mc.aper_base, (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size); r = vm_phys_fictitious_reg_range( rdev->mc.aper_base, rdev->mc.aper_base + rdev->mc.visible_vram_size, VM_MEMATTR_WRITE_COMBINING); if (r != 0) { DRM_ERROR("Failed to register fictitious range " "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.aper_base, (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r); return (-r); } rdev->fictitious_range_registered = true; +#if __OS_HAS_AGP + if (rdev->flags & RADEON_IS_AGP) { + DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n", + __func__, (uintmax_t)rdev->mc.agp_base, + (uintmax_t)rdev->mc.agp_base + rdev->mc.gtt_size); + r = vm_phys_fictitious_reg_range( + rdev->mc.agp_base, + rdev->mc.agp_base + rdev->mc.gtt_size, + VM_MEMATTR_WRITE_COMBINING); + if (r != 0) { + DRM_ERROR("Failed to register fictitious range " + "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.agp_base, + (uintmax_t)rdev->mc.agp_base + rdev->mc.gtt_size, r); + return (-r); + } + rdev->fictitious_agp_range_registered = true; + } +#endif if ((radeon_testing & 1)) { radeon_test_moves(rdev); } if ((radeon_testing & 2)) { radeon_test_syncing(rdev); } if (radeon_benchmarking) { radeon_benchmark(rdev, radeon_benchmarking); } return 0; } #ifdef DUMBBELL_WIP static void radeon_debugfs_remove_files(struct radeon_device *rdev); #endif /* DUMBBELL_WIP */ /** * radeon_device_fini - tear down the driver * * @rdev: radeon_device pointer * * Tear down the driver info (all asics). * Called at driver shutdown. */ void radeon_device_fini(struct radeon_device *rdev) { DRM_INFO("radeon: finishing device.\n"); rdev->shutdown = true; /* evict vram memory */ radeon_bo_evict_vram(rdev); if (rdev->fictitious_range_registered) { vm_phys_fictitious_unreg_range( rdev->mc.aper_base, rdev->mc.aper_base + rdev->mc.visible_vram_size); } +#if __OS_HAS_AGP + if (rdev->fictitious_agp_range_registered) { + vm_phys_fictitious_unreg_range( + rdev->mc.agp_base, + rdev->mc.agp_base + rdev->mc.gtt_size); + } +#endif radeon_fini(rdev); #ifdef DUMBBELL_WIP vga_switcheroo_unregister_client(rdev->pdev); vga_client_register(rdev->pdev, NULL, NULL, NULL); #endif /* DUMBBELL_WIP */ if (rdev->tq != NULL) { taskqueue_free(rdev->tq); rdev->tq = NULL; } if (rdev->rio_mem) bus_release_resource(rdev->dev, SYS_RES_IOPORT, rdev->rio_rid, rdev->rio_mem); rdev->rio_mem = NULL; bus_release_resource(rdev->dev, SYS_RES_MEMORY, rdev->rmmio_rid, rdev->rmmio); rdev->rmmio = NULL; #ifdef DUMBBELL_WIP radeon_debugfs_remove_files(rdev); #endif /* DUMBBELL_WIP */ } /* * Suspend & resume. */ /** * radeon_suspend_kms - initiate device suspend * * @pdev: drm dev pointer * @state: suspend state * * Puts the hw in the suspend state (all asics). * Returns 0 for success or an error on failure. * Called at driver suspend. */ int radeon_suspend_kms(struct drm_device *dev) { struct radeon_device *rdev; struct drm_crtc *crtc; struct drm_connector *connector; int i, r; bool force_completion = false; if (dev == NULL || dev->dev_private == NULL) { return -ENODEV; } #ifdef DUMBBELL_WIP if (state.event == PM_EVENT_PRETHAW) { return 0; } #endif /* DUMBBELL_WIP */ rdev = dev->dev_private; if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) return 0; drm_kms_helper_poll_disable(dev); /* turn off display hw */ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); } /* unpin the front buffers */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); struct radeon_bo *robj; if (rfb == NULL || rfb->obj == NULL) { continue; } robj = gem_to_radeon_bo(rfb->obj); /* don't unpin kernel fb objects */ if (!radeon_fbdev_robj_is_fb(rdev, robj)) { r = radeon_bo_reserve(robj, false); if (r == 0) { radeon_bo_unpin(robj); radeon_bo_unreserve(robj); } } } /* evict vram memory */ radeon_bo_evict_vram(rdev); sx_xlock(&rdev->ring_lock); /* wait for gpu to finish processing current batch */ for (i = 0; i < RADEON_NUM_RINGS; i++) { r = radeon_fence_wait_empty_locked(rdev, i); if (r) { /* delay GPU reset to resume */ force_completion = true; } } if (force_completion) { radeon_fence_driver_force_completion(rdev); } sx_xunlock(&rdev->ring_lock); radeon_save_bios_scratch_regs(rdev); radeon_pm_suspend(rdev); radeon_suspend(rdev); radeon_hpd_fini(rdev); /* evict remaining vram memory */ radeon_bo_evict_vram(rdev); radeon_agp_suspend(rdev); pci_save_state(device_get_parent(rdev->dev)); #ifdef DUMBBELL_WIP if (state.event == PM_EVENT_SUSPEND) { /* Shut down the device */ pci_disable_device(dev->pdev); #endif /* DUMBBELL_WIP */ pci_set_powerstate(dev->device, PCI_POWERSTATE_D3); #ifdef DUMBBELL_WIP } console_lock(); #endif /* DUMBBELL_WIP */ radeon_fbdev_set_suspend(rdev, 1); #ifdef DUMBBELL_WIP console_unlock(); #endif /* DUMBBELL_WIP */ return 0; } /** * radeon_resume_kms - initiate device resume * * @pdev: drm dev pointer * * Bring the hw back to operating state (all asics). * Returns 0 for success or an error on failure. * Called at driver resume. */ int radeon_resume_kms(struct drm_device *dev) { struct drm_connector *connector; struct radeon_device *rdev = dev->dev_private; int r; if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) return 0; #ifdef DUMBBELL_WIP console_lock(); #endif /* DUMBBELL_WIP */ pci_set_powerstate(dev->device, PCI_POWERSTATE_D0); pci_restore_state(device_get_parent(rdev->dev)); #ifdef DUMBBELL_WIP if (pci_enable_device(dev->pdev)) { console_unlock(); return -1; } #endif /* DUMBBELL_WIP */ /* resume AGP if in use */ radeon_agp_resume(rdev); radeon_resume(rdev); r = radeon_ib_ring_tests(rdev); if (r) DRM_ERROR("ib ring test failed (%d).\n", r); radeon_pm_resume(rdev); radeon_restore_bios_scratch_regs(rdev); radeon_fbdev_set_suspend(rdev, 0); #ifdef DUMBBELL_WIP console_unlock(); #endif /* DUMBBELL_WIP */ /* init dig PHYs, disp eng pll */ if (rdev->is_atom_bios) { radeon_atom_encoder_init(rdev); radeon_atom_disp_eng_pll_init(rdev); /* turn on the BL */ if (rdev->mode_info.bl_encoder) { u8 bl_level = radeon_get_backlight_level(rdev, rdev->mode_info.bl_encoder); radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, bl_level); } } /* reset hpd state */ radeon_hpd_init(rdev); /* blat the mode back in */ drm_helper_resume_force_mode(dev); /* turn on display hw */ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); } drm_kms_helper_poll_enable(dev); return 0; } /** * radeon_gpu_reset - reset the asic * * @rdev: radeon device pointer * * Attempt the reset the GPU if it has hung (all asics). * Returns 0 for success or an error on failure. */ int radeon_gpu_reset(struct radeon_device *rdev) { unsigned ring_sizes[RADEON_NUM_RINGS]; uint32_t *ring_data[RADEON_NUM_RINGS]; bool saved = false; int i, r; int resched; sx_xlock(&rdev->exclusive_lock); radeon_save_bios_scratch_regs(rdev); /* block TTM */ resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); radeon_suspend(rdev); for (i = 0; i < RADEON_NUM_RINGS; ++i) { ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], &ring_data[i]); if (ring_sizes[i]) { saved = true; dev_info(rdev->dev, "Saved %d dwords of commands " "on ring %d.\n", ring_sizes[i], i); } } retry: r = radeon_asic_reset(rdev); if (!r) { dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); radeon_resume(rdev); } radeon_restore_bios_scratch_regs(rdev); if (!r) { for (i = 0; i < RADEON_NUM_RINGS; ++i) { radeon_ring_restore(rdev, &rdev->ring[i], ring_sizes[i], ring_data[i]); ring_sizes[i] = 0; ring_data[i] = NULL; } r = radeon_ib_ring_tests(rdev); if (r) { dev_err(rdev->dev, "ib ring test failed (%d).\n", r); if (saved) { saved = false; radeon_suspend(rdev); goto retry; } } } else { radeon_fence_driver_force_completion(rdev); for (i = 0; i < RADEON_NUM_RINGS; ++i) { free(ring_data[i], DRM_MEM_DRIVER); } } drm_helper_resume_force_mode(rdev->ddev); ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); if (r) { /* bad news, how to tell it to userspace ? */ dev_info(rdev->dev, "GPU reset failed\n"); } sx_xunlock(&rdev->exclusive_lock); return r; } /* * Debugfs */ #ifdef DUMBBELL_WIP int radeon_debugfs_add_files(struct radeon_device *rdev, struct drm_info_list *files, unsigned nfiles) { unsigned i; for (i = 0; i < rdev->debugfs_count; i++) { if (rdev->debugfs[i].files == files) { /* Already registered */ return 0; } } i = rdev->debugfs_count + 1; if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { DRM_ERROR("Reached maximum number of debugfs components.\n"); DRM_ERROR("Report so we increase " "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); return -EINVAL; } rdev->debugfs[rdev->debugfs_count].files = files; rdev->debugfs[rdev->debugfs_count].num_files = nfiles; rdev->debugfs_count = i; #if defined(CONFIG_DEBUG_FS) drm_debugfs_create_files(files, nfiles, rdev->ddev->control->debugfs_root, rdev->ddev->control); drm_debugfs_create_files(files, nfiles, rdev->ddev->primary->debugfs_root, rdev->ddev->primary); #endif return 0; } static void radeon_debugfs_remove_files(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) unsigned i; for (i = 0; i < rdev->debugfs_count; i++) { drm_debugfs_remove_files(rdev->debugfs[i].files, rdev->debugfs[i].num_files, rdev->ddev->control); drm_debugfs_remove_files(rdev->debugfs[i].files, rdev->debugfs[i].num_files, rdev->ddev->primary); } #endif } #if defined(CONFIG_DEBUG_FS) int radeon_debugfs_init(struct drm_minor *minor) { return 0; } void radeon_debugfs_cleanup(struct drm_minor *minor) { } #endif /* DUMBBELL_WIP */ #endif Index: head/sys/dev/drm2/radeon/radeon_ttm.c =================================================================== --- head/sys/dev/drm2/radeon/radeon_ttm.c (revision 273861) +++ head/sys/dev/drm2/radeon/radeon_ttm.c (revision 273862) @@ -1,931 +1,925 @@ /* * Copyright 2009 Jerome Glisse. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * */ /* * Authors: * Jerome Glisse * Thomas Hellstrom * Dave Airlie */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include "radeon_reg.h" #include "radeon.h" #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) static int radeon_ttm_debugfs_init(struct radeon_device *rdev); static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) { struct radeon_mman *mman; struct radeon_device *rdev; mman = container_of(bdev, struct radeon_mman, bdev); rdev = container_of(mman, struct radeon_device, mman); return rdev; } /* * Global memory. */ static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) { return ttm_mem_global_init(ref->object); } static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) { ttm_mem_global_release(ref->object); } static int radeon_ttm_global_init(struct radeon_device *rdev) { struct drm_global_reference *global_ref; int r; rdev->mman.mem_global_referenced = false; global_ref = &rdev->mman.mem_global_ref; global_ref->global_type = DRM_GLOBAL_TTM_MEM; global_ref->size = sizeof(struct ttm_mem_global); global_ref->init = &radeon_ttm_mem_global_init; global_ref->release = &radeon_ttm_mem_global_release; r = drm_global_item_ref(global_ref); if (r != 0) { DRM_ERROR("Failed setting up TTM memory accounting " "subsystem.\n"); return r; } rdev->mman.bo_global_ref.mem_glob = rdev->mman.mem_global_ref.object; global_ref = &rdev->mman.bo_global_ref.ref; global_ref->global_type = DRM_GLOBAL_TTM_BO; global_ref->size = sizeof(struct ttm_bo_global); global_ref->init = &ttm_bo_global_init; global_ref->release = &ttm_bo_global_release; r = drm_global_item_ref(global_ref); if (r != 0) { DRM_ERROR("Failed setting up TTM BO subsystem.\n"); drm_global_item_unref(&rdev->mman.mem_global_ref); return r; } rdev->mman.mem_global_referenced = true; return 0; } static void radeon_ttm_global_fini(struct radeon_device *rdev) { if (rdev->mman.mem_global_referenced) { drm_global_item_unref(&rdev->mman.bo_global_ref.ref); drm_global_item_unref(&rdev->mman.mem_global_ref); rdev->mman.mem_global_referenced = false; } } static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) { return 0; } static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, struct ttm_mem_type_manager *man) { struct radeon_device *rdev; rdev = radeon_get_rdev(bdev); switch (type) { case TTM_PL_SYSTEM: /* System memory */ man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; man->available_caching = TTM_PL_MASK_CACHING; man->default_caching = TTM_PL_FLAG_CACHED; break; case TTM_PL_TT: man->func = &ttm_bo_manager_func; man->gpu_offset = rdev->mc.gtt_start; man->available_caching = TTM_PL_MASK_CACHING; man->default_caching = TTM_PL_FLAG_CACHED; man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; #if __OS_HAS_AGP if (rdev->flags & RADEON_IS_AGP) { if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { DRM_ERROR("AGP is not enabled for memory type %u\n", (unsigned)type); return -EINVAL; } if (!rdev->ddev->agp->cant_use_aperture) man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; man->default_caching = TTM_PL_FLAG_WC; } #endif break; case TTM_PL_VRAM: /* "On-card" video ram */ man->func = &ttm_bo_manager_func; man->gpu_offset = rdev->mc.vram_start; man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_MAPPABLE; man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; man->default_caching = TTM_PL_FLAG_WC; break; default: DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); return -EINVAL; } return 0; } static void radeon_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *placement) { struct radeon_bo *rbo; static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; if (!radeon_ttm_bo_is_radeon_bo(bo)) { placement->fpfn = 0; placement->lpfn = 0; placement->placement = &placements; placement->busy_placement = &placements; placement->num_placement = 1; placement->num_busy_placement = 1; return; } rbo = container_of(bo, struct radeon_bo, tbo); switch (bo->mem.mem_type) { case TTM_PL_VRAM: if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); else radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); break; case TTM_PL_TT: default: radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); } *placement = rbo->placement; } static int radeon_verify_access(struct ttm_buffer_object *bo) { return 0; } static void radeon_move_null(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) { struct ttm_mem_reg *old_mem = &bo->mem; KASSERT(old_mem->mm_node == NULL, ("old_mem->mm_node != NULL")); *old_mem = *new_mem; new_mem->mm_node = NULL; } static int radeon_move_blit(struct ttm_buffer_object *bo, bool evict, bool no_wait_gpu, struct ttm_mem_reg *new_mem, struct ttm_mem_reg *old_mem) { struct radeon_device *rdev; uint64_t old_start, new_start; struct radeon_fence *fence; int r, ridx; rdev = radeon_get_rdev(bo->bdev); ridx = radeon_copy_ring_index(rdev); old_start = old_mem->start << PAGE_SHIFT; new_start = new_mem->start << PAGE_SHIFT; switch (old_mem->mem_type) { case TTM_PL_VRAM: old_start += rdev->mc.vram_start; break; case TTM_PL_TT: old_start += rdev->mc.gtt_start; break; default: DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); return -EINVAL; } switch (new_mem->mem_type) { case TTM_PL_VRAM: new_start += rdev->mc.vram_start; break; case TTM_PL_TT: new_start += rdev->mc.gtt_start; break; default: DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); return -EINVAL; } if (!rdev->ring[ridx].ready) { DRM_ERROR("Trying to move memory with ring turned off.\n"); return -EINVAL; } CTASSERT((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) == 0); /* sync other rings */ fence = bo->sync_obj; r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ &fence); /* FIXME: handle copy error */ r = ttm_bo_move_accel_cleanup(bo, (void *)fence, evict, no_wait_gpu, new_mem); radeon_fence_unref(&fence); return r; } static int radeon_move_vram_ram(struct ttm_buffer_object *bo, bool evict, bool interruptible, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { struct radeon_device *rdev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; u32 placements; struct ttm_placement placement; int r; rdev = radeon_get_rdev(bo->bdev); tmp_mem = *new_mem; tmp_mem.mm_node = NULL; placement.fpfn = 0; placement.lpfn = 0; placement.num_placement = 1; placement.placement = &placements; placement.num_busy_placement = 1; placement.busy_placement = &placements; placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_gpu); if (unlikely(r)) { return r; } r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); if (unlikely(r)) { goto out_cleanup; } r = ttm_tt_bind(bo->ttm, &tmp_mem); if (unlikely(r)) { goto out_cleanup; } r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); if (unlikely(r)) { goto out_cleanup; } r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); out_cleanup: ttm_bo_mem_put(bo, &tmp_mem); return r; } static int radeon_move_ram_vram(struct ttm_buffer_object *bo, bool evict, bool interruptible, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { struct radeon_device *rdev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; struct ttm_placement placement; u32 placements; int r; rdev = radeon_get_rdev(bo->bdev); tmp_mem = *new_mem; tmp_mem.mm_node = NULL; placement.fpfn = 0; placement.lpfn = 0; placement.num_placement = 1; placement.placement = &placements; placement.num_busy_placement = 1; placement.busy_placement = &placements; placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_gpu); if (unlikely(r)) { return r; } r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); if (unlikely(r)) { goto out_cleanup; } r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); if (unlikely(r)) { goto out_cleanup; } out_cleanup: ttm_bo_mem_put(bo, &tmp_mem); return r; } static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, bool interruptible, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { struct radeon_device *rdev; struct ttm_mem_reg *old_mem = &bo->mem; int r; rdev = radeon_get_rdev(bo->bdev); if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { radeon_move_null(bo, new_mem); return 0; } if ((old_mem->mem_type == TTM_PL_TT && new_mem->mem_type == TTM_PL_SYSTEM) || (old_mem->mem_type == TTM_PL_SYSTEM && new_mem->mem_type == TTM_PL_TT)) { /* bind is enough */ radeon_move_null(bo, new_mem); return 0; } if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || rdev->asic->copy.copy == NULL) { /* use memcpy */ goto memcpy; } if (old_mem->mem_type == TTM_PL_VRAM && new_mem->mem_type == TTM_PL_SYSTEM) { r = radeon_move_vram_ram(bo, evict, interruptible, no_wait_gpu, new_mem); } else if (old_mem->mem_type == TTM_PL_SYSTEM && new_mem->mem_type == TTM_PL_VRAM) { r = radeon_move_ram_vram(bo, evict, interruptible, no_wait_gpu, new_mem); } else { r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); } if (r) { memcpy: r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); } return r; } static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) { struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; struct radeon_device *rdev = radeon_get_rdev(bdev); mem->bus.addr = NULL; mem->bus.offset = 0; mem->bus.size = mem->num_pages << PAGE_SHIFT; mem->bus.base = 0; mem->bus.is_iomem = false; if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) return -EINVAL; switch (mem->mem_type) { case TTM_PL_SYSTEM: /* system memory */ return 0; case TTM_PL_TT: #if __OS_HAS_AGP if (rdev->flags & RADEON_IS_AGP) { /* RADEON_IS_AGP is set only if AGP is active */ mem->bus.offset = mem->start << PAGE_SHIFT; mem->bus.base = rdev->mc.agp_base; mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; } #endif break; case TTM_PL_VRAM: mem->bus.offset = mem->start << PAGE_SHIFT; /* check if it's visible */ if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) return -EINVAL; mem->bus.base = rdev->mc.aper_base; mem->bus.is_iomem = true; #ifdef __alpha__ /* * Alpha: use bus.addr to hold the ioremap() return, * so we can modify bus.base below. */ if (mem->placement & TTM_PL_FLAG_WC) mem->bus.addr = ioremap_wc(mem->bus.base + mem->bus.offset, mem->bus.size); else mem->bus.addr = ioremap_nocache(mem->bus.base + mem->bus.offset, mem->bus.size); /* * Alpha: Use just the bus offset plus * the hose/domain memory base for bus.base. * It then can be used to build PTEs for VRAM * access, as done in ttm_bo_vm_fault(). */ mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + rdev->ddev->hose->dense_mem_base; #endif break; default: return -EINVAL; } return 0; } static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) { } static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) { return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); } static int radeon_sync_obj_flush(void *sync_obj) { return 0; } static void radeon_sync_obj_unref(void **sync_obj) { radeon_fence_unref((struct radeon_fence **)sync_obj); } static void *radeon_sync_obj_ref(void *sync_obj) { return radeon_fence_ref((struct radeon_fence *)sync_obj); } static bool radeon_sync_obj_signaled(void *sync_obj) { return radeon_fence_signaled((struct radeon_fence *)sync_obj); } /* * TTM backend functions. */ struct radeon_ttm_tt { struct ttm_dma_tt ttm; struct radeon_device *rdev; u64 offset; }; static int radeon_ttm_backend_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) { struct radeon_ttm_tt *gtt = (void*)ttm; int r; gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); if (!ttm->num_pages) { DRM_ERROR("nothing to bind %lu pages for mreg %p back %p!\n", ttm->num_pages, bo_mem, ttm); } r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, ttm->pages, gtt->ttm.dma_address); if (r) { DRM_ERROR("failed to bind %lu pages at 0x%08X\n", ttm->num_pages, (unsigned)gtt->offset); return r; } return 0; } static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) { struct radeon_ttm_tt *gtt = (void *)ttm; radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); return 0; } static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) { struct radeon_ttm_tt *gtt = (void *)ttm; ttm_dma_tt_fini(>t->ttm); free(gtt, DRM_MEM_DRIVER); } static struct ttm_backend_func radeon_backend_func = { .bind = &radeon_ttm_backend_bind, .unbind = &radeon_ttm_backend_unbind, .destroy = &radeon_ttm_backend_destroy, }; static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, uint32_t page_flags, vm_page_t dummy_read_page) { struct radeon_device *rdev; struct radeon_ttm_tt *gtt; rdev = radeon_get_rdev(bdev); #if __OS_HAS_AGP -#ifdef DUMBBELL_WIP if (rdev->flags & RADEON_IS_AGP) { return ttm_agp_tt_create(bdev, rdev->ddev->agp->agpdev, size, page_flags, dummy_read_page); } -#endif /* DUMBBELL_WIP */ #endif gtt = malloc(sizeof(struct radeon_ttm_tt), DRM_MEM_DRIVER, M_WAITOK | M_ZERO); if (gtt == NULL) { return NULL; } gtt->ttm.ttm.func = &radeon_backend_func; gtt->rdev = rdev; if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { free(gtt, DRM_MEM_DRIVER); return NULL; } return >t->ttm.ttm; } static int radeon_ttm_tt_populate(struct ttm_tt *ttm) { struct radeon_device *rdev; struct radeon_ttm_tt *gtt = (void *)ttm; unsigned i; int r; #ifdef DUMBBELL_WIP bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); #endif /* DUMBBELL_WIP */ if (ttm->state != tt_unpopulated) return 0; #ifdef DUMBBELL_WIP /* * Maybe unneeded on FreeBSD. * -- dumbbell@ */ if (slave && ttm->sg) { drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, gtt->ttm.dma_address, ttm->num_pages); ttm->state = tt_unbound; return 0; } #endif /* DUMBBELL_WIP */ rdev = radeon_get_rdev(ttm->bdev); #if __OS_HAS_AGP -#ifdef DUMBBELL_WIP if (rdev->flags & RADEON_IS_AGP) { return ttm_agp_tt_populate(ttm); } -#endif /* DUMBBELL_WIP */ #endif #ifdef CONFIG_SWIOTLB if (swiotlb_nr_tbl()) { return ttm_dma_populate(>t->ttm, rdev->dev); } #endif r = ttm_pool_populate(ttm); if (r) { return r; } for (i = 0; i < ttm->num_pages; i++) { gtt->ttm.dma_address[i] = VM_PAGE_TO_PHYS(ttm->pages[i]); #ifdef DUMBBELL_WIP gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { while (--i) { pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); gtt->ttm.dma_address[i] = 0; } ttm_pool_unpopulate(ttm); return -EFAULT; } #endif /* DUMBBELL_WIP */ } return 0; } static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) { struct radeon_device *rdev; struct radeon_ttm_tt *gtt = (void *)ttm; unsigned i; bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); if (slave) return; rdev = radeon_get_rdev(ttm->bdev); #if __OS_HAS_AGP -#ifdef DUMBBELL_WIP if (rdev->flags & RADEON_IS_AGP) { ttm_agp_tt_unpopulate(ttm); return; } -#endif /* DUMBBELL_WIP */ #endif #ifdef CONFIG_SWIOTLB if (swiotlb_nr_tbl()) { ttm_dma_unpopulate(>t->ttm, rdev->dev); return; } #endif for (i = 0; i < ttm->num_pages; i++) { if (gtt->ttm.dma_address[i]) { gtt->ttm.dma_address[i] = 0; #ifdef DUMBBELL_WIP pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); #endif /* DUMBBELL_WIP */ } } ttm_pool_unpopulate(ttm); } static struct ttm_bo_driver radeon_bo_driver = { .ttm_tt_create = &radeon_ttm_tt_create, .ttm_tt_populate = &radeon_ttm_tt_populate, .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, .invalidate_caches = &radeon_invalidate_caches, .init_mem_type = &radeon_init_mem_type, .evict_flags = &radeon_evict_flags, .move = &radeon_bo_move, .verify_access = &radeon_verify_access, .sync_obj_signaled = &radeon_sync_obj_signaled, .sync_obj_wait = &radeon_sync_obj_wait, .sync_obj_flush = &radeon_sync_obj_flush, .sync_obj_unref = &radeon_sync_obj_unref, .sync_obj_ref = &radeon_sync_obj_ref, .move_notify = &radeon_bo_move_notify, .fault_reserve_notify = &radeon_bo_fault_reserve_notify, .io_mem_reserve = &radeon_ttm_io_mem_reserve, .io_mem_free = &radeon_ttm_io_mem_free, }; int radeon_ttm_init(struct radeon_device *rdev) { int r, r2; r = radeon_ttm_global_init(rdev); if (r) { return r; } /* No others user of address space so set it to 0 */ r = ttm_bo_device_init(&rdev->mman.bdev, rdev->mman.bo_global_ref.ref.object, &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, rdev->need_dma32); if (r) { DRM_ERROR("failed initializing buffer object driver(%d).\n", r); return r; } rdev->mman.initialized = true; rdev->ddev->drm_ttm_bdev = &rdev->mman.bdev; r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, rdev->mc.real_vram_size >> PAGE_SHIFT); if (r) { DRM_ERROR("Failed initializing VRAM heap.\n"); return r; } r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->stollen_vga_memory); if (r) { return r; } r = radeon_bo_reserve(rdev->stollen_vga_memory, false); if (r) { radeon_bo_unref(&rdev->stollen_vga_memory); return r; } r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); radeon_bo_unreserve(rdev->stollen_vga_memory); if (r) { radeon_bo_unref(&rdev->stollen_vga_memory); return r; } DRM_INFO("radeon: %uM of VRAM memory ready\n", (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, rdev->mc.gtt_size >> PAGE_SHIFT); if (r) { DRM_ERROR("Failed initializing GTT heap.\n"); r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false); if (likely(r2 == 0)) { radeon_bo_unpin(rdev->stollen_vga_memory); radeon_bo_unreserve(rdev->stollen_vga_memory); } radeon_bo_unref(&rdev->stollen_vga_memory); return r; } DRM_INFO("radeon: %uM of GTT memory ready.\n", (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); r = radeon_ttm_debugfs_init(rdev); if (r) { DRM_ERROR("Failed to init debugfs\n"); r2 = radeon_bo_reserve(rdev->stollen_vga_memory, false); if (likely(r2 == 0)) { radeon_bo_unpin(rdev->stollen_vga_memory); radeon_bo_unreserve(rdev->stollen_vga_memory); } radeon_bo_unref(&rdev->stollen_vga_memory); return r; } return 0; } void radeon_ttm_fini(struct radeon_device *rdev) { int r; if (!rdev->mman.initialized) return; if (rdev->stollen_vga_memory) { r = radeon_bo_reserve(rdev->stollen_vga_memory, false); if (r == 0) { radeon_bo_unpin(rdev->stollen_vga_memory); radeon_bo_unreserve(rdev->stollen_vga_memory); } radeon_bo_unref(&rdev->stollen_vga_memory); } ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); ttm_bo_device_release(&rdev->mman.bdev); radeon_gart_fini(rdev); radeon_ttm_global_fini(rdev); rdev->mman.initialized = false; DRM_INFO("radeon: ttm finalized\n"); } /* this should only be called at bootup or when userspace * isn't running */ void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) { struct ttm_mem_type_manager *man; if (!rdev->mman.initialized) return; man = &rdev->mman.bdev.man[TTM_PL_VRAM]; /* this just adjusts TTM size idea, which sets lpfn to the correct value */ man->size = size >> PAGE_SHIFT; } #ifdef DUMBBELL_WIP static struct vm_operations_struct radeon_ttm_vm_ops; static const struct vm_operations_struct *ttm_vm_ops = NULL; static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) { struct ttm_buffer_object *bo; struct radeon_device *rdev; int r; bo = (struct ttm_buffer_object *)vma->vm_private_data; if (bo == NULL) { return VM_FAULT_NOPAGE; } rdev = radeon_get_rdev(bo->bdev); sx_slock(&rdev->pm.mclk_lock); r = ttm_vm_ops->fault(vma, vmf); sx_sunlock(&rdev->pm.mclk_lock); return r; } int radeon_mmap(struct file *filp, struct vm_area_struct *vma) { struct drm_file *file_priv; struct radeon_device *rdev; int r; if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { return drm_mmap(filp, vma); } file_priv = filp->private_data; rdev = file_priv->minor->dev->dev_private; if (rdev == NULL) { return -EINVAL; } r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); if (unlikely(r != 0)) { return r; } if (unlikely(ttm_vm_ops == NULL)) { ttm_vm_ops = vma->vm_ops; radeon_ttm_vm_ops = *ttm_vm_ops; radeon_ttm_vm_ops.fault = &radeon_ttm_fault; } vma->vm_ops = &radeon_ttm_vm_ops; return 0; } #endif /* DUMBBELL_WIP */ #define RADEON_DEBUGFS_MEM_TYPES 2 #if defined(CONFIG_DEBUG_FS) static int radeon_mm_dump_table(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *)m->private; struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; struct drm_device *dev = node->minor->dev; struct radeon_device *rdev = dev->dev_private; int ret; struct ttm_bo_global *glob = rdev->mman.bdev.glob; spin_lock(&glob->lru_lock); ret = drm_mm_dump_table(m, mm); spin_unlock(&glob->lru_lock); return ret; } #endif static int radeon_ttm_debugfs_init(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2]; static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32]; unsigned i; for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { if (i == 0) sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); else sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); radeon_mem_types_list[i].name = radeon_mem_types_names[i]; radeon_mem_types_list[i].show = &radeon_mm_dump_table; radeon_mem_types_list[i].driver_features = 0; if (i == 0) radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; else radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; } /* Add ttm page pool to debugfs */ sprintf(radeon_mem_types_names[i], "ttm_page_pool"); radeon_mem_types_list[i].name = radeon_mem_types_names[i]; radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; radeon_mem_types_list[i].driver_features = 0; radeon_mem_types_list[i++].data = NULL; #ifdef CONFIG_SWIOTLB if (swiotlb_nr_tbl()) { sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool"); radeon_mem_types_list[i].name = radeon_mem_types_names[i]; radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs; radeon_mem_types_list[i].driver_features = 0; radeon_mem_types_list[i++].data = NULL; } #endif return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i); #endif return 0; } Index: head/sys/dev/drm2/ttm/ttm_agp_backend.c =================================================================== --- head/sys/dev/drm2/ttm/ttm_agp_backend.c (revision 273861) +++ head/sys/dev/drm2/ttm/ttm_agp_backend.c (revision 273862) @@ -1,145 +1,136 @@ /************************************************************************** * * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * **************************************************************************/ /* * Authors: Thomas Hellstrom * Keith Packard. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #ifdef TTM_HAS_AGP #include struct ttm_agp_backend { struct ttm_tt ttm; - struct agp_memory *mem; + vm_offset_t offset; + vm_page_t *pages; device_t bridge; }; MALLOC_DEFINE(M_TTM_AGP, "ttm_agp", "TTM AGP Backend"); static int ttm_agp_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) { struct ttm_agp_backend *agp_be = container_of(ttm, struct ttm_agp_backend, ttm); struct drm_mm_node *node = bo_mem->mm_node; - struct agp_memory *mem; - int ret, cached = (bo_mem->placement & TTM_PL_FLAG_CACHED); + int ret; unsigned i; - mem = agp_alloc_memory(agp_be->bridge, AGP_USER_MEMORY, ttm->num_pages); - if (unlikely(mem == NULL)) - return -ENOMEM; - - mem->page_count = 0; for (i = 0; i < ttm->num_pages; i++) { vm_page_t page = ttm->pages[i]; if (!page) page = ttm->dummy_read_page; - mem->pages[mem->page_count++] = page; + agp_be->pages[i] = page; } - agp_be->mem = mem; - mem->is_flushed = 1; - mem->type = (cached) ? AGP_USER_CACHED_MEMORY : AGP_USER_MEMORY; - - ret = agp_bind_memory(mem, node->start); + agp_be->offset = node->start * PAGE_SIZE; + ret = -agp_bind_pages(agp_be->bridge, agp_be->pages, + ttm->num_pages << PAGE_SHIFT, agp_be->offset); if (ret) - pr_err("AGP Bind memory failed\n"); + printf("[TTM] AGP Bind memory failed\n"); return ret; } static int ttm_agp_unbind(struct ttm_tt *ttm) { struct ttm_agp_backend *agp_be = container_of(ttm, struct ttm_agp_backend, ttm); - if (agp_be->mem) { - if (agp_be->mem->is_bound) - return agp_unbind_memory(agp_be->mem); - agp_free_memory(agp_be->mem); - agp_be->mem = NULL; - } - return 0; + return -agp_unbind_pages(agp_be->bridge, ttm->num_pages << PAGE_SHIFT, + agp_be->offset); } static void ttm_agp_destroy(struct ttm_tt *ttm) { struct ttm_agp_backend *agp_be = container_of(ttm, struct ttm_agp_backend, ttm); - if (agp_be->mem) - ttm_agp_unbind(ttm); ttm_tt_fini(ttm); + free(agp_be->pages, M_TTM_AGP); free(agp_be, M_TTM_AGP); } static struct ttm_backend_func ttm_agp_func = { .bind = ttm_agp_bind, .unbind = ttm_agp_unbind, .destroy = ttm_agp_destroy, }; struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev, device_t bridge, unsigned long size, uint32_t page_flags, vm_page_t dummy_read_page) { struct ttm_agp_backend *agp_be; agp_be = malloc(sizeof(*agp_be), M_TTM_AGP, M_WAITOK | M_ZERO); - agp_be->mem = NULL; agp_be->bridge = bridge; agp_be->ttm.func = &ttm_agp_func; if (ttm_tt_init(&agp_be->ttm, bdev, size, page_flags, dummy_read_page)) { + free(agp_be, M_TTM_AGP); return NULL; } + + agp_be->offset = 0; + agp_be->pages = malloc(agp_be->ttm.num_pages * sizeof(*agp_be->pages), + M_TTM_AGP, M_WAITOK); return &agp_be->ttm; } int ttm_agp_tt_populate(struct ttm_tt *ttm) { if (ttm->state != tt_unpopulated) return 0; return ttm_pool_populate(ttm); } void ttm_agp_tt_unpopulate(struct ttm_tt *ttm) { ttm_pool_unpopulate(ttm); } #endif Index: head/sys/dev/drm2/ttm/ttm_bo_driver.h =================================================================== --- head/sys/dev/drm2/ttm/ttm_bo_driver.h (revision 273861) +++ head/sys/dev/drm2/ttm/ttm_bo_driver.h (revision 273862) @@ -1,1025 +1,1024 @@ /************************************************************************** * * Copyright (c) 2006-2009 Vmware, Inc., Palo Alto, CA., USA * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * **************************************************************************/ /* * Authors: Thomas Hellstrom */ /* $FreeBSD$ */ #ifndef _TTM_BO_DRIVER_H_ #define _TTM_BO_DRIVER_H_ #include #include #include #include #include #include #include struct ttm_backend_func { /** * struct ttm_backend_func member bind * * @ttm: Pointer to a struct ttm_tt. * @bo_mem: Pointer to a struct ttm_mem_reg describing the * memory type and location for binding. * * Bind the backend pages into the aperture in the location * indicated by @bo_mem. This function should be able to handle * differences between aperture and system page sizes. */ int (*bind) (struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem); /** * struct ttm_backend_func member unbind * * @ttm: Pointer to a struct ttm_tt. * * Unbind previously bound backend pages. This function should be * able to handle differences between aperture and system page sizes. */ int (*unbind) (struct ttm_tt *ttm); /** * struct ttm_backend_func member destroy * * @ttm: Pointer to a struct ttm_tt. * * Destroy the backend. This will be call back from ttm_tt_destroy so * don't call ttm_tt_destroy from the callback or infinite loop. */ void (*destroy) (struct ttm_tt *ttm); }; #define TTM_PAGE_FLAG_WRITE (1 << 3) #define TTM_PAGE_FLAG_SWAPPED (1 << 4) #define TTM_PAGE_FLAG_PERSISTENT_SWAP (1 << 5) #define TTM_PAGE_FLAG_ZERO_ALLOC (1 << 6) #define TTM_PAGE_FLAG_DMA32 (1 << 7) #define TTM_PAGE_FLAG_SG (1 << 8) enum ttm_caching_state { tt_uncached, tt_wc, tt_cached }; /** * struct ttm_tt * * @bdev: Pointer to a struct ttm_bo_device. * @func: Pointer to a struct ttm_backend_func that describes * the backend methods. * @dummy_read_page: Page to map where the ttm_tt page array contains a NULL * pointer. * @pages: Array of pages backing the data. * @num_pages: Number of pages in the page array. * @bdev: Pointer to the current struct ttm_bo_device. * @be: Pointer to the ttm backend. * @swap_storage: Pointer to shmem struct file for swap storage. * @caching_state: The current caching state of the pages. * @state: The current binding state of the pages. * * This is a structure holding the pages, caching- and aperture binding * status for a buffer object that isn't backed by fixed (VRAM / AGP) * memory. */ struct ttm_tt { struct ttm_bo_device *bdev; struct ttm_backend_func *func; struct vm_page *dummy_read_page; struct vm_page **pages; uint32_t page_flags; unsigned long num_pages; struct sg_table *sg; /* for SG objects via dma-buf */ struct ttm_bo_global *glob; struct vm_object *swap_storage; enum ttm_caching_state caching_state; enum { tt_bound, tt_unbound, tt_unpopulated, } state; }; /** * struct ttm_dma_tt * * @ttm: Base ttm_tt struct. * @dma_address: The DMA (bus) addresses of the pages * @pages_list: used by some page allocation backend * * This is a structure holding the pages, caching- and aperture binding * status for a buffer object that isn't backed by fixed (VRAM / AGP) * memory. */ struct ttm_dma_tt { struct ttm_tt ttm; dma_addr_t *dma_address; struct list_head pages_list; }; #define TTM_MEMTYPE_FLAG_FIXED (1 << 0) /* Fixed (on-card) PCI memory */ #define TTM_MEMTYPE_FLAG_MAPPABLE (1 << 1) /* Memory mappable */ #define TTM_MEMTYPE_FLAG_CMA (1 << 3) /* Can't map aperture */ struct ttm_mem_type_manager; struct ttm_mem_type_manager_func { /** * struct ttm_mem_type_manager member init * * @man: Pointer to a memory type manager. * @p_size: Implementation dependent, but typically the size of the * range to be managed in pages. * * Called to initialize a private range manager. The function is * expected to initialize the man::priv member. * Returns 0 on success, negative error code on failure. */ int (*init)(struct ttm_mem_type_manager *man, unsigned long p_size); /** * struct ttm_mem_type_manager member takedown * * @man: Pointer to a memory type manager. * * Called to undo the setup done in init. All allocated resources * should be freed. */ int (*takedown)(struct ttm_mem_type_manager *man); /** * struct ttm_mem_type_manager member get_node * * @man: Pointer to a memory type manager. * @bo: Pointer to the buffer object we're allocating space for. * @placement: Placement details. * @mem: Pointer to a struct ttm_mem_reg to be filled in. * * This function should allocate space in the memory type managed * by @man. Placement details if * applicable are given by @placement. If successful, * @mem::mm_node should be set to a non-null value, and * @mem::start should be set to a value identifying the beginning * of the range allocated, and the function should return zero. * If the memory region accommodate the buffer object, @mem::mm_node * should be set to NULL, and the function should return 0. * If a system error occurred, preventing the request to be fulfilled, * the function should return a negative error code. * * Note that @mem::mm_node will only be dereferenced by * struct ttm_mem_type_manager functions and optionally by the driver, * which has knowledge of the underlying type. * * This function may not be called from within atomic context, so * an implementation can and must use either a mutex or a spinlock to * protect any data structures managing the space. */ int (*get_node)(struct ttm_mem_type_manager *man, struct ttm_buffer_object *bo, struct ttm_placement *placement, struct ttm_mem_reg *mem); /** * struct ttm_mem_type_manager member put_node * * @man: Pointer to a memory type manager. * @mem: Pointer to a struct ttm_mem_reg to be filled in. * * This function frees memory type resources previously allocated * and that are identified by @mem::mm_node and @mem::start. May not * be called from within atomic context. */ void (*put_node)(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem); /** * struct ttm_mem_type_manager member debug * * @man: Pointer to a memory type manager. * @prefix: Prefix to be used in printout to identify the caller. * * This function is called to print out the state of the memory * type manager to aid debugging of out-of-memory conditions. * It may not be called from within atomic context. */ void (*debug)(struct ttm_mem_type_manager *man, const char *prefix); }; /** * struct ttm_mem_type_manager * * @has_type: The memory type has been initialized. * @use_type: The memory type is enabled. * @flags: TTM_MEMTYPE_XX flags identifying the traits of the memory * managed by this memory type. * @gpu_offset: If used, the GPU offset of the first managed page of * fixed memory or the first managed location in an aperture. * @size: Size of the managed region. * @available_caching: A mask of available caching types, TTM_PL_FLAG_XX, * as defined in ttm_placement_common.h * @default_caching: The default caching policy used for a buffer object * placed in this memory type if the user doesn't provide one. * @func: structure pointer implementing the range manager. See above * @priv: Driver private closure for @func. * @io_reserve_mutex: Mutex optionally protecting shared io_reserve structures * @use_io_reserve_lru: Use an lru list to try to unreserve io_mem_regions * reserved by the TTM vm system. * @io_reserve_lru: Optional lru list for unreserving io mem regions. * @io_reserve_fastpath: Only use bdev::driver::io_mem_reserve to obtain * static information. bdev::driver::io_mem_free is never used. * @lru: The lru list for this memory type. * * This structure is used to identify and manage memory types for a device. * It's set up by the ttm_bo_driver::init_mem_type method. */ struct ttm_mem_type_manager { struct ttm_bo_device *bdev; /* * No protection. Constant from start. */ bool has_type; bool use_type; uint32_t flags; unsigned long gpu_offset; uint64_t size; uint32_t available_caching; uint32_t default_caching; const struct ttm_mem_type_manager_func *func; void *priv; struct sx io_reserve_mutex; bool use_io_reserve_lru; bool io_reserve_fastpath; /* * Protected by @io_reserve_mutex: */ struct list_head io_reserve_lru; /* * Protected by the global->lru_lock. */ struct list_head lru; }; /** * struct ttm_bo_driver * * @create_ttm_backend_entry: Callback to create a struct ttm_backend. * @invalidate_caches: Callback to invalidate read caches when a buffer object * has been evicted. * @init_mem_type: Callback to initialize a struct ttm_mem_type_manager * structure. * @evict_flags: Callback to obtain placement flags when a buffer is evicted. * @move: Callback for a driver to hook in accelerated functions to * move a buffer. * If set to NULL, a potentially slow memcpy() move is used. * @sync_obj_signaled: See ttm_fence_api.h * @sync_obj_wait: See ttm_fence_api.h * @sync_obj_flush: See ttm_fence_api.h * @sync_obj_unref: See ttm_fence_api.h * @sync_obj_ref: See ttm_fence_api.h */ struct ttm_bo_driver { /** * ttm_tt_create * * @bdev: pointer to a struct ttm_bo_device: * @size: Size of the data needed backing. * @page_flags: Page flags as identified by TTM_PAGE_FLAG_XX flags. * @dummy_read_page: See struct ttm_bo_device. * * Create a struct ttm_tt to back data with system memory pages. * No pages are actually allocated. * Returns: * NULL: Out of memory. */ struct ttm_tt *(*ttm_tt_create)(struct ttm_bo_device *bdev, unsigned long size, uint32_t page_flags, struct vm_page *dummy_read_page); /** * ttm_tt_populate * * @ttm: The struct ttm_tt to contain the backing pages. * * Allocate all backing pages * Returns: * -ENOMEM: Out of memory. */ int (*ttm_tt_populate)(struct ttm_tt *ttm); /** * ttm_tt_unpopulate * * @ttm: The struct ttm_tt to contain the backing pages. * * Free all backing page */ void (*ttm_tt_unpopulate)(struct ttm_tt *ttm); /** * struct ttm_bo_driver member invalidate_caches * * @bdev: the buffer object device. * @flags: new placement of the rebound buffer object. * * A previosly evicted buffer has been rebound in a * potentially new location. Tell the driver that it might * consider invalidating read (texture) caches on the next command * submission as a consequence. */ int (*invalidate_caches) (struct ttm_bo_device *bdev, uint32_t flags); int (*init_mem_type) (struct ttm_bo_device *bdev, uint32_t type, struct ttm_mem_type_manager *man); /** * struct ttm_bo_driver member evict_flags: * * @bo: the buffer object to be evicted * * Return the bo flags for a buffer which is not mapped to the hardware. * These will be placed in proposed_flags so that when the move is * finished, they'll end up in bo->mem.flags */ void(*evict_flags) (struct ttm_buffer_object *bo, struct ttm_placement *placement); /** * struct ttm_bo_driver member move: * * @bo: the buffer to move * @evict: whether this motion is evicting the buffer from * the graphics address space * @interruptible: Use interruptible sleeps if possible when sleeping. * @no_wait: whether this should give up and return -EBUSY * if this move would require sleeping * @new_mem: the new memory region receiving the buffer * * Move a buffer between two memory regions. */ int (*move) (struct ttm_buffer_object *bo, bool evict, bool interruptible, bool no_wait_gpu, struct ttm_mem_reg *new_mem); /** * struct ttm_bo_driver_member verify_access * * @bo: Pointer to a buffer object. * @filp: Pointer to a struct file trying to access the object. * FreeBSD: use devfs_get_cdevpriv etc. * * Called from the map / write / read methods to verify that the * caller is permitted to access the buffer object. * This member may be set to NULL, which will refuse this kind of * access for all buffer objects. * This function should return 0 if access is granted, -EPERM otherwise. */ int (*verify_access) (struct ttm_buffer_object *bo); /** * In case a driver writer dislikes the TTM fence objects, * the driver writer can replace those with sync objects of * his / her own. If it turns out that no driver writer is * using these. I suggest we remove these hooks and plug in * fences directly. The bo driver needs the following functionality: * See the corresponding functions in the fence object API * documentation. */ bool (*sync_obj_signaled) (void *sync_obj); int (*sync_obj_wait) (void *sync_obj, bool lazy, bool interruptible); int (*sync_obj_flush) (void *sync_obj); void (*sync_obj_unref) (void **sync_obj); void *(*sync_obj_ref) (void *sync_obj); /* hook to notify driver about a driver move so it * can do tiling things */ void (*move_notify)(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem); /* notify the driver we are taking a fault on this BO * and have reserved it */ int (*fault_reserve_notify)(struct ttm_buffer_object *bo); /** * notify the driver that we're about to swap out this bo */ void (*swap_notify) (struct ttm_buffer_object *bo); /** * Driver callback on when mapping io memory (for bo_move_memcpy * for instance). TTM will take care to call io_mem_free whenever * the mapping is not use anymore. io_mem_reserve & io_mem_free * are balanced. */ int (*io_mem_reserve)(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem); void (*io_mem_free)(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem); }; /** * struct ttm_bo_global_ref - Argument to initialize a struct ttm_bo_global. */ struct ttm_bo_global_ref { struct drm_global_reference ref; struct ttm_mem_global *mem_glob; }; /** * struct ttm_bo_global - Buffer object driver global data. * * @mem_glob: Pointer to a struct ttm_mem_global object for accounting. * @dummy_read_page: Pointer to a dummy page used for mapping requests * of unpopulated pages. * @shrink: A shrink callback object used for buffer object swap. * @device_list_mutex: Mutex protecting the device list. * This mutex is held while traversing the device list for pm options. * @lru_lock: Spinlock protecting the bo subsystem lru lists. * @device_list: List of buffer object devices. * @swap_lru: Lru list of buffer objects used for swapping. */ struct ttm_bo_global { u_int kobj_ref; /** * Constant after init. */ struct ttm_mem_global *mem_glob; struct vm_page *dummy_read_page; struct ttm_mem_shrink shrink; struct sx device_list_mutex; struct mtx lru_lock; /** * Protected by device_list_mutex. */ struct list_head device_list; /** * Protected by the lru_lock. */ struct list_head swap_lru; /** * Internal protection. */ atomic_t bo_count; }; #define TTM_NUM_MEM_TYPES 8 #define TTM_BO_PRIV_FLAG_MOVING 0 /* Buffer object is moving and needs idling before CPU mapping */ #define TTM_BO_PRIV_FLAG_MAX 1 /** * struct ttm_bo_device - Buffer object driver device-specific data. * * @driver: Pointer to a struct ttm_bo_driver struct setup by the driver. * @man: An array of mem_type_managers. * @fence_lock: Protects the synchronizing members on *all* bos belonging * to this device. * @addr_space_mm: Range manager for the device address space. * lru_lock: Spinlock that protects the buffer+device lru lists and * ddestroy lists. * @val_seq: Current validation sequence. * @dev_mapping: A pointer to the struct address_space representing the * device address space. * @wq: Work queue structure for the delayed delete workqueue. * */ struct ttm_bo_device { /* * Constant after bo device init / atomic. */ struct list_head device_list; struct ttm_bo_global *glob; struct ttm_bo_driver *driver; struct rwlock vm_lock; struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES]; struct mtx fence_lock; /* * Protected by the vm lock. */ RB_HEAD(ttm_bo_device_buffer_objects, ttm_buffer_object) addr_space_rb; struct drm_mm addr_space_mm; /* * Protected by the global:lru lock. */ struct list_head ddestroy; uint32_t val_seq; /* * Protected by load / firstopen / lastclose /unload sync. */ struct address_space *dev_mapping; /* * Internal protection. */ struct timeout_task wq; bool need_dma32; }; /** * ttm_flag_masked * * @old: Pointer to the result and original value. * @new: New value of bits. * @mask: Mask of bits to change. * * Convenience function to change a number of bits identified by a mask. */ static inline uint32_t ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t mask) { *old ^= (*old ^ new) & mask; return *old; } /** * ttm_tt_init * * @ttm: The struct ttm_tt. * @bdev: pointer to a struct ttm_bo_device: * @size: Size of the data needed backing. * @page_flags: Page flags as identified by TTM_PAGE_FLAG_XX flags. * @dummy_read_page: See struct ttm_bo_device. * * Create a struct ttm_tt to back data with system memory pages. * No pages are actually allocated. * Returns: * NULL: Out of memory. */ extern int ttm_tt_init(struct ttm_tt *ttm, struct ttm_bo_device *bdev, unsigned long size, uint32_t page_flags, struct vm_page *dummy_read_page); extern int ttm_dma_tt_init(struct ttm_dma_tt *ttm_dma, struct ttm_bo_device *bdev, unsigned long size, uint32_t page_flags, struct vm_page *dummy_read_page); /** * ttm_tt_fini * * @ttm: the ttm_tt structure. * * Free memory of ttm_tt structure */ extern void ttm_tt_fini(struct ttm_tt *ttm); extern void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma); /** * ttm_ttm_bind: * * @ttm: The struct ttm_tt containing backing pages. * @bo_mem: The struct ttm_mem_reg identifying the binding location. * * Bind the pages of @ttm to an aperture location identified by @bo_mem */ extern int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem); /** * ttm_ttm_destroy: * * @ttm: The struct ttm_tt. * * Unbind, unpopulate and destroy common struct ttm_tt. */ extern void ttm_tt_destroy(struct ttm_tt *ttm); /** * ttm_ttm_unbind: * * @ttm: The struct ttm_tt. * * Unbind a struct ttm_tt. */ extern void ttm_tt_unbind(struct ttm_tt *ttm); /** * ttm_tt_swapin: * * @ttm: The struct ttm_tt. * * Swap in a previously swap out ttm_tt. */ extern int ttm_tt_swapin(struct ttm_tt *ttm); /** * ttm_tt_cache_flush: * * @pages: An array of pointers to struct page:s to flush. * @num_pages: Number of pages to flush. * * Flush the data of the indicated pages from the cpu caches. * This is used when changing caching attributes of the pages from * cache-coherent. */ extern void ttm_tt_cache_flush(struct vm_page *pages[], unsigned long num_pages); /** * ttm_tt_set_placement_caching: * * @ttm A struct ttm_tt the backing pages of which will change caching policy. * @placement: Flag indicating the desired caching policy. * * This function will change caching policy of any default kernel mappings of * the pages backing @ttm. If changing from cached to uncached or * write-combined, * all CPU caches will first be flushed to make sure the data of the pages * hit RAM. This function may be very costly as it involves global TLB * and cache flushes and potential page splitting / combining. */ extern int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement); extern int ttm_tt_swapout(struct ttm_tt *ttm, struct vm_object *persistent_swap_storage); /* * ttm_bo.c */ /** * ttm_mem_reg_is_pci * * @bdev: Pointer to a struct ttm_bo_device. * @mem: A valid struct ttm_mem_reg. * * Returns true if the memory described by @mem is PCI memory, * false otherwise. */ extern bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem); /** * ttm_bo_mem_space * * @bo: Pointer to a struct ttm_buffer_object. the data of which * we want to allocate space for. * @proposed_placement: Proposed new placement for the buffer object. * @mem: A struct ttm_mem_reg. * @interruptible: Sleep interruptible when sliping. * @no_wait_gpu: Return immediately if the GPU is busy. * * Allocate memory space for the buffer object pointed to by @bo, using * the placement flags in @mem, potentially evicting other idle buffer objects. * This function may sleep while waiting for space to become available. * Returns: * -EBUSY: No space available (only if no_wait == 1). * -ENOMEM: Could not allocate memory for the buffer object, either due to * fragmentation or concurrent allocators. * -ERESTARTSYS: An interruptible sleep was interrupted by a signal. */ extern int ttm_bo_mem_space(struct ttm_buffer_object *bo, struct ttm_placement *placement, struct ttm_mem_reg *mem, bool interruptible, bool no_wait_gpu); extern void ttm_bo_mem_put(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem); extern void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem); extern void ttm_bo_global_release(struct drm_global_reference *ref); extern int ttm_bo_global_init(struct drm_global_reference *ref); extern int ttm_bo_device_release(struct ttm_bo_device *bdev); /** * ttm_bo_device_init * * @bdev: A pointer to a struct ttm_bo_device to initialize. * @glob: A pointer to an initialized struct ttm_bo_global. * @driver: A pointer to a struct ttm_bo_driver set up by the caller. * @file_page_offset: Offset into the device address space that is available * for buffer data. This ensures compatibility with other users of the * address space. * * Initializes a struct ttm_bo_device: * Returns: * !0: Failure. */ extern int ttm_bo_device_init(struct ttm_bo_device *bdev, struct ttm_bo_global *glob, struct ttm_bo_driver *driver, uint64_t file_page_offset, bool need_dma32); /** * ttm_bo_unmap_virtual * * @bo: tear down the virtual mappings for this BO */ extern void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo); /** * ttm_bo_unmap_virtual * * @bo: tear down the virtual mappings for this BO * * The caller must take ttm_mem_io_lock before calling this function. */ extern void ttm_bo_unmap_virtual_locked(struct ttm_buffer_object *bo); extern int ttm_mem_io_reserve_vm(struct ttm_buffer_object *bo); extern void ttm_mem_io_free_vm(struct ttm_buffer_object *bo); extern int ttm_mem_io_lock(struct ttm_mem_type_manager *man, bool interruptible); extern void ttm_mem_io_unlock(struct ttm_mem_type_manager *man); /** * ttm_bo_reserve: * * @bo: A pointer to a struct ttm_buffer_object. * @interruptible: Sleep interruptible if waiting. * @no_wait: Don't sleep while trying to reserve, rather return -EBUSY. * @use_sequence: If @bo is already reserved, Only sleep waiting for * it to become unreserved if @sequence < (@bo)->sequence. * * Locks a buffer object for validation. (Or prevents other processes from * locking it for validation) and removes it from lru lists, while taking * a number of measures to prevent deadlocks. * * Deadlocks may occur when two processes try to reserve multiple buffers in * different order, either by will or as a result of a buffer being evicted * to make room for a buffer already reserved. (Buffers are reserved before * they are evicted). The following algorithm prevents such deadlocks from * occurring: * Processes attempting to reserve multiple buffers other than for eviction, * (typically execbuf), should first obtain a unique 32-bit * validation sequence number, * and call this function with @use_sequence == 1 and @sequence == the unique * sequence number. If upon call of this function, the buffer object is already * reserved, the validation sequence is checked against the validation * sequence of the process currently reserving the buffer, * and if the current validation sequence is greater than that of the process * holding the reservation, the function returns -EAGAIN. Otherwise it sleeps * waiting for the buffer to become unreserved, after which it retries * reserving. * The caller should, when receiving an -EAGAIN error * release all its buffer reservations, wait for @bo to become unreserved, and * then rerun the validation with the same validation sequence. This procedure * will always guarantee that the process with the lowest validation sequence * will eventually succeed, preventing both deadlocks and starvation. * * Returns: * -EAGAIN: The reservation may cause a deadlock. * Release all buffer reservations, wait for @bo to become unreserved and * try again. (only if use_sequence == 1). * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by * a signal. Release all buffer reservations and return to user-space. * -EBUSY: The function needed to sleep, but @no_wait was true * -EDEADLK: Bo already reserved using @sequence. This error code will only * be returned if @use_sequence is set to true. */ extern int ttm_bo_reserve(struct ttm_buffer_object *bo, bool interruptible, bool no_wait, bool use_sequence, uint32_t sequence); /** * ttm_bo_reserve_slowpath_nolru: * @bo: A pointer to a struct ttm_buffer_object. * @interruptible: Sleep interruptible if waiting. * @sequence: Set (@bo)->sequence to this value after lock * * This is called after ttm_bo_reserve returns -EAGAIN and we backed off * from all our other reservations. Because there are no other reservations * held by us, this function cannot deadlock any more. * * Will not remove reserved buffers from the lru lists. * Otherwise identical to ttm_bo_reserve_slowpath. */ extern int ttm_bo_reserve_slowpath_nolru(struct ttm_buffer_object *bo, bool interruptible, uint32_t sequence); /** * ttm_bo_reserve_slowpath: * @bo: A pointer to a struct ttm_buffer_object. * @interruptible: Sleep interruptible if waiting. * @sequence: Set (@bo)->sequence to this value after lock * * This is called after ttm_bo_reserve returns -EAGAIN and we backed off * from all our other reservations. Because there are no other reservations * held by us, this function cannot deadlock any more. */ extern int ttm_bo_reserve_slowpath(struct ttm_buffer_object *bo, bool interruptible, uint32_t sequence); /** * ttm_bo_reserve_nolru: * * @bo: A pointer to a struct ttm_buffer_object. * @interruptible: Sleep interruptible if waiting. * @no_wait: Don't sleep while trying to reserve, rather return -EBUSY. * @use_sequence: If @bo is already reserved, Only sleep waiting for * it to become unreserved if @sequence < (@bo)->sequence. * * Will not remove reserved buffers from the lru lists. * Otherwise identical to ttm_bo_reserve. * * Returns: * -EAGAIN: The reservation may cause a deadlock. * Release all buffer reservations, wait for @bo to become unreserved and * try again. (only if use_sequence == 1). * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by * a signal. Release all buffer reservations and return to user-space. * -EBUSY: The function needed to sleep, but @no_wait was true * -EDEADLK: Bo already reserved using @sequence. This error code will only * be returned if @use_sequence is set to true. */ extern int ttm_bo_reserve_nolru(struct ttm_buffer_object *bo, bool interruptible, bool no_wait, bool use_sequence, uint32_t sequence); /** * ttm_bo_unreserve * * @bo: A pointer to a struct ttm_buffer_object. * * Unreserve a previous reservation of @bo. */ extern void ttm_bo_unreserve(struct ttm_buffer_object *bo); /** * ttm_bo_unreserve_locked * * @bo: A pointer to a struct ttm_buffer_object. * * Unreserve a previous reservation of @bo. * Needs to be called with struct ttm_bo_global::lru_lock held. */ extern void ttm_bo_unreserve_locked(struct ttm_buffer_object *bo); /* * ttm_bo_util.c */ /** * ttm_bo_move_ttm * * @bo: A pointer to a struct ttm_buffer_object. * @evict: 1: This is an eviction. Don't try to pipeline. * @no_wait_gpu: Return immediately if the GPU is busy. * @new_mem: struct ttm_mem_reg indicating where to move. * * Optimized move function for a buffer object with both old and * new placement backed by a TTM. The function will, if successful, * free any old aperture space, and set (@new_mem)->mm_node to NULL, * and update the (@bo)->mem placement flags. If unsuccessful, the old * data remains untouched, and it's up to the caller to free the * memory space indicated by @new_mem. * Returns: * !0: Failure. */ extern int ttm_bo_move_ttm(struct ttm_buffer_object *bo, bool evict, bool no_wait_gpu, struct ttm_mem_reg *new_mem); /** * ttm_bo_move_memcpy * * @bo: A pointer to a struct ttm_buffer_object. * @evict: 1: This is an eviction. Don't try to pipeline. * @no_wait_gpu: Return immediately if the GPU is busy. * @new_mem: struct ttm_mem_reg indicating where to move. * * Fallback move function for a mappable buffer object in mappable memory. * The function will, if successful, * free any old aperture space, and set (@new_mem)->mm_node to NULL, * and update the (@bo)->mem placement flags. If unsuccessful, the old * data remains untouched, and it's up to the caller to free the * memory space indicated by @new_mem. * Returns: * !0: Failure. */ extern int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, bool evict, bool no_wait_gpu, struct ttm_mem_reg *new_mem); /** * ttm_bo_free_old_node * * @bo: A pointer to a struct ttm_buffer_object. * * Utility function to free an old placement after a successful move. */ extern void ttm_bo_free_old_node(struct ttm_buffer_object *bo); /** * ttm_bo_move_accel_cleanup. * * @bo: A pointer to a struct ttm_buffer_object. * @sync_obj: A sync object that signals when moving is complete. * @evict: This is an evict move. Don't return until the buffer is idle. * @no_wait_gpu: Return immediately if the GPU is busy. * @new_mem: struct ttm_mem_reg indicating where to move. * * Accelerated move function to be called when an accelerated move * has been scheduled. The function will create a new temporary buffer object * representing the old placement, and put the sync object on both buffer * objects. After that the newly created buffer object is unref'd to be * destroyed when the move is complete. This will help pipeline * buffer moves. */ extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, void *sync_obj, bool evict, bool no_wait_gpu, struct ttm_mem_reg *new_mem); /** * ttm_io_prot * * @c_state: Caching state. * @tmp: Page protection flag for a normal, cached mapping. * * Utility function that returns the pgprot_t that should be used for * setting up a PTE with the caching model indicated by @c_state. */ extern vm_memattr_t ttm_io_prot(uint32_t caching_flags); extern const struct ttm_mem_type_manager_func ttm_bo_manager_func; -#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))) +#if __OS_HAS_AGP #define TTM_HAS_AGP -#include /** * ttm_agp_tt_create * * @bdev: Pointer to a struct ttm_bo_device. * @bridge: The agp bridge this device is sitting on. * @size: Size of the data needed backing. * @page_flags: Page flags as identified by TTM_PAGE_FLAG_XX flags. * @dummy_read_page: See struct ttm_bo_device. * * * Create a TTM backend that uses the indicated AGP bridge as an aperture * for TT memory. This function uses the linux agpgart interface to * bind and unbind memory backing a ttm_tt. */ extern struct ttm_tt *ttm_agp_tt_create(struct ttm_bo_device *bdev, - struct agp_bridge_data *bridge, + device_t bridge, unsigned long size, uint32_t page_flags, struct vm_page *dummy_read_page); int ttm_agp_tt_populate(struct ttm_tt *ttm); void ttm_agp_tt_unpopulate(struct ttm_tt *ttm); #endif int ttm_bo_cmp_rb_tree_items(struct ttm_buffer_object *a, struct ttm_buffer_object *b); RB_PROTOTYPE(ttm_bo_device_buffer_objects, ttm_buffer_object, vm_rb, ttm_bo_cmp_rb_tree_items); #endif Index: head/sys/dev/drm2/ttm/ttm_page_alloc.c =================================================================== --- head/sys/dev/drm2/ttm/ttm_page_alloc.c (revision 273861) +++ head/sys/dev/drm2/ttm/ttm_page_alloc.c (revision 273862) @@ -1,901 +1,885 @@ /* * Copyright (c) Red Hat Inc. * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sub license, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Jerome Glisse * Pauli Nieminen */ /* * Copyright (c) 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Konstantin Belousov * under sponsorship from the FreeBSD Foundation. */ /* simple list based uncached page pool * - Pool collects resently freed pages for reuse * - Use page->lru to keep a free list * - doesn't track currently in use pages */ #include __FBSDID("$FreeBSD$"); #include #include #include -#ifdef TTM_HAS_AGP -#include -#endif - #define NUM_PAGES_TO_ALLOC (PAGE_SIZE/sizeof(vm_page_t)) #define SMALL_ALLOCATION 16 #define FREE_ALL_PAGES (~0U) /* times are in msecs */ #define PAGE_FREE_INTERVAL 1000 /** * struct ttm_page_pool - Pool to reuse recently allocated uc/wc pages. * * @lock: Protects the shared pool from concurrnet access. Must be used with * irqsave/irqrestore variants because pool allocator maybe called from * delayed work. * @fill_lock: Prevent concurrent calls to fill. * @list: Pool of free uc/wc pages for fast reuse. * @gfp_flags: Flags to pass for alloc_page. * @npages: Number of pages in pool. */ struct ttm_page_pool { struct mtx lock; bool fill_lock; bool dma32; struct pglist list; int ttm_page_alloc_flags; unsigned npages; char *name; unsigned long nfrees; unsigned long nrefills; }; /** * Limits for the pool. They are handled without locks because only place where * they may change is in sysfs store. They won't have immediate effect anyway * so forcing serialization to access them is pointless. */ struct ttm_pool_opts { unsigned alloc_size; unsigned max_size; unsigned small; }; #define NUM_POOLS 4 /** * struct ttm_pool_manager - Holds memory pools for fst allocation * * Manager is read only object for pool code so it doesn't need locking. * * @free_interval: minimum number of jiffies between freeing pages from pool. * @page_alloc_inited: reference counting for pool allocation. * @work: Work that is used to shrink the pool. Work is only run when there is * some pages to free. * @small_allocation: Limit in number of pages what is small allocation. * * @pools: All pool objects in use. **/ struct ttm_pool_manager { unsigned int kobj_ref; eventhandler_tag lowmem_handler; struct ttm_pool_opts options; union { struct ttm_page_pool u_pools[NUM_POOLS]; struct _utag { struct ttm_page_pool u_wc_pool; struct ttm_page_pool u_uc_pool; struct ttm_page_pool u_wc_pool_dma32; struct ttm_page_pool u_uc_pool_dma32; } _ut; } _u; }; #define pools _u.u_pools #define wc_pool _u._ut.u_wc_pool #define uc_pool _u._ut.u_uc_pool #define wc_pool_dma32 _u._ut.u_wc_pool_dma32 #define uc_pool_dma32 _u._ut.u_uc_pool_dma32 MALLOC_DEFINE(M_TTM_POOLMGR, "ttm_poolmgr", "TTM Pool Manager"); static void ttm_vm_page_free(vm_page_t m) { KASSERT(m->object == NULL, ("ttm page %p is owned", m)); KASSERT(m->wire_count == 1, ("ttm lost wire %p", m)); KASSERT((m->flags & PG_FICTITIOUS) != 0, ("ttm lost fictitious %p", m)); KASSERT((m->oflags & VPO_UNMANAGED) == 0, ("ttm got unmanaged %p", m)); m->flags &= ~PG_FICTITIOUS; m->oflags |= VPO_UNMANAGED; vm_page_unwire(m, PQ_INACTIVE); vm_page_free(m); } static vm_memattr_t ttm_caching_state_to_vm(enum ttm_caching_state cstate) { switch (cstate) { case tt_uncached: return (VM_MEMATTR_UNCACHEABLE); case tt_wc: return (VM_MEMATTR_WRITE_COMBINING); case tt_cached: return (VM_MEMATTR_WRITE_BACK); } panic("caching state %d\n", cstate); } static void ttm_pool_kobj_release(struct ttm_pool_manager *m) { free(m, M_TTM_POOLMGR); } #if 0 /* XXXKIB sysctl */ static ssize_t ttm_pool_store(struct ttm_pool_manager *m, struct attribute *attr, const char *buffer, size_t size) { int chars; unsigned val; chars = sscanf(buffer, "%u", &val); if (chars == 0) return size; /* Convert kb to number of pages */ val = val / (PAGE_SIZE >> 10); if (attr == &ttm_page_pool_max) m->options.max_size = val; else if (attr == &ttm_page_pool_small) m->options.small = val; else if (attr == &ttm_page_pool_alloc_size) { if (val > NUM_PAGES_TO_ALLOC*8) { pr_err("Setting allocation size to %lu is not allowed. Recommended size is %lu\n", NUM_PAGES_TO_ALLOC*(PAGE_SIZE >> 7), NUM_PAGES_TO_ALLOC*(PAGE_SIZE >> 10)); return size; } else if (val > NUM_PAGES_TO_ALLOC) { pr_warn("Setting allocation size to larger than %lu is not recommended\n", NUM_PAGES_TO_ALLOC*(PAGE_SIZE >> 10)); } m->options.alloc_size = val; } return size; } static ssize_t ttm_pool_show(struct ttm_pool_manager *m, struct attribute *attr, char *buffer) { unsigned val = 0; if (attr == &ttm_page_pool_max) val = m->options.max_size; else if (attr == &ttm_page_pool_small) val = m->options.small; else if (attr == &ttm_page_pool_alloc_size) val = m->options.alloc_size; val = val * (PAGE_SIZE >> 10); return snprintf(buffer, PAGE_SIZE, "%u\n", val); } #endif static struct ttm_pool_manager *_manager; static int set_pages_array_wb(vm_page_t *pages, int addrinarray) { - vm_page_t m; +#ifdef TTM_HAS_AGP int i; - for (i = 0; i < addrinarray; i++) { - m = pages[i]; -#ifdef TTM_HAS_AGP - unmap_page_from_agp(m); + for (i = 0; i < addrinarray; i++) + pmap_page_set_memattr(pages[i], VM_MEMATTR_WRITE_BACK); #endif - pmap_page_set_memattr(m, VM_MEMATTR_WRITE_BACK); - } return 0; } static int set_pages_array_wc(vm_page_t *pages, int addrinarray) { - vm_page_t m; +#ifdef TTM_HAS_AGP int i; - for (i = 0; i < addrinarray; i++) { - m = pages[i]; -#ifdef TTM_HAS_AGP - map_page_into_agp(pages[i]); + for (i = 0; i < addrinarray; i++) + pmap_page_set_memattr(pages[i], VM_MEMATTR_WRITE_COMBINING); #endif - pmap_page_set_memattr(m, VM_MEMATTR_WRITE_COMBINING); - } return 0; } static int set_pages_array_uc(vm_page_t *pages, int addrinarray) { - vm_page_t m; +#ifdef TTM_HAS_AGP int i; - for (i = 0; i < addrinarray; i++) { - m = pages[i]; -#ifdef TTM_HAS_AGP - map_page_into_agp(pages[i]); + for (i = 0; i < addrinarray; i++) + pmap_page_set_memattr(pages[i], VM_MEMATTR_UNCACHEABLE); #endif - pmap_page_set_memattr(m, VM_MEMATTR_UNCACHEABLE); - } return 0; } /** * Select the right pool or requested caching state and ttm flags. */ static struct ttm_page_pool *ttm_get_pool(int flags, enum ttm_caching_state cstate) { int pool_index; if (cstate == tt_cached) return NULL; if (cstate == tt_wc) pool_index = 0x0; else pool_index = 0x1; if (flags & TTM_PAGE_FLAG_DMA32) pool_index |= 0x2; return &_manager->pools[pool_index]; } /* set memory back to wb and free the pages. */ static void ttm_pages_put(vm_page_t *pages, unsigned npages) { unsigned i; /* Our VM handles vm memattr automatically on the page free. */ if (set_pages_array_wb(pages, npages)) printf("[TTM] Failed to set %d pages to wb!\n", npages); for (i = 0; i < npages; ++i) ttm_vm_page_free(pages[i]); } static void ttm_pool_update_free_locked(struct ttm_page_pool *pool, unsigned freed_pages) { pool->npages -= freed_pages; pool->nfrees += freed_pages; } /** * Free pages from pool. * * To prevent hogging the ttm_swap process we only free NUM_PAGES_TO_ALLOC * number of pages in one go. * * @pool: to free the pages from * @free_all: If set to true will free all pages in pool **/ static int ttm_page_pool_free(struct ttm_page_pool *pool, unsigned nr_free) { vm_page_t p, p1; vm_page_t *pages_to_free; unsigned freed_pages = 0, npages_to_free = nr_free; unsigned i; if (NUM_PAGES_TO_ALLOC < nr_free) npages_to_free = NUM_PAGES_TO_ALLOC; pages_to_free = malloc(npages_to_free * sizeof(vm_page_t), M_TEMP, M_WAITOK | M_ZERO); restart: mtx_lock(&pool->lock); TAILQ_FOREACH_REVERSE_SAFE(p, &pool->list, pglist, plinks.q, p1) { if (freed_pages >= npages_to_free) break; pages_to_free[freed_pages++] = p; /* We can only remove NUM_PAGES_TO_ALLOC at a time. */ if (freed_pages >= NUM_PAGES_TO_ALLOC) { /* remove range of pages from the pool */ for (i = 0; i < freed_pages; i++) TAILQ_REMOVE(&pool->list, pages_to_free[i], plinks.q); ttm_pool_update_free_locked(pool, freed_pages); /** * Because changing page caching is costly * we unlock the pool to prevent stalling. */ mtx_unlock(&pool->lock); ttm_pages_put(pages_to_free, freed_pages); if (likely(nr_free != FREE_ALL_PAGES)) nr_free -= freed_pages; if (NUM_PAGES_TO_ALLOC >= nr_free) npages_to_free = nr_free; else npages_to_free = NUM_PAGES_TO_ALLOC; freed_pages = 0; /* free all so restart the processing */ if (nr_free) goto restart; /* Not allowed to fall through or break because * following context is inside spinlock while we are * outside here. */ goto out; } } /* remove range of pages from the pool */ if (freed_pages) { for (i = 0; i < freed_pages; i++) TAILQ_REMOVE(&pool->list, pages_to_free[i], plinks.q); ttm_pool_update_free_locked(pool, freed_pages); nr_free -= freed_pages; } mtx_unlock(&pool->lock); if (freed_pages) ttm_pages_put(pages_to_free, freed_pages); out: free(pages_to_free, M_TEMP); return nr_free; } /* Get good estimation how many pages are free in pools */ static int ttm_pool_get_num_unused_pages(void) { unsigned i; int total = 0; for (i = 0; i < NUM_POOLS; ++i) total += _manager->pools[i].npages; return total; } /** * Callback for mm to request pool to reduce number of page held. */ static int ttm_pool_mm_shrink(void *arg) { static unsigned int start_pool = 0; unsigned i; unsigned pool_offset = atomic_fetchadd_int(&start_pool, 1); struct ttm_page_pool *pool; int shrink_pages = 100; /* XXXKIB */ pool_offset = pool_offset % NUM_POOLS; /* select start pool in round robin fashion */ for (i = 0; i < NUM_POOLS; ++i) { unsigned nr_free = shrink_pages; if (shrink_pages == 0) break; pool = &_manager->pools[(i + pool_offset)%NUM_POOLS]; shrink_pages = ttm_page_pool_free(pool, nr_free); } /* return estimated number of unused pages in pool */ return ttm_pool_get_num_unused_pages(); } static void ttm_pool_mm_shrink_init(struct ttm_pool_manager *manager) { manager->lowmem_handler = EVENTHANDLER_REGISTER(vm_lowmem, ttm_pool_mm_shrink, manager, EVENTHANDLER_PRI_ANY); } static void ttm_pool_mm_shrink_fini(struct ttm_pool_manager *manager) { EVENTHANDLER_DEREGISTER(vm_lowmem, manager->lowmem_handler); } static int ttm_set_pages_caching(vm_page_t *pages, enum ttm_caching_state cstate, unsigned cpages) { int r = 0; /* Set page caching */ switch (cstate) { case tt_uncached: r = set_pages_array_uc(pages, cpages); if (r) printf("[TTM] Failed to set %d pages to uc!\n", cpages); break; case tt_wc: r = set_pages_array_wc(pages, cpages); if (r) printf("[TTM] Failed to set %d pages to wc!\n", cpages); break; default: break; } return r; } /** * Free pages the pages that failed to change the caching state. If there is * any pages that have changed their caching state already put them to the * pool. */ static void ttm_handle_caching_state_failure(struct pglist *pages, int ttm_flags, enum ttm_caching_state cstate, vm_page_t *failed_pages, unsigned cpages) { unsigned i; /* Failed pages have to be freed */ for (i = 0; i < cpages; ++i) { TAILQ_REMOVE(pages, failed_pages[i], plinks.q); ttm_vm_page_free(failed_pages[i]); } } /** * Allocate new pages with correct caching. * * This function is reentrant if caller updates count depending on number of * pages returned in pages array. */ static int ttm_alloc_new_pages(struct pglist *pages, int ttm_alloc_flags, int ttm_flags, enum ttm_caching_state cstate, unsigned count) { vm_page_t *caching_array; vm_page_t p; int r = 0; unsigned i, cpages, aflags; unsigned max_cpages = min(count, (unsigned)(PAGE_SIZE/sizeof(vm_page_t))); aflags = VM_ALLOC_NORMAL | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ | ((ttm_alloc_flags & TTM_PAGE_FLAG_ZERO_ALLOC) != 0 ? VM_ALLOC_ZERO : 0); /* allocate array for page caching change */ caching_array = malloc(max_cpages * sizeof(vm_page_t), M_TEMP, M_WAITOK | M_ZERO); for (i = 0, cpages = 0; i < count; ++i) { p = vm_page_alloc_contig(NULL, 0, aflags, 1, 0, (ttm_alloc_flags & TTM_PAGE_FLAG_DMA32) ? 0xffffffff : VM_MAX_ADDRESS, PAGE_SIZE, 0, ttm_caching_state_to_vm(cstate)); if (!p) { printf("[TTM] Unable to get page %u\n", i); /* store already allocated pages in the pool after * setting the caching state */ if (cpages) { r = ttm_set_pages_caching(caching_array, cstate, cpages); if (r) ttm_handle_caching_state_failure(pages, ttm_flags, cstate, caching_array, cpages); } r = -ENOMEM; goto out; } p->oflags &= ~VPO_UNMANAGED; p->flags |= PG_FICTITIOUS; #ifdef CONFIG_HIGHMEM /* KIB: nop */ /* gfp flags of highmem page should never be dma32 so we * we should be fine in such case */ if (!PageHighMem(p)) #endif { caching_array[cpages++] = p; if (cpages == max_cpages) { r = ttm_set_pages_caching(caching_array, cstate, cpages); if (r) { ttm_handle_caching_state_failure(pages, ttm_flags, cstate, caching_array, cpages); goto out; } cpages = 0; } } TAILQ_INSERT_HEAD(pages, p, plinks.q); } if (cpages) { r = ttm_set_pages_caching(caching_array, cstate, cpages); if (r) ttm_handle_caching_state_failure(pages, ttm_flags, cstate, caching_array, cpages); } out: free(caching_array, M_TEMP); return r; } /** * Fill the given pool if there aren't enough pages and the requested number of * pages is small. */ static void ttm_page_pool_fill_locked(struct ttm_page_pool *pool, int ttm_flags, enum ttm_caching_state cstate, unsigned count) { vm_page_t p; int r; unsigned cpages = 0; /** * Only allow one pool fill operation at a time. * If pool doesn't have enough pages for the allocation new pages are * allocated from outside of pool. */ if (pool->fill_lock) return; pool->fill_lock = true; /* If allocation request is small and there are not enough * pages in a pool we fill the pool up first. */ if (count < _manager->options.small && count > pool->npages) { struct pglist new_pages; unsigned alloc_size = _manager->options.alloc_size; /** * Can't change page caching if in irqsave context. We have to * drop the pool->lock. */ mtx_unlock(&pool->lock); TAILQ_INIT(&new_pages); r = ttm_alloc_new_pages(&new_pages, pool->ttm_page_alloc_flags, ttm_flags, cstate, alloc_size); mtx_lock(&pool->lock); if (!r) { TAILQ_CONCAT(&pool->list, &new_pages, plinks.q); ++pool->nrefills; pool->npages += alloc_size; } else { printf("[TTM] Failed to fill pool (%p)\n", pool); /* If we have any pages left put them to the pool. */ TAILQ_FOREACH(p, &pool->list, plinks.q) { ++cpages; } TAILQ_CONCAT(&pool->list, &new_pages, plinks.q); pool->npages += cpages; } } pool->fill_lock = false; } /** * Cut 'count' number of pages from the pool and put them on the return list. * * @return count of pages still required to fulfill the request. */ static unsigned ttm_page_pool_get_pages(struct ttm_page_pool *pool, struct pglist *pages, int ttm_flags, enum ttm_caching_state cstate, unsigned count) { vm_page_t p; unsigned i; mtx_lock(&pool->lock); ttm_page_pool_fill_locked(pool, ttm_flags, cstate, count); if (count >= pool->npages) { /* take all pages from the pool */ TAILQ_CONCAT(pages, &pool->list, plinks.q); count -= pool->npages; pool->npages = 0; goto out; } for (i = 0; i < count; i++) { p = TAILQ_FIRST(&pool->list); TAILQ_REMOVE(&pool->list, p, plinks.q); TAILQ_INSERT_TAIL(pages, p, plinks.q); } pool->npages -= count; count = 0; out: mtx_unlock(&pool->lock); return count; } /* Put all pages in pages list to correct pool to wait for reuse */ static void ttm_put_pages(vm_page_t *pages, unsigned npages, int flags, enum ttm_caching_state cstate) { struct ttm_page_pool *pool = ttm_get_pool(flags, cstate); unsigned i; if (pool == NULL) { /* No pool for this memory type so free the pages */ for (i = 0; i < npages; i++) { if (pages[i]) { ttm_vm_page_free(pages[i]); pages[i] = NULL; } } return; } mtx_lock(&pool->lock); for (i = 0; i < npages; i++) { if (pages[i]) { TAILQ_INSERT_TAIL(&pool->list, pages[i], plinks.q); pages[i] = NULL; pool->npages++; } } /* Check that we don't go over the pool limit */ npages = 0; if (pool->npages > _manager->options.max_size) { npages = pool->npages - _manager->options.max_size; /* free at least NUM_PAGES_TO_ALLOC number of pages * to reduce calls to set_memory_wb */ if (npages < NUM_PAGES_TO_ALLOC) npages = NUM_PAGES_TO_ALLOC; } mtx_unlock(&pool->lock); if (npages) ttm_page_pool_free(pool, npages); } /* * On success pages list will hold count number of correctly * cached pages. */ static int ttm_get_pages(vm_page_t *pages, unsigned npages, int flags, enum ttm_caching_state cstate) { struct ttm_page_pool *pool = ttm_get_pool(flags, cstate); struct pglist plist; vm_page_t p = NULL; int gfp_flags, aflags; unsigned count; int r; aflags = VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | ((flags & TTM_PAGE_FLAG_ZERO_ALLOC) != 0 ? VM_ALLOC_ZERO : 0); /* No pool for cached pages */ if (pool == NULL) { for (r = 0; r < npages; ++r) { p = vm_page_alloc_contig(NULL, 0, aflags, 1, 0, (flags & TTM_PAGE_FLAG_DMA32) ? 0xffffffff : VM_MAX_ADDRESS, PAGE_SIZE, 0, ttm_caching_state_to_vm(cstate)); if (!p) { printf("[TTM] Unable to allocate page\n"); return -ENOMEM; } p->oflags &= ~VPO_UNMANAGED; p->flags |= PG_FICTITIOUS; pages[r] = p; } return 0; } /* combine zero flag to pool flags */ gfp_flags = flags | pool->ttm_page_alloc_flags; /* First we take pages from the pool */ TAILQ_INIT(&plist); npages = ttm_page_pool_get_pages(pool, &plist, flags, cstate, npages); count = 0; TAILQ_FOREACH(p, &plist, plinks.q) { pages[count++] = p; } /* clear the pages coming from the pool if requested */ if (flags & TTM_PAGE_FLAG_ZERO_ALLOC) { TAILQ_FOREACH(p, &plist, plinks.q) { pmap_zero_page(p); } } /* If pool didn't have enough pages allocate new one. */ if (npages > 0) { /* ttm_alloc_new_pages doesn't reference pool so we can run * multiple requests in parallel. **/ TAILQ_INIT(&plist); r = ttm_alloc_new_pages(&plist, gfp_flags, flags, cstate, npages); TAILQ_FOREACH(p, &plist, plinks.q) { pages[count++] = p; } if (r) { /* If there is any pages in the list put them back to * the pool. */ printf("[TTM] Failed to allocate extra pages for large request\n"); ttm_put_pages(pages, count, flags, cstate); return r; } } return 0; } static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, int flags, char *name) { mtx_init(&pool->lock, "ttmpool", NULL, MTX_DEF); pool->fill_lock = false; TAILQ_INIT(&pool->list); pool->npages = pool->nfrees = 0; pool->ttm_page_alloc_flags = flags; pool->name = name; } int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) { if (_manager != NULL) printf("[TTM] manager != NULL\n"); printf("[TTM] Initializing pool allocator\n"); _manager = malloc(sizeof(*_manager), M_TTM_POOLMGR, M_WAITOK | M_ZERO); ttm_page_pool_init_locked(&_manager->wc_pool, 0, "wc"); ttm_page_pool_init_locked(&_manager->uc_pool, 0, "uc"); ttm_page_pool_init_locked(&_manager->wc_pool_dma32, TTM_PAGE_FLAG_DMA32, "wc dma"); ttm_page_pool_init_locked(&_manager->uc_pool_dma32, TTM_PAGE_FLAG_DMA32, "uc dma"); _manager->options.max_size = max_pages; _manager->options.small = SMALL_ALLOCATION; _manager->options.alloc_size = NUM_PAGES_TO_ALLOC; refcount_init(&_manager->kobj_ref, 1); ttm_pool_mm_shrink_init(_manager); return 0; } void ttm_page_alloc_fini(void) { int i; printf("[TTM] Finalizing pool allocator\n"); ttm_pool_mm_shrink_fini(_manager); for (i = 0; i < NUM_POOLS; ++i) ttm_page_pool_free(&_manager->pools[i], FREE_ALL_PAGES); if (refcount_release(&_manager->kobj_ref)) ttm_pool_kobj_release(_manager); _manager = NULL; } int ttm_pool_populate(struct ttm_tt *ttm) { struct ttm_mem_global *mem_glob = ttm->glob->mem_glob; unsigned i; int ret; if (ttm->state != tt_unpopulated) return 0; for (i = 0; i < ttm->num_pages; ++i) { ret = ttm_get_pages(&ttm->pages[i], 1, ttm->page_flags, ttm->caching_state); if (ret != 0) { ttm_pool_unpopulate(ttm); return -ENOMEM; } ret = ttm_mem_global_alloc_page(mem_glob, ttm->pages[i], false, false); if (unlikely(ret != 0)) { ttm_pool_unpopulate(ttm); return -ENOMEM; } } if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) { ret = ttm_tt_swapin(ttm); if (unlikely(ret != 0)) { ttm_pool_unpopulate(ttm); return ret; } } ttm->state = tt_unbound; return 0; } void ttm_pool_unpopulate(struct ttm_tt *ttm) { unsigned i; for (i = 0; i < ttm->num_pages; ++i) { if (ttm->pages[i]) { ttm_mem_global_free_page(ttm->glob->mem_glob, ttm->pages[i]); ttm_put_pages(&ttm->pages[i], 1, ttm->page_flags, ttm->caching_state); } } ttm->state = tt_unpopulated; } #if 0 /* XXXKIB sysctl */ int ttm_page_alloc_debugfs(struct seq_file *m, void *data) { struct ttm_page_pool *p; unsigned i; char *h[] = {"pool", "refills", "pages freed", "size"}; if (!_manager) { seq_printf(m, "No pool allocator running.\n"); return 0; } seq_printf(m, "%6s %12s %13s %8s\n", h[0], h[1], h[2], h[3]); for (i = 0; i < NUM_POOLS; ++i) { p = &_manager->pools[i]; seq_printf(m, "%6s %12ld %13ld %8d\n", p->name, p->nrefills, p->nfrees, p->npages); } return 0; } #endif