Index: stable/10/lib/libc/arm/aeabi/aeabi_vfp.h =================================================================== --- stable/10/lib/libc/arm/aeabi/aeabi_vfp.h (revision 273826) +++ stable/10/lib/libc/arm/aeabi/aeabi_vfp.h (revision 273827) @@ -1,129 +1,131 @@ /* * Copyright (C) 2013 Andrew Turner * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef AEABI_VFP_H #define AEABI_VFP_H +#include + /* * ASM helper macros. These allow the functions to be changed depending on * the endian-ness we are building for. */ /* Allow the name of the function to be changed depending on the ABI */ #ifndef __ARM_PCS_VFP #define AEABI_ENTRY(x) ENTRY(__aeabi_ ## x ## _vfp) #define AEABI_END(x) END(__aeabi_ ## x ## _vfp) #else #define AEABI_ENTRY(x) ENTRY(__aeabi_ ## x) #define AEABI_END(x) END(__aeabi_ ## x) #endif /* * These should be used when a function either takes, or returns a floating * point falue. They will load the data from an ARM to a VFP register(s), * or from a VFP to an ARM register */ -#ifdef __ARMEB__ +#ifdef __ARM_BIG_ENDIAN #define LOAD_DREG(vreg, reg0, reg1) vmov vreg, reg1, reg0 #define UNLOAD_DREG(reg0, reg1, vreg) vmov reg1, reg0, vreg #else #define LOAD_DREG(vreg, reg0, reg1) vmov vreg, reg0, reg1 #define UNLOAD_DREG(reg0, reg1, vreg) vmov reg0, reg1, vreg #endif #define LOAD_SREGS(vreg0, vreg1, reg0, reg1) vmov vreg0, vreg1, reg0, reg1 #define LOAD_SREG(vreg, reg) vmov vreg, reg #define UNLOAD_SREG(reg, vreg) vmov reg, vreg /* * C Helper macros */ -#if defined(__FreeBSD_ARCH_armv6__) || (defined(__ARM_ARCH) && __ARM_ARCH >= 6) +#if __ARM_ARCH >= 6 /* * Generate a function that will either call into the VFP implementation, * or the soft float version for a given __aeabi_* helper. The function * will take a single argument of the type given by in_type. */ #define AEABI_FUNC(name, in_type, soft_func) \ __aeabi_ ## name(in_type a) \ { \ if (_libc_arm_fpu_present) \ return __aeabi_ ## name ## _vfp(a); \ else \ return soft_func (a); \ } /* As above, but takes two arguments of the same type */ #define AEABI_FUNC2(name, in_type, soft_func) \ __aeabi_ ## name(in_type a, in_type b) \ { \ if (_libc_arm_fpu_present) \ return __aeabi_ ## name ## _vfp(a, b); \ else \ return soft_func (a, b); \ } /* As above, but with the soft float arguments reversed */ #define AEABI_FUNC2_REV(name, in_type, soft_func) \ __aeabi_ ## name(in_type a, in_type b) \ { \ if (_libc_arm_fpu_present) \ return __aeabi_ ## name ## _vfp(a, b); \ else \ return soft_func (b, a); \ } #else /* * Helper macros for when we are only able to use the softfloat * version of these functions, i.e. on arm before armv6. */ #define AEABI_FUNC(name, in_type, soft_func) \ __aeabi_ ## name(in_type a) \ { \ return soft_func (a); \ } /* As above, but takes two arguments of the same type */ #define AEABI_FUNC2(name, in_type, soft_func) \ __aeabi_ ## name(in_type a, in_type b) \ { \ return soft_func (a, b); \ } /* As above, but with the soft float arguments reversed */ #define AEABI_FUNC2_REV(name, in_type, soft_func) \ __aeabi_ ## name(in_type a, in_type b) \ { \ return soft_func (b, a); \ } #endif #endif Index: stable/10/lib/msun/arm/fenv.c =================================================================== --- stable/10/lib/msun/arm/fenv.c (revision 273826) +++ stable/10/lib/msun/arm/fenv.c (revision 273827) @@ -1,315 +1,317 @@ /*- * Copyright (c) 2004 David Schultz * Copyright (c) 2013 Andrew Turner * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #define __fenv_static #include "fenv.h" -#if defined(__FreeBSD_ARCH_armv6__) || (defined(__ARM_ARCH) && __ARM_ARCH >= 6) +#include + +#if __ARM_ARCH >= 6 #define FENV_ARMv6 #endif /* When SOFTFP_ABI is defined we are using the softfp ABI. */ #if defined(__VFP_FP__) && !defined(__ARM_PCS_VFP) #define SOFTFP_ABI #endif #ifndef FENV_MANGLE /* * Hopefully the system ID byte is immutable, so it's valid to use * this as a default environment. */ const fenv_t __fe_dfl_env = 0; #endif /* If this is a non-mangled softfp version special processing is required */ #if defined(FENV_MANGLE) || !defined(SOFTFP_ABI) || !defined(FENV_ARMv6) /* * The following macros map between the softfloat emulator's flags and * the hardware's FPSR. The hardware this file was written for doesn't * have rounding control bits, so we stick those in the system ID byte. */ #ifndef __ARM_PCS_VFP #define __set_env(env, flags, mask, rnd) env = ((flags) \ | (mask)<<_FPUSW_SHIFT \ | (rnd) << 24) #define __env_flags(env) ((env) & FE_ALL_EXCEPT) #define __env_mask(env) (((env) >> _FPUSW_SHIFT) \ & FE_ALL_EXCEPT) #define __env_round(env) (((env) >> 24) & _ROUND_MASK) #include "fenv-softfloat.h" #endif #ifdef __GNUC_GNU_INLINE__ #error "This file must be compiled with C99 'inline' semantics" #endif extern inline int feclearexcept(int __excepts); extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts); extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts); extern inline int feraiseexcept(int __excepts); extern inline int fetestexcept(int __excepts); extern inline int fegetround(void); extern inline int fesetround(int __round); extern inline int fegetenv(fenv_t *__envp); extern inline int feholdexcept(fenv_t *__envp); extern inline int fesetenv(const fenv_t *__envp); extern inline int feupdateenv(const fenv_t *__envp); extern inline int feenableexcept(int __mask); extern inline int fedisableexcept(int __mask); extern inline int fegetexcept(void); #else /* !FENV_MANGLE && SOFTFP_ABI */ /* Set by libc when the VFP unit is enabled */ extern int _libc_arm_fpu_present; int __softfp_feclearexcept(int __excepts); int __softfp_fegetexceptflag(fexcept_t *__flagp, int __excepts); int __softfp_fesetexceptflag(const fexcept_t *__flagp, int __excepts); int __softfp_feraiseexcept(int __excepts); int __softfp_fetestexcept(int __excepts); int __softfp_fegetround(void); int __softfp_fesetround(int __round); int __softfp_fegetenv(fenv_t *__envp); int __softfp_feholdexcept(fenv_t *__envp); int __softfp_fesetenv(const fenv_t *__envp); int __softfp_feupdateenv(const fenv_t *__envp); int __softfp_feenableexcept(int __mask); int __softfp_fedisableexcept(int __mask); int __softfp_fegetexcept(void); int __vfp_feclearexcept(int __excepts); int __vfp_fegetexceptflag(fexcept_t *__flagp, int __excepts); int __vfp_fesetexceptflag(const fexcept_t *__flagp, int __excepts); int __vfp_feraiseexcept(int __excepts); int __vfp_fetestexcept(int __excepts); int __vfp_fegetround(void); int __vfp_fesetround(int __round); int __vfp_fegetenv(fenv_t *__envp); int __vfp_feholdexcept(fenv_t *__envp); int __vfp_fesetenv(const fenv_t *__envp); int __vfp_feupdateenv(const fenv_t *__envp); int __vfp_feenableexcept(int __mask); int __vfp_fedisableexcept(int __mask); int __vfp_fegetexcept(void); static int __softfp_round_to_vfp(int round) { switch (round) { case FE_TONEAREST: default: return VFP_FE_TONEAREST; case FE_TOWARDZERO: return VFP_FE_TOWARDZERO; case FE_UPWARD: return VFP_FE_UPWARD; case FE_DOWNWARD: return VFP_FE_DOWNWARD; } } static int __softfp_round_from_vfp(int round) { switch (round) { case VFP_FE_TONEAREST: default: return FE_TONEAREST; case VFP_FE_TOWARDZERO: return FE_TOWARDZERO; case VFP_FE_UPWARD: return FE_UPWARD; case VFP_FE_DOWNWARD: return FE_DOWNWARD; } } int feclearexcept(int __excepts) { if (_libc_arm_fpu_present) __vfp_feclearexcept(__excepts); __softfp_feclearexcept(__excepts); return (0); } int fegetexceptflag(fexcept_t *__flagp, int __excepts) { fexcept_t __vfp_flagp; __vfp_flagp = 0; if (_libc_arm_fpu_present) __vfp_fegetexceptflag(&__vfp_flagp, __excepts); __softfp_fegetexceptflag(__flagp, __excepts); *__flagp |= __vfp_flagp; return (0); } int fesetexceptflag(const fexcept_t *__flagp, int __excepts) { if (_libc_arm_fpu_present) __vfp_fesetexceptflag(__flagp, __excepts); __softfp_fesetexceptflag(__flagp, __excepts); return (0); } int feraiseexcept(int __excepts) { if (_libc_arm_fpu_present) __vfp_feraiseexcept(__excepts); __softfp_feraiseexcept(__excepts); return (0); } int fetestexcept(int __excepts) { int __got_excepts; __got_excepts = 0; if (_libc_arm_fpu_present) __got_excepts = __vfp_fetestexcept(__excepts); __got_excepts |= __softfp_fetestexcept(__excepts); return (__got_excepts); } int fegetround(void) { if (_libc_arm_fpu_present) return __softfp_round_from_vfp(__vfp_fegetround()); return __softfp_fegetround(); } int fesetround(int __round) { if (_libc_arm_fpu_present) __vfp_fesetround(__softfp_round_to_vfp(__round)); __softfp_fesetround(__round); return (0); } int fegetenv(fenv_t *__envp) { fenv_t __vfp_envp; __vfp_envp = 0; if (_libc_arm_fpu_present) __vfp_fegetenv(&__vfp_envp); __softfp_fegetenv(__envp); *__envp |= __vfp_envp; return (0); } int feholdexcept(fenv_t *__envp) { fenv_t __vfp_envp; __vfp_envp = 0; if (_libc_arm_fpu_present) __vfp_feholdexcept(&__vfp_envp); __softfp_feholdexcept(__envp); *__envp |= __vfp_envp; return (0); } int fesetenv(const fenv_t *__envp) { if (_libc_arm_fpu_present) __vfp_fesetenv(__envp); __softfp_fesetenv(__envp); return (0); } int feupdateenv(const fenv_t *__envp) { if (_libc_arm_fpu_present) __vfp_feupdateenv(__envp); __softfp_feupdateenv(__envp); return (0); } int feenableexcept(int __mask) { int __unmasked; __unmasked = 0; if (_libc_arm_fpu_present) __unmasked = __vfp_feenableexcept(__mask); __unmasked |= __softfp_feenableexcept(__mask); return (__unmasked); } int fedisableexcept(int __mask) { int __unmasked; __unmasked = 0; if (_libc_arm_fpu_present) __unmasked = __vfp_fedisableexcept(__mask); __unmasked |= __softfp_fedisableexcept(__mask); return (__unmasked); } int fegetexcept(void) { int __unmasked; __unmasked = 0; if (_libc_arm_fpu_present) __unmasked = __vfp_fegetexcept(); __unmasked |= __softfp_fegetexcept(); return (__unmasked); } #endif Index: stable/10/sys/arm/arm/disassem.c =================================================================== --- stable/10/sys/arm/arm/disassem.c (revision 273826) +++ stable/10/sys/arm/arm/disassem.c (revision 273827) @@ -1,692 +1,693 @@ /* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */ /*- * Copyright (c) 1996 Mark Brinicombe. * Copyright (c) 1996 Brini. * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * db_disasm.c * * Kernel disassembler * * Created : 10/02/96 * * Structured after the sparc/sparc/db_disasm.c by David S. Miller & * Paul Kranenburg * * This code is not complete. Not all instructions are disassembled. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include +#include #include /* * General instruction format * * insn[cc][mod] [operands] * * Those fields with an uppercase format code indicate that the field * follows directly after the instruction before the separator i.e. * they modify the instruction rather than just being an operand to * the instruction. The only exception is the writeback flag which * follows a operand. * * * 2 - print Operand 2 of a data processing instruction * d - destination register (bits 12-15) * n - n register (bits 16-19) * s - s register (bits 8-11) * o - indirect register rn (bits 16-19) (used by swap) * m - m register (bits 0-3) * a - address operand of ldr/str instruction * l - register list for ldm/stm instruction * f - 1st fp operand (register) (bits 12-14) * g - 2nd fp operand (register) (bits 16-18) * h - 3rd fp operand (register/immediate) (bits 0-4) * b - branch address * t - thumb branch address (bits 24, 0-23) * k - breakpoint comment (bits 0-3, 8-19) * X - block transfer type * Y - block transfer type (r13 base) * c - comment field bits(0-23) * p - saved or current status register * F - PSR transfer fields * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN * L - co-processor transfer size * S - set status flag * P - fp precision * Q - fp precision (for ldf/stf) * R - fp rounding * v - co-processor data transfer registers + addressing mode * W - writeback flag * x - instruction in hex * # - co-processor number * y - co-processor data processing registers * z - co-processor register transfer registers */ struct arm32_insn { u_int mask; u_int pattern; char* name; char* format; }; static const struct arm32_insn arm32_i[] = { { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */ { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */ { 0x0f000000, 0x0f000000, "swi", "c" }, { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */ { 0x0f000000, 0x0a000000, "b", "b" }, { 0x0f000000, 0x0b000000, "bl", "b" }, { 0x0fe000f0, 0x00000090, "mul", "Snms" }, { 0x0fe000f0, 0x00200090, "mla", "Snmsd" }, { 0x0fe000f0, 0x00800090, "umull", "Sdnms" }, { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" }, { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" }, { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" }, { 0x0d700000, 0x04200000, "strt", "daW" }, { 0x0d700000, 0x04300000, "ldrt", "daW" }, { 0x0d700000, 0x04600000, "strbt", "daW" }, { 0x0d700000, 0x04700000, "ldrbt", "daW" }, { 0x0c500000, 0x04000000, "str", "daW" }, { 0x0c500000, 0x04100000, "ldr", "daW" }, { 0x0c500000, 0x04400000, "strb", "daW" }, { 0x0c500000, 0x04500000, "ldrb", "daW" }, -#if defined(__FreeBSD_ARCH_armv6__) || (defined(__ARM_ARCH) && __ARM_ARCH >= 6) +#if __ARM_ARCH >= 6 { 0xffffffff, 0xf57ff01f, "clrex", "c" }, { 0x0ff00ff0, 0x01800f90, "strex", "dmo" }, { 0x0ff00fff, 0x01900f9f, "ldrex", "do" }, { 0x0ff00ff0, 0x01a00f90, "strexd", "dmo" }, { 0x0ff00fff, 0x01b00f9f, "ldrexd", "do" }, { 0x0ff00ff0, 0x01c00f90, "strexb", "dmo" }, { 0x0ff00fff, 0x01d00f9f, "ldrexb", "do" }, { 0x0ff00ff0, 0x01e00f90, "strexh", "dmo" }, { 0x0ff00fff, 0x01f00f9f, "ldrexh", "do" }, #endif { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ { 0x0e100000, 0x08000000, "stm", "XnWl" }, { 0x0e100000, 0x08100000, "ldm", "XnWl" }, { 0x0e1000f0, 0x00100090, "ldrb", "de" }, { 0x0e1000f0, 0x00000090, "strb", "de" }, { 0x0e1000f0, 0x001000d0, "ldrsb", "de" }, { 0x0e1000f0, 0x001000b0, "ldrh", "de" }, { 0x0e1000f0, 0x000000b0, "strh", "de" }, { 0x0e1000f0, 0x001000f0, "ldrsh", "de" }, { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */ { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */ { 0x0ff00ff0, 0x01000090, "swp", "dmo" }, { 0x0ff00ff0, 0x01400090, "swpb", "dmo" }, { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */ { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */ { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */ { 0x0ffffff0, 0x012fff10, "bx", "m" }, { 0x0fff0ff0, 0x016f0f10, "clz", "dm" }, { 0x0ffffff0, 0x012fff30, "blx", "m" }, { 0xfff000f0, 0xe1200070, "bkpt", "k" }, { 0x0de00000, 0x00000000, "and", "Sdn2" }, { 0x0de00000, 0x00200000, "eor", "Sdn2" }, { 0x0de00000, 0x00400000, "sub", "Sdn2" }, { 0x0de00000, 0x00600000, "rsb", "Sdn2" }, { 0x0de00000, 0x00800000, "add", "Sdn2" }, { 0x0de00000, 0x00a00000, "adc", "Sdn2" }, { 0x0de00000, 0x00c00000, "sbc", "Sdn2" }, { 0x0de00000, 0x00e00000, "rsc", "Sdn2" }, { 0x0df00000, 0x01100000, "tst", "Dn2" }, { 0x0df00000, 0x01300000, "teq", "Dn2" }, { 0x0de00000, 0x01400000, "cmp", "Dn2" }, { 0x0de00000, 0x01600000, "cmn", "Dn2" }, { 0x0de00000, 0x01800000, "orr", "Sdn2" }, { 0x0de00000, 0x01a00000, "mov", "Sd2" }, { 0x0de00000, 0x01c00000, "bic", "Sdn2" }, { 0x0de00000, 0x01e00000, "mvn", "Sd2" }, { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" }, { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" }, { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" }, { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" }, { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" }, { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" }, { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" }, { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" }, { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" }, { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" }, { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" }, { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" }, { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" }, { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" }, { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" }, { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" }, { 0x0ff08f10, 0x0e208100, "abs", "PRfh" }, { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" }, { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" }, { 0x0ff08f10, 0x0e508100, "log", "PRfh" }, { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" }, { 0x0ff08f10, 0x0e708100, "exp", "PRfh" }, { 0x0ff08f10, 0x0e808100, "sin", "PRfh" }, { 0x0ff08f10, 0x0e908100, "cos", "PRfh" }, { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" }, { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" }, { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" }, { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" }, { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" }, { 0x0e100f00, 0x0c000100, "stf", "QLv" }, { 0x0e100f00, 0x0c100100, "ldf", "QLv" }, { 0x0ff00f10, 0x0e000110, "flt", "PRgd" }, { 0x0ff00f10, 0x0e100110, "fix", "PRdh" }, { 0x0ff00f10, 0x0e200110, "wfs", "d" }, { 0x0ff00f10, 0x0e300110, "rfs", "d" }, { 0x0ff00f10, 0x0e400110, "wfc", "d" }, { 0x0ff00f10, 0x0e500110, "rfc", "d" }, { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" }, { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" }, { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" }, { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" }, { 0xff100010, 0xfe000010, "mcr2", "#z" }, { 0x0f100010, 0x0e000010, "mcr", "#z" }, { 0xff100010, 0xfe100010, "mrc2", "#z" }, { 0x0f100010, 0x0e100010, "mrc", "#z" }, { 0xff000010, 0xfe000000, "cdp2", "#y" }, { 0x0f000010, 0x0e000000, "cdp", "#y" }, { 0xfe100090, 0xfc100000, "ldc2", "L#v" }, { 0x0e100090, 0x0c100000, "ldc", "L#v" }, { 0xfe100090, 0xfc000000, "stc2", "L#v" }, { 0x0e100090, 0x0c000000, "stc", "L#v" }, { 0x00000000, 0x00000000, NULL, NULL } }; static char const arm32_insn_conditions[][4] = { "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", "nv" }; static char const insn_block_transfers[][4] = { "da", "ia", "db", "ib" }; static char const insn_stack_block_transfers[][4] = { "ed", "ea", "fd", "fa" }; static char const op_shifts[][4] = { "lsl", "lsr", "asr", "ror" }; static char const insn_fpa_rounding[][2] = { "", "p", "m", "z" }; static char const insn_fpa_precision[][2] = { "s", "d", "e", "p" }; static char const insn_fpaconstants[][8] = { "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0" }; #define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f] #define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3] #define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3] #define op2_shift(x) op_shifts[(x >> 5) & 3] #define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03] #define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1] #define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] #define insn_fpaimm(x) insn_fpaconstants[x & 0x07] /* Local prototypes */ static void disasm_register_shift(const disasm_interface_t *di, u_int insn); static void disasm_print_reglist(const disasm_interface_t *di, u_int insn); static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc); static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc); static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc); static u_int disassemble_readword(u_int address); static void disassemble_printaddr(u_int address); vm_offset_t disasm(const disasm_interface_t *di, vm_offset_t loc, int altfmt) { struct arm32_insn *i_ptr = (struct arm32_insn *)&arm32_i; u_int insn; int matchp; int branch; char* f_ptr; int fmt; fmt = 0; matchp = 0; insn = di->di_readword(loc); /* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ while (i_ptr->name) { if ((insn & i_ptr->mask) == i_ptr->pattern) { matchp = 1; break; } i_ptr++; } if (!matchp) { di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); return(loc + INSN_SIZE); } /* If instruction forces condition code, don't print it. */ if ((i_ptr->mask & 0xf0000000) == 0xf0000000) di->di_printf("%s", i_ptr->name); else di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); f_ptr = i_ptr->format; /* Insert tab if there are no instruction modifiers */ if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { ++fmt; di->di_printf("\t"); } while (*f_ptr) { switch (*f_ptr) { /* 2 - print Operand 2 of a data processing instruction */ case '2': if (insn & 0x02000000) { int rotate= ((insn >> 7) & 0x1e); di->di_printf("#0x%08x", (insn & 0xff) << (32 - rotate) | (insn & 0xff) >> rotate); } else { disasm_register_shift(di, insn); } break; /* d - destination register (bits 12-15) */ case 'd': di->di_printf("r%d", ((insn >> 12) & 0x0f)); break; /* D - insert 'p' if Rd is R15 */ case 'D': if (((insn >> 12) & 0x0f) == 15) di->di_printf("p"); break; /* n - n register (bits 16-19) */ case 'n': di->di_printf("r%d", ((insn >> 16) & 0x0f)); break; /* s - s register (bits 8-11) */ case 's': di->di_printf("r%d", ((insn >> 8) & 0x0f)); break; /* o - indirect register rn (bits 16-19) (used by swap) */ case 'o': di->di_printf("[r%d]", ((insn >> 16) & 0x0f)); break; /* m - m register (bits 0-4) */ case 'm': di->di_printf("r%d", ((insn >> 0) & 0x0f)); break; /* a - address operand of ldr/str instruction */ case 'a': disasm_insn_ldrstr(di, insn, loc); break; /* e - address operand of ldrh/strh instruction */ case 'e': disasm_insn_ldrhstrh(di, insn, loc); break; /* l - register list for ldm/stm instruction */ case 'l': disasm_print_reglist(di, insn); break; /* f - 1st fp operand (register) (bits 12-14) */ case 'f': di->di_printf("f%d", (insn >> 12) & 7); break; /* g - 2nd fp operand (register) (bits 16-18) */ case 'g': di->di_printf("f%d", (insn >> 16) & 7); break; /* h - 3rd fp operand (register/immediate) (bits 0-4) */ case 'h': if (insn & (1 << 3)) di->di_printf("#%s", insn_fpaimm(insn)); else di->di_printf("f%d", insn & 7); break; /* b - branch address */ case 'b': branch = ((insn << 2) & 0x03ffffff); if (branch & 0x02000000) branch |= 0xfc000000; di->di_printaddr(loc + 8 + branch); break; /* t - blx address */ case 't': branch = ((insn << 2) & 0x03ffffff) | (insn >> 23 & 0x00000002); if (branch & 0x02000000) branch |= 0xfc000000; di->di_printaddr(loc + 8 + branch); break; /* X - block transfer type */ case 'X': di->di_printf("%s", insn_blktrans(insn)); break; /* Y - block transfer type (r13 base) */ case 'Y': di->di_printf("%s", insn_stkblktrans(insn)); break; /* c - comment field bits(0-23) */ case 'c': di->di_printf("0x%08x", (insn & 0x00ffffff)); break; /* k - breakpoint comment (bits 0-3, 8-19) */ case 'k': di->di_printf("0x%04x", (insn & 0x000fff00) >> 4 | (insn & 0x0000000f)); break; /* p - saved or current status register */ case 'p': if (insn & 0x00400000) di->di_printf("spsr"); else di->di_printf("cpsr"); break; /* F - PSR transfer fields */ case 'F': di->di_printf("_"); if (insn & (1 << 16)) di->di_printf("c"); if (insn & (1 << 17)) di->di_printf("x"); if (insn & (1 << 18)) di->di_printf("s"); if (insn & (1 << 19)) di->di_printf("f"); break; /* B - byte transfer flag */ case 'B': if (insn & 0x00400000) di->di_printf("b"); break; /* L - co-processor transfer size */ case 'L': if (insn & (1 << 22)) di->di_printf("l"); break; /* S - set status flag */ case 'S': if (insn & 0x00100000) di->di_printf("s"); break; /* P - fp precision */ case 'P': di->di_printf("%s", insn_fpaprec(insn)); break; /* Q - fp precision (for ldf/stf) */ case 'Q': break; /* R - fp rounding */ case 'R': di->di_printf("%s", insn_fparnd(insn)); break; /* W - writeback flag */ case 'W': if (insn & (1 << 21)) di->di_printf("!"); break; /* # - co-processor number */ case '#': di->di_printf("p%d", (insn >> 8) & 0x0f); break; /* v - co-processor data transfer registers+addressing mode */ case 'v': disasm_insn_ldcstc(di, insn, loc); break; /* x - instruction in hex */ case 'x': di->di_printf("0x%08x", insn); break; /* y - co-processor data processing registers */ case 'y': di->di_printf("%d, ", (insn >> 20) & 0x0f); di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, insn & 0x0f); di->di_printf(", %d", (insn >> 5) & 0x07); break; /* z - co-processor register transfer registers */ case 'z': di->di_printf("%d, ", (insn >> 21) & 0x07); di->di_printf("r%d, c%d, c%d, %d", (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, insn & 0x0f, (insn >> 5) & 0x07); /* if (((insn >> 5) & 0x07) != 0) di->di_printf(", %d", (insn >> 5) & 0x07);*/ break; default: di->di_printf("[%c - unknown]", *f_ptr); break; } if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z') ++f_ptr; else if (*(++f_ptr)) { ++fmt; if (fmt == 1) di->di_printf("\t"); else di->di_printf(", "); } }; di->di_printf("\n"); return(loc + INSN_SIZE); } static void disasm_register_shift(const disasm_interface_t *di, u_int insn) { di->di_printf("r%d", (insn & 0x0f)); if ((insn & 0x00000ff0) == 0) ; else if ((insn & 0x00000ff0) == 0x00000060) di->di_printf(", rrx"); else { if (insn & 0x10) di->di_printf(", %s r%d", op2_shift(insn), (insn >> 8) & 0x0f); else di->di_printf(", %s #%d", op2_shift(insn), (insn >> 7) & 0x1f); } } static void disasm_print_reglist(const disasm_interface_t *di, u_int insn) { int loop; int start; int comma; di->di_printf("{"); start = -1; comma = 0; for (loop = 0; loop < 17; ++loop) { if (start != -1) { if (loop == 16 || !(insn & (1 << loop))) { if (comma) di->di_printf(", "); else comma = 1; if (start == loop - 1) di->di_printf("r%d", start); else di->di_printf("r%d-r%d", start, loop - 1); start = -1; } } else { if (insn & (1 << loop)) start = loop; } } di->di_printf("}"); if (insn & (1 << 22)) di->di_printf("^"); } static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc) { int offset; offset = insn & 0xfff; if ((insn & 0x032f0000) == 0x010f0000) { /* rA = pc, immediate index */ if (insn & 0x00800000) loc += offset; else loc -= offset; di->di_printaddr(loc + 8); } else { di->di_printf("[r%d", (insn >> 16) & 0x0f); if ((insn & 0x03000fff) != 0x01000000) { di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); if (!(insn & 0x00800000)) di->di_printf("-"); if (insn & (1 << 25)) disasm_register_shift(di, insn); else di->di_printf("#0x%03x", offset); } if (insn & (1 << 24)) di->di_printf("]"); } } static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc) { int offset; offset = ((insn & 0xf00) >> 4) | (insn & 0xf); if ((insn & 0x004f0000) == 0x004f0000) { /* rA = pc, immediate index */ if (insn & 0x00800000) loc += offset; else loc -= offset; di->di_printaddr(loc + 8); } else { di->di_printf("[r%d", (insn >> 16) & 0x0f); if ((insn & 0x01400f0f) != 0x01400000) { di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); if (!(insn & 0x00800000)) di->di_printf("-"); if (insn & (1 << 22)) di->di_printf("#0x%02x", offset); else di->di_printf("r%d", (insn & 0x0f)); } if (insn & (1 << 24)) di->di_printf("]"); } } static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc) { if (((insn >> 8) & 0xf) == 1) di->di_printf("f%d, ", (insn >> 12) & 0x07); else di->di_printf("c%d, ", (insn >> 12) & 0x0f); di->di_printf("[r%d", (insn >> 16) & 0x0f); di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); if (!(insn & (1 << 23))) di->di_printf("-"); di->di_printf("#0x%03x", (insn & 0xff) << 2); if (insn & (1 << 24)) di->di_printf("]"); if (insn & (1 << 21)) di->di_printf("!"); } static u_int disassemble_readword(u_int address) { return(*((u_int *)address)); } static void disassemble_printaddr(u_int address) { printf("0x%08x", address); } static const disasm_interface_t disassemble_di = { disassemble_readword, disassemble_printaddr, db_printf }; void disassemble(u_int address) { (void)disasm(&disassemble_di, address, 0); } /* End of disassem.c */ Index: stable/10/sys/arm/include/acle-compat.h =================================================================== --- stable/10/sys/arm/include/acle-compat.h (nonexistent) +++ stable/10/sys/arm/include/acle-compat.h (revision 273827) @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2014 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __ARM_ARCH + +/* ACLE standardises a set of pre-defines that describe the ARM architecture. + These were mostly implemented in GCC around GCC-4.8; older versions + have no, or only partial support. To provide a level of backwards + compatibility we try to work out what the definitions should be, given + the older pre-defines that GCC did produce. This isn't complete, but + it should be enough for use by routines that depend on this header. */ + +/* No need to handle ARMv8, GCC had ACLE support before that. */ + +#define __ARM_ACLE 101 + +# ifdef __ARM_ARCH_7__ +/* The common subset of ARMv7 in all profiles. */ +# define __ARM_ARCH 7 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_LDREX 7 +# define __ARM_FEATURE_UNALIGNED +# endif + +# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__) +# define __ARM_ARCH 7 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_ARCH_ISA_ARM +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_SIMD32 +# define __ARM_FEATURE_DSP +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_LDREX 15 +# define __ARM_FEATURE_UNALIGNED +# ifdef __ARM_ARCH_7A__ +# define __ARM_ARCH_PROFILE 'A' +# else +# define __ARM_ARCH_PROFILE 'R' +# endif +# endif + +# ifdef __ARM_ARCH_7EM__ +# define __ARM_ARCH 7 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_SIMD32 +# define __ARM_FEATURE_DSP +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_LDREX 7 +# define __ARM_FEATURE_UNALIGNED +# define __ARM_ARCH_PROFILE 'M' +# endif + +# ifdef __ARM_ARCH_7M__ +# define __ARM_ARCH 7 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_LDREX 7 +# define __ARM_FEATURE_UNALIGNED +# define __ARM_ARCH_PROFILE 'M' +# endif + +# ifdef __ARM_ARCH_6T2__ +# define __ARM_ARCH 6 +# define __ARM_ARCH_ISA_THUMB 2 +# define __ARM_ARCH_ISA_ARM +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_SIMD32 +# define __ARM_FEATURE_DSP +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_LDREX 4 +# define __ARM_FEATURE_UNALIGNED +# endif + +# ifdef __ARM_ARCH_6M__ +# define __ARM_ARCH 6 +# define __ARM_ARCH_ISA_THUMB 1 +# define __ARM_ARCH_PROFILE 'M' +# endif + +# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \ + || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \ + || defined (__ARM_ARCH_6ZK__) +# define __ARM_ARCH 6 +# define __ARM_ARCH_ISA_THUMB 1 +# define __ARM_ARCH_ISA_ARM +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_SIMD32 +# define __ARM_FEATURE_DSP +# define __ARM_FEATURE_QBIT +# define __ARM_FEATURE_SAT +# define __ARM_FEATURE_UNALIGNED +# ifndef __thumb__ +# if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__) +# define __ARM_FEATURE_LDREX 15 +# else +# define __ARM_FEATURE_LDREX 4 +# endif +# endif +# endif + +# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__) +# define __ARM_ARCH 5 +# define __ARM_ARCH_ISA_ARM +# ifdef __ARM_ARCH_5TE__ +# define __ARM_ARCH_ISA_THUMB 1 +# endif +# define __ARM_FEATURE_CLZ +# define __ARM_FEATURE_DSP +# endif + +# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__) +# define __ARM_ARCH 5 +# define __ARM_ARCH_ISA_ARM +# ifdef __ARM_ARCH_5TE__ +# define __ARM_ARCH_ISA_THUMB 1 +# endif +# define __ARM_FEATURE_CLZ +# endif + +# ifdef __ARM_ARCH_4T__ +# define __ARM_ARCH 4 +# define __ARM_ARCH_ISA_ARM +# define __ARM_ARCH_ISA_THUMB 1 +# endif + +# ifdef __ARM_ARCH_4__ +# define __ARM_ARCH 4 +# define __ARM_ARCH_ISA_ARM +# endif + +# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__) +# define __ARM_ARCH 3 +# define __ARM_ARCH_ISA_ARM +# endif + +# ifdef __ARM_ARCH_2__ +# define __ARM_ARCH 2 +# define __ARM_ARCH_ISA_ARM +# endif + +# ifdef __ARMEB__ +# define __ARM_BIG_ENDIAN +# endif + +/* If we still don't know what the target architecture is, then we're + probably not using GCC. */ +# ifndef __ARM_ARCH +# error Unable to determine architecture version. +# endif + +#endif /* __ARM_ARCH */ Property changes on: stable/10/sys/arm/include/acle-compat.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/10/sys/arm/include/param.h =================================================================== --- stable/10/sys/arm/include/param.h (revision 273826) +++ stable/10/sys/arm/include/param.h (revision 273827) @@ -1,151 +1,152 @@ /*- * Copyright (c) 2001 David E. O'Brien * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)param.h 5.8 (Berkeley) 6/28/91 * $FreeBSD$ */ #ifndef _ARM_INCLUDE_PARAM_H_ #define _ARM_INCLUDE_PARAM_H_ /* * Machine dependent constants for StrongARM */ #include +#include #define STACKALIGNBYTES (8 - 1) #define STACKALIGN(p) ((u_int)(p) & ~STACKALIGNBYTES) #define __PCI_REROUTE_INTERRUPT -#if defined(__FreeBSD_ARCH_armv6__) || (defined(__ARM_ARCH) && __ARM_ARCH >= 6) +#if __ARM_ARCH >= 6 #define _V6_SUFFIX "v6" #else #define _V6_SUFFIX "" #endif #ifdef __ARM_PCS_VFP #define _HF_SUFFIX "hf" #else #define _HF_SUFFIX "" #endif -#ifdef __ARMEB__ +#ifdef __ARM_BIG_ENDIAN #define _EB_SUFFIX "eb" #else #define _EB_SUFFIX "" #endif #ifndef MACHINE #define MACHINE "arm" #endif #ifndef MACHINE_ARCH #define MACHINE_ARCH "arm" _V6_SUFFIX _HF_SUFFIX _EB_SUFFIX #endif #if defined(SMP) || defined(KLD_MODULE) #ifndef MAXCPU #define MAXCPU 4 #endif #else #define MAXCPU 1 #endif /* SMP || KLD_MODULE */ #ifndef MAXMEMDOM #define MAXMEMDOM 1 #endif #define ALIGNBYTES _ALIGNBYTES #define ALIGN(p) _ALIGN(p) /* * ALIGNED_POINTER is a boolean macro that checks whether an address * is valid to fetch data elements of type t from on this architecture. * This does not reflect the optimal alignment, just the possibility * (within reasonable limits). */ #define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t)-1)) == 0) /* * CACHE_LINE_SIZE is the compile-time maximum cache line size for an * architecture. It should be used with appropriate caution. */ #define CACHE_LINE_SHIFT 6 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) #define PAGE_SHIFT 12 #define PAGE_SIZE (1 << PAGE_SHIFT) /* Page size */ #define PAGE_MASK (PAGE_SIZE - 1) #define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t))) #define PDR_SHIFT 20 /* log2(NBPDR) */ #define NBPDR (1 << PDR_SHIFT) #define PDRMASK (NBPDR - 1) #define NPDEPG (1 << (32 - PDR_SHIFT)) #define MAXPAGESIZES 2 /* maximum number of supported page sizes */ #ifndef KSTACK_PAGES #define KSTACK_PAGES 2 #endif /* !KSTACK_PAGES */ #ifndef FPCONTEXTSIZE #define FPCONTEXTSIZE (0x100) #endif #ifndef KSTACK_GUARD_PAGES #define KSTACK_GUARD_PAGES 1 #endif /* !KSTACK_GUARD_PAGES */ #define USPACE_SVC_STACK_TOP (KSTACK_PAGES * PAGE_SIZE) /* * Mach derived conversion macros */ #define trunc_page(x) ((x) & ~PAGE_MASK) #define round_page(x) (((x) + PAGE_MASK) & ~PAGE_MASK) #define trunc_1mpage(x) ((unsigned)(x) & ~PDRMASK) #define round_1mpage(x) ((((unsigned)(x)) + PDRMASK) & ~PDRMASK) #define atop(x) ((unsigned)(x) >> PAGE_SHIFT) #define ptoa(x) ((unsigned)(x) << PAGE_SHIFT) #define arm32_btop(x) ((unsigned)(x) >> PAGE_SHIFT) #define arm32_ptob(x) ((unsigned)(x) << PAGE_SHIFT) #define pgtok(x) ((x) * (PAGE_SIZE / 1024)) #endif /* !_ARM_INCLUDE_PARAM_H_ */ Index: stable/10 =================================================================== --- stable/10 (revision 273826) +++ stable/10 (revision 273827) Property changes on: stable/10 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r269956