Index: head/sys/arm/altera/socfpga/files.socfpga =================================================================== --- head/sys/arm/altera/socfpga/files.socfpga (revision 272711) +++ head/sys/arm/altera/socfpga/files.socfpga (revision 272712) @@ -1,21 +1,22 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/arm/bus_space_generic.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard arm/arm/bus_space-v6.c standard arm/arm/gic.c standard arm/arm/mpcore_timer.c standard arm/altera/socfpga/socfpga_common.c standard arm/altera/socfpga/socfpga_machdep.c standard arm/altera/socfpga/socfpga_manager.c standard arm/altera/socfpga/socfpga_rstmgr.c standard dev/dwc/if_dwc.c optional dwc +dev/mmc/host/dwmmc.c optional dwmmc Index: head/sys/arm/altera/socfpga/socfpga_machdep.c =================================================================== --- head/sys/arm/altera/socfpga/socfpga_machdep.c (revision 272711) +++ head/sys/arm/altera/socfpga/socfpga_machdep.c (revision 272712) @@ -1,107 +1,110 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_ddb.h" #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include #include #include vm_offset_t platform_lastaddr(void) { return (arm_devmap_lastaddr()); } void platform_probe_and_attach(void) { } void platform_gpio_init(void) { } void platform_late_init(void) { } int platform_devmap_init(void) { /* UART */ arm_devmap_add_entry(0xffc00000, 0x100000); /* * USB OTG * * We use static device map for USB due to some bug in the Altera * which throws Translation Fault (P) exception on high load. * It might be caused due to some power save options being turned * on or something else. */ arm_devmap_add_entry(0xffb00000, 0x100000); + /* dwmmc */ + arm_devmap_add_entry(0xff700000, 0x100000); + return (0); } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } int bus_dma_get_range_nb(void) { return (0); } Index: head/sys/arm/conf/EXYNOS5.common =================================================================== --- head/sys/arm/conf/EXYNOS5.common (revision 272711) +++ head/sys/arm/conf/EXYNOS5.common (revision 272712) @@ -1,136 +1,136 @@ # Kernel configuration for Samsung Exynos 5 SoC. # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ makeoptions MODULES_OVERRIDE="" makeoptions WITHOUT_MODULES="ahc" makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WERROR="-Werror" options HZ=100 options SCHED_4BSD # 4BSD scheduler options INET # InterNETworking options INET6 # IPv6 communications protocols options GEOM_PART_BSD # BSD partition scheme options GEOM_PART_MBR # MBR partition scheme options GEOM_PART_GPT # GUID partition tables options TMPFS # Efficient memory filesystem options FFS # Berkeley Fast Filesystem options SOFTUPDATES options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options COMPAT_43 # Compatible with BSD 4.3 [KEEP THIS!] options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # Posix P1003_1B real-time extensions options KBD_INSTALL_CDEV options PREEMPTION options FREEBSD_BOOT_LOADER options VFP # vfp/neon options SMP # Debugging makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols options BREAK_TO_DEBUGGER #options VERBOSE_SYSINIT # Enable verbose sysinit messages options KDB options DDB # Enable the kernel debugger #options INVARIANTS # Enable calls of extra sanity checking #options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS #options WITNESS # Enable checks to detect deadlocks and cycles #options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed #options DIAGNOSTIC # NFS support options NFSCL # Network Filesystem Client options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCLIENT # Uncomment this for NFS root #options NFS_ROOT # NFS usable as /, requires NFSCL #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=ue0 device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards -device sdhci # generic sdhci +device dwmmc options ROOTDEVNAME=\"ufs:/dev/da0\" # Pseudo devices device loop device random device pty device md device gpio # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device musb device ehci #device ohci device xhci device umass device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # SATA #device ata #device atadisk #device mvs # Serial ports device uart # I2C (TWSI) device iic device iicbus # SPI device spibus device exynos_spi # Ethernet device ether device mii device smsc device smscphy # USB ethernet support, requires miibus device miibus device axe # ASIX Electronics USB Ethernet device bpf # Berkeley packet filter Index: head/sys/arm/conf/SOCKIT =================================================================== --- head/sys/arm/conf/SOCKIT (revision 272711) +++ head/sys/arm/conf/SOCKIT (revision 272712) @@ -1,137 +1,137 @@ # Kernel configuration for Terasic SoCKit (Altera Cyclone V SoC). # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident SOCKIT include "../altera/socfpga/std.socfpga" makeoptions MODULES_OVERRIDE="" makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WERROR="-Werror" options HZ=100 options SCHED_4BSD # 4BSD scheduler options INET # InterNETworking options INET6 # IPv6 communications protocols options GEOM_PART_BSD # BSD partition scheme options GEOM_PART_MBR # MBR partition scheme options GEOM_PART_GPT # GUID partition tables options TMPFS # Efficient memory filesystem options FFS # Berkeley Fast Filesystem options SOFTUPDATES options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options COMPAT_43 # Compatible with BSD 4.3 [KEEP THIS!] options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # Posix P1003_1B real-time extensions options KBD_INSTALL_CDEV options PREEMPTION options FREEBSD_BOOT_LOADER options VFP # vfp/neon #options SMP # Debugging makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols options BREAK_TO_DEBUGGER #options VERBOSE_SYSINIT # Enable verbose sysinit messages options KDB options DDB # Enable the kernel debugger options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS #options WITNESS # Enable checks to detect deadlocks and cycles #options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed #options DIAGNOSTIC # NFS support options NFSCL # Network Filesystem Client options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCLIENT # Uncomment this for NFS root #options NFS_ROOT # NFS usable as /, requires NFSCL #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=ue0 device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards -device sdhci # generic sdhci +device dwmmc options ROOTDEVNAME=\"ufs:/dev/da0\" # Pseudo devices device loop device random device pty device md device gpio # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb options USB_DEBUG #options USB_REQ_DEBUG #options USB_VERBOSE #device musb device dwcotg device umass device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device pass # Serial ports device uart device uart_ns8250 # I2C (TWSI) device iic device iicbus # SPI device spibus # Ethernet device ether device mii device smsc device smscphy device dwc # USB ethernet support, requires miibus device miibus device axe # ASIX Electronics USB Ethernet device bpf # Berkeley packet filter #FDT options FDT options FDT_DTB_STATIC makeoptions FDT_DTS_FILE=socfpga-sockit.dts Index: head/sys/arm/samsung/exynos/exynos5_machdep.c =================================================================== --- head/sys/arm/samsung/exynos/exynos5_machdep.c (revision 272711) +++ head/sys/arm/samsung/exynos/exynos5_machdep.c (revision 272712) @@ -1,96 +1,99 @@ /*- * Copyright (c) 2013 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_ddb.h" #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include #include #include vm_offset_t platform_lastaddr(void) { return (arm_devmap_lastaddr()); } void platform_probe_and_attach(void) { } void platform_gpio_init(void) { } void platform_late_init(void) { } int platform_devmap_init(void) { /* CHIP ID */ arm_devmap_add_entry(0x10000000, 0x100000); /* UART */ arm_devmap_add_entry(0x12C00000, 0x100000); + /* DWMMC */ + arm_devmap_add_entry(0x12200000, 0x100000); + return (0); } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } int bus_dma_get_range_nb(void) { return (0); } Index: head/sys/arm/samsung/exynos/files.exynos5 =================================================================== --- head/sys/arm/samsung/exynos/files.exynos5 (revision 272711) +++ head/sys/arm/samsung/exynos/files.exynos5 (revision 272712) @@ -1,36 +1,36 @@ # $FreeBSD$ kern/kern_clocksource.c standard arm/arm/bus_space_generic.c standard arm/arm/bus_space_asm_generic.S standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm10.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard arm/arm/bus_space-v6.c standard arm/arm/gic.c standard arm/arm/generic_timer.c standard arm/samsung/exynos/exynos5_mct.c standard arm/samsung/exynos/exynos5_mp.c optional smp arm/samsung/exynos/exynos5_common.c standard arm/samsung/exynos/exynos5_machdep.c standard arm/samsung/exynos/exynos5_combiner.c standard arm/samsung/exynos/exynos5_pad.c optional gpio arm/samsung/exynos/exynos_uart.c optional uart arm/samsung/exynos/exynos5_ehci.c optional ehci arm/samsung/exynos/exynos5_xhci.c optional xhci arm/samsung/exynos/exynos5_fimd.c optional vt arm/samsung/exynos/exynos5_i2c.c optional iicbus arm/samsung/exynos/exynos5_usb_phy.c standard arm/samsung/exynos/exynos5_pmu.c standard arm/samsung/exynos/exynos5_spi.c optional exynos_spi # chromebook drivers arm/samsung/exynos/chrome_ec.c optional chrome_ec_i2c arm/samsung/exynos/chrome_ec_spi.c optional chrome_ec_spi arm/samsung/exynos/chrome_kb.c optional chrome_kb -#dev/sdhci/sdhci_fdt.c optional sdhci +dev/mmc/host/dwmmc.c optional dwmmc Index: head/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts =================================================================== --- head/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts (revision 272711) +++ head/sys/boot/fdt/dts/arm/exynos5420-arndale-octa.dts (revision 272712) @@ -1,59 +1,70 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /dts-v1/; /include/ "exynos5420.dtsi" / { model = "Arndale Octa Board"; memory { device_type = "memory"; reg = < 0x20000000 0x7f200000 >; /* 2G */ }; SOC: Exynos5@0 { serial3: serial@12C30000 { status = "okay"; }; usb@12110000 { status = "okay"; }; - sdhci@12220000 { - status = "disabled"; + mmc2: dwmmc@12220000 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-frequency = <50000000>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; }; }; chosen { stdin = &serial3; stdout = &serial3; }; }; Index: head/sys/boot/fdt/dts/arm/exynos5420-peach-pit.dts =================================================================== --- head/sys/boot/fdt/dts/arm/exynos5420-peach-pit.dts (revision 272711) +++ head/sys/boot/fdt/dts/arm/exynos5420-peach-pit.dts (revision 272712) @@ -1,72 +1,87 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /dts-v1/; /include/ "exynos5420.dtsi" / { model = "Chromebook Peach Pit"; memory { device_type = "memory"; reg = < 0x20000000 0xdf000000 >; /* 3.5G */ }; SOC: Exynos5@0 { fimd0: fimd@14400000 { status = "okay"; panel-size = < 1366 768 >; panel-hsync = < 80 32 48 >; panel-vsync = < 14 5 3 >; panel-clk-div = < 17 >; panel-backlight-pin = < 25 >; }; spi2: spi@12d40000 { status = "okay"; }; keyboard-controller { compatible = "google,mkbp-keyb"; google,key-rows = <8>; google,key-columns = <13>; freebsd,intr-gpio = < 21 >; }; usbdrd_phy0: phy@12100000 { vbus-supply = < 217 >; }; usbdrd_phy1: phy@12500000 { vbus-supply = < 218 >; }; + + mmc2: dwmmc@12220000 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + bus-frequency = <50000000>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; }; }; Index: head/sys/boot/fdt/dts/arm/exynos5420.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/exynos5420.dtsi (revision 272711) +++ head/sys/boot/fdt/dts/arm/exynos5420.dtsi (revision 272712) @@ -1,85 +1,112 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /include/ "exynos5.dtsi" / { compatible = "samsung,exynos5420", "samsung,exynos5"; SOC: Exynos5@0 { pmu_system_controller: system-controller@10040000 { compatible = "samsung,exynos5420-pmu"; status = "okay"; }; pad0: pad@11400000 { compatible = "samsung,exynos5420-padctrl"; status = "okay"; reg = <0x13400000 0x1000>, <0x13410000 0x1000>, <0x14000000 0x1000>, <0x14010000 0x1000>, <0x03860000 0x1000>; interrupts = < 77 110 78 82 79 >; interrupt-parent = <&GIC>; }; serial0: serial@12C00000 { clock-frequency = < 50000000 >; }; serial1: serial@12C10000 { clock-frequency = < 50000000 >; }; serial2: serial@12C20000 { clock-frequency = < 50000000 >; }; serial3: serial@12C30000 { clock-frequency = < 50000000 >; }; usbdrd_phy0: phy@12100000 { status = "okay"; }; usbdrd_phy1: phy@12500000 { status = "okay"; }; xhci@12000000 { status = "okay"; }; xhci@12400000 { status = "okay"; }; + + mmc0: dwmmc@12200000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + reg = <0x12200000 0x10000>; + interrupts = <107>; + interrupt-parent = <&GIC>; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mmc1: dwmmc@12210000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + reg = <0x12210000 0x10000>; + interrupts = <108>; + interrupt-parent = <&GIC>; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mmc2: dwmmc@12220000 { + compatible = "samsung,exynos5420-dw-mshc"; + reg = <0x12220000 0x10000>; + interrupts = <109>; + interrupt-parent = <&GIC>; + fifo-depth = <0x40>; + status = "disabled"; + }; }; }; Index: head/sys/boot/fdt/dts/arm/socfpga-sockit.dts =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga-sockit.dts (revision 272711) +++ head/sys/boot/fdt/dts/arm/socfpga-sockit.dts (revision 272712) @@ -1,65 +1,78 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /dts-v1/; /include/ "socfpga.dtsi" / { model = "Terasic SoCKit"; compatible = "altr,socfpga-cyclone5", "altr,socfpga"; memory { device_type = "memory"; reg = < 0x00000000 0x40000000 >; /* 1G RAM */ }; SOC: socfpga { serial0: serial@ffc02000 { status = "okay"; }; usb1: usb@ffb40000 { status = "okay"; }; gmac1: ethernet@ff702000 { status = "okay"; }; + + mmc: dwmmc@ff704000 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + broken-cd; + bus-frequency = <25000000>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; }; chosen { bootargs = "-v"; stdin = "serial0"; stdout = "serial0"; }; }; Index: head/sys/boot/fdt/dts/arm/socfpga.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/socfpga.dtsi (revision 272711) +++ head/sys/boot/fdt/dts/arm/socfpga.dtsi (revision 272712) @@ -1,156 +1,165 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ / { compatible = "altr,socfpga"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&GIC>; aliases { soc = &SOC; rstmgr = &rstmgr; l3regs = &l3regs; serial0 = &serial0; serial1 = &serial1; }; SOC: socfpga { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; bus-frequency = <0>; GIC: interrupt-controller@fffed000 { compatible = "arm,gic"; reg = < 0xfffed000 0x1000 >, /* Distributor */ < 0xfffec100 0x100 >; /* CPU Interface */ interrupt-controller; #interrupt-cells = <1>; }; mp_tmr@40002100 { compatible = "arm,mpcore-timers"; clock-frequency = <200000000>; #address-cells = <1>; #size-cells = <0>; reg = < 0xfffec200 0x100 >, /* Global Timer */ < 0xfffec600 0x100 >; /* Private Timer */ interrupts = < 27 29 >; interrupt-parent = < &GIC >; }; sysmgr: sysmgr@ffd08000 { compatible = "altr,sys-mgr"; reg = <0xffd08000 0x1000>; }; rstmgr: rstmgr@ffd05000 { compatible = "altr,rst-mgr"; reg = <0xffd05000 0x1000>; }; l3regs: l3regs@ff800000 { compatible = "altr,l3regs"; reg = <0xff800000 0x1000>; }; fpgamgr: fpgamgr@ff706000 { compatible = "altr,fpga-mgr"; reg = <0xff706000 0x1000>, /* FPGAMGRREGS */ <0xffb90000 0x1000>; /* FPGAMGRDATA */ interrupts = < 207 >; interrupt-parent = <&GIC>; }; serial0: serial@ffc02000 { compatible = "ns16550"; reg = <0xffc02000 0x1000>; reg-shift = <2>; interrupts = <194>; interrupt-parent = <&GIC>; current-speed = <115200>; clock-frequency = < 100000000 >; status = "disabled"; }; serial1: serial@ffc03000 { compatible = "ns16550"; reg = <0xffc03000 0x1000>; reg-shift = <2>; interrupts = <195>; interrupt-parent = <&GIC>; current-speed = <115200>; clock-frequency = < 100000000 >; status = "disabled"; }; usb0: usb@ffb00000 { compatible = "synopsys,designware-hs-otg2"; reg = <0xffb00000 0xffff>; interrupts = <157>; interrupt-parent = <&GIC>; status = "disabled"; }; usb1: usb@ffb40000 { compatible = "synopsys,designware-hs-otg2"; reg = <0xffb40000 0xffff>; interrupts = <160>; interrupt-parent = <&GIC>; dr_mode = "host"; status = "disabled"; }; gmac0: ethernet@ff700000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; reg = <0xff700000 0x2000>; interrupts = <147>; interrupt-parent = <&GIC>; phy-mode = "rgmii"; status = "disabled"; }; gmac1: ethernet@ff702000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; reg = <0xff702000 0x2000>; interrupts = <152>; interrupt-parent = <&GIC>; phy-mode = "rgmii"; status = "disabled"; }; + + mmc: dwmmc@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <171>; + interrupt-parent = <&GIC>; + fifo-depth = <0x400>; + status = "disabled"; + }; }; }; Index: head/sys/dev/mmc/host/dwmmc.c =================================================================== --- head/sys/dev/mmc/host/dwmmc.c (nonexistent) +++ head/sys/dev/mmc/host/dwmmc.c (revision 272712) @@ -0,0 +1,1103 @@ +/*- + * Copyright (c) 2014 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Synopsys DesignWare Mobile Storage Host Controller + * Chapter 14, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "mmcbr_if.h" + +#define dprintf(x, arg...) + +#define READ4(_sc, _reg) \ + bus_read_4((_sc)->res[0], _reg) +#define WRITE4(_sc, _reg, _val) \ + bus_write_4((_sc)->res[0], _reg, _val) + +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +#define DWMMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) +#define DWMMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) +#define DWMMC_LOCK_INIT(_sc) \ + mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ + "dwmmc", MTX_DEF) +#define DWMMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); +#define DWMMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); +#define DWMMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); + +#define PENDING_CMD 0x01 +#define PENDING_STOP 0x02 +#define CARD_INIT_DONE 0x04 + +#define DWMMC_DATA_ERR_FLAGS (SDMMC_INTMASK_DRT | SDMMC_INTMASK_DCRC \ + |SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE \ + |SDMMC_INTMASK_EBE) +#define DWMMC_CMD_ERR_FLAGS (SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC \ + |SDMMC_INTMASK_RE) +#define DWMMC_ERR_FLAGS (DWMMC_DATA_ERR_FLAGS | DWMMC_CMD_ERR_FLAGS \ + |SDMMC_INTMASK_HLE) + +#define DES0_DIC (1 << 1) +#define DES0_LD (1 << 2) +#define DES0_FS (1 << 3) +#define DES0_CH (1 << 4) +#define DES0_ER (1 << 5) +#define DES0_CES (1 << 30) +#define DES0_OWN (1 << 31) + +#define DES1_BS1_MASK 0xfff +#define DES1_BS1_SHIFT 0 + +struct idmac_desc { + uint32_t des0; /* control */ + uint32_t des1; /* bufsize */ + uint32_t des2; /* buf1 phys addr */ + uint32_t des3; /* buf2 phys addr or next descr */ +}; + +#define DESC_COUNT 256 +#define DESC_SIZE (sizeof(struct idmac_desc) * DESC_COUNT) +#define DEF_MSIZE 0x2 /* Burst size of multiple transaction */ + +struct dwmmc_softc { + struct resource *res[2]; + bus_space_tag_t bst; + bus_space_handle_t bsh; + device_t dev; + void *intr_cookie; + struct mmc_host host; + struct mtx sc_mtx; + struct mmc_request *req; + struct mmc_command *curcmd; + uint32_t flags; + uint32_t hwtype; + uint32_t use_auto_stop; + + bus_dma_tag_t desc_tag; + bus_dmamap_t desc_map; + struct idmac_desc *desc_ring; + bus_addr_t desc_ring_paddr; + bus_dma_tag_t buf_tag; + bus_dmamap_t buf_map; + + uint32_t bus_busy; + uint32_t dto_rcvd; + uint32_t acd_rcvd; + uint32_t cmd_done; + uint32_t bus_hz; + uint32_t fifo_depth; + uint32_t num_slots; + uint32_t sdr_timing; + uint32_t ddr_timing; +}; + +static void dwmmc_next_operation(struct dwmmc_softc *); +static int dwmmc_setup_bus(struct dwmmc_softc *, int); +static int dma_done(struct dwmmc_softc *, struct mmc_command *); +static int dma_stop(struct dwmmc_softc *); + +static struct resource_spec dwmmc_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { -1, 0 } +}; + +enum { + HWTYPE_NONE, + HWTYPE_ALTERA, + HWTYPE_EXYNOS, +}; + +#define HWTYPE_MASK (0x0000ffff) +#define HWFLAG_MASK (0xffff << 16) + +static struct ofw_compat_data compat_data[] = { + {"altr,socfpga-dw-mshc", HWTYPE_ALTERA}, + {"samsung,exynos5420-dw-mshc", HWTYPE_EXYNOS}, + {NULL, HWTYPE_NONE}, +}; + +static void +dwmmc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + + if (error != 0) + return; + *(bus_addr_t *)arg = segs[0].ds_addr; +} + +static void +dwmmc_ring_setup(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + struct dwmmc_softc *sc; + int idx; + + if (error != 0) + return; + + sc = arg; + + dprintf("nsegs %d seg0len %lu\n", nsegs, segs[0].ds_len); + + for (idx = 0; idx < nsegs; idx++) { + sc->desc_ring[idx].des0 = (DES0_OWN | DES0_DIC | DES0_CH); + sc->desc_ring[idx].des1 = segs[idx].ds_len; + sc->desc_ring[idx].des2 = segs[idx].ds_addr; + + if (idx == 0) + sc->desc_ring[idx].des0 |= DES0_FS; + + if (idx == (nsegs - 1)) { + sc->desc_ring[idx].des0 &= ~(DES0_DIC | DES0_CH); + sc->desc_ring[idx].des0 |= DES0_LD; + } + } +} + +static int +dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits) +{ + int reg; + int i; + + reg = READ4(sc, SDMMC_CTRL); + reg |= (reset_bits); + WRITE4(sc, SDMMC_CTRL, reg); + + /* Wait reset done */ + for (i = 0; i < 100; i++) { + if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) + return (0); + DELAY(10); + }; + + device_printf(sc->dev, "Reset failed\n"); + + return (1); +} + +static int +dma_setup(struct dwmmc_softc *sc) +{ + int error; + int nidx; + int idx; + + /* + * Set up TX descriptor ring, descriptors, and dma maps. + */ + error = bus_dma_tag_create( + bus_get_dma_tag(sc->dev), /* Parent tag. */ + 4096, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + DESC_SIZE, 1, /* maxsize, nsegments */ + DESC_SIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->desc_tag); + if (error != 0) { + device_printf(sc->dev, + "could not create ring DMA tag.\n"); + return (1); + } + + error = bus_dmamem_alloc(sc->desc_tag, (void**)&sc->desc_ring, + BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, + &sc->desc_map); + if (error != 0) { + device_printf(sc->dev, + "could not allocate descriptor ring.\n"); + return (1); + } + + error = bus_dmamap_load(sc->desc_tag, sc->desc_map, + sc->desc_ring, DESC_SIZE, dwmmc_get1paddr, + &sc->desc_ring_paddr, 0); + if (error != 0) { + device_printf(sc->dev, + "could not load descriptor ring map.\n"); + return (1); + } + + for (idx = 0; idx < DESC_COUNT; idx++) { + sc->desc_ring[idx].des0 = DES0_CH; + sc->desc_ring[idx].des1 = 0; + nidx = (idx + 1) % DESC_COUNT; + sc->desc_ring[idx].des3 = sc->desc_ring_paddr + \ + (nidx * sizeof(struct idmac_desc)); + } + + error = bus_dma_tag_create( + bus_get_dma_tag(sc->dev), /* Parent tag. */ + 4096, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + DESC_COUNT*MMC_SECTOR_SIZE, /* maxsize */ + DESC_COUNT, /* nsegments */ + MMC_SECTOR_SIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->buf_tag); + if (error != 0) { + device_printf(sc->dev, + "could not create ring DMA tag.\n"); + return (1); + } + + error = bus_dmamap_create(sc->buf_tag, 0, + &sc->buf_map); + if (error != 0) { + device_printf(sc->dev, + "could not create TX buffer DMA map.\n"); + return (1); + } + + return (0); +} + +static void +dwmmc_cmd_done(struct dwmmc_softc *sc) +{ + struct mmc_command *cmd; + + cmd = sc->curcmd; + if (cmd == NULL) + return; + + if (cmd->flags & MMC_RSP_PRESENT) { + if (cmd->flags & MMC_RSP_136) { + cmd->resp[3] = READ4(sc, SDMMC_RESP0); + cmd->resp[2] = READ4(sc, SDMMC_RESP1); + cmd->resp[1] = READ4(sc, SDMMC_RESP2); + cmd->resp[0] = READ4(sc, SDMMC_RESP3); + } else { + cmd->resp[3] = 0; + cmd->resp[2] = 0; + cmd->resp[1] = 0; + cmd->resp[0] = READ4(sc, SDMMC_RESP0); + } + } +} + +static void +dwmmc_tasklet(struct dwmmc_softc *sc) +{ + struct mmc_command *cmd; + + cmd = sc->curcmd; + if (cmd == NULL) + return; + + if (cmd->error != MMC_ERR_NONE) { + dwmmc_next_operation(sc); + } else if (!cmd->data && sc->cmd_done) { + dwmmc_next_operation(sc); + } else if (cmd->data && sc->dto_rcvd) { + if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || + cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && + sc->use_auto_stop) { + if (sc->acd_rcvd) + dwmmc_next_operation(sc); + } else { + dwmmc_next_operation(sc); + } + } +} + +static void +dwmmc_intr(void *arg) +{ + struct mmc_command *cmd; + struct dwmmc_softc *sc; + uint32_t reg; + + sc = arg; + + DWMMC_LOCK(sc); + + cmd = sc->curcmd; + + /* First handle SDMMC controller interrupts */ + reg = READ4(sc, SDMMC_MINTSTS); + if (reg) { + dprintf("%s 0x%08x\n", __func__, reg); + + if (reg & DWMMC_CMD_ERR_FLAGS) { + WRITE4(sc, SDMMC_RINTSTS, DWMMC_CMD_ERR_FLAGS); + dprintf("cmd err 0x%08x cmd 0x%08x\n", + reg, cmd->opcode); + cmd->error = MMC_ERR_TIMEOUT; + } + + if (reg & DWMMC_DATA_ERR_FLAGS) { + WRITE4(sc, SDMMC_RINTSTS, DWMMC_DATA_ERR_FLAGS); + dprintf("data err 0x%08x cmd 0x%08x\n", + reg, cmd->opcode); + cmd->error = MMC_ERR_FAILED; + + dma_done(sc, cmd); + dma_stop(sc); + DWMMC_UNLOCK(sc); + return; + } + + if (reg & SDMMC_INTMASK_CMD_DONE) { + dwmmc_cmd_done(sc); + sc->cmd_done = 1; + WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CMD_DONE); + } + + if (reg & SDMMC_INTMASK_ACD) { + sc->acd_rcvd = 1; + WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_ACD); + } + + if (reg & SDMMC_INTMASK_DTO) { + sc->dto_rcvd = 1; + WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_DTO); + } + + if (reg & SDMMC_INTMASK_CD) { + /* XXX: Handle card detect */ + WRITE4(sc, SDMMC_RINTSTS, SDMMC_INTMASK_CD); + } + } + + /* Now handle DMA interrupts */ + reg = READ4(sc, SDMMC_IDSTS); + if (reg) { + dprintf("dma intr 0x%08x\n", reg); + if (reg & (SDMMC_IDINTEN_TI | SDMMC_IDINTEN_RI)) { + WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI | + SDMMC_IDINTEN_RI)); + WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI); + dma_done(sc, cmd); + } + } + + dwmmc_tasklet(sc); + + DWMMC_UNLOCK(sc); +} + +static int +parse_fdt(struct dwmmc_softc *sc) +{ + pcell_t dts_value[3]; + phandle_t node; + int len; + + if ((node = ofw_bus_get_node(sc->dev)) == -1) + return (ENXIO); + + /* fifo-depth */ + if ((len = OF_getproplen(node, "fifo-depth")) <= 0) + return (ENXIO); + OF_getencprop(node, "fifo-depth", dts_value, len); + sc->fifo_depth = dts_value[0]; + + /* num-slots */ + if ((len = OF_getproplen(node, "num-slots")) <= 0) + return (ENXIO); + OF_getencprop(node, "num-slots", dts_value, len); + sc->num_slots = dts_value[0]; + + /* + * We need some platform-specific code to know + * what the clock is supplied for our device. + * For now rely on the value specified in FDT. + */ + if ((len = OF_getproplen(node, "bus-frequency")) <= 0) + return (ENXIO); + OF_getencprop(node, "bus-frequency", dts_value, len); + sc->bus_hz = dts_value[0]; + + /* + * Platform-specific stuff + * XXX: Move to separate file + */ + + if ((sc->hwtype & HWTYPE_MASK) != HWTYPE_EXYNOS) + return (0); + + if ((len = OF_getproplen(node, "samsung,dw-mshc-ciu-div")) <= 0) + return (ENXIO); + OF_getencprop(node, "samsung,dw-mshc-ciu-div", dts_value, len); + sc->sdr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT); + sc->ddr_timing = (dts_value[0] << SDMMC_CLKSEL_DIVIDER_SHIFT); + + if ((len = OF_getproplen(node, "samsung,dw-mshc-sdr-timing")) <= 0) + return (ENXIO); + OF_getencprop(node, "samsung,dw-mshc-sdr-timing", dts_value, len); + sc->sdr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) | + (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT)); + + if ((len = OF_getproplen(node, "samsung,dw-mshc-ddr-timing")) <= 0) + return (ENXIO); + OF_getencprop(node, "samsung,dw-mshc-ddr-timing", dts_value, len); + sc->ddr_timing |= ((dts_value[0] << SDMMC_CLKSEL_SAMPLE_SHIFT) | + (dts_value[1] << SDMMC_CLKSEL_DRIVE_SHIFT)); + + return (0); +} + +static int +dwmmc_probe(device_t dev) +{ + uintptr_t hwtype; + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + if (hwtype == HWTYPE_NONE) + return (ENXIO); + + device_set_desc(dev, "Synopsys DesignWare Mobile " + "Storage Host Controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +dwmmc_attach(device_t dev) +{ + struct dwmmc_softc *sc; + device_t child; + int error; + int slot; + + sc = device_get_softc(dev); + + sc->dev = dev; + sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + + /* Why not to use Auto Stop? It save a hundred of irq per second */ + sc->use_auto_stop = 1; + + error = parse_fdt(sc); + if (error != 0) { + device_printf(dev, "Can't get FDT property.\n"); + return (ENXIO); + } + + DWMMC_LOCK_INIT(sc); + + if (bus_alloc_resources(dev, dwmmc_spec, sc->res)) { + device_printf(dev, "could not allocate resources\n"); + return (ENXIO); + } + + /* Memory interface */ + sc->bst = rman_get_bustag(sc->res[0]); + sc->bsh = rman_get_bushandle(sc->res[0]); + + /* Setup interrupt handler. */ + error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, + NULL, dwmmc_intr, sc, &sc->intr_cookie); + if (error != 0) { + device_printf(dev, "could not setup interrupt handler.\n"); + return (ENXIO); + } + + device_printf(dev, "Hardware version ID is %04x\n", + READ4(sc, SDMMC_VERID) & 0xffff); + + WRITE4(sc, EMMCP_MPSBEGIN0, 0); + WRITE4(sc, EMMCP_SEND0, 0); + WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT | + MPSCTRL_SECURE_WRITE_BIT | + MPSCTRL_NON_SECURE_READ_BIT | + MPSCTRL_NON_SECURE_WRITE_BIT | + MPSCTRL_VALID)); + + /* XXX: we support operation for slot index 0 only */ + slot = 0; + WRITE4(sc, SDMMC_PWREN, (1 << slot)); + + /* Reset all */ + if (dwmmc_ctrl_reset(sc, (SDMMC_CTRL_RESET | + SDMMC_CTRL_FIFO_RESET | + SDMMC_CTRL_DMA_RESET))) + return (ENXIO); + + dwmmc_setup_bus(sc, sc->host.f_min); + + if (dma_setup(sc)) + return (ENXIO); + + /* Install desc base */ + WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr); + + /* Enable DMA interrupts */ + WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK); + WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI | + SDMMC_IDINTEN_RI | + SDMMC_IDINTEN_TI)); + + /* Clear and disable interrups for a while */ + WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); + WRITE4(sc, SDMMC_INTMASK, 0); + + /* Maximum timeout */ + WRITE4(sc, SDMMC_TMOUT, 0xffffffff); + + /* Enable interrupts */ + WRITE4(sc, SDMMC_RINTSTS, 0xffffffff); + WRITE4(sc, SDMMC_INTMASK, (SDMMC_INTMASK_CMD_DONE | + SDMMC_INTMASK_DTO | + SDMMC_INTMASK_ACD | + SDMMC_INTMASK_TXDR | + SDMMC_INTMASK_RXDR | + DWMMC_ERR_FLAGS | + SDMMC_INTMASK_CD)); + WRITE4(sc, SDMMC_CTRL, SDMMC_CTRL_INT_ENABLE); + + sc->host.f_min = 400000; + sc->host.f_max = 200000000; + sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; + sc->host.caps = MMC_CAP_4_BIT_DATA; + + child = device_add_child(dev, "mmc", 0); + return (bus_generic_attach(dev)); +} + +static int +dwmmc_setup_bus(struct dwmmc_softc *sc, int freq) +{ + int tout; + int div; + + if (freq == 0) { + WRITE4(sc, SDMMC_CLKENA, 0); + WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | + SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); + + tout = 1000; + do { + if (tout-- < 0) { + device_printf(sc->dev, "Failed update clk\n"); + return (1); + } + } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); + + return (0); + } + + WRITE4(sc, SDMMC_CLKENA, 0); + WRITE4(sc, SDMMC_CLKSRC, 0); + + div = (sc->bus_hz != freq) ? DIV_ROUND_UP(sc->bus_hz, 2 * freq) : 0; + + WRITE4(sc, SDMMC_CLKDIV, div); + WRITE4(sc, SDMMC_CMD, (SDMMC_CMD_WAIT_PRVDATA | + SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START)); + + tout = 1000; + do { + if (tout-- < 0) { + device_printf(sc->dev, "Failed to update clk"); + return (1); + } + } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); + + WRITE4(sc, SDMMC_CLKENA, (SDMMC_CLKENA_CCLK_EN | SDMMC_CLKENA_LP)); + WRITE4(sc, SDMMC_CMD, SDMMC_CMD_WAIT_PRVDATA | + SDMMC_CMD_UPD_CLK_ONLY | SDMMC_CMD_START); + + tout = 1000; + do { + if (tout-- < 0) { + device_printf(sc->dev, "Failed to enable clk\n"); + return (1); + } + } while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START); + + return (0); +} + +static int +dwmmc_update_ios(device_t brdev, device_t reqdev) +{ + struct dwmmc_softc *sc; + struct mmc_ios *ios; + + sc = device_get_softc(brdev); + ios = &sc->host.ios; + + dprintf("Setting up clk %u bus_width %d\n", + ios->clock, ios->bus_width); + + dwmmc_setup_bus(sc, ios->clock); + + if (ios->bus_width == bus_width_8) + WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_8BIT); + else if (ios->bus_width == bus_width_4) + WRITE4(sc, SDMMC_CTYPE, SDMMC_CTYPE_4BIT); + else + WRITE4(sc, SDMMC_CTYPE, 0); + + if ((sc->hwtype & HWTYPE_MASK) == HWTYPE_EXYNOS) { + /* XXX: take care about DDR or SDR use here */ + WRITE4(sc, SDMMC_CLKSEL, sc->sdr_timing); + } + + /* + * XXX: take care about DDR bit + * + * reg = READ4(sc, SDMMC_UHS_REG); + * reg |= (SDMMC_UHS_REG_DDR); + * WRITE4(sc, SDMMC_UHS_REG, reg); + */ + + return (0); +} + +static int +dma_done(struct dwmmc_softc *sc, struct mmc_command *cmd) +{ + struct mmc_data *data; + + data = cmd->data; + + if (data->flags & MMC_DATA_WRITE) + bus_dmamap_sync(sc->buf_tag, sc->buf_map, + BUS_DMASYNC_POSTWRITE); + else + bus_dmamap_sync(sc->buf_tag, sc->buf_map, + BUS_DMASYNC_POSTREAD); + + bus_dmamap_unload(sc->buf_tag, sc->buf_map); + + return (0); +} + +static int +dma_stop(struct dwmmc_softc *sc) +{ + int reg; + + reg = READ4(sc, SDMMC_CTRL); + reg &= ~(SDMMC_CTRL_USE_IDMAC); + reg |= (SDMMC_CTRL_DMA_RESET); + WRITE4(sc, SDMMC_CTRL, reg); + + reg = READ4(sc, SDMMC_BMOD); + reg &= ~(SDMMC_BMOD_DE | SDMMC_BMOD_FB); + reg |= (SDMMC_BMOD_SWR); + WRITE4(sc, SDMMC_BMOD, reg); + + return (0); +} + +static int +dma_prepare(struct dwmmc_softc *sc, struct mmc_command *cmd) +{ + struct mmc_data *data; + int len; + int err; + int reg; + + data = cmd->data; + len = data->len; + + reg = READ4(sc, SDMMC_INTMASK); + reg &= ~(SDMMC_INTMASK_TXDR | SDMMC_INTMASK_RXDR); + WRITE4(sc, SDMMC_INTMASK, reg); + + err = bus_dmamap_load(sc->buf_tag, sc->buf_map, + data->data, data->len, dwmmc_ring_setup, + sc, BUS_DMA_NOWAIT); + if (err != 0) + panic("dmamap_load failed\n"); + + if (data->flags & MMC_DATA_WRITE) + bus_dmamap_sync(sc->buf_tag, sc->buf_map, + BUS_DMASYNC_PREWRITE); + else + bus_dmamap_sync(sc->buf_tag, sc->buf_map, + BUS_DMASYNC_PREREAD); + + reg = (DEF_MSIZE << SDMMC_FIFOTH_MSIZE_S); + reg |= ((sc->fifo_depth / 2) - 1) << SDMMC_FIFOTH_RXWMARK_S; + reg |= (sc->fifo_depth / 2) << SDMMC_FIFOTH_TXWMARK_S; + + WRITE4(sc, SDMMC_FIFOTH, reg); + wmb(); + + reg = READ4(sc, SDMMC_CTRL); + reg |= (SDMMC_CTRL_USE_IDMAC | SDMMC_CTRL_DMA_ENABLE); + WRITE4(sc, SDMMC_CTRL, reg); + wmb(); + + reg = READ4(sc, SDMMC_BMOD); + reg |= (SDMMC_BMOD_DE | SDMMC_BMOD_FB); + WRITE4(sc, SDMMC_BMOD, reg); + + /* Start */ + WRITE4(sc, SDMMC_PLDMND, 1); + + return (0); +} + +static void +dwmmc_start_cmd(struct dwmmc_softc *sc, struct mmc_command *cmd) +{ + struct mmc_data *data; + uint32_t blksz; + uint32_t cmdr; + + sc->curcmd = cmd; + data = cmd->data; + + /* XXX Upper layers don't always set this */ + cmd->mrq = sc->req; + + /* Begin setting up command register. */ + + cmdr = cmd->opcode; + + dprintf("cmd->opcode 0x%08x\n", cmd->opcode); + + if (cmd->opcode == MMC_STOP_TRANSMISSION || + cmd->opcode == MMC_GO_IDLE_STATE || + cmd->opcode == MMC_GO_INACTIVE_STATE) + cmdr |= SDMMC_CMD_STOP_ABORT; + else if (cmd->opcode != MMC_SEND_STATUS && data) + cmdr |= SDMMC_CMD_WAIT_PRVDATA; + + /* Set up response handling. */ + if (MMC_RSP(cmd->flags) != MMC_RSP_NONE) { + cmdr |= SDMMC_CMD_RESP_EXP; + if (cmd->flags & MMC_RSP_136) + cmdr |= SDMMC_CMD_RESP_LONG; + } + + if (cmd->flags & MMC_RSP_CRC) + cmdr |= SDMMC_CMD_RESP_CRC; + + /* + * XXX: Not all platforms want this. + */ + cmdr |= SDMMC_CMD_USE_HOLD_REG; + + if ((sc->flags & CARD_INIT_DONE) == 0) { + sc->flags |= (CARD_INIT_DONE); + cmdr |= SDMMC_CMD_SEND_INIT; + } + + if (data) { + if ((cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK || + cmd->opcode == MMC_READ_MULTIPLE_BLOCK) && + sc->use_auto_stop) + cmdr |= SDMMC_CMD_SEND_ASTOP; + + cmdr |= SDMMC_CMD_DATA_EXP; + if (data->flags & MMC_DATA_STREAM) + cmdr |= SDMMC_CMD_MODE_STREAM; + if (data->flags & MMC_DATA_WRITE) + cmdr |= SDMMC_CMD_DATA_WRITE; + + WRITE4(sc, SDMMC_TMOUT, 0xffffffff); + WRITE4(sc, SDMMC_BYTCNT, data->len); + blksz = (data->len < MMC_SECTOR_SIZE) ? \ + data->len : MMC_SECTOR_SIZE; + WRITE4(sc, SDMMC_BLKSIZ, blksz); + + dma_prepare(sc, cmd); + wmb(); + } + + dprintf("cmdr 0x%08x\n", cmdr); + + WRITE4(sc, SDMMC_CMDARG, cmd->arg); + wmb(); + WRITE4(sc, SDMMC_CMD, cmdr | SDMMC_CMD_START); +}; + +static void +dwmmc_next_operation(struct dwmmc_softc *sc) +{ + struct mmc_request *req; + + req = sc->req; + if (req == NULL) + return; + + sc->acd_rcvd = 0; + sc->dto_rcvd = 0; + sc->cmd_done = 0; + + /* + * XXX: Wait until card is still busy. + * We do need this to prevent data timeouts, + * mostly caused by multi-block write command + * followed by single-read. + */ + while(READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY)) + continue; + + if (sc->flags & PENDING_CMD) { + sc->flags &= ~PENDING_CMD; + dwmmc_start_cmd(sc, req->cmd); + return; + } else if (sc->flags & PENDING_STOP && !sc->use_auto_stop) { + sc->flags &= ~PENDING_STOP; + dwmmc_start_cmd(sc, req->stop); + return; + } + + sc->req = NULL; + sc->curcmd = NULL; + req->done(req); +} + +static int +dwmmc_request(device_t brdev, device_t reqdev, struct mmc_request *req) +{ + struct dwmmc_softc *sc; + + sc = device_get_softc(brdev); + + dprintf("%s\n", __func__); + + DWMMC_LOCK(sc); + + if (sc->req != NULL) { + DWMMC_UNLOCK(sc); + return (EBUSY); + } + + sc->req = req; + sc->flags |= PENDING_CMD; + if (sc->req->stop) + sc->flags |= PENDING_STOP; + dwmmc_next_operation(sc); + + DWMMC_UNLOCK(sc); + return (0); +} + +static int +dwmmc_get_ro(device_t brdev, device_t reqdev) +{ + + dprintf("%s\n", __func__); + + return (0); +} + +static int +dwmmc_acquire_host(device_t brdev, device_t reqdev) +{ + struct dwmmc_softc *sc; + + sc = device_get_softc(brdev); + + DWMMC_LOCK(sc); + while (sc->bus_busy) + msleep(sc, &sc->sc_mtx, PZERO, "dwmmcah", hz / 5); + sc->bus_busy++; + DWMMC_UNLOCK(sc); + return (0); +} + +static int +dwmmc_release_host(device_t brdev, device_t reqdev) +{ + struct dwmmc_softc *sc; + + sc = device_get_softc(brdev); + + DWMMC_LOCK(sc); + sc->bus_busy--; + wakeup(sc); + DWMMC_UNLOCK(sc); + return (0); +} + +static int +dwmmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) +{ + struct dwmmc_softc *sc; + + sc = device_get_softc(bus); + + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + *(int *)result = sc->host.ios.bus_mode; + break; + case MMCBR_IVAR_BUS_WIDTH: + *(int *)result = sc->host.ios.bus_width; + break; + case MMCBR_IVAR_CHIP_SELECT: + *(int *)result = sc->host.ios.chip_select; + break; + case MMCBR_IVAR_CLOCK: + *(int *)result = sc->host.ios.clock; + break; + case MMCBR_IVAR_F_MIN: + *(int *)result = sc->host.f_min; + break; + case MMCBR_IVAR_F_MAX: + *(int *)result = sc->host.f_max; + break; + case MMCBR_IVAR_HOST_OCR: + *(int *)result = sc->host.host_ocr; + break; + case MMCBR_IVAR_MODE: + *(int *)result = sc->host.mode; + break; + case MMCBR_IVAR_OCR: + *(int *)result = sc->host.ocr; + break; + case MMCBR_IVAR_POWER_MODE: + *(int *)result = sc->host.ios.power_mode; + break; + case MMCBR_IVAR_VDD: + *(int *)result = sc->host.ios.vdd; + break; + case MMCBR_IVAR_CAPS: + sc->host.caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; + *(int *)result = sc->host.caps; + break; + case MMCBR_IVAR_MAX_DATA: + *(int *)result = DESC_COUNT; + } + return (0); +} + +static int +dwmmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) +{ + struct dwmmc_softc *sc; + + sc = device_get_softc(bus); + + switch (which) { + default: + return (EINVAL); + case MMCBR_IVAR_BUS_MODE: + sc->host.ios.bus_mode = value; + break; + case MMCBR_IVAR_BUS_WIDTH: + sc->host.ios.bus_width = value; + break; + case MMCBR_IVAR_CHIP_SELECT: + sc->host.ios.chip_select = value; + break; + case MMCBR_IVAR_CLOCK: + sc->host.ios.clock = value; + break; + case MMCBR_IVAR_MODE: + sc->host.mode = value; + break; + case MMCBR_IVAR_OCR: + sc->host.ocr = value; + break; + case MMCBR_IVAR_POWER_MODE: + sc->host.ios.power_mode = value; + break; + case MMCBR_IVAR_VDD: + sc->host.ios.vdd = value; + break; + /* These are read-only */ + case MMCBR_IVAR_CAPS: + case MMCBR_IVAR_HOST_OCR: + case MMCBR_IVAR_F_MIN: + case MMCBR_IVAR_F_MAX: + case MMCBR_IVAR_MAX_DATA: + return (EINVAL); + } + return (0); +} + +static device_method_t dwmmc_methods[] = { + DEVMETHOD(device_probe, dwmmc_probe), + DEVMETHOD(device_attach, dwmmc_attach), + + /* Bus interface */ + DEVMETHOD(bus_read_ivar, dwmmc_read_ivar), + DEVMETHOD(bus_write_ivar, dwmmc_write_ivar), + + /* mmcbr_if */ + DEVMETHOD(mmcbr_update_ios, dwmmc_update_ios), + DEVMETHOD(mmcbr_request, dwmmc_request), + DEVMETHOD(mmcbr_get_ro, dwmmc_get_ro), + DEVMETHOD(mmcbr_acquire_host, dwmmc_acquire_host), + DEVMETHOD(mmcbr_release_host, dwmmc_release_host), + + DEVMETHOD_END +}; + +static driver_t dwmmc_driver = { + "dwmmc", + dwmmc_methods, + sizeof(struct dwmmc_softc), +}; + +static devclass_t dwmmc_devclass; + +DRIVER_MODULE(dwmmc, simplebus, dwmmc_driver, dwmmc_devclass, 0, 0); + Property changes on: head/sys/dev/mmc/host/dwmmc.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/mmc/host/dwmmc.h =================================================================== --- head/sys/dev/mmc/host/dwmmc.h (nonexistent) +++ head/sys/dev/mmc/host/dwmmc.h (revision 272712) @@ -0,0 +1,150 @@ +/*- + * Copyright (c) 2014 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#define SDMMC_CTRL 0x0 /* Control Register */ +#define SDMMC_CTRL_USE_IDMAC (1 << 25) /* Use Internal DMAC */ +#define SDMMC_CTRL_DMA_ENABLE (1 << 5) /* */ +#define SDMMC_CTRL_INT_ENABLE (1 << 4) /* Enable interrupts */ +#define SDMMC_CTRL_DMA_RESET (1 << 2) /* Reset DMA */ +#define SDMMC_CTRL_FIFO_RESET (1 << 1) /* Reset FIFO */ +#define SDMMC_CTRL_RESET (1 << 0) /* Reset SD/MMC controller */ +#define SDMMC_PWREN 0x4 /* Power Enable Register */ +#define SDMMC_PWREN_PE (1 << 0) /* Power On */ +#define SDMMC_CLKDIV 0x8 /* Clock Divider Register */ +#define SDMMC_CLKSRC 0xC /* SD Clock Source Register */ +#define SDMMC_CLKENA 0x10 /* Clock Enable Register */ +#define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */ +#define SDMMC_CLKENA_CCLK_EN (1 << 0) /* SD/MMC Enable */ +#define SDMMC_TMOUT 0x14 /* Timeout Register */ +#define SDMMC_CTYPE 0x18 /* Card Type Register */ +#define SDMMC_CTYPE_8BIT (1 << 16) +#define SDMMC_CTYPE_4BIT (1 << 0) +#define SDMMC_BLKSIZ 0x1C /* Block Size Register */ +#define SDMMC_BYTCNT 0x20 /* Byte Count Register */ +#define SDMMC_INTMASK 0x24 /* Interrupt Mask Register */ +#define SDMMC_INTMASK_SDIO (1 << 16) /* SDIO Interrupt Enable */ +#define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */ +#define SDMMC_INTMASK_ACD (1 << 14) /* Auto command done */ +#define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */ +#define SDMMC_INTMASK_HLE (1 << 12) /* Hardware locked write err */ +#define SDMMC_INTMASK_FRUN (1 << 11) /* FIFO underrun/overrun err */ +#define SDMMC_INTMASK_HTO (1 << 10) /* Data starvation by host timeout */ +#define SDMMC_INTMASK_DRT (1 << 9) /* Data read timeout */ +#define SDMMC_INTMASK_RTO (1 << 8) /* Response timeout */ +#define SDMMC_INTMASK_DCRC (1 << 7) /* Data CRC error */ +#define SDMMC_INTMASK_RCRC (1 << 6) /* Response CRC error */ +#define SDMMC_INTMASK_RXDR (1 << 5) /* Receive FIFO data request */ +#define SDMMC_INTMASK_TXDR (1 << 4) /* Transmit FIFO data request */ +#define SDMMC_INTMASK_DTO (1 << 3) /* Data transfer over */ +#define SDMMC_INTMASK_CMD_DONE (1 << 2) /* Command done */ +#define SDMMC_INTMASK_RE (1 << 1) /* Response error */ +#define SDMMC_INTMASK_CD (1 << 0) /* Card Detected */ +#define SDMMC_CMDARG 0x28 /* Command Argument Register */ +#define SDMMC_CMD 0x2C /* Command Register */ +#define SDMMC_CMD_START (1 << 31) +#define SDMMC_CMD_USE_HOLD_REG (1 << 29) +#define SDMMC_CMD_UPD_CLK_ONLY (1 << 21) /* Update clk only */ +#define SDMMC_CMD_SEND_INIT (1 << 15) /* Send initialization */ +#define SDMMC_CMD_STOP_ABORT (1 << 14) /* stop current data transfer */ +#define SDMMC_CMD_WAIT_PRVDATA (1 << 13) /* Wait for prev data transfer completion */ +#define SDMMC_CMD_SEND_ASTOP (1 << 12) /* Send stop command at end of data tx/rx */ +#define SDMMC_CMD_MODE_STREAM (1 << 11) /* Stream data transfer */ +#define SDMMC_CMD_DATA_WRITE (1 << 10) /* Write to card */ +#define SDMMC_CMD_DATA_EXP (1 << 9) /* Data transfer expected */ +#define SDMMC_CMD_RESP_CRC (1 << 8) /* Check Response CRC */ +#define SDMMC_CMD_RESP_LONG (1 << 7) /* Long response expected */ +#define SDMMC_CMD_RESP_EXP (1 << 6) /* Response expected */ +#define SDMMC_RESP0 0x30 /* Response Register 0 */ +#define SDMMC_RESP1 0x34 /* Response Register 1 */ +#define SDMMC_RESP2 0x38 /* Response Register 2 */ +#define SDMMC_RESP3 0x3C /* Response Register 3 */ +#define SDMMC_MINTSTS 0x40 /* Masked Interrupt Status Register */ +#define SDMMC_RINTSTS 0x44 /* Raw Interrupt Status Register */ +#define SDMMC_STATUS 0x48 /* Status Register */ +#define SDMMC_STATUS_DATA_BUSY (1 << 9) /* card_data[0] */ +#define SDMMC_FIFOTH 0x4C /* FIFO Threshold Watermark Register */ +#define SDMMC_FIFOTH_MSIZE_S 28 /* Burst size of multiple transaction */ +#define SDMMC_FIFOTH_RXWMARK_S 16 /* FIFO threshold watermark level */ +#define SDMMC_FIFOTH_TXWMARK_S 0 /* FIFO threshold watermark level */ +#define SDMMC_CDETECT 0x50 /* Card Detect Register */ +#define SDMMC_WRTPRT 0x54 /* Write Protect Register */ +#define SDMMC_TCBCNT 0x5C /* Transferred CIU Card Byte Count */ +#define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */ +#define SDMMC_DEBNCE 0x64 /* Debounce Count Register */ +#define SDMMC_USRID 0x68 /* User ID Register */ +#define SDMMC_VERID 0x6C /* Version ID Register */ +#define SDMMC_HCON 0x70 /* Hardware Configuration Register */ +#define SDMMC_UHS_REG 0x74 /* UHS-1 Register */ +#define SDMMC_UHS_REG_DDR (1 << 16) /* DDR mode */ +#define SDMMC_RST_N 0x78 /* Hardware Reset Register */ +#define SDMMC_BMOD 0x80 /* Bus Mode Register */ +#define SDMMC_BMOD_DE (1 << 7) /* IDMAC Enable */ +#define SDMMC_BMOD_FB (1 << 1) /* AHB Master Fixed Burst */ +#define SDMMC_BMOD_SWR (1 << 0) /* Reset DMA */ +#define SDMMC_PLDMND 0x84 /* Poll Demand Register */ +#define SDMMC_DBADDR 0x88 /* Descriptor List Base Address */ +#define SDMMC_IDSTS 0x8C /* Internal DMAC Status Register */ +#define SDMMC_IDINTEN 0x90 /* Internal DMAC Interrupt Enable */ +#define SDMMC_IDINTEN_AI (1 << 9) /* Abnormal Interrupt Summary */ +#define SDMMC_IDINTEN_NI (1 << 8) /* Normal Interrupt Summary */ +#define SDMMC_IDINTEN_CES (1 << 5) /* Card Error Summary */ +#define SDMMC_IDINTEN_DU (1 << 4) /* Descriptor Unavailable */ +#define SDMMC_IDINTEN_FBE (1 << 2) /* Fatal Bus Error */ +#define SDMMC_IDINTEN_RI (1 << 1) /* Receive Interrupt */ +#define SDMMC_IDINTEN_TI (1 << 0) /* Transmit Interrupt */ +#define SDMMC_IDINTEN_MASK (SDMMC_IDINTEN_AI | SDMMC_IDINTEN_NI | SDMMC_IDINTEN_CES | \ + SDMMC_IDINTEN_DU | SDMMC_IDINTEN_FBE | SDMMC_IDINTEN_RI | \ + SDMMC_IDINTEN_TI) +#define SDMMC_DSCADDR 0x94 /* Current Host Descriptor Address */ +#define SDMMC_BUFADDR 0x98 /* Current Buffer Descriptor Address */ +#define SDMMC_CARDTHRCTL 0x100 /* Card Threshold Control Register */ +#define SDMMC_BACK_END_POWER_R 0x104 /* Back End Power Register */ +#define SDMMC_DATA 0x200 /* Data FIFO Access */ + +/* eMMC */ +#define EMMCP_MPSBEGIN0 0x1200 /* */ +#define EMMCP_SEND0 0x1204 /* */ +#define EMMCP_CTRL0 0x120C /* */ +#define MPSCTRL_SECURE_READ_BIT (1 << 7) +#define MPSCTRL_SECURE_WRITE_BIT (1 << 6) +#define MPSCTRL_NON_SECURE_READ_BIT (1 << 5) +#define MPSCTRL_NON_SECURE_WRITE_BIT (1 << 4) +#define MPSCTRL_USE_FUSE_KEY (1 << 3) +#define MPSCTRL_ECB_MODE (1 << 2) +#define MPSCTRL_ENCRYPTION (1 << 1) +#define MPSCTRL_VALID (1 << 0) + +/* Platform-specific defines */ +#define SDMMC_CLKSEL 0x9C +#define SDMMC_CLKSEL_SAMPLE_SHIFT 0 +#define SDMMC_CLKSEL_DRIVE_SHIFT 16 +#define SDMMC_CLKSEL_DIVIDER_SHIFT 24 Property changes on: head/sys/dev/mmc/host/dwmmc.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/mmc/mmc.c =================================================================== --- head/sys/dev/mmc/mmc.c (revision 272711) +++ head/sys/dev/mmc/mmc.c (revision 272712) @@ -1,1776 +1,1777 @@ /*- * Copyright (c) 2006 Bernd Walter. All rights reserved. * Copyright (c) 2006 M. Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Portions of this software may have been developed with reference to * the SD Simplified Specification. The following disclaimer may apply: * * The following conditions apply to the release of the simplified * specification ("Simplified Specification") by the SD Card Association and * the SD Group. The Simplified Specification is a subset of the complete SD * Specification which is owned by the SD Card Association and the SD * Group. This Simplified Specification is provided on a non-confidential * basis subject to the disclaimers below. Any implementation of the * Simplified Specification may require a license from the SD Card * Association, SD Group, SD-3C LLC or other third parties. * * Disclaimers: * * The information contained in the Simplified Specification is presented only * as a standard specification for SD Cards and SD Host/Ancillary products and * is provided "AS-IS" without any representations or warranties of any * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD * Card Association for any damages, any infringements of patents or other * right of the SD Group, SD-3C LLC, the SD Card Association or any third * parties, which may result from its use. No license is granted by * implication, estoppel or otherwise under any patent or other rights of the * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing * herein shall be construed as an obligation by the SD Group, the SD-3C LLC * or the SD Card Association to disclose or distribute any technical * information, know-how or other confidential information to any third party. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mmcbr_if.h" #include "mmcbus_if.h" struct mmc_softc { device_t dev; struct mtx sc_mtx; struct intr_config_hook config_intrhook; device_t owner; uint32_t last_rca; }; /* * Per-card data */ struct mmc_ivars { uint32_t raw_cid[4]; /* Raw bits of the CID */ uint32_t raw_csd[4]; /* Raw bits of the CSD */ uint32_t raw_scr[2]; /* Raw bits of the SCR */ uint8_t raw_ext_csd[512]; /* Raw bits of the EXT_CSD */ uint32_t raw_sd_status[16]; /* Raw bits of the SD_STATUS */ uint16_t rca; enum mmc_card_mode mode; struct mmc_cid cid; /* cid decoded */ struct mmc_csd csd; /* csd decoded */ struct mmc_scr scr; /* scr decoded */ struct mmc_sd_status sd_status; /* SD_STATUS decoded */ u_char read_only; /* True when the device is read-only */ u_char bus_width; /* Bus width to use */ u_char timing; /* Bus timing support */ u_char high_cap; /* High Capacity card (block addressed) */ uint32_t sec_count; /* Card capacity in 512byte blocks */ uint32_t tran_speed; /* Max speed in normal mode */ uint32_t hs_tran_speed; /* Max speed in high speed mode */ uint32_t erase_sector; /* Card native erase sector size */ char card_id_string[64];/* Formatted CID info (serial, MFG, etc) */ char card_sn_string[16];/* Formatted serial # for disk->d_ident */ }; #define CMD_RETRIES 3 #define CARD_ID_FREQUENCY 400000 /* Spec requires 400kHz max during ID phase. */ static SYSCTL_NODE(_hw, OID_AUTO, mmc, CTLFLAG_RD, NULL, "mmc driver"); static int mmc_debug; SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RW, &mmc_debug, 0, "Debug level"); /* bus entry points */ static int mmc_acquire_bus(device_t busdev, device_t dev); static int mmc_attach(device_t dev); static int mmc_child_location_str(device_t dev, device_t child, char *buf, size_t buflen); static int mmc_detach(device_t dev); static int mmc_probe(device_t dev); static int mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); static int mmc_release_bus(device_t busdev, device_t dev); static int mmc_resume(device_t dev); static int mmc_suspend(device_t dev); static int mmc_wait_for_request(device_t brdev, device_t reqdev, struct mmc_request *req); static int mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value); #define MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define MMC_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ "mmc", MTX_DEF) #define MMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); #define MMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); #define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); static int mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid); static void mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr); static void mmc_app_decode_sd_status(uint32_t *raw_sd_status, struct mmc_sd_status *sd_status); static int mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, uint32_t *rawsdstatus); static int mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca, uint32_t *rawscr); static int mmc_calculate_clock(struct mmc_softc *sc); static void mmc_decode_cid_mmc(uint32_t *raw_cid, struct mmc_cid *cid); static void mmc_decode_cid_sd(uint32_t *raw_cid, struct mmc_cid *cid); static void mmc_decode_csd_mmc(uint32_t *raw_csd, struct mmc_csd *csd); static void mmc_decode_csd_sd(uint32_t *raw_csd, struct mmc_csd *csd); static void mmc_delayed_attach(void *xsc); static int mmc_delete_cards(struct mmc_softc *sc); static void mmc_discover_cards(struct mmc_softc *sc); static void mmc_format_card_id_string(struct mmc_ivars *ivar); static void mmc_go_discovery(struct mmc_softc *sc); static uint32_t mmc_get_bits(uint32_t *bits, int bit_len, int start, int size); static int mmc_highest_voltage(uint32_t ocr); static void mmc_idle_cards(struct mmc_softc *sc); static void mmc_ms_delay(int ms); static void mmc_log_card(device_t dev, struct mmc_ivars *ivar, int newcard); static void mmc_power_down(struct mmc_softc *sc); static void mmc_power_up(struct mmc_softc *sc); static void mmc_rescan_cards(struct mmc_softc *sc); static void mmc_scan(struct mmc_softc *sc); static int mmc_sd_switch(struct mmc_softc *sc, uint8_t mode, uint8_t grp, uint8_t value, uint8_t *res); static int mmc_select_card(struct mmc_softc *sc, uint16_t rca); static uint32_t mmc_select_vdd(struct mmc_softc *sc, uint32_t ocr); static int mmc_send_app_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr); static int mmc_send_csd(struct mmc_softc *sc, uint16_t rca, uint32_t *rawcsd); static int mmc_send_ext_csd(struct mmc_softc *sc, uint8_t *rawextcsd); static int mmc_send_if_cond(struct mmc_softc *sc, uint8_t vhs); static int mmc_send_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr); static int mmc_send_relative_addr(struct mmc_softc *sc, uint32_t *resp); static int mmc_send_status(struct mmc_softc *sc, uint16_t rca, uint32_t *status); static int mmc_set_blocklen(struct mmc_softc *sc, uint32_t len); static int mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width); static int mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp); static int mmc_set_timing(struct mmc_softc *sc, int timing); static int mmc_switch(struct mmc_softc *sc, uint8_t set, uint8_t index, uint8_t value); static int mmc_test_bus_width(struct mmc_softc *sc); static int mmc_wait_for_app_cmd(struct mmc_softc *sc, uint32_t rca, struct mmc_command *cmd, int retries); static int mmc_wait_for_cmd(struct mmc_softc *sc, struct mmc_command *cmd, int retries); static int mmc_wait_for_command(struct mmc_softc *sc, uint32_t opcode, uint32_t arg, uint32_t flags, uint32_t *resp, int retries); static int mmc_wait_for_req(struct mmc_softc *sc, struct mmc_request *req); static void mmc_wakeup(struct mmc_request *req); static void mmc_ms_delay(int ms) { DELAY(1000 * ms); /* XXX BAD */ } static int mmc_probe(device_t dev) { device_set_desc(dev, "MMC/SD bus"); return (0); } static int mmc_attach(device_t dev) { struct mmc_softc *sc; sc = device_get_softc(dev); sc->dev = dev; MMC_LOCK_INIT(sc); /* We'll probe and attach our children later, but before / mount */ sc->config_intrhook.ich_func = mmc_delayed_attach; sc->config_intrhook.ich_arg = sc; if (config_intrhook_establish(&sc->config_intrhook) != 0) device_printf(dev, "config_intrhook_establish failed\n"); return (0); } static int mmc_detach(device_t dev) { struct mmc_softc *sc = device_get_softc(dev); int err; if ((err = mmc_delete_cards(sc)) != 0) return (err); mmc_power_down(sc); MMC_LOCK_DESTROY(sc); return (0); } static int mmc_suspend(device_t dev) { struct mmc_softc *sc = device_get_softc(dev); int err; err = bus_generic_suspend(dev); if (err) return (err); mmc_power_down(sc); return (0); } static int mmc_resume(device_t dev) { struct mmc_softc *sc = device_get_softc(dev); mmc_scan(sc); return (bus_generic_resume(dev)); } static int mmc_acquire_bus(device_t busdev, device_t dev) { struct mmc_softc *sc; struct mmc_ivars *ivar; int err; int rca; err = MMCBR_ACQUIRE_HOST(device_get_parent(busdev), busdev); if (err) return (err); sc = device_get_softc(busdev); MMC_LOCK(sc); if (sc->owner) panic("mmc: host bridge didn't serialize us."); sc->owner = dev; MMC_UNLOCK(sc); if (busdev != dev) { /* * Keep track of the last rca that we've selected. If * we're asked to do it again, don't. We never * unselect unless the bus code itself wants the mmc * bus, and constantly reselecting causes problems. */ rca = mmc_get_rca(dev); if (sc->last_rca != rca) { mmc_select_card(sc, rca); sc->last_rca = rca; /* Prepare bus width for the new card. */ ivar = device_get_ivars(dev); if (bootverbose || mmc_debug) { device_printf(busdev, "setting bus width to %d bits\n", (ivar->bus_width == bus_width_4) ? 4 : (ivar->bus_width == bus_width_8) ? 8 : 1); } mmc_set_card_bus_width(sc, rca, ivar->bus_width); mmcbr_set_bus_width(busdev, ivar->bus_width); mmcbr_update_ios(busdev); } } else { /* * If there's a card selected, stand down. */ if (sc->last_rca != 0) { mmc_select_card(sc, 0); sc->last_rca = 0; } } return (0); } static int mmc_release_bus(device_t busdev, device_t dev) { struct mmc_softc *sc; int err; sc = device_get_softc(busdev); MMC_LOCK(sc); if (!sc->owner) panic("mmc: releasing unowned bus."); if (sc->owner != dev) panic("mmc: you don't own the bus. game over."); MMC_UNLOCK(sc); err = MMCBR_RELEASE_HOST(device_get_parent(busdev), busdev); if (err) return (err); MMC_LOCK(sc); sc->owner = NULL; MMC_UNLOCK(sc); return (0); } static uint32_t mmc_select_vdd(struct mmc_softc *sc, uint32_t ocr) { return (ocr & MMC_OCR_VOLTAGE); } static int mmc_highest_voltage(uint32_t ocr) { int i; for (i = MMC_OCR_MAX_VOLTAGE_SHIFT; i >= MMC_OCR_MIN_VOLTAGE_SHIFT; i--) if (ocr & (1 << i)) return (i); return (-1); } static void mmc_wakeup(struct mmc_request *req) { struct mmc_softc *sc; sc = (struct mmc_softc *)req->done_data; MMC_LOCK(sc); req->flags |= MMC_REQ_DONE; MMC_UNLOCK(sc); wakeup(req); } static int mmc_wait_for_req(struct mmc_softc *sc, struct mmc_request *req) { req->done = mmc_wakeup; req->done_data = sc; if (mmc_debug > 1) { device_printf(sc->dev, "REQUEST: CMD%d arg %#x flags %#x", req->cmd->opcode, req->cmd->arg, req->cmd->flags); if (req->cmd->data) { printf(" data %d\n", (int)req->cmd->data->len); } else printf("\n"); } MMCBR_REQUEST(device_get_parent(sc->dev), sc->dev, req); MMC_LOCK(sc); while ((req->flags & MMC_REQ_DONE) == 0) msleep(req, &sc->sc_mtx, 0, "mmcreq", 0); MMC_UNLOCK(sc); if (mmc_debug > 2 || (mmc_debug > 0 && req->cmd->error != MMC_ERR_NONE)) device_printf(sc->dev, "CMD%d RESULT: %d\n", req->cmd->opcode, req->cmd->error); return (0); } static int mmc_wait_for_request(device_t brdev, device_t reqdev, struct mmc_request *req) { struct mmc_softc *sc = device_get_softc(brdev); return (mmc_wait_for_req(sc, req)); } static int mmc_wait_for_cmd(struct mmc_softc *sc, struct mmc_command *cmd, int retries) { struct mmc_request mreq; int err; do { memset(&mreq, 0, sizeof(mreq)); memset(cmd->resp, 0, sizeof(cmd->resp)); cmd->retries = 0; /* Retries done here, not in hardware. */ cmd->mrq = &mreq; mreq.cmd = cmd; if (mmc_wait_for_req(sc, &mreq) != 0) err = MMC_ERR_FAILED; else err = cmd->error; } while (err != MMC_ERR_NONE && retries-- > 0); return (err); } static int mmc_wait_for_app_cmd(struct mmc_softc *sc, uint32_t rca, struct mmc_command *cmd, int retries) { struct mmc_command appcmd; int err; do { memset(&appcmd, 0, sizeof(appcmd)); appcmd.opcode = MMC_APP_CMD; appcmd.arg = rca << 16; appcmd.flags = MMC_RSP_R1 | MMC_CMD_AC; appcmd.data = NULL; if (mmc_wait_for_cmd(sc, &appcmd, 0) != 0) err = MMC_ERR_FAILED; else err = appcmd.error; if (err == MMC_ERR_NONE) { if (!(appcmd.resp[0] & R1_APP_CMD)) err = MMC_ERR_FAILED; else if (mmc_wait_for_cmd(sc, cmd, 0) != 0) err = MMC_ERR_FAILED; else err = cmd->error; } } while (err != MMC_ERR_NONE && retries-- > 0); return (err); } static int mmc_wait_for_command(struct mmc_softc *sc, uint32_t opcode, uint32_t arg, uint32_t flags, uint32_t *resp, int retries) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = opcode; cmd.arg = arg; cmd.flags = flags; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, retries); if (err) return (err); if (resp) { if (flags & MMC_RSP_136) memcpy(resp, cmd.resp, 4 * sizeof(uint32_t)); else *resp = cmd.resp[0]; } return (0); } static void mmc_idle_cards(struct mmc_softc *sc) { device_t dev; struct mmc_command cmd; dev = sc->dev; mmcbr_set_chip_select(dev, cs_high); mmcbr_update_ios(dev); mmc_ms_delay(1); memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_GO_IDLE_STATE; cmd.arg = 0; cmd.flags = MMC_RSP_NONE | MMC_CMD_BC; cmd.data = NULL; mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); mmc_ms_delay(1); mmcbr_set_chip_select(dev, cs_dontcare); mmcbr_update_ios(dev); mmc_ms_delay(1); } static int mmc_send_app_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr) { struct mmc_command cmd; int err = MMC_ERR_NONE, i; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = ACMD_SD_SEND_OP_COND; cmd.arg = ocr; cmd.flags = MMC_RSP_R3 | MMC_CMD_BCR; cmd.data = NULL; for (i = 0; i < 1000; i++) { err = mmc_wait_for_app_cmd(sc, 0, &cmd, CMD_RETRIES); if (err != MMC_ERR_NONE) break; if ((cmd.resp[0] & MMC_OCR_CARD_BUSY) || (ocr & MMC_OCR_VOLTAGE) == 0) break; err = MMC_ERR_TIMEOUT; mmc_ms_delay(10); } if (rocr && err == MMC_ERR_NONE) *rocr = cmd.resp[0]; return (err); } static int mmc_send_op_cond(struct mmc_softc *sc, uint32_t ocr, uint32_t *rocr) { struct mmc_command cmd; int err = MMC_ERR_NONE, i; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SEND_OP_COND; cmd.arg = ocr; cmd.flags = MMC_RSP_R3 | MMC_CMD_BCR; cmd.data = NULL; for (i = 0; i < 1000; i++) { err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); if (err != MMC_ERR_NONE) break; if ((cmd.resp[0] & MMC_OCR_CARD_BUSY) || (ocr & MMC_OCR_VOLTAGE) == 0) break; err = MMC_ERR_TIMEOUT; mmc_ms_delay(10); } if (rocr && err == MMC_ERR_NONE) *rocr = cmd.resp[0]; return (err); } static int mmc_send_if_cond(struct mmc_softc *sc, uint8_t vhs) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = SD_SEND_IF_COND; cmd.arg = (vhs << 8) + 0xAA; cmd.flags = MMC_RSP_R7 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static void mmc_power_up(struct mmc_softc *sc) { device_t dev; dev = sc->dev; mmcbr_set_vdd(dev, mmc_highest_voltage(mmcbr_get_host_ocr(dev))); mmcbr_set_bus_mode(dev, opendrain); mmcbr_set_chip_select(dev, cs_dontcare); mmcbr_set_bus_width(dev, bus_width_1); mmcbr_set_power_mode(dev, power_up); mmcbr_set_clock(dev, 0); mmcbr_update_ios(dev); mmc_ms_delay(1); mmcbr_set_clock(dev, CARD_ID_FREQUENCY); mmcbr_set_timing(dev, bus_timing_normal); mmcbr_set_power_mode(dev, power_on); mmcbr_update_ios(dev); mmc_ms_delay(2); } static void mmc_power_down(struct mmc_softc *sc) { device_t dev = sc->dev; mmcbr_set_bus_mode(dev, opendrain); mmcbr_set_chip_select(dev, cs_dontcare); mmcbr_set_bus_width(dev, bus_width_1); mmcbr_set_power_mode(dev, power_off); mmcbr_set_clock(dev, 0); mmcbr_set_timing(dev, bus_timing_normal); mmcbr_update_ios(dev); } static int mmc_select_card(struct mmc_softc *sc, uint16_t rca) { int flags; flags = (rca ? MMC_RSP_R1B : MMC_RSP_NONE) | MMC_CMD_AC; return (mmc_wait_for_command(sc, MMC_SELECT_CARD, (uint32_t)rca << 16, flags, NULL, CMD_RETRIES)); } static int mmc_switch(struct mmc_softc *sc, uint8_t set, uint8_t index, uint8_t value) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SWITCH_FUNC; cmd.arg = (MMC_SWITCH_FUNC_WR << 24) | (index << 16) | (value << 8) | set; cmd.flags = MMC_RSP_R1B | MMC_CMD_AC; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static int mmc_sd_switch(struct mmc_softc *sc, uint8_t mode, uint8_t grp, uint8_t value, uint8_t *res) { int err; struct mmc_command cmd; struct mmc_data data; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); memset(res, 0, 64); cmd.opcode = SD_SWITCH_FUNC; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.arg = mode << 31; /* 0 - check, 1 - set */ cmd.arg |= 0x00FFFFFF; cmd.arg &= ~(0xF << (grp * 4)); cmd.arg |= value << (grp * 4); cmd.data = &data; data.data = res; data.len = 64; data.flags = MMC_DATA_READ; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static int mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width) { struct mmc_command cmd; int err; uint8_t value; if (mmcbr_get_mode(sc->dev) == mode_sd) { memset(&cmd, 0, sizeof(cmd)); cmd.opcode = ACMD_SET_CLR_CARD_DETECT; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; cmd.arg = SD_CLR_CARD_DETECT; err = mmc_wait_for_app_cmd(sc, rca, &cmd, CMD_RETRIES); if (err != 0) return (err); memset(&cmd, 0, sizeof(cmd)); cmd.opcode = ACMD_SET_BUS_WIDTH; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; switch (width) { case bus_width_1: cmd.arg = SD_BUS_WIDTH_1; break; case bus_width_4: cmd.arg = SD_BUS_WIDTH_4; break; default: return (MMC_ERR_INVALID); } err = mmc_wait_for_app_cmd(sc, rca, &cmd, CMD_RETRIES); } else { switch (width) { case bus_width_1: value = EXT_CSD_BUS_WIDTH_1; break; case bus_width_4: value = EXT_CSD_BUS_WIDTH_4; break; case bus_width_8: value = EXT_CSD_BUS_WIDTH_8; break; default: return (MMC_ERR_INVALID); } err = mmc_switch(sc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, value); } return (err); } static int mmc_set_timing(struct mmc_softc *sc, int timing) { int err; uint8_t value; u_char switch_res[64]; switch (timing) { case bus_timing_normal: value = 0; break; case bus_timing_hs: value = 1; break; default: return (MMC_ERR_INVALID); } if (mmcbr_get_mode(sc->dev) == mode_sd) err = mmc_sd_switch(sc, SD_SWITCH_MODE_SET, SD_SWITCH_GROUP1, value, switch_res); else err = mmc_switch(sc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, value); return (err); } static int mmc_test_bus_width(struct mmc_softc *sc) { struct mmc_command cmd; struct mmc_data data; int err; uint8_t buf[8]; uint8_t p8[8] = { 0x55, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; uint8_t p8ok[8] = { 0xAA, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; uint8_t p4[4] = { 0x5A, 0x00, 0x00, 0x00, }; uint8_t p4ok[4] = { 0xA5, 0x00, 0x00, 0x00, }; if (mmcbr_get_caps(sc->dev) & MMC_CAP_8_BIT_DATA) { mmcbr_set_bus_width(sc->dev, bus_width_8); mmcbr_update_ios(sc->dev); memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); cmd.opcode = MMC_BUSTEST_W; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.data = &data; data.data = p8; data.len = 8; data.flags = MMC_DATA_WRITE; mmc_wait_for_cmd(sc, &cmd, 0); memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); cmd.opcode = MMC_BUSTEST_R; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.data = &data; data.data = buf; data.len = 8; data.flags = MMC_DATA_READ; err = mmc_wait_for_cmd(sc, &cmd, 0); mmcbr_set_bus_width(sc->dev, bus_width_1); mmcbr_update_ios(sc->dev); if (err == MMC_ERR_NONE && memcmp(buf, p8ok, 8) == 0) return (bus_width_8); } if (mmcbr_get_caps(sc->dev) & MMC_CAP_4_BIT_DATA) { mmcbr_set_bus_width(sc->dev, bus_width_4); mmcbr_update_ios(sc->dev); memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); cmd.opcode = MMC_BUSTEST_W; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.data = &data; data.data = p4; data.len = 4; data.flags = MMC_DATA_WRITE; mmc_wait_for_cmd(sc, &cmd, 0); memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); cmd.opcode = MMC_BUSTEST_R; cmd.arg = 0; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.data = &data; data.data = buf; data.len = 4; data.flags = MMC_DATA_READ; err = mmc_wait_for_cmd(sc, &cmd, 0); mmcbr_set_bus_width(sc->dev, bus_width_1); mmcbr_update_ios(sc->dev); if (err == MMC_ERR_NONE && memcmp(buf, p4ok, 4) == 0) return (bus_width_4); } return (bus_width_1); } static uint32_t mmc_get_bits(uint32_t *bits, int bit_len, int start, int size) { const int i = (bit_len / 32) - (start / 32) - 1; const int shift = start & 31; uint32_t retval = bits[i] >> shift; if (size + shift > 32) retval |= bits[i - 1] << (32 - shift); return (retval & ((1llu << size) - 1)); } static void mmc_decode_cid_sd(uint32_t *raw_cid, struct mmc_cid *cid) { int i; /* There's no version info, so we take it on faith */ memset(cid, 0, sizeof(*cid)); cid->mid = mmc_get_bits(raw_cid, 128, 120, 8); cid->oid = mmc_get_bits(raw_cid, 128, 104, 16); for (i = 0; i < 5; i++) cid->pnm[i] = mmc_get_bits(raw_cid, 128, 96 - i * 8, 8); cid->pnm[5] = 0; cid->prv = mmc_get_bits(raw_cid, 128, 56, 8); cid->psn = mmc_get_bits(raw_cid, 128, 24, 32); cid->mdt_year = mmc_get_bits(raw_cid, 128, 12, 8) + 2000; cid->mdt_month = mmc_get_bits(raw_cid, 128, 8, 4); } static void mmc_decode_cid_mmc(uint32_t *raw_cid, struct mmc_cid *cid) { int i; /* There's no version info, so we take it on faith */ memset(cid, 0, sizeof(*cid)); cid->mid = mmc_get_bits(raw_cid, 128, 120, 8); cid->oid = mmc_get_bits(raw_cid, 128, 104, 8); for (i = 0; i < 6; i++) cid->pnm[i] = mmc_get_bits(raw_cid, 128, 96 - i * 8, 8); cid->pnm[6] = 0; cid->prv = mmc_get_bits(raw_cid, 128, 48, 8); cid->psn = mmc_get_bits(raw_cid, 128, 16, 32); cid->mdt_month = mmc_get_bits(raw_cid, 128, 12, 4); cid->mdt_year = mmc_get_bits(raw_cid, 128, 8, 4) + 1997; } static void mmc_format_card_id_string(struct mmc_ivars *ivar) { char oidstr[8]; uint8_t c1; uint8_t c2; /* * Format a card ID string for use by the mmcsd driver, it's what * appears between the <> in the following: * mmcsd0: 968MB at mmc0 * 22.5MHz/4bit/128-block * * Also format just the card serial number, which the mmcsd driver will * use as the disk->d_ident string. * * The card_id_string in mmc_ivars is currently allocated as 64 bytes, * and our max formatted length is currently 55 bytes if every field * contains the largest value. * * Sometimes the oid is two printable ascii chars; when it's not, * format it as 0xnnnn instead. */ c1 = (ivar->cid.oid >> 8) & 0x0ff; c2 = ivar->cid.oid & 0x0ff; if (c1 > 0x1f && c1 < 0x7f && c2 > 0x1f && c2 < 0x7f) snprintf(oidstr, sizeof(oidstr), "%c%c", c1, c2); else snprintf(oidstr, sizeof(oidstr), "0x%04x", ivar->cid.oid); snprintf(ivar->card_sn_string, sizeof(ivar->card_sn_string), "%08X", ivar->cid.psn); snprintf(ivar->card_id_string, sizeof(ivar->card_id_string), "%s%s %s %d.%d SN %08X MFG %02d/%04d by %d %s", ivar->mode == mode_sd ? "SD" : "MMC", ivar->high_cap ? "HC" : "", ivar->cid.pnm, ivar->cid.prv >> 4, ivar->cid.prv & 0x0f, ivar->cid.psn, ivar->cid.mdt_month, ivar->cid.mdt_year, ivar->cid.mid, oidstr); } static const int exp[8] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 }; static const int mant[16] = { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 }; static const int cur_min[8] = { 500, 1000, 5000, 10000, 25000, 35000, 60000, 100000 }; static const int cur_max[8] = { 1000, 5000, 10000, 25000, 35000, 45000, 800000, 200000 }; static void mmc_decode_csd_sd(uint32_t *raw_csd, struct mmc_csd *csd) { int v; int m; int e; memset(csd, 0, sizeof(*csd)); csd->csd_structure = v = mmc_get_bits(raw_csd, 128, 126, 2); if (v == 0) { m = mmc_get_bits(raw_csd, 128, 115, 4); e = mmc_get_bits(raw_csd, 128, 112, 3); csd->tacc = (exp[e] * mant[m] + 9) / 10; csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; m = mmc_get_bits(raw_csd, 128, 99, 4); e = mmc_get_bits(raw_csd, 128, 96, 3); csd->tran_speed = exp[e] * 10000 * mant[m]; csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); csd->vdd_r_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 59, 3)]; csd->vdd_r_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 56, 3)]; csd->vdd_w_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 53, 3)]; csd->vdd_w_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 50, 3)]; m = mmc_get_bits(raw_csd, 128, 62, 12); e = mmc_get_bits(raw_csd, 128, 47, 3); csd->capacity = ((1 + m) << (e + 2)) * csd->read_bl_len; csd->erase_blk_en = mmc_get_bits(raw_csd, 128, 46, 1); csd->erase_sector = mmc_get_bits(raw_csd, 128, 39, 7) + 1; csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 7); csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); } else if (v == 1) { m = mmc_get_bits(raw_csd, 128, 115, 4); e = mmc_get_bits(raw_csd, 128, 112, 3); csd->tacc = (exp[e] * mant[m] + 9) / 10; csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; m = mmc_get_bits(raw_csd, 128, 99, 4); e = mmc_get_bits(raw_csd, 128, 96, 3); csd->tran_speed = exp[e] * 10000 * mant[m]; csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); csd->capacity = ((uint64_t)mmc_get_bits(raw_csd, 128, 48, 22) + 1) * 512 * 1024; csd->erase_blk_en = mmc_get_bits(raw_csd, 128, 46, 1); csd->erase_sector = mmc_get_bits(raw_csd, 128, 39, 7) + 1; csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 7); csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); } else panic("unknown SD CSD version"); } static void mmc_decode_csd_mmc(uint32_t *raw_csd, struct mmc_csd *csd) { int m; int e; memset(csd, 0, sizeof(*csd)); csd->csd_structure = mmc_get_bits(raw_csd, 128, 126, 2); csd->spec_vers = mmc_get_bits(raw_csd, 128, 122, 4); m = mmc_get_bits(raw_csd, 128, 115, 4); e = mmc_get_bits(raw_csd, 128, 112, 3); csd->tacc = exp[e] * mant[m] + 9 / 10; csd->nsac = mmc_get_bits(raw_csd, 128, 104, 8) * 100; m = mmc_get_bits(raw_csd, 128, 99, 4); e = mmc_get_bits(raw_csd, 128, 96, 3); csd->tran_speed = exp[e] * 10000 * mant[m]; csd->ccc = mmc_get_bits(raw_csd, 128, 84, 12); csd->read_bl_len = 1 << mmc_get_bits(raw_csd, 128, 80, 4); csd->read_bl_partial = mmc_get_bits(raw_csd, 128, 79, 1); csd->write_blk_misalign = mmc_get_bits(raw_csd, 128, 78, 1); csd->read_blk_misalign = mmc_get_bits(raw_csd, 128, 77, 1); csd->dsr_imp = mmc_get_bits(raw_csd, 128, 76, 1); csd->vdd_r_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 59, 3)]; csd->vdd_r_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 56, 3)]; csd->vdd_w_curr_min = cur_min[mmc_get_bits(raw_csd, 128, 53, 3)]; csd->vdd_w_curr_max = cur_max[mmc_get_bits(raw_csd, 128, 50, 3)]; m = mmc_get_bits(raw_csd, 128, 62, 12); e = mmc_get_bits(raw_csd, 128, 47, 3); csd->capacity = ((1 + m) << (e + 2)) * csd->read_bl_len; csd->erase_blk_en = 0; csd->erase_sector = (mmc_get_bits(raw_csd, 128, 42, 5) + 1) * (mmc_get_bits(raw_csd, 128, 37, 5) + 1); csd->wp_grp_size = mmc_get_bits(raw_csd, 128, 32, 5); csd->wp_grp_enable = mmc_get_bits(raw_csd, 128, 31, 1); csd->r2w_factor = 1 << mmc_get_bits(raw_csd, 128, 26, 3); csd->write_bl_len = 1 << mmc_get_bits(raw_csd, 128, 22, 4); csd->write_bl_partial = mmc_get_bits(raw_csd, 128, 21, 1); } static void mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr) { unsigned int scr_struct; memset(scr, 0, sizeof(*scr)); scr_struct = mmc_get_bits(raw_scr, 64, 60, 4); if (scr_struct != 0) { printf("Unrecognised SCR structure version %d\n", scr_struct); return; } scr->sda_vsn = mmc_get_bits(raw_scr, 64, 56, 4); scr->bus_widths = mmc_get_bits(raw_scr, 64, 48, 4); } static void mmc_app_decode_sd_status(uint32_t *raw_sd_status, struct mmc_sd_status *sd_status) { memset(sd_status, 0, sizeof(*sd_status)); sd_status->bus_width = mmc_get_bits(raw_sd_status, 512, 510, 2); sd_status->secured_mode = mmc_get_bits(raw_sd_status, 512, 509, 1); sd_status->card_type = mmc_get_bits(raw_sd_status, 512, 480, 16); sd_status->prot_area = mmc_get_bits(raw_sd_status, 512, 448, 12); sd_status->speed_class = mmc_get_bits(raw_sd_status, 512, 440, 8); sd_status->perf_move = mmc_get_bits(raw_sd_status, 512, 432, 8); sd_status->au_size = mmc_get_bits(raw_sd_status, 512, 428, 4); sd_status->erase_size = mmc_get_bits(raw_sd_status, 512, 408, 16); sd_status->erase_timeout = mmc_get_bits(raw_sd_status, 512, 402, 6); sd_status->erase_offset = mmc_get_bits(raw_sd_status, 512, 400, 2); } static int mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_ALL_SEND_CID; cmd.arg = 0; cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); memcpy(rawcid, cmd.resp, 4 * sizeof(uint32_t)); return (err); } static int mmc_send_csd(struct mmc_softc *sc, uint16_t rca, uint32_t *rawcsd) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SEND_CSD; cmd.arg = rca << 16; cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); memcpy(rawcsd, cmd.resp, 4 * sizeof(uint32_t)); return (err); } static int mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca, uint32_t *rawscr) { int err; struct mmc_command cmd; struct mmc_data data; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); memset(rawscr, 0, 8); cmd.opcode = ACMD_SEND_SCR; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.arg = 0; cmd.data = &data; data.data = rawscr; data.len = 8; data.flags = MMC_DATA_READ; err = mmc_wait_for_app_cmd(sc, rca, &cmd, CMD_RETRIES); rawscr[0] = be32toh(rawscr[0]); rawscr[1] = be32toh(rawscr[1]); return (err); } static int mmc_send_ext_csd(struct mmc_softc *sc, uint8_t *rawextcsd) { int err; struct mmc_command cmd; struct mmc_data data; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); memset(rawextcsd, 0, 512); cmd.opcode = MMC_SEND_EXT_CSD; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.arg = 0; cmd.data = &data; data.data = rawextcsd; data.len = 512; data.flags = MMC_DATA_READ; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static int mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, uint32_t *rawsdstatus) { int err, i; struct mmc_command cmd; struct mmc_data data; memset(&cmd, 0, sizeof(cmd)); memset(&data, 0, sizeof(data)); memset(rawsdstatus, 0, 64); cmd.opcode = ACMD_SD_STATUS; cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; cmd.arg = 0; cmd.data = &data; data.data = rawsdstatus; data.len = 64; data.flags = MMC_DATA_READ; err = mmc_wait_for_app_cmd(sc, rca, &cmd, CMD_RETRIES); for (i = 0; i < 16; i++) rawsdstatus[i] = be32toh(rawsdstatus[i]); return (err); } static int mmc_set_relative_addr(struct mmc_softc *sc, uint16_t resp) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SET_RELATIVE_ADDR; cmd.arg = resp << 16; cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static int mmc_send_relative_addr(struct mmc_softc *sc, uint32_t *resp) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = SD_SEND_RELATIVE_ADDR; cmd.arg = 0; cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); *resp = cmd.resp[0]; return (err); } static int mmc_send_status(struct mmc_softc *sc, uint16_t rca, uint32_t *status) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SEND_STATUS; cmd.arg = rca << 16; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); *status = cmd.resp[0]; return (err); } static int mmc_set_blocklen(struct mmc_softc *sc, uint32_t len) { struct mmc_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); cmd.opcode = MMC_SET_BLOCKLEN; cmd.arg = len; cmd.flags = MMC_RSP_R1 | MMC_CMD_AC; cmd.data = NULL; err = mmc_wait_for_cmd(sc, &cmd, CMD_RETRIES); return (err); } static void mmc_log_card(device_t dev, struct mmc_ivars *ivar, int newcard) { device_printf(dev, "Card at relative address 0x%04x%s:\n", ivar->rca, newcard ? " added" : ""); device_printf(dev, " card: %s\n", ivar->card_id_string); device_printf(dev, " bus: %ubit, %uMHz%s\n", (ivar->bus_width == bus_width_1 ? 1 : (ivar->bus_width == bus_width_4 ? 4 : 8)), (ivar->timing == bus_timing_hs ? ivar->hs_tran_speed : ivar->tran_speed) / 1000000, ivar->timing == bus_timing_hs ? ", high speed timing" : ""); device_printf(dev, " memory: %u blocks, erase sector %u blocks%s\n", ivar->sec_count, ivar->erase_sector, ivar->read_only ? ", read-only" : ""); } static void mmc_discover_cards(struct mmc_softc *sc) { struct mmc_ivars *ivar = NULL; device_t *devlist; int err, i, devcount, newcard; uint32_t raw_cid[4], resp, sec_count, status; device_t child; uint16_t rca = 2; u_char switch_res[64]; if (bootverbose || mmc_debug) device_printf(sc->dev, "Probing cards\n"); while (1) { err = mmc_all_send_cid(sc, raw_cid); if (err == MMC_ERR_TIMEOUT) break; if (err != MMC_ERR_NONE) { device_printf(sc->dev, "Error reading CID %d\n", err); break; } newcard = 1; if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) return; for (i = 0; i < devcount; i++) { ivar = device_get_ivars(devlist[i]); if (memcmp(ivar->raw_cid, raw_cid, sizeof(raw_cid)) == 0) { newcard = 0; break; } } free(devlist, M_TEMP); if (bootverbose || mmc_debug) { device_printf(sc->dev, "%sard detected (CID %08x%08x%08x%08x)\n", newcard ? "New c" : "C", raw_cid[0], raw_cid[1], raw_cid[2], raw_cid[3]); } if (newcard) { ivar = malloc(sizeof(struct mmc_ivars), M_DEVBUF, M_WAITOK | M_ZERO); memcpy(ivar->raw_cid, raw_cid, sizeof(raw_cid)); } if (mmcbr_get_ro(sc->dev)) ivar->read_only = 1; ivar->bus_width = bus_width_1; ivar->timing = bus_timing_normal; ivar->mode = mmcbr_get_mode(sc->dev); if (ivar->mode == mode_sd) { mmc_decode_cid_sd(ivar->raw_cid, &ivar->cid); mmc_send_relative_addr(sc, &resp); ivar->rca = resp >> 16; /* Get card CSD. */ mmc_send_csd(sc, ivar->rca, ivar->raw_csd); if (bootverbose || mmc_debug) device_printf(sc->dev, "%sard detected (CSD %08x%08x%08x%08x)\n", newcard ? "New c" : "C", ivar->raw_csd[0], ivar->raw_csd[1], ivar->raw_csd[2], ivar->raw_csd[3]); mmc_decode_csd_sd(ivar->raw_csd, &ivar->csd); ivar->sec_count = ivar->csd.capacity / MMC_SECTOR_SIZE; if (ivar->csd.csd_structure > 0) ivar->high_cap = 1; ivar->tran_speed = ivar->csd.tran_speed; ivar->erase_sector = ivar->csd.erase_sector * ivar->csd.write_bl_len / MMC_SECTOR_SIZE; err = mmc_send_status(sc, ivar->rca, &status); if (err != MMC_ERR_NONE) { device_printf(sc->dev, "Error reading card status %d\n", err); break; } if ((status & R1_CARD_IS_LOCKED) != 0) { device_printf(sc->dev, "Card is password protected, skipping.\n"); break; } /* Get card SCR. Card must be selected to fetch it. */ mmc_select_card(sc, ivar->rca); mmc_app_send_scr(sc, ivar->rca, ivar->raw_scr); mmc_app_decode_scr(ivar->raw_scr, &ivar->scr); /* Get card switch capabilities (command class 10). */ if ((ivar->scr.sda_vsn >= 1) && (ivar->csd.ccc & (1<<10))) { mmc_sd_switch(sc, SD_SWITCH_MODE_CHECK, SD_SWITCH_GROUP1, SD_SWITCH_NOCHANGE, switch_res); if (switch_res[13] & 2) { ivar->timing = bus_timing_hs; ivar->hs_tran_speed = SD_MAX_HS; } } mmc_app_sd_status(sc, ivar->rca, ivar->raw_sd_status); mmc_app_decode_sd_status(ivar->raw_sd_status, &ivar->sd_status); if (ivar->sd_status.au_size != 0) { ivar->erase_sector = 16 << ivar->sd_status.au_size; } mmc_select_card(sc, 0); /* Find max supported bus width. */ if ((mmcbr_get_caps(sc->dev) & MMC_CAP_4_BIT_DATA) && (ivar->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) ivar->bus_width = bus_width_4; /* * Some cards that report maximum I/O block sizes * greater than 512 require the block length to be * set to 512, even though that is supposed to be * the default. Example: * * Transcend 2GB SDSC card, CID: * mid=0x1b oid=0x534d pnm="00000" prv=1.0 mdt=00.2000 */ if (ivar->csd.read_bl_len != MMC_SECTOR_SIZE || ivar->csd.write_bl_len != MMC_SECTOR_SIZE) mmc_set_blocklen(sc, MMC_SECTOR_SIZE); mmc_format_card_id_string(ivar); if (bootverbose || mmc_debug) mmc_log_card(sc->dev, ivar, newcard); if (newcard) { /* Add device. */ child = device_add_child(sc->dev, NULL, -1); device_set_ivars(child, ivar); } return; } mmc_decode_cid_mmc(ivar->raw_cid, &ivar->cid); ivar->rca = rca++; mmc_set_relative_addr(sc, ivar->rca); /* Get card CSD. */ mmc_send_csd(sc, ivar->rca, ivar->raw_csd); if (bootverbose || mmc_debug) device_printf(sc->dev, "%sard detected (CSD %08x%08x%08x%08x)\n", newcard ? "New c" : "C", ivar->raw_csd[0], ivar->raw_csd[1], ivar->raw_csd[2], ivar->raw_csd[3]); mmc_decode_csd_mmc(ivar->raw_csd, &ivar->csd); ivar->sec_count = ivar->csd.capacity / MMC_SECTOR_SIZE; ivar->tran_speed = ivar->csd.tran_speed; ivar->erase_sector = ivar->csd.erase_sector * ivar->csd.write_bl_len / MMC_SECTOR_SIZE; err = mmc_send_status(sc, ivar->rca, &status); if (err != MMC_ERR_NONE) { device_printf(sc->dev, "Error reading card status %d\n", err); break; } if ((status & R1_CARD_IS_LOCKED) != 0) { device_printf(sc->dev, "Card is password protected, skipping.\n"); break; } /* Only MMC >= 4.x cards support EXT_CSD. */ if (ivar->csd.spec_vers >= 4) { /* Card must be selected to fetch EXT_CSD. */ mmc_select_card(sc, ivar->rca); mmc_send_ext_csd(sc, ivar->raw_ext_csd); /* Handle extended capacity from EXT_CSD */ sec_count = ivar->raw_ext_csd[EXT_CSD_SEC_CNT] + (ivar->raw_ext_csd[EXT_CSD_SEC_CNT + 1] << 8) + (ivar->raw_ext_csd[EXT_CSD_SEC_CNT + 2] << 16) + (ivar->raw_ext_csd[EXT_CSD_SEC_CNT + 3] << 24); if (sec_count != 0) { ivar->sec_count = sec_count; ivar->high_cap = 1; } /* Get card speed in high speed mode. */ ivar->timing = bus_timing_hs; if (ivar->raw_ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_52) ivar->hs_tran_speed = MMC_TYPE_52_MAX_HS; else if (ivar->raw_ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_26) ivar->hs_tran_speed = MMC_TYPE_26_MAX_HS; else ivar->hs_tran_speed = ivar->tran_speed; /* Find max supported bus width. */ ivar->bus_width = mmc_test_bus_width(sc); mmc_select_card(sc, 0); /* Handle HC erase sector size. */ if (ivar->raw_ext_csd[EXT_CSD_ERASE_GRP_SIZE] != 0) { ivar->erase_sector = 1024 * ivar->raw_ext_csd[EXT_CSD_ERASE_GRP_SIZE]; mmc_switch(sc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_ERASE_GRP_DEF, 1); } } else { ivar->bus_width = bus_width_1; ivar->timing = bus_timing_normal; } /* * Some cards that report maximum I/O block sizes greater * than 512 require the block length to be set to 512, even * though that is supposed to be the default. Example: * * Transcend 2GB SDSC card, CID: * mid=0x1b oid=0x534d pnm="00000" prv=1.0 mdt=00.2000 */ if (ivar->csd.read_bl_len != MMC_SECTOR_SIZE || ivar->csd.write_bl_len != MMC_SECTOR_SIZE) mmc_set_blocklen(sc, MMC_SECTOR_SIZE); mmc_format_card_id_string(ivar); if (bootverbose || mmc_debug) mmc_log_card(sc->dev, ivar, newcard); if (newcard) { /* Add device. */ child = device_add_child(sc->dev, NULL, -1); device_set_ivars(child, ivar); } } } static void mmc_rescan_cards(struct mmc_softc *sc) { struct mmc_ivars *ivar = NULL; device_t *devlist; int err, i, devcount; if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) return; for (i = 0; i < devcount; i++) { ivar = device_get_ivars(devlist[i]); if (mmc_select_card(sc, ivar->rca)) { if (bootverbose || mmc_debug) device_printf(sc->dev, "Card at relative address %d lost.\n", ivar->rca); device_delete_child(sc->dev, devlist[i]); free(ivar, M_DEVBUF); } } free(devlist, M_TEMP); mmc_select_card(sc, 0); } static int mmc_delete_cards(struct mmc_softc *sc) { struct mmc_ivars *ivar; device_t *devlist; int err, i, devcount; if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0) return (err); for (i = 0; i < devcount; i++) { ivar = device_get_ivars(devlist[i]); if (bootverbose || mmc_debug) device_printf(sc->dev, "Card at relative address %d deleted.\n", ivar->rca); device_delete_child(sc->dev, devlist[i]); free(ivar, M_DEVBUF); } free(devlist, M_TEMP); return (0); } static void mmc_go_discovery(struct mmc_softc *sc) { uint32_t ocr; device_t dev; int err; dev = sc->dev; if (mmcbr_get_power_mode(dev) != power_on) { /* * First, try SD modes */ mmcbr_set_mode(dev, mode_sd); mmc_power_up(sc); mmcbr_set_bus_mode(dev, pushpull); if (bootverbose || mmc_debug) device_printf(sc->dev, "Probing bus\n"); mmc_idle_cards(sc); err = mmc_send_if_cond(sc, 1); if ((bootverbose || mmc_debug) && err == 0) device_printf(sc->dev, "SD 2.0 interface conditions: OK\n"); if (mmc_send_app_op_cond(sc, 0, &ocr) != MMC_ERR_NONE) { if (bootverbose || mmc_debug) device_printf(sc->dev, "SD probe: failed\n"); /* * Failed, try MMC */ mmcbr_set_mode(dev, mode_mmc); if (mmc_send_op_cond(sc, 0, &ocr) != MMC_ERR_NONE) { if (bootverbose || mmc_debug) device_printf(sc->dev, "MMC probe: failed\n"); ocr = 0; /* Failed both, powerdown. */ } else if (bootverbose || mmc_debug) device_printf(sc->dev, "MMC probe: OK (OCR: 0x%08x)\n", ocr); } else if (bootverbose || mmc_debug) device_printf(sc->dev, "SD probe: OK (OCR: 0x%08x)\n", ocr); mmcbr_set_ocr(dev, mmc_select_vdd(sc, ocr)); if (mmcbr_get_ocr(dev) != 0) mmc_idle_cards(sc); } else { mmcbr_set_bus_mode(dev, opendrain); mmcbr_set_clock(dev, CARD_ID_FREQUENCY); mmcbr_update_ios(dev); /* XXX recompute vdd based on new cards? */ } /* * Make sure that we have a mutually agreeable voltage to at least * one card on the bus. */ if (bootverbose || mmc_debug) device_printf(sc->dev, "Current OCR: 0x%08x\n", mmcbr_get_ocr(dev)); if (mmcbr_get_ocr(dev) == 0) { device_printf(sc->dev, "No compatible cards found on bus\n"); mmc_delete_cards(sc); mmc_power_down(sc); return; } /* * Reselect the cards after we've idled them above. */ if (mmcbr_get_mode(dev) == mode_sd) { err = mmc_send_if_cond(sc, 1); mmc_send_app_op_cond(sc, (err ? 0 : MMC_OCR_CCS) | mmcbr_get_ocr(dev), NULL); } else mmc_send_op_cond(sc, mmcbr_get_ocr(dev), NULL); mmc_discover_cards(sc); mmc_rescan_cards(sc); mmcbr_set_bus_mode(dev, pushpull); mmcbr_update_ios(dev); mmc_calculate_clock(sc); bus_generic_attach(dev); /* mmc_update_children_sysctl(dev);*/ } static int mmc_calculate_clock(struct mmc_softc *sc) { int max_dtr, max_hs_dtr, max_timing; int nkid, i, f_max; device_t *kids; struct mmc_ivars *ivar; f_max = mmcbr_get_f_max(sc->dev); max_dtr = max_hs_dtr = f_max; if ((mmcbr_get_caps(sc->dev) & MMC_CAP_HSPEED)) max_timing = bus_timing_hs; else max_timing = bus_timing_normal; if (device_get_children(sc->dev, &kids, &nkid) != 0) panic("can't get children"); for (i = 0; i < nkid; i++) { ivar = device_get_ivars(kids[i]); if (ivar->timing < max_timing) max_timing = ivar->timing; if (ivar->tran_speed < max_dtr) max_dtr = ivar->tran_speed; if (ivar->hs_tran_speed < max_hs_dtr) max_hs_dtr = ivar->hs_tran_speed; } for (i = 0; i < nkid; i++) { ivar = device_get_ivars(kids[i]); if (ivar->timing == bus_timing_normal) continue; mmc_select_card(sc, ivar->rca); mmc_set_timing(sc, max_timing); } mmc_select_card(sc, 0); free(kids, M_TEMP); if (max_timing == bus_timing_hs) max_dtr = max_hs_dtr; if (bootverbose || mmc_debug) { device_printf(sc->dev, "setting transfer rate to %d.%03dMHz%s\n", max_dtr / 1000000, (max_dtr / 1000) % 1000, max_timing == bus_timing_hs ? " (high speed timing)" : ""); } mmcbr_set_timing(sc->dev, max_timing); mmcbr_set_clock(sc->dev, max_dtr); mmcbr_update_ios(sc->dev); return max_dtr; } static void mmc_scan(struct mmc_softc *sc) { device_t dev = sc->dev; mmc_acquire_bus(dev, dev); mmc_go_discovery(sc); mmc_release_bus(dev, dev); } static int mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct mmc_ivars *ivar = device_get_ivars(child); switch (which) { default: return (EINVAL); case MMC_IVAR_DSR_IMP: *result = ivar->csd.dsr_imp; break; case MMC_IVAR_MEDIA_SIZE: *result = ivar->sec_count; break; case MMC_IVAR_RCA: *result = ivar->rca; break; case MMC_IVAR_SECTOR_SIZE: *result = MMC_SECTOR_SIZE; break; case MMC_IVAR_TRAN_SPEED: *result = mmcbr_get_clock(bus); break; case MMC_IVAR_READ_ONLY: *result = ivar->read_only; break; case MMC_IVAR_HIGH_CAP: *result = ivar->high_cap; break; case MMC_IVAR_CARD_TYPE: *result = ivar->mode; break; case MMC_IVAR_BUS_WIDTH: *result = ivar->bus_width; break; case MMC_IVAR_ERASE_SECTOR: *result = ivar->erase_sector; break; case MMC_IVAR_MAX_DATA: *result = mmcbr_get_max_data(bus); break; case MMC_IVAR_CARD_ID_STRING: *(char **)result = ivar->card_id_string; break; case MMC_IVAR_CARD_SN_STRING: *(char **)result = ivar->card_sn_string; break; } return (0); } static int mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) { /* * None are writable ATM */ return (EINVAL); } static void mmc_delayed_attach(void *xsc) { struct mmc_softc *sc = xsc; mmc_scan(sc); config_intrhook_disestablish(&sc->config_intrhook); } static int mmc_child_location_str(device_t dev, device_t child, char *buf, size_t buflen) { snprintf(buf, buflen, "rca=0x%04x", mmc_get_rca(child)); return (0); } static device_method_t mmc_methods[] = { /* device_if */ DEVMETHOD(device_probe, mmc_probe), DEVMETHOD(device_attach, mmc_attach), DEVMETHOD(device_detach, mmc_detach), DEVMETHOD(device_suspend, mmc_suspend), DEVMETHOD(device_resume, mmc_resume), /* Bus interface */ DEVMETHOD(bus_read_ivar, mmc_read_ivar), DEVMETHOD(bus_write_ivar, mmc_write_ivar), DEVMETHOD(bus_child_location_str, mmc_child_location_str), /* MMC Bus interface */ DEVMETHOD(mmcbus_wait_for_request, mmc_wait_for_request), DEVMETHOD(mmcbus_acquire_bus, mmc_acquire_bus), DEVMETHOD(mmcbus_release_bus, mmc_release_bus), DEVMETHOD_END }; static driver_t mmc_driver = { "mmc", mmc_methods, sizeof(struct mmc_softc), }; static devclass_t mmc_devclass; DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_bcm, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_fdt, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_imx, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL); DRIVER_MODULE(mmc, ti_mmchs, mmc_driver, mmc_devclass, NULL, NULL); +DRIVER_MODULE(mmc, dwmmc, mmc_driver, mmc_devclass, NULL, NULL);