Index: head/sys/arm/arm/nexus.c =================================================================== --- head/sys/arm/arm/nexus.c (revision 271483) +++ head/sys/arm/arm/nexus.c (revision 271484) @@ -1,364 +1,382 @@ /*- * Copyright 1998 Massachusetts Institute of Technology * * Permission to use, copy, modify, and distribute this software and * its documentation for any purpose and without fee is hereby * granted, provided that both the above copyright notice and this * permission notice appear in all copies, that both the above * copyright notice and this permission notice appear in all * supporting documentation, and that the name of M.I.T. not be used * in advertising or publicity pertaining to distribution of the * software without specific, written prior permission. M.I.T. makes * no representations about the suitability of this software for any * purpose. It is provided "as is" without express or implied * warranty. * * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ /* * This code implements a `root nexus' for Arm Architecture * machines. The function of the root nexus is to serve as an * attachment point for both processors and buses, and to manage * resources which are common to all of them. In particular, * this code implements the core resource managers for interrupt * requests, DMA requests (which rightfully should be a part of the * ISA code but it's easier to do it here for now), I/O port addresses, * and I/O memory address space. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "opt_platform.h" #ifdef FDT #include #include #include "ofw_bus_if.h" #endif static MALLOC_DEFINE(M_NEXUSDEV, "nexusdev", "Nexus device"); struct nexus_device { struct resource_list nx_resources; }; #define DEVTONX(dev) ((struct nexus_device *)device_get_ivars(dev)) static struct rman mem_rman; static int nexus_probe(device_t); static int nexus_attach(device_t); static int nexus_print_child(device_t, device_t); static device_t nexus_add_child(device_t, u_int, const char *, int); static struct resource *nexus_alloc_resource(device_t, device_t, int, int *, u_long, u_long, u_long, u_int); static int nexus_activate_resource(device_t, device_t, int, int, struct resource *); static int nexus_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol); static int nexus_deactivate_resource(device_t, device_t, int, int, struct resource *); +static int nexus_release_resource(device_t, device_t, int, int, + struct resource *); static int nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep); static int nexus_teardown_intr(device_t, device_t, struct resource *, void *); #ifdef FDT static int nexus_ofw_map_intr(device_t dev, device_t child, phandle_t iparent, int icells, pcell_t *intr); #endif static device_method_t nexus_methods[] = { /* Device interface */ DEVMETHOD(device_probe, nexus_probe), DEVMETHOD(device_attach, nexus_attach), /* Bus interface */ DEVMETHOD(bus_print_child, nexus_print_child), DEVMETHOD(bus_add_child, nexus_add_child), DEVMETHOD(bus_alloc_resource, nexus_alloc_resource), DEVMETHOD(bus_activate_resource, nexus_activate_resource), DEVMETHOD(bus_config_intr, nexus_config_intr), DEVMETHOD(bus_deactivate_resource, nexus_deactivate_resource), + DEVMETHOD(bus_release_resource, nexus_release_resource), DEVMETHOD(bus_setup_intr, nexus_setup_intr), DEVMETHOD(bus_teardown_intr, nexus_teardown_intr), #ifdef FDT DEVMETHOD(ofw_bus_map_intr, nexus_ofw_map_intr), #endif { 0, 0 } }; static devclass_t nexus_devclass; static driver_t nexus_driver = { "nexus", nexus_methods, 1 /* no softc */ }; #ifdef ARM_DEVICE_MULTIPASS EARLY_DRIVER_MODULE(nexus, root, nexus_driver, nexus_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_EARLY); #else DRIVER_MODULE(nexus, root, nexus_driver, nexus_devclass, 0, 0); #endif static int nexus_probe(device_t dev) { device_quiet(dev); /* suppress attach message for neatness */ return (BUS_PROBE_DEFAULT); } static int nexus_attach(device_t dev) { mem_rman.rm_start = 0; mem_rman.rm_end = ~0ul; mem_rman.rm_type = RMAN_ARRAY; mem_rman.rm_descr = "I/O memory addresses"; if (rman_init(&mem_rman) || rman_manage_region(&mem_rman, 0, ~0)) panic("nexus_probe mem_rman"); /* * First, deal with the children we know about already */ bus_generic_probe(dev); bus_generic_attach(dev); return (0); } static int nexus_print_child(device_t bus, device_t child) { int retval = 0; retval += bus_print_child_header(bus, child); retval += printf("\n"); return (retval); } static device_t nexus_add_child(device_t bus, u_int order, const char *name, int unit) { device_t child; struct nexus_device *ndev; ndev = malloc(sizeof(struct nexus_device), M_NEXUSDEV, M_NOWAIT|M_ZERO); if (!ndev) return (0); resource_list_init(&ndev->nx_resources); child = device_add_child_ordered(bus, order, name, unit); /* should we free this in nexus_child_detached? */ device_set_ivars(child, ndev); return (child); } /* * Allocate a resource on behalf of child. NB: child is usually going to be a * child of one of our descendants, not a direct child of nexus0. * (Exceptions include footbridge.) */ static struct resource * nexus_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct resource *rv; struct rman *rm; int needactivate = flags & RF_ACTIVE; + flags &= ~RF_ACTIVE; + switch (type) { case SYS_RES_MEMORY: case SYS_RES_IOPORT: rm = &mem_rman; break; default: - return (0); + return (NULL); } rv = rman_reserve_resource(rm, start, end, count, flags, child); if (rv == 0) - return (0); + return (NULL); rman_set_rid(rv, *rid); - rman_set_bushandle(rv, rman_get_start(rv)); if (needactivate) { if (bus_activate_resource(child, type, *rid, rv)) { rman_release_resource(rv); return (0); } } return (rv); +} + +static int +nexus_release_resource(device_t bus, device_t child, int type, int rid, + struct resource *res) +{ + int error; + + if (rman_get_flags(res) & RF_ACTIVE) { + error = bus_deactivate_resource(child, type, rid, res); + if (error) + return (error); + } + return (rman_release_resource(res)); } static int nexus_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol) { int ret = ENODEV; if (arm_config_irq) ret = (*arm_config_irq)(irq, trig, pol); return (ret); } static int nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int irq; if ((rman_get_flags(res) & RF_SHAREABLE) == 0) flags |= INTR_EXCL; for (irq = rman_get_start(res); irq <= rman_get_end(res); irq++) { arm_setup_irqhandler(device_get_nameunit(child), filt, intr, arg, irq, flags, cookiep); arm_unmask_irq(irq); } return (0); } static int nexus_teardown_intr(device_t dev, device_t child, struct resource *r, void *ih) { return (arm_remove_irqhandler(rman_get_start(r), ih)); } static int nexus_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { int err; bus_addr_t paddr; bus_size_t psize; bus_space_handle_t vaddr; if ((err = rman_activate_resource(r)) != 0) return (err); /* * If this is a memory resource, map it into the kernel. */ if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { paddr = (bus_addr_t)rman_get_start(r); psize = (bus_size_t)rman_get_size(r); #ifdef FDT err = bus_space_map(fdtbus_bs_tag, paddr, psize, 0, &vaddr); if (err != 0) { rman_deactivate_resource(r); return (err); } rman_set_bustag(r, fdtbus_bs_tag); #else vaddr = (bus_space_handle_t)pmap_mapdev((vm_offset_t)paddr, (vm_size_t)psize); if (vaddr == 0) { rman_deactivate_resource(r); return (ENOMEM); } rman_set_bustag(r, (void *)1); #endif rman_set_virtual(r, (void *)vaddr); rman_set_bushandle(r, vaddr); } return (0); } static int nexus_deactivate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { bus_size_t psize; bus_space_handle_t vaddr; psize = (bus_size_t)rman_get_size(r); vaddr = rman_get_bushandle(r); if (vaddr != 0) { #ifdef FDT bus_space_unmap(fdtbus_bs_tag, vaddr, psize); #else pmap_unmapdev((vm_offset_t)vaddr, (vm_size_t)psize); #endif rman_set_virtual(r, NULL); rman_set_bushandle(r, 0); } return (rman_deactivate_resource(r)); } #ifdef FDT static int nexus_ofw_map_intr(device_t dev, device_t child, phandle_t iparent, int icells, pcell_t *intr) { fdt_pic_decode_t intr_decode; phandle_t intr_offset; int i, rv, interrupt, trig, pol; intr_offset = OF_node_from_xref(iparent); for (i = 0; i < icells; i++) intr[i] = cpu_to_fdt32(intr[i]); for (i = 0; fdt_pic_table[i] != NULL; i++) { intr_decode = fdt_pic_table[i]; rv = intr_decode(intr_offset, intr, &interrupt, &trig, &pol); if (rv == 0) { /* This was recognized as our PIC and decoded. */ interrupt = FDT_MAP_IRQ(intr_parent, interrupt); return (interrupt); } } /* Not in table, so guess */ interrupt = FDT_MAP_IRQ(intr_parent, fdt32_to_cpu(intr[0])); return (interrupt); } #endif Index: head/sys/arm/xscale/ixp425/ixp425_pci.c =================================================================== --- head/sys/arm/xscale/ixp425/ixp425_pci.c (revision 271483) +++ head/sys/arm/xscale/ixp425/ixp425_pci.c (revision 271484) @@ -1,477 +1,480 @@ /* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */ /* * Copyright (c) 2003 * Ichiro FUKUHARA . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Ichiro FUKUHARA. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #include extern struct ixp425_softc *ixp425_softc; #define PCI_CSR_WRITE_4(sc, reg, data) \ bus_write_4(sc->sc_csr, reg, data) #define PCI_CSR_READ_4(sc, reg) \ bus_read_4(sc->sc_csr, reg) #define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I) #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) static device_probe_t ixppcib_probe; static device_attach_t ixppcib_attach; static bus_read_ivar_t ixppcib_read_ivar; static bus_write_ivar_t ixppcib_write_ivar; static bus_setup_intr_t ixppcib_setup_intr; static bus_teardown_intr_t ixppcib_teardown_intr; static bus_alloc_resource_t ixppcib_alloc_resource; static bus_activate_resource_t ixppcib_activate_resource; static bus_deactivate_resource_t ixppcib_deactivate_resource; static bus_release_resource_t ixppcib_release_resource; static pcib_maxslots_t ixppcib_maxslots; static pcib_read_config_t ixppcib_read_config; static pcib_write_config_t ixppcib_write_config; static pcib_route_interrupt_t ixppcib_route_interrupt; static int ixppcib_probe(device_t dev) { device_set_desc(dev, "IXP4XX PCI Bus"); return (0); } static void ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg, uint32_t data) { PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE)); PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data); } static int ixppcib_attach(device_t dev) { int rid; struct ixppcib_softc *sc; sc = device_get_softc(dev); rid = 0; sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE, IXP425_PCI_SIZE, RF_ACTIVE); if (sc->sc_csr == NULL) panic("cannot allocate PCI CSR registers"); ixp425_md_attach(dev); /* always setup the base, incase another OS messes w/ it */ PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b); rid = 0; sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE, IXP425_PCI_MEM_SIZE, RF_ACTIVE); if (sc->sc_mem == NULL) panic("cannot allocate PCI MEM space"); /* NB: PCI dma window is 64M so anything above must be bounced */ if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024, BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_dmat)) panic("couldn't create the PCI dma tag !"); /* * The PCI bus can only address 64MB. However, due to the way our * implementation of busdma works, busdma can't tell if a device * is a PCI device or not. So defaults to the PCI dma tag, which * restrict the DMA'able memory to the first 64MB, and explicitely * create less restrictive tags for non-PCI devices. */ arm_root_dma_tag = sc->sc_dmat; /* * Initialize the bus space tags. */ ixp425_io_bs_init(&sc->sc_pci_iot, sc); ixp425_mem_bs_init(&sc->sc_pci_memt, sc); sc->sc_dev = dev; /* Initialize memory and i/o rmans. */ sc->sc_io_rman.rm_type = RMAN_ARRAY; sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports"; if (rman_init(&sc->sc_io_rman) != 0 || rman_manage_region(&sc->sc_io_rman, 0, IXP425_PCI_IO_SIZE) != 0) { panic("ixppcib_probe: failed to set up I/O rman"); } sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory"; if (rman_init(&sc->sc_mem_rman) != 0 || rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) { panic("ixppcib_probe: failed to set up memory rman"); } /* * PCI->AHB address translation * begin at the physical memory start + OFFSET */ PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, (IXP425_AHB_OFFSET & 0xFF000000) + ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) + ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) + ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) + 0x00010203); #define IXPPCIB_WRITE_CONF(sc, reg, val) \ ixp425_pci_conf_reg_write(sc, reg, val) /* Write Mapping registers PCI Configuration Registers */ /* Base Address 0 - 3 */ IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000); IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000); IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000); IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000); /* Base Address 4 */ IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff); /* Base Address 5 */ IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000); /* Assert some PCI errors */ PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE); #ifdef __ARMEB__ /* * Set up byte lane swapping between little-endian PCI * and the big-endian AHB bus */ PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS); #else PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE); #endif /* * Enable bus mastering and I/O,memory access */ IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND, PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); /* * Wait some more to ensure PCI devices have stabilised. */ DELAY(50000); device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } static int ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) { struct ixppcib_softc *sc; sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_DOMAIN: *result = 0; return (0); case PCIB_IVAR_BUS: *result = sc->sc_bus; return (0); } return (ENOENT); } static int ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) { struct ixppcib_softc *sc; sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_DOMAIN: return (EINVAL); case PCIB_IVAR_BUS: sc->sc_bus = value; return (0); } return (ENOENT); } static int ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep)); } static int ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec, void *cookie) { return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie)); } static struct resource * ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct ixppcib_softc *sc = device_get_softc(bus); struct rman *rmanp; struct resource *rv; rv = NULL; switch (type) { case SYS_RES_IRQ: rmanp = &sc->sc_irq_rman; break; case SYS_RES_IOPORT: rmanp = &sc->sc_io_rman; break; case SYS_RES_MEMORY: rmanp = &sc->sc_mem_rman; break; default: return (rv); } rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE, child); if (rv == NULL) return (NULL); rman_set_rid(rv, *rid); if (flags & RF_ACTIVE) { if (bus_activate_resource(child, type, *rid, rv)) { rman_release_resource(rv); return (NULL); } } return (rv); } static int ixppcib_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { - struct ixppcib_softc *sc = device_get_softc(bus); + int error; + error = rman_activate_resource(r); + if (error) + return (error); switch (type) { case SYS_RES_IOPORT: rman_set_bustag(r, &sc->sc_pci_iot); rman_set_bushandle(r, rman_get_start(r)); break; case SYS_RES_MEMORY: rman_set_bustag(r, &sc->sc_pci_memt); rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) + (rman_get_start(r) - IXP425_PCI_MEM_HWBASE)); break; } - return (rman_activate_resource(r)); + return (0); } static int ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { device_printf(bus, "%s called deactivate_resource (unexpected)\n", device_get_nameunit(child)); return (ENXIO); } static int ixppcib_release_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { device_printf(bus, "%s called release_resource (unexpected)\n", device_get_nameunit(child)); return (ENXIO); } static void ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func, int reg) { if (bus == 0) { /* configuration type 0 */ PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - (slot & 0x1f))) | ((func & 0x7) << 8) | (reg & ~3)); } else { /* configuration type 1 */ PCI_CSR_WRITE_4(sc, PCI_NP_AD, (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3) | 1); } } static int ixppcib_maxslots(device_t dev) { return (PCI_SLOTMAX); } static u_int32_t ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { struct ixppcib_softc *sc = device_get_softc(dev); u_int32_t data, ret; ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ); ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA); ret >>= (reg & 3) * 8; ret &= 0xffffffff >> ((4 - bytes) * 8); #if 0 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", __func__, bus, slot, func, reg, bytes, ret); #endif /* check & clear PCI abort */ data = PCI_CSR_READ_4(sc, PCI_ISR); if (data & ISR_PFE) { PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); return (-1); } return (ret); } static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 }; static void ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, u_int32_t val, int bytes) { struct ixppcib_softc *sc = device_get_softc(dev); u_int32_t data; #if 0 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", __func__, bus, slot, func, reg, bytes, val); #endif ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); /* Byte enables are active low, so not them first */ PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE | (~(byteenables[bytes] << (reg & 3)) & 0xf0)); PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8)); /* check & clear PCI abort */ data = PCI_CSR_READ_4(sc, PCI_ISR); if (data & ISR_PFE) PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); } static int ixppcib_route_interrupt(device_t bridge, device_t device, int pin) { return (ixp425_md_route_interrupt(bridge, device, pin)); } static device_method_t ixppcib_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ixppcib_probe), DEVMETHOD(device_attach, ixppcib_attach), /* Bus interface */ DEVMETHOD(bus_read_ivar, ixppcib_read_ivar), DEVMETHOD(bus_write_ivar, ixppcib_write_ivar), DEVMETHOD(bus_setup_intr, ixppcib_setup_intr), DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr), DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource), DEVMETHOD(bus_activate_resource, ixppcib_activate_resource), DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource), DEVMETHOD(bus_release_resource, ixppcib_release_resource), /* DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), */ /* pcib interface */ DEVMETHOD(pcib_maxslots, ixppcib_maxslots), DEVMETHOD(pcib_read_config, ixppcib_read_config), DEVMETHOD(pcib_write_config, ixppcib_write_config), DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt), DEVMETHOD_END }; static driver_t ixppcib_driver = { "pcib", ixppcib_methods, sizeof(struct ixppcib_softc), }; static devclass_t ixppcib_devclass; DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);