Index: head/sys/arm/arm/cpufunc_asm_sheeva.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_sheeva.S (revision 271397) +++ head/sys/arm/arm/cpufunc_asm_sheeva.S (revision 271398) @@ -1,420 +1,421 @@ /*- * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of MARVELL nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ +#include #include __FBSDID("$FreeBSD$"); #include .Lsheeva_cache_line_size: .word _C_LABEL(arm_pdcache_line_size) .Lsheeva_asm_page_mask: .word _C_LABEL(PAGE_MASK) ENTRY(sheeva_setttb) /* Disable irqs */ mrs r2, cpsr - orr r3, r2, #I32_bit | F32_bit + orr r3, r2, #PSR_I | PSR_F msr cpsr_c, r3 mov r1, #0 mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */ 1: mrc p15, 0, r15, c7, c14, 3 /* Test, clean and invalidate DCache */ bne 1b /* More to do? */ mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */ mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */ /* Reenable irqs */ msr cpsr_c, r2 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ RET END(sheeva_setttb) ENTRY(sheeva_dcache_wbinv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip add r1, r1, r2 add r1, r1, ip bics r1, r1, ip bics r0, r0, ip ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 movcc ip, r1 movcs ip, r2 1: add r3, r0, ip sub r2, r3, #1 /* Disable irqs */ - orr r3, lr, #I32_bit | F32_bit + orr r3, lr, #PSR_I | PSR_F msr cpsr_c, r3 mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */ mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */ /* Enable irqs */ msr cpsr_c, lr add r0, r0, ip sub r1, r1, ip cmp r1, #PAGE_SIZE movcc ip, r1 movcs ip, #PAGE_SIZE cmp r1, #0 bne 1b mov r0, #0 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ ldr lr, [sp], #4 RET END(sheeva_dcache_wbinv_range) ENTRY(sheeva_idcache_wbinv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip add r1, r1, r2 add r1, r1, ip bics r1, r1, ip bics r0, r0, ip ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 movcc ip, r1 movcs ip, r2 1: add r3, r0, ip sub r2, r3, #1 /* Disable irqs */ - orr r3, lr, #I32_bit | F32_bit + orr r3, lr, #PSR_I | PSR_F msr cpsr_c, r3 mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */ mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */ /* Enable irqs */ msr cpsr_c, lr /* Invalidate and clean icache line by line */ ldr r3, .Lsheeva_cache_line_size ldr r3, [r3] 2: mcr p15, 0, r0, c7, c5, 1 add r0, r0, r3 cmp r2, r0 bhi 2b add r0, r2, #1 sub r1, r1, ip cmp r1, #PAGE_SIZE movcc ip, r1 movcs ip, #PAGE_SIZE cmp r1, #0 bne 1b mov r0, #0 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ ldr lr, [sp], #4 RET END(sheeva_idcache_wbinv_range) ENTRY(sheeva_dcache_inv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip add r1, r1, r2 add r1, r1, ip bics r1, r1, ip bics r0, r0, ip ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 movcc ip, r1 movcs ip, r2 1: add r3, r0, ip sub r2, r3, #1 /* Disable irqs */ - orr r3, lr, #I32_bit | F32_bit + orr r3, lr, #PSR_I | PSR_F msr cpsr_c, r3 mcr p15, 5, r0, c15, c14, 0 /* Inv zone start address */ mcr p15, 5, r2, c15, c14, 1 /* Inv zone end address */ /* Enable irqs */ msr cpsr_c, lr add r0, r0, ip sub r1, r1, ip cmp r1, #PAGE_SIZE movcc ip, r1 movcs ip, #PAGE_SIZE cmp r1, #0 bne 1b mov r0, #0 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ ldr lr, [sp], #4 RET END(sheeva_dcache_inv_range) ENTRY(sheeva_dcache_wb_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip add r1, r1, r2 add r1, r1, ip bics r1, r1, ip bics r0, r0, ip ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 movcc ip, r1 movcs ip, r2 1: add r3, r0, ip sub r2, r3, #1 /* Disable irqs */ - orr r3, lr, #I32_bit | F32_bit + orr r3, lr, #PSR_I | PSR_F msr cpsr_c, r3 mcr p15, 5, r0, c15, c13, 0 /* Clean zone start address */ mcr p15, 5, r2, c15, c13, 1 /* Clean zone end address */ /* Enable irqs */ msr cpsr_c, lr add r0, r0, ip sub r1, r1, ip cmp r1, #PAGE_SIZE movcc ip, r1 movcs ip, #PAGE_SIZE cmp r1, #0 bne 1b mov r0, #0 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ ldr lr, [sp], #4 RET END(sheeva_dcache_wb_range) ENTRY(sheeva_l2cache_wbinv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip add r1, r1, r2 add r1, r1, ip bics r1, r1, ip bics r0, r0, ip ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 movcc ip, r1 movcs ip, r2 1: add r3, r0, ip sub r2, r3, #1 /* Disable irqs */ - orr r3, lr, #I32_bit | F32_bit + orr r3, lr, #PSR_I | PSR_F msr cpsr_c, r3 mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */ mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */ mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */ mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */ /* Enable irqs */ msr cpsr_c, lr add r0, r0, ip sub r1, r1, ip cmp r1, #PAGE_SIZE movcc ip, r1 movcs ip, #PAGE_SIZE cmp r1, #0 bne 1b mov r0, #0 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ ldr lr, [sp], #4 RET END(sheeva_l2cache_wbinv_range) ENTRY(sheeva_l2cache_inv_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip add r1, r1, r2 add r1, r1, ip bics r1, r1, ip bics r0, r0, ip ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 movcc ip, r1 movcs ip, r2 1: add r3, r0, ip sub r2, r3, #1 /* Disable irqs */ - orr r3, lr, #I32_bit | F32_bit + orr r3, lr, #PSR_I | PSR_F msr cpsr_c, r3 mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */ mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */ /* Enable irqs */ msr cpsr_c, lr add r0, r0, ip sub r1, r1, ip cmp r1, #PAGE_SIZE movcc ip, r1 movcs ip, #PAGE_SIZE cmp r1, #0 bne 1b mov r0, #0 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ ldr lr, [sp], #4 RET END(sheeva_l2cache_inv_range) ENTRY(sheeva_l2cache_wb_range) str lr, [sp, #-4]! mrs lr, cpsr /* Start with cache line aligned address */ ldr ip, .Lsheeva_cache_line_size ldr ip, [ip] sub ip, ip, #1 and r2, r0, ip add r1, r1, r2 add r1, r1, ip bics r1, r1, ip bics r0, r0, ip ldr ip, .Lsheeva_asm_page_mask and r2, r0, ip rsb r2, r2, #PAGE_SIZE cmp r1, r2 movcc ip, r1 movcs ip, r2 1: add r3, r0, ip sub r2, r3, #1 /* Disable irqs */ - orr r3, lr, #I32_bit | F32_bit + orr r3, lr, #PSR_I | PSR_F msr cpsr_c, r3 mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */ mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */ /* Enable irqs */ msr cpsr_c, lr add r0, r0, ip sub r1, r1, ip cmp r1, #PAGE_SIZE movcc ip, r1 movcs ip, #PAGE_SIZE cmp r1, #0 bne 1b mov r0, #0 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ ldr lr, [sp], #4 RET END(sheeva_l2cache_wb_range) ENTRY(sheeva_l2cache_wbinv_all) /* Disable irqs */ mrs r1, cpsr - orr r2, r1, #I32_bit | F32_bit + orr r2, r1, #PSR_I | PSR_F msr cpsr_c, r2 mov r0, #0 mcr p15, 1, r0, c15, c9, 0 /* Clean L2 */ mcr p15, 1, r0, c15, c11, 0 /* Invalidate L2 */ msr cpsr_c, r1 /* Reenable irqs */ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(sheeva_l2cache_wbinv_all) /* This function modifies register value as follows: * * arg1 arg EFFECT (bit value saved into register) * 0 0 not changed * 0 1 negated * 1 0 cleared * 1 1 set */ ENTRY(sheeva_control_ext) mrc p15, 1, r3, c15, c1, 0 /* Read the control register */ bic r2, r3, r0 /* Clear bits */ eor r2, r2, r1 /* XOR bits */ teq r2, r3 /* Only write if there is a change */ mcrne p15, 1, r2, c15, c1, 0 /* Write new control register */ mov r0, r3 /* Return old value */ RET END(sheeva_control_ext) ENTRY(sheeva_cpu_sleep) mov r0, #0 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt */ mov pc, lr END(sheeva_cpu_sleep) Index: head/sys/arm/arm/cpufunc_asm_xscale.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_xscale.S (revision 271397) +++ head/sys/arm/arm/cpufunc_asm_xscale.S (revision 271398) @@ -1,523 +1,523 @@ /* $NetBSD: cpufunc_asm_xscale.S,v 1.16 2002/08/17 16:36:32 thorpej Exp $ */ /*- * Copyright (c) 2001, 2002 Wasabi Systems, Inc. * All rights reserved. * * Written by Allen Briggs and Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * */ /*- * Copyright (c) 2001 Matt Thomas. * Copyright (c) 1997,1998 Mark Brinicombe. * Copyright (c) 1997 Causality Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Causality Limited. * 4. The name of Causality Limited may not be used to endorse or promote * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * XScale assembly functions for CPU / MMU / TLB specific operations */ - +#include #include __FBSDID("$FreeBSD$"); /* * Size of the XScale core D-cache. */ #define DCACHE_SIZE 0x00008000 .Lblock_userspace_access: .word _C_LABEL(block_userspace_access) /* * CPWAIT -- Canonical method to wait for CP15 update. * From: Intel 80200 manual, section 2.3.3. * * NOTE: Clobbers the specified temp reg. */ #define CPWAIT_BRANCH \ sub pc, pc, #4 #define CPWAIT(tmp) \ mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ CPWAIT_BRANCH /* branch to next insn */ #define CPWAIT_AND_RETURN_SHIFTER lsr #32 #define CPWAIT_AND_RETURN(tmp) \ mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ /* Wait for it to complete and branch to the return address */ \ sub pc, lr, tmp, CPWAIT_AND_RETURN_SHIFTER ENTRY(xscale_cpwait) CPWAIT_AND_RETURN(r0) END(xscale_cpwait) /* * We need a separate cpu_control() entry point, since we have to * invalidate the Branch Target Buffer in the event the BPRD bit * changes in the control register. */ ENTRY(xscale_control) mrc p15, 0, r3, c1, c0, 0 /* Read the control register */ bic r2, r3, r0 /* Clear bits */ eor r2, r2, r1 /* XOR bits */ teq r2, r3 /* Only write if there was a change */ mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */ mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ mov r0, r3 /* Return old value */ CPWAIT_AND_RETURN(r1) END(xscale_control) /* * Functions to set the MMU Translation Table Base register * * We need to clean and flush the cache as it uses virtual * addresses that are about to change. */ ENTRY(xscale_setttb) #ifdef CACHE_CLEAN_BLOCK_INTR mrs r3, cpsr - orr r1, r3, #(I32_bit | F32_bit) + orr r1, r3, #(PSR_I | PSR_F) msr cpsr_fsxc, r1 #else ldr r3, .Lblock_userspace_access ldr r2, [r3] orr r1, r2, #1 str r1, [r3] #endif stmfd sp!, {r0-r3, lr} bl _C_LABEL(xscale_cache_cleanID) mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */ CPWAIT(r0) ldmfd sp!, {r0-r3, lr} /* Write the TTB */ mcr p15, 0, r0, c2, c0, 0 /* If we have updated the TTB we must flush the TLB */ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */ /* The cleanID above means we only need to flush the I cache here */ mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ CPWAIT(r0) #ifdef CACHE_CLEAN_BLOCK_INTR msr cpsr_fsxc, r3 #else str r2, [r3] #endif RET END(xscale_setttb) /* * TLB functions * */ ENTRY(xscale_tlb_flushID_SE) mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ CPWAIT_AND_RETURN(r0) END(xscale_tlb_flushID_SE) /* * Cache functions */ ENTRY(xscale_cache_flushID) mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ CPWAIT_AND_RETURN(r0) END(xscale_cache_flushID) ENTRY(xscale_cache_flushI) mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ CPWAIT_AND_RETURN(r0) END(xscale_cache_flushI) ENTRY(xscale_cache_flushD) mcr p15, 0, r0, c7, c6, 0 /* flush D cache */ CPWAIT_AND_RETURN(r0) END(xscale_cache_flushD) ENTRY(xscale_cache_flushI_SE) mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ CPWAIT_AND_RETURN(r0) END(xscale_cache_flushI_SE) ENTRY(xscale_cache_flushD_SE) /* * Errata (rev < 2): Must clean-dcache-line to an address * before invalidate-dcache-line to an address, or dirty * bits will not be cleared in the dcache array. */ mcr p15, 0, r0, c7, c10, 1 mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ CPWAIT_AND_RETURN(r0) END(xscale_cache_flushD_SE) ENTRY(xscale_cache_cleanD_E) mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ CPWAIT_AND_RETURN(r0) END(xscale_cache_cleanD_E) /* * Information for the XScale cache clean/purge functions: * * * Virtual address of the memory region to use * * Size of memory region * * Note the virtual address for the Data cache clean operation * does not need to be backed by physical memory, since no loads * will actually be performed by the allocate-line operation. * * Note that the Mini-Data cache MUST be cleaned by executing * loads from memory mapped into a region reserved exclusively * for cleaning of the Mini-Data cache. */ .data .global _C_LABEL(xscale_cache_clean_addr) _C_LABEL(xscale_cache_clean_addr): .word 0x00000000 .global _C_LABEL(xscale_cache_clean_size) _C_LABEL(xscale_cache_clean_size): .word DCACHE_SIZE .global _C_LABEL(xscale_minidata_clean_addr) _C_LABEL(xscale_minidata_clean_addr): .word 0x00000000 .global _C_LABEL(xscale_minidata_clean_size) _C_LABEL(xscale_minidata_clean_size): .word 0x00000800 .text .Lxscale_cache_clean_addr: .word _C_LABEL(xscale_cache_clean_addr) .Lxscale_cache_clean_size: .word _C_LABEL(xscale_cache_clean_size) .Lxscale_minidata_clean_addr: .word _C_LABEL(xscale_minidata_clean_addr) .Lxscale_minidata_clean_size: .word _C_LABEL(xscale_minidata_clean_size) #ifdef CACHE_CLEAN_BLOCK_INTR #define XSCALE_CACHE_CLEAN_BLOCK \ mrs r3, cpsr ; \ - orr r0, r3, #(I32_bit | F32_bit) ; \ + orr r0, r3, #(PSR_I | PSR_F) ; \ msr cpsr_fsxc, r0 #define XSCALE_CACHE_CLEAN_UNBLOCK \ msr cpsr_fsxc, r3 #else #define XSCALE_CACHE_CLEAN_BLOCK \ ldr r3, .Lblock_userspace_access ; \ ldr ip, [r3] ; \ orr r0, ip, #1 ; \ str r0, [r3] #define XSCALE_CACHE_CLEAN_UNBLOCK \ str ip, [r3] #endif /* CACHE_CLEAN_BLOCK_INTR */ #define XSCALE_CACHE_CLEAN_PROLOGUE \ XSCALE_CACHE_CLEAN_BLOCK ; \ ldr r2, .Lxscale_cache_clean_addr ; \ ldmia r2, {r0, r1} ; \ /* \ * BUG ALERT! \ * \ * The XScale core has a strange cache eviction bug, which \ * requires us to use 2x the cache size for the cache clean \ * and for that area to be aligned to 2 * cache size. \ * \ * The work-around is to use 2 areas for cache clean, and to \ * alternate between them whenever this is done. No one knows \ * why the work-around works (mmm!). \ */ \ eor r0, r0, #(DCACHE_SIZE) ; \ str r0, [r2] ; \ add r0, r0, r1 #define XSCALE_CACHE_CLEAN_EPILOGUE \ XSCALE_CACHE_CLEAN_UNBLOCK ENTRY_NP(xscale_cache_syncI) EENTRY_NP(xscale_cache_purgeID) mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */ EENTRY_NP(xscale_cache_cleanID) EENTRY_NP(xscale_cache_purgeD) EENTRY(xscale_cache_cleanD) XSCALE_CACHE_CLEAN_PROLOGUE 1: subs r0, r0, #32 mcr p15, 0, r0, c7, c2, 5 /* allocate cache line */ subs r1, r1, #32 bne 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT(r0) XSCALE_CACHE_CLEAN_EPILOGUE RET EEND(xscale_cache_cleanD) EEND(xscale_cache_purgeD) EEND(xscale_cache_cleanID) EEND(xscale_cache_purgeID) END(xscale_cache_syncI) /* * Clean the mini-data cache. * * It's expected that we only use the mini-data cache for * kernel addresses, so there is no need to purge it on * context switch, and no need to prevent userspace access * while we clean it. */ ENTRY(xscale_cache_clean_minidata) ldr r2, .Lxscale_minidata_clean_addr ldmia r2, {r0, r1} 1: ldr r3, [r0], #32 subs r1, r1, #32 bne 1b mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r1) END(xscale_cache_clean_minidata) ENTRY(xscale_cache_purgeID_E) mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ CPWAIT(r1) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ CPWAIT_AND_RETURN(r1) END(xscale_cache_purgeID_E) ENTRY(xscale_cache_purgeD_E) mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ CPWAIT(r1) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ CPWAIT_AND_RETURN(r1) END(xscale_cache_purgeD_E) /* * Soft functions */ /* xscale_cache_syncI is identical to xscale_cache_purgeID */ EENTRY(xscale_cache_cleanID_rng) ENTRY(xscale_cache_cleanD_rng) cmp r1, #0x4000 bcs _C_LABEL(xscale_cache_cleanID) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) /*END(xscale_cache_cleanID_rng)*/ END(xscale_cache_cleanD_rng) ENTRY(xscale_cache_purgeID_rng) cmp r1, #0x4000 bcs _C_LABEL(xscale_cache_purgeID) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) END(xscale_cache_purgeID_rng) ENTRY(xscale_cache_purgeD_rng) cmp r1, #0x4000 bcs _C_LABEL(xscale_cache_purgeD) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) END(xscale_cache_purgeD_rng) ENTRY(xscale_cache_syncI_rng) cmp r1, #0x4000 bcs _C_LABEL(xscale_cache_syncI) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) END(xscale_cache_syncI_rng) ENTRY(xscale_cache_flushD_rng) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) END(xscale_cache_flushD_rng) /* * Context switch. * * These is the CPU-specific parts of the context switcher cpu_switch() * These functions actually perform the TTB reload. * * NOTE: Special calling convention * r1, r4-r13 must be preserved */ ENTRY(xscale_context_switch) /* * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this. * Thus the data cache will contain only kernel data and the * instruction cache will contain only kernel code, and all * kernel mappings are shared by all processes. */ /* Write the TTB */ mcr p15, 0, r0, c2, c0, 0 /* If we have updated the TTB we must flush the TLB */ mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ CPWAIT_AND_RETURN(r0) END(xscale_context_switch) /* * xscale_cpu_sleep * * This is called when there is nothing on any of the run queues. * We go into IDLE mode so that any IRQ or FIQ will awaken us. * * If this is called with anything other than ARM_SLEEP_MODE_IDLE, * ignore it. */ ENTRY(xscale_cpu_sleep) tst r0, #0x00000000 bne 1f mov r0, #0x1 mcr p14, 0, r0, c7, c0, 0 1: RET END(xscale_cpu_sleep) Index: head/sys/arm/arm/cpufunc_asm_xscale_c3.S =================================================================== --- head/sys/arm/arm/cpufunc_asm_xscale_c3.S (revision 271397) +++ head/sys/arm/arm/cpufunc_asm_xscale_c3.S (revision 271398) @@ -1,416 +1,417 @@ /* $NetBSD: cpufunc_asm_xscale.S,v 1.16 2002/08/17 16:36:32 thorpej Exp $ */ /*- * Copyright (c) 2007 Olivier Houchard * Copyright (c) 2001, 2002 Wasabi Systems, Inc. * All rights reserved. * * Written by Allen Briggs and Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * */ /*- * Copyright (c) 2001 Matt Thomas. * Copyright (c) 1997,1998 Mark Brinicombe. * Copyright (c) 1997 Causality Limited * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Causality Limited. * 4. The name of Causality Limited may not be used to endorse or promote * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * XScale core 3 assembly functions for CPU / MMU / TLB specific operations */ +#include #include __FBSDID("$FreeBSD$"); /* * Size of the XScale core D-cache. */ #define DCACHE_SIZE 0x00008000 .Lblock_userspace_access: .word _C_LABEL(block_userspace_access) /* * CPWAIT -- Canonical method to wait for CP15 update. * From: Intel 80200 manual, section 2.3.3. * * NOTE: Clobbers the specified temp reg. */ #define CPWAIT_BRANCH \ sub pc, pc, #4 #define CPWAIT(tmp) \ mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ CPWAIT_BRANCH /* branch to next insn */ #define CPWAIT_AND_RETURN_SHIFTER lsr #32 #define CPWAIT_AND_RETURN(tmp) \ mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ /* Wait for it to complete and branch to the return address */ \ sub pc, lr, tmp, CPWAIT_AND_RETURN_SHIFTER #define ARM_USE_L2_CACHE #define L2_CACHE_SIZE 0x80000 #define L2_CACHE_WAYS 8 #define L2_CACHE_LINE_SIZE 32 #define L2_CACHE_SETS (L2_CACHE_SIZE / \ (L2_CACHE_WAYS * L2_CACHE_LINE_SIZE)) #define L1_DCACHE_SIZE 32 * 1024 #define L1_DCACHE_WAYS 4 #define L1_DCACHE_LINE_SIZE 32 #define L1_DCACHE_SETS (L1_DCACHE_SIZE / \ (L1_DCACHE_WAYS * L1_DCACHE_LINE_SIZE)) #ifdef CACHE_CLEAN_BLOCK_INTR #define XSCALE_CACHE_CLEAN_BLOCK \ stmfd sp!, {r4} ; \ mrs r4, cpsr ; \ - orr r0, r4, #(I32_bit | F32_bit) ; \ + orr r0, r4, #(PSR_I | PSR_F) ; \ msr cpsr_fsxc, r0 #define XSCALE_CACHE_CLEAN_UNBLOCK \ msr cpsr_fsxc, r4 ; \ ldmfd sp!, {r4} #else #define XSCALE_CACHE_CLEAN_BLOCK \ stmfd sp!, {r4} ; \ ldr r4, .Lblock_userspace_access ; \ ldr ip, [r4] ; \ orr r0, ip, #1 ; \ str r0, [r4] #define XSCALE_CACHE_CLEAN_UNBLOCK \ str ip, [r3] ; \ ldmfd sp!, {r4} #endif /* CACHE_CLEAN_BLOCK_INTR */ ENTRY_NP(xscalec3_cache_syncI) xscalec3_cache_purgeID: EENTRY_NP(xscalec3_cache_purgeID) mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */ EENTRY_NP(xscalec3_cache_cleanID) EENTRY_NP(xscalec3_cache_purgeD) EENTRY(xscalec3_cache_cleanD) XSCALE_CACHE_CLEAN_BLOCK mov r0, #0 1: mov r1, r0, asl #30 mov r2, #0 2: orr r3, r1, r2, asl #5 mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */ add r2, r2, #1 cmp r2, #L1_DCACHE_SETS bne 2b add r0, r0, #1 cmp r0, #4 bne 1b CPWAIT(r0) XSCALE_CACHE_CLEAN_UNBLOCK mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ RET EEND(xscalec3_cache_purgeID) EEND(xscalec3_cache_cleanID) EEND(xscalec3_cache_purgeD) EEND(xscalec3_cache_cleanD) END(xscalec3_cache_syncI) ENTRY(xscalec3_cache_purgeID_rng) cmp r1, #0x4000 bcs _C_LABEL(xscalec3_cache_cleanID) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */ nop mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) END(xscalec3_cache_purgeID_rng) ENTRY(xscalec3_cache_syncI_rng) cmp r1, #0x4000 bcs _C_LABEL(xscalec3_cache_syncI) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) END(xscalec3_cache_syncI_rng) ENTRY(xscalec3_cache_purgeD_rng) cmp r1, #0x4000 bcs _C_LABEL(xscalec3_cache_cleanID) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c14, 1 /* Clean and invalidate D cache entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) END(xscalec3_cache_purgeD_rng) ENTRY(xscalec3_cache_cleanID_rng) EENTRY(xscalec3_cache_cleanD_rng) cmp r1, #0x4000 bcs _C_LABEL(xscalec3_cache_cleanID) and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 0, r0, c7, c10, 1 /* clean L1 D cache entry */ nop add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ CPWAIT_AND_RETURN(r0) EEND(xscalec3_cache_cleanD_rng) END(xscalec3_cache_cleanID_rng) ENTRY(xscalec3_l2cache_purge) /* Clean-up the L2 cache */ mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */ mov r0, #0 1: mov r1, r0, asl #29 mov r2, #0 2: orr r3, r1, r2, asl #5 mcr p15, 1, r3, c7, c15, 2 add r2, r2, #1 cmp r2, #L2_CACHE_SETS bne 2b add r0, r0, #1 cmp r0, #8 bne 1b mcr p15, 0, r0, c7, c10, 4 @ data write barrier CPWAIT(r0) mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */ RET END(xscalec3_l2cache_purge) ENTRY(xscalec3_l2cache_clean_rng) mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */ and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 1, r0, c7, c11, 1 /* Clean L2 D cache entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 CPWAIT_AND_RETURN(r0) END(xscalec3_l2cache_clean_rng) ENTRY(xscalec3_l2cache_purge_rng) mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */ and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 1, r0, c7, c11, 1 /* Clean L2 D cache entry */ mcr p15, 1, r0, c7, c7, 1 /* Invalidate L2 D cache entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 CPWAIT_AND_RETURN(r0) END(xscalec3_l2cache_purge_rng) ENTRY(xscalec3_l2cache_flush_rng) mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */ and r2, r0, #0x1f add r1, r1, r2 bic r0, r0, #0x1f 1: mcr p15, 1, r0, c7, c7, 1 /* Invalidate L2 cache line */ add r0, r0, #32 subs r1, r1, #32 bhi 1b mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 CPWAIT_AND_RETURN(r0) END(xscalec3_l2cache_flush_rng) /* * Functions to set the MMU Translation Table Base register * * We need to clean and flush the cache as it uses virtual * addresses that are about to change. */ ENTRY(xscalec3_setttb) #ifdef CACHE_CLEAN_BLOCK_INTR mrs r3, cpsr - orr r1, r3, #(I32_bit | F32_bit) + orr r1, r3, #(PSR_I | PSR_F) msr cpsr_fsxc, r1 #else ldr r3, .Lblock_userspace_access ldr r2, [r3] orr r1, r2, #1 str r1, [r3] #endif stmfd sp!, {r0-r3, lr} bl _C_LABEL(xscalec3_cache_cleanID) mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */ CPWAIT(r0) ldmfd sp!, {r0-r3, lr} #ifdef ARM_USE_L2_CACHE orr r0, r0, #0x18 /* cache the page table in L2 */ #endif /* Write the TTB */ mcr p15, 0, r0, c2, c0, 0 /* If we have updated the TTB we must flush the TLB */ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */ CPWAIT(r0) #ifdef CACHE_CLEAN_BLOCK_INTR msr cpsr_fsxc, r3 #else str r2, [r3] #endif RET END(xscalec3_setttb) /* * Context switch. * * These is the CPU-specific parts of the context switcher cpu_switch() * These functions actually perform the TTB reload. * * NOTE: Special calling convention * r1, r4-r13 must be preserved */ ENTRY(xscalec3_context_switch) /* * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this. * Thus the data cache will contain only kernel data and the * instruction cache will contain only kernel code, and all * kernel mappings are shared by all processes. */ #ifdef ARM_USE_L2_CACHE orr r0, r0, #0x18 /* Cache the page table in L2 */ #endif /* Write the TTB */ mcr p15, 0, r0, c2, c0, 0 /* If we have updated the TTB we must flush the TLB */ mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ CPWAIT_AND_RETURN(r0) END(xscalec3_context_switch) Index: head/sys/arm/arm/exception.S =================================================================== --- head/sys/arm/arm/exception.S (revision 271397) +++ head/sys/arm/arm/exception.S (revision 271398) @@ -1,463 +1,463 @@ /* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */ /*- * Copyright (c) 1994-1997 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * exception.S * * Low level handlers for exception vectors * * Created : 24/09/94 * * Based on kate/display/abort.s * */ #include "assym.s" #include #include #include __FBSDID("$FreeBSD$"); .text .align 0 /* * ASM macros for pushing and pulling trapframes from the stack * * These macros are used to handle the irqframe and trapframe structures * defined above. */ /* * PUSHFRAME - macro to push a trap frame on the stack in the current mode * Since the current mode is used, the SVC lr field is not defined. * * NOTE: r13 and r14 are stored separately as a work around for the * SA110 rev 2 STM^ bug */ #ifdef ARM_TP_ADDRESS #define PUSHFRAME \ sub sp, sp, #4; /* Align the stack */ \ str lr, [sp, #-4]!; /* Push the return address */ \ sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ stmia sp, {r0-r12}; /* Push the user mode registers */ \ add r0, sp, #(4*13); /* Adjust the stack pointer */ \ stmia r0, {r13-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ mrs r0, spsr; /* Put the SPSR on the stack */ \ str r0, [sp, #-4]!; \ ldr r0, =ARM_RAS_START; \ mov r1, #0; \ str r1, [r0]; \ mov r1, #0xffffffff; \ str r1, [r0, #4]; #else #define PUSHFRAME \ sub sp, sp, #4; /* Align the stack */ \ str lr, [sp, #-4]!; /* Push the return address */ \ sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ stmia sp, {r0-r12}; /* Push the user mode registers */ \ add r0, sp, #(4*13); /* Adjust the stack pointer */ \ stmia r0, {r13-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ mrs r0, spsr; /* Put the SPSR on the stack */ \ str r0, [sp, #-4]!; #endif /* * PULLFRAME - macro to pull a trap frame from the stack in the current mode * Since the current mode is used, the SVC lr field is ignored. */ #ifdef ARM_TP_ADDRESS #define PULLFRAME \ ldr r0, [sp], #4; /* Get the SPSR from stack */ \ msr spsr_fsxc, r0; \ ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ mov r0, r0; /* NOP for previous instruction */ \ add sp, sp, #(4*17); /* Adjust the stack pointer */ \ ldr lr, [sp], #4; /* Pull the return address */ \ add sp, sp, #4 /* Align the stack */ #else #define PULLFRAME \ ldr r0, [sp], #4 ; /* Get the SPSR from stack */ \ msr spsr_fsxc, r0; \ clrex; \ ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ mov r0, r0; /* NOP for previous instruction */ \ add sp, sp, #(4*17); /* Adjust the stack pointer */ \ ldr lr, [sp], #4; /* Pull the return address */ \ add sp, sp, #4 /* Align the stack */ #endif /* * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode * This should only be used if the processor is not currently in SVC32 * mode. The processor mode is switched to SVC mode and the trap frame is * stored. The SVC lr field is used to store the previous value of * lr in SVC mode. * * NOTE: r13 and r14 are stored separately as a work around for the * SA110 rev 2 STM^ bug */ #ifdef ARM_TP_ADDRESS #define PUSHFRAMEINSVC \ stmdb sp, {r0-r3}; /* Save 4 registers */ \ mov r0, lr; /* Save xxx32 r14 */ \ mov r1, sp; /* Save xxx32 sp */ \ mrs r3, spsr; /* Save xxx32 spsr */ \ mrs r2, cpsr; /* Get the CPSR */ \ bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ orr r2, r2, #(PSR_SVC32_MODE); \ msr cpsr_c, r2; /* Punch into SVC mode */ \ mov r2, sp; /* Save SVC sp */ \ bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ sub sp, sp, #4; /* Pad trapframe to keep alignment */ \ str r0, [sp, #-4]!; /* Push return address */ \ str lr, [sp, #-4]!; /* Push SVC lr */ \ str r2, [sp, #-4]!; /* Push SVC sp */ \ msr spsr_fsxc, r3; /* Restore correct spsr */ \ ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ stmia sp, {r0-r12}; /* Push the user mode registers */ \ add r0, sp, #(4*13); /* Adjust the stack pointer */ \ stmia r0, {r13-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \ ldr r4, [r5, #4]; /* reset it to point at the */ \ cmp r4, #0xffffffff; /* end of memory if necessary; */ \ movne r1, #0xffffffff; /* leave value in r4 for later */ \ strne r1, [r5, #4]; /* comparision against PC. */ \ ldr r3, [r5]; /* Retrieve global RAS_START */ \ cmp r3, #0; /* and reset it if non-zero. */ \ movne r1, #0; /* If non-zero RAS_START and */ \ strne r1, [r5]; /* PC was lower than RAS_END, */ \ ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \ cmpne r4, r1; /* execution later resumes at */ \ strhi r3, [r0, #16]; /* the RAS_START location. */ \ mrs r0, spsr; \ str r0, [sp, #-4]! #else #define PUSHFRAMEINSVC \ stmdb sp, {r0-r3}; /* Save 4 registers */ \ mov r0, lr; /* Save xxx32 r14 */ \ mov r1, sp; /* Save xxx32 sp */ \ mrs r3, spsr; /* Save xxx32 spsr */ \ mrs r2, cpsr; /* Get the CPSR */ \ bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ orr r2, r2, #(PSR_SVC32_MODE); \ msr cpsr_c, r2; /* Punch into SVC mode */ \ mov r2, sp; /* Save SVC sp */ \ bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ sub sp, sp, #4; /* Pad trapframe to keep alignment */ \ str r0, [sp, #-4]!; /* Push return address */ \ str lr, [sp, #-4]!; /* Push SVC lr */ \ str r2, [sp, #-4]!; /* Push SVC sp */ \ msr spsr_fsxc, r3; /* Restore correct spsr */ \ ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ stmia sp, {r0-r12}; /* Push the user mode registers */ \ add r0, sp, #(4*13); /* Adjust the stack pointer */ \ stmia r0, {r13-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ mrs r0, spsr; /* Put the SPSR on the stack */ \ str r0, [sp, #-4]! #endif /* * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack * in SVC32 mode and restore the saved processor mode and PC. * This should be used when the SVC lr register needs to be restored on * exit. */ #ifdef ARM_TP_ADDRESS #define PULLFRAMEFROMSVCANDEXIT \ ldr r0, [sp], #4; /* Get the SPSR from stack */ \ msr spsr_fsxc, r0; /* restore SPSR */ \ ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ mov r0, r0; /* NOP for previous instruction */ \ add sp, sp, #(4*15); /* Adjust the stack pointer */ \ ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ #else #define PULLFRAMEFROMSVCANDEXIT \ ldr r0, [sp], #4; /* Get the SPSR from stack */ \ msr spsr_fsxc, r0; /* restore SPSR */ \ clrex; \ ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ mov r0, r0; /* NOP for previous instruction */ \ add sp, sp, #(4*15); /* Adjust the stack pointer */ \ ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ #endif #if defined(__ARM_EABI__) /* * Unwind hints so we can unwind past functions that use * PULLFRAMEFROMSVCANDEXIT. They are run in reverse order. * As the last thing we do is restore the stack pointer * we can ignore the padding at the end of struct trapframe. */ #define UNWINDSVCFRAME \ .save {r13-r15}; /* Restore sp, lr, pc */ \ .pad #(2*4); /* Skip user sp and lr */ \ .save {r0-r12}; /* Restore r0-r12 */ \ .pad #(4) /* Skip spsr */ #else #define UNWINDSVCFRAME #endif #define DO_AST \ ldr r0, [sp] /* Get the SPSR from stack */ ;\ mrs r4, cpsr /* save CPSR */ ;\ - orr r1, r4, #(I32_bit|F32_bit) ;\ + orr r1, r4, #(PSR_I|PSR_F) ;\ msr cpsr_c, r1 /* Disable interrupts */ ;\ and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ teq r0, #(PSR_USR32_MODE) ;\ bne 2f /* Nope, get out now */ ;\ - bic r4, r4, #(I32_bit|F32_bit) ;\ + bic r4, r4, #(PSR_I|PSR_F) ;\ 1: GET_CURTHREAD_PTR(r5) ;\ ldr r1, [r5, #(TD_FLAGS)] ;\ and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED) ;\ teq r1, #0x00000000 ;\ beq 2f /* Nope. Just bail */ ;\ msr cpsr_c, r4 /* Restore interrupts */ ;\ mov r0, sp ;\ bl _C_LABEL(ast) /* ast(frame) */ ;\ - orr r0, r4, #(I32_bit|F32_bit) ;\ + orr r0, r4, #(PSR_I|PSR_F) ;\ msr cpsr_c, r0 ;\ b 1b ;\ 2: /* * Entry point for a Software Interrupt (SWI). * * The hardware switches to svc32 mode on a swi, so we're already on the * right stack; just build a trapframe and call the handler. */ ASENTRY_NP(swi_entry) PUSHFRAME /* Build the trapframe on the */ mov r0, sp /* scv32 stack, pass it to the */ bl _C_LABEL(swi_handler) /* swi handler. */ /* * The fork_trampoline() code in swtch.S aranges for the MI fork_exit() * to return to swi_exit here, to return to userland. The net effect is * that a newly created thread appears to return from a SWI just like * the parent thread that created it. */ ASEENTRY_NP(swi_exit) DO_AST /* Handle pending signals. */ PULLFRAME /* Deallocate trapframe. */ movs pc, lr /* Return to userland. */ STOP_UNWINDING /* Don't unwind into user mode. */ EEND(swi_exit) END(swi_entry) /* * Standard exception exit handler. * * This is used to return from all exceptions except SWI. It uses DO_AST and * PULLFRAMEFROMSVCANDEXIT and can only be called if the exception entry code * used PUSHFRAMEINSVC. * * If the return is to user mode, this uses DO_AST to deliver any pending * signals and/or handle TDF_NEEDRESCHED first. */ ASENTRY_NP(exception_exit) DO_AST /* Handle pending signals. */ PULLFRAMEFROMSVCANDEXIT /* Return. */ UNWINDSVCFRAME /* Special unwinding for exceptions. */ END(exception_exit) /* * Entry point for a Prefetch Abort exception. * * The hardware switches to the abort mode stack; we switch to svc32 before * calling the handler, then return directly to the original mode/stack * on exit (without transitioning back through the abort mode stack). */ ASENTRY_NP(prefetch_abort_entry) #ifdef __XSCALE__ nop /* Make absolutely sure any pending */ nop /* imprecise aborts have occurred. */ #endif sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ PUSHFRAMEINSVC /* mode stack, build trapframe there. */ adr lr, exception_exit /* Return from handler via standard */ mov r0, sp /* exception exit routine. Pass the */ b prefetch_abort_handler /* trapframe to the handler. */ END(prefetch_abort_entry) /* * Entry point for a Data Abort exception. * * The hardware switches to the abort mode stack; we switch to svc32 before * calling the handler, then return directly to the original mode/stack * on exit (without transitioning back through the abort mode stack). */ ASENTRY_NP(data_abort_entry) #ifdef __XSCALE__ nop /* Make absolutely sure any pending */ nop /* imprecise aborts have occurred. */ #endif sub lr, lr, #8 /* Adjust the lr. Transition to scv32 */ PUSHFRAMEINSVC /* mode stack, build trapframe there. */ adr lr, exception_exit /* Return from handler via standard */ mov r0, sp /* exception exit routine. Pass the */ b data_abort_handler /* trapframe to the handler. */ END(data_abort_entry) /* * Entry point for an Undefined Instruction exception. * * The hardware switches to the undefined mode stack; we switch to svc32 before * calling the handler, then return directly to the original mode/stack * on exit (without transitioning back through the undefined mode stack). */ ASENTRY_NP(undefined_entry) sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ PUSHFRAMEINSVC /* mode stack, build trapframe there. */ adr lr, exception_exit /* Return from handler via standard */ mov r0, sp /* exception exit routine. Pass the */ b undefinedinstruction /* trapframe to the handler. */ END(undefined_entry) /* * Entry point for a normal IRQ. * * The hardware switches to the IRQ mode stack; we switch to svc32 before * calling the handler, then return directly to the original mode/stack * on exit (without transitioning back through the IRQ mode stack). */ ASENTRY_NP(irq_entry) sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ PUSHFRAMEINSVC /* mode stack, build trapframe there. */ adr lr, exception_exit /* Return from handler via standard */ mov r0, sp /* exception exit routine. Pass the */ b _C_LABEL(arm_irq_handler)/* trapframe to the handler. */ END(irq_entry) /* * Entry point for an FIQ interrupt. * * We don't currently support FIQ handlers very much. Something can * install itself in the FIQ vector using code (that may or may not work * these days) in fiq.c. If nobody does that and an FIQ happens, this * default handler just disables FIQs and otherwise ignores it. */ ASENTRY_NP(fiq_entry) mrs r8, cpsr /* FIQ handling isn't supported, */ - bic r8, #(F32_bit) /* just disable FIQ and return. */ + bic r8, #(PSR_F) /* just disable FIQ and return. */ msr cpsr_c, r8 /* The r8 we trash here is the */ subs pc, lr, #4 /* banked FIQ-mode r8. */ END(fiq_entry) /* * Entry point for an Address Exception exception. * This is an arm26 exception that should never happen. */ ASENTRY_NP(addr_exception_entry) mov r3, lr mrs r2, spsr mrs r1, cpsr adr r0, Laddr_exception_msg b _C_LABEL(panic) Laddr_exception_msg: .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n" .balign 4 END(addr_exception_entry) /* * Entry point for the system Reset vector. * This should never happen, so panic. */ ASENTRY_NP(reset_entry) mov r1, lr adr r0, Lreset_panicmsg b _C_LABEL(panic) /* NOTREACHED */ Lreset_panicmsg: .asciz "Reset vector called, LR = 0x%08x" .balign 4 END(reset_entry) /* * page0 and page0_data -- An image of the ARM vectors which is copied to * the ARM vectors page (high or low) as part of CPU initialization. The * code that does the copy assumes that page0_data holds one 32-bit word * of data for each of the predefined ARM vectors. It also assumes that * page0_data follows the vectors in page0, but other stuff can appear * between the two. We currently leave room between the two for some fiq * handler code to be copied in. */ .global _C_LABEL(page0), _C_LABEL(page0_data) _C_LABEL(page0): ldr pc, .Lreset_entry ldr pc, .Lundefined_entry ldr pc, .Lswi_entry ldr pc, .Lprefetch_abort_entry ldr pc, .Ldata_abort_entry ldr pc, .Laddr_exception_entry ldr pc, .Lirq_entry .fiqv: ldr pc, .Lfiq_entry .space 256 /* room for some fiq handler code */ _C_LABEL(page0_data): .Lreset_entry: .word reset_entry .Lundefined_entry: .word undefined_entry .Lswi_entry: .word swi_entry .Lprefetch_abort_entry: .word prefetch_abort_entry .Ldata_abort_entry: .word data_abort_entry .Laddr_exception_entry: .word addr_exception_entry .Lirq_entry: .word irq_entry .Lfiq_entry: .word fiq_entry /* * These items are used by the code in fiq.c to install what it calls the * "null" handler. It's actually our default vector entry that just jumps * to the default handler which just disables FIQs and returns. */ .global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size) _C_LABEL(fiq_nullhandler_code): .word .fiqv _C_LABEL(fiq_nullhandler_size): .word 4 Index: head/sys/arm/arm/fiq.c =================================================================== --- head/sys/arm/arm/fiq.c (revision 271397) +++ head/sys/arm/arm/fiq.c (revision 271398) @@ -1,174 +1,172 @@ /* $NetBSD: fiq.c,v 1.5 2002/04/03 23:33:27 thorpej Exp $ */ /*- * Copyright (c) 2001, 2002 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include +#include #include #include #include #include #include #include TAILQ_HEAD(, fiqhandler) fiqhandler_stack = TAILQ_HEAD_INITIALIZER(fiqhandler_stack); extern char *fiq_nullhandler_code; extern uint32_t fiq_nullhandler_size; -#define IRQ_BIT I32_bit -#define FIQ_BIT F32_bit - /* * fiq_installhandler: * * Actually install the FIQ handler down at the FIQ vector. * * The FIQ vector is fixed by the hardware definition as the * seventh 32-bit word in the vector page. * * Note: If the FIQ is invoked via an extra layer of * indirection, the actual FIQ code store lives in the * data segment, so there is no need to manipulate * the vector page's protection. */ static void fiq_installhandler(void *func, size_t size) { const uint32_t fiqvector = 7 * sizeof(uint32_t); #if !defined(__ARM_FIQ_INDIRECT) vector_page_setprot(VM_PROT_READ|VM_PROT_WRITE); #endif memcpy((void *)(vector_page + fiqvector), func, size); #if !defined(__ARM_FIQ_INDIRECT) vector_page_setprot(VM_PROT_READ); cpu_icache_sync_range((vm_offset_t) fiqvector, size); #endif } /* * fiq_claim: * * Claim the FIQ vector. */ int fiq_claim(struct fiqhandler *fh) { struct fiqhandler *ofh; u_int oldirqstate; int error = 0; if (fh->fh_size > 0x100) return (EFBIG); - oldirqstate = disable_interrupts(FIQ_BIT); + oldirqstate = disable_interrupts(PSR_F); if ((ofh = TAILQ_FIRST(&fiqhandler_stack)) != NULL) { if ((ofh->fh_flags & FH_CANPUSH) == 0) { error = EBUSY; goto out; } /* Save the previous FIQ handler's registers. */ if (ofh->fh_regs != NULL) fiq_getregs(ofh->fh_regs); } /* Set FIQ mode registers to ours. */ if (fh->fh_regs != NULL) fiq_setregs(fh->fh_regs); TAILQ_INSERT_HEAD(&fiqhandler_stack, fh, fh_list); /* Now copy the actual handler into place. */ fiq_installhandler(fh->fh_func, fh->fh_size); /* Make sure FIQs are enabled when we return. */ - oldirqstate &= ~FIQ_BIT; + oldirqstate &= ~PSR_F; out: restore_interrupts(oldirqstate); return (error); } /* * fiq_release: * * Release the FIQ vector. */ void fiq_release(struct fiqhandler *fh) { u_int oldirqstate; struct fiqhandler *ofh; - oldirqstate = disable_interrupts(FIQ_BIT); + oldirqstate = disable_interrupts(PSR_F); /* * If we are the currently active FIQ handler, then we * need to save our registers and pop the next one back * into the vector. */ if (fh == TAILQ_FIRST(&fiqhandler_stack)) { if (fh->fh_regs != NULL) fiq_getregs(fh->fh_regs); TAILQ_REMOVE(&fiqhandler_stack, fh, fh_list); if ((ofh = TAILQ_FIRST(&fiqhandler_stack)) != NULL) { if (ofh->fh_regs != NULL) fiq_setregs(ofh->fh_regs); fiq_installhandler(ofh->fh_func, ofh->fh_size); } } else TAILQ_REMOVE(&fiqhandler_stack, fh, fh_list); if (TAILQ_FIRST(&fiqhandler_stack) == NULL) { /* Copy the NULL handler back down into the vector. */ fiq_installhandler(fiq_nullhandler_code, fiq_nullhandler_size); /* Make sure FIQs are disabled when we return. */ - oldirqstate |= FIQ_BIT; + oldirqstate |= PSR_F; } restore_interrupts(oldirqstate); } Index: head/sys/arm/arm/locore.S =================================================================== --- head/sys/arm/arm/locore.S (revision 271397) +++ head/sys/arm/arm/locore.S (revision 271398) @@ -1,578 +1,578 @@ /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */ /*- * Copyright 2011 Semihalf * Copyright (C) 1994-1997 Mark Brinicombe * Copyright (C) 1994 Brini * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of Brini may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include "assym.s" #include #include #include #include #include __FBSDID("$FreeBSD$"); /* What size should this really be ? It is only used by initarm() */ #define INIT_ARM_STACK_SIZE (2048 * 4) #define CPWAIT_BRANCH \ sub pc, pc, #4 #define CPWAIT(tmp) \ mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ CPWAIT_BRANCH /* branch to next insn */ /* * This is for kvm_mkdb, and should be the address of the beginning * of the kernel text segment (not necessarily the same as kernbase). */ .text .align 0 .globl kernbase .set kernbase,KERNBASE .globl physaddr .set physaddr,PHYSADDR /* * On entry for FreeBSD boot ABI: * r0 - metadata pointer or 0 (boothowto on AT91's boot2) * r1 - if (r0 == 0) then metadata pointer * On entry for Linux boot ABI: * r0 - 0 * r1 - machine type (passed as arg2 to initarm) * r2 - Pointer to a tagged list or dtb image (phys addr) (passed as arg1 initarm) * * For both types of boot we gather up the args, put them in a struct arm_boot_params * structure and pass that to initarm. */ .globl btext btext: ASENTRY_NP(_start) STOP_UNWINDING /* Can't unwind into the bootloader! */ mov r9, r0 /* 0 or boot mode from boot2 */ mov r8, r1 /* Save Machine type */ mov ip, r2 /* Save meta data */ mov fp, r3 /* Future expansion */ /* Make sure interrupts are disabled. */ mrs r7, cpsr - orr r7, r7, #(I32_bit|F32_bit) + orr r7, r7, #(PSR_I | PSR_F) msr cpsr_c, r7 #if defined (FLASHADDR) && defined(LOADERRAMADDR) /* Check if we're running from flash. */ ldr r7, =FLASHADDR /* * If we're running with MMU disabled, test against the * physical address instead. */ mrc p15, 0, r2, c1, c0, 0 ands r2, r2, #CPU_CONTROL_MMU_ENABLE ldreq r6, =PHYSADDR ldrne r6, =LOADERRAMADDR cmp r7, r6 bls flash_lower cmp r7, pc bhi from_ram b do_copy flash_lower: cmp r6, pc bls from_ram do_copy: ldr r7, =KERNBASE adr r1, _start ldr r0, Lreal_start ldr r2, Lend sub r2, r2, r0 sub r0, r0, r7 add r0, r0, r6 mov r4, r0 bl memcpy ldr r0, Lram_offset add pc, r4, r0 Lram_offset: .word from_ram-_C_LABEL(_start) from_ram: nop #endif disable_mmu: /* Disable MMU for a while */ mrc p15, 0, r2, c1, c0, 0 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\ CPU_CONTROL_WBUF_ENABLE) bic r2, r2, #(CPU_CONTROL_IC_ENABLE) bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE) mcr p15, 0, r2, c1, c0, 0 nop nop nop CPWAIT(r0) Lunmapped: /* * Build page table from scratch. */ /* Find the delta between VA and PA */ adr r0, Lpagetable bl translate_va_to_pa #ifndef _ARM_ARCH_6 /* * Some of the older ports (the various XScale, mostly) assume * that the memory before the kernel is mapped, and use it for * the various stacks, page tables, etc. For those CPUs, map the * 64 first MB of RAM, as it used to be. */ /* * Map PA == VA */ ldr r5, =PHYSADDR mov r1, r5 mov r2, r5 /* Map 64MiB, preserved over calls to build_pagetables */ mov r3, #64 bl build_pagetables /* Create the kernel map to jump to */ mov r1, r5 ldr r2, =(KERNBASE) bl build_pagetables ldr r5, =(KERNPHYSADDR) #else /* * Map PA == VA */ /* Find the start kernels load address */ adr r5, _start ldr r2, =(L1_S_OFFSET) bic r5, r2 mov r1, r5 mov r2, r5 /* Map 64MiB, preserved over calls to build_pagetables */ mov r3, #64 bl build_pagetables /* Create the kernel map to jump to */ mov r1, r5 ldr r2, =(KERNVIRTADDR) bl build_pagetables #endif #if defined(SOCDEV_PA) && defined(SOCDEV_VA) /* Create the custom map */ ldr r1, =SOCDEV_PA ldr r2, =SOCDEV_VA bl build_pagetables #endif #if defined(SMP) orr r0, r0, #2 /* Set TTB shared memory flag */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) mcr p15, 0, r0, c3, c0, 0 /* * Enable MMU. * On armv6 enable extended page tables, and set alignment checking * to modulo-4 (CPU_CONTROL_UNAL_ENABLE) for the ldrd/strd * instructions emitted by clang. */ mrc p15, 0, r0, c1, c0, 0 #ifdef _ARM_ARCH_6 orr r0, r0, #(CPU_CONTROL_V6_EXTPAGE | CPU_CONTROL_UNAL_ENABLE) orr r0, r0, #(CPU_CONTROL_AFLT_ENABLE) orr r0, r0, #(CPU_CONTROL_AF_ENABLE) #endif orr r0, r0, #(CPU_CONTROL_MMU_ENABLE) mcr p15, 0, r0, c1, c0, 0 nop nop nop CPWAIT(r0) mmu_done: nop adr r1, .Lstart ldmia r1, {r1, r2, sp} /* Set initial stack and */ sub r2, r2, r1 /* get zero init data */ mov r3, #0 .L1: str r3, [r1], #0x0004 /* get zero init data */ subs r2, r2, #4 bgt .L1 ldr pc, .Lvirt_done virt_done: mov r1, #28 /* loader info size is 28 bytes also second arg */ subs sp, sp, r1 /* allocate arm_boot_params struct on stack */ mov r0, sp /* loader info pointer is first arg */ bic sp, sp, #7 /* align stack to 8 bytes */ str r1, [r0] /* Store length of loader info */ str r9, [r0, #4] /* Store r0 from boot loader */ str r8, [r0, #8] /* Store r1 from boot loader */ str ip, [r0, #12] /* store r2 from boot loader */ str fp, [r0, #16] /* store r3 from boot loader */ str r5, [r0, #20] /* store the physical address */ adr r4, Lpagetable /* load the pagetable address */ ldr r5, [r4, #4] str r5, [r0, #24] /* store the pagetable address */ mov fp, #0 /* trace back starts here */ bl _C_LABEL(initarm) /* Off we go */ /* init arm will return the new stack pointer. */ mov sp, r0 bl _C_LABEL(mi_startup) /* call mi_startup()! */ adr r0, .Lmainreturned b _C_LABEL(panic) /* NOTREACHED */ END(_start) #define VA_TO_PA_POINTER(name, table) \ name: ;\ .word . ;\ .word table /* * Returns the physical address of a magic va to pa pointer. * r0 - The pagetable data pointer. This must be built using the * VA_TO_PA_POINTER macro. * e.g. * VA_TO_PA_POINTER(Lpagetable, pagetable) * ... * adr r0, Lpagetable * bl translate_va_to_pa * r0 will now contain the physical address of pagetable * r1, r2 - Trashed */ translate_va_to_pa: ldr r1, [r0] sub r2, r1, r0 /* At this point: r2 = VA - PA */ /* * Find the physical address of the table. After these two * instructions: * r1 = va(pagetable) * * r0 = va(pagetable) - (VA - PA) * = va(pagetable) - VA + PA * = pa(pagetable) */ ldr r1, [r0, #4] sub r0, r1, r2 RET /* * Builds the page table * r0 - The table base address * r1 - The physical address (trashed) * r2 - The virtual address (trashed) * r3 - The number of 1MiB sections * r4 - Trashed * * Addresses must be 1MiB aligned */ build_pagetables: /* Set the required page attributed */ ldr r4, =(L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) #if defined(SMP) orr r4, #(L1_SHARED) #endif orr r1, r4 /* Move the virtual address to the correct bit location */ lsr r2, #(L1_S_SHIFT - 2) mov r4, r3 1: str r1, [r0, r2] add r2, r2, #4 add r1, r1, #(L1_S_SIZE) adds r4, r4, #-1 bhi 1b RET VA_TO_PA_POINTER(Lpagetable, pagetable) Lreal_start: .word _start Lend: .word _edata .Lstart: .word _edata .word _ebss .word svcstk + INIT_ARM_STACK_SIZE .Lvirt_done: .word virt_done .Lmainreturned: .asciz "main() returned" .align 0 .bss svcstk: .space INIT_ARM_STACK_SIZE /* * Memory for the initial pagetable. We are unable to place this in * the bss as this will be cleared after the table is loaded. */ .section ".init_pagetable" .align 14 /* 16KiB aligned */ pagetable: .space L1_TABLE_SIZE .text .align 0 .Lcpufuncs: .word _C_LABEL(cpufuncs) #if defined(SMP) .Lmpvirt_done: .word mpvirt_done VA_TO_PA_POINTER(Lstartup_pagetable_secondary, temp_pagetable) ASENTRY_NP(mpentry) /* Make sure interrupts are disabled. */ mrs r7, cpsr - orr r7, r7, #(I32_bit|F32_bit) + orr r7, r7, #(PSR_I | PSR_F) msr cpsr_c, r7 /* Disable MMU. It should be disabled already, but make sure. */ mrc p15, 0, r2, c1, c0, 0 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\ CPU_CONTROL_WBUF_ENABLE) bic r2, r2, #(CPU_CONTROL_IC_ENABLE) bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE) mcr p15, 0, r2, c1, c0, 0 nop nop nop CPWAIT(r0) #if ARM_MMU_V6 bl armv6_idcache_inv_all /* Modifies r0 only */ #elif ARM_MMU_V7 bl armv7_idcache_inv_all /* Modifies r0-r3, ip */ #endif /* Load the page table physical address */ adr r0, Lstartup_pagetable_secondary bl translate_va_to_pa /* Load the address the secondary page table */ ldr r0, [r0] orr r0, r0, #2 /* Set TTB shared memory flag */ mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE orr r0, r0, #CPU_CONTROL_AF_ENABLE orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\ CPU_CONTROL_WBUF_ENABLE) orr r0, r0, #(CPU_CONTROL_IC_ENABLE) orr r0, r0, #(CPU_CONTROL_BPRD_ENABLE) mcr p15, 0, r0, c1, c0, 0 nop nop nop CPWAIT(r0) adr r1, .Lstart ldmia r1, {r1, r2, sp} /* Set initial stack and */ mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 mov r1, #2048 mul r2, r1, r0 sub sp, sp, r2 str r1, [sp] ldr pc, .Lmpvirt_done mpvirt_done: mov fp, #0 /* trace back starts here */ bl _C_LABEL(init_secondary) /* Off we go */ adr r0, .Lmpreturned b _C_LABEL(panic) /* NOTREACHED */ .Lmpreturned: .asciz "init_secondary() returned" .align 0 END(mpentry) #endif ENTRY_NP(cpu_halt) mrs r2, cpsr bic r2, r2, #(PSR_MODE) orr r2, r2, #(PSR_SVC32_MODE) - orr r2, r2, #(I32_bit | F32_bit) + orr r2, r2, #(PSR_I | PSR_F) msr cpsr_fsxc, r2 ldr r4, .Lcpu_reset_address ldr r4, [r4] ldr r0, .Lcpufuncs mov lr, pc ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] mov lr, pc ldr pc, [r0, #CF_L2CACHE_WBINV_ALL] /* * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's * necessary. */ ldr r1, .Lcpu_reset_needs_v4_MMU_disable ldr r1, [r1] cmp r1, #0 mov r2, #0 /* * MMU & IDC off, 32 bit program & data space * Hurl ourselves into the ROM */ mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) mcr 15, 0, r0, c1, c0, 0 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ mov pc, r4 /* * _cpu_reset_address contains the address to branch to, to complete * the cpu reset after turning the MMU off * This variable is provided by the hardware specific code */ .Lcpu_reset_address: .word _C_LABEL(cpu_reset_address) /* * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the * v4 MMU disable instruction needs executing... it is an illegal instruction * on f.e. ARM6/7 that locks up the computer in an endless illegal * instruction / data-abort / reset loop. */ .Lcpu_reset_needs_v4_MMU_disable: .word _C_LABEL(cpu_reset_needs_v4_MMU_disable) END(cpu_halt) /* * setjump + longjmp */ ENTRY(setjmp) stmia r0, {r4-r14} mov r0, #0x00000000 RET END(setjmp) ENTRY(longjmp) ldmia r0, {r4-r14} mov r0, #0x00000001 RET END(longjmp) .data .global _C_LABEL(esym) _C_LABEL(esym): .word _C_LABEL(end) ENTRY_NP(abort) b _C_LABEL(abort) END(abort) ENTRY_NP(sigcode) mov r0, sp add r0, r0, #SIGF_UC /* * Call the sigreturn system call. * * We have to load r7 manually rather than using * "ldr r7, =SYS_sigreturn" to ensure the value of szsigcode is * correct. Using the alternative places esigcode at the address * of the data rather than the address one past the data. */ ldr r7, [pc, #12] /* Load SYS_sigreturn */ swi SYS_sigreturn /* Well if that failed we better exit quick ! */ ldr r7, [pc, #8] /* Load SYS_exit */ swi SYS_exit /* Branch back to retry SYS_sigreturn */ b . - 16 END(sigcode) .word SYS_sigreturn .word SYS_exit .align 0 .global _C_LABEL(esigcode) _C_LABEL(esigcode): .data .global szsigcode szsigcode: .long esigcode-sigcode /* End of locore.S */ Index: head/sys/arm/arm/machdep.c =================================================================== --- head/sys/arm/arm/machdep.c (revision 271397) +++ head/sys/arm/arm/machdep.c (revision 271398) @@ -1,1305 +1,1305 @@ /* $NetBSD: arm32_machdep.c,v 1.44 2004/03/24 15:34:47 atatat Exp $ */ /*- * Copyright (c) 2004 Olivier Houchard * Copyright (c) 1994-1998 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Mark Brinicombe * for the NetBSD Project. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Machine dependant functions for kernel setup * * Created : 17/09/94 * Updated : 18/04/01 updated for new wscons */ #include "opt_compat.h" #include "opt_ddb.h" #include "opt_platform.h" #include "opt_sched.h" #include "opt_timer.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #endif #ifdef DEBUG #define debugf(fmt, args...) printf(fmt, ##args) #else #define debugf(fmt, args...) #endif struct pcpu __pcpu[MAXCPU]; struct pcpu *pcpup = &__pcpu[0]; static struct trapframe proc0_tf; uint32_t cpu_reset_address = 0; int cold = 1; vm_offset_t vector_page; int (*_arm_memcpy)(void *, void *, int, int) = NULL; int (*_arm_bzero)(void *, int, int) = NULL; int _min_memcpy_size = 0; int _min_bzero_size = 0; extern int *end; #ifdef DDB extern vm_offset_t ksym_start, ksym_end; #endif #ifdef FDT /* * This is the number of L2 page tables required for covering max * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf, * stacks etc.), uprounded to be divisible by 4. */ #define KERNEL_PT_MAX 78 static struct pv_addr kernel_pt_table[KERNEL_PT_MAX]; vm_paddr_t pmap_pa; struct pv_addr systempage; static struct pv_addr msgbufpv; struct pv_addr irqstack; struct pv_addr undstack; struct pv_addr abtstack; static struct pv_addr kernelstack; #endif #if defined(LINUX_BOOT_ABI) #define LBABI_MAX_BANKS 10 uint32_t board_id; struct arm_lbabi_tag *atag_list; char linux_command_line[LBABI_MAX_COMMAND_LINE + 1]; char atags[LBABI_MAX_COMMAND_LINE * 2]; uint32_t memstart[LBABI_MAX_BANKS]; uint32_t memsize[LBABI_MAX_BANKS]; uint32_t membanks; #endif static uint32_t board_revision; /* hex representation of uint64_t */ static char board_serial[32]; SYSCTL_NODE(_hw, OID_AUTO, board, CTLFLAG_RD, 0, "Board attributes"); SYSCTL_UINT(_hw_board, OID_AUTO, revision, CTLFLAG_RD, &board_revision, 0, "Board revision"); SYSCTL_STRING(_hw_board, OID_AUTO, serial, CTLFLAG_RD, board_serial, 0, "Board serial"); int vfp_exists; SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, &vfp_exists, 0, "Floating point support enabled"); void board_set_serial(uint64_t serial) { snprintf(board_serial, sizeof(board_serial)-1, "%016jx", serial); } void board_set_revision(uint32_t revision) { board_revision = revision; } void sendsig(catcher, ksi, mask) sig_t catcher; ksiginfo_t *ksi; sigset_t *mask; { struct thread *td; struct proc *p; struct trapframe *tf; struct sigframe *fp, frame; struct sigacts *psp; int onstack; int sig; int code; td = curthread; p = td->td_proc; PROC_LOCK_ASSERT(p, MA_OWNED); sig = ksi->ksi_signo; code = ksi->ksi_code; psp = p->p_sigacts; mtx_assert(&psp->ps_mtx, MA_OWNED); tf = td->td_frame; onstack = sigonstack(tf->tf_usr_sp); CTR4(KTR_SIG, "sendsig: td=%p (%s) catcher=%p sig=%d", td, p->p_comm, catcher, sig); /* Allocate and validate space for the signal handler context. */ if ((td->td_pflags & TDP_ALTSTACK) != 0 && !(onstack) && SIGISMEMBER(psp->ps_sigonstack, sig)) { fp = (struct sigframe *)(td->td_sigstk.ss_sp + td->td_sigstk.ss_size); #if defined(COMPAT_43) td->td_sigstk.ss_flags |= SS_ONSTACK; #endif } else fp = (struct sigframe *)td->td_frame->tf_usr_sp; /* make room on the stack */ fp--; /* make the stack aligned */ fp = (struct sigframe *)STACKALIGN(fp); /* Populate the siginfo frame. */ get_mcontext(td, &frame.sf_uc.uc_mcontext, 0); frame.sf_si = ksi->ksi_info; frame.sf_uc.uc_sigmask = *mask; frame.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK ) ? ((onstack) ? SS_ONSTACK : 0) : SS_DISABLE; frame.sf_uc.uc_stack = td->td_sigstk; mtx_unlock(&psp->ps_mtx); PROC_UNLOCK(td->td_proc); /* Copy the sigframe out to the user's stack. */ if (copyout(&frame, fp, sizeof(*fp)) != 0) { /* Process has trashed its stack. Kill it. */ CTR2(KTR_SIG, "sendsig: sigexit td=%p fp=%p", td, fp); PROC_LOCK(p); sigexit(td, SIGILL); } /* Translate the signal if appropriate. */ if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; /* * Build context to run handler in. We invoke the handler * directly, only returning via the trampoline. Note the * trampoline version numbers are coordinated with machine- * dependent code in libc. */ tf->tf_r0 = sig; tf->tf_r1 = (register_t)&fp->sf_si; tf->tf_r2 = (register_t)&fp->sf_uc; /* the trampoline uses r5 as the uc address */ tf->tf_r5 = (register_t)&fp->sf_uc; tf->tf_pc = (register_t)catcher; tf->tf_usr_sp = (register_t)fp; tf->tf_usr_lr = (register_t)(PS_STRINGS - *(p->p_sysent->sv_szsigcode)); CTR3(KTR_SIG, "sendsig: return td=%p pc=%#x sp=%#x", td, tf->tf_usr_lr, tf->tf_usr_sp); PROC_LOCK(p); mtx_lock(&psp->ps_mtx); } struct kva_md_info kmi; /* * arm32_vector_init: * * Initialize the vector page, and select whether or not to * relocate the vectors. * * NOTE: We expect the vector page to be mapped at its expected * destination. */ extern unsigned int page0[], page0_data[]; void arm_vector_init(vm_offset_t va, int which) { unsigned int *vectors = (int *) va; unsigned int *vectors_data = vectors + (page0_data - page0); int vec; /* * Loop through the vectors we're taking over, and copy the * vector's insn and data word. */ for (vec = 0; vec < ARM_NVEC; vec++) { if ((which & (1 << vec)) == 0) { /* Don't want to take over this vector. */ continue; } vectors[vec] = page0[vec]; vectors_data[vec] = page0_data[vec]; } /* Now sync the vectors. */ cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int)); vector_page = va; if (va == ARM_VECTORS_HIGH) { /* * Assume the MD caller knows what it's doing here, and * really does want the vector page relocated. * * Note: This has to be done here (and not just in * cpu_setup()) because the vector page needs to be * accessible *before* cpu_startup() is called. * Think ddb(9) ... * * NOTE: If the CPU control register is not readable, * this will totally fail! We'll just assume that * any system that has high vector support has a * readable CPU control register, for now. If we * ever encounter one that does not, we'll have to * rethink this. */ cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC); } } static void cpu_startup(void *dummy) { struct pcb *pcb = thread0.td_pcb; const unsigned int mbyte = 1024 * 1024; #ifdef ARM_TP_ADDRESS #ifndef ARM_CACHE_LOCK_ENABLE vm_page_t m; #endif #endif identify_arm_cpu(); vm_ksubmap_init(&kmi); /* * Display the RAM layout. */ printf("real memory = %ju (%ju MB)\n", (uintmax_t)arm32_ptob(realmem), (uintmax_t)arm32_ptob(realmem) / mbyte); printf("avail memory = %ju (%ju MB)\n", (uintmax_t)arm32_ptob(vm_cnt.v_free_count), (uintmax_t)arm32_ptob(vm_cnt.v_free_count) / mbyte); if (bootverbose) { arm_physmem_print_tables(); arm_devmap_print_table(); } bufinit(); vm_pager_bufferinit(); pcb->un_32.pcb32_sp = (u_int)thread0.td_kstack + USPACE_SVC_STACK_TOP; vector_page_setprot(VM_PROT_READ); pmap_set_pcb_pagedir(pmap_kernel(), pcb); pmap_postinit(); #ifdef ARM_TP_ADDRESS #ifdef ARM_CACHE_LOCK_ENABLE pmap_kenter_user(ARM_TP_ADDRESS, ARM_TP_ADDRESS); arm_lock_cache_line(ARM_TP_ADDRESS); #else m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_ZERO); pmap_kenter_user(ARM_TP_ADDRESS, VM_PAGE_TO_PHYS(m)); #endif *(uint32_t *)ARM_RAS_START = 0; *(uint32_t *)ARM_RAS_END = 0xffffffff; #endif } SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); /* * Flush the D-cache for non-DMA I/O so that the I-cache can * be made coherent later. */ void cpu_flush_dcache(void *ptr, size_t len) { cpu_dcache_wb_range((uintptr_t)ptr, len); #ifdef ARM_L2_PIPT cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len); #else cpu_l2cache_wb_range((uintptr_t)ptr, len); #endif } /* Get current clock frequency for the given cpu id. */ int cpu_est_clockrate(int cpu_id, uint64_t *rate) { return (ENXIO); } void cpu_idle(int busy) { CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", busy, curcpu); spinlock_enter(); #ifndef NO_EVENTTIMERS if (!busy) cpu_idleclock(); #endif if (!sched_runnable()) cpu_sleep(0); #ifndef NO_EVENTTIMERS if (!busy) cpu_activeclock(); #endif spinlock_exit(); CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", busy, curcpu); } int cpu_idle_wakeup(int cpu) { return (0); } /* * Most ARM platforms don't need to do anything special to init their clocks * (they get intialized during normal device attachment), and by not defining a * cpu_initclocks() function they get this generic one. Any platform that needs * to do something special can just provide their own implementation, which will * override this one due to the weak linkage. */ void arm_generic_initclocks(void) { #ifndef NO_EVENTTIMERS #ifdef SMP if (PCPU_GET(cpuid) == 0) cpu_initclocks_bsp(); else cpu_initclocks_ap(); #else cpu_initclocks_bsp(); #endif #endif } __weak_reference(arm_generic_initclocks, cpu_initclocks); int fill_regs(struct thread *td, struct reg *regs) { struct trapframe *tf = td->td_frame; bcopy(&tf->tf_r0, regs->r, sizeof(regs->r)); regs->r_sp = tf->tf_usr_sp; regs->r_lr = tf->tf_usr_lr; regs->r_pc = tf->tf_pc; regs->r_cpsr = tf->tf_spsr; return (0); } int fill_fpregs(struct thread *td, struct fpreg *regs) { bzero(regs, sizeof(*regs)); return (0); } int set_regs(struct thread *td, struct reg *regs) { struct trapframe *tf = td->td_frame; bcopy(regs->r, &tf->tf_r0, sizeof(regs->r)); tf->tf_usr_sp = regs->r_sp; tf->tf_usr_lr = regs->r_lr; tf->tf_pc = regs->r_pc; tf->tf_spsr &= ~PSR_FLAGS; tf->tf_spsr |= regs->r_cpsr & PSR_FLAGS; return (0); } int set_fpregs(struct thread *td, struct fpreg *regs) { return (0); } int fill_dbregs(struct thread *td, struct dbreg *regs) { return (0); } int set_dbregs(struct thread *td, struct dbreg *regs) { return (0); } static int ptrace_read_int(struct thread *td, vm_offset_t addr, u_int32_t *v) { struct iovec iov; struct uio uio; PROC_LOCK_ASSERT(td->td_proc, MA_NOTOWNED); iov.iov_base = (caddr_t) v; iov.iov_len = sizeof(u_int32_t); uio.uio_iov = &iov; uio.uio_iovcnt = 1; uio.uio_offset = (off_t)addr; uio.uio_resid = sizeof(u_int32_t); uio.uio_segflg = UIO_SYSSPACE; uio.uio_rw = UIO_READ; uio.uio_td = td; return proc_rwmem(td->td_proc, &uio); } static int ptrace_write_int(struct thread *td, vm_offset_t addr, u_int32_t v) { struct iovec iov; struct uio uio; PROC_LOCK_ASSERT(td->td_proc, MA_NOTOWNED); iov.iov_base = (caddr_t) &v; iov.iov_len = sizeof(u_int32_t); uio.uio_iov = &iov; uio.uio_iovcnt = 1; uio.uio_offset = (off_t)addr; uio.uio_resid = sizeof(u_int32_t); uio.uio_segflg = UIO_SYSSPACE; uio.uio_rw = UIO_WRITE; uio.uio_td = td; return proc_rwmem(td->td_proc, &uio); } int ptrace_single_step(struct thread *td) { struct proc *p; int error; KASSERT(td->td_md.md_ptrace_instr == 0, ("Didn't clear single step")); p = td->td_proc; PROC_UNLOCK(p); error = ptrace_read_int(td, td->td_frame->tf_pc + 4, &td->td_md.md_ptrace_instr); if (error) goto out; error = ptrace_write_int(td, td->td_frame->tf_pc + 4, PTRACE_BREAKPOINT); if (error) td->td_md.md_ptrace_instr = 0; td->td_md.md_ptrace_addr = td->td_frame->tf_pc + 4; out: PROC_LOCK(p); return (error); } int ptrace_clear_single_step(struct thread *td) { struct proc *p; if (td->td_md.md_ptrace_instr) { p = td->td_proc; PROC_UNLOCK(p); ptrace_write_int(td, td->td_md.md_ptrace_addr, td->td_md.md_ptrace_instr); PROC_LOCK(p); td->td_md.md_ptrace_instr = 0; } return (0); } int ptrace_set_pc(struct thread *td, unsigned long addr) { td->td_frame->tf_pc = addr; return (0); } void cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) { } void spinlock_enter(void) { struct thread *td; register_t cspr; td = curthread; if (td->td_md.md_spinlock_count == 0) { - cspr = disable_interrupts(I32_bit | F32_bit); + cspr = disable_interrupts(PSR_I | PSR_F); td->td_md.md_spinlock_count = 1; td->td_md.md_saved_cspr = cspr; } else td->td_md.md_spinlock_count++; critical_enter(); } void spinlock_exit(void) { struct thread *td; register_t cspr; td = curthread; critical_exit(); cspr = td->td_md.md_saved_cspr; td->td_md.md_spinlock_count--; if (td->td_md.md_spinlock_count == 0) restore_interrupts(cspr); } /* * Clear registers on exec */ void exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) { struct trapframe *tf = td->td_frame; memset(tf, 0, sizeof(*tf)); tf->tf_usr_sp = stack; tf->tf_usr_lr = imgp->entry_addr; tf->tf_svc_lr = 0x77777777; tf->tf_pc = imgp->entry_addr; tf->tf_spsr = PSR_USR32_MODE; } /* * Get machine context. */ int get_mcontext(struct thread *td, mcontext_t *mcp, int clear_ret) { struct trapframe *tf = td->td_frame; __greg_t *gr = mcp->__gregs; if (clear_ret & GET_MC_CLEAR_RET) gr[_REG_R0] = 0; else gr[_REG_R0] = tf->tf_r0; gr[_REG_R1] = tf->tf_r1; gr[_REG_R2] = tf->tf_r2; gr[_REG_R3] = tf->tf_r3; gr[_REG_R4] = tf->tf_r4; gr[_REG_R5] = tf->tf_r5; gr[_REG_R6] = tf->tf_r6; gr[_REG_R7] = tf->tf_r7; gr[_REG_R8] = tf->tf_r8; gr[_REG_R9] = tf->tf_r9; gr[_REG_R10] = tf->tf_r10; gr[_REG_R11] = tf->tf_r11; gr[_REG_R12] = tf->tf_r12; gr[_REG_SP] = tf->tf_usr_sp; gr[_REG_LR] = tf->tf_usr_lr; gr[_REG_PC] = tf->tf_pc; gr[_REG_CPSR] = tf->tf_spsr; return (0); } /* * Set machine context. * * However, we don't set any but the user modifiable flags, and we won't * touch the cs selector. */ int set_mcontext(struct thread *td, const mcontext_t *mcp) { struct trapframe *tf = td->td_frame; const __greg_t *gr = mcp->__gregs; tf->tf_r0 = gr[_REG_R0]; tf->tf_r1 = gr[_REG_R1]; tf->tf_r2 = gr[_REG_R2]; tf->tf_r3 = gr[_REG_R3]; tf->tf_r4 = gr[_REG_R4]; tf->tf_r5 = gr[_REG_R5]; tf->tf_r6 = gr[_REG_R6]; tf->tf_r7 = gr[_REG_R7]; tf->tf_r8 = gr[_REG_R8]; tf->tf_r9 = gr[_REG_R9]; tf->tf_r10 = gr[_REG_R10]; tf->tf_r11 = gr[_REG_R11]; tf->tf_r12 = gr[_REG_R12]; tf->tf_usr_sp = gr[_REG_SP]; tf->tf_usr_lr = gr[_REG_LR]; tf->tf_pc = gr[_REG_PC]; tf->tf_spsr = gr[_REG_CPSR]; return (0); } /* * MPSAFE */ int sys_sigreturn(td, uap) struct thread *td; struct sigreturn_args /* { const struct __ucontext *sigcntxp; } */ *uap; { ucontext_t uc; int spsr; if (uap == NULL) return (EFAULT); if (copyin(uap->sigcntxp, &uc, sizeof(uc))) return (EFAULT); /* * Make sure the processor mode has not been tampered with and * interrupts have not been disabled. */ spsr = uc.uc_mcontext.__gregs[_REG_CPSR]; if ((spsr & PSR_MODE) != PSR_USR32_MODE || - (spsr & (I32_bit | F32_bit)) != 0) + (spsr & (PSR_I | PSR_F)) != 0) return (EINVAL); /* Restore register context. */ set_mcontext(td, &uc.uc_mcontext); /* Restore signal mask. */ kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0); return (EJUSTRETURN); } /* * Construct a PCB from a trapframe. This is called from kdb_trap() where * we want to start a backtrace from the function that caused us to enter * the debugger. We have the context in the trapframe, but base the trace * on the PCB. The PCB doesn't have to be perfect, as long as it contains * enough for a backtrace. */ void makectx(struct trapframe *tf, struct pcb *pcb) { pcb->un_32.pcb32_r8 = tf->tf_r8; pcb->un_32.pcb32_r9 = tf->tf_r9; pcb->un_32.pcb32_r10 = tf->tf_r10; pcb->un_32.pcb32_r11 = tf->tf_r11; pcb->un_32.pcb32_r12 = tf->tf_r12; pcb->un_32.pcb32_pc = tf->tf_pc; pcb->un_32.pcb32_lr = tf->tf_usr_lr; pcb->un_32.pcb32_sp = tf->tf_usr_sp; } /* * Fake up a boot descriptor table */ vm_offset_t fake_preload_metadata(struct arm_boot_params *abp __unused) { #ifdef DDB vm_offset_t zstart = 0, zend = 0; #endif vm_offset_t lastaddr; int i = 0; static uint32_t fake_preload[35]; fake_preload[i++] = MODINFO_NAME; fake_preload[i++] = strlen("kernel") + 1; strcpy((char*)&fake_preload[i++], "kernel"); i += 1; fake_preload[i++] = MODINFO_TYPE; fake_preload[i++] = strlen("elf kernel") + 1; strcpy((char*)&fake_preload[i++], "elf kernel"); i += 2; fake_preload[i++] = MODINFO_ADDR; fake_preload[i++] = sizeof(vm_offset_t); fake_preload[i++] = KERNVIRTADDR; fake_preload[i++] = MODINFO_SIZE; fake_preload[i++] = sizeof(uint32_t); fake_preload[i++] = (uint32_t)&end - KERNVIRTADDR; #ifdef DDB if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) { fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM; fake_preload[i++] = sizeof(vm_offset_t); fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4); fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM; fake_preload[i++] = sizeof(vm_offset_t); fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8); lastaddr = *(uint32_t *)(KERNVIRTADDR + 8); zend = lastaddr; zstart = *(uint32_t *)(KERNVIRTADDR + 4); ksym_start = zstart; ksym_end = zend; } else #endif lastaddr = (vm_offset_t)&end; fake_preload[i++] = 0; fake_preload[i] = 0; preload_metadata = (void *)fake_preload; return (lastaddr); } void pcpu0_init(void) { #if ARM_ARCH_6 || ARM_ARCH_7A || defined(CPU_MV_PJ4B) set_curthread(&thread0); #endif pcpu_init(pcpup, 0, sizeof(struct pcpu)); PCPU_SET(curthread, &thread0); #ifdef VFP PCPU_SET(cpu, 0); #endif } #if defined(LINUX_BOOT_ABI) vm_offset_t linux_parse_boot_param(struct arm_boot_params *abp) { struct arm_lbabi_tag *walker; uint32_t revision; uint64_t serial; /* * Linux boot ABI: r0 = 0, r1 is the board type (!= 0) and r2 * is atags or dtb pointer. If all of these aren't satisfied, * then punt. */ if (!(abp->abp_r0 == 0 && abp->abp_r1 != 0 && abp->abp_r2 != 0)) return 0; board_id = abp->abp_r1; walker = (struct arm_lbabi_tag *) (abp->abp_r2 + KERNVIRTADDR - abp->abp_physaddr); /* xxx - Need to also look for binary device tree */ if (ATAG_TAG(walker) != ATAG_CORE) return 0; atag_list = walker; while (ATAG_TAG(walker) != ATAG_NONE) { switch (ATAG_TAG(walker)) { case ATAG_CORE: break; case ATAG_MEM: arm_physmem_hardware_region(walker->u.tag_mem.start, walker->u.tag_mem.size); break; case ATAG_INITRD2: break; case ATAG_SERIAL: serial = walker->u.tag_sn.low | ((uint64_t)walker->u.tag_sn.high << 32); board_set_serial(serial); break; case ATAG_REVISION: revision = walker->u.tag_rev.rev; board_set_revision(revision); break; case ATAG_CMDLINE: /* XXX open question: Parse this for boothowto? */ bcopy(walker->u.tag_cmd.command, linux_command_line, ATAG_SIZE(walker)); break; default: break; } walker = ATAG_NEXT(walker); } /* Save a copy for later */ bcopy(atag_list, atags, (char *)walker - (char *)atag_list + ATAG_SIZE(walker)); return fake_preload_metadata(abp); } #endif #if defined(FREEBSD_BOOT_LOADER) vm_offset_t freebsd_parse_boot_param(struct arm_boot_params *abp) { vm_offset_t lastaddr = 0; void *mdp; void *kmdp; /* * Mask metadata pointer: it is supposed to be on page boundary. If * the first argument (mdp) doesn't point to a valid address the * bootloader must have passed us something else than the metadata * ptr, so we give up. Also give up if we cannot find metadta section * the loader creates that we get all this data out of. */ if ((mdp = (void *)(abp->abp_r0 & ~PAGE_MASK)) == NULL) return 0; preload_metadata = mdp; kmdp = preload_search_by_type("elf kernel"); if (kmdp == NULL) return 0; boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *); lastaddr = MD_FETCH(kmdp, MODINFOMD_KERNEND, vm_offset_t); #ifdef DDB ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); #endif preload_addr_relocate = KERNVIRTADDR - abp->abp_physaddr; return lastaddr; } #endif vm_offset_t default_parse_boot_param(struct arm_boot_params *abp) { vm_offset_t lastaddr; #if defined(LINUX_BOOT_ABI) if ((lastaddr = linux_parse_boot_param(abp)) != 0) return lastaddr; #endif #if defined(FREEBSD_BOOT_LOADER) if ((lastaddr = freebsd_parse_boot_param(abp)) != 0) return lastaddr; #endif /* Fall back to hardcoded metadata. */ lastaddr = fake_preload_metadata(abp); return lastaddr; } /* * Stub version of the boot parameter parsing routine. We are * called early in initarm, before even VM has been initialized. * This routine needs to preserve any data that the boot loader * has passed in before the kernel starts to grow past the end * of the BSS, traditionally the place boot-loaders put this data. * * Since this is called so early, things that depend on the vm system * being setup (including access to some SoC's serial ports), about * all that can be done in this routine is to copy the arguments. * * This is the default boot parameter parsing routine. Individual * kernels/boards can override this weak function with one of their * own. We just fake metadata... */ __weak_reference(default_parse_boot_param, parse_boot_param); /* * Initialize proc0 */ void init_proc0(vm_offset_t kstack) { proc_linkup0(&proc0, &thread0); thread0.td_kstack = kstack; thread0.td_pcb = (struct pcb *) (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; thread0.td_pcb->pcb_flags = 0; thread0.td_pcb->pcb_vfpcpu = -1; thread0.td_pcb->pcb_vfpstate.fpscr = VFPSCR_DN | VFPSCR_FZ; thread0.td_frame = &proc0_tf; pcpup->pc_curpcb = thread0.td_pcb; } void set_stackptrs(int cpu) { set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); set_stackptr(PSR_UND32_MODE, undstack.pv_va + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1))); } #ifdef FDT static char * kenv_next(char *cp) { if (cp != NULL) { while (*cp != 0) cp++; cp++; if (*cp == 0) cp = NULL; } return (cp); } static void print_kenv(void) { int len; char *cp; debugf("loader passed (static) kenv:\n"); if (kern_envp == NULL) { debugf(" no env, null ptr\n"); return; } debugf(" kern_envp = 0x%08x\n", (uint32_t)kern_envp); len = 0; for (cp = kern_envp; cp != NULL; cp = kenv_next(cp)) debugf(" %x %s\n", (uint32_t)cp, cp); } void * initarm(struct arm_boot_params *abp) { struct mem_region mem_regions[FDT_MEM_REGIONS]; struct pv_addr kernel_l1pt; struct pv_addr dpcpu; vm_offset_t dtbp, freemempos, l2_start, lastaddr; uint32_t memsize, l2size; char *env; void *kmdp; u_int l1pagetable; int i, j, err_devmap, mem_regions_sz; lastaddr = parse_boot_param(abp); arm_physmem_kernaddr = abp->abp_physaddr; memsize = 0; set_cpufuncs(); /* * Find the dtb passed in by the boot loader. */ kmdp = preload_search_by_type("elf kernel"); if (kmdp != NULL) dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t); else dtbp = (vm_offset_t)NULL; #if defined(FDT_DTB_STATIC) /* * In case the device tree blob was not retrieved (from metadata) try * to use the statically embedded one. */ if (dtbp == (vm_offset_t)NULL) dtbp = (vm_offset_t)&fdt_static_dtb; #endif if (OF_install(OFW_FDT, 0) == FALSE) panic("Cannot install FDT"); if (OF_init((void *)dtbp) != 0) panic("OF_init failed with the found device tree"); /* Grab physical memory regions information from device tree. */ if (fdt_get_mem_regions(mem_regions, &mem_regions_sz, &memsize) != 0) panic("Cannot get physical memory regions"); arm_physmem_hardware_regions(mem_regions, mem_regions_sz); /* Grab reserved memory regions information from device tree. */ if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0) arm_physmem_exclude_regions(mem_regions, mem_regions_sz, EXFLAG_NODUMP | EXFLAG_NOALLOC); /* Platform-specific initialisation */ platform_probe_and_attach(); pcpu0_init(); /* Do basic tuning, hz etc */ init_param1(); /* Calculate number of L2 tables needed for mapping vm_page_array */ l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page); l2size = (l2size >> L1_S_SHIFT) + 1; /* * Add one table for end of kernel map, one for stacks, msgbuf and * L1 and L2 tables map and one for vectors map. */ l2size += 3; /* Make it divisible by 4 */ l2size = (l2size + 3) & ~3; freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; /* Define a macro to simplify memory allocation */ #define valloc_pages(var, np) \ alloc_pages((var).pv_va, (np)); \ (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR); #define alloc_pages(var, np) \ (var) = freemempos; \ freemempos += (np * PAGE_SIZE); \ memset((char *)(var), 0, ((np) * PAGE_SIZE)); while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) freemempos += PAGE_SIZE; valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); for (i = 0, j = 0; i < l2size; ++i) { if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { valloc_pages(kernel_pt_table[i], L2_TABLE_SIZE / PAGE_SIZE); j = i; } else { kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va + L2_TABLE_SIZE_REAL * (i - j); kernel_pt_table[i].pv_pa = kernel_pt_table[i].pv_va - KERNVIRTADDR + abp->abp_physaddr; } } /* * Allocate a page for the system page mapped to 0x00000000 * or 0xffff0000. This page will just contain the system vectors * and can be shared by all processes. */ valloc_pages(systempage, 1); /* Allocate dynamic per-cpu area. */ valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); dpcpu_init((void *)dpcpu.pv_va, 0); /* Allocate stacks for all modes */ valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU); valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU); valloc_pages(undstack, UND_STACK_SIZE * MAXCPU); valloc_pages(kernelstack, KSTACK_PAGES * MAXCPU); valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); /* * Now we start construction of the L1 page table * We start by mapping the L2 page tables into the L1. * This means that we can replace L1 mappings later on if necessary */ l1pagetable = kernel_l1pt.pv_va; /* * Try to map as much as possible of kernel text and data using * 1MB section mapping and for the rest of initial kernel address * space use L2 coarse tables. * * Link L2 tables for mapping remainder of kernel (modulo 1MB) * and kernel structures */ l2_start = lastaddr & ~(L1_S_OFFSET); for (i = 0 ; i < l2size - 1; i++) pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE, &kernel_pt_table[i]); pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE; /* Map kernel code and data */ pmap_map_chunk(l1pagetable, KERNVIRTADDR, abp->abp_physaddr, (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); /* Map L1 directory and allocated L2 page tables */ pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va, kernel_pt_table[0].pv_pa, L2_TABLE_SIZE_REAL * l2size, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); /* Map allocated DPCPU, stacks and msgbuf */ pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, freemempos - dpcpu.pv_va, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); /* Link and map the vector page */ pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH, &kernel_pt_table[l2size - 1]); pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE); /* Establish static device mappings. */ err_devmap = platform_devmap_init(); arm_devmap_bootstrap(l1pagetable, NULL); vm_max_kernel_address = platform_lastaddr(); cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT); pmap_pa = kernel_l1pt.pv_pa; setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)); /* * Now that proper page tables are installed, call cpu_setup() to enable * instruction and data caches and other chip-specific features. */ cpu_setup(""); /* * Only after the SOC registers block is mapped we can perform device * tree fixups, as they may attempt to read parameters from hardware. */ OF_interpret("perform-fixup", 0); platform_gpio_init(); cninit(); debugf("initarm: console initialized\n"); debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp); debugf(" boothowto = 0x%08x\n", boothowto); debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp); print_kenv(); env = getenv("kernelname"); if (env != NULL) strlcpy(kernelname, env, sizeof(kernelname)); if (err_devmap != 0) printf("WARNING: could not fully configure devmap, error=%d\n", err_devmap); platform_late_init(); /* * Pages were allocated during the secondary bootstrap for the * stacks for different CPU modes. * We must now set the r13 registers in the different CPU modes to * point to these stacks. * Since the ARM stacks use STMFD etc. we must set r13 to the top end * of the stack memory. */ cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); set_stackptrs(0); /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any * dirty data in the cache. This will have happened in setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. * After booting there are no gross relocations of the kernel thus * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); undefined_init(); init_proc0(kernelstack.pv_va); arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); pmap_bootstrap(freemempos, &kernel_l1pt); msgbufp = (void *)msgbufpv.pv_va; msgbufinit(msgbufp, msgbufsize); mutex_init(); /* * Exclude the kernel (and all the things we allocated which immediately * follow the kernel) from the VM allocation pool but not from crash * dumps. virtual_avail is a global variable which tracks the kva we've * "allocated" while setting up pmaps. * * Prepare the list of physical memory available to the vm subsystem. */ arm_physmem_exclude_region(abp->abp_physaddr, (virtual_avail - KERNVIRTADDR), EXFLAG_NOALLOC); arm_physmem_init_kernel_globals(); init_param2(physmem); kdb_init(); return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - sizeof(struct pcb))); } #endif Index: head/sys/arm/arm/mp_machdep.c =================================================================== --- head/sys/arm/arm/mp_machdep.c (revision 271397) +++ head/sys/arm/arm/mp_machdep.c (revision 271398) @@ -1,435 +1,436 @@ /*- * Copyright (c) 2011 Semihalf. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #ifdef VFP #include #endif #ifdef CPU_MV_PJ4B #include #include #endif #include "opt_smp.h" void *temp_pagetable; extern struct pcpu __pcpu[]; /* used to hold the AP's until we are ready to release them */ struct mtx ap_boot_mtx; struct pcb stoppcbs[MAXCPU]; /* # of Applications processors */ volatile int mp_naps; /* Set to 1 once we're ready to let the APs out of the pen. */ volatile int aps_ready = 0; static int ipi_handler(void *arg); void set_stackptrs(int cpu); /* Temporary variables for init_secondary() */ void *dpcpu[MAXCPU - 1]; /* Determine if we running MP machine */ int cpu_mp_probe(void) { CPU_SETOF(0, &all_cpus); return (platform_mp_probe()); } /* Start Application Processor via platform specific function */ static int check_ap(void) { uint32_t ms; for (ms = 0; ms < 2000; ++ms) { if ((mp_naps + 1) == mp_ncpus) return (0); /* success */ else DELAY(1000); } return (-2); } extern unsigned char _end[]; /* Initialize and fire up non-boot processors */ void cpu_mp_start(void) { int error, i; vm_offset_t temp_pagetable_va; vm_paddr_t addr, addr_end; mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); /* Reserve memory for application processors */ for(i = 0; i < (mp_ncpus - 1); i++) dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, M_WAITOK | M_ZERO); temp_pagetable_va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_TEMP, 0, 0x0, 0xffffffff, L1_TABLE_SIZE, 0); addr = arm_physmem_kernaddr; addr_end = (vm_offset_t)&_end - KERNVIRTADDR + arm_physmem_kernaddr; addr_end &= ~L1_S_OFFSET; addr_end += L1_S_SIZE; bzero((void *)temp_pagetable_va, L1_TABLE_SIZE); for (addr = arm_physmem_kernaddr; addr <= addr_end; addr += L1_S_SIZE) { ((int *)(temp_pagetable_va))[addr >> L1_S_SHIFT] = L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; ((int *)(temp_pagetable_va))[(addr - arm_physmem_kernaddr + KERNVIRTADDR) >> L1_S_SHIFT] = L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_B|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr; } #if defined(CPU_MV_PJ4B) /* Add ARMADAXP registers required for snoop filter initialization */ ((int *)(temp_pagetable_va))[MV_BASE >> L1_S_SHIFT] = L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|fdt_immr_pa; #endif temp_pagetable = (void*)(vtophys(temp_pagetable_va)); cpu_idcache_wbinv_all(); cpu_l2cache_wbinv_all(); /* Initialize boot code and start up processors */ platform_mp_start_ap(); /* Check if ap's started properly */ error = check_ap(); if (error) printf("WARNING: Some AP's failed to start\n"); else for (i = 1; i < mp_ncpus; i++) CPU_SET(i, &all_cpus); contigfree((void *)temp_pagetable_va, L1_TABLE_SIZE, M_TEMP); } /* Introduce rest of cores to the world */ void cpu_mp_announce(void) { } extern vm_paddr_t pmap_pa; void init_secondary(int cpu) { struct pcpu *pc; uint32_t loop_counter; int start = 0, end = 0; cpu_idcache_inv_all(); cpu_setup(NULL); setttb(pmap_pa); cpu_tlb_flushID(); pc = &__pcpu[cpu]; /* * pcpu_init() updates queue, so it should not be executed in parallel * on several cores */ while(mp_naps < (cpu - 1)) ; pcpu_init(pc, cpu, sizeof(struct pcpu)); dpcpu_init(dpcpu[cpu - 1], cpu); /* Provide stack pointers for other processor modes. */ set_stackptrs(cpu); /* Signal our startup to BSP */ atomic_add_rel_32(&mp_naps, 1); /* Spin until the BSP releases the APs */ while (!aps_ready) ; /* Initialize curthread */ KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); pc->pc_curthread = pc->pc_idlethread; pc->pc_curpcb = pc->pc_idlethread->td_pcb; set_curthread(pc->pc_idlethread); #ifdef VFP pc->pc_cpu = cpu; vfp_init(); #endif mtx_lock_spin(&ap_boot_mtx); atomic_add_rel_32(&smp_cpus, 1); if (smp_cpus == mp_ncpus) { /* enable IPI's, tlb shootdown, freezes etc */ atomic_store_rel_int(&smp_started, 1); } mtx_unlock_spin(&ap_boot_mtx); /* Enable ipi */ #ifdef IPI_IRQ_START start = IPI_IRQ_START; #ifdef IPI_IRQ_END end = IPI_IRQ_END; #else end = IPI_IRQ_START; #endif #endif for (int i = start; i <= end; i++) arm_unmask_irq(i); - enable_interrupts(I32_bit); + enable_interrupts(PSR_I); loop_counter = 0; while (smp_started == 0) { DELAY(100); loop_counter++; if (loop_counter == 1000) CTR0(KTR_SMP, "AP still wait for smp_started"); } /* Start per-CPU event timers. */ cpu_initclocks_ap(); CTR0(KTR_SMP, "go into scheduler"); platform_mp_init_secondary(); /* Enter the scheduler */ sched_throw(NULL); panic("scheduler returned us to %s", __func__); /* NOTREACHED */ } static int ipi_handler(void *arg) { u_int cpu, ipi; cpu = PCPU_GET(cpuid); ipi = pic_ipi_get((int)arg); while ((ipi != 0x3ff)) { switch (ipi) { case IPI_RENDEZVOUS: CTR0(KTR_SMP, "IPI_RENDEZVOUS"); smp_rendezvous_action(); break; case IPI_AST: CTR0(KTR_SMP, "IPI_AST"); break; case IPI_STOP: /* * IPI_STOP_HARD is mapped to IPI_STOP so it is not * necessary to add it in the switch. */ CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); savectx(&stoppcbs[cpu]); /* * CPUs are stopped when entering the debugger and at * system shutdown, both events which can precede a * panic dump. For the dump to be correct, all caches * must be flushed and invalidated, but on ARM there's * no way to broadcast a wbinv_all to other cores. * Instead, we have each core do the local wbinv_all as * part of stopping the core. The core requesting the * stop will do the l2 cache flush after all other cores * have done their l1 flushes and stopped. */ cpu_idcache_wbinv_all(); /* Indicate we are stopped */ CPU_SET_ATOMIC(cpu, &stopped_cpus); /* Wait for restart */ while (!CPU_ISSET(cpu, &started_cpus)) cpu_spinwait(); CPU_CLR_ATOMIC(cpu, &started_cpus); CPU_CLR_ATOMIC(cpu, &stopped_cpus); CTR0(KTR_SMP, "IPI_STOP (restart)"); break; case IPI_PREEMPT: CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); sched_preempt(curthread); break; case IPI_HARDCLOCK: CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); hardclockintr(); break; case IPI_TLB: CTR1(KTR_SMP, "%s: IPI_TLB", __func__); cpufuncs.cf_tlb_flushID(); break; default: panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu); } pic_ipi_clear(ipi); ipi = pic_ipi_get(-1); } return (FILTER_HANDLED); } static void release_aps(void *dummy __unused) { uint32_t loop_counter; int start = 0, end = 0; if (mp_ncpus == 1) return; #ifdef IPI_IRQ_START start = IPI_IRQ_START; #ifdef IPI_IRQ_END end = IPI_IRQ_END; #else end = IPI_IRQ_START; #endif #endif for (int i = start; i <= end; i++) { /* * IPI handler */ /* * Use 0xdeadbeef as the argument value for irq 0, * if we used 0, the intr code will give the trap frame * pointer instead. */ arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i, INTR_TYPE_MISC | INTR_EXCL, NULL); /* Enable ipi */ arm_unmask_irq(i); } atomic_store_rel_int(&aps_ready, 1); printf("Release APs\n"); for (loop_counter = 0; loop_counter < 2000; loop_counter++) { if (smp_started) return; DELAY(1000); } printf("AP's not started\n"); } SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); struct cpu_group * cpu_topo(void) { return (smp_topo_1level(CG_SHARE_L2, mp_ncpus, 0)); } void cpu_mp_setmaxid(void) { platform_mp_setmaxid(); } /* Sending IPI */ void ipi_all_but_self(u_int ipi) { cpuset_t other_cpus; other_cpus = all_cpus; CPU_CLR(PCPU_GET(cpuid), &other_cpus); CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); platform_ipi_send(other_cpus, ipi); } void ipi_cpu(int cpu, u_int ipi) { cpuset_t cpus; CPU_ZERO(&cpus); CPU_SET(cpu, &cpus); CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); platform_ipi_send(cpus, ipi); } void ipi_selected(cpuset_t cpus, u_int ipi) { CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); platform_ipi_send(cpus, ipi); } void tlb_broadcast(int ipi) { if (smp_started) ipi_all_but_self(ipi); } Index: head/sys/arm/arm/trap.c =================================================================== --- head/sys/arm/arm/trap.c (revision 271397) +++ head/sys/arm/arm/trap.c (revision 271398) @@ -1,880 +1,880 @@ /* $NetBSD: fault.c,v 1.45 2003/11/20 14:44:36 scw Exp $ */ /*- * Copyright 2004 Olivier Houchard * Copyright 2003 Wasabi Systems, Inc. * All rights reserved. * * Written by Steve C. Woodford for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 1994-1997 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * fault.c * * Fault handlers * * Created : 28/11/94 */ #include "opt_ktrace.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #ifdef KTRACE #include #include #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef KDB #include #endif void swi_handler(struct trapframe *); #include #include extern char fusubailout[]; #ifdef DEBUG int last_fault_code; /* For the benefit of pmap_fault_fixup() */ #endif struct ksig { int signb; u_long code; }; struct data_abort { int (*func)(struct trapframe *, u_int, u_int, struct thread *, struct ksig *); const char *desc; }; static int dab_fatal(struct trapframe *, u_int, u_int, struct thread *, struct ksig *); static int dab_align(struct trapframe *, u_int, u_int, struct thread *, struct ksig *); static int dab_buserr(struct trapframe *, u_int, u_int, struct thread *, struct ksig *); static const struct data_abort data_aborts[] = { {dab_fatal, "Vector Exception"}, {dab_align, "Alignment Fault 1"}, {dab_fatal, "Terminal Exception"}, {dab_align, "Alignment Fault 3"}, {dab_buserr, "External Linefetch Abort (S)"}, {NULL, "Translation Fault (S)"}, #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 {NULL, "Translation Flag Fault"}, #else {dab_buserr, "External Linefetch Abort (P)"}, #endif {NULL, "Translation Fault (P)"}, {dab_buserr, "External Non-Linefetch Abort (S)"}, {NULL, "Domain Fault (S)"}, {dab_buserr, "External Non-Linefetch Abort (P)"}, {NULL, "Domain Fault (P)"}, {dab_buserr, "External Translation Abort (L1)"}, {NULL, "Permission Fault (S)"}, {dab_buserr, "External Translation Abort (L2)"}, {NULL, "Permission Fault (P)"} }; /* Determine if a fault came from user mode */ #define TRAP_USERMODE(tf) ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE) /* Determine if 'x' is a permission fault */ #define IS_PERMISSION_FAULT(x) \ (((1 << ((x) & FAULT_TYPE_MASK)) & \ ((1 << FAULT_PERM_P) | (1 << FAULT_PERM_S))) != 0) static __inline void call_trapsignal(struct thread *td, int sig, u_long code) { ksiginfo_t ksi; ksiginfo_init_trap(&ksi); ksi.ksi_signo = sig; ksi.ksi_code = (int)code; trapsignal(td, &ksi); } void data_abort_handler(struct trapframe *tf) { struct vm_map *map; struct pcb *pcb; struct thread *td; u_int user, far, fsr; vm_prot_t ftype; void *onfault; vm_offset_t va; int error = 0; struct ksig ksig; struct proc *p; /* Grab FAR/FSR before enabling interrupts */ far = cpu_faultaddress(); fsr = cpu_faultstatus(); #if 0 printf("data abort: fault address=%p (from pc=%p lr=%p)\n", (void*)far, (void*)tf->tf_pc, (void*)tf->tf_svc_lr); #endif /* Update vmmeter statistics */ #if 0 vmexp.traps++; #endif td = curthread; p = td->td_proc; PCPU_INC(cnt.v_trap); /* Data abort came from user mode? */ user = TRAP_USERMODE(tf); if (user) { td->td_pticks = 0; td->td_frame = tf; if (td->td_ucred != td->td_proc->p_ucred) cred_update_thread(td); } /* Grab the current pcb */ pcb = td->td_pcb; /* Re-enable interrupts if they were enabled previously */ if (td->td_md.md_spinlock_count == 0) { - if (__predict_true(tf->tf_spsr & I32_bit) == 0) - enable_interrupts(I32_bit); - if (__predict_true(tf->tf_spsr & F32_bit) == 0) - enable_interrupts(F32_bit); + if (__predict_true(tf->tf_spsr & PSR_I) == 0) + enable_interrupts(PSR_I); + if (__predict_true(tf->tf_spsr & PSR_F) == 0) + enable_interrupts(PSR_F); } /* Invoke the appropriate handler, if necessary */ if (__predict_false(data_aborts[fsr & FAULT_TYPE_MASK].func != NULL)) { if ((data_aborts[fsr & FAULT_TYPE_MASK].func)(tf, fsr, far, td, &ksig)) { goto do_trapsignal; } goto out; } /* * At this point, we're dealing with one of the following data aborts: * * FAULT_TRANS_S - Translation -- Section * FAULT_TRANS_P - Translation -- Page * FAULT_DOMAIN_S - Domain -- Section * FAULT_DOMAIN_P - Domain -- Page * FAULT_PERM_S - Permission -- Section * FAULT_PERM_P - Permission -- Page * * These are the main virtual memory-related faults signalled by * the MMU. */ /* fusubailout is used by [fs]uswintr to avoid page faulting */ if (__predict_false(pcb->pcb_onfault == fusubailout)) { tf->tf_r0 = EFAULT; tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault; return; } /* * Make sure the Program Counter is sane. We could fall foul of * someone executing Thumb code, in which case the PC might not * be word-aligned. This would cause a kernel alignment fault * further down if we have to decode the current instruction. * XXX: It would be nice to be able to support Thumb at some point. */ if (__predict_false((tf->tf_pc & 3) != 0)) { if (user) { /* * Give the user an illegal instruction signal. */ /* Deliver a SIGILL to the process */ ksig.signb = SIGILL; ksig.code = 0; goto do_trapsignal; } /* * The kernel never executes Thumb code. */ printf("\ndata_abort_fault: Misaligned Kernel-mode " "Program Counter\n"); dab_fatal(tf, fsr, far, td, &ksig); } va = trunc_page((vm_offset_t)far); /* * It is only a kernel address space fault iff: * 1. user == 0 and * 2. pcb_onfault not set or * 3. pcb_onfault set and not LDRT/LDRBT/STRT/STRBT instruction. */ if (user == 0 && (va >= VM_MIN_KERNEL_ADDRESS || (va < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW)) && __predict_true((pcb->pcb_onfault == NULL || (ReadWord(tf->tf_pc) & 0x05200000) != 0x04200000))) { map = kernel_map; /* Was the fault due to the FPE/IPKDB ? */ if (__predict_false((tf->tf_spsr & PSR_MODE)==PSR_UND32_MODE)) { /* * Force exit via userret() * This is necessary as the FPE is an extension to * userland that actually runs in a priveledged mode * but uses USR mode permissions for its accesses. */ user = 1; ksig.signb = SIGSEGV; ksig.code = 0; goto do_trapsignal; } } else { map = &td->td_proc->p_vmspace->vm_map; } /* * We need to know whether the page should be mapped as R or R/W. On * armv6 and later the fault status register indicates whether the * access was a read or write. Prior to armv6, we know that a * permission fault can only be the result of a write to a read-only * location, so we can deal with those quickly. Otherwise we need to * disassemble the faulting instruction to determine if it was a write. */ #if ARM_ARCH_6 || ARM_ARCH_7A ftype = (fsr & FAULT_WNR) ? VM_PROT_READ | VM_PROT_WRITE : VM_PROT_READ; #else if (IS_PERMISSION_FAULT(fsr)) ftype = VM_PROT_WRITE; else { u_int insn = ReadWord(tf->tf_pc); if (((insn & 0x0c100000) == 0x04000000) || /* STR/STRB */ ((insn & 0x0e1000b0) == 0x000000b0) || /* STRH/STRD */ ((insn & 0x0a100000) == 0x08000000)) { /* STM/CDT */ ftype = VM_PROT_WRITE; } else { if ((insn & 0x0fb00ff0) == 0x01000090) /* SWP */ ftype = VM_PROT_READ | VM_PROT_WRITE; else ftype = VM_PROT_READ; } } #endif /* * See if the fault is as a result of ref/mod emulation, * or domain mismatch. */ #ifdef DEBUG last_fault_code = fsr; #endif if (td->td_critnest != 0 || WITNESS_CHECK(WARN_SLEEPOK | WARN_GIANTOK, NULL, "Kernel page fault") != 0) goto fatal_pagefault; if (pmap_fault_fixup(vmspace_pmap(td->td_proc->p_vmspace), va, ftype, user)) { goto out; } onfault = pcb->pcb_onfault; pcb->pcb_onfault = NULL; if (map != kernel_map) { PROC_LOCK(p); p->p_lock++; PROC_UNLOCK(p); } error = vm_fault(map, va, ftype, VM_FAULT_NORMAL); pcb->pcb_onfault = onfault; if (map != kernel_map) { PROC_LOCK(p); p->p_lock--; PROC_UNLOCK(p); } if (__predict_true(error == 0)) goto out; fatal_pagefault: if (user == 0) { if (pcb->pcb_onfault) { tf->tf_r0 = error; tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault; return; } printf("\nvm_fault(%p, %x, %x, 0) -> %x\n", map, va, ftype, error); dab_fatal(tf, fsr, far, td, &ksig); } if (error == ENOMEM) { printf("VM: pid %d (%s), uid %d killed: " "out of swap\n", td->td_proc->p_pid, td->td_name, (td->td_proc->p_ucred) ? td->td_proc->p_ucred->cr_uid : -1); ksig.signb = SIGKILL; } else { ksig.signb = SIGSEGV; } ksig.code = 0; do_trapsignal: call_trapsignal(td, ksig.signb, ksig.code); out: /* If returning to user mode, make sure to invoke userret() */ if (user) userret(td, tf); } /* * dab_fatal() handles the following data aborts: * * FAULT_WRTBUF_0 - Vector Exception * FAULT_WRTBUF_1 - Terminal Exception * * We should never see these on a properly functioning system. * * This function is also called by the other handlers if they * detect a fatal problem. * * Note: If 'l' is NULL, we assume we're dealing with a prefetch abort. */ static int dab_fatal(struct trapframe *tf, u_int fsr, u_int far, struct thread *td, struct ksig *ksig) { const char *mode; mode = TRAP_USERMODE(tf) ? "user" : "kernel"; - disable_interrupts(I32_bit|F32_bit); + disable_interrupts(PSR_I|PSR_F); if (td != NULL) { printf("Fatal %s mode data abort: '%s'\n", mode, data_aborts[fsr & FAULT_TYPE_MASK].desc); printf("trapframe: %p\nFSR=%08x, FAR=", tf, fsr); if ((fsr & FAULT_IMPRECISE) == 0) printf("%08x, ", far); else printf("Invalid, "); printf("spsr=%08x\n", tf->tf_spsr); } else { printf("Fatal %s mode prefetch abort at 0x%08x\n", mode, tf->tf_pc); printf("trapframe: %p, spsr=%08x\n", tf, tf->tf_spsr); } printf("r0 =%08x, r1 =%08x, r2 =%08x, r3 =%08x\n", tf->tf_r0, tf->tf_r1, tf->tf_r2, tf->tf_r3); printf("r4 =%08x, r5 =%08x, r6 =%08x, r7 =%08x\n", tf->tf_r4, tf->tf_r5, tf->tf_r6, tf->tf_r7); printf("r8 =%08x, r9 =%08x, r10=%08x, r11=%08x\n", tf->tf_r8, tf->tf_r9, tf->tf_r10, tf->tf_r11); printf("r12=%08x, ", tf->tf_r12); if (TRAP_USERMODE(tf)) printf("usp=%08x, ulr=%08x", tf->tf_usr_sp, tf->tf_usr_lr); else printf("ssp=%08x, slr=%08x", tf->tf_svc_sp, tf->tf_svc_lr); printf(", pc =%08x\n\n", tf->tf_pc); #ifdef KDB if (debugger_on_panic || kdb_active) if (kdb_trap(fsr, 0, tf)) return (0); #endif panic("Fatal abort"); /*NOTREACHED*/ } /* * dab_align() handles the following data aborts: * * FAULT_ALIGN_0 - Alignment fault * FAULT_ALIGN_1 - Alignment fault * * These faults are fatal if they happen in kernel mode. Otherwise, we * deliver a bus error to the process. */ static int dab_align(struct trapframe *tf, u_int fsr, u_int far, struct thread *td, struct ksig *ksig) { /* Alignment faults are always fatal if they occur in kernel mode */ if (!TRAP_USERMODE(tf)) { if (!td || !td->td_pcb->pcb_onfault) dab_fatal(tf, fsr, far, td, ksig); tf->tf_r0 = EFAULT; tf->tf_pc = (int)td->td_pcb->pcb_onfault; return (0); } /* pcb_onfault *must* be NULL at this point */ /* Deliver a bus error signal to the process */ ksig->code = 0; ksig->signb = SIGBUS; td->td_frame = tf; return (1); } /* * dab_buserr() handles the following data aborts: * * FAULT_BUSERR_0 - External Abort on Linefetch -- Section * FAULT_BUSERR_1 - External Abort on Linefetch -- Page * FAULT_BUSERR_2 - External Abort on Non-linefetch -- Section * FAULT_BUSERR_3 - External Abort on Non-linefetch -- Page * FAULT_BUSTRNL1 - External abort on Translation -- Level 1 * FAULT_BUSTRNL2 - External abort on Translation -- Level 2 * * If pcb_onfault is set, flag the fault and return to the handler. * If the fault occurred in user mode, give the process a SIGBUS. * * Note: On XScale, FAULT_BUSERR_0, FAULT_BUSERR_1, and FAULT_BUSERR_2 * can be flagged as imprecise in the FSR. This causes a real headache * since some of the machine state is lost. In this case, tf->tf_pc * may not actually point to the offending instruction. In fact, if * we've taken a double abort fault, it generally points somewhere near * the top of "data_abort_entry" in exception.S. * * In all other cases, these data aborts are considered fatal. */ static int dab_buserr(struct trapframe *tf, u_int fsr, u_int far, struct thread *td, struct ksig *ksig) { struct pcb *pcb = td->td_pcb; #ifdef __XSCALE__ if ((fsr & FAULT_IMPRECISE) != 0 && (tf->tf_spsr & PSR_MODE) == PSR_ABT32_MODE) { /* * Oops, an imprecise, double abort fault. We've lost the * r14_abt/spsr_abt values corresponding to the original * abort, and the spsr saved in the trapframe indicates * ABT mode. */ tf->tf_spsr &= ~PSR_MODE; /* * We use a simple heuristic to determine if the double abort * happened as a result of a kernel or user mode access. * If the current trapframe is at the top of the kernel stack, * the fault _must_ have come from user mode. */ if (tf != ((struct trapframe *)pcb->un_32.pcb32_sp) - 1) { /* * Kernel mode. We're either about to die a * spectacular death, or pcb_onfault will come * to our rescue. Either way, the current value * of tf->tf_pc is irrelevant. */ tf->tf_spsr |= PSR_SVC32_MODE; if (pcb->pcb_onfault == NULL) printf("\nKernel mode double abort!\n"); } else { /* * User mode. We've lost the program counter at the * time of the fault (not that it was accurate anyway; * it's not called an imprecise fault for nothing). * About all we can do is copy r14_usr to tf_pc and * hope for the best. The process is about to get a * SIGBUS, so it's probably history anyway. */ tf->tf_spsr |= PSR_USR32_MODE; tf->tf_pc = tf->tf_usr_lr; } } /* FAR is invalid for imprecise exceptions */ if ((fsr & FAULT_IMPRECISE) != 0) far = 0; #endif /* __XSCALE__ */ if (pcb->pcb_onfault) { tf->tf_r0 = EFAULT; tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault; return (0); } /* * At this point, if the fault happened in kernel mode, we're toast */ if (!TRAP_USERMODE(tf)) dab_fatal(tf, fsr, far, td, ksig); /* Deliver a bus error signal to the process */ ksig->signb = SIGBUS; ksig->code = 0; td->td_frame = tf; return (1); } /* * void prefetch_abort_handler(struct trapframe *tf) * * Abort handler called when instruction execution occurs at * a non existent or restricted (access permissions) memory page. * If the address is invalid and we were in SVC mode then panic as * the kernel should never prefetch abort. * If the address is invalid and the page is mapped then the user process * does no have read permission so send it a signal. * Otherwise fault the page in and try again. */ void prefetch_abort_handler(struct trapframe *tf) { struct thread *td; struct proc * p; struct vm_map *map; vm_offset_t fault_pc, va; int error = 0; struct ksig ksig; #if 0 /* Update vmmeter statistics */ uvmexp.traps++; #endif #if 0 printf("prefetch abort handler: %p %p\n", (void*)tf->tf_pc, (void*)tf->tf_usr_lr); #endif td = curthread; p = td->td_proc; PCPU_INC(cnt.v_trap); if (TRAP_USERMODE(tf)) { td->td_frame = tf; if (td->td_ucred != td->td_proc->p_ucred) cred_update_thread(td); } fault_pc = tf->tf_pc; if (td->td_md.md_spinlock_count == 0) { - if (__predict_true(tf->tf_spsr & I32_bit) == 0) - enable_interrupts(I32_bit); - if (__predict_true(tf->tf_spsr & F32_bit) == 0) - enable_interrupts(F32_bit); + if (__predict_true(tf->tf_spsr & PSR_I) == 0) + enable_interrupts(PSR_I); + if (__predict_true(tf->tf_spsr & PSR_F) == 0) + enable_interrupts(PSR_F); } /* Prefetch aborts cannot happen in kernel mode */ if (__predict_false(!TRAP_USERMODE(tf))) dab_fatal(tf, 0, tf->tf_pc, NULL, &ksig); td->td_pticks = 0; /* Ok validate the address, can only execute in USER space */ if (__predict_false(fault_pc >= VM_MAXUSER_ADDRESS || (fault_pc < VM_MIN_ADDRESS && vector_page == ARM_VECTORS_LOW))) { ksig.signb = SIGSEGV; ksig.code = 0; goto do_trapsignal; } map = &td->td_proc->p_vmspace->vm_map; va = trunc_page(fault_pc); /* * See if the pmap can handle this fault on its own... */ #ifdef DEBUG last_fault_code = -1; #endif if (pmap_fault_fixup(map->pmap, va, VM_PROT_READ, 1)) goto out; if (map != kernel_map) { PROC_LOCK(p); p->p_lock++; PROC_UNLOCK(p); } error = vm_fault(map, va, VM_PROT_READ | VM_PROT_EXECUTE, VM_FAULT_NORMAL); if (map != kernel_map) { PROC_LOCK(p); p->p_lock--; PROC_UNLOCK(p); } if (__predict_true(error == 0)) goto out; if (error == ENOMEM) { printf("VM: pid %d (%s), uid %d killed: " "out of swap\n", td->td_proc->p_pid, td->td_name, (td->td_proc->p_ucred) ? td->td_proc->p_ucred->cr_uid : -1); ksig.signb = SIGKILL; } else { ksig.signb = SIGSEGV; } ksig.code = 0; do_trapsignal: call_trapsignal(td, ksig.signb, ksig.code); out: userret(td, tf); } extern int badaddr_read_1(const uint8_t *, uint8_t *); extern int badaddr_read_2(const uint16_t *, uint16_t *); extern int badaddr_read_4(const uint32_t *, uint32_t *); /* * Tentatively read an 8, 16, or 32-bit value from 'addr'. * If the read succeeds, the value is written to 'rptr' and zero is returned. * Else, return EFAULT. */ int badaddr_read(void *addr, size_t size, void *rptr) { union { uint8_t v1; uint16_t v2; uint32_t v4; } u; int rv; cpu_drain_writebuf(); /* Read from the test address. */ switch (size) { case sizeof(uint8_t): rv = badaddr_read_1(addr, &u.v1); if (rv == 0 && rptr) *(uint8_t *) rptr = u.v1; break; case sizeof(uint16_t): rv = badaddr_read_2(addr, &u.v2); if (rv == 0 && rptr) *(uint16_t *) rptr = u.v2; break; case sizeof(uint32_t): rv = badaddr_read_4(addr, &u.v4); if (rv == 0 && rptr) *(uint32_t *) rptr = u.v4; break; default: panic("badaddr: invalid size (%lu)", (u_long) size); } /* Return EFAULT if the address was invalid, else zero */ return (rv); } int cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa) { struct proc *p; register_t *ap; int error; #ifdef __ARM_EABI__ sa->code = td->td_frame->tf_r7; #else sa->code = sa->insn & 0x000fffff; #endif ap = &td->td_frame->tf_r0; if (sa->code == SYS_syscall) { sa->code = *ap++; sa->nap--; } else if (sa->code == SYS___syscall) { sa->code = ap[_QUAD_LOWWORD]; sa->nap -= 2; ap += 2; } p = td->td_proc; if (p->p_sysent->sv_mask) sa->code &= p->p_sysent->sv_mask; if (sa->code >= p->p_sysent->sv_size) sa->callp = &p->p_sysent->sv_table[0]; else sa->callp = &p->p_sysent->sv_table[sa->code]; sa->narg = sa->callp->sy_narg; error = 0; memcpy(sa->args, ap, sa->nap * sizeof(register_t)); if (sa->narg > sa->nap) { error = copyin((void *)td->td_frame->tf_usr_sp, sa->args + sa->nap, (sa->narg - sa->nap) * sizeof(register_t)); } if (error == 0) { td->td_retval[0] = 0; td->td_retval[1] = 0; } return (error); } #include "../../kern/subr_syscall.c" static void syscall(struct thread *td, struct trapframe *frame) { struct syscall_args sa; int error; #ifndef __ARM_EABI__ sa.insn = *(uint32_t *)(frame->tf_pc - INSN_SIZE); switch (sa.insn & SWI_OS_MASK) { case 0: /* XXX: we need our own one. */ break; default: call_trapsignal(td, SIGILL, 0); userret(td, frame); return; } #endif sa.nap = 4; error = syscallenter(td, &sa); KASSERT(error != 0 || td->td_ar == NULL, ("returning from syscall with td_ar set!")); syscallret(td, error, &sa); } void swi_handler(struct trapframe *frame) { struct thread *td = curthread; td->td_frame = frame; td->td_pticks = 0; /* * Make sure the program counter is correctly aligned so we * don't take an alignment fault trying to read the opcode. */ if (__predict_false(((frame->tf_pc - INSN_SIZE) & 3) != 0)) { call_trapsignal(td, SIGILL, 0); userret(td, frame); return; } /* * Enable interrupts if they were enabled before the exception. * Since all syscalls *should* come from user mode it will always * be safe to enable them, but check anyway. */ if (td->td_md.md_spinlock_count == 0) { - if (__predict_true(frame->tf_spsr & I32_bit) == 0) - enable_interrupts(I32_bit); - if (__predict_true(frame->tf_spsr & F32_bit) == 0) - enable_interrupts(F32_bit); + if (__predict_true(frame->tf_spsr & PSR_I) == 0) + enable_interrupts(PSR_I); + if (__predict_true(frame->tf_spsr & PSR_F) == 0) + enable_interrupts(PSR_F); } syscall(td, frame); } Index: head/sys/arm/arm/undefined.c =================================================================== --- head/sys/arm/arm/undefined.c (revision 271397) +++ head/sys/arm/arm/undefined.c (revision 271398) @@ -1,291 +1,294 @@ /* $NetBSD: undefined.c,v 1.22 2003/11/29 22:21:29 bjh21 Exp $ */ /*- * Copyright (c) 2001 Ben Harris. * Copyright (c) 1995 Mark Brinicombe. * Copyright (c) 1995 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * undefined.c * * Fault handler * * Created : 06/01/95 */ #include "opt_ddb.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #ifdef KDB #include #endif #include #include +#include #include #include #include #include #include #include #ifdef DDB #include #endif #ifdef KDB #include #endif static int gdb_trapper(u_int, u_int, struct trapframe *, int); LIST_HEAD(, undefined_handler) undefined_handlers[MAX_COPROCS]; void * install_coproc_handler(int coproc, undef_handler_t handler) { struct undefined_handler *uh; KASSERT(coproc >= 0 && coproc < MAX_COPROCS, ("bad coproc")); KASSERT(handler != NULL, ("handler is NULL")); /* Used to be legal. */ /* XXX: M_TEMP??? */ uh = malloc(sizeof(*uh), M_TEMP, M_WAITOK); uh->uh_handler = handler; install_coproc_handler_static(coproc, uh); return uh; } void install_coproc_handler_static(int coproc, struct undefined_handler *uh) { LIST_INSERT_HEAD(&undefined_handlers[coproc], uh, uh_link); } void remove_coproc_handler(void *cookie) { struct undefined_handler *uh = cookie; LIST_REMOVE(uh, uh_link); free(uh, M_TEMP); } static int gdb_trapper(u_int addr, u_int insn, struct trapframe *frame, int code) { struct thread *td; ksiginfo_t ksi; td = (curthread == NULL) ? &thread0 : curthread; if (insn == GDB_BREAKPOINT || insn == GDB5_BREAKPOINT) { if (code == FAULT_USER) { ksiginfo_init_trap(&ksi); ksi.ksi_signo = SIGTRAP; ksi.ksi_code = TRAP_BRKPT; ksi.ksi_addr = (u_int32_t *)addr; trapsignal(td, &ksi); return 0; } #if 0 #ifdef KGDB return !kgdb_trap(T_BREAKPOINT, frame); #endif #endif } return 1; } static struct undefined_handler gdb_uh; void undefined_init() { int loop; /* Not actually necessary -- the initialiser is just NULL */ for (loop = 0; loop < MAX_COPROCS; ++loop) LIST_INIT(&undefined_handlers[loop]); /* Install handler for GDB breakpoints */ gdb_uh.uh_handler = gdb_trapper; install_coproc_handler_static(0, &gdb_uh); } void undefinedinstruction(struct trapframe *frame) { struct thread *td; u_int fault_pc; int fault_instruction; int fault_code; int coprocessor; struct undefined_handler *uh; #ifdef VERBOSE_ARM32 int s; #endif ksiginfo_t ksi; /* Enable interrupts if they were enabled before the exception. */ - if (!(frame->tf_spsr & I32_bit)) - enable_interrupts(I32_bit|F32_bit); + if (__predict_true(frame->tf_spsr & PSR_I) == 0) + enable_interrupts(PSR_I); + if (__predict_true(frame->tf_spsr & PSR_F) == 0) + enable_interrupts(PSR_F); PCPU_INC(cnt.v_trap); fault_pc = frame->tf_pc; /* * Get the current thread/proc structure or thread0/proc0 if there is * none. */ td = curthread == NULL ? &thread0 : curthread; /* * Make sure the program counter is correctly aligned so we * don't take an alignment fault trying to read the opcode. */ if (__predict_false((fault_pc & 3) != 0)) { ksiginfo_init_trap(&ksi); ksi.ksi_signo = SIGILL; ksi.ksi_code = ILL_ILLADR; ksi.ksi_addr = (u_int32_t *)(intptr_t) fault_pc; trapsignal(td, &ksi); userret(td, frame); return; } /* * Should use fuword() here .. but in the interests of squeezing every * bit of speed we will just use ReadWord(). We know the instruction * can be read as was just executed so this will never fail unless the * kernel is screwed up in which case it does not really matter does * it ? */ fault_instruction = *(u_int32_t *)fault_pc; /* Update vmmeter statistics */ #if 0 uvmexp.traps++; #endif /* Check for coprocessor instruction */ /* * According to the datasheets you only need to look at bit 27 of the * instruction to tell the difference between and undefined * instruction and a coprocessor instruction following an undefined * instruction trap. */ coprocessor = 0; if ((fault_instruction & (1 << 27)) != 0) coprocessor = (fault_instruction >> 8) & 0x0f; #ifdef VFP else { /* check for special instructions */ if (((fault_instruction & 0xfe000000) == 0xf2000000) || ((fault_instruction & 0xff100000) == 0xf4000000)) coprocessor = 10; /* vfp / simd */ } #endif /* VFP */ if ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE) { /* * Modify the fault_code to reflect the USR/SVC state at * time of fault. */ fault_code = FAULT_USER; td->td_frame = frame; } else fault_code = 0; /* OK this is were we do something about the instruction. */ LIST_FOREACH(uh, &undefined_handlers[coprocessor], uh_link) if (uh->uh_handler(fault_pc, fault_instruction, frame, fault_code) == 0) break; if (fault_code & FAULT_USER && fault_instruction == PTRACE_BREAKPOINT) { PROC_LOCK(td->td_proc); _PHOLD(td->td_proc); ptrace_clear_single_step(td); _PRELE(td->td_proc); PROC_UNLOCK(td->td_proc); return; } if (uh == NULL && (fault_code & FAULT_USER)) { /* Fault has not been handled */ ksiginfo_init_trap(&ksi); ksi.ksi_signo = SIGILL; ksi.ksi_code = ILL_ILLOPC; ksi.ksi_addr = (u_int32_t *)(intptr_t) fault_pc; trapsignal(td, &ksi); } if ((fault_code & FAULT_USER) == 0) { if (fault_instruction == KERNEL_BREAKPOINT) { #ifdef KDB kdb_trap(T_BREAKPOINT, 0, frame); #else printf("No debugger in kernel.\n"); #endif return; } else panic("Undefined instruction in kernel.\n"); } userret(td, frame); } Index: head/sys/arm/arm/vm_machdep.c =================================================================== --- head/sys/arm/arm/vm_machdep.c (revision 271397) +++ head/sys/arm/arm/vm_machdep.c (revision 271398) @@ -1,348 +1,348 @@ /*- * Copyright (c) 1982, 1986 The Regents of the University of California. * Copyright (c) 1989, 1990 William Jolitz * Copyright (c) 1994 John Dyson * All rights reserved. * * This code is derived from software contributed to Berkeley by * the Systems Programming Group of the University of Utah Computer * Science Department, and William Jolitz. * * Redistribution and use in source and binary :forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Berkeley and its contributors. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)vm_machdep.c 7.3 (Berkeley) 5/13/91 * Utah $Hdr: vm_machdep.c 1.16.1.1 89/06/23$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* * struct switchframe and trapframe must both be a multiple of 8 * for correct stack alignment. */ CTASSERT(sizeof(struct switchframe) == 24); CTASSERT(sizeof(struct trapframe) == 80); /* * Finish a fork operation, with process p2 nearly set up. * Copy and update the pcb, set up the stack so that the child * ready to run and return to user mode. */ void cpu_fork(register struct thread *td1, register struct proc *p2, struct thread *td2, int flags) { struct pcb *pcb2; struct trapframe *tf; struct switchframe *sf; struct mdproc *mdp2; if ((flags & RFPROC) == 0) return; pcb2 = (struct pcb *)(td2->td_kstack + td2->td_kstack_pages * PAGE_SIZE) - 1; #ifdef __XSCALE__ #ifndef CPU_XSCALE_CORE3 pmap_use_minicache(td2->td_kstack, td2->td_kstack_pages * PAGE_SIZE); #endif #endif td2->td_pcb = pcb2; bcopy(td1->td_pcb, pcb2, sizeof(*pcb2)); mdp2 = &p2->p_md; bcopy(&td1->td_proc->p_md, mdp2, sizeof(*mdp2)); pcb2->un_32.pcb32_sp = td2->td_kstack + USPACE_SVC_STACK_TOP - sizeof(*pcb2); pcb2->pcb_vfpcpu = -1; pcb2->pcb_vfpstate.fpscr = VFPSCR_DN | VFPSCR_FZ; pmap_activate(td2); td2->td_frame = tf = (struct trapframe *)STACKALIGN( pcb2->un_32.pcb32_sp - sizeof(struct trapframe)); *tf = *td1->td_frame; sf = (struct switchframe *)tf - 1; sf->sf_r4 = (u_int)fork_return; sf->sf_r5 = (u_int)td2; sf->sf_pc = (u_int)fork_trampoline; - tf->tf_spsr &= ~PSR_C_bit; + tf->tf_spsr &= ~PSR_C; tf->tf_r0 = 0; tf->tf_r1 = 0; pcb2->un_32.pcb32_sp = (u_int)sf; KASSERT((pcb2->un_32.pcb32_sp & 7) == 0, ("cpu_fork: Incorrect stack alignment")); /* Setup to release spin count in fork_exit(). */ td2->td_md.md_spinlock_count = 1; td2->td_md.md_saved_cspr = 0; #ifdef ARM_TP_ADDRESS td2->td_md.md_tp = *(register_t *)ARM_TP_ADDRESS; #else td2->td_md.md_tp = (register_t) get_tls(); #endif } void cpu_thread_swapin(struct thread *td) { } void cpu_thread_swapout(struct thread *td) { } void cpu_set_syscall_retval(struct thread *td, int error) { struct trapframe *frame; int fixup; #ifdef __ARMEB__ u_int call; #endif frame = td->td_frame; fixup = 0; #ifdef __ARMEB__ /* * __syscall returns an off_t while most other syscalls return an * int. As an off_t is 64-bits and an int is 32-bits we need to * place the returned data into r1. As the lseek and frerebsd6_lseek * syscalls also return an off_t they do not need this fixup. */ #ifdef __ARM_EABI__ call = frame->tf_r7; #else call = *(u_int32_t *)(frame->tf_pc - INSN_SIZE) & 0x000fffff; #endif if (call == SYS___syscall) { register_t *ap = &frame->tf_r0; register_t code = ap[_QUAD_LOWWORD]; if (td->td_proc->p_sysent->sv_mask) code &= td->td_proc->p_sysent->sv_mask; fixup = (code != SYS_freebsd6_lseek && code != SYS_lseek) ? 1 : 0; } #endif switch (error) { case 0: if (fixup) { frame->tf_r0 = 0; frame->tf_r1 = td->td_retval[0]; } else { frame->tf_r0 = td->td_retval[0]; frame->tf_r1 = td->td_retval[1]; } - frame->tf_spsr &= ~PSR_C_bit; /* carry bit */ + frame->tf_spsr &= ~PSR_C; /* carry bit */ break; case ERESTART: /* * Reconstruct the pc to point at the swi. */ frame->tf_pc -= INSN_SIZE; break; case EJUSTRETURN: /* nothing to do */ break; default: frame->tf_r0 = error; - frame->tf_spsr |= PSR_C_bit; /* carry bit */ + frame->tf_spsr |= PSR_C; /* carry bit */ break; } } /* * Initialize machine state (pcb and trap frame) for a new thread about to * upcall. Put enough state in the new thread's PCB to get it to go back * userret(), where we can intercept it again to set the return (upcall) * Address and stack, along with those from upcals that are from other sources * such as those generated in thread_userret() itself. */ void cpu_set_upcall(struct thread *td, struct thread *td0) { struct trapframe *tf; struct switchframe *sf; bcopy(td0->td_frame, td->td_frame, sizeof(struct trapframe)); bcopy(td0->td_pcb, td->td_pcb, sizeof(struct pcb)); tf = td->td_frame; sf = (struct switchframe *)tf - 1; sf->sf_r4 = (u_int)fork_return; sf->sf_r5 = (u_int)td; sf->sf_pc = (u_int)fork_trampoline; - tf->tf_spsr &= ~PSR_C_bit; + tf->tf_spsr &= ~PSR_C; tf->tf_r0 = 0; td->td_pcb->un_32.pcb32_sp = (u_int)sf; KASSERT((td->td_pcb->un_32.pcb32_sp & 7) == 0, ("cpu_set_upcall: Incorrect stack alignment")); /* Setup to release spin count in fork_exit(). */ td->td_md.md_spinlock_count = 1; td->td_md.md_saved_cspr = 0; } /* * Set that machine state for performing an upcall that has to * be done in thread_userret() so that those upcalls generated * in thread_userret() itself can be done as well. */ void cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg, stack_t *stack) { struct trapframe *tf = td->td_frame; tf->tf_usr_sp = STACKALIGN((int)stack->ss_sp + stack->ss_size - sizeof(struct trapframe)); tf->tf_pc = (int)entry; tf->tf_r0 = (int)arg; tf->tf_spsr = PSR_USR32_MODE; } int cpu_set_user_tls(struct thread *td, void *tls_base) { td->td_md.md_tp = (register_t)tls_base; if (td == curthread) { critical_enter(); #ifdef ARM_TP_ADDRESS *(register_t *)ARM_TP_ADDRESS = (register_t)tls_base; #else set_tls((void *)tls_base); #endif critical_exit(); } return (0); } void cpu_thread_exit(struct thread *td) { } void cpu_thread_alloc(struct thread *td) { td->td_pcb = (struct pcb *)(td->td_kstack + td->td_kstack_pages * PAGE_SIZE) - 1; /* * Ensure td_frame is aligned to an 8 byte boundary as it will be * placed into the stack pointer which must be 8 byte aligned in * the ARM EABI. */ td->td_frame = (struct trapframe *)STACKALIGN((u_int)td->td_kstack + USPACE_SVC_STACK_TOP - sizeof(struct pcb) - sizeof(struct trapframe)); #ifdef __XSCALE__ #ifndef CPU_XSCALE_CORE3 pmap_use_minicache(td->td_kstack, td->td_kstack_pages * PAGE_SIZE); #endif #endif } void cpu_thread_free(struct thread *td) { } void cpu_thread_clean(struct thread *td) { } /* * Intercept the return address from a freshly forked process that has NOT * been scheduled yet. * * This is needed to make kernel threads stay in kernel mode. */ void cpu_set_fork_handler(struct thread *td, void (*func)(void *), void *arg) { struct switchframe *sf; struct trapframe *tf; tf = td->td_frame; sf = (struct switchframe *)tf - 1; sf->sf_r4 = (u_int)func; sf->sf_r5 = (u_int)arg; td->td_pcb->un_32.pcb32_sp = (u_int)sf; KASSERT((td->td_pcb->un_32.pcb32_sp & 7) == 0, ("cpu_set_fork_handler: Incorrect stack alignment")); } /* * Software interrupt handler for queued VM system processing. */ void swi_vm(void *dummy) { if (busdma_swi_pending) busdma_swi(); } void cpu_exit(struct thread *td) { } Index: head/sys/arm/at91/at91.c =================================================================== --- head/sys/arm/at91/at91.c (revision 271397) +++ head/sys/arm/at91/at91.c (revision 271398) @@ -1,533 +1,534 @@ /*- * Copyright (c) 2005 Olivier Houchard. All rights reserved. * Copyright (c) 2010 Greg Ansley. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include +#include #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include uint32_t at91_master_clock; static int at91_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags, bus_space_handle_t *bshp) { vm_paddr_t pa, endpa; pa = trunc_page(bpa); if (pa >= AT91_PA_BASE + 0xff00000) { *bshp = bpa - AT91_PA_BASE + AT91_BASE; return (0); } if (pa >= AT91_BASE + 0xff00000) { *bshp = bpa; return (0); } endpa = round_page(bpa + size); *bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa) + (bpa - pa); return (0); } static void at91_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size) { vm_offset_t va, endva; if (t == 0) return; va = trunc_page((vm_offset_t)t); if (va >= AT91_BASE && va <= AT91_BASE + 0xff00000) return; endva = round_page((vm_offset_t)t + size); /* Free the kernel virtual mapping. */ kva_free(va, endva - va); } static int at91_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) { *nbshp = bsh + offset; return (0); } static void at91_barrier(void *t, bus_space_handle_t bsh, bus_size_t size, bus_size_t b, int a) { } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } int bus_dma_get_range_nb(void) { return (0); } bs_protos(generic); bs_protos(generic_armv4); struct bus_space at91_bs_tag = { /* cookie */ (void *) 0, /* mapping/unmapping */ at91_bs_map, at91_bs_unmap, at91_bs_subregion, /* allocation/deallocation */ NULL, NULL, /* barrier */ at91_barrier, /* read (single) */ generic_bs_r_1, generic_armv4_bs_r_2, generic_bs_r_4, NULL, /* read multiple */ generic_bs_rm_1, generic_armv4_bs_rm_2, generic_bs_rm_4, NULL, /* read region */ generic_bs_rr_1, generic_armv4_bs_rr_2, generic_bs_rr_4, NULL, /* write (single) */ generic_bs_w_1, generic_armv4_bs_w_2, generic_bs_w_4, NULL, /* write multiple */ generic_bs_wm_1, generic_armv4_bs_wm_2, generic_bs_wm_4, NULL, /* write region */ NULL, generic_armv4_bs_wr_2, generic_bs_wr_4, NULL, /* set multiple */ NULL, NULL, NULL, NULL, /* set region */ NULL, generic_armv4_bs_sr_2, generic_bs_sr_4, NULL, /* copy */ NULL, generic_armv4_bs_c_2, NULL, NULL, /* read (single) stream */ generic_bs_r_1, generic_armv4_bs_r_2, generic_bs_r_4, NULL, /* read multiple stream */ generic_bs_rm_1, generic_armv4_bs_rm_2, generic_bs_rm_4, NULL, /* read region stream */ generic_bs_rr_1, generic_armv4_bs_rr_2, generic_bs_rr_4, NULL, /* write (single) stream */ generic_bs_w_1, generic_armv4_bs_w_2, generic_bs_w_4, NULL, /* write multiple stream */ generic_bs_wm_1, generic_armv4_bs_wm_2, generic_bs_wm_4, NULL, /* write region stream */ NULL, generic_armv4_bs_wr_2, generic_bs_wr_4, NULL, }; #ifndef FDT static struct at91_softc *at91_softc; static void at91_eoi(void *); static int at91_probe(device_t dev) { device_set_desc(dev, soc_info.name); return (BUS_PROBE_NOWILDCARD); } static void at91_identify(driver_t *drv, device_t parent) { BUS_ADD_CHILD(parent, 0, "atmelarm", 0); } static void at91_cpu_add_builtin_children(device_t dev, const struct cpu_devs *walker) { int i; for (i = 0; walker->name; i++, walker++) { at91_add_child(dev, i, walker->name, walker->unit, walker->mem_base, walker->mem_len, walker->irq0, walker->irq1, walker->irq2); } } static int at91_attach(device_t dev) { struct at91_softc *sc = device_get_softc(dev); arm_post_filter = at91_eoi; at91_softc = sc; sc->sc_st = &at91_bs_tag; sc->sc_sh = AT91_BASE; sc->sc_aic_sh = AT91_BASE + AT91_SYS_BASE; sc->dev = dev; sc->sc_irq_rman.rm_type = RMAN_ARRAY; sc->sc_irq_rman.rm_descr = "AT91 IRQs"; if (rman_init(&sc->sc_irq_rman) != 0 || rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0) panic("at91_attach: failed to set up IRQ rman"); sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "AT91 Memory"; if (rman_init(&sc->sc_mem_rman) != 0) panic("at91_attach: failed to set up memory rman"); /* * Manage the physical space, defined as being everything that isn't * DRAM. */ if (rman_manage_region(&sc->sc_mem_rman, 0, PHYSADDR - 1) != 0) panic("at91_attach: failed to set up memory rman"); if (rman_manage_region(&sc->sc_mem_rman, PHYSADDR + (256 << 20), 0xfffffffful) != 0) panic("at91_attach: failed to set up memory rman"); /* * Add this device's children... */ at91_cpu_add_builtin_children(dev, soc_info.soc_data->soc_children); soc_info.soc_data->soc_clock_init(); bus_generic_probe(dev); bus_generic_attach(dev); - enable_interrupts(I32_bit | F32_bit); + enable_interrupts(PSR_I | PSR_F); return (0); } static struct resource * at91_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct at91_softc *sc = device_get_softc(dev); struct resource_list_entry *rle; struct at91_ivar *ivar = device_get_ivars(child); struct resource_list *rl = &ivar->resources; bus_space_handle_t bsh; if (device_get_parent(child) != dev) return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, start, end, count, flags)); rle = resource_list_find(rl, type, *rid); if (rle == NULL) return (NULL); if (rle->res) panic("Resource rid %d type %d already in use", *rid, type); if (start == 0UL && end == ~0UL) { start = rle->start; count = ulmax(count, rle->count); end = ulmax(rle->end, start + count - 1); } switch (type) { case SYS_RES_IRQ: rle->res = rman_reserve_resource(&sc->sc_irq_rman, start, end, count, flags, child); break; case SYS_RES_MEMORY: rle->res = rman_reserve_resource(&sc->sc_mem_rman, start, end, count, flags, child); if (rle->res != NULL) { bus_space_map(&at91_bs_tag, start, rman_get_size(rle->res), 0, &bsh); rman_set_bustag(rle->res, &at91_bs_tag); rman_set_bushandle(rle->res, bsh); } break; } if (rle->res) { rle->start = rman_get_start(rle->res); rle->end = rman_get_end(rle->res); rle->count = count; rman_set_rid(rle->res, *rid); } return (rle->res); } static struct resource_list * at91_get_resource_list(device_t dev, device_t child) { struct at91_ivar *ivar; ivar = device_get_ivars(child); return (&(ivar->resources)); } static int at91_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct resource_list *rl; struct resource_list_entry *rle; rl = at91_get_resource_list(dev, child); if (rl == NULL) return (EINVAL); rle = resource_list_find(rl, type, rid); if (rle == NULL) return (EINVAL); rman_release_resource(r); rle->res = NULL; return (0); } static int at91_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error; if (rman_get_start(ires) == AT91_IRQ_SYSTEM && filt == NULL) panic("All system interrupt ISRs must be FILTER"); error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep); if (error) return (error); return (0); } static int at91_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { struct at91_softc *sc = device_get_softc(dev); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 1 << rman_get_start(res)); return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static int at91_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { #if 0 u_long p; int error; if (type == SYS_RES_MEMORY) { error = bus_space_map(rman_get_bustag(r), rman_get_bushandle(r), rman_get_size(r), 0, &p); if (error) return (error); rman_set_bushandle(r, p); } #endif return (rman_activate_resource(r)); } static int at91_print_child(device_t dev, device_t child) { struct at91_ivar *ivars; struct resource_list *rl; int retval = 0; ivars = device_get_ivars(child); rl = &ivars->resources; retval += bus_print_child_header(dev, child); retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); if (device_get_flags(dev)) retval += printf(" flags %#x", device_get_flags(dev)); retval += bus_print_child_footer(dev, child); return (retval); } static void at91_eoi(void *unused) { bus_space_write_4(at91_softc->sc_st, at91_softc->sc_aic_sh, IC_EOICR, 0); } void at91_add_child(device_t dev, int prio, const char *name, int unit, bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2) { device_t kid; struct at91_ivar *ivar; kid = device_add_child_ordered(dev, prio, name, unit); if (kid == NULL) { printf("Can't add child %s%d ordered\n", name, unit); return; } ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO); if (ivar == NULL) { device_delete_child(dev, kid); printf("Can't add alloc ivar\n"); return; } device_set_ivars(kid, ivar); resource_list_init(&ivar->resources); if (irq0 != -1) { bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1); if (irq0 != AT91_IRQ_SYSTEM) at91_pmc_clock_add(device_get_nameunit(kid), irq0, 0); } if (irq1 != 0) bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1); if (irq2 != 0) bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1); /* * Special case for on-board devices. These have their address * defined relative to AT91_PA_BASE in all the register files we * have. We could change this, but that's a lot of effort which * will be obsoleted when FDT arrives. */ if (addr != 0 && addr < 0x10000000 && addr >= 0x0f000000) addr += AT91_PA_BASE; if (addr != 0) bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size); } static device_method_t at91_methods[] = { DEVMETHOD(device_probe, at91_probe), DEVMETHOD(device_attach, at91_attach), DEVMETHOD(device_identify, at91_identify), DEVMETHOD(bus_alloc_resource, at91_alloc_resource), DEVMETHOD(bus_setup_intr, at91_setup_intr), DEVMETHOD(bus_teardown_intr, at91_teardown_intr), DEVMETHOD(bus_activate_resource, at91_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_get_resource_list,at91_get_resource_list), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_release_resource, at91_release_resource), DEVMETHOD(bus_print_child, at91_print_child), {0, 0}, }; static driver_t at91_driver = { "atmelarm", at91_methods, sizeof(struct at91_softc), }; static devclass_t at91_devclass; DRIVER_MODULE(atmelarm, nexus, at91_driver, at91_devclass, 0, 0); #endif Index: head/sys/arm/at91/at91_aic.c =================================================================== --- head/sys/arm/at91/at91_aic.c (revision 271397) +++ head/sys/arm/at91/at91_aic.c (revision 271398) @@ -1,184 +1,185 @@ /*- * Copyright (c) 2014 Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #include #endif static struct aic_softc { struct resource *mem_res; /* Memory resource */ void *intrhand; /* Interrupt handle */ device_t sc_dev; } *sc; static inline uint32_t RD4(struct aic_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct aic_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } void arm_mask_irq(uintptr_t nb) { WR4(sc, IC_IDCR, 1 << nb); } int arm_get_next_irq(int last __unused) { int status; int irq; irq = RD4(sc, IC_IVR); status = RD4(sc, IC_ISR); if (status == 0) { WR4(sc, IC_EOICR, 1); return (-1); } return (irq); } void arm_unmask_irq(uintptr_t nb) { WR4(sc, IC_IECR, 1 << nb); WR4(sc, IC_EOICR, 0); } static int at91_aic_probe(device_t dev) { #ifdef FDT if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-aic")) return (ENXIO); #endif device_set_desc(dev, "AIC"); return (0); } static int at91_aic_attach(device_t dev) { int i, rid, err = 0; device_printf(dev, "Attach %d\n", bus_current_pass); sc = device_get_softc(dev); sc->sc_dev = dev; rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) panic("couldn't allocate register resources"); /* * Setup the interrupt table. */ if (soc_info.soc_data == NULL || soc_info.soc_data->soc_irq_prio == NULL) panic("Interrupt priority table missing\n"); for (i = 0; i < 32; i++) { WR4(sc, IC_SVR + i * 4, i); /* Priority. */ WR4(sc, IC_SMR + i * 4, soc_info.soc_data->soc_irq_prio[i]); if (i < 8) WR4(sc, IC_EOICR, 1); } WR4(sc, IC_SPU, 32); /* No debug. */ WR4(sc, IC_DCR, 0); /* Disable and clear all interrupts. */ WR4(sc, IC_IDCR, 0xffffffff); WR4(sc, IC_ICCR, 0xffffffff); - enable_interrupts(I32_bit | F32_bit); + enable_interrupts(PSR_I | PSR_F); return (err); } static void at91_aic_new_pass(device_t dev) { device_printf(dev, "Pass %d\n", bus_current_pass); } static device_method_t at91_aic_methods[] = { DEVMETHOD(device_probe, at91_aic_probe), DEVMETHOD(device_attach, at91_aic_attach), DEVMETHOD(bus_new_pass, at91_aic_new_pass), DEVMETHOD_END }; static driver_t at91_aic_driver = { "at91_aic", at91_aic_methods, sizeof(struct aic_softc), }; static devclass_t at91_aic_devclass; #ifdef FDT EARLY_DRIVER_MODULE(at91_aic, simplebus, at91_aic_driver, at91_aic_devclass, NULL, NULL, BUS_PASS_INTERRUPT); #else EARLY_DRIVER_MODULE(at91_aic, atmelarm, at91_aic_driver, at91_aic_devclass, NULL, NULL, BUS_PASS_INTERRUPT); #endif Index: head/sys/arm/cavium/cns11xx/econa.c =================================================================== --- head/sys/arm/cavium/cns11xx/econa.c (revision 271397) +++ head/sys/arm/cavium/cns11xx/econa.c (revision 271398) @@ -1,759 +1,760 @@ /*- * Copyright (c) 2009 Yohanes Nugroho * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #define _ARM32_BUS_DMA_PRIVATE +#include #include #include #include #include "econa_reg.h" #include "econa_var.h" static struct econa_softc *econa_softc; unsigned int CPU_clock = 200000000; unsigned int AHB_clock; unsigned int APB_clock; bs_protos(generic); bs_protos(generic_armv4); struct bus_space econa_bs_tag = { /* cookie */ (void *) 0, /* mapping/unmapping */ generic_bs_map, generic_bs_unmap, generic_bs_subregion, /* allocation/deallocation */ generic_bs_alloc, generic_bs_free, /* barrier */ generic_bs_barrier, /* read (single) */ generic_bs_r_1, generic_armv4_bs_r_2, generic_bs_r_4, NULL, /* read multiple */ generic_bs_rm_1, generic_armv4_bs_rm_2, generic_bs_rm_4, NULL, /* read region */ generic_bs_rr_1, generic_armv4_bs_rr_2, generic_bs_rr_4, NULL, /* write (single) */ generic_bs_w_1, generic_armv4_bs_w_2, generic_bs_w_4, NULL, /* write multiple */ generic_bs_wm_1, generic_armv4_bs_wm_2, generic_bs_wm_4, NULL, /* write region */ NULL, NULL, NULL, NULL, /* set multiple */ NULL, NULL, NULL, NULL, /* set region */ NULL, NULL, NULL, NULL, /* copy */ NULL, NULL, NULL, NULL, /* read (single) stream */ NULL, NULL, NULL, NULL, /* read multiple stream */ NULL, generic_armv4_bs_rm_2, NULL, NULL, /* read region stream */ NULL, NULL, NULL, NULL, /* write (single) stream */ NULL, NULL, NULL, NULL, /* write multiple stream */ NULL, generic_armv4_bs_wm_2, NULL, NULL, /* write region stream */ NULL, NULL, NULL, NULL }; bus_space_tag_t obio_tag = &econa_bs_tag; static int econa_probe(device_t dev) { device_set_desc(dev, "ECONA device bus"); return (BUS_PROBE_NOWILDCARD); } static void econa_identify(driver_t *drv, device_t parent) { BUS_ADD_CHILD(parent, 0, "econaarm", 0); } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } int bus_dma_get_range_nb(void) { return (0); } extern void irq_entry(void); static void econa_add_child(device_t dev, int prio, const char *name, int unit, bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2, int irq3, int irq4) { device_t kid; struct econa_ivar *ivar; kid = device_add_child_ordered(dev, prio, name, unit); if (kid == NULL) { printf("Can't add child %s%d ordered\n", name, unit); return; } ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO); if (ivar == NULL) { device_delete_child(dev, kid); return; } device_set_ivars(kid, ivar); resource_list_init(&ivar->resources); if (irq0 != -1) bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1); if (irq1 != 0) bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1); if (irq2 != 0) bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1); if (irq3 != 0) bus_set_resource(kid, SYS_RES_IRQ, 3, irq3, 1); if (irq4 != 0) bus_set_resource(kid, SYS_RES_IRQ, 4, irq4, 1); if (addr != 0) bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size); } struct cpu_devs { const char *name; int unit; bus_addr_t mem_base; bus_size_t mem_len; int irq0; int irq1; int irq2; int irq3; int irq4; }; struct cpu_devs econarm_devs[] = { { "econa_ic", 0, ECONA_IO_BASE + ECONA_PIC_BASE, ECONA_PIC_SIZE, 0 }, { "system", 0, ECONA_IO_BASE + ECONA_SYSTEM_BASE, ECONA_SYSTEM_SIZE, 0 }, { "uart", 0, ECONA_IO_BASE + ECONA_UART_BASE, ECONA_UART_SIZE, ECONA_IRQ_UART }, { "timer", 0, ECONA_IO_BASE + ECONA_TIMER_BASE, ECONA_TIMER_SIZE, ECONA_IRQ_TIMER_1, ECONA_IRQ_TIMER_2 }, { "ohci", 0, ECONA_OHCI_VBASE, ECONA_OHCI_SIZE, ECONA_IRQ_OHCI }, { "ehci", 0, ECONA_EHCI_VBASE, ECONA_EHCI_SIZE, ECONA_IRQ_EHCI }, { "cfi", 0, ECONA_CFI_VBASE, ECONA_CFI_SIZE, 0 }, { "ece", 0, ECONA_IO_BASE + ECONA_NET_BASE, ECONA_NET_SIZE, ECONA_IRQ_STATUS, ECONA_IRQ_TSTC, ECONA_IRQ_FSRC, ECONA_IRQ_TSQE, ECONA_IRQ_FSQF, }, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } }; static void econa_cpu_add_builtin_children(device_t dev, struct econa_softc *sc) { int i; struct cpu_devs *walker; for (i = 0, walker = econarm_devs; walker->name; i++, walker++) { econa_add_child(dev, i, walker->name, walker->unit, walker->mem_base, walker->mem_len, walker->irq0,walker->irq1, walker->irq2, walker->irq3, walker->irq4); } } struct intc_trigger_t { int mode; int level; }; static struct intc_trigger_t intc_trigger_table[] = { {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_FALLING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_EDGE_TRIGGER, INTC_FALLING_EDGE}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_EDGE_TRIGGER, INTC_RISING_EDGE}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW}, {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW}, }; static inline uint32_t read_4(struct econa_softc *sc, bus_size_t off) { return bus_space_read_4(sc->ec_st, sc->ec_sys_sh, off); } static inline void write_4(struct econa_softc *sc, bus_size_t off, uint32_t val) { return bus_space_write_4(sc->ec_st, sc->ec_sys_sh, off, val); } static inline uint32_t system_read_4(struct econa_softc *sc, bus_size_t off) { return bus_space_read_4(sc->ec_st, sc->ec_system_sh, off); } static inline void system_write_4(struct econa_softc *sc, bus_size_t off, uint32_t val) { return bus_space_write_4(sc->ec_st, sc->ec_system_sh, off, val); } static inline void econa_set_irq_mode(struct econa_softc * sc, unsigned int irq, unsigned int mode) { unsigned int val; if ((mode != INTC_LEVEL_TRIGGER) && (mode != INTC_EDGE_TRIGGER)) return; val = read_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET); if (mode == INTC_LEVEL_TRIGGER) { if (val & (1UL << irq)) { val &= ~(1UL << irq); write_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET, val); } } else { if (!(val & (1UL << irq))) { val |= (1UL << irq); write_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET, val); } } } /* * Configure interrupt trigger level to be Active High/Low * or Rising/Falling Edge */ static inline void econa_set_irq_level(struct econa_softc * sc, unsigned int irq, unsigned int level) { unsigned int val; if ((level != INTC_ACTIVE_HIGH) && (level != INTC_ACTIVE_LOW) && (level != INTC_RISING_EDGE) && (level != INTC_FALLING_EDGE)) { return; } val = read_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET); if ((level == INTC_ACTIVE_HIGH) || (level == INTC_RISING_EDGE)) { if (val & (1UL << irq)) { val &= ~(1UL << irq); write_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET, val); } } else { if (!(val & (1UL << irq))) { val |= (1UL << irq); write_4(sc, INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET, val); } } } static void get_system_clock(void) { uint32_t sclock = system_read_4(econa_softc, SYSTEM_CLOCK); sclock = (sclock >> 6) & 0x03; switch (sclock) { case 0: CPU_clock = 175000000; break; case 1: CPU_clock = 200000000; break; case 2: CPU_clock = 225000000; break; case 3: CPU_clock = 250000000; break; } AHB_clock = CPU_clock >> 1; APB_clock = AHB_clock >> 1; } static int econa_attach(device_t dev) { struct econa_softc *sc = device_get_softc(dev); int i; econa_softc = sc; sc->ec_st = &econa_bs_tag; sc->ec_sh = ECONA_IO_BASE; sc->dev = dev; if (bus_space_subregion(sc->ec_st, sc->ec_sh, ECONA_PIC_BASE, ECONA_PIC_SIZE, &sc->ec_sys_sh) != 0) panic("Unable to map IRQ registers"); if (bus_space_subregion(sc->ec_st, sc->ec_sh, ECONA_SYSTEM_BASE, ECONA_SYSTEM_SIZE, &sc->ec_system_sh) != 0) panic("Unable to map IRQ registers"); sc->ec_irq_rman.rm_type = RMAN_ARRAY; sc->ec_irq_rman.rm_descr = "ECONA IRQs"; sc->ec_mem_rman.rm_type = RMAN_ARRAY; sc->ec_mem_rman.rm_descr = "ECONA Memory"; if (rman_init(&sc->ec_irq_rman) != 0 || rman_manage_region(&sc->ec_irq_rman, 0, 31) != 0) panic("econa_attach: failed to set up IRQ rman"); if (rman_init(&sc->ec_mem_rman) != 0 || rman_manage_region(&sc->ec_mem_rman, 0, ~0) != 0) panic("econa_attach: failed to set up memory rman"); write_4(sc, INTC_INTERRUPT_CLEAR_EDGE_TRIGGER_REG_OFFSET, 0xffffffff); write_4(sc, INTC_INTERRUPT_MASK_REG_OFFSET, 0xffffffff); write_4(sc, INTC_FIQ_MODE_SELECT_REG_OFFSET, 0); /*initialize irq*/ for (i = 0; i < 32; i++) { if (intc_trigger_table[i].mode != INTC_TRIGGER_UNKNOWN) { econa_set_irq_mode(sc,i, intc_trigger_table[i].mode); econa_set_irq_level(sc, i, intc_trigger_table[i].level); } } get_system_clock(); econa_cpu_add_builtin_children(dev, sc); bus_generic_probe(dev); bus_generic_attach(dev); - enable_interrupts(I32_bit | F32_bit); + enable_interrupts(PSR_I | PSR_F); return (0); } static struct resource * econa_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct econa_softc *sc = device_get_softc(dev); struct resource_list_entry *rle; struct econa_ivar *ivar = device_get_ivars(child); struct resource_list *rl = &ivar->resources; if (device_get_parent(child) != dev) return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, start, end, count, flags)); rle = resource_list_find(rl, type, *rid); if (rle == NULL) { return (NULL); } if (rle->res) panic("Resource rid %d type %d already in use", *rid, type); if (start == 0UL && end == ~0UL) { start = rle->start; count = ulmax(count, rle->count); end = ulmax(rle->end, start + count - 1); } switch (type) { case SYS_RES_IRQ: rle->res = rman_reserve_resource(&sc->ec_irq_rman, start, end, count, flags, child); break; case SYS_RES_MEMORY: rle->res = rman_reserve_resource(&sc->ec_mem_rman, start, end, count, flags, child); if (rle->res != NULL) { rman_set_bustag(rle->res, &econa_bs_tag); rman_set_bushandle(rle->res, start); } break; } if (rle->res) { rle->start = rman_get_start(rle->res); rle->end = rman_get_end(rle->res); rle->count = count; rman_set_rid(rle->res, *rid); } return (rle->res); } static struct resource_list * econa_get_resource_list(device_t dev, device_t child) { struct econa_ivar *ivar; ivar = device_get_ivars(child); return (&(ivar->resources)); } static int econa_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct resource_list *rl; struct resource_list_entry *rle; rl = econa_get_resource_list(dev, child); if (rl == NULL) return (EINVAL); rle = resource_list_find(rl, type, rid); if (rle == NULL) return (EINVAL); rman_release_resource(r); rle->res = NULL; return (0); } static int econa_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error; if (rman_get_start(ires) == ECONA_IRQ_SYSTEM && filt == NULL) panic("All system interrupt ISRs must be FILTER"); error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep); if (error) return (error); return (0); } static int econa_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static int econa_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { return (rman_activate_resource(r)); } static int econa_print_child(device_t dev, device_t child) { struct econa_ivar *ivars; struct resource_list *rl; int retval = 0; ivars = device_get_ivars(child); rl = &ivars->resources; retval += bus_print_child_header(dev, child); retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); if (device_get_flags(dev)) retval += printf(" flags %#x", device_get_flags(dev)); retval += bus_print_child_footer(dev, child); return (retval); } void arm_mask_irq(uintptr_t nb) { unsigned int value; value = read_4(econa_softc,INTC_INTERRUPT_MASK_REG_OFFSET) | 1<> 12) & 0xfff) /* D$ info */ #define CPU_CT_S (1U << 24) /* split cache */ #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ #define CPU_CT_FORMAT(x) ((x) >> 29) #define CPU_CT_CTYPE_WT 0 /* write-through */ #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ #define CPU_CT_ARMV7 0x4 /* ARM v7 Cache type definitions */ #define CPUV7_CT_CTYPE_WT (1U << 31) #define CPUV7_CT_CTYPE_WB (1 << 30) #define CPUV7_CT_CTYPE_RA (1 << 29) #define CPUV7_CT_CTYPE_WA (1 << 28) #define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ #define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ #define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ #define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) #define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) #define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) #define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) #define CACHE_ICACHE 1 #define CACHE_DCACHE 2 #define CACHE_SEP_CACHE 3 #define CACHE_UNI_CACHE 4 /* Fault status register definitions */ #define FAULT_TYPE_MASK 0x0f #define FAULT_USER 0x10 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ #define FAULT_ALIGN_0 0x01 /* Alignment */ #define FAULT_ALIGN_1 0x03 /* Alignment */ #define FAULT_TRANS_S 0x05 /* Translation -- Section */ #define FAULT_TRANS_F 0x06 /* Translation -- Flag */ #define FAULT_TRANS_P 0x07 /* Translation -- Page */ #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ #define FAULT_PERM_S 0x0d /* Permission -- Section */ #define FAULT_PERM_P 0x0f /* Permission -- Page */ #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ #define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */ #define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */ /* Fault status register definitions - v6+ */ #define FSR_STATUS_TO_IDX(fsr) (((fsr) & 0xF) | \ (((fsr) & (1 << 10)>> (10 - 4)))) #define FSR_LPAE (1 << 9) /* LPAE indicator */ #define FSR_WNR (1 << 11) /* Write-not-Read access */ #define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ #define FSR_CM (1 << 13) /* Cache maintenance fault */ /* * Address of the vector page, low and high versions. */ #ifndef __ASSEMBLER__ #define ARM_VECTORS_LOW 0x00000000U #define ARM_VECTORS_HIGH 0xffff0000U #else #define ARM_VECTORS_LOW 0 #define ARM_VECTORS_HIGH 0xffff0000 #endif /* * ARM Instructions * * 3 3 2 2 2 * 1 0 9 8 7 0 * +-------+-------------------------------------------------------+ * | cond | instruction dependant | * |c c c c| | * +-------+-------------------------------------------------------+ */ #define INSN_SIZE 4 /* Always 4 bytes */ #define INSN_COND_MASK 0xf0000000 /* Condition mask */ #define INSN_COND_AL 0xe0000000 /* Always condition */ #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ #endif /* !MACHINE_ARMREG_H */ Index: head/sys/arm/include/asm.h =================================================================== --- head/sys/arm/include/asm.h (revision 271397) +++ head/sys/arm/include/asm.h (revision 271398) @@ -1,209 +1,206 @@ /* $NetBSD: asm.h,v 1.5 2003/08/07 16:26:53 agc Exp $ */ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)asm.h 5.5 (Berkeley) 5/7/91 * * $FreeBSD$ */ #ifndef _MACHINE_ASM_H_ #define _MACHINE_ASM_H_ #include #define _C_LABEL(x) x #define _ASM_LABEL(x) x -#define I32_bit (1 << 7) /* IRQ disable */ -#define F32_bit (1 << 6) /* FIQ disable */ - #ifndef _ALIGN_TEXT # define _ALIGN_TEXT .align 0 #endif #if defined(__ARM_EABI__) && !defined(_STANDALONE) #define STOP_UNWINDING .cantunwind #define _FNSTART .fnstart #define _FNEND .fnend #else #define STOP_UNWINDING #define _FNSTART #define _FNEND #endif /* * gas/arm uses @ as a single comment character and thus cannot be used here * Instead it recognised the # instead of an @ symbols in .type directives * We define a couple of macros so that assembly code will not be dependent * on one or the other. */ #define _ASM_TYPE_FUNCTION #function #define _ASM_TYPE_OBJECT #object #define GLOBAL(X) .globl x #define _ENTRY(x) \ .text; _ALIGN_TEXT; .globl x; .type x,_ASM_TYPE_FUNCTION; x: _FNSTART #define _END(x) .size x, . - x; _FNEND /* * EENTRY()/EEND() mark "extra" entry/exit points from a function. * The unwind info cannot handle the concept of a nested function, or a function * with multiple .fnstart directives, but some of our assembler code is written * with multiple labels to allow entry at several points. The EENTRY() macro * defines such an extra entry point without a new .fnstart, so that it's * basically just a label that you can jump to. The EEND() macro does nothing * at all, except document the exit point associated with the same-named entry. */ #define _EENTRY(x) .globl x; .type x,_ASM_TYPE_FUNCTION; x: #define _EEND(x) /* nothing */ #ifdef GPROF # define _PROF_PROLOGUE \ mov ip, lr; bl __mcount #else # define _PROF_PROLOGUE #endif #define ENTRY(y) _ENTRY(_C_LABEL(y)); _PROF_PROLOGUE #define EENTRY(y) _EENTRY(_C_LABEL(y)); _PROF_PROLOGUE #define ENTRY_NP(y) _ENTRY(_C_LABEL(y)) #define EENTRY_NP(y) _EENTRY(_C_LABEL(y)) #define END(y) _END(_C_LABEL(y)) #define EEND(y) #define ASENTRY(y) _ENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE #define ASEENTRY(y) _EENTRY(_ASM_LABEL(y)); _PROF_PROLOGUE #define ASENTRY_NP(y) _ENTRY(_ASM_LABEL(y)) #define ASEENTRY_NP(y) _EENTRY(_ASM_LABEL(y)) #define ASEND(y) _END(_ASM_LABEL(y)) #define ASEEND(y) #define ASMSTR .asciz #if defined(PIC) #define PLT_SYM(x) PIC_SYM(x, PLT) #define GOT_SYM(x) PIC_SYM(x, GOT) #define GOT_GET(x,got,sym) \ ldr x, sym; \ ldr x, [x, got] #define GOT_INIT(got,gotsym,pclabel) \ ldr got, gotsym; \ add got, got, pc; \ pclabel: #define GOT_INITSYM(gotsym,pclabel) \ gotsym: .word _C_LABEL(_GLOBAL_OFFSET_TABLE_) + (. - (pclabel+4)) #ifdef __STDC__ #define PIC_SYM(x,y) x ## ( ## y ## ) #else #define PIC_SYM(x,y) x/**/(/**/y/**/) #endif #else #define PLT_SYM(x) x #define GOT_SYM(x) x #define GOT_GET(x,got,sym) \ ldr x, sym; #define GOT_INIT(got,gotsym,pclabel) #define GOT_INITSYM(gotsym,pclabel) #define PIC_SYM(x,y) x #endif /* PIC */ #undef __FBSDID #if !defined(lint) && !defined(STRIP_FBSDID) #define __FBSDID(s) .ident s #else #define __FBSDID(s) /* nothing */ #endif #define WEAK_ALIAS(alias,sym) \ .weak alias; \ alias = sym #ifdef __STDC__ #define WARN_REFERENCES(sym,msg) \ .stabs msg ## ,30,0,0,0 ; \ .stabs __STRING(_C_LABEL(sym)) ## ,1,0,0,0 #else #define WARN_REFERENCES(sym,msg) \ .stabs msg,30,0,0,0 ; \ .stabs __STRING(sym),1,0,0,0 #endif /* __STDC__ */ /* Exactly one of the __ARM_ARCH_*__ macros will be defined by the compiler. */ /* The _ARM_ARCH_* macros are deprecated and will be removed soon. */ /* This should be moved into another header so it can be used in * both asm and C code. machine/asm.h cannot be included in C code. */ #if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) #define _ARM_ARCH_7 #define _HAVE_ARMv7_INSTRUCTIONS 1 #endif #if defined (_HAVE_ARMv7_INSTRUCTIONS) || defined (__ARM_ARCH_6__) || \ defined (__ARM_ARCH_6J__) || defined (__ARM_ARCH_6K__) || \ defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) #define _ARM_ARCH_6 #define _HAVE_ARMv6_INSTRUCTIONS 1 #endif #if defined (_HAVE_ARMv6_INSTRUCTIONS) || defined (__ARM_ARCH_5TE__) || \ defined (__ARM_ARCH_5TEJ__) || defined (__ARM_ARCH_5E__) #define _ARM_ARCH_5E #define _HAVE_ARMv5E_INSTRUCTIONS 1 #endif #if defined (_HAVE_ARMv5E_INSTRUCTIONS) || defined (__ARM_ARCH_5__) || \ defined (__ARM_ARCH_5T__) #define _ARM_ARCH_5 #define _HAVE_ARMv5_INSTRUCTIONS 1 #endif #if defined (_HAVE_ARMv5_INSTRUCTIONS) || defined (__ARM_ARCH_4T__) #define _ARM_ARCH_4T #define _HAVE_ARMv4T_INSTRUCTIONS 1 #endif /* FreeBSD requires ARMv4, so this is always set. */ #define _HAVE_ARMv4_INSTRUCTIONS 1 #if defined (_HAVE_ARMv4T_INSTRUCTIONS) # define RET bx lr # define RETeq bxeq lr # define RETne bxne lr # define RETc(c) bx##c lr #else # define RET mov pc, lr # define RETeq moveq pc, lr # define RETne movne pc, lr # define RETc(c) mov##c pc, lr #endif #endif /* !_MACHINE_ASM_H_ */ Index: head/sys/arm/include/atomic.h =================================================================== --- head/sys/arm/include/atomic.h (revision 271397) +++ head/sys/arm/include/atomic.h (revision 271398) @@ -1,1138 +1,1134 @@ /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ /*- * Copyright (C) 2003-2004 Olivier Houchard * Copyright (C) 1994-1997 Mark Brinicombe * Copyright (C) 1994 Brini * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of Brini may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_ATOMIC_H_ #define _MACHINE_ATOMIC_H_ #include +#include #ifndef _KERNEL #include #else #include #endif #if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) #define isb() __asm __volatile("isb" : : : "memory") #define dsb() __asm __volatile("dsb" : : : "memory") #define dmb() __asm __volatile("dmb" : : : "memory") #elif defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) || \ defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6T2__) || \ defined (__ARM_ARCH_6Z__) || defined (__ARM_ARCH_6ZK__) #define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory") #define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory") #define dmb() __asm __volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory") #else #define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory") #define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory") #define dmb() dsb() #endif #define mb() dmb() #define wmb() dmb() #define rmb() dmb() -#ifndef I32_bit -#define I32_bit (1 << 7) /* IRQ disable */ -#endif -#ifndef F32_bit -#define F32_bit (1 << 6) /* FIQ disable */ -#endif + /* * It would be nice to use _HAVE_ARMv6_INSTRUCTIONS from machine/asm.h * here, but that header can't be included here because this is C * code. I would like to move the _HAVE_ARMv6_INSTRUCTIONS definition * out of asm.h so it can be used in both asm and C code. - kientzle@ */ #if defined (__ARM_ARCH_7__) || \ defined (__ARM_ARCH_7A__) || \ defined (__ARM_ARCH_6__) || \ defined (__ARM_ARCH_6J__) || \ defined (__ARM_ARCH_6K__) || \ defined (__ARM_ARCH_6T2__) || \ defined (__ARM_ARCH_6Z__) || \ defined (__ARM_ARCH_6ZK__) #define ARM_HAVE_ATOMIC64 static __inline void __do_dmb(void) { #if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__) __asm __volatile("dmb" : : : "memory"); #else __asm __volatile("mcr p15, 0, r0, c7, c10, 5" : : : "memory"); #endif } #define ATOMIC_ACQ_REL_LONG(NAME) \ static __inline void \ atomic_##NAME##_acq_long(__volatile u_long *p, u_long v) \ { \ atomic_##NAME##_long(p, v); \ __do_dmb(); \ } \ \ static __inline void \ atomic_##NAME##_rel_long(__volatile u_long *p, u_long v) \ { \ __do_dmb(); \ atomic_##NAME##_long(p, v); \ } #define ATOMIC_ACQ_REL(NAME, WIDTH) \ static __inline void \ atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ { \ atomic_##NAME##_##WIDTH(p, v); \ __do_dmb(); \ } \ \ static __inline void \ atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ { \ __do_dmb(); \ atomic_##NAME##_##WIDTH(p, v); \ } static __inline void atomic_set_32(volatile uint32_t *address, uint32_t setmask) { uint32_t tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%2]\n" "orr %0, %0, %3\n" "strex %1, %0, [%2]\n" "cmp %1, #0\n" "it ne\n" "bne 1b\n" : "=&r" (tmp), "+r" (tmp2) , "+r" (address), "+r" (setmask) : : "cc", "memory"); } static __inline void atomic_set_64(volatile uint64_t *p, uint64_t val) { uint64_t tmp; uint32_t exflag; __asm __volatile( "1: \n" " ldrexd %[tmp], [%[ptr]]\n" " orr %Q[tmp], %Q[val]\n" " orr %R[tmp], %R[val]\n" " strexd %[exf], %[tmp], [%[ptr]]\n" " teq %[exf], #0\n" " it ne \n" " bne 1b\n" : [exf] "=&r" (exflag), [tmp] "=&r" (tmp) : [ptr] "r" (p), [val] "r" (val) : "cc", "memory"); } static __inline void atomic_set_long(volatile u_long *address, u_long setmask) { u_long tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%2]\n" "orr %0, %0, %3\n" "strex %1, %0, [%2]\n" "cmp %1, #0\n" "it ne\n" "bne 1b\n" : "=&r" (tmp), "+r" (tmp2) , "+r" (address), "+r" (setmask) : : "cc", "memory"); } static __inline void atomic_clear_32(volatile uint32_t *address, uint32_t setmask) { uint32_t tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%2]\n" "bic %0, %0, %3\n" "strex %1, %0, [%2]\n" "cmp %1, #0\n" "it ne\n" "bne 1b\n" : "=&r" (tmp), "+r" (tmp2) ,"+r" (address), "+r" (setmask) : : "cc", "memory"); } static __inline void atomic_clear_64(volatile uint64_t *p, uint64_t val) { uint64_t tmp; uint32_t exflag; __asm __volatile( "1: \n" " ldrexd %[tmp], [%[ptr]]\n" " bic %Q[tmp], %Q[val]\n" " bic %R[tmp], %R[val]\n" " strexd %[exf], %[tmp], [%[ptr]]\n" " teq %[exf], #0\n" " it ne \n" " bne 1b\n" : [exf] "=&r" (exflag), [tmp] "=&r" (tmp) : [ptr] "r" (p), [val] "r" (val) : "cc", "memory"); } static __inline void atomic_clear_long(volatile u_long *address, u_long setmask) { u_long tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%2]\n" "bic %0, %0, %3\n" "strex %1, %0, [%2]\n" "cmp %1, #0\n" "it ne\n" "bne 1b\n" : "=&r" (tmp), "+r" (tmp2) ,"+r" (address), "+r" (setmask) : : "cc", "memory"); } static __inline u_int32_t atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) { uint32_t ret; __asm __volatile("1: ldrex %0, [%1]\n" "cmp %0, %2\n" "itt ne\n" "movne %0, #0\n" "bne 2f\n" "strex %0, %3, [%1]\n" "cmp %0, #0\n" "ite eq\n" "moveq %0, #1\n" "bne 1b\n" "2:" : "=&r" (ret) ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory"); return (ret); } static __inline int atomic_cmpset_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval) { uint64_t tmp; uint32_t ret; __asm __volatile( "1: \n" " ldrexd %[tmp], [%[ptr]]\n" " teq %Q[tmp], %Q[cmpval]\n" " itee eq \n" " teqeq %R[tmp], %R[cmpval]\n" " movne %[ret], #0\n" " bne 2f\n" " strexd %[ret], %[newval], [%[ptr]]\n" " teq %[ret], #0\n" " it ne \n" " bne 1b\n" " mov %[ret], #1\n" "2: \n" : [ret] "=&r" (ret), [tmp] "=&r" (tmp) : [ptr] "r" (p), [cmpval] "r" (cmpval), [newval] "r" (newval) : "cc", "memory"); return (ret); } static __inline u_long atomic_cmpset_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval) { u_long ret; __asm __volatile("1: ldrex %0, [%1]\n" "cmp %0, %2\n" "itt ne\n" "movne %0, #0\n" "bne 2f\n" "strex %0, %3, [%1]\n" "cmp %0, #0\n" "ite eq\n" "moveq %0, #1\n" "bne 1b\n" "2:" : "=&r" (ret) ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory"); return (ret); } static __inline u_int32_t atomic_cmpset_acq_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) { u_int32_t ret = atomic_cmpset_32(p, cmpval, newval); __do_dmb(); return (ret); } static __inline uint64_t atomic_cmpset_acq_64(volatile uint64_t *p, volatile uint64_t cmpval, volatile uint64_t newval) { uint64_t ret = atomic_cmpset_64(p, cmpval, newval); __do_dmb(); return (ret); } static __inline u_long atomic_cmpset_acq_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval) { u_long ret = atomic_cmpset_long(p, cmpval, newval); __do_dmb(); return (ret); } static __inline u_int32_t atomic_cmpset_rel_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) { __do_dmb(); return (atomic_cmpset_32(p, cmpval, newval)); } static __inline uint64_t atomic_cmpset_rel_64(volatile uint64_t *p, volatile uint64_t cmpval, volatile uint64_t newval) { __do_dmb(); return (atomic_cmpset_64(p, cmpval, newval)); } static __inline u_long atomic_cmpset_rel_long(volatile u_long *p, volatile u_long cmpval, volatile u_long newval) { __do_dmb(); return (atomic_cmpset_long(p, cmpval, newval)); } static __inline void atomic_add_32(volatile u_int32_t *p, u_int32_t val) { uint32_t tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%2]\n" "add %0, %0, %3\n" "strex %1, %0, [%2]\n" "cmp %1, #0\n" "it ne\n" "bne 1b\n" : "=&r" (tmp), "+r" (tmp2) ,"+r" (p), "+r" (val) : : "cc", "memory"); } static __inline void atomic_add_64(volatile uint64_t *p, uint64_t val) { uint64_t tmp; uint32_t exflag; __asm __volatile( "1: \n" " ldrexd %[tmp], [%[ptr]]\n" " adds %Q[tmp], %Q[val]\n" " adc %R[tmp], %R[val]\n" " strexd %[exf], %[tmp], [%[ptr]]\n" " teq %[exf], #0\n" " it ne \n" " bne 1b\n" : [exf] "=&r" (exflag), [tmp] "=&r" (tmp) : [ptr] "r" (p), [val] "r" (val) : "cc", "memory"); } static __inline void atomic_add_long(volatile u_long *p, u_long val) { u_long tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%2]\n" "add %0, %0, %3\n" "strex %1, %0, [%2]\n" "cmp %1, #0\n" "it ne\n" "bne 1b\n" : "=&r" (tmp), "+r" (tmp2) ,"+r" (p), "+r" (val) : : "cc", "memory"); } static __inline void atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) { uint32_t tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%2]\n" "sub %0, %0, %3\n" "strex %1, %0, [%2]\n" "cmp %1, #0\n" "it ne\n" "bne 1b\n" : "=&r" (tmp), "+r" (tmp2) ,"+r" (p), "+r" (val) : : "cc", "memory"); } static __inline void atomic_subtract_64(volatile uint64_t *p, uint64_t val) { uint64_t tmp; uint32_t exflag; __asm __volatile( "1: \n" " ldrexd %[tmp], [%[ptr]]\n" " subs %Q[tmp], %Q[val]\n" " sbc %R[tmp], %R[val]\n" " strexd %[exf], %[tmp], [%[ptr]]\n" " teq %[exf], #0\n" " it ne \n" " bne 1b\n" : [exf] "=&r" (exflag), [tmp] "=&r" (tmp) : [ptr] "r" (p), [val] "r" (val) : "cc", "memory"); } static __inline void atomic_subtract_long(volatile u_long *p, u_long val) { u_long tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%2]\n" "sub %0, %0, %3\n" "strex %1, %0, [%2]\n" "cmp %1, #0\n" "it ne\n" "bne 1b\n" : "=&r" (tmp), "+r" (tmp2) ,"+r" (p), "+r" (val) : : "cc", "memory"); } ATOMIC_ACQ_REL(clear, 32) ATOMIC_ACQ_REL(add, 32) ATOMIC_ACQ_REL(subtract, 32) ATOMIC_ACQ_REL(set, 32) ATOMIC_ACQ_REL(clear, 64) ATOMIC_ACQ_REL(add, 64) ATOMIC_ACQ_REL(subtract, 64) ATOMIC_ACQ_REL(set, 64) ATOMIC_ACQ_REL_LONG(clear) ATOMIC_ACQ_REL_LONG(add) ATOMIC_ACQ_REL_LONG(subtract) ATOMIC_ACQ_REL_LONG(set) #undef ATOMIC_ACQ_REL #undef ATOMIC_ACQ_REL_LONG static __inline uint32_t atomic_fetchadd_32(volatile uint32_t *p, uint32_t val) { uint32_t tmp = 0, tmp2 = 0, ret = 0; __asm __volatile("1: ldrex %0, [%3]\n" "add %1, %0, %4\n" "strex %2, %1, [%3]\n" "cmp %2, #0\n" "it ne\n" "bne 1b\n" : "+r" (ret), "=&r" (tmp), "+r" (tmp2) ,"+r" (p), "+r" (val) : : "cc", "memory"); return (ret); } static __inline uint32_t atomic_readandclear_32(volatile u_int32_t *p) { uint32_t ret, tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%3]\n" "mov %1, #0\n" "strex %2, %1, [%3]\n" "cmp %2, #0\n" "it ne\n" "bne 1b\n" : "=r" (ret), "=&r" (tmp), "+r" (tmp2) ,"+r" (p) : : "cc", "memory"); return (ret); } static __inline uint32_t atomic_load_acq_32(volatile uint32_t *p) { uint32_t v; v = *p; __do_dmb(); return (v); } static __inline void atomic_store_rel_32(volatile uint32_t *p, uint32_t v) { __do_dmb(); *p = v; } static __inline uint64_t atomic_fetchadd_64(volatile uint64_t *p, uint64_t val) { uint64_t ret, tmp; uint32_t exflag; __asm __volatile( "1: \n" " ldrexd %[ret], [%[ptr]]\n" " adds %Q[tmp], %Q[ret], %Q[val]\n" " adc %R[tmp], %R[ret], %R[val]\n" " strexd %[exf], %[tmp], [%[ptr]]\n" " teq %[exf], #0\n" " it ne \n" " bne 1b\n" : [ret] "=&r" (ret), [exf] "=&r" (exflag), [tmp] "=&r" (tmp) : [ptr] "r" (p), [val] "r" (val) : "cc", "memory"); return (ret); } static __inline uint64_t atomic_readandclear_64(volatile uint64_t *p) { uint64_t ret, tmp; uint32_t exflag; __asm __volatile( "1: \n" " ldrexd %[ret], [%[ptr]]\n" " mov %Q[tmp], #0\n" " mov %R[tmp], #0\n" " strexd %[exf], %[tmp], [%[ptr]]\n" " teq %[exf], #0\n" " it ne \n" " bne 1b\n" : [ret] "=&r" (ret), [exf] "=&r" (exflag), [tmp] "=&r" (tmp) : [ptr] "r" (p) : "cc", "memory"); return (ret); } static __inline uint64_t atomic_load_64(volatile uint64_t *p) { uint64_t ret; /* * The only way to atomically load 64 bits is with LDREXD which puts the * exclusive monitor into the open state, so reset it with CLREX because * we don't actually need to store anything. */ __asm __volatile( "1: \n" " ldrexd %[ret], [%[ptr]]\n" " clrex \n" : [ret] "=&r" (ret) : [ptr] "r" (p) : "cc", "memory"); return (ret); } static __inline uint64_t atomic_load_acq_64(volatile uint64_t *p) { uint64_t ret; ret = atomic_load_64(p); __do_dmb(); return (ret); } static __inline void atomic_store_64(volatile uint64_t *p, uint64_t val) { uint64_t tmp; uint32_t exflag; /* * The only way to atomically store 64 bits is with STREXD, which will * succeed only if paired up with a preceeding LDREXD using the same * address, so we read and discard the existing value before storing. */ __asm __volatile( "1: \n" " ldrexd %[tmp], [%[ptr]]\n" " strexd %[exf], %[val], [%[ptr]]\n" " teq %[exf], #0\n" " it ne \n" " bne 1b\n" : [tmp] "=&r" (tmp), [exf] "=&r" (exflag) : [ptr] "r" (p), [val] "r" (val) : "cc", "memory"); } static __inline void atomic_store_rel_64(volatile uint64_t *p, uint64_t val) { __do_dmb(); atomic_store_64(p, val); } static __inline u_long atomic_fetchadd_long(volatile u_long *p, u_long val) { u_long tmp = 0, tmp2 = 0, ret = 0; __asm __volatile("1: ldrex %0, [%3]\n" "add %1, %0, %4\n" "strex %2, %1, [%3]\n" "cmp %2, #0\n" "it ne\n" "bne 1b\n" : "+r" (ret), "=&r" (tmp), "+r" (tmp2) ,"+r" (p), "+r" (val) : : "cc", "memory"); return (ret); } static __inline u_long atomic_readandclear_long(volatile u_long *p) { u_long ret, tmp = 0, tmp2 = 0; __asm __volatile("1: ldrex %0, [%3]\n" "mov %1, #0\n" "strex %2, %1, [%3]\n" "cmp %2, #0\n" "it ne\n" "bne 1b\n" : "=r" (ret), "=&r" (tmp), "+r" (tmp2) ,"+r" (p) : : "cc", "memory"); return (ret); } static __inline u_long atomic_load_acq_long(volatile u_long *p) { u_long v; v = *p; __do_dmb(); return (v); } static __inline void atomic_store_rel_long(volatile u_long *p, u_long v) { __do_dmb(); *p = v; } #else /* < armv6 */ #define __with_interrupts_disabled(expr) \ do { \ u_int cpsr_save, tmp; \ \ __asm __volatile( \ "mrs %0, cpsr;" \ "orr %1, %0, %2;" \ "msr cpsr_fsxc, %1;" \ : "=r" (cpsr_save), "=r" (tmp) \ - : "I" (I32_bit | F32_bit) \ + : "I" (PSR_I | PSR_F) \ : "cc" ); \ (expr); \ __asm __volatile( \ "msr cpsr_fsxc, %0" \ : /* no output */ \ : "r" (cpsr_save) \ : "cc" ); \ } while(0) static __inline uint32_t __swp(uint32_t val, volatile uint32_t *ptr) { __asm __volatile("swp %0, %2, [%3]" : "=&r" (val), "=m" (*ptr) : "r" (val), "r" (ptr), "m" (*ptr) : "memory"); return (val); } #ifdef _KERNEL #define ARM_HAVE_ATOMIC64 static __inline void atomic_set_32(volatile uint32_t *address, uint32_t setmask) { __with_interrupts_disabled(*address |= setmask); } static __inline void atomic_set_64(volatile uint64_t *address, uint64_t setmask) { __with_interrupts_disabled(*address |= setmask); } static __inline void atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) { __with_interrupts_disabled(*address &= ~clearmask); } static __inline void atomic_clear_64(volatile uint64_t *address, uint64_t clearmask) { __with_interrupts_disabled(*address &= ~clearmask); } static __inline u_int32_t atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) { int ret; __with_interrupts_disabled( { if (*p == cmpval) { *p = newval; ret = 1; } else { ret = 0; } }); return (ret); } static __inline u_int64_t atomic_cmpset_64(volatile u_int64_t *p, volatile u_int64_t cmpval, volatile u_int64_t newval) { int ret; __with_interrupts_disabled( { if (*p == cmpval) { *p = newval; ret = 1; } else { ret = 0; } }); return (ret); } static __inline void atomic_add_32(volatile u_int32_t *p, u_int32_t val) { __with_interrupts_disabled(*p += val); } static __inline void atomic_add_64(volatile u_int64_t *p, u_int64_t val) { __with_interrupts_disabled(*p += val); } static __inline void atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) { __with_interrupts_disabled(*p -= val); } static __inline void atomic_subtract_64(volatile u_int64_t *p, u_int64_t val) { __with_interrupts_disabled(*p -= val); } static __inline uint32_t atomic_fetchadd_32(volatile uint32_t *p, uint32_t v) { uint32_t value; __with_interrupts_disabled( { value = *p; *p += v; }); return (value); } static __inline uint64_t atomic_fetchadd_64(volatile uint64_t *p, uint64_t v) { uint64_t value; __with_interrupts_disabled( { value = *p; *p += v; }); return (value); } static __inline uint64_t atomic_load_64(volatile uint64_t *p) { uint64_t value; __with_interrupts_disabled(value = *p); return (value); } static __inline void atomic_store_64(volatile uint64_t *p, uint64_t value) { __with_interrupts_disabled(*p = value); } #else /* !_KERNEL */ static __inline u_int32_t atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) { register int done, ras_start = ARM_RAS_START; __asm __volatile("1:\n" "adr %1, 1b\n" "str %1, [%0]\n" "adr %1, 2f\n" "str %1, [%0, #4]\n" "ldr %1, [%2]\n" "cmp %1, %3\n" "streq %4, [%2]\n" "2:\n" "mov %1, #0\n" "str %1, [%0]\n" "mov %1, #0xffffffff\n" "str %1, [%0, #4]\n" "moveq %1, #1\n" "movne %1, #0\n" : "+r" (ras_start), "=r" (done) ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory"); return (done); } static __inline void atomic_add_32(volatile u_int32_t *p, u_int32_t val) { int start, ras_start = ARM_RAS_START; __asm __volatile("1:\n" "adr %1, 1b\n" "str %1, [%0]\n" "adr %1, 2f\n" "str %1, [%0, #4]\n" "ldr %1, [%2]\n" "add %1, %1, %3\n" "str %1, [%2]\n" "2:\n" "mov %1, #0\n" "str %1, [%0]\n" "mov %1, #0xffffffff\n" "str %1, [%0, #4]\n" : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val) : : "memory"); } static __inline void atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) { int start, ras_start = ARM_RAS_START; __asm __volatile("1:\n" "adr %1, 1b\n" "str %1, [%0]\n" "adr %1, 2f\n" "str %1, [%0, #4]\n" "ldr %1, [%2]\n" "sub %1, %1, %3\n" "str %1, [%2]\n" "2:\n" "mov %1, #0\n" "str %1, [%0]\n" "mov %1, #0xffffffff\n" "str %1, [%0, #4]\n" : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val) : : "memory"); } static __inline void atomic_set_32(volatile uint32_t *address, uint32_t setmask) { int start, ras_start = ARM_RAS_START; __asm __volatile("1:\n" "adr %1, 1b\n" "str %1, [%0]\n" "adr %1, 2f\n" "str %1, [%0, #4]\n" "ldr %1, [%2]\n" "orr %1, %1, %3\n" "str %1, [%2]\n" "2:\n" "mov %1, #0\n" "str %1, [%0]\n" "mov %1, #0xffffffff\n" "str %1, [%0, #4]\n" : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask) : : "memory"); } static __inline void atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) { int start, ras_start = ARM_RAS_START; __asm __volatile("1:\n" "adr %1, 1b\n" "str %1, [%0]\n" "adr %1, 2f\n" "str %1, [%0, #4]\n" "ldr %1, [%2]\n" "bic %1, %1, %3\n" "str %1, [%2]\n" "2:\n" "mov %1, #0\n" "str %1, [%0]\n" "mov %1, #0xffffffff\n" "str %1, [%0, #4]\n" : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask) : : "memory"); } static __inline uint32_t atomic_fetchadd_32(volatile uint32_t *p, uint32_t v) { uint32_t start, tmp, ras_start = ARM_RAS_START; __asm __volatile("1:\n" "adr %1, 1b\n" "str %1, [%0]\n" "adr %1, 2f\n" "str %1, [%0, #4]\n" "ldr %1, [%3]\n" "mov %2, %1\n" "add %2, %2, %4\n" "str %2, [%3]\n" "2:\n" "mov %2, #0\n" "str %2, [%0]\n" "mov %2, #0xffffffff\n" "str %2, [%0, #4]\n" : "+r" (ras_start), "=r" (start), "=r" (tmp), "+r" (p), "+r" (v) : : "memory"); return (start); } #endif /* _KERNEL */ static __inline uint32_t atomic_readandclear_32(volatile u_int32_t *p) { return (__swp(0, p)); } #define atomic_cmpset_rel_32 atomic_cmpset_32 #define atomic_cmpset_acq_32 atomic_cmpset_32 #define atomic_set_rel_32 atomic_set_32 #define atomic_set_acq_32 atomic_set_32 #define atomic_clear_rel_32 atomic_clear_32 #define atomic_clear_acq_32 atomic_clear_32 #define atomic_add_rel_32 atomic_add_32 #define atomic_add_acq_32 atomic_add_32 #define atomic_subtract_rel_32 atomic_subtract_32 #define atomic_subtract_acq_32 atomic_subtract_32 #define atomic_store_rel_32 atomic_store_32 #define atomic_store_rel_long atomic_store_long #define atomic_load_acq_32 atomic_load_32 #define atomic_load_acq_long atomic_load_long #define atomic_add_acq_long atomic_add_long #define atomic_add_rel_long atomic_add_long #define atomic_subtract_acq_long atomic_subtract_long #define atomic_subtract_rel_long atomic_subtract_long #define atomic_clear_acq_long atomic_clear_long #define atomic_clear_rel_long atomic_clear_long #define atomic_set_acq_long atomic_set_long #define atomic_set_rel_long atomic_set_long #define atomic_cmpset_acq_long atomic_cmpset_long #define atomic_cmpset_rel_long atomic_cmpset_long #define atomic_load_acq_long atomic_load_long #undef __with_interrupts_disabled static __inline void atomic_add_long(volatile u_long *p, u_long v) { atomic_add_32((volatile uint32_t *)p, v); } static __inline void atomic_clear_long(volatile u_long *p, u_long v) { atomic_clear_32((volatile uint32_t *)p, v); } static __inline int atomic_cmpset_long(volatile u_long *dst, u_long old, u_long newe) { return (atomic_cmpset_32((volatile uint32_t *)dst, old, newe)); } static __inline u_long atomic_fetchadd_long(volatile u_long *p, u_long v) { return (atomic_fetchadd_32((volatile uint32_t *)p, v)); } static __inline void atomic_readandclear_long(volatile u_long *p) { atomic_readandclear_32((volatile uint32_t *)p); } static __inline void atomic_set_long(volatile u_long *p, u_long v) { atomic_set_32((volatile uint32_t *)p, v); } static __inline void atomic_subtract_long(volatile u_long *p, u_long v) { atomic_subtract_32((volatile uint32_t *)p, v); } #endif /* Arch >= v6 */ static __inline int atomic_load_32(volatile uint32_t *v) { return (*v); } static __inline void atomic_store_32(volatile uint32_t *dst, uint32_t src) { *dst = src; } static __inline int atomic_load_long(volatile u_long *v) { return (*v); } static __inline void atomic_store_long(volatile u_long *dst, u_long src) { *dst = src; } #define atomic_clear_ptr atomic_clear_32 #define atomic_set_ptr atomic_set_32 #define atomic_cmpset_ptr atomic_cmpset_32 #define atomic_cmpset_rel_ptr atomic_cmpset_rel_32 #define atomic_cmpset_acq_ptr atomic_cmpset_acq_32 #define atomic_store_ptr atomic_store_32 #define atomic_store_rel_ptr atomic_store_rel_32 #define atomic_add_int atomic_add_32 #define atomic_add_acq_int atomic_add_acq_32 #define atomic_add_rel_int atomic_add_rel_32 #define atomic_subtract_int atomic_subtract_32 #define atomic_subtract_acq_int atomic_subtract_acq_32 #define atomic_subtract_rel_int atomic_subtract_rel_32 #define atomic_clear_int atomic_clear_32 #define atomic_clear_acq_int atomic_clear_acq_32 #define atomic_clear_rel_int atomic_clear_rel_32 #define atomic_set_int atomic_set_32 #define atomic_set_acq_int atomic_set_acq_32 #define atomic_set_rel_int atomic_set_rel_32 #define atomic_cmpset_int atomic_cmpset_32 #define atomic_cmpset_acq_int atomic_cmpset_acq_32 #define atomic_cmpset_rel_int atomic_cmpset_rel_32 #define atomic_fetchadd_int atomic_fetchadd_32 #define atomic_readandclear_int atomic_readandclear_32 #define atomic_load_acq_int atomic_load_acq_32 #define atomic_store_rel_int atomic_store_rel_32 #endif /* _MACHINE_ATOMIC_H_ */ Index: head/sys/arm/s3c2xx0/s3c24x0.c =================================================================== --- head/sys/arm/s3c2xx0/s3c24x0.c (revision 271397) +++ head/sys/arm/s3c2xx0/s3c24x0.c (revision 271398) @@ -1,798 +1,799 @@ /* $NetBSD: s3c2410.c,v 1.4 2003/08/27 03:46:05 bsh Exp $ */ /* * Copyright (c) 2003 Genetec corporation. All rights reserved. * Written by Hiroyuki Bessho for Genetec corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of Genetec corporation may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #define S3C2XX0_XTAL_CLK 12000000 #define IPL_LEVELS 13 u_int irqmasks[IPL_LEVELS]; static struct { uint32_t idcode; const char *name; s3c2xx0_cpu cpu; } s3c2x0_cpu_id[] = { { CHIPID_S3C2410A, "S3C2410A", CPU_S3C2410 }, { CHIPID_S3C2440A, "S3C2440A", CPU_S3C2440 }, { CHIPID_S3C2442B, "S3C2442B", CPU_S3C2440 }, { 0, NULL } }; static struct { const char *name; int prio; int unit; struct { int type; u_long start; u_long count; } res[2]; } s3c24x0_children[] = { { "rtc", 0, -1, { { SYS_RES_IOPORT, S3C24X0_RTC_PA_BASE, S3C24X0_RTC_SIZE }, { 0 }, } }, { "timer", 0, -1, { { 0 }, } }, { "uart", 1, 0, { { SYS_RES_IRQ, S3C24X0_INT_UART0, 1 }, { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(0), S3C24X0_UART_BASE(1) - S3C24X0_UART_BASE(0) }, } }, { "uart", 1, 1, { { SYS_RES_IRQ, S3C24X0_INT_UART1, 1 }, { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(1), S3C24X0_UART_BASE(2) - S3C24X0_UART_BASE(1) }, } }, { "uart", 1, 2, { { SYS_RES_IRQ, S3C24X0_INT_UART2, 1 }, { SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(2), S3C24X0_UART_BASE(3) - S3C24X0_UART_BASE(2) }, } }, { "ohci", 0, -1, { { SYS_RES_IRQ, S3C24X0_INT_USBH, 0 }, { SYS_RES_IOPORT, S3C24X0_USBHC_PA_BASE, S3C24X0_USBHC_SIZE }, } }, { NULL }, }; /* prototypes */ static device_t s3c24x0_add_child(device_t, int, const char *, int); static int s3c24x0_probe(device_t); static int s3c24x0_attach(device_t); static void s3c24x0_identify(driver_t *, device_t); static int s3c24x0_setup_intr(device_t, device_t, struct resource *, int, driver_filter_t *, driver_intr_t *, void *, void **); static int s3c24x0_teardown_intr(device_t, device_t, struct resource *, void *); static int s3c24x0_config_intr(device_t, int, enum intr_trigger, enum intr_polarity); static struct resource *s3c24x0_alloc_resource(device_t, device_t, int, int *, u_long, u_long, u_long, u_int); static int s3c24x0_activate_resource(device_t, device_t, int, int, struct resource *); static int s3c24x0_release_resource(device_t, device_t, int, int, struct resource *); static struct resource_list *s3c24x0_get_resource_list(device_t, device_t); static void s3c24x0_identify_cpu(device_t); static device_method_t s3c24x0_methods[] = { DEVMETHOD(device_probe, s3c24x0_probe), DEVMETHOD(device_attach, s3c24x0_attach), DEVMETHOD(device_identify, s3c24x0_identify), DEVMETHOD(bus_setup_intr, s3c24x0_setup_intr), DEVMETHOD(bus_teardown_intr, s3c24x0_teardown_intr), DEVMETHOD(bus_config_intr, s3c24x0_config_intr), DEVMETHOD(bus_alloc_resource, s3c24x0_alloc_resource), DEVMETHOD(bus_activate_resource, s3c24x0_activate_resource), DEVMETHOD(bus_release_resource, s3c24x0_release_resource), DEVMETHOD(bus_get_resource_list,s3c24x0_get_resource_list), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), {0, 0}, }; static driver_t s3c24x0_driver = { "s3c24x0", s3c24x0_methods, sizeof(struct s3c24x0_softc), }; static devclass_t s3c24x0_devclass; DRIVER_MODULE(s3c24x0, nexus, s3c24x0_driver, s3c24x0_devclass, 0, 0); struct s3c2xx0_softc *s3c2xx0_softc = NULL; static device_t s3c24x0_add_child(device_t bus, int prio, const char *name, int unit) { device_t child; struct s3c2xx0_ivar *ivar; child = device_add_child_ordered(bus, prio, name, unit); if (child == NULL) return (NULL); ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO); if (ivar == NULL) { device_delete_child(bus, child); printf("Can't add alloc ivar\n"); return (NULL); } device_set_ivars(child, ivar); resource_list_init(&ivar->resources); return (child); } static void s3c24x0_enable_ext_intr(unsigned int irq) { uint32_t reg, value; int offset; if (irq <= 7) { reg = GPIO_PFCON; offset = irq * 2; } else if (irq <= 23) { reg = GPIO_PGCON; offset = (irq - 8) * 2; } else return; /* Make the pin an interrupt source */ value = bus_space_read_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, reg); value &= ~(3 << offset); value |= 2 << offset; bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, reg, value); } static int s3c24x0_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error, irq; error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep); if (error != 0) return (error); for (irq = rman_get_start(ires); irq <= rman_get_end(ires); irq++) { if (irq >= S3C24X0_EXTIRQ_MIN && irq <= S3C24X0_EXTIRQ_MAX) { /* Enable the external interrupt pin */ s3c24x0_enable_ext_intr(irq - S3C24X0_EXTIRQ_MIN); } } return (0); } static int s3c24x0_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static int s3c24x0_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol) { uint32_t mask, reg, value; int offset; /* Only external interrupts can be configured */ if (irq < S3C24X0_EXTIRQ_MIN || irq > S3C24X0_EXTIRQ_MAX) return (EINVAL); /* There is no standard trigger or polarity for the bus */ if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) return (EINVAL); irq -= S3C24X0_EXTIRQ_MIN; /* Get the bits to set */ mask = 0; if (pol == INTR_POLARITY_LOW) { mask = 2; } else if (pol == INTR_POLARITY_HIGH) { mask = 4; } if (trig == INTR_TRIGGER_LEVEL) { mask >>= 2; } /* Get the register to set */ if (irq <= 7) { reg = GPIO_EXTINT(0); offset = irq * 4; } else if (irq <= 15) { reg = GPIO_EXTINT(1); offset = (irq - 8) * 4; } else if (irq <= 23) { reg = GPIO_EXTINT(2); offset = (irq - 16) * 4; } else { return (EINVAL); } /* Set the new signaling method */ value = bus_space_read_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, reg); value &= ~(7 << offset); value |= mask << offset; bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, reg, value); return (0); } static struct resource * s3c24x0_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct resource_list_entry *rle; struct s3c2xx0_ivar *ivar = device_get_ivars(child); struct resource_list *rl = &ivar->resources; struct resource *res = NULL; if (device_get_parent(child) != bus) return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, rid, start, end, count, flags)); rle = resource_list_find(rl, type, *rid); if (rle != NULL) { /* There is a resource list. Use it */ if (rle->res) panic("Resource rid %d type %d already in use", *rid, type); if (start == 0UL && end == ~0UL) { start = rle->start; count = ulmax(count, rle->count); end = ulmax(rle->end, start + count - 1); } /* * When allocating an irq with children irq's really * allocate the children as it is those we are interested * in receiving, not the parent. */ if (type == SYS_RES_IRQ && start == end) { switch (start) { case S3C24X0_INT_ADCTC: start = S3C24X0_INT_TC; end = S3C24X0_INT_ADC; break; #ifdef S3C2440_INT_CAM case S3C2440_INT_CAM: start = S3C2440_INT_CAM_C; end = S3C2440_INT_CAM_P; break; #endif default: break; } count = end - start + 1; } } switch (type) { case SYS_RES_IRQ: res = rman_reserve_resource( &s3c2xx0_softc->s3c2xx0_irq_rman, start, end, count, flags, child); break; case SYS_RES_IOPORT: case SYS_RES_MEMORY: res = rman_reserve_resource( &s3c2xx0_softc->s3c2xx0_mem_rman, start, end, count, flags, child); if (res == NULL) panic("Unable to map address space %#lX-%#lX", start, end); rman_set_bustag(res, &s3c2xx0_bs_tag); rman_set_bushandle(res, start); if (flags & RF_ACTIVE) { if (bus_activate_resource(child, type, *rid, res)) { rman_release_resource(res); return (NULL); } } break; } if (res != NULL) { rman_set_rid(res, *rid); if (rle != NULL) { rle->res = res; rle->start = rman_get_start(res); rle->end = rman_get_end(res); rle->count = count; } } return (res); } static int s3c24x0_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { bus_space_handle_t p; int error; if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { error = bus_space_map(rman_get_bustag(r), rman_get_bushandle(r), rman_get_size(r), 0, &p); if (error) return (error); rman_set_bushandle(r, p); } return (rman_activate_resource(r)); } static int s3c24x0_release_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { struct s3c2xx0_ivar *ivar = device_get_ivars(child); struct resource_list *rl = &ivar->resources; struct resource_list_entry *rle; if (rl == NULL) return (EINVAL); rle = resource_list_find(rl, type, rid); if (rle == NULL) return (EINVAL); rman_release_resource(r); rle->res = NULL; return 0; } static struct resource_list * s3c24x0_get_resource_list(device_t dev, device_t child) { struct s3c2xx0_ivar *ivar; ivar = device_get_ivars(child); return (&(ivar->resources)); } void s3c24x0_identify(driver_t *driver, device_t parent) { BUS_ADD_CHILD(parent, 0, "s3c24x0", 0); } int s3c24x0_probe(device_t dev) { return (BUS_PROBE_NOWILDCARD); } int s3c24x0_attach(device_t dev) { struct s3c24x0_softc *sc = device_get_softc(dev); bus_space_tag_t iot; device_t child; unsigned int i, j; u_long irqmax; s3c2xx0_softc = &(sc->sc_sx); sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag; s3c2xx0_softc->s3c2xx0_irq_rman.rm_type = RMAN_ARRAY; s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C24X0 IRQs"; s3c2xx0_softc->s3c2xx0_mem_rman.rm_type = RMAN_ARRAY; s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C24X0 Device Registers"; /* Manage the registor memory space */ if ((rman_init(&s3c2xx0_softc->s3c2xx0_mem_rman) != 0) || (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman, S3C24X0_DEV_VA_OFFSET, S3C24X0_DEV_VA_OFFSET + S3C24X0_DEV_VA_SIZE) != 0) || (rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman, S3C24X0_DEV_START, S3C24X0_DEV_STOP) != 0)) panic("s3c24x0_attach: failed to set up register rman"); /* These are needed for things without a proper device to attach to */ sc->sc_sx.sc_intctl_ioh = S3C24X0_INTCTL_BASE; sc->sc_sx.sc_gpio_ioh = S3C24X0_GPIO_BASE; sc->sc_sx.sc_clkman_ioh = S3C24X0_CLKMAN_BASE; sc->sc_sx.sc_wdt_ioh = S3C24X0_WDT_BASE; sc->sc_timer_ioh = S3C24X0_TIMER_BASE; /* * Identify the CPU */ s3c24x0_identify_cpu(dev); /* * Manage the interrupt space. * We need to put this after s3c24x0_identify_cpu as the avaliable * interrupts change depending on which CPU we have. */ if (sc->sc_sx.sc_cpu == CPU_S3C2410) irqmax = S3C2410_SUBIRQ_MAX; else irqmax = S3C2440_SUBIRQ_MAX; if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 || rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0, irqmax) != 0 || rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, S3C24X0_EXTIRQ_MIN, S3C24X0_EXTIRQ_MAX)) panic("s3c24x0_attach: failed to set up IRQ rman"); /* calculate current clock frequency */ s3c24x0_clock_freq(&sc->sc_sx); device_printf(dev, "fclk %d MHz hclk %d MHz pclk %d MHz\n", sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000, sc->sc_sx.sc_pclk / 1000000); /* * Attach children devices */ for (i = 0; s3c24x0_children[i].name != NULL; i++) { child = s3c24x0_add_child(dev, s3c24x0_children[i].prio, s3c24x0_children[i].name, s3c24x0_children[i].unit); for (j = 0; j < sizeof(s3c24x0_children[i].res) / sizeof(s3c24x0_children[i].res[0]) && s3c24x0_children[i].res[j].type != 0; j++) { bus_set_resource(child, s3c24x0_children[i].res[j].type, 0, s3c24x0_children[i].res[j].start, s3c24x0_children[i].res[j].count); } } bus_generic_probe(dev); bus_generic_attach(dev); return (0); } static void s3c24x0_identify_cpu(device_t dev) { struct s3c24x0_softc *sc = device_get_softc(dev); uint32_t idcode; int i; idcode = bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_gpio_ioh, GPIO_GSTATUS1); for (i = 0; s3c2x0_cpu_id[i].name != NULL; i++) { if (s3c2x0_cpu_id[i].idcode == idcode) break; } if (s3c2x0_cpu_id[i].name == NULL) panic("Unknown CPU detected ((Chip ID: %#X)", idcode); device_printf(dev, "Found %s CPU (Chip ID: %#X)\n", s3c2x0_cpu_id[i].name, idcode); sc->sc_sx.sc_cpu = s3c2x0_cpu_id[i].cpu; } /* * fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register. * * s3c24{1,4}0_clock_freq2() is meant to be called from kernel startup routines. * s3c24x0_clock_freq() is for after kernel initialization is done. * * Because they can be called before bus_space is available we need to use * volatile pointers rather than bus_space_read. */ void s3c2410_clock_freq2(vm_offset_t clkman_base, int *fclk, int *hclk, int *pclk) { uint32_t pllcon, divn; unsigned int mdiv, pdiv, sdiv; unsigned int f, h, p; pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON); divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN); mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT; sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT; f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)); h = f; if (divn & S3C2410_CLKDIVN_HDIVN) h /= 2; p = h; if (divn & CLKDIVN_PDIVN) p /= 2; if (fclk) *fclk = f; if (hclk) *hclk = h; if (pclk) *pclk = p; } void s3c2440_clock_freq2(vm_offset_t clkman_base, int *fclk, int *hclk, int *pclk) { uint32_t pllcon, divn, camdivn; unsigned int mdiv, pdiv, sdiv; unsigned int f, h, p; pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON); divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN); camdivn = *(volatile uint32_t *)(clkman_base + S3C2440_CLKMAN_CAMDIVN); mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT; sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT; f = (2 * (mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)); h = f; switch((divn >> 1) & 3) { case 0: break; case 1: h /= 2; break; case 2: if ((camdivn & S3C2440_CAMDIVN_HCLK4_HALF) == S3C2440_CAMDIVN_HCLK4_HALF) h /= 8; else h /= 4; break; case 3: if ((camdivn & S3C2440_CAMDIVN_HCLK3_HALF) == S3C2440_CAMDIVN_HCLK3_HALF) h /= 6; else h /= 3; break; } p = h; if (divn & CLKDIVN_PDIVN) p /= 2; if (fclk) *fclk = f; if (hclk) *hclk = h; if (pclk) *pclk = p; } void s3c24x0_clock_freq(struct s3c2xx0_softc *sc) { vm_offset_t va; va = sc->sc_clkman_ioh; switch(sc->sc_cpu) { case CPU_S3C2410: s3c2410_clock_freq2(va, &sc->sc_fclk, &sc->sc_hclk, &sc->sc_pclk); break; case CPU_S3C2440: s3c2440_clock_freq2(va, &sc->sc_fclk, &sc->sc_hclk, &sc->sc_pclk); break; } } void cpu_reset(void) { - (void) disable_interrupts(I32_bit|F32_bit); + (void) disable_interrupts(PSR_I|PSR_F); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_wdt_ioh, WDT_WTCON, WTCON_ENABLE | WTCON_CLKSEL_16 | WTCON_ENRST); for(;;); } void s3c24x0_sleep(int mode __unused) { int reg; reg = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh, CLKMAN_CLKCON); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_clkman_ioh, CLKMAN_CLKCON, reg | CLKCON_IDLE); } int arm_get_next_irq(int last __unused) { uint32_t intpnd; int irq, subirq; if ((irq = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTOFFSET)) != 0) { /* Clear the pending bit */ intpnd = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTPND); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_SRCPND, intpnd); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTPND, intpnd); switch (irq) { case S3C24X0_INT_ADCTC: case S3C24X0_INT_UART0: case S3C24X0_INT_UART1: case S3C24X0_INT_UART2: /* Find the sub IRQ */ subirq = 0x7ff; subirq &= bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND); subirq &= ~(bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK)); if (subirq == 0) return (irq); subirq = ffs(subirq) - 1; /* Clear the sub irq pending bit */ bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND, (1 << subirq)); /* * Return the parent IRQ for UART * as it is all we ever need */ if (subirq <= 8) return (irq); return (S3C24X0_SUBIRQ_MIN + subirq); case S3C24X0_INT_0: case S3C24X0_INT_1: case S3C24X0_INT_2: case S3C24X0_INT_3: /* There is a 1:1 mapping to the IRQ we are handling */ return S3C24X0_INT_EXT(irq); case S3C24X0_INT_4_7: case S3C24X0_INT_8_23: /* Find the external interrupt being called */ subirq = 0x7fffff; subirq &= bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND); subirq &= ~bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK); if (subirq == 0) return (irq); subirq = ffs(subirq) - 1; /* Clear the external irq pending bit */ bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTPEND, (1 << subirq)); return S3C24X0_INT_EXT(subirq); } return (irq); } return (-1); } void arm_mask_irq(uintptr_t irq) { u_int32_t mask; if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) { /* External interrupt 0..3 are directly mapped to irq 0..3 */ irq -= S3C24X0_EXTIRQ_MIN; } if (irq < S3C24X0_SUBIRQ_MIN) { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK); mask |= (1 << irq); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask); } else if (irq < S3C24X0_EXTIRQ_MIN) { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK); mask |= (1 << (irq - S3C24X0_SUBIRQ_MIN)); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask); } else { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK); mask |= (1 << (irq - S3C24X0_EXTIRQ_MIN)); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask); } } void arm_unmask_irq(uintptr_t irq) { u_int32_t mask; if (irq >= S3C24X0_INT_EXT(0) && irq <= S3C24X0_INT_EXT(3)) { /* External interrupt 0..3 are directly mapped to irq 0..3 */ irq -= S3C24X0_EXTIRQ_MIN; } if (irq < S3C24X0_SUBIRQ_MIN) { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK); mask &= ~(1 << irq); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK, mask); } else if (irq < S3C24X0_EXTIRQ_MIN) { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK); mask &= ~(1 << (irq - S3C24X0_SUBIRQ_MIN)); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask); } else { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_gpio_ioh, GPIO_EINTMASK); mask &= ~(1 << (irq - S3C24X0_EXTIRQ_MIN)); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, GPIO_EINTMASK, mask); } } Index: head/sys/arm/xscale/i80321/i80321_intr.h =================================================================== --- head/sys/arm/xscale/i80321/i80321_intr.h (revision 271397) +++ head/sys/arm/xscale/i80321/i80321_intr.h (revision 271398) @@ -1,165 +1,165 @@ /* $NetBSD: i80321_intr.h,v 1.5 2004/01/12 10:25:06 scw Exp $ */ /*- * Copyright (c) 2001, 2002 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef _I80321_INTR_H_ #define _I80321_INTR_H_ #define ARM_IRQ_HANDLER _C_LABEL(i80321_intr_dispatch) #ifndef _LOCORE #include #include #include void i80321_do_pending(void); extern __volatile uint32_t intr_enabled; extern uint32_t intr_steer; static __inline void __attribute__((__unused__)) i80321_set_intrmask(void) { __asm __volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (intr_enabled & ICU_INT_HWMASK)); } static __inline void i80321_set_intrsteer(void) { __asm __volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (intr_steer & ICU_INT_HWMASK)); } #if defined ( CPU_XSCALE_80219 ) #define INT_SWMASK \ ((1U << ICU_INT_bit26) | \ (1U << ICU_INT_bit25) | \ (1U << ICU_INT_bit23) | \ (1U << ICU_INT_bit22) | \ (1U << ICU_INT_bit7) | \ (1U << ICU_INT_bit6) | \ (1U << ICU_INT_bit5) | \ (1U << ICU_INT_bit4)) #else #define INT_SWMASK \ ((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \ (1U << ICU_INT_bit5) | (1U << ICU_INT_bit4)) #endif #if 0 static __inline void __attribute__((__unused__)) i80321_splx(int new) { extern __volatile uint32_t intr_enabled; extern __volatile int current_spl_level; extern __volatile int i80321_ipending; extern void i80321_do_pending(void); int oldirqstate, hwpend; /* Don't let the compiler re-order this code with preceding code */ __insn_barrier(); current_spl_level = new; hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new; if (hwpend != 0) { - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); intr_enabled |= hwpend; i80321_set_intrmask(); restore_interrupts(oldirqstate); } if ((i80321_ipending & INT_SWMASK) & ~new) i80321_do_pending(); } static __inline int __attribute__((__unused__)) i80321_splraise(int ipl) { extern __volatile int current_spl_level; extern int i80321_imask[]; int old; old = current_spl_level; current_spl_level |= i80321_imask[ipl]; /* Don't let the compiler re-order this code with subsequent code */ __insn_barrier(); return (old); } static __inline int __attribute__((__unused__)) i80321_spllower(int ipl) { extern __volatile int current_spl_level; extern int i80321_imask[]; int old = current_spl_level; i80321_splx(i80321_imask[ipl]); return(old); } #endif #if !defined(EVBARM_SPL_NOINLINE) #define splx(new) i80321_splx(new) #define _spllower(ipl) i80321_spllower(ipl) #define _splraise(ipl) i80321_splraise(ipl) void _setsoftintr(int); #else int _splraise(int); int _spllower(int); void splx(int); void _setsoftintr(int); #endif /* ! EVBARM_SPL_NOINLINE */ #endif /* _LOCORE */ #endif /* _I80321_INTR_H_ */ Index: head/sys/arm/xscale/i80321/i80321_timer.c =================================================================== --- head/sys/arm/xscale/i80321/i80321_timer.c (revision 271397) +++ head/sys/arm/xscale/i80321/i80321_timer.c (revision 271398) @@ -1,484 +1,485 @@ /* $NetBSD: i80321_timer.c,v 1.7 2003/07/27 04:52:28 thorpej Exp $ */ /*- * Copyright (c) 2001, 2002 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * Timer/clock support for the Intel i80321 I/O processor. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #ifdef CPU_XSCALE_81342 #define ICU_INT_TIMER0 (8) /* XXX: Can't include i81342reg.h because definitions overrides the ones from i80321reg.h */ #endif #include "opt_timer.h" void (*i80321_hardclock_hook)(void) = NULL; struct i80321_timer_softc { device_t dev; } timer_softc; static unsigned i80321_timer_get_timecount(struct timecounter *tc); static uint32_t counts_per_hz; #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342) static uint32_t offset; static uint32_t last = -1; #endif static int ticked = 0; #ifndef COUNTS_PER_SEC #define COUNTS_PER_SEC 200000000 /* 200MHz */ #endif #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000) static struct timecounter i80321_timer_timecounter = { i80321_timer_get_timecount, /* get_timecount */ NULL, /* no poll_pps */ ~0u, /* counter_mask */ #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342) COUNTS_PER_SEC, #else COUNTS_PER_SEC * 3, /* frequency */ #endif "i80321 timer", /* name */ 1000 /* quality */ }; static int i80321_timer_probe(device_t dev) { device_set_desc(dev, "i80321 timer"); return (0); } static int i80321_timer_attach(device_t dev) { timer_softc.dev = dev; return (0); } static device_method_t i80321_timer_methods[] = { DEVMETHOD(device_probe, i80321_timer_probe), DEVMETHOD(device_attach, i80321_timer_attach), {0, 0}, }; static driver_t i80321_timer_driver = { "itimer", i80321_timer_methods, sizeof(struct i80321_timer_softc), }; static devclass_t i80321_timer_devclass; DRIVER_MODULE(itimer, iq, i80321_timer_driver, i80321_timer_devclass, 0, 0); int clockhandler(void *); static __inline uint32_t tmr1_read(void) { uint32_t rv; #ifdef CPU_XSCALE_81342 __asm __volatile("mrc p6, 0, %0, c1, c9, 0" #else __asm __volatile("mrc p6, 0, %0, c1, c1, 0" #endif : "=r" (rv)); return (rv); } static __inline void tmr1_write(uint32_t val) { #ifdef CPU_XSCALE_81342 __asm __volatile("mcr p6, 0, %0, c1, c9, 0" #else __asm __volatile("mcr p6, 0, %0, c1, c1, 0" #endif : : "r" (val)); } static __inline uint32_t tcr1_read(void) { uint32_t rv; #ifdef CPU_XSCALE_81342 __asm __volatile("mrc p6, 0, %0, c3, c9, 0" #else __asm __volatile("mrc p6, 0, %0, c3, c1, 0" #endif : "=r" (rv)); return (rv); } static __inline void tcr1_write(uint32_t val) { #ifdef CPU_XSCALE_81342 __asm __volatile("mcr p6, 0, %0, c3, c9, 0" #else __asm __volatile("mcr p6, 0, %0, c3, c1, 0" #endif : : "r" (val)); } static __inline void trr1_write(uint32_t val) { #ifdef CPU_XSCALE_81342 __asm __volatile("mcr p6, 0, %0, c5, c9, 0" #else __asm __volatile("mcr p6, 0, %0, c5, c1, 0" #endif : : "r" (val)); } static __inline uint32_t tmr0_read(void) { uint32_t rv; #ifdef CPU_XSCALE_81342 __asm __volatile("mrc p6, 0, %0, c0, c9, 0" #else __asm __volatile("mrc p6, 0, %0, c0, c1, 0" #endif : "=r" (rv)); return (rv); } static __inline void tmr0_write(uint32_t val) { #ifdef CPU_XSCALE_81342 __asm __volatile("mcr p6, 0, %0, c0, c9, 0" #else __asm __volatile("mcr p6, 0, %0, c0, c1, 0" #endif : : "r" (val)); } static __inline uint32_t tcr0_read(void) { uint32_t rv; #ifdef CPU_XSCALE_81342 __asm __volatile("mrc p6, 0, %0, c2, c9, 0" #else __asm __volatile("mrc p6, 0, %0, c2, c1, 0" #endif : "=r" (rv)); return (rv); } static __inline void tcr0_write(uint32_t val) { #ifdef CPU_XSCALE_81342 __asm __volatile("mcr p6, 0, %0, c2, c9, 0" #else __asm __volatile("mcr p6, 0, %0, c2, c1, 0" #endif : : "r" (val)); } static __inline void trr0_write(uint32_t val) { #ifdef CPU_XSCALE_81342 __asm __volatile("mcr p6, 0, %0, c4, c9, 0" #else __asm __volatile("mcr p6, 0, %0, c4, c1, 0" #endif : : "r" (val)); } static __inline void tisr_write(uint32_t val) { #ifdef CPU_XSCALE_81342 __asm __volatile("mcr p6, 0, %0, c6, c9, 0" #else __asm __volatile("mcr p6, 0, %0, c6, c1, 0" #endif : : "r" (val)); } static __inline uint32_t tisr_read(void) { int ret; #ifdef CPU_XSCALE_81342 __asm __volatile("mrc p6, 0, %0, c6, c9, 0" : "=r" (ret)); #else __asm __volatile("mrc p6, 0, %0, c6, c1, 0" : "=r" (ret)); #endif return (ret); } static unsigned i80321_timer_get_timecount(struct timecounter *tc) { #if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342) uint32_t cur = tcr0_read(); if (cur > last && last != -1) { offset += counts_per_hz; if (ticked > 0) ticked--; } if (ticked) { offset += ticked * counts_per_hz; ticked = 0; } return (counts_per_hz - cur + offset); #else uint32_t ret; __asm __volatile("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (ret)); return (ret); #endif } /* * i80321_calibrate_delay: * * Calibrate the delay loop. */ void i80321_calibrate_delay(void) { /* * Just use hz=100 for now -- we'll adjust it, if necessary, * in cpu_initclocks(). */ counts_per_hz = COUNTS_PER_SEC / 100; tmr0_write(0); /* stop timer */ tisr_write(TISR_TMR0); /* clear interrupt */ trr0_write(counts_per_hz); /* reload value */ tcr0_write(counts_per_hz); /* current value */ tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); } /* * cpu_initclocks: * * Initialize the clock and get them going. */ void cpu_initclocks(void) { u_int oldirqstate; struct resource *irq; int rid = 0; void *ihl; device_t dev = timer_softc.dev; if (hz < 50 || COUNTS_PER_SEC % hz) { printf("Cannot get %d Hz clock; using 100 Hz\n", hz); hz = 100; } tick = 1000000 / hz; /* number of microseconds between interrupts */ /* * We only have one timer available; stathz and profhz are * always left as 0 (the upper-layer clock code deals with * this situation). */ if (stathz != 0) printf("Cannot get %d Hz statclock\n", stathz); stathz = 0; if (profhz != 0) printf("Cannot get %d Hz profclock\n", profhz); profhz = 0; /* Report the clock frequency. */ - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, #ifdef CPU_XSCALE_81342 ICU_INT_TIMER0, ICU_INT_TIMER0, #else ICU_INT_TMR0, ICU_INT_TMR0, #endif 1, RF_ACTIVE); if (!irq) panic("Unable to setup the clock irq handler.\n"); else bus_setup_intr(dev, irq, INTR_TYPE_CLK, clockhandler, NULL, NULL, &ihl); tmr0_write(0); /* stop timer */ tisr_write(TISR_TMR0); /* clear interrupt */ counts_per_hz = COUNTS_PER_SEC / hz; trr0_write(counts_per_hz); /* reload value */ tcr0_write(counts_per_hz); /* current value */ tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE); tc_init(&i80321_timer_timecounter); restore_interrupts(oldirqstate); rid = 0; #if !defined(XSCALE_DISABLE_CCNT) && !defined(CPU_XSCALE_81342) /* Enable the clock count register. */ __asm __volatile("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (rid)); rid &= ~(1 << 3); rid |= (1 << 2) | 1; __asm __volatile("mcr p14, 0, %0, c0, c0, 0\n" : : "r" (rid)); #endif } /* * DELAY: * * Delay for at least N microseconds. */ void DELAY(int n) { uint32_t cur, last, delta, usecs; /* * This works by polling the timer and counting the * number of microseconds that go by. */ last = tcr0_read(); delta = usecs = 0; while (n > usecs) { cur = tcr0_read(); /* Check to see if the timer has wrapped around. */ if (last < cur) delta += (last + (counts_per_hz - cur)); else delta += (last - cur); last = cur; if (delta >= COUNTS_PER_USEC) { usecs += delta / COUNTS_PER_USEC; delta %= COUNTS_PER_USEC; } } } /* * clockhandler: * * Handle the hardclock interrupt. */ int clockhandler(void *arg) { struct trapframe *frame = arg; ticked++; tisr_write(TISR_TMR0); hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); if (i80321_hardclock_hook != NULL) (*i80321_hardclock_hook)(); return (FILTER_HANDLED); } void cpu_startprofclock(void) { } void cpu_stopprofclock(void) { } Index: head/sys/arm/xscale/i80321/iq80321.c =================================================================== --- head/sys/arm/xscale/i80321/iq80321.c (revision 271397) +++ head/sys/arm/xscale/i80321/iq80321.c (revision 271398) @@ -1,393 +1,394 @@ /* $NetBSD: i80321_mainbus.c,v 1.13 2003/12/17 22:03:24 abs Exp $ */ /*- * Copyright (c) 2001, 2002 Wasabi Systems, Inc. * All rights reserved. * * Written by Jason R. Thorpe for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * IQ80321 front-end for the i80321 I/O Processor. We take care * of setting up the i80321 memory map, PCI interrupt routing, etc., * which are all specific to the board the i80321 is wired up to. */ #include __FBSDID("$FreeBSD$"); #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include #include int iq80321_probe(device_t); void iq80321_identify(driver_t *, device_t); int iq80321_attach(device_t); int iq80321_probe(device_t dev) { device_set_desc(dev, "Intel 80321"); return (BUS_PROBE_NOWILDCARD); } void iq80321_identify(driver_t *driver, device_t parent) { BUS_ADD_CHILD(parent, 0, "iq", 0); } static struct arm32_dma_range i80321_dr; static int dma_range_init = 0; struct arm32_dma_range * bus_dma_get_range(void) { if (dma_range_init == 0) return (NULL); return (&i80321_dr); } int bus_dma_get_range_nb(void) { if (dma_range_init == 0) return (0); return (1); } #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 int iq80321_attach(device_t dev) { struct i80321_softc *sc = device_get_softc(dev); int b0u, b0l, b1u, b1l; vm_paddr_t memstart = 0; vm_size_t memsize = 0; int busno; /* * Fill in the space tag for the i80321's own devices, * and hand-craft the space handle for it (the device * was mapped during early bootstrap). */ i80321_bs_init(&i80321_bs_tag, sc); sc->sc_st = &i80321_bs_tag; sc->sc_sh = IQ80321_80321_VBASE; sc->dev = dev; sc->sc_is_host = 1; /* * Slice off a subregion for the Memory Controller -- we need it * here in order read the memory size. */ if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE, VERDE_MCU_SIZE, &sc->sc_mcu_sh)) panic("%s: unable to subregion MCU registers", device_get_name(dev)); if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, VERDE_ATU_SIZE, &sc->sc_atu_sh)) panic("%s: unable to subregion ATU registers", device_get_name(dev)); /* * We have mapped the PCI I/O windows in the early * bootstrap phase. */ sc->sc_iow_vaddr = IQ80321_IOW_VBASE; /* * Check the configuration of the ATU to see if another BIOS * has configured us. If a PC BIOS didn't configure us, then: * IQ80321: BAR0 00000000.0000000c BAR1 is 00000000.8000000c. * IQ31244: BAR0 00000000.00000004 BAR1 is 00000000.0000000c. * If a BIOS has configured us, at least one of those should be * different. This is pretty fragile, but it's not clear what * would work better. */ b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x0); b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x4); b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0x8); b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_BARS+0xc); #ifdef VERBOSE_INIT_ARM printf("i80321: BAR0 = %08x.%08x BAR1 = %08x.%08x\n", b0l,b0u, b1l, b1u ); #endif #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 b0l &= PCI_MAPREG_MEM_ADDR_MASK; b0u &= PCI_MAPREG_MEM_ADDR_MASK; b1l &= PCI_MAPREG_MEM_ADDR_MASK; b1u &= PCI_MAPREG_MEM_ADDR_MASK; #ifdef VERBOSE_INIT_ARM printf("i80219: BAR0 = %08x.%08x BAR1 = %08x.%08x\n", b0l,b0u, b1l, b1u ); #endif if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0)) sc->sc_is_host = 0; else sc->sc_is_host = 1; /* FIXME: i force it's */ #ifdef CPU_XSCALE_80219 sc->sc_is_host = 1; #endif i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); /* * We set up the Inbound Windows as follows: * * 0 Access to i80321 PMMRs * * 1 Reserve space for private devices * * 2 RAM access * * 3 Unused. * * This chunk needs to be customized for each IOP321 application. */ #if 0 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE; sc->sc_iwin[0].iwin_base_hi = 0; sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE; sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE; #endif if (sc->sc_is_host) { /* Map PCI:Local 1:1. */ sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE | PCI_MAPREG_MEM_PREFETCHABLE_MASK | PCI_MAPREG_MEM_TYPE_64BIT; sc->sc_iwin[1].iwin_base_hi = 0; } else { sc->sc_iwin[1].iwin_base_lo = 0; sc->sc_iwin[1].iwin_base_hi = 0; } sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE; sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE; if (sc->sc_is_host) { sc->sc_iwin[2].iwin_base_lo = memstart | PCI_MAPREG_MEM_PREFETCHABLE_MASK | PCI_MAPREG_MEM_TYPE_64BIT; sc->sc_iwin[2].iwin_base_hi = 0; } else { sc->sc_iwin[2].iwin_base_lo = 0; sc->sc_iwin[2].iwin_base_hi = 0; } sc->sc_iwin[2].iwin_xlate = memstart; sc->sc_iwin[2].iwin_size = memsize; if (sc->sc_is_host) { sc->sc_iwin[3].iwin_base_lo = 0 | PCI_MAPREG_MEM_PREFETCHABLE_MASK | PCI_MAPREG_MEM_TYPE_64BIT; } else { sc->sc_iwin[3].iwin_base_lo = 0; } sc->sc_iwin[3].iwin_base_hi = 0; sc->sc_iwin[3].iwin_xlate = 0; sc->sc_iwin[3].iwin_size = 0; #ifdef VERBOSE_INIT_ARM printf("i80321: Reserve space for private devices (Inbound Window 1) \n hi:0x%08x lo:0x%08x xlate:0x%08x size:0x%08x\n", sc->sc_iwin[1].iwin_base_hi, sc->sc_iwin[1].iwin_base_lo, sc->sc_iwin[1].iwin_xlate, sc->sc_iwin[1].iwin_size ); printf("i80321: RAM access (Inbound Window 2) \n hi:0x%08x lo:0x%08x xlate:0x%08x size:0x%08x\n", sc->sc_iwin[2].iwin_base_hi, sc->sc_iwin[2].iwin_base_lo, sc->sc_iwin[2].iwin_xlate, sc->sc_iwin[2].iwin_size ); #endif /* * We set up the Outbound Windows as follows: * * 0 Access to private PCI space. * * 1 Unused. */ #define PCI_MAPREG_MEM_ADDR(x) ((x) & 0xfffffff0) sc->sc_owin[0].owin_xlate_lo = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; /* * Set the Secondary Outbound I/O window to map * to PCI address 0 for all 64K of the I/O space. */ sc->sc_ioout_xlate = 0; i80321_attach(sc); i80321_dr.dr_sysbase = sc->sc_iwin[2].iwin_xlate; i80321_dr.dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo); i80321_dr.dr_len = sc->sc_iwin[2].iwin_size; dma_range_init = 1; busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); busno = PCIXSR_BUSNO(busno); if (busno == 0xff) busno = 0; sc->sc_irq_rman.rm_type = RMAN_ARRAY; sc->sc_irq_rman.rm_descr = "i80321 IRQs"; if (rman_init(&sc->sc_irq_rman) != 0 || rman_manage_region(&sc->sc_irq_rman, 0, 25) != 0) panic("i80321_attach: failed to set up IRQ rman"); device_add_child(dev, "obio", 0); device_add_child(dev, "itimer", 0); device_add_child(dev, "iopwdog", 0); #ifndef CPU_XSCALE_80219 device_add_child(dev, "iqseg", 0); #endif device_add_child(dev, "pcib", busno); device_add_child(dev, "i80321_dma", 0); device_add_child(dev, "i80321_dma", 1); #ifndef CPU_XSCALE_80219 device_add_child(dev, "i80321_aau", 0); #endif bus_generic_probe(dev); bus_generic_attach(dev); return (0); } void arm_mask_irq(uintptr_t nb) { intr_enabled &= ~(1 << nb); i80321_set_intrmask(); } void arm_unmask_irq(uintptr_t nb) { intr_enabled |= (1 << nb); i80321_set_intrmask(); } void cpu_reset() { - (void) disable_interrupts(I32_bit|F32_bit); + (void) disable_interrupts(PSR_I|PSR_F); *(__volatile uint32_t *)(IQ80321_80321_VBASE + VERDE_ATU_BASE + ATU_PCSR) = PCSR_RIB | PCSR_RPB; printf("Reset failed!\n"); for(;;); } static struct resource * iq80321_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct i80321_softc *sc = device_get_softc(dev); struct resource *rv; if (type == SYS_RES_IRQ) { rv = rman_reserve_resource(&sc->sc_irq_rman, start, end, count, flags, child); if (rv != NULL) rman_set_rid(rv, *rid); return (rv); } return (NULL); } static int iq80321_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error; error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep); if (error) return (error); intr_enabled |= 1 << rman_get_start(ires); i80321_set_intrmask(); return (0); } static int iq80321_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static device_method_t iq80321_methods[] = { DEVMETHOD(device_probe, iq80321_probe), DEVMETHOD(device_attach, iq80321_attach), DEVMETHOD(device_identify, iq80321_identify), DEVMETHOD(bus_alloc_resource, iq80321_alloc_resource), DEVMETHOD(bus_setup_intr, iq80321_setup_intr), DEVMETHOD(bus_teardown_intr, iq80321_teardown_intr), {0, 0}, }; static driver_t iq80321_driver = { "iq", iq80321_methods, sizeof(struct i80321_softc), }; static devclass_t iq80321_devclass; DRIVER_MODULE(iq, nexus, iq80321_driver, iq80321_devclass, 0, 0); Index: head/sys/arm/xscale/i8134x/i81342.c =================================================================== --- head/sys/arm/xscale/i8134x/i81342.c (revision 271397) +++ head/sys/arm/xscale/i8134x/i81342.c (revision 271398) @@ -1,465 +1,466 @@ /*- * Copyright (c) 2006 Olivier Houchard * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #define _ARM32_BUS_DMA_PRIVATE +#include #include #include #include #include #define WDTCR_ENABLE1 0x1e1e1e1e #define WDTCR_ENABLE2 0xe1e1e1e1 static volatile int intr_enabled0; static volatile int intr_enabled1; static volatile int intr_enabled2; static volatile int intr_enabled3; struct bus_space i81342_bs_tag; /* Read the interrupt pending register */ static __inline uint32_t intpnd0_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c0, c3, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intpnd1_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c1, c3, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intpnd2_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c2, c3, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intpnd3_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c3, c3, 0" : "=r" (ret)); return (ret); } /* Read the interrupt control register */ /* 0 masked, 1 unmasked */ static __inline uint32_t intctl0_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c0, c4, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intctl1_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c1, c4, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intctl2_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c2, c4, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intctl3_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c3, c4, 0" : "=r" (ret)); return (ret); } /* Write the interrupt control register */ static __inline void intctl0_write(uint32_t val) { __asm __volatile("mcr p6, 0, %0, c0, c4, 0" : : "r" (val)); } static __inline void intctl1_write(uint32_t val) { __asm __volatile("mcr p6, 0, %0, c1, c4, 0" : : "r" (val)); } static __inline void intctl2_write(uint32_t val) { __asm __volatile("mcr p6, 0, %0, c2, c4, 0" : : "r" (val)); } static __inline void intctl3_write(uint32_t val) { __asm __volatile("mcr p6, 0, %0, c3, c4, 0" : : "r" (val)); } /* Read the interrupt steering register */ /* 0 IRQ 1 FIQ */ static __inline uint32_t intstr0_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c0, c5, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intstr1_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c1, c5, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intstr2_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c2, c5, 0" : "=r" (ret)); return (ret); } static __inline uint32_t intstr3_read(void) { uint32_t ret; __asm __volatile("mrc p6, 0, %0, c3, c5, 0" : "=r" (ret)); return (ret); } /* Write the interrupt steering register */ static __inline void intstr0_write(uint32_t val) { __asm __volatile("mcr p6, 0, %0, c0, c5, 0" : : "r" (val)); } static __inline void intstr1_write(uint32_t val) { __asm __volatile("mcr p6, 0, %0, c1, c5, 0" : : "r" (val)); } static __inline void intstr2_write(uint32_t val) { __asm __volatile("mcr p6, 0, %0, c2, c5, 0" : : "r" (val)); } static __inline void intstr3_write(uint32_t val) { __asm __volatile("mcr p6, 0, %0, c3, c5, 0" : : "r" (val)); } void cpu_reset(void) { - disable_interrupts(I32_bit); + disable_interrupts(PSR_I); /* XXX: Use the watchdog to reset for now */ __asm __volatile("mcr p6, 0, %0, c8, c9, 0\n" "mcr p6, 0, %1, c7, c9, 0\n" "mcr p6, 0, %2, c7, c9, 0\n" : : "r" (1), "r" (WDTCR_ENABLE1), "r" (WDTCR_ENABLE2)); while (1); } void arm_mask_irq(uintptr_t nb) { if (nb < 32) { intr_enabled0 &= ~(1 << nb); intctl0_write(intr_enabled0); } else if (nb < 64) { intr_enabled1 &= ~(1 << (nb - 32)); intctl1_write(intr_enabled1); } else if (nb < 96) { intr_enabled2 &= ~(1 << (nb - 64)); intctl2_write(intr_enabled2); } else { intr_enabled3 &= ~(1 << (nb - 96)); intctl3_write(intr_enabled3); } } void arm_unmask_irq(uintptr_t nb) { if (nb < 32) { intr_enabled0 |= (1 << nb); intctl0_write(intr_enabled0); } else if (nb < 64) { intr_enabled1 |= (1 << (nb - 32)); intctl1_write(intr_enabled1); } else if (nb < 96) { intr_enabled2 |= (1 << (nb - 64)); intctl2_write(intr_enabled2); } else { intr_enabled3 |= (1 << (nb - 96)); intctl3_write(intr_enabled3); } } int arm_get_next_irq(int last __unused) { uint32_t val; val = intpnd0_read() & intr_enabled0; if (val) return (ffs(val) - 1); val = intpnd1_read() & intr_enabled1; if (val) return (32 + ffs(val) - 1); val = intpnd2_read() & intr_enabled2; if (val) return (64 + ffs(val) - 1); val = intpnd3_read() & intr_enabled3; if (val) return (96 + ffs(val) - 1); return (-1); } int bus_dma_get_range_nb(void) { return (0); } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } static int i81342_probe(device_t dev) { unsigned int freq; freq = *(volatile unsigned int *)(IOP34X_VADDR + IOP34X_PFR); switch (freq & IOP34X_FREQ_MASK) { case IOP34X_FREQ_600: device_set_desc(dev, "Intel 81342 600MHz"); break; case IOP34X_FREQ_667: device_set_desc(dev, "Intel 81342 667MHz"); break; case IOP34X_FREQ_800: device_set_desc(dev, "Intel 81342 800MHz"); break; case IOP34X_FREQ_833: device_set_desc(dev, "Intel 81342 833MHz"); break; case IOP34X_FREQ_1000: device_set_desc(dev, "Intel 81342 1000MHz"); break; case IOP34X_FREQ_1200: device_set_desc(dev, "Intel 81342 1200MHz"); break; default: device_set_desc(dev, "Intel 81342 unknown frequency"); break; } return (0); } static void i81342_identify(driver_t *driver, device_t parent) { BUS_ADD_CHILD(parent, 0, "iq", 0); } static int i81342_attach(device_t dev) { struct i81342_softc *sc = device_get_softc(dev); uint32_t esstrsr; i81342_bs_init(&i81342_bs_tag, sc); sc->sc_st = &i81342_bs_tag; sc->sc_sh = IOP34X_VADDR; esstrsr = bus_space_read_4(sc->sc_st, sc->sc_sh, IOP34X_ESSTSR0); sc->sc_atux_sh = IOP34X_ATUX_ADDR(esstrsr) - IOP34X_HWADDR + IOP34X_VADDR; sc->sc_atue_sh = IOP34X_ATUE_ADDR(esstrsr) - IOP34X_HWADDR + IOP34X_VADDR; /* Disable all interrupts. */ intctl0_write(0); intctl1_write(0); intctl2_write(0); intctl3_write(0); /* Defaults to IRQ */ intstr0_write(0); intstr1_write(0); intstr2_write(0); intstr3_write(0); sc->sc_irq_rman.rm_type = RMAN_ARRAY; sc->sc_irq_rman.rm_descr = "i81342 IRQs"; if (rman_init(&sc->sc_irq_rman) != 0 || rman_manage_region(&sc->sc_irq_rman, 0, 127) != 0) panic("i81342_attach: failed to set up IRQ rman"); device_add_child(dev, "obio", 0); device_add_child(dev, "itimer", 0); device_add_child(dev, "iopwdog", 0); device_add_child(dev, "pcib", 0); device_add_child(dev, "pcib", 1); device_add_child(dev, "iqseg", 0); bus_generic_probe(dev); bus_generic_attach(dev); return (0); } static struct resource * i81342_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct i81342_softc *sc = device_get_softc(dev); struct resource *rv; if (type == SYS_RES_IRQ) { rv = rman_reserve_resource(&sc->sc_irq_rman, start, end, count, flags, child); if (rv != NULL) rman_set_rid(rv, *rid); return (rv); } return (NULL); } static int i81342_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { int error; error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep); if (error) return (error); return (0); } static int i81342_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static device_method_t i81342_methods[] = { DEVMETHOD(device_probe, i81342_probe), DEVMETHOD(device_attach, i81342_attach), DEVMETHOD(device_identify, i81342_identify), DEVMETHOD(bus_alloc_resource, i81342_alloc_resource), DEVMETHOD(bus_setup_intr, i81342_setup_intr), DEVMETHOD(bus_teardown_intr, i81342_teardown_intr), {0, 0}, }; static driver_t i81342_driver = { "iq", i81342_methods, sizeof(struct i81342_softc), }; static devclass_t i81342_devclass; DRIVER_MODULE(iq, nexus, i81342_driver, i81342_devclass, 0, 0); Index: head/sys/arm/xscale/ixp425/ixp425.c =================================================================== --- head/sys/arm/xscale/ixp425/ixp425.c (revision 271397) +++ head/sys/arm/xscale/ixp425/ixp425.c (revision 271398) @@ -1,695 +1,696 @@ /* $NetBSD: ixp425.c,v 1.10 2005/12/11 12:16:51 christos Exp $ */ /* * Copyright (c) 2003 * Ichiro FUKUHARA . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Ichiro FUKUHARA. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ddb.h" #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include #include volatile uint32_t intr_enabled; uint32_t intr_steer = 0; /* ixp43x et. al have +32 IRQ's */ volatile uint32_t intr_enabled2; uint32_t intr_steer2 = 0; struct ixp425_softc *ixp425_softc = NULL; struct mtx ixp425_gpio_mtx; static int ixp425_probe(device_t); static void ixp425_identify(driver_t *, device_t); static int ixp425_attach(device_t); /* * Return a mask of the "fuse" bits that identify * which h/w features are present. * NB: assumes the expansion bus is mapped. */ uint32_t ixp4xx_read_feature_bits(void) { uint32_t bits = ~IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET); bits &= ~EXP_FCTRL_RESVD; if (!cpu_is_ixp46x()) bits &= ~EXP_FCTRL_IXP46X_ONLY; return bits; } void ixp4xx_write_feature_bits(uint32_t v) { IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET) = ~v; } struct arm32_dma_range * bus_dma_get_range(void) { return (NULL); } int bus_dma_get_range_nb(void) { return (0); } static const uint8_t int2gpio[32] __attribute__ ((aligned(32))) = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 0xff, 0xff /* INT#30 -> INT#31 */ }; static __inline uint32_t ixp425_irq2gpio_bit(int irq) { return (1U << int2gpio[irq]); } #ifdef DDB #include DB_SHOW_COMMAND(gpio, db_show_gpio) { static const char *itype[8] = { [GPIO_TYPE_ACT_HIGH] = "act-high", [GPIO_TYPE_ACT_LOW] = "act-low", [GPIO_TYPE_EDG_RISING] = "edge-rising", [GPIO_TYPE_EDG_FALLING] = "edge-falling", [GPIO_TYPE_TRANSITIONAL]= "transitional", [5] = "type-5", [6] = "type-6", [7] = "type-7" }; uint32_t gpoutr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR); uint32_t gpoer = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER); uint32_t gpinr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPINR); uint32_t gpit1r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT1R); uint32_t gpit2r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT2R); int i, j; db_printf("GPOUTR %08x GPINR %08x GPOER %08x GPISR %08x\n", gpoutr, gpinr, gpoer, GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPISR)); db_printf("GPIT1R %08x GPIT2R %08x GPCLKR %08x\n", gpit1r, gpit2r, GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPCLKR)); for (i = 0; i < 16; i++) { db_printf("[%2d] out %u in %u %-3s", i, (gpoutr>>i)&1, (gpinr>>i)&1, (gpoer>>i)&1 ? "in" : "out"); for (j = 0; j < 32; j++) if (int2gpio[j] == i) { db_printf(" irq %2u %s", j, itype[ (((i & 8) ? gpit2r : gpit1r) >> (3*(i&7))) & 7]); break; } db_printf("\n"); } } #endif void ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type) { uint32_t gpiotr = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(pin)); IXP4XX_GPIO_LOCK(); /* clear interrupt type */ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin), gpiotr &~ GPIO_TYPE(pin, GPIO_TYPE_MASK)); /* clear any pending interrupt */ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1<> last; for (; mask != 0; mask >>= 1, last++) { if (mask & 1) return last; } last = 32; } if (cpu_is_ixp43x()) { mask = ixp435_irq_read() >> (32-last); for (; mask != 0; mask >>= 1, last++) { if (mask & 1) return last; } } return -1; } void cpu_reset(void) { bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK); bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, IXP425_OST_WDOG, 0); bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, IXP425_OST_WDOG_ENAB, OST_WDOG_ENAB_RST_ENA | OST_WDOG_ENAB_CNT_ENA); printf("Reset failed!\n"); for(;;); } static void ixp425_identify(driver_t *driver, device_t parent) { BUS_ADD_CHILD(parent, 0, "ixp", 0); } static int ixp425_probe(device_t dev) { device_set_desc(dev, "Intel IXP4XX"); return (0); } static int ixp425_attach(device_t dev) { struct ixp425_softc *sc; device_printf(dev, "%b\n", ixp4xx_read_feature_bits(), EXP_FCTRL_BITS); sc = device_get_softc(dev); sc->sc_iot = &ixp425_bs_tag; KASSERT(ixp425_softc == NULL, ("%s called twice?", __func__)); ixp425_softc = sc; intr_enabled = 0; ixp425_set_intrmask(); ixp425_set_intrsteer(); if (cpu_is_ixp43x()) { intr_enabled2 = 0; ixp435_set_intrmask(); ixp435_set_intrsteer(); } arm_post_filter = ixp425_post_filter; mtx_init(&ixp425_gpio_mtx, "gpio", NULL, MTX_DEF); if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE, 0, &sc->sc_gpio_ioh)) panic("%s: unable to map GPIO registers", __func__); if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 0, &sc->sc_exp_ioh)) panic("%s: unable to map Expansion Bus registers", __func__); /* XXX belongs in platform init */ if (cpu_is_ixp43x()) cambria_exp_bus_init(sc); if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_dmat)) panic("%s: failed to create dma tag", __func__); sc->sc_irq_rman.rm_type = RMAN_ARRAY; sc->sc_irq_rman.rm_descr = "IXP4XX IRQs"; if (rman_init(&sc->sc_irq_rman) != 0 || rman_manage_region(&sc->sc_irq_rman, 0, cpu_is_ixp43x() ? 63 : 31) != 0) panic("%s: failed to set up IRQ rman", __func__); sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "IXP4XX Memory"; if (rman_init(&sc->sc_mem_rman) != 0 || rman_manage_region(&sc->sc_mem_rman, 0, ~0) != 0) panic("%s: failed to set up memory rman", __func__); BUS_ADD_CHILD(dev, 0, "pcib", 0); BUS_ADD_CHILD(dev, 0, "ixpclk", 0); BUS_ADD_CHILD(dev, 0, "ixpiic", 0); /* XXX move to hints? */ BUS_ADD_CHILD(dev, 0, "ixpwdog", 0); /* attach wired devices via hints */ bus_enumerate_hinted_children(dev); bus_generic_probe(dev); bus_generic_attach(dev); return (0); } static void ixp425_hinted_child(device_t bus, const char *dname, int dunit) { device_t child; struct ixp425_ivar *ivar; child = BUS_ADD_CHILD(bus, 0, dname, dunit); ivar = IXP425_IVAR(child); resource_int_value(dname, dunit, "addr", &ivar->addr); resource_int_value(dname, dunit, "irq", &ivar->irq); } static device_t ixp425_add_child(device_t dev, u_int order, const char *name, int unit) { device_t child; struct ixp425_ivar *ivar; child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return NULL; ivar = malloc(sizeof(struct ixp425_ivar), M_DEVBUF, M_NOWAIT); if (ivar == NULL) { device_delete_child(dev, child); return NULL; } ivar->addr = 0; ivar->irq = -1; device_set_ivars(child, ivar); return child; } static int ixp425_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct ixp425_ivar *ivar = IXP425_IVAR(child); switch (which) { case IXP425_IVAR_ADDR: if (ivar->addr != 0) { *(uint32_t *)result = ivar->addr; return 0; } break; case IXP425_IVAR_IRQ: if (ivar->irq != -1) { *(int *)result = ivar->irq; return 0; } break; } return EINVAL; } /* * NB: This table handles P->V translations for regions setup with * static mappings in initarm. This is used solely for calls to * bus_alloc_resource_any; anything done with bus_space_map is * handled elsewhere and does not require an entry here. * * XXX this table is also used by uart_cpu_getdev via getvbase * (hence the public api) */ struct hwvtrans { uint32_t hwbase; uint32_t size; uint32_t vbase; int isa4x; /* XXX needs special bus space tag */ int isslow; /* XXX needs special bus space tag */ }; static const struct hwvtrans * gethwvtrans(uint32_t hwbase, uint32_t size) { static const struct hwvtrans hwvtrans[] = { /* NB: needed only for uart_cpu_getdev */ { .hwbase = IXP425_UART0_HWBASE, .size = IXP425_REG_SIZE, .vbase = IXP425_UART0_VBASE, .isa4x = 1 }, { .hwbase = IXP425_UART1_HWBASE, .size = IXP425_REG_SIZE, .vbase = IXP425_UART1_VBASE, .isa4x = 1 }, { .hwbase = IXP425_PCI_HWBASE, .size = IXP425_PCI_SIZE, .vbase = IXP425_PCI_VBASE }, { .hwbase = IXP425_PCI_MEM_HWBASE, .size = IXP425_PCI_MEM_SIZE, .vbase = IXP425_PCI_MEM_VBASE }, { .hwbase = IXP425_EXP_BUS_CS0_HWBASE, .size = IXP425_EXP_BUS_CS0_SIZE, .vbase = IXP425_EXP_BUS_CS0_VBASE }, /* NB: needed for ixp435 ehci controllers */ { .hwbase = IXP435_USB1_HWBASE, .size = IXP435_USB1_SIZE, .vbase = IXP435_USB1_VBASE }, { .hwbase = IXP435_USB2_HWBASE, .size = IXP435_USB2_SIZE, .vbase = IXP435_USB2_VBASE }, { .hwbase = CAMBRIA_GPS_HWBASE, .size = CAMBRIA_GPS_SIZE, .vbase = CAMBRIA_GPS_VBASE, .isslow = 1 }, { .hwbase = CAMBRIA_RS485_HWBASE, .size = CAMBRIA_RS485_SIZE, .vbase = CAMBRIA_RS485_VBASE, .isslow = 1 }, }; int i; for (i = 0; i < sizeof hwvtrans / sizeof *hwvtrans; i++) { if (hwbase >= hwvtrans[i].hwbase && hwbase + size <= hwvtrans[i].hwbase + hwvtrans[i].size) return &hwvtrans[i]; } return NULL; } /* XXX for uart_cpu_getdev */ int getvbase(uint32_t hwbase, uint32_t size, uint32_t *vbase) { const struct hwvtrans *hw; hw = gethwvtrans(hwbase, size); if (hw == NULL) return (ENOENT); *vbase = hwbase - hw->hwbase + hw->vbase; return (0); } static struct resource * ixp425_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct ixp425_softc *sc = device_get_softc(dev); const struct hwvtrans *vtrans; struct resource *rv; uint32_t addr; int needactivate = flags & RF_ACTIVE; int irq; flags &= ~RF_ACTIVE; switch (type) { case SYS_RES_IRQ: /* override per hints */ if (BUS_READ_IVAR(dev, child, IXP425_IVAR_IRQ, &irq) == 0) start = end = irq; rv = rman_reserve_resource(&sc->sc_irq_rman, start, end, count, flags, child); if (rv != NULL) rman_set_rid(rv, *rid); break; case SYS_RES_MEMORY: /* override per hints */ if (BUS_READ_IVAR(dev, child, IXP425_IVAR_ADDR, &addr) == 0) { start = addr; /* XXX use nominal window to check for mapping */ vtrans = gethwvtrans(start, 0x1000); if (vtrans != NULL) { /* * Assign the entire mapped region; this may * not be correct but without more info from * the caller we cannot tell. */ end = start + vtrans->size - (start - vtrans->hwbase); if (bootverbose) device_printf(child, "%s: assign 0x%lx:0x%lx%s\n", __func__, start, end - start, vtrans->isa4x ? " A4X" : vtrans->isslow ? " SLOW" : ""); } } else vtrans = gethwvtrans(start, end - start); if (vtrans == NULL) { /* likely means above table needs to be updated */ device_printf(child, "%s: no mapping for 0x%lx:0x%lx\n", __func__, start, end - start); return NULL; } rv = rman_reserve_resource(&sc->sc_mem_rman, start, end, end - start, flags, child); if (rv == NULL) { device_printf(child, "%s: cannot reserve 0x%lx:0x%lx\n", __func__, start, end - start); return NULL; } rman_set_rid(rv, *rid); break; default: rv = NULL; break; } if (rv != NULL && needactivate) { if (bus_activate_resource(child, type, *rid, rv)) { rman_release_resource(rv); return (NULL); } } return (rv); } static int ixp425_release_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { /* NB: no private resources, just release */ return rman_release_resource(r); } static int ixp425_activate_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { struct ixp425_softc *sc = device_get_softc(dev); const struct hwvtrans *vtrans; if (type == SYS_RES_MEMORY) { vtrans = gethwvtrans(rman_get_start(r), rman_get_size(r)); if (vtrans == NULL) { /* NB: should not happen */ device_printf(child, "%s: no mapping for 0x%lx:0x%lx\n", __func__, rman_get_start(r), rman_get_size(r)); return (ENOENT); } if (vtrans->isa4x) rman_set_bustag(r, &ixp425_a4x_bs_tag); else if (vtrans->isslow) rman_set_bustag(r, &cambria_exp_bs_tag); else rman_set_bustag(r, sc->sc_iot); rman_set_bushandle(r, vtrans->vbase); } return (rman_activate_resource(r)); } static int ixp425_deactivate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { /* NB: no private resources, just deactive */ return (rman_deactivate_resource(r)); } static __inline void get_masks(struct resource *res, uint32_t *mask, uint32_t *mask2) { int i; *mask = 0; for (i = rman_get_start(res); i < 32 && i <= rman_get_end(res); i++) *mask |= 1 << i; *mask2 = 0; for (; i <= rman_get_end(res); i++) *mask2 |= 1 << (i - 32); } static __inline void update_masks(uint32_t mask, uint32_t mask2) { intr_enabled = mask; ixp425_set_intrmask(); if (cpu_is_ixp43x()) { intr_enabled2 = mask2; ixp435_set_intrmask(); } } static int ixp425_setup_intr(device_t dev, device_t child, struct resource *res, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { uint32_t mask, mask2; int error; error = BUS_SETUP_INTR(device_get_parent(dev), child, res, flags, filt, intr, arg, cookiep); if (error) return (error); get_masks(res, &mask, &mask2); update_masks(intr_enabled | mask, intr_enabled2 | mask2); return (0); } static int ixp425_teardown_intr(device_t dev, device_t child, struct resource *res, void *cookie) { uint32_t mask, mask2; get_masks(res, &mask, &mask2); update_masks(intr_enabled &~ mask, intr_enabled2 &~ mask2); return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); } static device_method_t ixp425_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ixp425_probe), DEVMETHOD(device_attach, ixp425_attach), DEVMETHOD(device_identify, ixp425_identify), /* Bus interface */ DEVMETHOD(bus_add_child, ixp425_add_child), DEVMETHOD(bus_hinted_child, ixp425_hinted_child), DEVMETHOD(bus_read_ivar, ixp425_read_ivar), DEVMETHOD(bus_alloc_resource, ixp425_alloc_resource), DEVMETHOD(bus_release_resource, ixp425_release_resource), DEVMETHOD(bus_activate_resource, ixp425_activate_resource), DEVMETHOD(bus_deactivate_resource, ixp425_deactivate_resource), DEVMETHOD(bus_setup_intr, ixp425_setup_intr), DEVMETHOD(bus_teardown_intr, ixp425_teardown_intr), {0, 0}, }; static driver_t ixp425_driver = { "ixp", ixp425_methods, sizeof(struct ixp425_softc), }; static devclass_t ixp425_devclass; DRIVER_MODULE(ixp, nexus, ixp425_driver, ixp425_devclass, 0, 0); Index: head/sys/arm/xscale/ixp425/ixp425_pci.c =================================================================== --- head/sys/arm/xscale/ixp425/ixp425_pci.c (revision 271397) +++ head/sys/arm/xscale/ixp425/ixp425_pci.c (revision 271398) @@ -1,476 +1,477 @@ /* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */ /* * Copyright (c) 2003 * Ichiro FUKUHARA . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Ichiro FUKUHARA. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #include extern struct ixp425_softc *ixp425_softc; #define PCI_CSR_WRITE_4(sc, reg, data) \ bus_write_4(sc->sc_csr, reg, data) #define PCI_CSR_READ_4(sc, reg) \ bus_read_4(sc->sc_csr, reg) -#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) +#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I) #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) static device_probe_t ixppcib_probe; static device_attach_t ixppcib_attach; static bus_read_ivar_t ixppcib_read_ivar; static bus_write_ivar_t ixppcib_write_ivar; static bus_setup_intr_t ixppcib_setup_intr; static bus_teardown_intr_t ixppcib_teardown_intr; static bus_alloc_resource_t ixppcib_alloc_resource; static bus_activate_resource_t ixppcib_activate_resource; static bus_deactivate_resource_t ixppcib_deactivate_resource; static bus_release_resource_t ixppcib_release_resource; static pcib_maxslots_t ixppcib_maxslots; static pcib_read_config_t ixppcib_read_config; static pcib_write_config_t ixppcib_write_config; static pcib_route_interrupt_t ixppcib_route_interrupt; static int ixppcib_probe(device_t dev) { device_set_desc(dev, "IXP4XX PCI Bus"); return (0); } static void ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg, uint32_t data) { PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE)); PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data); } static int ixppcib_attach(device_t dev) { int rid; struct ixppcib_softc *sc; sc = device_get_softc(dev); rid = 0; sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE, IXP425_PCI_SIZE, RF_ACTIVE); if (sc->sc_csr == NULL) panic("cannot allocate PCI CSR registers"); ixp425_md_attach(dev); /* always setup the base, incase another OS messes w/ it */ PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b); rid = 0; sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE, IXP425_PCI_MEM_SIZE, RF_ACTIVE); if (sc->sc_mem == NULL) panic("cannot allocate PCI MEM space"); /* NB: PCI dma window is 64M so anything above must be bounced */ if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024, BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_dmat)) panic("couldn't create the PCI dma tag !"); /* * The PCI bus can only address 64MB. However, due to the way our * implementation of busdma works, busdma can't tell if a device * is a PCI device or not. So defaults to the PCI dma tag, which * restrict the DMA'able memory to the first 64MB, and explicitely * create less restrictive tags for non-PCI devices. */ arm_root_dma_tag = sc->sc_dmat; /* * Initialize the bus space tags. */ ixp425_io_bs_init(&sc->sc_pci_iot, sc); ixp425_mem_bs_init(&sc->sc_pci_memt, sc); sc->sc_dev = dev; /* Initialize memory and i/o rmans. */ sc->sc_io_rman.rm_type = RMAN_ARRAY; sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports"; if (rman_init(&sc->sc_io_rman) != 0 || rman_manage_region(&sc->sc_io_rman, 0, IXP425_PCI_IO_SIZE) != 0) { panic("ixppcib_probe: failed to set up I/O rman"); } sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory"; if (rman_init(&sc->sc_mem_rman) != 0 || rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) { panic("ixppcib_probe: failed to set up memory rman"); } /* * PCI->AHB address translation * begin at the physical memory start + OFFSET */ PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, (IXP425_AHB_OFFSET & 0xFF000000) + ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) + ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) + ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) + 0x00010203); #define IXPPCIB_WRITE_CONF(sc, reg, val) \ ixp425_pci_conf_reg_write(sc, reg, val) /* Write Mapping registers PCI Configuration Registers */ /* Base Address 0 - 3 */ IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000); IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000); IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000); IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000); /* Base Address 4 */ IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff); /* Base Address 5 */ IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000); /* Assert some PCI errors */ PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE); #ifdef __ARMEB__ /* * Set up byte lane swapping between little-endian PCI * and the big-endian AHB bus */ PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS); #else PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE); #endif /* * Enable bus mastering and I/O,memory access */ IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND, PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); /* * Wait some more to ensure PCI devices have stabilised. */ DELAY(50000); device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } static int ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) { struct ixppcib_softc *sc; sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_DOMAIN: *result = 0; return (0); case PCIB_IVAR_BUS: *result = sc->sc_bus; return (0); } return (ENOENT); } static int ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) { struct ixppcib_softc *sc; sc = device_get_softc(dev); switch (which) { case PCIB_IVAR_DOMAIN: return (EINVAL); case PCIB_IVAR_BUS: sc->sc_bus = value; return (0); } return (ENOENT); } static int ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep) { return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt, intr, arg, cookiep)); } static int ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec, void *cookie) { return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie)); } static struct resource * ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct ixppcib_softc *sc = device_get_softc(bus); struct rman *rmanp; struct resource *rv; rv = NULL; switch (type) { case SYS_RES_IRQ: rmanp = &sc->sc_irq_rman; break; case SYS_RES_IOPORT: rmanp = &sc->sc_io_rman; break; case SYS_RES_MEMORY: rmanp = &sc->sc_mem_rman; break; default: return (rv); } rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE, child); if (rv == NULL) return (NULL); rman_set_rid(rv, *rid); if (flags & RF_ACTIVE) { if (bus_activate_resource(child, type, *rid, rv)) { rman_release_resource(rv); return (NULL); } } return (rv); } static int ixppcib_activate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { struct ixppcib_softc *sc = device_get_softc(bus); switch (type) { case SYS_RES_IOPORT: rman_set_bustag(r, &sc->sc_pci_iot); rman_set_bushandle(r, rman_get_start(r)); break; case SYS_RES_MEMORY: rman_set_bustag(r, &sc->sc_pci_memt); rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) + (rman_get_start(r) - IXP425_PCI_MEM_HWBASE)); break; } return (rman_activate_resource(r)); } static int ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { device_printf(bus, "%s called deactivate_resource (unexpected)\n", device_get_nameunit(child)); return (ENXIO); } static int ixppcib_release_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { device_printf(bus, "%s called release_resource (unexpected)\n", device_get_nameunit(child)); return (ENXIO); } static void ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func, int reg) { if (bus == 0) { /* configuration type 0 */ PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - (slot & 0x1f))) | ((func & 0x7) << 8) | (reg & ~3)); } else { /* configuration type 1 */ PCI_CSR_WRITE_4(sc, PCI_NP_AD, (bus << 16) | (slot << 11) | (func << 8) | (reg & ~3) | 1); } } static int ixppcib_maxslots(device_t dev) { return (PCI_SLOTMAX); } static u_int32_t ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { struct ixppcib_softc *sc = device_get_softc(dev); u_int32_t data, ret; ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ); ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA); ret >>= (reg & 3) * 8; ret &= 0xffffffff >> ((4 - bytes) * 8); #if 0 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", __func__, bus, slot, func, reg, bytes, ret); #endif /* check & clear PCI abort */ data = PCI_CSR_READ_4(sc, PCI_ISR); if (data & ISR_PFE) { PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); return (-1); } return (ret); } static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 }; static void ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, u_int32_t val, int bytes) { struct ixppcib_softc *sc = device_get_softc(dev); u_int32_t data; #if 0 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", __func__, bus, slot, func, reg, bytes, val); #endif ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); /* Byte enables are active low, so not them first */ PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE | (~(byteenables[bytes] << (reg & 3)) & 0xf0)); PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8)); /* check & clear PCI abort */ data = PCI_CSR_READ_4(sc, PCI_ISR); if (data & ISR_PFE) PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); } static int ixppcib_route_interrupt(device_t bridge, device_t device, int pin) { return (ixp425_md_route_interrupt(bridge, device, pin)); } static device_method_t ixppcib_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ixppcib_probe), DEVMETHOD(device_attach, ixppcib_attach), /* Bus interface */ DEVMETHOD(bus_read_ivar, ixppcib_read_ivar), DEVMETHOD(bus_write_ivar, ixppcib_write_ivar), DEVMETHOD(bus_setup_intr, ixppcib_setup_intr), DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr), DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource), DEVMETHOD(bus_activate_resource, ixppcib_activate_resource), DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource), DEVMETHOD(bus_release_resource, ixppcib_release_resource), /* DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), */ /* pcib interface */ DEVMETHOD(pcib_maxslots, ixppcib_maxslots), DEVMETHOD(pcib_read_config, ixppcib_read_config), DEVMETHOD(pcib_write_config, ixppcib_write_config), DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt), DEVMETHOD_END }; static driver_t ixppcib_driver = { "pcib", ixppcib_methods, sizeof(struct ixppcib_softc), }; static devclass_t ixppcib_devclass; DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0); Index: head/sys/arm/xscale/ixp425/ixp425_timer.c =================================================================== --- head/sys/arm/xscale/ixp425/ixp425_timer.c (revision 271397) +++ head/sys/arm/xscale/ixp425/ixp425_timer.c (revision 271398) @@ -1,268 +1,269 @@ /* $NetBSD: ixp425_timer.c,v 1.11 2006/04/10 03:36:03 simonb Exp $ */ /* * Copyright (c) 2003 * Ichiro FUKUHARA . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Ichiro FUKUHARA. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include #include static uint32_t counts_per_hz; /* callback functions for intr_functions */ int ixpclk_intr(void *); struct ixpclk_softc { device_t sc_dev; bus_addr_t sc_baseaddr; bus_space_tag_t sc_iot; bus_space_handle_t sc_ioh; }; static unsigned ixp425_timer_get_timecount(struct timecounter *tc); #ifndef IXP425_CLOCK_FREQ #define COUNTS_PER_SEC 66666600 /* 66MHz */ #else #define COUNTS_PER_SEC IXP425_CLOCK_FREQ #endif #define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1) static struct ixpclk_softc *ixpclk_sc = NULL; #define GET_TS_VALUE(sc) (*(volatile u_int32_t *) \ (IXP425_TIMER_VBASE + IXP425_OST_TS)) static struct timecounter ixp425_timer_timecounter = { ixp425_timer_get_timecount, /* get_timecount */ NULL, /* no poll_pps */ ~0u, /* counter_mask */ COUNTS_PER_SEC, /* frequency */ "IXP4XX Timer", /* name */ 1000, /* quality */ }; static int ixpclk_probe(device_t dev) { device_set_desc(dev, "IXP4XX Timer"); return (0); } static int ixpclk_attach(device_t dev) { struct ixpclk_softc *sc = device_get_softc(dev); struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); ixpclk_sc = sc; sc->sc_dev = dev; sc->sc_iot = sa->sc_iot; sc->sc_baseaddr = IXP425_TIMER_HWBASE; if (bus_space_map(sc->sc_iot, sc->sc_baseaddr, 8, 0, &sc->sc_ioh)) panic("%s: Cannot map registers", device_get_name(dev)); return (0); } static device_method_t ixpclk_methods[] = { DEVMETHOD(device_probe, ixpclk_probe), DEVMETHOD(device_attach, ixpclk_attach), {0, 0}, }; static driver_t ixpclk_driver = { "ixpclk", ixpclk_methods, sizeof(struct ixpclk_softc), }; static devclass_t ixpclk_devclass; DRIVER_MODULE(ixpclk, ixp, ixpclk_driver, ixpclk_devclass, 0, 0); static unsigned ixp425_timer_get_timecount(struct timecounter *tc) { uint32_t ret; ret = GET_TS_VALUE(sc); return (ret); } /* * cpu_initclocks: * * Initialize the clock and get them going. */ void cpu_initclocks(void) { struct ixpclk_softc* sc = ixpclk_sc; struct resource *irq; device_t dev = sc->sc_dev; u_int oldirqstate; int rid = 0; void *ihl; if (hz < 50 || COUNTS_PER_SEC % hz) { printf("Cannot get %d Hz clock; using 100 Hz\n", hz); hz = 100; } tick = 1000000 / hz; /* number of microseconds between interrupts */ /* * We only have one timer available; stathz and profhz are * always left as 0 (the upper-layer clock code deals with * this situation). */ if (stathz != 0) printf("Cannot get %d Hz statclock\n", stathz); stathz = 0; if (profhz != 0) printf("Cannot get %d Hz profclock\n", profhz); profhz = 0; /* Report the clock frequency. */ - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, IXP425_INT_TMR0, IXP425_INT_TMR0, 1, RF_ACTIVE); if (!irq) panic("Unable to setup the clock irq handler.\n"); else bus_setup_intr(dev, irq, INTR_TYPE_CLK, ixpclk_intr, NULL, NULL, &ihl); /* Set up the new clock parameters. */ /* clear interrupt */ bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT | OST_TIM1_INT | OST_TIM0_INT); counts_per_hz = COUNTS_PER_SEC / hz; /* reload value & Timer enable */ bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD, (counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN); tc_init(&ixp425_timer_timecounter); restore_interrupts(oldirqstate); rid = 0; } /* * DELAY: * * Delay for at least N microseconds. */ void DELAY(int n) { u_int32_t first, last; int usecs; if (n == 0) return; /* * Clamp the timeout at a maximum value (about 32 seconds with * a 66MHz clock). *Nobody* should be delay()ing for anywhere * near that length of time and if they are, they should be hung * out to dry. */ if (n >= (0x80000000U / COUNTS_PER_USEC)) usecs = (0x80000000U / COUNTS_PER_USEC) - 1; else usecs = n * COUNTS_PER_USEC; /* Note: Timestamp timer counts *up*, unlike the other timers */ first = GET_TS_VALUE(); while (usecs > 0) { last = GET_TS_VALUE(); usecs -= (int)(last - first); first = last; } } /* * ixpclk_intr: * * Handle the hardclock interrupt. */ int ixpclk_intr(void *arg) { struct ixpclk_softc* sc = ixpclk_sc; struct trapframe *frame = arg; bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, OST_TIM0_INT); hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); return (FILTER_HANDLED); } void cpu_startprofclock(void) { } void cpu_stopprofclock(void) { } Index: head/sys/arm/xscale/pxa/pxa_icu.c =================================================================== --- head/sys/arm/xscale/pxa/pxa_icu.c (revision 271397) +++ head/sys/arm/xscale/pxa/pxa_icu.c (revision 271398) @@ -1,258 +1,259 @@ /*- * Copyright (c) 2006 Benno Rice. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include +#include #include #include #include #include struct pxa_icu_softc { struct resource * pi_res[1]; bus_space_tag_t pi_bst; bus_space_handle_t pi_bsh; }; static struct resource_spec pxa_icu_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; static struct pxa_icu_softc *pxa_icu_softc = NULL; static int pxa_icu_probe(device_t); static int pxa_icu_attach(device_t); uint32_t pxa_icu_get_icip(void); void pxa_icu_clear_icip(int); uint32_t pxa_icu_get_icfp(void); void pxa_icu_clear_icfp(int); uint32_t pxa_icu_get_icmr(void); void pxa_icu_set_icmr(uint32_t); uint32_t pxa_icu_get_iclr(void); void pxa_icu_set_iclr(uint32_t); uint32_t pxa_icu_get_icpr(void); void pxa_icu_idle_enable(void); void pxa_icu_idle_disable(void); extern uint32_t pxa_gpio_intr_flags[]; static int pxa_icu_probe(device_t dev) { device_set_desc(dev, "Interrupt Controller"); return (0); } static int pxa_icu_attach(device_t dev) { int error; struct pxa_icu_softc *sc; sc = (struct pxa_icu_softc *)device_get_softc(dev); if (pxa_icu_softc != NULL) return (ENXIO); pxa_icu_softc = sc; error = bus_alloc_resources(dev, pxa_icu_spec, sc->pi_res); if (error) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } sc->pi_bst = rman_get_bustag(sc->pi_res[0]); sc->pi_bsh = rman_get_bushandle(sc->pi_res[0]); /* Disable all interrupts. */ pxa_icu_set_icmr(0); /* Route all interrupts to IRQ rather than FIQ. */ pxa_icu_set_iclr(0); /* XXX: This should move to configure_final or something. */ - enable_interrupts(I32_bit|F32_bit); + enable_interrupts(PSR_I|PSR_F); return (0); } static device_method_t pxa_icu_methods[] = { DEVMETHOD(device_probe, pxa_icu_probe), DEVMETHOD(device_attach, pxa_icu_attach), {0, 0} }; static driver_t pxa_icu_driver = { "icu", pxa_icu_methods, sizeof(struct pxa_icu_softc), }; static devclass_t pxa_icu_devclass; DRIVER_MODULE(pxaicu, pxa, pxa_icu_driver, pxa_icu_devclass, 0, 0); int arm_get_next_irq(int last __unused) { int irq; if ((irq = pxa_icu_get_icip()) != 0) { return (ffs(irq) - 1); } return (pxa_gpio_get_next_irq()); } void arm_mask_irq(uintptr_t nb) { uint32_t mr; if (nb >= IRQ_GPIO0) { pxa_gpio_mask_irq(nb); return; } mr = pxa_icu_get_icmr(); mr &= ~(1 << nb); pxa_icu_set_icmr(mr); } void arm_unmask_irq(uintptr_t nb) { uint32_t mr; if (nb >= IRQ_GPIO0) { pxa_gpio_unmask_irq(nb); return; } mr = pxa_icu_get_icmr(); mr |= (1 << nb); pxa_icu_set_icmr(mr); } uint32_t pxa_icu_get_icip() { return (bus_space_read_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_IP)); } void pxa_icu_clear_icip(int irq) { bus_space_write_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_IP, (1 << irq)); } uint32_t pxa_icu_get_icfp() { return (bus_space_read_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_FP)); } void pxa_icu_clear_icfp(int irq) { bus_space_write_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_FP, (1 << irq)); } uint32_t pxa_icu_get_icmr() { return (bus_space_read_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_MR)); } void pxa_icu_set_icmr(uint32_t val) { bus_space_write_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_MR, val); } uint32_t pxa_icu_get_iclr() { return (bus_space_read_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_LR)); } void pxa_icu_set_iclr(uint32_t val) { bus_space_write_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_LR, val); } uint32_t pxa_icu_get_icpr() { return (bus_space_read_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_PR)); } void pxa_icu_idle_enable() { bus_space_write_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_CR, 0x0); } void pxa_icu_idle_disable() { bus_space_write_4(pxa_icu_softc->pi_bst, pxa_icu_softc->pi_bsh, ICU_CR, 0x1); } Index: head/sys/arm/xscale/pxa/pxa_timer.c =================================================================== --- head/sys/arm/xscale/pxa/pxa_timer.c (revision 271397) +++ head/sys/arm/xscale/pxa/pxa_timer.c (revision 271398) @@ -1,317 +1,318 @@ /*- * Copyright (c) 2006 Benno Rice. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #define PXA_TIMER_FREQUENCY 3686400 #define PXA_TIMER_TICK (PXA_TIMER_FREQUENCY / hz) struct pxa_timer_softc { struct resource * pt_res[5]; bus_space_tag_t pt_bst; bus_space_handle_t pt_bsh; }; static struct resource_spec pxa_timer_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { SYS_RES_IRQ, 1, RF_ACTIVE }, { SYS_RES_IRQ, 2, RF_ACTIVE }, { SYS_RES_IRQ, 3, RF_ACTIVE }, { -1, 0 } }; static struct pxa_timer_softc *timer_softc = NULL; static int pxa_timer_probe(device_t); static int pxa_timer_attach(device_t); static driver_filter_t pxa_hardclock; static unsigned pxa_timer_get_timecount(struct timecounter *); uint32_t pxa_timer_get_osmr(int); void pxa_timer_set_osmr(int, uint32_t); uint32_t pxa_timer_get_oscr(void); void pxa_timer_set_oscr(uint32_t); uint32_t pxa_timer_get_ossr(void); void pxa_timer_clear_ossr(uint32_t); void pxa_timer_watchdog_enable(void); void pxa_timer_watchdog_disable(void); void pxa_timer_interrupt_enable(int); void pxa_timer_interrupt_disable(int); static struct timecounter pxa_timer_timecounter = { .tc_get_timecount = pxa_timer_get_timecount, .tc_name = "OS Timer", .tc_frequency = PXA_TIMER_FREQUENCY, .tc_counter_mask = ~0u, .tc_quality = 1000, }; static int pxa_timer_probe(device_t dev) { device_set_desc(dev, "OS Timer"); return (0); } static int pxa_timer_attach(device_t dev) { int error; void *ihl; struct pxa_timer_softc *sc; sc = (struct pxa_timer_softc *)device_get_softc(dev); if (timer_softc != NULL) return (ENXIO); error = bus_alloc_resources(dev, pxa_timer_spec, sc->pt_res); if (error) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } sc->pt_bst = rman_get_bustag(sc->pt_res[0]); sc->pt_bsh = rman_get_bushandle(sc->pt_res[0]); timer_softc = sc; pxa_timer_interrupt_disable(-1); pxa_timer_watchdog_disable(); if (bus_setup_intr(dev, sc->pt_res[1], INTR_TYPE_CLK, pxa_hardclock, NULL, NULL, &ihl) != 0) { bus_release_resources(dev, pxa_timer_spec, sc->pt_res); device_printf(dev, "could not setup hardclock interrupt\n"); return (ENXIO); } return (0); } static int pxa_hardclock(void *arg) { struct trapframe *frame; frame = (struct trapframe *)arg; /* Clear the interrupt */ pxa_timer_clear_ossr(OST_SR_CH0); /* Schedule next tick */ pxa_timer_set_osmr(0, pxa_timer_get_oscr() + PXA_TIMER_TICK); /* Do what we came here for */ hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); return (FILTER_HANDLED); } static device_method_t pxa_timer_methods[] = { DEVMETHOD(device_probe, pxa_timer_probe), DEVMETHOD(device_attach, pxa_timer_attach), {0, 0} }; static driver_t pxa_timer_driver = { "timer", pxa_timer_methods, sizeof(struct pxa_timer_softc), }; static devclass_t pxa_timer_devclass; DRIVER_MODULE(pxatimer, pxa, pxa_timer_driver, pxa_timer_devclass, 0, 0); static unsigned pxa_timer_get_timecount(struct timecounter *tc) { return (pxa_timer_get_oscr()); } void cpu_initclocks(void) { pxa_timer_set_oscr(0); pxa_timer_set_osmr(0, PXA_TIMER_TICK); pxa_timer_interrupt_enable(0); tc_init(&pxa_timer_timecounter); } void cpu_reset(void) { uint32_t val; - (void)disable_interrupts(I32_bit|F32_bit); + (void)disable_interrupts(PSR_I|PSR_F); val = pxa_timer_get_oscr(); val += PXA_TIMER_FREQUENCY; pxa_timer_set_osmr(3, val); pxa_timer_watchdog_enable(); for(;;); } void DELAY(int usec) { uint32_t val; if (timer_softc == NULL) { for (; usec > 0; usec--) for (val = 100; val > 0; val--) ; return; } val = pxa_timer_get_oscr(); val += (PXA_TIMER_FREQUENCY * usec) / 1000000; while (pxa_timer_get_oscr() <= val); } uint32_t pxa_timer_get_osmr(int which) { return (bus_space_read_4(timer_softc->pt_bst, timer_softc->pt_bsh, which * 0x4)); } void pxa_timer_set_osmr(int which, uint32_t val) { bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, which * 0x4, val); } uint32_t pxa_timer_get_oscr() { return (bus_space_read_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_CR)); } void pxa_timer_set_oscr(uint32_t val) { bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_CR, val); } uint32_t pxa_timer_get_ossr() { return (bus_space_read_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_SR)); } void pxa_timer_clear_ossr(uint32_t val) { bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_SR, val); } void pxa_timer_watchdog_enable() { bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_WR, 0x1); } void pxa_timer_watchdog_disable() { bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_WR, 0x0); } void pxa_timer_interrupt_enable(int which) { uint32_t oier; if (which == -1) { bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_IR, 0xf); return; } oier = bus_space_read_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_IR); oier |= 1 << which; bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_IR, oier); } void pxa_timer_interrupt_disable(int which) { uint32_t oier; if (which == -1) { bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_IR, 0); } oier = bus_space_read_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_IR); oier &= ~(1 << which); bus_space_write_4(timer_softc->pt_bst, timer_softc->pt_bsh, OST_IR, oier); } Index: head/usr.bin/truss/arm-fbsd.c =================================================================== --- head/usr.bin/truss/arm-fbsd.c (revision 271397) +++ head/usr.bin/truss/arm-fbsd.c (revision 271398) @@ -1,369 +1,369 @@ /* * Copyright 1997 Sean Eric Fagan * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Sean Eric Fagan * 4. Neither the name of the author may be used to endorse or promote * products derived from this software without specific prior written * permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * FreeBSD/arm-specific system call handling. This is probably the most * complex part of the entire truss program, although I've got lots of * it handled relatively cleanly now. The system call names are generated * automatically, thanks to /usr/src/sys/kern/syscalls.master. The * names used for the various structures are confusing, I sadly admit. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "truss.h" #include "syscall.h" #include "extern.h" #include "syscalls.h" static int nsyscalls = sizeof(syscallnames) / sizeof(syscallnames[0]); /* * This is what this particular file uses to keep track of a system call. * It is probably not quite sufficient -- I can probably use the same * structure for the various syscall personalities, and I also probably * need to nest system calls (for signal handlers). * * 'struct syscall' describes the system call; it may be NULL, however, * if we don't know about this particular system call yet. */ struct freebsd_syscall { struct syscall *sc; const char *name; int number; unsigned long *args; int nargs; /* number of arguments -- *not* number of words! */ char **s_args; /* the printable arguments */ }; static struct freebsd_syscall * alloc_fsc(void) { return (malloc(sizeof(struct freebsd_syscall))); } /* Clear up and free parts of the fsc structure. */ static void free_fsc(struct freebsd_syscall *fsc) { int i; free(fsc->args); if (fsc->s_args) { for (i = 0; i < fsc->nargs; i++) free(fsc->s_args[i]); free(fsc->s_args); } free(fsc); } /* * Called when a process has entered a system call. nargs is the * number of words, not number of arguments (a necessary distinction * in some cases). Note that if the STOPEVENT() code in i386/i386/trap.c * is ever changed these functions need to keep up. */ void arm_syscall_entry(struct trussinfo *trussinfo, int nargs) { struct ptrace_io_desc iorequest; struct reg regs; struct freebsd_syscall *fsc; struct syscall *sc; lwpid_t tid; int i, syscall_num; register_t *ap; tid = trussinfo->curthread->tid; if (ptrace(PT_GETREGS, tid, (caddr_t)®s, 0) < 0) { fprintf(trussinfo->outfile, "-- CANNOT READ REGISTERS --\n"); return; } ap = ®s.r[0]; /* * FreeBSD has two special kinds of system call redirctions -- * SYS_syscall, and SYS___syscall. The former is the old syscall() * routine, basically; the latter is for quad-aligned arguments. */ #ifdef __ARM_EABI__ syscall_num = regs.r[7]; #else if ((syscall_num = ptrace(PT_READ_I, tid, (caddr_t)(regs.r[_REG_PC] - INSN_SIZE), 0)) == -1) { fprintf(trussinfo->outfile, "-- CANNOT READ PC --\n"); return; } syscall_num = syscall_num & 0x000fffff; #endif switch (syscall_num) { case SYS_syscall: syscall_num = *ap++; nargs--; break; case SYS___syscall: syscall_num = ap[_QUAD_LOWWORD]; ap += 2; nargs -= 2; break; } fsc = alloc_fsc(); if (fsc == NULL) return; fsc->number = syscall_num; fsc->name = (syscall_num < 0 || syscall_num >= nsyscalls) ? NULL : syscallnames[syscall_num]; if (!fsc->name) { fprintf(trussinfo->outfile, "-- UNKNOWN SYSCALL %d --\n", syscall_num); } if (fsc->name && (trussinfo->flags & FOLLOWFORKS) && (strcmp(fsc->name, "fork") == 0 || strcmp(fsc->name, "rfork") == 0 || strcmp(fsc->name, "vfork") == 0)) trussinfo->curthread->in_fork = 1; if (nargs == 0) return; fsc->args = malloc((1 + nargs) * sizeof(unsigned long)); switch (nargs) { default: /* * The OS doesn't seem to allow more than 10 words of * parameters (yay!). So we shouldn't be here. */ warn("More than 10 words (%d) of arguments!\n", nargs); break; case 10: case 9: case 8: case 7: case 6: case 5: /* * If there are 7-10 words of arguments, they are placed * on the stack, as is normal for other processors. * The fall-through for all of these is deliberate!!! */ // XXX BAD constant used here iorequest.piod_op = PIOD_READ_D; iorequest.piod_offs = (void *)(regs.r_sp + 4 * sizeof(uint32_t)); iorequest.piod_addr = &fsc->args[4]; iorequest.piod_len = (nargs - 4) * sizeof(fsc->args[0]); ptrace(PT_IO, tid, (caddr_t)&iorequest, 0); if (iorequest.piod_len == 0) return; case 4: fsc->args[3] = ap[3]; case 3: fsc->args[2] = ap[2]; case 2: fsc->args[1] = ap[1]; case 1: fsc->args[0] = ap[0]; case 0: break; } sc = NULL; if (fsc->name) sc = get_syscall(fsc->name); if (sc) fsc->nargs = sc->nargs; else { #if DEBUG fprintf(trussinfo->outfile, "unknown syscall %s -- setting " "args to %d\n", fsc->name, nargs); #endif fsc->nargs = nargs; } fsc->s_args = calloc(1, (1 + fsc->nargs) * sizeof(char *)); fsc->sc = sc; /* * At this point, we set up the system call arguments. * We ignore any OUT ones, however -- those are arguments that * are set by the system call, and so are probably meaningless * now. This doesn't currently support arguments that are * passed in *and* out, however. */ if (fsc->name) { #if DEBUG fprintf(stderr, "syscall %s(", fsc->name); #endif for (i = 0; i < fsc->nargs; i++) { #if DEBUG fprintf(stderr, "0x%x%s", sc ? fsc->args[sc->args[i].offset] : fsc->args[i], i < (fsc->nargs - 1) ? "," : ""); #endif if (sc && !(sc->args[i].type & OUT)) { fsc->s_args[i] = print_arg(&sc->args[i], fsc->args, 0, trussinfo); } } #if DEBUG fprintf(stderr, ")\n"); #endif } #if DEBUG fprintf(trussinfo->outfile, "\n"); #endif if (fsc->name != NULL && (strcmp(fsc->name, "execve") == 0 || strcmp(fsc->name, "exit") == 0)) { /* * XXX * This could be done in a more general * manner but it still wouldn't be very pretty. */ if (strcmp(fsc->name, "execve") == 0) { if ((trussinfo->flags & EXECVEARGS) == 0) { if (fsc->s_args[1]) { free(fsc->s_args[1]); fsc->s_args[1] = NULL; } } if ((trussinfo->flags & EXECVEENVS) == 0) { if (fsc->s_args[2]) { free(fsc->s_args[2]); fsc->s_args[2] = NULL; } } } } trussinfo->curthread->fsc = fsc; } /* * And when the system call is done, we handle it here. * Currently, no attempt is made to ensure that the system calls * match -- this needs to be fixed (and is, in fact, why S_SCX includes * the system call number instead of, say, an error status). */ long arm_syscall_exit(struct trussinfo *trussinfo, int syscall_num __unused) { struct reg regs; struct freebsd_syscall *fsc; struct syscall *sc; lwpid_t tid; long retval; int errorp, i; if (trussinfo->curthread->fsc == NULL) return (-1); tid = trussinfo->curthread->tid; if (ptrace(PT_GETREGS, tid, (caddr_t)®s, 0) < 0) { fprintf(trussinfo->outfile, "-- CANNOT READ REGISTERS --\n"); return (-1); } retval = regs.r[0]; - errorp = !!(regs.r_cpsr & PSR_C_bit); + errorp = !!(regs.r_cpsr & PSR_C); /* * This code, while simpler than the initial versions I used, could * stand some significant cleaning. */ fsc = trussinfo->curthread->fsc; sc = fsc->sc; if (!sc) { for (i = 0; i < fsc->nargs; i++) asprintf(&fsc->s_args[i], "0x%lx", fsc->args[i]); } else { /* * Here, we only look for arguments that have OUT masked in -- * otherwise, they were handled in the syscall_entry function. */ for (i = 0; i < sc->nargs; i++) { char *temp; if (sc->args[i].type & OUT) { /* * If an error occurred, then don't bother * getting the data; it may not be valid. */ if (errorp) { asprintf(&temp, "0x%lx", fsc->args[sc->args[i].offset]); } else { temp = print_arg(&sc->args[i], fsc->args, retval, trussinfo); } fsc->s_args[i] = temp; } } } if (fsc->name != NULL && (strcmp(fsc->name, "execve") == 0 || strcmp(fsc->name, "exit") == 0)) trussinfo->curthread->in_syscall = 1; /* * It would probably be a good idea to merge the error handling, * but that complicates things considerably. */ print_syscall_ret(trussinfo, fsc->name, fsc->nargs, fsc->s_args, errorp, retval, fsc->sc); free_fsc(fsc); return (retval); }