Index: head/sys/amd64/amd64/identcpu.c =================================================================== --- head/sys/amd64/amd64/identcpu.c (revision 271097) +++ head/sys/amd64/amd64/identcpu.c (nonexistent) @@ -1,916 +0,0 @@ -/*- - * Copyright (c) 1992 Terrence R. Lambert. - * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. - * Copyright (c) 1997 KATO Takenori. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_cpu.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -static u_int find_cpu_vendor_id(void); -static void print_AMD_info(void); -static void print_via_padlock_info(void); -static void print_vmx_info(void); - -int cpu_class; -char machine[] = "amd64"; - -#ifdef SCTL_MASK32 -extern int adaptive_machine_arch; -#endif - -static int -sysctl_hw_machine(SYSCTL_HANDLER_ARGS) -{ -#ifdef SCTL_MASK32 - static const char machine32[] = "i386"; -#endif - int error; - -#ifdef SCTL_MASK32 - if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) - error = SYSCTL_OUT(req, machine32, sizeof(machine32)); - else -#endif - error = SYSCTL_OUT(req, machine, sizeof(machine)); - return (error); - -} -SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, - NULL, 0, sysctl_hw_machine, "A", "Machine class"); - -static char cpu_model[128]; -SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, - cpu_model, 0, "Machine model"); - -static int hw_clockrate; -SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, - &hw_clockrate, 0, "CPU instruction clock rate"); - -static eventhandler_tag tsc_post_tag; - -static char cpu_brand[48]; - -static struct { - char *cpu_name; - int cpu_class; -} amd64_cpus[] = { - { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ - { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ -}; - -static struct { - char *vendor; - u_int vendor_id; -} cpu_vendors[] = { - { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ - { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ - { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ -}; - - -void -printcpuinfo(void) -{ - u_int regs[4], i; - char *brand; - - cpu_class = amd64_cpus[cpu].cpu_class; - printf("CPU: "); - strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); - - /* Check for extended CPUID information and a processor name. */ - if (cpu_exthigh >= 0x80000004) { - brand = cpu_brand; - for (i = 0x80000002; i < 0x80000005; i++) { - do_cpuid(i, regs); - memcpy(brand, regs, sizeof(regs)); - brand += sizeof(regs); - } - } - - switch (cpu_vendor_id) { - case CPU_VENDOR_INTEL: - /* Please make up your mind folks! */ - strcat(cpu_model, "EM64T"); - break; - case CPU_VENDOR_AMD: - /* - * Values taken from AMD Processor Recognition - * http://www.amd.com/K6/k6docs/pdf/20734g.pdf - * (also describes ``Features'' encodings. - */ - strcpy(cpu_model, "AMD "); - if ((cpu_id & 0xf00) == 0xf00) - strcat(cpu_model, "AMD64 Processor"); - else - strcat(cpu_model, "Unknown"); - break; - case CPU_VENDOR_CENTAUR: - strcpy(cpu_model, "VIA "); - if ((cpu_id & 0xff0) == 0x6f0) - strcat(cpu_model, "Nano Processor"); - else - strcat(cpu_model, "Unknown"); - break; - default: - strcat(cpu_model, "Unknown"); - break; - } - - /* - * Replace cpu_model with cpu_brand minus leading spaces if - * we have one. - */ - brand = cpu_brand; - while (*brand == ' ') - ++brand; - if (*brand != '\0') - strcpy(cpu_model, brand); - - printf("%s (", cpu_model); - switch(cpu_class) { - case CPUCLASS_K8: - if (tsc_freq != 0) { - hw_clockrate = (tsc_freq + 5000) / 1000000; - printf("%jd.%02d-MHz ", - (intmax_t)(tsc_freq + 4999) / 1000000, - (u_int)((tsc_freq + 4999) / 10000) % 100); - } - printf("K8"); - break; - default: - printf("Unknown"); /* will panic below... */ - } - printf("-class CPU)\n"); - if (*cpu_vendor) - printf(" Origin=\"%s\"", cpu_vendor); - if (cpu_id) - printf(" Id=0x%x", cpu_id); - - if (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD || - cpu_vendor_id == CPU_VENDOR_CENTAUR) { - printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); - printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); - printf(" Stepping=%u", cpu_id & CPUID_STEPPING); - - /* - * AMD CPUID Specification - * http://support.amd.com/us/Embedded_TechDocs/25481.pdf - * - * Intel Processor Identification and CPUID Instruction - * http://www.intel.com/assets/pdf/appnote/241618.pdf - */ - if (cpu_high > 0) { - - /* - * Here we should probably set up flags indicating - * whether or not various features are available. - * The interesting ones are probably VME, PSE, PAE, - * and PGE. The code already assumes without bothering - * to check that all CPUs >= Pentium have a TSC and - * MSRs. - */ - printf("\n Features=0x%b", cpu_feature, - "\020" - "\001FPU" /* Integral FPU */ - "\002VME" /* Extended VM86 mode support */ - "\003DE" /* Debugging Extensions (CR4.DE) */ - "\004PSE" /* 4MByte page tables */ - "\005TSC" /* Timestamp counter */ - "\006MSR" /* Machine specific registers */ - "\007PAE" /* Physical address extension */ - "\010MCE" /* Machine Check support */ - "\011CX8" /* CMPEXCH8 instruction */ - "\012APIC" /* SMP local APIC */ - "\013oldMTRR" /* Previous implementation of MTRR */ - "\014SEP" /* Fast System Call */ - "\015MTRR" /* Memory Type Range Registers */ - "\016PGE" /* PG_G (global bit) support */ - "\017MCA" /* Machine Check Architecture */ - "\020CMOV" /* CMOV instruction */ - "\021PAT" /* Page attributes table */ - "\022PSE36" /* 36 bit address space support */ - "\023PN" /* Processor Serial number */ - "\024CLFLUSH" /* Has the CLFLUSH instruction */ - "\025" - "\026DTS" /* Debug Trace Store */ - "\027ACPI" /* ACPI support */ - "\030MMX" /* MMX instructions */ - "\031FXSR" /* FXSAVE/FXRSTOR */ - "\032SSE" /* Streaming SIMD Extensions */ - "\033SSE2" /* Streaming SIMD Extensions #2 */ - "\034SS" /* Self snoop */ - "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ - "\036TM" /* Thermal Monitor clock slowdown */ - "\037IA64" /* CPU can execute IA64 instructions */ - "\040PBE" /* Pending Break Enable */ - ); - - if (cpu_feature2 != 0) { - printf("\n Features2=0x%b", cpu_feature2, - "\020" - "\001SSE3" /* SSE3 */ - "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ - "\003DTES64" /* 64-bit Debug Trace */ - "\004MON" /* MONITOR/MWAIT Instructions */ - "\005DS_CPL" /* CPL Qualified Debug Store */ - "\006VMX" /* Virtual Machine Extensions */ - "\007SMX" /* Safer Mode Extensions */ - "\010EST" /* Enhanced SpeedStep */ - "\011TM2" /* Thermal Monitor 2 */ - "\012SSSE3" /* SSSE3 */ - "\013CNXT-ID" /* L1 context ID available */ - "\014" - "\015FMA" /* Fused Multiply Add */ - "\016CX16" /* CMPXCHG16B Instruction */ - "\017xTPR" /* Send Task Priority Messages*/ - "\020PDCM" /* Perf/Debug Capability MSR */ - "\021" - "\022PCID" /* Process-context Identifiers*/ - "\023DCA" /* Direct Cache Access */ - "\024SSE4.1" /* SSE 4.1 */ - "\025SSE4.2" /* SSE 4.2 */ - "\026x2APIC" /* xAPIC Extensions */ - "\027MOVBE" /* MOVBE Instruction */ - "\030POPCNT" /* POPCNT Instruction */ - "\031TSCDLT" /* TSC-Deadline Timer */ - "\032AESNI" /* AES Crypto */ - "\033XSAVE" /* XSAVE/XRSTOR States */ - "\034OSXSAVE" /* OS-Enabled State Management*/ - "\035AVX" /* Advanced Vector Extensions */ - "\036F16C" /* Half-precision conversions */ - "\037RDRAND" /* RDRAND Instruction */ - "\040HV" /* Hypervisor */ - ); - } - - if (amd_feature != 0) { - printf("\n AMD Features=0x%b", amd_feature, - "\020" /* in hex */ - "\001" /* Same */ - "\002" /* Same */ - "\003" /* Same */ - "\004" /* Same */ - "\005" /* Same */ - "\006" /* Same */ - "\007" /* Same */ - "\010" /* Same */ - "\011" /* Same */ - "\012" /* Same */ - "\013" /* Undefined */ - "\014SYSCALL" /* Have SYSCALL/SYSRET */ - "\015" /* Same */ - "\016" /* Same */ - "\017" /* Same */ - "\020" /* Same */ - "\021" /* Same */ - "\022" /* Same */ - "\023" /* Reserved, unknown */ - "\024MP" /* Multiprocessor Capable */ - "\025NX" /* Has EFER.NXE, NX */ - "\026" /* Undefined */ - "\027MMX+" /* AMD MMX Extensions */ - "\030" /* Same */ - "\031" /* Same */ - "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ - "\033Page1GB" /* 1-GB large page support */ - "\034RDTSCP" /* RDTSCP */ - "\035" /* Undefined */ - "\036LM" /* 64 bit long mode */ - "\0373DNow!+" /* AMD 3DNow! Extensions */ - "\0403DNow!" /* AMD 3DNow! */ - ); - } - - if (amd_feature2 != 0) { - printf("\n AMD Features2=0x%b", amd_feature2, - "\020" - "\001LAHF" /* LAHF/SAHF in long mode */ - "\002CMP" /* CMP legacy */ - "\003SVM" /* Secure Virtual Mode */ - "\004ExtAPIC" /* Extended APIC register */ - "\005CR8" /* CR8 in legacy mode */ - "\006ABM" /* LZCNT instruction */ - "\007SSE4A" /* SSE4A */ - "\010MAS" /* Misaligned SSE mode */ - "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ - "\012OSVW" /* OS visible workaround */ - "\013IBS" /* Instruction based sampling */ - "\014XOP" /* XOP extended instructions */ - "\015SKINIT" /* SKINIT/STGI */ - "\016WDT" /* Watchdog timer */ - "\017" - "\020LWP" /* Lightweight Profiling */ - "\021FMA4" /* 4-operand FMA instructions */ - "\022TCE" /* Translation Cache Extension */ - "\023" - "\024NodeId" /* NodeId MSR support */ - "\025" - "\026TBM" /* Trailing Bit Manipulation */ - "\027Topology" /* Topology Extensions */ - "\030PCXC" /* Core perf count */ - "\031PNXC" /* NB perf count */ - "\032" - "\033DBE" /* Data Breakpoint extension */ - "\034PTSC" /* Performance TSC */ - "\035PL2I" /* L2I perf count */ - "\036" - "\037" - "\040" - ); - } - - if (cpu_stdext_feature != 0) { - printf("\n Structured Extended Features=0x%b", - cpu_stdext_feature, - "\020" - /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ - "\001FSGSBASE" - "\002TSCADJ" - /* Bit Manipulation Instructions */ - "\004BMI1" - /* Hardware Lock Elision */ - "\005HLE" - /* Advanced Vector Instructions 2 */ - "\006AVX2" - /* Supervisor Mode Execution Prot. */ - "\010SMEP" - /* Bit Manipulation Instructions */ - "\011BMI2" - "\012ERMS" - /* Invalidate Processor Context ID */ - "\013INVPCID" - /* Restricted Transactional Memory */ - "\014RTM" - /* Intel Memory Protection Extensions */ - "\017MPX" - /* AVX512 Foundation */ - "\021AVX512F" - /* Enhanced NRBG */ - "\023RDSEED" - /* ADCX + ADOX */ - "\024ADX" - /* Supervisor Mode Access Prevention */ - "\025SMAP" - "\030CLFLUSHOPT" - "\032PROCTRACE" - "\033AVX512PF" - "\034AVX512ER" - "\035AVX512CD" - "\036SHA" - ); - } - - if (via_feature_rng != 0 || via_feature_xcrypt != 0) - print_via_padlock_info(); - - if (cpu_feature2 & CPUID2_VMX) - print_vmx_info(); - - if ((cpu_feature & CPUID_HTT) && - cpu_vendor_id == CPU_VENDOR_AMD) - cpu_feature &= ~CPUID_HTT; - - /* - * If this CPU supports P-state invariant TSC then - * mention the capability. - */ - if (tsc_is_invariant) { - printf("\n TSC: P-state invariant"); - if (tsc_perf_stat) - printf(", performance statistics"); - } - - } - } - /* Avoid ugly blank lines: only print newline when we have to. */ - if (*cpu_vendor || cpu_id) - printf("\n"); - - if (!bootverbose) - return; - - if (cpu_vendor_id == CPU_VENDOR_AMD) - print_AMD_info(); -} - -void -panicifcpuunsupported(void) -{ - -#ifndef HAMMER -#error "You need to specify a cpu type" -#endif - /* - * Now that we have told the user what they have, - * let them know if that machine type isn't configured. - */ - switch (cpu_class) { - case CPUCLASS_X86: -#ifndef HAMMER - case CPUCLASS_K8: -#endif - panic("CPU class not configured"); - default: - break; - } -} - - -/* Update TSC freq with the value indicated by the caller. */ -static void -tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) -{ - - /* If there was an error during the transition, don't do anything. */ - if (status != 0) - return; - - /* Total setting for this level gives the new frequency in MHz. */ - hw_clockrate = level->total_set.freq; -} - -static void -hook_tsc_freq(void *arg __unused) -{ - - if (tsc_is_invariant) - return; - - tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, - tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); -} - -SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); - -/* - * Final stage of CPU identification. - */ -void -identify_cpu(void) -{ - u_int regs[4], cpu_stdext_disable; - - do_cpuid(0, regs); - cpu_high = regs[0]; - ((u_int *)&cpu_vendor)[0] = regs[1]; - ((u_int *)&cpu_vendor)[1] = regs[3]; - ((u_int *)&cpu_vendor)[2] = regs[2]; - cpu_vendor[12] = '\0'; - cpu_vendor_id = find_cpu_vendor_id(); - - do_cpuid(1, regs); - cpu_id = regs[0]; - cpu_procinfo = regs[1]; - cpu_feature = regs[3]; - cpu_feature2 = regs[2]; - - /* - * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID - * function number again if it is set from BIOS. It is necessary - * for probing correct CPU topology later. - * XXX This is only done on the BSP package. - */ - if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) { - uint64_t msr; - msr = rdmsr(MSR_IA32_MISC_ENABLE); - if ((msr & 0x400000ULL) != 0) { - wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); - do_cpuid(0, regs); - cpu_high = regs[0]; - } - } - - if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { - do_cpuid(5, regs); - cpu_mon_mwait_flags = regs[2]; - cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; - cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; - } - - if (cpu_high >= 7) { - cpuid_count(7, 0, regs); - cpu_stdext_feature = regs[1]; - - /* - * Some hypervisors fail to filter out unsupported - * extended features. For now, disable the - * extensions, activation of which requires setting a - * bit in CR4, and which VM monitors do not support. - */ - if (cpu_feature2 & CPUID2_HV) { - cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | - CPUID_STDEXT_SMEP; - } else - cpu_stdext_disable = 0; - TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); - cpu_stdext_feature &= ~cpu_stdext_disable; - } - - if (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD || - cpu_vendor_id == CPU_VENDOR_CENTAUR) { - do_cpuid(0x80000000, regs); - cpu_exthigh = regs[0]; - } - if (cpu_exthigh >= 0x80000001) { - do_cpuid(0x80000001, regs); - amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); - amd_feature2 = regs[2]; - } - if (cpu_exthigh >= 0x80000007) { - do_cpuid(0x80000007, regs); - amd_pminfo = regs[3]; - } - if (cpu_exthigh >= 0x80000008) { - do_cpuid(0x80000008, regs); - cpu_procinfo2 = regs[2]; - } - - /* XXX */ - cpu = CPU_CLAWHAMMER; -} - -static u_int -find_cpu_vendor_id(void) -{ - int i; - - for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) - if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) - return (cpu_vendors[i].vendor_id); - return (0); -} - -static void -print_AMD_assoc(int i) -{ - if (i == 255) - printf(", fully associative\n"); - else - printf(", %d-way associative\n", i); -} - -static void -print_AMD_l2_assoc(int i) -{ - switch (i & 0x0f) { - case 0: printf(", disabled/not present\n"); break; - case 1: printf(", direct mapped\n"); break; - case 2: printf(", 2-way associative\n"); break; - case 4: printf(", 4-way associative\n"); break; - case 6: printf(", 8-way associative\n"); break; - case 8: printf(", 16-way associative\n"); break; - case 15: printf(", fully associative\n"); break; - default: printf(", reserved configuration\n"); break; - } -} - -static void -print_AMD_info(void) -{ - u_int regs[4]; - - if (cpu_exthigh < 0x80000005) - return; - - do_cpuid(0x80000005, regs); - printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); - print_AMD_assoc(regs[0] >> 24); - - printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); - print_AMD_assoc((regs[0] >> 8) & 0xff); - - printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); - print_AMD_assoc(regs[1] >> 24); - - printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); - print_AMD_assoc((regs[1] >> 8) & 0xff); - - printf("L1 data cache: %d kbytes", regs[2] >> 24); - printf(", %d bytes/line", regs[2] & 0xff); - printf(", %d lines/tag", (regs[2] >> 8) & 0xff); - print_AMD_assoc((regs[2] >> 16) & 0xff); - - printf("L1 instruction cache: %d kbytes", regs[3] >> 24); - printf(", %d bytes/line", regs[3] & 0xff); - printf(", %d lines/tag", (regs[3] >> 8) & 0xff); - print_AMD_assoc((regs[3] >> 16) & 0xff); - - if (cpu_exthigh >= 0x80000006) { - do_cpuid(0x80000006, regs); - if ((regs[0] >> 16) != 0) { - printf("L2 2MB data TLB: %d entries", - (regs[0] >> 16) & 0xfff); - print_AMD_l2_assoc(regs[0] >> 28); - printf("L2 2MB instruction TLB: %d entries", - regs[0] & 0xfff); - print_AMD_l2_assoc((regs[0] >> 28) & 0xf); - } else { - printf("L2 2MB unified TLB: %d entries", - regs[0] & 0xfff); - print_AMD_l2_assoc((regs[0] >> 28) & 0xf); - } - if ((regs[1] >> 16) != 0) { - printf("L2 4KB data TLB: %d entries", - (regs[1] >> 16) & 0xfff); - print_AMD_l2_assoc(regs[1] >> 28); - - printf("L2 4KB instruction TLB: %d entries", - (regs[1] >> 16) & 0xfff); - print_AMD_l2_assoc((regs[1] >> 28) & 0xf); - } else { - printf("L2 4KB unified TLB: %d entries", - (regs[1] >> 16) & 0xfff); - print_AMD_l2_assoc((regs[1] >> 28) & 0xf); - } - printf("L2 unified cache: %d kbytes", regs[2] >> 16); - printf(", %d bytes/line", regs[2] & 0xff); - printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); - print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); - } - - /* - * Opteron Rev E shows a bug as in very rare occasions a read memory - * barrier is not performed as expected if it is followed by a - * non-atomic read-modify-write instruction. - * As long as that bug pops up very rarely (intensive machine usage - * on other operating systems generally generates one unexplainable - * crash any 2 months) and as long as a model specific fix would be - * impratical at this stage, print out a warning string if the broken - * model and family are identified. - */ - if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && - CPUID_TO_MODEL(cpu_id) <= 0x3f) - printf("WARNING: This architecture revision has known SMP " - "hardware bugs which may cause random instability\n"); -} - -static void -print_via_padlock_info(void) -{ - u_int regs[4]; - - do_cpuid(0xc0000001, regs); - printf("\n VIA Padlock Features=0x%b", regs[3], - "\020" - "\003RNG" /* RNG */ - "\007AES" /* ACE */ - "\011AES-CTR" /* ACE2 */ - "\013SHA1,SHA256" /* PHE */ - "\015RSA" /* PMM */ - ); -} - -static uint32_t -vmx_settable(uint64_t basic, int msr, int true_msr) -{ - uint64_t val; - - if (basic & (1UL << 55)) - val = rdmsr(true_msr); - else - val = rdmsr(msr); - - /* Just report the controls that can be set to 1. */ - return (val >> 32); -} - -static void -print_vmx_info(void) -{ - uint64_t basic, msr; - uint32_t entry, exit, mask, pin, proc, proc2; - int comma; - - printf("\n VT-x: "); - msr = rdmsr(MSR_IA32_FEATURE_CONTROL); - if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) - printf("(disabled in BIOS) "); - basic = rdmsr(MSR_VMX_BASIC); - pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, - MSR_VMX_TRUE_PINBASED_CTLS); - proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, - MSR_VMX_TRUE_PROCBASED_CTLS); - if (proc & PROCBASED_SECONDARY_CONTROLS) - proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, - MSR_VMX_PROCBASED_CTLS2); - else - proc2 = 0; - exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); - entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); - - if (!bootverbose) { - comma = 0; - if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && - entry & VM_ENTRY_LOAD_PAT) { - printf("%sPAT", comma ? "," : ""); - comma = 1; - } - if (proc & PROCBASED_HLT_EXITING) { - printf("%sHLT", comma ? "," : ""); - comma = 1; - } - if (proc & PROCBASED_MTF) { - printf("%sMTF", comma ? "," : ""); - comma = 1; - } - if (proc & PROCBASED_PAUSE_EXITING) { - printf("%sPAUSE", comma ? "," : ""); - comma = 1; - } - if (proc2 & PROCBASED2_ENABLE_EPT) { - printf("%sEPT", comma ? "," : ""); - comma = 1; - } - if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { - printf("%sUG", comma ? "," : ""); - comma = 1; - } - if (proc2 & PROCBASED2_ENABLE_VPID) { - printf("%sVPID", comma ? "," : ""); - comma = 1; - } - if (proc & PROCBASED_USE_TPR_SHADOW && - proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && - proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && - proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && - proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { - printf("%sVID", comma ? "," : ""); - comma = 1; - if (pin & PINBASED_POSTED_INTERRUPT) - printf(",PostIntr"); - } - return; - } - - mask = basic >> 32; - printf("Basic Features=0x%b", mask, - "\020" - "\02132PA" /* 32-bit physical addresses */ - "\022SMM" /* SMM dual-monitor */ - "\027INS/OUTS" /* VM-exit info for INS and OUTS */ - "\030TRUE" /* TRUE_CTLS MSRs */ - ); - printf("\n Pin-Based Controls=0x%b", pin, - "\020" - "\001ExtINT" /* External-interrupt exiting */ - "\004NMI" /* NMI exiting */ - "\006VNMI" /* Virtual NMIs */ - "\007PreTmr" /* Activate VMX-preemption timer */ - "\010PostIntr" /* Process posted interrupts */ - ); - printf("\n Primary Processor Controls=0x%b", proc, - "\020" - "\003INTWIN" /* Interrupt-window exiting */ - "\004TSCOff" /* Use TSC offsetting */ - "\010HLT" /* HLT exiting */ - "\012INVLPG" /* INVLPG exiting */ - "\013MWAIT" /* MWAIT exiting */ - "\014RDPMC" /* RDPMC exiting */ - "\015RDTSC" /* RDTSC exiting */ - "\020CR3-LD" /* CR3-load exiting */ - "\021CR3-ST" /* CR3-store exiting */ - "\024CR8-LD" /* CR8-load exiting */ - "\025CR8-ST" /* CR8-store exiting */ - "\026TPR" /* Use TPR shadow */ - "\027NMIWIN" /* NMI-window exiting */ - "\030MOV-DR" /* MOV-DR exiting */ - "\031IO" /* Unconditional I/O exiting */ - "\032IOmap" /* Use I/O bitmaps */ - "\034MTF" /* Monitor trap flag */ - "\035MSRmap" /* Use MSR bitmaps */ - "\036MONITOR" /* MONITOR exiting */ - "\037PAUSE" /* PAUSE exiting */ - ); - if (proc & PROCBASED_SECONDARY_CONTROLS) - printf("\n Secondary Processor Controls=0x%b", proc2, - "\020" - "\001APIC" /* Virtualize APIC accesses */ - "\002EPT" /* Enable EPT */ - "\003DT" /* Descriptor-table exiting */ - "\004RDTSCP" /* Enable RDTSCP */ - "\005x2APIC" /* Virtualize x2APIC mode */ - "\006VPID" /* Enable VPID */ - "\007WBINVD" /* WBINVD exiting */ - "\010UG" /* Unrestricted guest */ - "\011APIC-reg" /* APIC-register virtualization */ - "\012VID" /* Virtual-interrupt delivery */ - "\013PAUSE-loop" /* PAUSE-loop exiting */ - "\014RDRAND" /* RDRAND exiting */ - "\015INVPCID" /* Enable INVPCID */ - "\016VMFUNC" /* Enable VM functions */ - "\017VMCS" /* VMCS shadowing */ - "\020EPT#VE" /* EPT-violation #VE */ - "\021XSAVES" /* Enable XSAVES/XRSTORS */ - ); - printf("\n Exit Controls=0x%b", mask, - "\020" - "\003DR" /* Save debug controls */ - /* Ignore Host address-space size */ - "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ - "\020AckInt" /* Acknowledge interrupt on exit */ - "\023PAT-SV" /* Save MSR_PAT */ - "\024PAT-LD" /* Load MSR_PAT */ - "\025EFER-SV" /* Save MSR_EFER */ - "\026EFER-LD" /* Load MSR_EFER */ - "\027PTMR-SV" /* Save VMX-preemption timer value */ - ); - printf("\n Entry Controls=0x%b", mask, - "\020" - "\003DR" /* Save debug controls */ - /* Ignore IA-32e mode guest */ - /* Ignore Entry to SMM */ - /* Ignore Deactivate dual-monitor treatment */ - "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ - "\017PAT" /* Load MSR_PAT */ - "\020EFER" /* Load MSR_EFER */ - ); - if (proc & PROCBASED_SECONDARY_CONTROLS && - (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { - msr = rdmsr(MSR_VMX_EPT_VPID_CAP); - mask = msr; - printf("\n EPT Features=0x%b", mask, - "\020" - "\001XO" /* Execute-only translations */ - "\007PW4" /* Page-walk length of 4 */ - "\011UC" /* EPT paging-structure mem can be UC */ - "\017WB" /* EPT paging-structure mem can be WB */ - "\0212M" /* EPT PDE can map a 2-Mbyte page */ - "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ - "\025INVEPT" /* INVEPT is supported */ - "\026AD" /* Accessed and dirty flags for EPT */ - "\032single" /* INVEPT single-context type */ - "\033all" /* INVEPT all-context type */ - ); - mask = msr >> 32; - printf("\n VPID Features=0x%b", mask, - "\020" - "\001INVVPID" /* INVVPID is supported */ - "\011individual" /* INVVPID individual-address type */ - "\012single" /* INVVPID single-context type */ - "\013all" /* INVVPID all-context type */ - /* INVVPID single-context-retaining-globals type */ - "\014single-globals" - ); - } -} Property changes on: head/sys/amd64/amd64/identcpu.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/conf/files.amd64 =================================================================== --- head/sys/conf/files.amd64 (revision 271097) +++ head/sys/conf/files.amd64 (revision 271098) @@ -1,562 +1,562 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # # linux32_genassym.o optional compat_linux32 \ dependency "$S/amd64/linux32/linux32_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "linux32_genassym.o" # linux32_assym.h optional compat_linux32 \ dependency "$S/kern/genassym.sh linux32_genassym.o" \ compile-with "sh $S/kern/genassym.sh linux32_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "linux32_assym.h" # ia32_genassym.o standard \ dependency "$S/compat/ia32/ia32_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "ia32_genassym.o" # ia32_assym.h standard \ dependency "$S/kern/genassym.sh ia32_genassym.o" \ compile-with "env NM='${NM}' sh $S/kern/genassym.sh ia32_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "ia32_assym.h" # font.h optional sc_dflt_font \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'static u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'static u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'static u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" # atkbdmap.h optional atkbd_dflt_keymap \ compile-with "/usr/sbin/kbdcontrol -L ${ATKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > atkbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "atkbdmap.h" # ukbdmap.h optional ukbd_dflt_keymap \ compile-with "/usr/sbin/kbdcontrol -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "ukbdmap.h" # hpt27xx_lib.o optional hpt27xx \ dependency "$S/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu" \ compile-with "uudecode < $S/dev/hpt27xx/amd64-elf.hpt27xx_lib.o.uu" \ no-implicit-rule # hptmvraid.o optional hptmv \ dependency "$S/dev/hptmv/amd64-elf.raid.o.uu" \ compile-with "uudecode < $S/dev/hptmv/amd64-elf.raid.o.uu" \ no-implicit-rule # hptnr_lib.o optional hptnr \ dependency "$S/dev/hptnr/amd64-elf.hptnr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptnr/amd64-elf.hptnr_lib.o.uu" \ no-implicit-rule # hptrr_lib.o optional hptrr \ dependency "$S/dev/hptrr/amd64-elf.hptrr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptrr/amd64-elf.hptrr_lib.o.uu" \ no-implicit-rule # amd64/acpica/acpi_machdep.c optional acpi acpi_wakecode.o optional acpi \ dependency "$S/amd64/acpica/acpi_wakecode.S assym.s" \ compile-with "${NORMAL_S}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.o" acpi_wakecode.bin optional acpi \ dependency "acpi_wakecode.o" \ compile-with "${OBJCOPY} -S -O binary acpi_wakecode.o ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.bin" acpi_wakecode.h optional acpi \ dependency "acpi_wakecode.bin" \ compile-with "file2c -sx 'static char wakecode[] = {' '};' < acpi_wakecode.bin > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.h" acpi_wakedata.h optional acpi \ dependency "acpi_wakecode.o" \ compile-with '${NM} -n --defined-only acpi_wakecode.o | while read offset dummy what; do echo "#define $${what} 0x$${offset}"; done > ${.TARGET}' \ no-obj no-implicit-rule before-depend \ clean "acpi_wakedata.h" # amd64/amd64/amd64_mem.c optional mem #amd64/amd64/apic_vector.S standard amd64/amd64/atomic.c standard amd64/amd64/autoconf.c standard amd64/amd64/bios.c standard amd64/amd64/bpf_jit_machdep.c optional bpf_jitter amd64/amd64/cpu_switch.S standard amd64/amd64/db_disasm.c optional ddb amd64/amd64/db_interface.c optional ddb amd64/amd64/db_trace.c optional ddb amd64/amd64/elf_machdep.c standard amd64/amd64/exception.S standard amd64/amd64/fpu.c standard amd64/amd64/gdb_machdep.c optional gdb -amd64/amd64/identcpu.c standard amd64/amd64/in_cksum.c optional inet | inet6 amd64/amd64/initcpu.c standard amd64/amd64/io.c optional io amd64/amd64/locore.S standard no-obj amd64/amd64/xen-locore.S optional xenhvm amd64/amd64/machdep.c standard amd64/amd64/mem.c optional mem amd64/amd64/minidump_machdep.c standard amd64/amd64/mp_machdep.c optional smp amd64/amd64/mp_watchdog.c optional mp_watchdog smp amd64/amd64/mpboot.S optional smp amd64/amd64/pmap.c standard amd64/amd64/prof_machdep.c optional profiling-routine amd64/amd64/ptrace_machdep.c standard amd64/amd64/sigtramp.S standard amd64/amd64/stack_machdep.c optional ddb | stack amd64/amd64/support.S standard amd64/amd64/sys_machdep.c standard amd64/amd64/trap.c standard amd64/amd64/uio_machdep.c standard amd64/amd64/uma_machdep.c standard amd64/amd64/vm_machdep.c standard amd64/pci/pci_cfgreg.c optional pci cddl/contrib/opensolaris/common/atomic/amd64/opensolaris_atomic.S optional zfs compile-with "${ZFS_S}" crypto/aesni/aeskeys_amd64.S optional aesni crypto/aesni/aesni.c optional aesni aesni_wrap.o optional aesni \ dependency "$S/crypto/aesni/aesni_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${PROF} -mmmx -msse -maes ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec crypto/des/des_enc.c optional crypto | ipsec | netsmb crypto/via/padlock.c optional padlock crypto/via/padlock_cipher.c optional padlock crypto/via/padlock_hash.c optional padlock dev/acpica/acpi_if.m standard dev/acpi_support/acpi_wmi_if.m standard dev/agp/agp_amd64.c optional agp dev/agp/agp_i810.c optional agp dev/agp/agp_intel.c optional agp dev/agp/agp_via.c optional agp dev/amdsbwd/amdsbwd.c optional amdsbwd dev/amdtemp/amdtemp.c optional amdtemp dev/arcmsr/arcmsr.c optional arcmsr pci dev/asmc/asmc.c optional asmc isa dev/atkbdc/atkbd.c optional atkbd atkbdc dev/atkbdc/atkbd_atkbdc.c optional atkbd atkbdc dev/atkbdc/atkbdc.c optional atkbdc dev/atkbdc/atkbdc_isa.c optional atkbdc isa dev/atkbdc/atkbdc_subr.c optional atkbdc dev/atkbdc/psm.c optional psm atkbdc dev/bxe/bxe.c optional bxe pci dev/bxe/bxe_stats.c optional bxe pci dev/bxe/bxe_debug.c optional bxe pci dev/bxe/ecore_sp.c optional bxe pci dev/bxe/bxe_elink.c optional bxe pci dev/bxe/57710_init_values.c optional bxe pci dev/bxe/57711_init_values.c optional bxe pci dev/bxe/57712_init_values.c optional bxe pci dev/coretemp/coretemp.c optional coretemp dev/cpuctl/cpuctl.c optional cpuctl dev/dpms/dpms.c optional dpms # There are no systems with isa slots, so all ed isa entries should go.. dev/ed/if_ed_3c503.c optional ed isa ed_3c503 dev/ed/if_ed_isa.c optional ed isa dev/ed/if_ed_wd80x3.c optional ed isa dev/ed/if_ed_hpp.c optional ed isa ed_hpp dev/ed/if_ed_sic.c optional ed isa ed_sic dev/fb/fb.c optional fb | vga dev/fb/s3_pci.c optional s3pci dev/fb/vesa.c optional vga vesa dev/fb/vga.c optional vga dev/ichwd/ichwd.c optional ichwd dev/if_ndis/if_ndis.c optional ndis dev/if_ndis/if_ndis_pccard.c optional ndis pccard dev/if_ndis/if_ndis_pci.c optional ndis cardbus | ndis pci dev/if_ndis/if_ndis_usb.c optional ndis usb dev/io/iodev.c optional io dev/ipmi/ipmi.c optional ipmi dev/ipmi/ipmi_acpi.c optional ipmi acpi dev/ipmi/ipmi_isa.c optional ipmi isa dev/ipmi/ipmi_kcs.c optional ipmi dev/ipmi/ipmi_smic.c optional ipmi dev/ipmi/ipmi_smbus.c optional ipmi smbus dev/ipmi/ipmi_smbios.c optional ipmi dev/ipmi/ipmi_ssif.c optional ipmi smbus dev/ipmi/ipmi_pci.c optional ipmi pci dev/ipmi/ipmi_linux.c optional ipmi compat_linux32 dev/fdc/fdc.c optional fdc dev/fdc/fdc_acpi.c optional fdc dev/fdc/fdc_isa.c optional fdc isa dev/fdc/fdc_pccard.c optional fdc pccard dev/fdt/fdt_x86.c optional fdt dev/hpt27xx/hpt27xx_os_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_osm_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_config.c optional hpt27xx dev/hptmv/entry.c optional hptmv dev/hptmv/mv.c optional hptmv dev/hptmv/gui_lib.c optional hptmv dev/hptmv/hptproc.c optional hptmv dev/hptmv/ioctl.c optional hptmv dev/hptnr/hptnr_os_bsd.c optional hptnr dev/hptnr/hptnr_osm_bsd.c optional hptnr dev/hptnr/hptnr_config.c optional hptnr dev/hptrr/hptrr_os_bsd.c optional hptrr dev/hptrr/hptrr_osm_bsd.c optional hptrr dev/hptrr/hptrr_config.c optional hptrr dev/hwpmc/hwpmc_amd.c optional hwpmc dev/hwpmc/hwpmc_intel.c optional hwpmc dev/hwpmc/hwpmc_core.c optional hwpmc dev/hwpmc/hwpmc_uncore.c optional hwpmc dev/hwpmc/hwpmc_piv.c optional hwpmc dev/hwpmc/hwpmc_tsc.c optional hwpmc dev/hwpmc/hwpmc_x86.c optional hwpmc dev/hyperv/netvsc/hv_net_vsc.c optional hyperv dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c optional hyperv dev/hyperv/netvsc/hv_rndis_filter.c optional hyperv dev/hyperv/stordisengage/hv_ata_pci_disengage.c optional hyperv dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c optional hyperv dev/hyperv/utilities/hv_util.c optional hyperv dev/hyperv/vmbus/hv_channel.c optional hyperv dev/hyperv/vmbus/hv_channel_mgmt.c optional hyperv dev/hyperv/vmbus/hv_connection.c optional hyperv dev/hyperv/vmbus/hv_hv.c optional hyperv dev/hyperv/vmbus/hv_ring_buffer.c optional hyperv dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c optional hyperv dev/kbd/kbd.c optional atkbd | sc | ukbd | vt dev/nfe/if_nfe.c optional nfe pci dev/ntb/if_ntb/if_ntb.c optional if_ntb dev/ntb/ntb_hw/ntb_hw.c optional if_ntb ntb_hw dev/nvd/nvd.c optional nvd nvme dev/nvme/nvme.c optional nvme dev/nvme/nvme_ctrlr.c optional nvme dev/nvme/nvme_ctrlr_cmd.c optional nvme dev/nvme/nvme_ns.c optional nvme dev/nvme/nvme_ns_cmd.c optional nvme dev/nvme/nvme_qpair.c optional nvme dev/nvme/nvme_sysctl.c optional nvme dev/nvme/nvme_test.c optional nvme dev/nvme/nvme_util.c optional nvme dev/nvram/nvram.c optional nvram isa dev/random/ivy.c optional rdrand_rng dev/random/nehemiah.c optional padlock_rng dev/qlxge/qls_dbg.c optional qlxge pci dev/qlxge/qls_dump.c optional qlxge pci dev/qlxge/qls_hw.c optional qlxge pci dev/qlxge/qls_ioctl.c optional qlxge pci dev/qlxge/qls_isr.c optional qlxge pci dev/qlxge/qls_os.c optional qlxge pci dev/qlxgb/qla_dbg.c optional qlxgb pci dev/qlxgb/qla_hw.c optional qlxgb pci dev/qlxgb/qla_ioctl.c optional qlxgb pci dev/qlxgb/qla_isr.c optional qlxgb pci dev/qlxgb/qla_misc.c optional qlxgb pci dev/qlxgb/qla_os.c optional qlxgb pci dev/qlxgbe/ql_dbg.c optional qlxgbe pci dev/qlxgbe/ql_hw.c optional qlxgbe pci dev/qlxgbe/ql_ioctl.c optional qlxgbe pci dev/qlxgbe/ql_isr.c optional qlxgbe pci dev/qlxgbe/ql_misc.c optional qlxgbe pci dev/qlxgbe/ql_os.c optional qlxgbe pci dev/qlxgbe/ql_reset.c optional qlxgbe pci dev/sfxge/common/efx_bootcfg.c optional sfxge inet pci dev/sfxge/common/efx_ev.c optional sfxge inet pci dev/sfxge/common/efx_filter.c optional sfxge inet pci dev/sfxge/common/efx_intr.c optional sfxge inet pci dev/sfxge/common/efx_mac.c optional sfxge inet pci dev/sfxge/common/efx_mcdi.c optional sfxge inet pci dev/sfxge/common/efx_mon.c optional sfxge inet pci dev/sfxge/common/efx_nic.c optional sfxge inet pci dev/sfxge/common/efx_nvram.c optional sfxge inet pci dev/sfxge/common/efx_phy.c optional sfxge inet pci dev/sfxge/common/efx_port.c optional sfxge inet pci dev/sfxge/common/efx_rx.c optional sfxge inet pci dev/sfxge/common/efx_sram.c optional sfxge inet pci dev/sfxge/common/efx_tx.c optional sfxge inet pci dev/sfxge/common/efx_vpd.c optional sfxge inet pci dev/sfxge/common/efx_wol.c optional sfxge inet pci dev/sfxge/common/siena_mac.c optional sfxge inet pci dev/sfxge/common/siena_mon.c optional sfxge inet pci dev/sfxge/common/siena_nic.c optional sfxge inet pci dev/sfxge/common/siena_nvram.c optional sfxge inet pci dev/sfxge/common/siena_phy.c optional sfxge inet pci dev/sfxge/common/siena_sram.c optional sfxge inet pci dev/sfxge/common/siena_vpd.c optional sfxge inet pci dev/sfxge/sfxge.c optional sfxge inet pci dev/sfxge/sfxge_dma.c optional sfxge inet pci dev/sfxge/sfxge_ev.c optional sfxge inet pci dev/sfxge/sfxge_intr.c optional sfxge inet pci dev/sfxge/sfxge_mcdi.c optional sfxge inet pci dev/sfxge/sfxge_port.c optional sfxge inet pci dev/sfxge/sfxge_rx.c optional sfxge inet pci dev/sfxge/sfxge_tx.c optional sfxge inet pci dev/sio/sio.c optional sio dev/sio/sio_isa.c optional sio isa dev/sio/sio_pccard.c optional sio pccard dev/sio/sio_pci.c optional sio pci dev/sio/sio_puc.c optional sio puc dev/speaker/spkr.c optional speaker dev/syscons/apm/apm_saver.c optional apm_saver apm dev/syscons/scterm-teken.c optional sc dev/syscons/scvesactl.c optional sc vga vesa dev/syscons/scvgarndr.c optional sc vga dev/syscons/scvtb.c optional sc dev/tpm/tpm.c optional tpm dev/tpm/tpm_acpi.c optional tpm acpi dev/tpm/tpm_isa.c optional tpm isa dev/uart/uart_cpu_x86.c optional uart dev/viawd/viawd.c optional viawd dev/vmware/vmxnet3/if_vmx.c optional vmx dev/wbwd/wbwd.c optional wbwd dev/wpi/if_wpi.c optional wpi dev/isci/isci.c optional isci dev/isci/isci_controller.c optional isci dev/isci/isci_domain.c optional isci dev/isci/isci_interrupt.c optional isci dev/isci/isci_io_request.c optional isci dev/isci/isci_logger.c optional isci dev/isci/isci_oem_parameters.c optional isci dev/isci/isci_remote_device.c optional isci dev/isci/isci_sysctl.c optional isci dev/isci/isci_task_request.c optional isci dev/isci/isci_timer.c optional isci dev/isci/scil/sati.c optional isci dev/isci/scil/sati_abort_task_set.c optional isci dev/isci/scil/sati_atapi.c optional isci dev/isci/scil/sati_device.c optional isci dev/isci/scil/sati_inquiry.c optional isci dev/isci/scil/sati_log_sense.c optional isci dev/isci/scil/sati_lun_reset.c optional isci dev/isci/scil/sati_mode_pages.c optional isci dev/isci/scil/sati_mode_select.c optional isci dev/isci/scil/sati_mode_sense.c optional isci dev/isci/scil/sati_mode_sense_10.c optional isci dev/isci/scil/sati_mode_sense_6.c optional isci dev/isci/scil/sati_move.c optional isci dev/isci/scil/sati_passthrough.c optional isci dev/isci/scil/sati_read.c optional isci dev/isci/scil/sati_read_buffer.c optional isci dev/isci/scil/sati_read_capacity.c optional isci dev/isci/scil/sati_reassign_blocks.c optional isci dev/isci/scil/sati_report_luns.c optional isci dev/isci/scil/sati_request_sense.c optional isci dev/isci/scil/sati_start_stop_unit.c optional isci dev/isci/scil/sati_synchronize_cache.c optional isci dev/isci/scil/sati_test_unit_ready.c optional isci dev/isci/scil/sati_unmap.c optional isci dev/isci/scil/sati_util.c optional isci dev/isci/scil/sati_verify.c optional isci dev/isci/scil/sati_write.c optional isci dev/isci/scil/sati_write_and_verify.c optional isci dev/isci/scil/sati_write_buffer.c optional isci dev/isci/scil/sati_write_long.c optional isci dev/isci/scil/sci_abstract_list.c optional isci dev/isci/scil/sci_base_controller.c optional isci dev/isci/scil/sci_base_domain.c optional isci dev/isci/scil/sci_base_iterator.c optional isci dev/isci/scil/sci_base_library.c optional isci dev/isci/scil/sci_base_logger.c optional isci dev/isci/scil/sci_base_memory_descriptor_list.c optional isci dev/isci/scil/sci_base_memory_descriptor_list_decorator.c optional isci dev/isci/scil/sci_base_object.c optional isci dev/isci/scil/sci_base_observer.c optional isci dev/isci/scil/sci_base_phy.c optional isci dev/isci/scil/sci_base_port.c optional isci dev/isci/scil/sci_base_remote_device.c optional isci dev/isci/scil/sci_base_request.c optional isci dev/isci/scil/sci_base_state_machine.c optional isci dev/isci/scil/sci_base_state_machine_logger.c optional isci dev/isci/scil/sci_base_state_machine_observer.c optional isci dev/isci/scil/sci_base_subject.c optional isci dev/isci/scil/sci_util.c optional isci dev/isci/scil/scic_sds_controller.c optional isci dev/isci/scil/scic_sds_library.c optional isci dev/isci/scil/scic_sds_pci.c optional isci dev/isci/scil/scic_sds_phy.c optional isci dev/isci/scil/scic_sds_port.c optional isci dev/isci/scil/scic_sds_port_configuration_agent.c optional isci dev/isci/scil/scic_sds_remote_device.c optional isci dev/isci/scil/scic_sds_remote_node_context.c optional isci dev/isci/scil/scic_sds_remote_node_table.c optional isci dev/isci/scil/scic_sds_request.c optional isci dev/isci/scil/scic_sds_sgpio.c optional isci dev/isci/scil/scic_sds_smp_remote_device.c optional isci dev/isci/scil/scic_sds_smp_request.c optional isci dev/isci/scil/scic_sds_ssp_request.c optional isci dev/isci/scil/scic_sds_stp_packet_request.c optional isci dev/isci/scil/scic_sds_stp_remote_device.c optional isci dev/isci/scil/scic_sds_stp_request.c optional isci dev/isci/scil/scic_sds_unsolicited_frame_control.c optional isci dev/isci/scil/scif_sas_controller.c optional isci dev/isci/scil/scif_sas_controller_state_handlers.c optional isci dev/isci/scil/scif_sas_controller_states.c optional isci dev/isci/scil/scif_sas_domain.c optional isci dev/isci/scil/scif_sas_domain_state_handlers.c optional isci dev/isci/scil/scif_sas_domain_states.c optional isci dev/isci/scil/scif_sas_high_priority_request_queue.c optional isci dev/isci/scil/scif_sas_internal_io_request.c optional isci dev/isci/scil/scif_sas_io_request.c optional isci dev/isci/scil/scif_sas_io_request_state_handlers.c optional isci dev/isci/scil/scif_sas_io_request_states.c optional isci dev/isci/scil/scif_sas_library.c optional isci dev/isci/scil/scif_sas_remote_device.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substates.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substates.c optional isci dev/isci/scil/scif_sas_remote_device_state_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_states.c optional isci dev/isci/scil/scif_sas_request.c optional isci dev/isci/scil/scif_sas_smp_activity_clear_affiliation.c optional isci dev/isci/scil/scif_sas_smp_io_request.c optional isci dev/isci/scil/scif_sas_smp_phy.c optional isci dev/isci/scil/scif_sas_smp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_io_request.c optional isci dev/isci/scil/scif_sas_stp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_task_request.c optional isci dev/isci/scil/scif_sas_task_request.c optional isci dev/isci/scil/scif_sas_task_request_state_handlers.c optional isci dev/isci/scil/scif_sas_task_request_states.c optional isci dev/isci/scil/scif_sas_timer.c optional isci dev/virtio/virtio.c optional virtio dev/virtio/virtqueue.c optional virtio dev/virtio/virtio_bus_if.m optional virtio dev/virtio/virtio_if.m optional virtio dev/virtio/pci/virtio_pci.c optional virtio_pci dev/virtio/network/if_vtnet.c optional vtnet dev/virtio/block/virtio_blk.c optional virtio_blk dev/virtio/balloon/virtio_balloon.c optional virtio_balloon dev/virtio/scsi/virtio_scsi.c optional virtio_scsi dev/virtio/random/virtio_random.c optional virtio_random isa/syscons_isa.c optional sc isa/vga_isa.c optional vga kern/kern_clocksource.c standard kern/link_elf_obj.c standard # # IA32 binary support # #amd64/ia32/ia32_exception.S optional compat_freebsd32 amd64/ia32/ia32_reg.c optional compat_freebsd32 amd64/ia32/ia32_signal.c optional compat_freebsd32 amd64/ia32/ia32_sigtramp.S optional compat_freebsd32 amd64/ia32/ia32_syscall.c optional compat_freebsd32 amd64/ia32/ia32_misc.c optional compat_freebsd32 compat/ia32/ia32_sysvec.c optional compat_freebsd32 compat/linprocfs/linprocfs.c optional linprocfs compat/linsysfs/linsysfs.c optional linsysfs # # Linux/i386 binary support # amd64/linux32/linux32_dummy.c optional compat_linux32 amd64/linux32/linux32_locore.s optional compat_linux32 \ dependency "linux32_assym.h" amd64/linux32/linux32_machdep.c optional compat_linux32 amd64/linux32/linux32_support.s optional compat_linux32 \ dependency "linux32_assym.h" amd64/linux32/linux32_sysent.c optional compat_linux32 amd64/linux32/linux32_sysvec.c optional compat_linux32 compat/linux/linux_emul.c optional compat_linux32 compat/linux/linux_file.c optional compat_linux32 compat/linux/linux_fork.c optional compat_linux32 compat/linux/linux_futex.c optional compat_linux32 compat/linux/linux_getcwd.c optional compat_linux32 compat/linux/linux_ioctl.c optional compat_linux32 compat/linux/linux_ipc.c optional compat_linux32 compat/linux/linux_mib.c optional compat_linux32 compat/linux/linux_misc.c optional compat_linux32 compat/linux/linux_signal.c optional compat_linux32 compat/linux/linux_socket.c optional compat_linux32 compat/linux/linux_stats.c optional compat_linux32 compat/linux/linux_sysctl.c optional compat_linux32 compat/linux/linux_time.c optional compat_linux32 compat/linux/linux_uid16.c optional compat_linux32 compat/linux/linux_util.c optional compat_linux32 dev/amr/amr_linux.c optional compat_linux32 amr dev/mfi/mfi_linux.c optional compat_linux32 mfi # # Windows NDIS driver support # compat/ndis/kern_ndis.c optional ndisapi pci compat/ndis/kern_windrv.c optional ndisapi pci compat/ndis/subr_hal.c optional ndisapi pci compat/ndis/subr_ndis.c optional ndisapi pci compat/ndis/subr_ntoskrnl.c optional ndisapi pci compat/ndis/subr_pe.c optional ndisapi pci compat/ndis/subr_usbd.c optional ndisapi pci compat/ndis/winx64_wrap.S optional ndisapi pci # libkern/memmove.c standard libkern/memset.c standard # # x86 real mode BIOS emulator, required by atkbdc/dpms/vesa # compat/x86bios/x86bios.c optional x86bios | atkbd | dpms | vesa contrib/x86emu/x86emu.c optional x86bios | atkbd | dpms | vesa # # bvm console # dev/bvm/bvm_console.c optional bvmconsole dev/bvm/bvm_dbg.c optional bvmdebug # # x86 shared code between IA32, AMD64 and PC98 architectures # x86/acpica/OsdEnvironment.c optional acpi x86/acpica/acpi_apm.c optional acpi x86/acpica/acpi_wakeup.c optional acpi x86/acpica/madt.c optional acpi x86/acpica/srat.c optional acpi x86/bios/smbios.c optional smbios x86/bios/vpd.c optional vpd x86/cpufreq/powernow.c optional cpufreq x86/cpufreq/est.c optional cpufreq x86/cpufreq/hwpstate.c optional cpufreq x86/cpufreq/p4tcc.c optional cpufreq x86/iommu/busdma_dmar.c optional acpi acpi_dmar pci x86/iommu/intel_ctx.c optional acpi acpi_dmar pci x86/iommu/intel_drv.c optional acpi acpi_dmar pci x86/iommu/intel_fault.c optional acpi acpi_dmar pci x86/iommu/intel_gas.c optional acpi acpi_dmar pci x86/iommu/intel_idpgtbl.c optional acpi acpi_dmar pci x86/iommu/intel_qi.c optional acpi acpi_dmar pci x86/iommu/intel_quirks.c optional acpi acpi_dmar pci x86/iommu/intel_utils.c optional acpi acpi_dmar pci x86/isa/atpic.c optional atpic isa x86/isa/atrtc.c standard x86/isa/clock.c standard x86/isa/elcr.c optional atpic isa | mptable x86/isa/isa.c standard x86/isa/isa_dma.c standard x86/isa/nmi.c standard x86/isa/orm.c optional isa x86/pci/pci_bus.c optional pci x86/pci/qpi.c optional pci x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/dump_machdep.c standard x86/x86/fdt_machdep.c optional fdt +x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c standard x86/x86/legacy.c standard x86/x86/local_apic.c standard x86/x86/mca.c standard x86/x86/mptable.c optional mptable x86/x86/mptable_pci.c optional mptable pci x86/x86/msi.c optional pci x86/x86/nexus.c standard x86/x86/tsc.c standard x86/x86/delay.c standard x86/xen/hvm.c optional xenhvm x86/xen/xen_intr.c optional xen | xenhvm x86/xen/pv.c optional xenhvm x86/xen/pvcpu_enum.c optional xenhvm x86/xen/xen_apic.c optional xenhvm x86/xen/xenpv.c optional xenhvm x86/xen/xen_nexus.c optional xenhvm Index: head/sys/conf/files.i386 =================================================================== --- head/sys/conf/files.i386 (revision 271097) +++ head/sys/conf/files.i386 (revision 271098) @@ -1,599 +1,599 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # linux_genassym.o optional compat_linux \ dependency "$S/i386/linux/linux_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "linux_genassym.o" # linux_assym.h optional compat_linux \ dependency "$S/kern/genassym.sh linux_genassym.o" \ compile-with "sh $S/kern/genassym.sh linux_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "linux_assym.h" # svr4_genassym.o optional compat_svr4 \ dependency "$S/i386/svr4/svr4_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "svr4_genassym.o" # svr4_assym.h optional compat_svr4 \ dependency "$S/kern/genassym.sh svr4_genassym.o" \ compile-with "sh $S/kern/genassym.sh svr4_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "svr4_assym.h" # font.h optional sc_dflt_font \ compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'static u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'static u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'static u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \ no-obj no-implicit-rule before-depend \ clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8" # atkbdmap.h optional atkbd_dflt_keymap \ compile-with "/usr/sbin/kbdcontrol -L ${ATKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > atkbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "atkbdmap.h" # ukbdmap.h optional ukbd_dflt_keymap \ compile-with "/usr/sbin/kbdcontrol -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "ukbdmap.h" # hpt27xx_lib.o optional hpt27xx \ dependency "$S/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu" \ compile-with "uudecode < $S/dev/hpt27xx/i386-elf.hpt27xx_lib.o.uu" \ no-implicit-rule # hptmvraid.o optional hptmv \ dependency "$S/dev/hptmv/i386-elf.raid.o.uu" \ compile-with "uudecode < $S/dev/hptmv/i386-elf.raid.o.uu" \ no-implicit-rule # hptnr_lib.o optional hptnr \ dependency "$S/dev/hptnr/i386-elf.hptnr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptnr/i386-elf.hptnr_lib.o.uu" \ no-implicit-rule # hptrr_lib.o optional hptrr \ dependency "$S/dev/hptrr/i386-elf.hptrr_lib.o.uu" \ compile-with "uudecode < $S/dev/hptrr/i386-elf.hptrr_lib.o.uu" \ no-implicit-rule # cddl/contrib/opensolaris/common/atomic/i386/opensolaris_atomic.S optional zfs compile-with "${ZFS_S}" compat/linprocfs/linprocfs.c optional linprocfs compat/linsysfs/linsysfs.c optional linsysfs compat/linux/linux_emul.c optional compat_linux compat/linux/linux_file.c optional compat_linux compat/linux/linux_fork.c optional compat_linux compat/linux/linux_futex.c optional compat_linux compat/linux/linux_getcwd.c optional compat_linux compat/linux/linux_ioctl.c optional compat_linux compat/linux/linux_ipc.c optional compat_linux compat/linux/linux_mib.c optional compat_linux compat/linux/linux_misc.c optional compat_linux compat/linux/linux_signal.c optional compat_linux compat/linux/linux_socket.c optional compat_linux compat/linux/linux_stats.c optional compat_linux compat/linux/linux_sysctl.c optional compat_linux compat/linux/linux_time.c optional compat_linux compat/linux/linux_uid16.c optional compat_linux compat/linux/linux_util.c optional compat_linux compat/ndis/kern_ndis.c optional ndisapi pci compat/ndis/kern_windrv.c optional ndisapi pci compat/ndis/subr_hal.c optional ndisapi pci compat/ndis/subr_ndis.c optional ndisapi pci compat/ndis/subr_ntoskrnl.c optional ndisapi pci compat/ndis/subr_pe.c optional ndisapi pci compat/ndis/subr_usbd.c optional ndisapi pci compat/ndis/winx32_wrap.S optional ndisapi pci compat/svr4/imgact_svr4.c optional compat_svr4 compat/svr4/svr4_fcntl.c optional compat_svr4 compat/svr4/svr4_filio.c optional compat_svr4 compat/svr4/svr4_ioctl.c optional compat_svr4 compat/svr4/svr4_ipc.c optional compat_svr4 compat/svr4/svr4_misc.c optional compat_svr4 compat/svr4/svr4_resource.c optional compat_svr4 compat/svr4/svr4_signal.c optional compat_svr4 compat/svr4/svr4_socket.c optional compat_svr4 compat/svr4/svr4_sockio.c optional compat_svr4 compat/svr4/svr4_stat.c optional compat_svr4 compat/svr4/svr4_stream.c optional compat_svr4 compat/svr4/svr4_syscallnames.c optional compat_svr4 compat/svr4/svr4_sysent.c optional compat_svr4 compat/svr4/svr4_sysvec.c optional compat_svr4 compat/svr4/svr4_termios.c optional compat_svr4 bf_enc.o optional crypto | ipsec \ dependency "$S/crypto/blowfish/arch/i386/bf_enc.S $S/crypto/blowfish/arch/i386/bf_enc_586.S $S/crypto/blowfish/arch/i386/bf_enc_686.S" \ compile-with "${CC} -c -I$S/crypto/blowfish/arch/i386 ${ASM_CFLAGS} ${WERROR} ${.IMPSRC}" \ no-implicit-rule crypto/aesni/aeskeys_i386.S optional aesni crypto/aesni/aesni.c optional aesni aesni_wrap.o optional aesni \ dependency "$S/crypto/aesni/aesni_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc} ${WERROR} ${PROF} -mmmx -msse -maes ${.IMPSRC}" \ no-implicit-rule \ clean "aesni_wrap.o" crypto/des/arch/i386/des_enc.S optional crypto | ipsec | netsmb crypto/via/padlock.c optional padlock crypto/via/padlock_cipher.c optional padlock crypto/via/padlock_hash.c optional padlock dev/advansys/adv_isa.c optional adv isa dev/agp/agp_ali.c optional agp dev/agp/agp_amd.c optional agp dev/agp/agp_amd64.c optional agp dev/agp/agp_ati.c optional agp dev/agp/agp_i810.c optional agp dev/agp/agp_intel.c optional agp dev/agp/agp_nvidia.c optional agp dev/agp/agp_sis.c optional agp dev/agp/agp_via.c optional agp dev/aic/aic_isa.c optional aic isa dev/amdsbwd/amdsbwd.c optional amdsbwd dev/amdtemp/amdtemp.c optional amdtemp dev/arcmsr/arcmsr.c optional arcmsr pci dev/asmc/asmc.c optional asmc isa dev/atkbdc/atkbd.c optional atkbd atkbdc dev/atkbdc/atkbd_atkbdc.c optional atkbd atkbdc dev/atkbdc/atkbdc.c optional atkbdc dev/atkbdc/atkbdc_isa.c optional atkbdc isa dev/atkbdc/atkbdc_subr.c optional atkbdc dev/atkbdc/psm.c optional psm atkbdc dev/bxe/bxe.c optional bxe pci dev/bxe/bxe_stats.c optional bxe pci dev/bxe/bxe_debug.c optional bxe pci dev/bxe/ecore_sp.c optional bxe pci dev/bxe/bxe_elink.c optional bxe pci dev/bxe/57710_init_values.c optional bxe pci dev/bxe/57711_init_values.c optional bxe pci dev/bxe/57712_init_values.c optional bxe pci dev/ce/ceddk.c optional ce dev/ce/if_ce.c optional ce dev/ce/tau32-ddk.c optional ce \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/cm/if_cm_isa.c optional cm isa dev/coretemp/coretemp.c optional coretemp dev/cp/cpddk.c optional cp dev/cp/if_cp.c optional cp dev/cpuctl/cpuctl.c optional cpuctl dev/ctau/ctau.c optional ctau dev/ctau/ctddk.c optional ctau dev/ctau/if_ct.c optional ctau dev/cx/csigma.c optional cx dev/cx/cxddk.c optional cx dev/cx/if_cx.c optional cx dev/dpms/dpms.c optional dpms dev/ed/if_ed_3c503.c optional ed isa ed_3c503 dev/ed/if_ed_isa.c optional ed isa dev/ed/if_ed_wd80x3.c optional ed isa dev/ed/if_ed_hpp.c optional ed isa ed_hpp dev/ed/if_ed_sic.c optional ed isa ed_sic dev/fb/fb.c optional fb | vga dev/fb/s3_pci.c optional s3pci dev/fb/vesa.c optional vga vesa dev/fb/vga.c optional vga dev/fdc/fdc.c optional fdc dev/fdc/fdc_acpi.c optional fdc dev/fdc/fdc_isa.c optional fdc isa dev/fdc/fdc_pccard.c optional fdc pccard dev/fdt/fdt_x86.c optional fdt dev/fe/if_fe_isa.c optional fe isa dev/glxiic/glxiic.c optional glxiic dev/glxsb/glxsb.c optional glxsb dev/glxsb/glxsb_hash.c optional glxsb dev/hpt27xx/hpt27xx_os_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_osm_bsd.c optional hpt27xx dev/hpt27xx/hpt27xx_config.c optional hpt27xx dev/hptmv/entry.c optional hptmv dev/hptmv/mv.c optional hptmv dev/hptmv/gui_lib.c optional hptmv dev/hptmv/hptproc.c optional hptmv dev/hptmv/ioctl.c optional hptmv dev/hptnr/hptnr_os_bsd.c optional hptnr dev/hptnr/hptnr_osm_bsd.c optional hptnr dev/hptnr/hptnr_config.c optional hptnr dev/hptrr/hptrr_os_bsd.c optional hptrr dev/hptrr/hptrr_osm_bsd.c optional hptrr dev/hptrr/hptrr_config.c optional hptrr dev/hwpmc/hwpmc_amd.c optional hwpmc dev/hwpmc/hwpmc_intel.c optional hwpmc dev/hwpmc/hwpmc_core.c optional hwpmc dev/hwpmc/hwpmc_uncore.c optional hwpmc dev/hwpmc/hwpmc_pentium.c optional hwpmc dev/hwpmc/hwpmc_piv.c optional hwpmc dev/hwpmc/hwpmc_ppro.c optional hwpmc dev/hwpmc/hwpmc_tsc.c optional hwpmc dev/hwpmc/hwpmc_x86.c optional hwpmc dev/hyperv/netvsc/hv_net_vsc.c optional hyperv dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c optional hyperv dev/hyperv/netvsc/hv_rndis_filter.c optional hyperv dev/hyperv/stordisengage/hv_ata_pci_disengage.c optional hyperv dev/hyperv/storvsc/hv_storvsc_drv_freebsd.c optional hyperv dev/hyperv/utilities/hv_util.c optional hyperv dev/hyperv/vmbus/hv_channel.c optional hyperv dev/hyperv/vmbus/hv_channel_mgmt.c optional hyperv dev/hyperv/vmbus/hv_connection.c optional hyperv dev/hyperv/vmbus/hv_hv.c optional hyperv dev/hyperv/vmbus/hv_ring_buffer.c optional hyperv dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c optional hyperv dev/ichwd/ichwd.c optional ichwd dev/if_ndis/if_ndis.c optional ndis dev/if_ndis/if_ndis_pccard.c optional ndis pccard dev/if_ndis/if_ndis_pci.c optional ndis cardbus | ndis pci dev/if_ndis/if_ndis_usb.c optional ndis usb dev/io/iodev.c optional io dev/ipmi/ipmi.c optional ipmi dev/ipmi/ipmi_acpi.c optional ipmi acpi dev/ipmi/ipmi_isa.c optional ipmi isa dev/ipmi/ipmi_kcs.c optional ipmi dev/ipmi/ipmi_smic.c optional ipmi dev/ipmi/ipmi_smbus.c optional ipmi smbus dev/ipmi/ipmi_smbios.c optional ipmi dev/ipmi/ipmi_ssif.c optional ipmi smbus dev/ipmi/ipmi_pci.c optional ipmi pci dev/ipmi/ipmi_linux.c optional ipmi compat_linux dev/kbd/kbd.c optional atkbd | sc | ukbd | vt dev/le/if_le_isa.c optional le isa dev/mse/mse.c optional mse dev/mse/mse_isa.c optional mse isa dev/nfe/if_nfe.c optional nfe pci dev/nvd/nvd.c optional nvd nvme dev/nvme/nvme.c optional nvme dev/nvme/nvme_ctrlr.c optional nvme dev/nvme/nvme_ctrlr_cmd.c optional nvme dev/nvme/nvme_ns.c optional nvme dev/nvme/nvme_ns_cmd.c optional nvme dev/nvme/nvme_qpair.c optional nvme dev/nvme/nvme_sysctl.c optional nvme dev/nvme/nvme_test.c optional nvme dev/nvme/nvme_util.c optional nvme dev/nvram/nvram.c optional nvram isa dev/pcf/pcf_isa.c optional pcf dev/random/ivy.c optional rdrand_rng dev/random/nehemiah.c optional padlock_rng dev/sbni/if_sbni.c optional sbni dev/sbni/if_sbni_isa.c optional sbni isa dev/sbni/if_sbni_pci.c optional sbni pci dev/sio/sio.c optional sio dev/sio/sio_isa.c optional sio isa dev/sio/sio_pccard.c optional sio pccard dev/sio/sio_pci.c optional sio pci dev/sio/sio_puc.c optional sio puc dev/speaker/spkr.c optional speaker dev/syscons/apm/apm_saver.c optional apm_saver apm dev/syscons/scterm-teken.c optional sc dev/syscons/scvesactl.c optional sc vga vesa dev/syscons/scvgarndr.c optional sc vga dev/syscons/scvtb.c optional sc dev/tpm/tpm.c optional tpm dev/tpm/tpm_acpi.c optional tpm acpi dev/tpm/tpm_isa.c optional tpm isa dev/uart/uart_cpu_x86.c optional uart dev/viawd/viawd.c optional viawd dev/vmware/vmxnet3/if_vmx.c optional vmx dev/acpica/acpi_if.m standard dev/acpi_support/acpi_wmi_if.m standard dev/wbwd/wbwd.c optional wbwd dev/wpi/if_wpi.c optional wpi dev/isci/isci.c optional isci dev/isci/isci_controller.c optional isci dev/isci/isci_domain.c optional isci dev/isci/isci_interrupt.c optional isci dev/isci/isci_io_request.c optional isci dev/isci/isci_logger.c optional isci dev/isci/isci_oem_parameters.c optional isci dev/isci/isci_remote_device.c optional isci dev/isci/isci_sysctl.c optional isci dev/isci/isci_task_request.c optional isci dev/isci/isci_timer.c optional isci dev/isci/scil/sati.c optional isci dev/isci/scil/sati_abort_task_set.c optional isci dev/isci/scil/sati_atapi.c optional isci dev/isci/scil/sati_device.c optional isci dev/isci/scil/sati_inquiry.c optional isci dev/isci/scil/sati_log_sense.c optional isci dev/isci/scil/sati_lun_reset.c optional isci dev/isci/scil/sati_mode_pages.c optional isci dev/isci/scil/sati_mode_select.c optional isci dev/isci/scil/sati_mode_sense.c optional isci dev/isci/scil/sati_mode_sense_10.c optional isci dev/isci/scil/sati_mode_sense_6.c optional isci dev/isci/scil/sati_move.c optional isci dev/isci/scil/sati_passthrough.c optional isci dev/isci/scil/sati_read.c optional isci dev/isci/scil/sati_read_buffer.c optional isci dev/isci/scil/sati_read_capacity.c optional isci dev/isci/scil/sati_reassign_blocks.c optional isci dev/isci/scil/sati_report_luns.c optional isci dev/isci/scil/sati_request_sense.c optional isci dev/isci/scil/sati_start_stop_unit.c optional isci dev/isci/scil/sati_synchronize_cache.c optional isci dev/isci/scil/sati_test_unit_ready.c optional isci dev/isci/scil/sati_unmap.c optional isci dev/isci/scil/sati_util.c optional isci dev/isci/scil/sati_verify.c optional isci dev/isci/scil/sati_write.c optional isci dev/isci/scil/sati_write_and_verify.c optional isci dev/isci/scil/sati_write_buffer.c optional isci dev/isci/scil/sati_write_long.c optional isci dev/isci/scil/sci_abstract_list.c optional isci dev/isci/scil/sci_base_controller.c optional isci dev/isci/scil/sci_base_domain.c optional isci dev/isci/scil/sci_base_iterator.c optional isci dev/isci/scil/sci_base_library.c optional isci dev/isci/scil/sci_base_logger.c optional isci dev/isci/scil/sci_base_memory_descriptor_list.c optional isci dev/isci/scil/sci_base_memory_descriptor_list_decorator.c optional isci dev/isci/scil/sci_base_object.c optional isci dev/isci/scil/sci_base_observer.c optional isci dev/isci/scil/sci_base_phy.c optional isci dev/isci/scil/sci_base_port.c optional isci dev/isci/scil/sci_base_remote_device.c optional isci dev/isci/scil/sci_base_request.c optional isci dev/isci/scil/sci_base_state_machine.c optional isci dev/isci/scil/sci_base_state_machine_logger.c optional isci dev/isci/scil/sci_base_state_machine_observer.c optional isci dev/isci/scil/sci_base_subject.c optional isci dev/isci/scil/sci_util.c optional isci dev/isci/scil/scic_sds_controller.c optional isci dev/isci/scil/scic_sds_library.c optional isci dev/isci/scil/scic_sds_pci.c optional isci dev/isci/scil/scic_sds_phy.c optional isci dev/isci/scil/scic_sds_port.c optional isci dev/isci/scil/scic_sds_port_configuration_agent.c optional isci dev/isci/scil/scic_sds_remote_device.c optional isci dev/isci/scil/scic_sds_remote_node_context.c optional isci dev/isci/scil/scic_sds_remote_node_table.c optional isci dev/isci/scil/scic_sds_request.c optional isci dev/isci/scil/scic_sds_sgpio.c optional isci dev/isci/scil/scic_sds_smp_remote_device.c optional isci dev/isci/scil/scic_sds_smp_request.c optional isci dev/isci/scil/scic_sds_ssp_request.c optional isci dev/isci/scil/scic_sds_stp_packet_request.c optional isci dev/isci/scil/scic_sds_stp_remote_device.c optional isci dev/isci/scil/scic_sds_stp_request.c optional isci dev/isci/scil/scic_sds_unsolicited_frame_control.c optional isci dev/isci/scil/scif_sas_controller.c optional isci dev/isci/scil/scif_sas_controller_state_handlers.c optional isci dev/isci/scil/scif_sas_controller_states.c optional isci dev/isci/scil/scif_sas_domain.c optional isci dev/isci/scil/scif_sas_domain_state_handlers.c optional isci dev/isci/scil/scif_sas_domain_states.c optional isci dev/isci/scil/scif_sas_high_priority_request_queue.c optional isci dev/isci/scil/scif_sas_internal_io_request.c optional isci dev/isci/scil/scif_sas_io_request.c optional isci dev/isci/scil/scif_sas_io_request_state_handlers.c optional isci dev/isci/scil/scif_sas_io_request_states.c optional isci dev/isci/scil/scif_sas_library.c optional isci dev/isci/scil/scif_sas_remote_device.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_ready_substates.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substate_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_starting_substates.c optional isci dev/isci/scil/scif_sas_remote_device_state_handlers.c optional isci dev/isci/scil/scif_sas_remote_device_states.c optional isci dev/isci/scil/scif_sas_request.c optional isci dev/isci/scil/scif_sas_smp_activity_clear_affiliation.c optional isci dev/isci/scil/scif_sas_smp_io_request.c optional isci dev/isci/scil/scif_sas_smp_phy.c optional isci dev/isci/scil/scif_sas_smp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_io_request.c optional isci dev/isci/scil/scif_sas_stp_remote_device.c optional isci dev/isci/scil/scif_sas_stp_task_request.c optional isci dev/isci/scil/scif_sas_task_request.c optional isci dev/isci/scil/scif_sas_task_request_state_handlers.c optional isci dev/isci/scil/scif_sas_task_request_states.c optional isci dev/isci/scil/scif_sas_timer.c optional isci dev/virtio/virtio.c optional virtio dev/virtio/virtqueue.c optional virtio dev/virtio/virtio_bus_if.m optional virtio dev/virtio/virtio_if.m optional virtio dev/virtio/pci/virtio_pci.c optional virtio_pci dev/virtio/network/if_vtnet.c optional vtnet dev/virtio/block/virtio_blk.c optional virtio_blk dev/virtio/balloon/virtio_balloon.c optional virtio_balloon dev/virtio/scsi/virtio_scsi.c optional virtio_scsi dev/virtio/random/virtio_random.c optional virtio_random i386/acpica/acpi_machdep.c optional acpi acpi_wakecode.o optional acpi \ dependency "$S/i386/acpica/acpi_wakecode.S assym.s" \ compile-with "${NORMAL_S}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.o" acpi_wakecode.bin optional acpi \ dependency "acpi_wakecode.o" \ compile-with "${OBJCOPY} -S -O binary acpi_wakecode.o ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.bin" acpi_wakecode.h optional acpi \ dependency "acpi_wakecode.bin" \ compile-with "file2c -sx 'static char wakecode[] = {' '};' < acpi_wakecode.bin > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "acpi_wakecode.h" acpi_wakedata.h optional acpi \ dependency "acpi_wakecode.o" \ compile-with '${NM} -n --defined-only acpi_wakecode.o | while read offset dummy what; do echo "#define $${what} 0x$${offset}"; done > ${.TARGET}' \ no-obj no-implicit-rule before-depend \ clean "acpi_wakedata.h" # i386/bios/apm.c optional apm i386/bios/mca_machdep.c optional mca i386/bios/smapi.c optional smapi i386/bios/smapi_bios.S optional smapi #i386/i386/apic_vector.s optional apic i386/i386/atomic.c standard \ compile-with "${CC} -c ${CFLAGS} ${DEFINED_PROF:S/^$/-fomit-frame-pointer/} ${.IMPSRC}" i386/i386/autoconf.c standard i386/i386/bios.c optional native i386/i386/bioscall.s optional native i386/i386/bpf_jit_machdep.c optional bpf_jitter i386/i386/db_disasm.c optional ddb i386/i386/db_interface.c optional ddb i386/i386/db_trace.c optional ddb i386/i386/elan-mmcr.c optional cpu_elan | cpu_soekris i386/i386/elf_machdep.c standard i386/i386/exception.s optional native i386/xen/exception.s optional xen i386/i386/gdb_machdep.c optional gdb i386/i386/geode.c optional cpu_geode i386/i386/i686_mem.c optional mem -i386/i386/identcpu.c standard i386/i386/in_cksum.c optional inet | inet6 i386/i386/initcpu.c standard i386/i386/io.c optional io i386/i386/k6_mem.c optional mem i386/i386/locore.s optional native no-obj i386/xen/locore.s optional xen no-obj i386/i386/longrun.c optional cpu_enable_longrun i386/i386/machdep.c standard i386/xen/xen_machdep.c optional xen i386/i386/mem.c optional mem i386/i386/minidump_machdep.c standard i386/i386/mp_clock.c optional smp i386/i386/mp_machdep.c optional native smp i386/xen/mp_machdep.c optional xen smp i386/i386/mp_watchdog.c optional mp_watchdog smp i386/i386/mpboot.s optional smp native i386/xen/mptable.c optional apic xen i386/i386/perfmon.c optional perfmon i386/i386/pmap.c optional native i386/xen/pmap.c optional xen i386/i386/ptrace_machdep.c standard i386/i386/stack_machdep.c optional ddb | stack i386/i386/support.s standard i386/i386/swtch.s standard i386/i386/sys_machdep.c standard i386/i386/trap.c standard i386/i386/uio_machdep.c standard i386/i386/vm86.c standard i386/i386/vm_machdep.c standard i386/ibcs2/ibcs2_errno.c optional ibcs2 i386/ibcs2/ibcs2_fcntl.c optional ibcs2 i386/ibcs2/ibcs2_ioctl.c optional ibcs2 i386/ibcs2/ibcs2_ipc.c optional ibcs2 i386/ibcs2/ibcs2_isc.c optional ibcs2 i386/ibcs2/ibcs2_isc_sysent.c optional ibcs2 i386/ibcs2/ibcs2_misc.c optional ibcs2 i386/ibcs2/ibcs2_msg.c optional ibcs2 i386/ibcs2/ibcs2_other.c optional ibcs2 i386/ibcs2/ibcs2_signal.c optional ibcs2 i386/ibcs2/ibcs2_socksys.c optional ibcs2 i386/ibcs2/ibcs2_stat.c optional ibcs2 i386/ibcs2/ibcs2_sysent.c optional ibcs2 i386/ibcs2/ibcs2_sysi86.c optional ibcs2 i386/ibcs2/ibcs2_sysvec.c optional ibcs2 i386/ibcs2/ibcs2_util.c optional ibcs2 i386/ibcs2/ibcs2_xenix.c optional ibcs2 i386/ibcs2/ibcs2_xenix_sysent.c optional ibcs2 i386/ibcs2/imgact_coff.c optional ibcs2 i386/xen/clock.c optional xen i386/isa/elink.c optional ep | ie i386/isa/npx.c optional npx i386/isa/pmtimer.c optional pmtimer i386/isa/prof_machdep.c optional profiling-routine i386/isa/spic.c optional spic i386/linux/imgact_linux.c optional compat_linux i386/linux/linux_dummy.c optional compat_linux i386/linux/linux_locore.s optional compat_linux \ dependency "linux_assym.h" i386/linux/linux_machdep.c optional compat_linux i386/linux/linux_ptrace.c optional compat_linux i386/linux/linux_support.s optional compat_linux \ dependency "linux_assym.h" i386/linux/linux_sysent.c optional compat_linux i386/linux/linux_sysvec.c optional compat_linux i386/pci/pci_cfgreg.c optional pci i386/pci/pci_pir.c optional pci i386/svr4/svr4_locore.s optional compat_svr4 \ dependency "svr4_assym.h" \ warning "COMPAT_SVR4 is broken and should be avoided" i386/svr4/svr4_machdep.c optional compat_svr4 # isa/syscons_isa.c optional sc isa/vga_isa.c optional vga kern/kern_clocksource.c standard kern/imgact_aout.c optional compat_aout kern/imgact_gzip.c optional gzip kern/subr_sfbuf.c standard libkern/divdi3.c standard libkern/flsll.c standard libkern/memmove.c standard libkern/memset.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard i386/xbox/xbox.c optional xbox i386/xbox/xboxfb.c optional xboxfb dev/fb/boot_font.c optional xboxfb i386/xbox/pic16l.s optional xbox # # x86 real mode BIOS support, required by atkbdc/dpms/vesa # compat/x86bios/x86bios.c optional x86bios | atkbd | dpms | vesa # # bvm console # dev/bvm/bvm_console.c optional bvmconsole dev/bvm/bvm_dbg.c optional bvmdebug # # x86 shared code between IA32, AMD64 and PC98 architectures # x86/acpica/OsdEnvironment.c optional acpi x86/acpica/acpi_apm.c optional acpi x86/acpica/acpi_wakeup.c optional acpi x86/acpica/madt.c optional acpi apic x86/acpica/srat.c optional acpi x86/bios/smbios.c optional smbios x86/bios/vpd.c optional vpd x86/cpufreq/est.c optional cpufreq x86/cpufreq/hwpstate.c optional cpufreq x86/cpufreq/p4tcc.c optional cpufreq x86/cpufreq/powernow.c optional cpufreq x86/cpufreq/smist.c optional cpufreq x86/iommu/busdma_dmar.c optional acpi acpi_dmar pci x86/iommu/intel_ctx.c optional acpi acpi_dmar pci x86/iommu/intel_drv.c optional acpi acpi_dmar pci x86/iommu/intel_fault.c optional acpi acpi_dmar pci x86/iommu/intel_gas.c optional acpi acpi_dmar pci x86/iommu/intel_idpgtbl.c optional acpi acpi_dmar pci x86/iommu/intel_qi.c optional acpi acpi_dmar pci x86/iommu/intel_quirks.c optional acpi acpi_dmar pci x86/iommu/intel_utils.c optional acpi acpi_dmar pci x86/isa/atpic.c optional atpic x86/isa/atrtc.c optional native x86/isa/clock.c optional native x86/isa/elcr.c optional atpic | apic native x86/isa/isa.c optional isa x86/isa/isa_dma.c optional isa x86/isa/nmi.c standard x86/isa/orm.c optional isa x86/pci/pci_bus.c optional pci x86/pci/qpi.c optional pci x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/dump_machdep.c standard x86/x86/fdt_machdep.c optional fdt +x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c optional apic x86/x86/legacy.c optional native x86/x86/local_apic.c optional apic x86/x86/mca.c standard x86/x86/mptable.c optional apic native x86/x86/mptable_pci.c optional apic native pci x86/x86/msi.c optional apic pci x86/x86/nexus.c standard x86/x86/tsc.c standard x86/x86/delay.c standard x86/xen/hvm.c optional xenhvm x86/xen/xen_intr.c optional xen | xenhvm x86/xen/xen_apic.c optional xenhvm x86/xen/xenpv.c optional xen | xenhvm x86/xen/xen_nexus.c optional xen | xenhvm Index: head/sys/conf/files.pc98 =================================================================== --- head/sys/conf/files.pc98 (revision 271097) +++ head/sys/conf/files.pc98 (revision 271098) @@ -1,262 +1,262 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # # modified for PC-9801/PC-9821 # # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # linux_genassym.o optional compat_linux \ dependency "$S/i386/linux/linux_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "linux_genassym.o" # linux_assym.h optional compat_linux \ dependency "$S/kern/genassym.sh linux_genassym.o" \ compile-with "sh $S/kern/genassym.sh linux_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "linux_assym.h" # svr4_genassym.o optional compat_svr4 \ dependency "$S/i386/svr4/svr4_genassym.c" \ compile-with "${CC} ${CFLAGS:N-fno-common} -c ${.IMPSRC}" \ no-obj no-implicit-rule \ clean "svr4_genassym.o" # svr4_assym.h optional compat_svr4 \ dependency "$S/kern/genassym.sh svr4_genassym.o" \ compile-with "sh $S/kern/genassym.sh svr4_genassym.o > ${.TARGET}" \ no-obj no-implicit-rule before-depend \ clean "svr4_assym.h" # ukbdmap.h optional ukbd_dflt_keymap \ compile-with "/usr/sbin/kbdcontrol -L ${UKBD_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > ukbdmap.h" \ no-obj no-implicit-rule before-depend \ clean "ukbdmap.h" # cddl/contrib/opensolaris/common/atomic/i386/opensolaris_atomic.S optional zfs compile-with "${ZFS_S}" compat/linprocfs/linprocfs.c optional linprocfs compat/linsysfs/linsysfs.c optional linsysfs compat/linux/linux_emul.c optional compat_linux compat/linux/linux_file.c optional compat_linux compat/linux/linux_fork.c optional compat_linux compat/linux/linux_futex.c optional compat_linux compat/linux/linux_getcwd.c optional compat_linux compat/linux/linux_ioctl.c optional compat_linux compat/linux/linux_ipc.c optional compat_linux compat/linux/linux_mib.c optional compat_linux compat/linux/linux_misc.c optional compat_linux compat/linux/linux_signal.c optional compat_linux compat/linux/linux_socket.c optional compat_linux compat/linux/linux_stats.c optional compat_linux compat/linux/linux_sysctl.c optional compat_linux compat/linux/linux_time.c optional compat_linux compat/linux/linux_uid16.c optional compat_linux compat/linux/linux_util.c optional compat_linux compat/svr4/imgact_svr4.c optional compat_svr4 compat/svr4/svr4_fcntl.c optional compat_svr4 compat/svr4/svr4_filio.c optional compat_svr4 compat/svr4/svr4_ioctl.c optional compat_svr4 compat/svr4/svr4_ipc.c optional compat_svr4 compat/svr4/svr4_misc.c optional compat_svr4 compat/svr4/svr4_resource.c optional compat_svr4 compat/svr4/svr4_signal.c optional compat_svr4 compat/svr4/svr4_socket.c optional compat_svr4 compat/svr4/svr4_sockio.c optional compat_svr4 compat/svr4/svr4_stat.c optional compat_svr4 compat/svr4/svr4_stream.c optional compat_svr4 compat/svr4/svr4_syscallnames.c optional compat_svr4 compat/svr4/svr4_sysent.c optional compat_svr4 compat/svr4/svr4_sysvec.c optional compat_svr4 compat/svr4/svr4_termios.c optional compat_svr4 bf_enc.o optional crypto | ipsec \ dependency "$S/crypto/blowfish/arch/i386/bf_enc.S $S/crypto/blowfish/arch/i386/bf_enc_586.S $S/crypto/blowfish/arch/i386/bf_enc_686.S" \ compile-with "${CC} -c -I$S/crypto/blowfish/arch/i386 ${ASM_CFLAGS} ${WERROR} ${.IMPSRC}" \ no-implicit-rule crypto/des/arch/i386/des_enc.S optional crypto | ipsec | netsmb dev/agp/agp_ali.c optional agp dev/agp/agp_amd.c optional agp dev/agp/agp_i810.c optional agp dev/agp/agp_intel.c optional agp dev/agp/agp_nvidia.c optional agp dev/agp/agp_sis.c optional agp dev/agp/agp_via.c optional agp dev/aic/aic_cbus.c optional aic isa dev/ce/ceddk.c optional ce dev/ce/if_ce.c optional ce dev/ce/tau32-ddk.c optional ce dev/cp/cpddk.c optional cp dev/cp/if_cp.c optional cp dev/ct/bshw_machdep.c optional ct dev/ct/ct.c optional ct dev/ct/ct_isa.c optional ct isa dev/ed/if_ed_cbus.c optional ed isa dev/ed/if_ed_wd80x3.c optional ed isa dev/fb/fb.c optional fb | gdc dev/fe/if_fe_cbus.c optional fe isa dev/hwpmc/hwpmc_amd.c optional hwpmc dev/hwpmc/hwpmc_intel.c optional hwpmc dev/hwpmc/hwpmc_core.c optional hwpmc dev/hwpmc/hwpmc_uncore.c optional hwpmc dev/hwpmc/hwpmc_pentium.c optional hwpmc dev/hwpmc/hwpmc_piv.c optional hwpmc dev/hwpmc/hwpmc_ppro.c optional hwpmc dev/hwpmc/hwpmc_tsc.c optional hwpmc dev/hwpmc/hwpmc_x86.c optional hwpmc dev/io/iodev.c optional io dev/kbd/kbd.c optional pckbd | sc | ukbd dev/le/if_le_cbus.c optional le isa dev/mse/mse.c optional mse dev/mse/mse_cbus.c optional mse isa dev/sbni/if_sbni.c optional sbni dev/sbni/if_sbni_pci.c optional sbni pci dev/sio/sio_pccard.c optional sio pccard dev/sio/sio_pci.c optional sio pci dev/sio/sio_puc.c optional sio puc dev/snc/dp83932.c optional snc dev/snc/dp83932subr.c optional snc dev/snc/if_snc.c optional snc dev/snc/if_snc_cbus.c optional snc isa dev/snc/if_snc_pccard.c optional snc pccard dev/speaker/spkr.c optional speaker dev/syscons/apm/apm_saver.c optional apm_saver apm dev/uart/uart_cpu_pc98.c optional uart i386/bios/apm.c optional apm #i386/i386/apic_vector.s optional apic i386/i386/atomic.c standard \ compile-with "${CC} -c ${CFLAGS} ${DEFINED_PROF:S/^$/-fomit-frame-pointer/} ${.IMPSRC}" i386/i386/autoconf.c standard i386/i386/bios.c standard i386/i386/bioscall.s standard i386/i386/bpf_jit_machdep.c optional bpf_jitter i386/i386/db_disasm.c optional ddb i386/i386/db_interface.c optional ddb i386/i386/db_trace.c optional ddb i386/i386/elf_machdep.c standard i386/i386/exception.s standard i386/i386/gdb_machdep.c optional gdb i386/i386/i686_mem.c optional mem -i386/i386/identcpu.c standard i386/i386/in_cksum.c optional inet | inet6 i386/i386/initcpu.c standard i386/i386/io.c optional io i386/i386/k6_mem.c optional mem i386/i386/locore.s standard no-obj i386/i386/mem.c optional mem i386/i386/minidump_machdep.c standard i386/i386/mp_clock.c optional smp i386/i386/mp_machdep.c optional smp i386/i386/mp_watchdog.c optional mp_watchdog smp i386/i386/mpboot.s optional smp i386/i386/perfmon.c optional perfmon i386/i386/pmap.c standard i386/i386/ptrace_machdep.c standard i386/i386/stack_machdep.c optional ddb | stack i386/i386/support.s standard i386/i386/swtch.s standard i386/i386/sys_machdep.c standard i386/i386/trap.c standard i386/i386/uio_machdep.c standard i386/i386/vm86.c standard i386/i386/vm_machdep.c standard i386/ibcs2/ibcs2_errno.c optional ibcs2 i386/ibcs2/ibcs2_fcntl.c optional ibcs2 i386/ibcs2/ibcs2_ioctl.c optional ibcs2 i386/ibcs2/ibcs2_ipc.c optional ibcs2 i386/ibcs2/ibcs2_isc.c optional ibcs2 i386/ibcs2/ibcs2_isc_sysent.c optional ibcs2 i386/ibcs2/ibcs2_misc.c optional ibcs2 i386/ibcs2/ibcs2_msg.c optional ibcs2 i386/ibcs2/ibcs2_other.c optional ibcs2 i386/ibcs2/ibcs2_signal.c optional ibcs2 i386/ibcs2/ibcs2_socksys.c optional ibcs2 i386/ibcs2/ibcs2_stat.c optional ibcs2 i386/ibcs2/ibcs2_sysent.c optional ibcs2 i386/ibcs2/ibcs2_sysi86.c optional ibcs2 i386/ibcs2/ibcs2_sysvec.c optional ibcs2 i386/ibcs2/ibcs2_util.c optional ibcs2 i386/ibcs2/ibcs2_xenix.c optional ibcs2 i386/ibcs2/ibcs2_xenix_sysent.c optional ibcs2 i386/ibcs2/imgact_coff.c optional ibcs2 i386/isa/elink.c optional ep | ie i386/isa/npx.c optional npx i386/isa/pmtimer.c optional pmtimer i386/isa/prof_machdep.c optional profiling-routine i386/linux/imgact_linux.c optional compat_linux i386/linux/linux_dummy.c optional compat_linux i386/linux/linux_locore.s optional compat_linux \ dependency "linux_assym.h" i386/linux/linux_machdep.c optional compat_linux i386/linux/linux_ptrace.c optional compat_linux i386/linux/linux_support.s optional compat_linux \ dependency "linux_assym.h" i386/linux/linux_sysent.c optional compat_linux i386/linux/linux_sysvec.c optional compat_linux i386/pci/pci_cfgreg.c optional pci i386/pci/pci_pir.c optional pci i386/svr4/svr4_locore.s optional compat_svr4 \ dependency "svr4_assym.h" \ warning "COMPAT_SVR4 is broken and should be avoided" i386/svr4/svr4_machdep.c optional compat_svr4 kern/kern_clocksource.c standard kern/imgact_aout.c optional compat_aout kern/imgact_gzip.c optional gzip kern/subr_sfbuf.c standard libkern/divdi3.c standard libkern/flsll.c standard libkern/memmove.c standard libkern/memset.c standard libkern/moddi3.c standard libkern/qdivrem.c standard libkern/ucmpdi2.c standard libkern/udivdi3.c standard libkern/umoddi3.c standard pc98/apm/apm_bioscall.S optional apm pc98/cbus/cbus_dma.c optional isa pc98/cbus/fdc.c optional fdc pc98/cbus/fdc_cbus.c optional fdc isa pc98/cbus/gdc.c optional gdc pc98/cbus/nmi.c standard pc98/cbus/olpt.c optional olpt pc98/cbus/pckbd.c optional pckbd pc98/cbus/pcrtc.c standard pc98/cbus/pmc.c optional pmc pc98/cbus/scgdcrndr.c optional sc gdc pc98/cbus/scterm-sck.c optional sc pc98/cbus/scvtb.c optional sc pc98/cbus/sio.c optional sio pc98/cbus/sio_cbus.c optional sio isa pc98/cbus/syscons_cbus.c optional sc pc98/pc98/busio.s standard pc98/pc98/busiosubr.c standard pc98/pc98/canbepm.c optional canbepm pc98/pc98/canbus.c optional canbus pc98/pc98/canbus_if.m optional canbus pc98/pc98/machdep.c standard pc98/pc98/pc98_machdep.c standard # # x86 shared code between IA32, AMD64 and PC98 architectures # x86/isa/atpic.c optional atpic x86/isa/clock.c standard x86/isa/isa.c optional isa x86/pci/pci_bus.c optional pci x86/x86/busdma_bounce.c standard x86/x86/busdma_machdep.c standard x86/x86/dump_machdep.c standard +x86/x86/identcpu.c standard x86/x86/intr_machdep.c standard x86/x86/io_apic.c optional apic x86/x86/legacy.c standard x86/x86/local_apic.c optional apic x86/x86/mca.c standard x86/x86/mptable.c optional apic x86/x86/mptable_pci.c optional apic pci x86/x86/msi.c optional apic pci x86/x86/nexus.c standard x86/x86/tsc.c standard x86/x86/tsc.c standard x86/x86/delay.c standard Index: head/sys/i386/i386/identcpu.c =================================================================== --- head/sys/i386/i386/identcpu.c (revision 271097) +++ head/sys/i386/i386/identcpu.c (nonexistent) @@ -1,1551 +0,0 @@ -/*- - * Copyright (c) 1992 Terrence R. Lambert. - * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. - * Copyright (c) 1997 KATO Takenori. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_cpu.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define IDENTBLUE_CYRIX486 0 -#define IDENTBLUE_IBMCPU 1 -#define IDENTBLUE_CYRIXM2 2 - -static void identifycyrix(void); -static u_int find_cpu_vendor_id(void); -static void print_AMD_info(void); -static void print_INTEL_info(void); -static void print_INTEL_TLB(u_int data); -static void print_transmeta_info(void); -static void print_via_padlock_info(void); - -int cpu_class; -char machine[] = MACHINE; -SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, - machine, 0, "Machine class"); - -static char cpu_model[128]; -SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, - cpu_model, 0, "Machine model"); - -static int hw_clockrate; -SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, - &hw_clockrate, 0, "CPU instruction clock rate"); - -static eventhandler_tag tsc_post_tag; - -static char cpu_brand[48]; - -#define MAX_BRAND_INDEX 8 - -static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { - NULL, /* No brand */ - "Intel Celeron", - "Intel Pentium III", - "Intel Pentium III Xeon", - NULL, - NULL, - NULL, - NULL, - "Intel Pentium 4" -}; - -static struct { - char *cpu_name; - int cpu_class; -} i386_cpus[] = { - { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ - { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ - { "i386DX", CPUCLASS_386 }, /* CPU_386 */ - { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ - { "i486DX", CPUCLASS_486 }, /* CPU_486 */ - { "Pentium", CPUCLASS_586 }, /* CPU_586 */ - { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ - { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ - { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ - { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ - { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ - { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ - { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ - { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ - { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ - { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ - { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ -}; - -static struct { - char *vendor; - u_int vendor_id; -} cpu_vendors[] = { - { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ - { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ - { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ - { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ - { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ - { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ - { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ - { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ - { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ - { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ -#if 0 - /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ - { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, -#endif -}; - -void -printcpuinfo(void) -{ - u_int regs[4], i; - char *brand; - - cpu_class = i386_cpus[cpu].cpu_class; - printf("CPU: "); - strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model)); - - /* Check for extended CPUID information and a processor name. */ - if (cpu_exthigh >= 0x80000004) { - brand = cpu_brand; - for (i = 0x80000002; i < 0x80000005; i++) { - do_cpuid(i, regs); - memcpy(brand, regs, sizeof(regs)); - brand += sizeof(regs); - } - } - - if (cpu_vendor_id == CPU_VENDOR_INTEL) { - if ((cpu_id & 0xf00) > 0x300) { - u_int brand_index; - - cpu_model[0] = '\0'; - - switch (cpu_id & 0x3000) { - case 0x1000: - strcpy(cpu_model, "Overdrive "); - break; - case 0x2000: - strcpy(cpu_model, "Dual "); - break; - } - - switch (cpu_id & 0xf00) { - case 0x400: - strcat(cpu_model, "i486 "); - /* Check the particular flavor of 486 */ - switch (cpu_id & 0xf0) { - case 0x00: - case 0x10: - strcat(cpu_model, "DX"); - break; - case 0x20: - strcat(cpu_model, "SX"); - break; - case 0x30: - strcat(cpu_model, "DX2"); - break; - case 0x40: - strcat(cpu_model, "SL"); - break; - case 0x50: - strcat(cpu_model, "SX2"); - break; - case 0x70: - strcat(cpu_model, - "DX2 Write-Back Enhanced"); - break; - case 0x80: - strcat(cpu_model, "DX4"); - break; - } - break; - case 0x500: - /* Check the particular flavor of 586 */ - strcat(cpu_model, "Pentium"); - switch (cpu_id & 0xf0) { - case 0x00: - strcat(cpu_model, " A-step"); - break; - case 0x10: - strcat(cpu_model, "/P5"); - break; - case 0x20: - strcat(cpu_model, "/P54C"); - break; - case 0x30: - strcat(cpu_model, "/P24T"); - break; - case 0x40: - strcat(cpu_model, "/P55C"); - break; - case 0x70: - strcat(cpu_model, "/P54C"); - break; - case 0x80: - strcat(cpu_model, "/P55C (quarter-micron)"); - break; - default: - /* nothing */ - break; - } -#if defined(I586_CPU) && !defined(NO_F00F_HACK) - /* - * XXX - If/when Intel fixes the bug, this - * should also check the version of the - * CPU, not just that it's a Pentium. - */ - has_f00f_bug = 1; -#endif - break; - case 0x600: - /* Check the particular flavor of 686 */ - switch (cpu_id & 0xf0) { - case 0x00: - strcat(cpu_model, "Pentium Pro A-step"); - break; - case 0x10: - strcat(cpu_model, "Pentium Pro"); - break; - case 0x30: - case 0x50: - case 0x60: - strcat(cpu_model, - "Pentium II/Pentium II Xeon/Celeron"); - cpu = CPU_PII; - break; - case 0x70: - case 0x80: - case 0xa0: - case 0xb0: - strcat(cpu_model, - "Pentium III/Pentium III Xeon/Celeron"); - cpu = CPU_PIII; - break; - default: - strcat(cpu_model, "Unknown 80686"); - break; - } - break; - case 0xf00: - strcat(cpu_model, "Pentium 4"); - cpu = CPU_P4; - break; - default: - strcat(cpu_model, "unknown"); - break; - } - - /* - * If we didn't get a brand name from the extended - * CPUID, try to look it up in the brand table. - */ - if (cpu_high > 0 && *cpu_brand == '\0') { - brand_index = cpu_procinfo & CPUID_BRAND_INDEX; - if (brand_index <= MAX_BRAND_INDEX && - cpu_brandtable[brand_index] != NULL) - strcpy(cpu_brand, - cpu_brandtable[brand_index]); - } - } - } else if (cpu_vendor_id == CPU_VENDOR_AMD) { - /* - * Values taken from AMD Processor Recognition - * http://www.amd.com/K6/k6docs/pdf/20734g.pdf - * (also describes ``Features'' encodings. - */ - strcpy(cpu_model, "AMD "); - switch (cpu_id & 0xFF0) { - case 0x410: - strcat(cpu_model, "Standard Am486DX"); - break; - case 0x430: - strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); - break; - case 0x470: - strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); - break; - case 0x480: - strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); - break; - case 0x490: - strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); - break; - case 0x4E0: - strcat(cpu_model, "Am5x86 Write-Through"); - break; - case 0x4F0: - strcat(cpu_model, "Am5x86 Write-Back"); - break; - case 0x500: - strcat(cpu_model, "K5 model 0"); - break; - case 0x510: - strcat(cpu_model, "K5 model 1"); - break; - case 0x520: - strcat(cpu_model, "K5 PR166 (model 2)"); - break; - case 0x530: - strcat(cpu_model, "K5 PR200 (model 3)"); - break; - case 0x560: - strcat(cpu_model, "K6"); - break; - case 0x570: - strcat(cpu_model, "K6 266 (model 1)"); - break; - case 0x580: - strcat(cpu_model, "K6-2"); - break; - case 0x590: - strcat(cpu_model, "K6-III"); - break; - case 0x5a0: - strcat(cpu_model, "Geode LX"); - /* - * Make sure the TSC runs through suspension, - * otherwise we can't use it as timecounter - */ - wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); - break; - default: - strcat(cpu_model, "Unknown"); - break; - } -#if defined(I586_CPU) && defined(CPU_WT_ALLOC) - if ((cpu_id & 0xf00) == 0x500) { - if (((cpu_id & 0x0f0) > 0) - && ((cpu_id & 0x0f0) < 0x60) - && ((cpu_id & 0x00f) > 3)) - enable_K5_wt_alloc(); - else if (((cpu_id & 0x0f0) > 0x80) - || (((cpu_id & 0x0f0) == 0x80) - && (cpu_id & 0x00f) > 0x07)) - enable_K6_2_wt_alloc(); - else if ((cpu_id & 0x0f0) > 0x50) - enable_K6_wt_alloc(); - } -#endif - } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { - strcpy(cpu_model, "Cyrix "); - switch (cpu_id & 0xff0) { - case 0x440: - strcat(cpu_model, "MediaGX"); - break; - case 0x520: - strcat(cpu_model, "6x86"); - break; - case 0x540: - cpu_class = CPUCLASS_586; - strcat(cpu_model, "GXm"); - break; - case 0x600: - strcat(cpu_model, "6x86MX"); - break; - default: - /* - * Even though CPU supports the cpuid - * instruction, it can be disabled. - * Therefore, this routine supports all Cyrix - * CPUs. - */ - switch (cyrix_did & 0xf0) { - case 0x00: - switch (cyrix_did & 0x0f) { - case 0x00: - strcat(cpu_model, "486SLC"); - break; - case 0x01: - strcat(cpu_model, "486DLC"); - break; - case 0x02: - strcat(cpu_model, "486SLC2"); - break; - case 0x03: - strcat(cpu_model, "486DLC2"); - break; - case 0x04: - strcat(cpu_model, "486SRx"); - break; - case 0x05: - strcat(cpu_model, "486DRx"); - break; - case 0x06: - strcat(cpu_model, "486SRx2"); - break; - case 0x07: - strcat(cpu_model, "486DRx2"); - break; - case 0x08: - strcat(cpu_model, "486SRu"); - break; - case 0x09: - strcat(cpu_model, "486DRu"); - break; - case 0x0a: - strcat(cpu_model, "486SRu2"); - break; - case 0x0b: - strcat(cpu_model, "486DRu2"); - break; - default: - strcat(cpu_model, "Unknown"); - break; - } - break; - case 0x10: - switch (cyrix_did & 0x0f) { - case 0x00: - strcat(cpu_model, "486S"); - break; - case 0x01: - strcat(cpu_model, "486S2"); - break; - case 0x02: - strcat(cpu_model, "486Se"); - break; - case 0x03: - strcat(cpu_model, "486S2e"); - break; - case 0x0a: - strcat(cpu_model, "486DX"); - break; - case 0x0b: - strcat(cpu_model, "486DX2"); - break; - case 0x0f: - strcat(cpu_model, "486DX4"); - break; - default: - strcat(cpu_model, "Unknown"); - break; - } - break; - case 0x20: - if ((cyrix_did & 0x0f) < 8) - strcat(cpu_model, "6x86"); /* Where did you get it? */ - else - strcat(cpu_model, "5x86"); - break; - case 0x30: - strcat(cpu_model, "6x86"); - break; - case 0x40: - if ((cyrix_did & 0xf000) == 0x3000) { - cpu_class = CPUCLASS_586; - strcat(cpu_model, "GXm"); - } else - strcat(cpu_model, "MediaGX"); - break; - case 0x50: - strcat(cpu_model, "6x86MX"); - break; - case 0xf0: - switch (cyrix_did & 0x0f) { - case 0x0d: - strcat(cpu_model, "Overdrive CPU"); - break; - case 0x0e: - strcpy(cpu_model, "Texas Instruments 486SXL"); - break; - case 0x0f: - strcat(cpu_model, "486SLC/DLC"); - break; - default: - strcat(cpu_model, "Unknown"); - break; - } - break; - default: - strcat(cpu_model, "Unknown"); - break; - } - break; - } - } else if (cpu_vendor_id == CPU_VENDOR_RISE) { - strcpy(cpu_model, "Rise "); - switch (cpu_id & 0xff0) { - case 0x500: /* 6401 and 6441 (Kirin) */ - case 0x520: /* 6510 (Lynx) */ - strcat(cpu_model, "mP6"); - break; - default: - strcat(cpu_model, "Unknown"); - } - } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) { - switch (cpu_id & 0xff0) { - case 0x540: - strcpy(cpu_model, "IDT WinChip C6"); - break; - case 0x580: - strcpy(cpu_model, "IDT WinChip 2"); - break; - case 0x590: - strcpy(cpu_model, "IDT WinChip 3"); - break; - case 0x660: - strcpy(cpu_model, "VIA C3 Samuel"); - break; - case 0x670: - if (cpu_id & 0x8) - strcpy(cpu_model, "VIA C3 Ezra"); - else - strcpy(cpu_model, "VIA C3 Samuel 2"); - break; - case 0x680: - strcpy(cpu_model, "VIA C3 Ezra-T"); - break; - case 0x690: - strcpy(cpu_model, "VIA C3 Nehemiah"); - break; - case 0x6a0: - case 0x6d0: - strcpy(cpu_model, "VIA C7 Esther"); - break; - case 0x6f0: - strcpy(cpu_model, "VIA Nano"); - break; - default: - strcpy(cpu_model, "VIA/IDT Unknown"); - } - } else if (cpu_vendor_id == CPU_VENDOR_IBM) { - strcpy(cpu_model, "Blue Lightning CPU"); - } else if (cpu_vendor_id == CPU_VENDOR_NSC) { - switch (cpu_id & 0xff0) { - case 0x540: - strcpy(cpu_model, "Geode SC1100"); - cpu = CPU_GEODE1100; - break; - default: - strcpy(cpu_model, "Geode/NSC unknown"); - break; - } - } - - /* - * Replace cpu_model with cpu_brand minus leading spaces if - * we have one. - */ - brand = cpu_brand; - while (*brand == ' ') - ++brand; - if (*brand != '\0') - strcpy(cpu_model, brand); - - printf("%s (", cpu_model); - switch(cpu_class) { - case CPUCLASS_286: - printf("286"); - break; - case CPUCLASS_386: - printf("386"); - break; -#if defined(I486_CPU) - case CPUCLASS_486: - printf("486"); - break; -#endif -#if defined(I586_CPU) - case CPUCLASS_586: - if (tsc_freq != 0) { - hw_clockrate = (tsc_freq + 5000) / 1000000; - printf("%jd.%02d-MHz ", - (intmax_t)(tsc_freq + 4999) / 1000000, - (u_int)((tsc_freq + 4999) / 10000) % 100); - } - printf("586"); - break; -#endif -#if defined(I686_CPU) - case CPUCLASS_686: - if (tsc_freq != 0) { - hw_clockrate = (tsc_freq + 5000) / 1000000; - printf("%jd.%02d-MHz ", - (intmax_t)(tsc_freq + 4999) / 1000000, - (u_int)((tsc_freq + 4999) / 10000) % 100); - } - printf("686"); - break; -#endif - default: - printf("Unknown"); /* will panic below... */ - } - printf("-class CPU)\n"); - if(*cpu_vendor) - printf(" Origin=\"%s\"",cpu_vendor); - if(cpu_id) - printf(" Id=0x%x", cpu_id); - - if (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD || - cpu_vendor_id == CPU_VENDOR_TRANSMETA || - cpu_vendor_id == CPU_VENDOR_RISE || - cpu_vendor_id == CPU_VENDOR_CENTAUR || - cpu_vendor_id == CPU_VENDOR_NSC || - (cpu_vendor_id == CPU_VENDOR_CYRIX && - ((cpu_id & 0xf00) > 0x500))) { - printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); - printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); - printf(" Stepping=%u", cpu_id & CPUID_STEPPING); - if (cpu_vendor_id == CPU_VENDOR_CYRIX) - printf("\n DIR=0x%04x", cyrix_did); - /* - * AMD CPUID Specification - * http://support.amd.com/us/Embedded_TechDocs/25481.pdf - * - * Intel Processor Identification and CPUID Instruction - * http://www.intel.com/assets/pdf/appnote/241618.pdf - */ - if (cpu_high > 0) { - - /* - * Here we should probably set up flags indicating - * whether or not various features are available. - * The interesting ones are probably VME, PSE, PAE, - * and PGE. The code already assumes without bothering - * to check that all CPUs >= Pentium have a TSC and - * MSRs. - */ - printf("\n Features=0x%b", cpu_feature, - "\020" - "\001FPU" /* Integral FPU */ - "\002VME" /* Extended VM86 mode support */ - "\003DE" /* Debugging Extensions (CR4.DE) */ - "\004PSE" /* 4MByte page tables */ - "\005TSC" /* Timestamp counter */ - "\006MSR" /* Machine specific registers */ - "\007PAE" /* Physical address extension */ - "\010MCE" /* Machine Check support */ - "\011CX8" /* CMPEXCH8 instruction */ - "\012APIC" /* SMP local APIC */ - "\013oldMTRR" /* Previous implementation of MTRR */ - "\014SEP" /* Fast System Call */ - "\015MTRR" /* Memory Type Range Registers */ - "\016PGE" /* PG_G (global bit) support */ - "\017MCA" /* Machine Check Architecture */ - "\020CMOV" /* CMOV instruction */ - "\021PAT" /* Page attributes table */ - "\022PSE36" /* 36 bit address space support */ - "\023PN" /* Processor Serial number */ - "\024CLFLUSH" /* Has the CLFLUSH instruction */ - "\025" - "\026DTS" /* Debug Trace Store */ - "\027ACPI" /* ACPI support */ - "\030MMX" /* MMX instructions */ - "\031FXSR" /* FXSAVE/FXRSTOR */ - "\032SSE" /* Streaming SIMD Extensions */ - "\033SSE2" /* Streaming SIMD Extensions #2 */ - "\034SS" /* Self snoop */ - "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ - "\036TM" /* Thermal Monitor clock slowdown */ - "\037IA64" /* CPU can execute IA64 instructions */ - "\040PBE" /* Pending Break Enable */ - ); - - if (cpu_feature2 != 0) { - printf("\n Features2=0x%b", cpu_feature2, - "\020" - "\001SSE3" /* SSE3 */ - "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ - "\003DTES64" /* 64-bit Debug Trace */ - "\004MON" /* MONITOR/MWAIT Instructions */ - "\005DS_CPL" /* CPL Qualified Debug Store */ - "\006VMX" /* Virtual Machine Extensions */ - "\007SMX" /* Safer Mode Extensions */ - "\010EST" /* Enhanced SpeedStep */ - "\011TM2" /* Thermal Monitor 2 */ - "\012SSSE3" /* SSSE3 */ - "\013CNXT-ID" /* L1 context ID available */ - "\014" - "\015FMA" /* Fused Multiply Add */ - "\016CX16" /* CMPXCHG16B Instruction */ - "\017xTPR" /* Send Task Priority Messages*/ - "\020PDCM" /* Perf/Debug Capability MSR */ - "\021" - "\022PCID" /* Process-context Identifiers*/ - "\023DCA" /* Direct Cache Access */ - "\024SSE4.1" /* SSE 4.1 */ - "\025SSE4.2" /* SSE 4.2 */ - "\026x2APIC" /* xAPIC Extensions */ - "\027MOVBE" /* MOVBE Instruction */ - "\030POPCNT" /* POPCNT Instruction */ - "\031TSCDLT" /* TSC-Deadline Timer */ - "\032AESNI" /* AES Crypto */ - "\033XSAVE" /* XSAVE/XRSTOR States */ - "\034OSXSAVE" /* OS-Enabled State Management*/ - "\035AVX" /* Advanced Vector Extensions */ - "\036F16C" /* Half-precision conversions */ - "\037RDRAND" /* RDRAND Instruction */ - "\040HV" /* Hypervisor */ - ); - } - - if (amd_feature != 0) { - printf("\n AMD Features=0x%b", amd_feature, - "\020" /* in hex */ - "\001" /* Same */ - "\002" /* Same */ - "\003" /* Same */ - "\004" /* Same */ - "\005" /* Same */ - "\006" /* Same */ - "\007" /* Same */ - "\010" /* Same */ - "\011" /* Same */ - "\012" /* Same */ - "\013" /* Undefined */ - "\014SYSCALL" /* Have SYSCALL/SYSRET */ - "\015" /* Same */ - "\016" /* Same */ - "\017" /* Same */ - "\020" /* Same */ - "\021" /* Same */ - "\022" /* Same */ - "\023" /* Reserved, unknown */ - "\024MP" /* Multiprocessor Capable */ - "\025NX" /* Has EFER.NXE, NX */ - "\026" /* Undefined */ - "\027MMX+" /* AMD MMX Extensions */ - "\030" /* Same */ - "\031" /* Same */ - "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ - "\033Page1GB" /* 1-GB large page support */ - "\034RDTSCP" /* RDTSCP */ - "\035" /* Undefined */ - "\036LM" /* 64 bit long mode */ - "\0373DNow!+" /* AMD 3DNow! Extensions */ - "\0403DNow!" /* AMD 3DNow! */ - ); - } - - if (amd_feature2 != 0) { - printf("\n AMD Features2=0x%b", amd_feature2, - "\020" - "\001LAHF" /* LAHF/SAHF in long mode */ - "\002CMP" /* CMP legacy */ - "\003SVM" /* Secure Virtual Mode */ - "\004ExtAPIC" /* Extended APIC register */ - "\005CR8" /* CR8 in legacy mode */ - "\006ABM" /* LZCNT instruction */ - "\007SSE4A" /* SSE4A */ - "\010MAS" /* Misaligned SSE mode */ - "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ - "\012OSVW" /* OS visible workaround */ - "\013IBS" /* Instruction based sampling */ - "\014XOP" /* XOP extended instructions */ - "\015SKINIT" /* SKINIT/STGI */ - "\016WDT" /* Watchdog timer */ - "\017" - "\020LWP" /* Lightweight Profiling */ - "\021FMA4" /* 4-operand FMA instructions */ - "\022TCE" /* Translation Cache Extension */ - "\023" - "\024NodeId" /* NodeId MSR support */ - "\025" - "\026TBM" /* Trailing Bit Manipulation */ - "\027Topology" /* Topology Extensions */ - "\030PCXC" /* Core perf count */ - "\031PNXC" /* NB perf count */ - "\032" - "\033DBE" /* Data Breakpoint extension */ - "\034PTSC" /* Performance TSC */ - "\035PL2I" /* L2I perf count */ - "\036" - "\037" - "\040" - ); - } - - if (via_feature_rng != 0 || via_feature_xcrypt != 0) - print_via_padlock_info(); - - if ((cpu_feature & CPUID_HTT) && - cpu_vendor_id == CPU_VENDOR_AMD) - cpu_feature &= ~CPUID_HTT; - - /* - * If this CPU supports P-state invariant TSC then - * mention the capability. - */ - if (tsc_is_invariant) { - printf("\n TSC: P-state invariant"); - if (tsc_perf_stat) - printf(", performance statistics"); - } - - } - } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { - printf(" DIR=0x%04x", cyrix_did); - printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); - printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); -#ifndef CYRIX_CACHE_REALLY_WORKS - if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) - printf("\n CPU cache: write-through mode"); -#endif - } - - /* Avoid ugly blank lines: only print newline when we have to. */ - if (*cpu_vendor || cpu_id) - printf("\n"); - - if (!bootverbose) - return; - - if (cpu_vendor_id == CPU_VENDOR_AMD) - print_AMD_info(); - else if (cpu_vendor_id == CPU_VENDOR_INTEL) - print_INTEL_info(); - else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) - print_transmeta_info(); -} - -void -panicifcpuunsupported(void) -{ - -#if !defined(lint) -#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) -#error This kernel is not configured for one of the supported CPUs -#endif -#else /* lint */ -#endif /* lint */ - /* - * Now that we have told the user what they have, - * let them know if that machine type isn't configured. - */ - switch (cpu_class) { - case CPUCLASS_286: /* a 286 should not make it this far, anyway */ - case CPUCLASS_386: -#if !defined(I486_CPU) - case CPUCLASS_486: -#endif -#if !defined(I586_CPU) - case CPUCLASS_586: -#endif -#if !defined(I686_CPU) - case CPUCLASS_686: -#endif - panic("CPU class not configured"); - default: - break; - } -} - - -static volatile u_int trap_by_rdmsr; - -/* - * Special exception 6 handler. - * The rdmsr instruction generates invalid opcodes fault on 486-class - * Cyrix CPU. Stacked eip register points the rdmsr instruction in the - * function identblue() when this handler is called. Stacked eip should - * be advanced. - */ -inthand_t bluetrap6; -#ifdef __GNUCLIKE_ASM -__asm -(" \n\ - .text \n\ - .p2align 2,0x90 \n\ - .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ -" __XSTRING(CNAME(bluetrap6)) ": \n\ - ss \n\ - movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ - addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ - iret \n\ -"); -#endif - -/* - * Special exception 13 handler. - * Accessing non-existent MSR generates general protection fault. - */ -inthand_t bluetrap13; -#ifdef __GNUCLIKE_ASM -__asm -(" \n\ - .text \n\ - .p2align 2,0x90 \n\ - .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ -" __XSTRING(CNAME(bluetrap13)) ": \n\ - ss \n\ - movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ - popl %eax /* discard error code */ \n\ - addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ - iret \n\ -"); -#endif - -/* - * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not - * support cpuid instruction. This function should be called after - * loading interrupt descriptor table register. - * - * I don't like this method that handles fault, but I couldn't get - * information for any other methods. Does blue giant know? - */ -static int -identblue(void) -{ - - trap_by_rdmsr = 0; - - /* - * Cyrix 486-class CPU does not support rdmsr instruction. - * The rdmsr instruction generates invalid opcode fault, and exception - * will be trapped by bluetrap6() on Cyrix 486-class CPU. The - * bluetrap6() set the magic number to trap_by_rdmsr. - */ - setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, - GSEL(GCODE_SEL, SEL_KPL)); - - /* - * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. - * In this case, rdmsr generates general protection fault, and - * exception will be trapped by bluetrap13(). - */ - setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, - GSEL(GCODE_SEL, SEL_KPL)); - - rdmsr(0x1002); /* Cyrix CPU generates fault. */ - - if (trap_by_rdmsr == 0xa8c1d) - return IDENTBLUE_CYRIX486; - else if (trap_by_rdmsr == 0xa89c4) - return IDENTBLUE_CYRIXM2; - return IDENTBLUE_IBMCPU; -} - - -/* - * identifycyrix() set lower 16 bits of cyrix_did as follows: - * - * F E D C B A 9 8 7 6 5 4 3 2 1 0 - * +-------+-------+---------------+ - * | SID | RID | Device ID | - * | (DIR 1) | (DIR 0) | - * +-------+-------+---------------+ - */ -static void -identifycyrix(void) -{ - register_t saveintr; - int ccr2_test = 0, dir_test = 0; - u_char ccr2, ccr3; - - saveintr = intr_disable(); - - ccr2 = read_cyrix_reg(CCR2); - write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); - read_cyrix_reg(CCR2); - if (read_cyrix_reg(CCR2) != ccr2) - ccr2_test = 1; - write_cyrix_reg(CCR2, ccr2); - - ccr3 = read_cyrix_reg(CCR3); - write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); - read_cyrix_reg(CCR3); - if (read_cyrix_reg(CCR3) != ccr3) - dir_test = 1; /* CPU supports DIRs. */ - write_cyrix_reg(CCR3, ccr3); - - if (dir_test) { - /* Device ID registers are available. */ - cyrix_did = read_cyrix_reg(DIR1) << 8; - cyrix_did += read_cyrix_reg(DIR0); - } else if (ccr2_test) - cyrix_did = 0x0010; /* 486S A-step */ - else - cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ - - intr_restore(saveintr); -} - -/* Update TSC freq with the value indicated by the caller. */ -static void -tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) -{ - - /* If there was an error during the transition, don't do anything. */ - if (status != 0) - return; - - /* Total setting for this level gives the new frequency in MHz. */ - hw_clockrate = level->total_set.freq; -} - -static void -hook_tsc_freq(void *arg __unused) -{ - - if (tsc_is_invariant) - return; - - tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, - tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); -} - -SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); - -/* - * Final stage of CPU identification. -- Should I check TI? - */ -void -finishidentcpu(void) -{ - int isblue = 0; - u_char ccr3; - u_int regs[4]; - - cpu_vendor_id = find_cpu_vendor_id(); - - /* - * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID - * function number again if it is set from BIOS. It is necessary - * for probing correct CPU topology later. - * XXX This is only done on the BSP package. - */ - if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 && - ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) || - (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) { - uint64_t msr; - msr = rdmsr(MSR_IA32_MISC_ENABLE); - if ((msr & 0x400000ULL) != 0) { - wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); - do_cpuid(0, regs); - cpu_high = regs[0]; - } - } - - if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { - do_cpuid(5, regs); - cpu_mon_mwait_flags = regs[2]; - cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; - cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; - } - - if (cpu_high > 0 && - (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD || - cpu_vendor_id == CPU_VENDOR_TRANSMETA || - cpu_vendor_id == CPU_VENDOR_CENTAUR || - cpu_vendor_id == CPU_VENDOR_NSC)) { - do_cpuid(0x80000000, regs); - if (regs[0] >= 0x80000000) - cpu_exthigh = regs[0]; - } - - /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ - if (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD) { - if (cpu_exthigh >= 0x80000001) { - do_cpuid(0x80000001, regs); - amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); - amd_feature2 = regs[2]; - } - if (cpu_exthigh >= 0x80000007) { - do_cpuid(0x80000007, regs); - amd_pminfo = regs[3]; - } - if (cpu_exthigh >= 0x80000008) { - do_cpuid(0x80000008, regs); - cpu_procinfo2 = regs[2]; - } - } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) { - if (cpu_exthigh >= 0x80000001) { - do_cpuid(0x80000001, regs); - amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); - } - } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { - if (cpu == CPU_486) { - /* - * These conditions are equivalent to: - * - CPU does not support cpuid instruction. - * - Cyrix/IBM CPU is detected. - */ - isblue = identblue(); - if (isblue == IDENTBLUE_IBMCPU) { - strcpy(cpu_vendor, "IBM"); - cpu_vendor_id = CPU_VENDOR_IBM; - cpu = CPU_BLUE; - return; - } - } - switch (cpu_id & 0xf00) { - case 0x600: - /* - * Cyrix's datasheet does not describe DIRs. - * Therefor, I assume it does not have them - * and use the result of the cpuid instruction. - * XXX they seem to have it for now at least. -Peter - */ - identifycyrix(); - cpu = CPU_M2; - break; - default: - identifycyrix(); - /* - * This routine contains a trick. - * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. - */ - switch (cyrix_did & 0x00f0) { - case 0x00: - case 0xf0: - cpu = CPU_486DLC; - break; - case 0x10: - cpu = CPU_CY486DX; - break; - case 0x20: - if ((cyrix_did & 0x000f) < 8) - cpu = CPU_M1; - else - cpu = CPU_M1SC; - break; - case 0x30: - cpu = CPU_M1; - break; - case 0x40: - /* MediaGX CPU */ - cpu = CPU_M1SC; - break; - default: - /* M2 and later CPUs are treated as M2. */ - cpu = CPU_M2; - - /* - * enable cpuid instruction. - */ - ccr3 = read_cyrix_reg(CCR3); - write_cyrix_reg(CCR3, CCR3_MAPEN0); - write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); - write_cyrix_reg(CCR3, ccr3); - - do_cpuid(0, regs); - cpu_high = regs[0]; /* eax */ - do_cpuid(1, regs); - cpu_id = regs[0]; /* eax */ - cpu_feature = regs[3]; /* edx */ - break; - } - } - } else if (cpu == CPU_486 && *cpu_vendor == '\0') { - /* - * There are BlueLightning CPUs that do not change - * undefined flags by dividing 5 by 2. In this case, - * the CPU identification routine in locore.s leaves - * cpu_vendor null string and puts CPU_486 into the - * cpu. - */ - isblue = identblue(); - if (isblue == IDENTBLUE_IBMCPU) { - strcpy(cpu_vendor, "IBM"); - cpu_vendor_id = CPU_VENDOR_IBM; - cpu = CPU_BLUE; - return; - } - } -} - -static u_int -find_cpu_vendor_id(void) -{ - int i; - - for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) - if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) - return (cpu_vendors[i].vendor_id); - return (0); -} - -static void -print_AMD_assoc(int i) -{ - if (i == 255) - printf(", fully associative\n"); - else - printf(", %d-way associative\n", i); -} - -static void -print_AMD_info(void) -{ - quad_t amd_whcr; - - if (cpu_exthigh >= 0x80000005) { - u_int regs[4]; - - do_cpuid(0x80000005, regs); - printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff); - print_AMD_assoc(regs[1] >> 24); - printf("Instruction TLB: %d entries", regs[1] & 0xff); - print_AMD_assoc((regs[1] >> 8) & 0xff); - printf("L1 data cache: %d kbytes", regs[2] >> 24); - printf(", %d bytes/line", regs[2] & 0xff); - printf(", %d lines/tag", (regs[2] >> 8) & 0xff); - print_AMD_assoc((regs[2] >> 16) & 0xff); - printf("L1 instruction cache: %d kbytes", regs[3] >> 24); - printf(", %d bytes/line", regs[3] & 0xff); - printf(", %d lines/tag", (regs[3] >> 8) & 0xff); - print_AMD_assoc((regs[3] >> 16) & 0xff); - if (cpu_exthigh >= 0x80000006) { /* K6-III only */ - do_cpuid(0x80000006, regs); - printf("L2 internal cache: %d kbytes", regs[2] >> 16); - printf(", %d bytes/line", regs[2] & 0xff); - printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); - print_AMD_assoc((regs[2] >> 12) & 0x0f); - } - } - if (((cpu_id & 0xf00) == 0x500) - && (((cpu_id & 0x0f0) > 0x80) - || (((cpu_id & 0x0f0) == 0x80) - && (cpu_id & 0x00f) > 0x07))) { - /* K6-2(new core [Stepping 8-F]), K6-III or later */ - amd_whcr = rdmsr(0xc0000082); - if (!(amd_whcr & (0x3ff << 22))) { - printf("Write Allocate Disable\n"); - } else { - printf("Write Allocate Enable Limit: %dM bytes\n", - (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); - printf("Write Allocate 15-16M bytes: %s\n", - (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); - } - } else if (((cpu_id & 0xf00) == 0x500) - && ((cpu_id & 0x0f0) > 0x50)) { - /* K6, K6-2(old core) */ - amd_whcr = rdmsr(0xc0000082); - if (!(amd_whcr & (0x7f << 1))) { - printf("Write Allocate Disable\n"); - } else { - printf("Write Allocate Enable Limit: %dM bytes\n", - (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); - printf("Write Allocate 15-16M bytes: %s\n", - (amd_whcr & 0x0001) ? "Enable" : "Disable"); - printf("Hardware Write Allocate Control: %s\n", - (amd_whcr & 0x0100) ? "Enable" : "Disable"); - } - } - - /* - * Opteron Rev E shows a bug as in very rare occasions a read memory - * barrier is not performed as expected if it is followed by a - * non-atomic read-modify-write instruction. - * As long as that bug pops up very rarely (intensive machine usage - * on other operating systems generally generates one unexplainable - * crash any 2 months) and as long as a model specific fix would be - * impratical at this stage, print out a warning string if the broken - * model and family are identified. - */ - if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && - CPUID_TO_MODEL(cpu_id) <= 0x3f) - printf("WARNING: This architecture revision has known SMP " - "hardware bugs which may cause random instability\n"); -} - -static void -print_INTEL_info(void) -{ - u_int regs[4]; - u_int rounds, regnum; - u_int nwaycode, nway; - - if (cpu_high >= 2) { - rounds = 0; - do { - do_cpuid(0x2, regs); - if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) - break; /* we have a buggy CPU */ - - for (regnum = 0; regnum <= 3; ++regnum) { - if (regs[regnum] & (1<<31)) - continue; - if (regnum != 0) - print_INTEL_TLB(regs[regnum] & 0xff); - print_INTEL_TLB((regs[regnum] >> 8) & 0xff); - print_INTEL_TLB((regs[regnum] >> 16) & 0xff); - print_INTEL_TLB((regs[regnum] >> 24) & 0xff); - } - } while (--rounds > 0); - } - - if (cpu_exthigh >= 0x80000006) { - do_cpuid(0x80000006, regs); - nwaycode = (regs[2] >> 12) & 0x0f; - if (nwaycode >= 0x02 && nwaycode <= 0x08) - nway = 1 << (nwaycode / 2); - else - nway = 0; - printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", - (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); - } -} - -static void -print_INTEL_TLB(u_int data) -{ - switch (data) { - case 0x0: - case 0x40: - default: - break; - case 0x1: - printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); - break; - case 0x2: - printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); - break; - case 0x3: - printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); - break; - case 0x4: - printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); - break; - case 0x6: - printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); - break; - case 0x8: - printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); - break; - case 0xa: - printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); - break; - case 0xc: - printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); - break; - case 0x22: - printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x23: - printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x25: - printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x29: - printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x2c: - printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); - break; - case 0x30: - printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); - break; - case 0x39: - printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x3b: - printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x3c: - printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x41: - printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); - break; - case 0x42: - printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); - break; - case 0x43: - printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); - break; - case 0x44: - printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); - break; - case 0x45: - printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); - break; - case 0x46: - printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); - break; - case 0x47: - printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); - break; - case 0x50: - printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); - break; - case 0x51: - printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); - break; - case 0x52: - printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); - break; - case 0x5b: - printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); - break; - case 0x5c: - printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); - break; - case 0x5d: - printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); - break; - case 0x60: - printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x66: - printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x67: - printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x68: - printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x70: - printf("Trace cache: 12K-uops, 8-way set associative\n"); - break; - case 0x71: - printf("Trace cache: 16K-uops, 8-way set associative\n"); - break; - case 0x72: - printf("Trace cache: 32K-uops, 8-way set associative\n"); - break; - case 0x78: - printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); - break; - case 0x79: - printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x7a: - printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x7b: - printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x7c: - printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); - break; - case 0x7d: - printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); - break; - case 0x7f: - printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); - break; - case 0x82: - printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); - break; - case 0x83: - printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); - break; - case 0x84: - printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); - break; - case 0x85: - printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); - break; - case 0x86: - printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); - break; - case 0x87: - printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); - break; - case 0xb0: - printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); - break; - case 0xb3: - printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); - break; - } -} - -static void -print_transmeta_info(void) -{ - u_int regs[4], nreg = 0; - - do_cpuid(0x80860000, regs); - nreg = regs[0]; - if (nreg >= 0x80860001) { - do_cpuid(0x80860001, regs); - printf(" Processor revision %u.%u.%u.%u\n", - (regs[1] >> 24) & 0xff, - (regs[1] >> 16) & 0xff, - (regs[1] >> 8) & 0xff, - regs[1] & 0xff); - } - if (nreg >= 0x80860002) { - do_cpuid(0x80860002, regs); - printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", - (regs[1] >> 24) & 0xff, - (regs[1] >> 16) & 0xff, - (regs[1] >> 8) & 0xff, - regs[1] & 0xff, - regs[2]); - } - if (nreg >= 0x80860006) { - char info[65]; - do_cpuid(0x80860003, (u_int*) &info[0]); - do_cpuid(0x80860004, (u_int*) &info[16]); - do_cpuid(0x80860005, (u_int*) &info[32]); - do_cpuid(0x80860006, (u_int*) &info[48]); - info[64] = 0; - printf(" %s\n", info); - } -} - -static void -print_via_padlock_info(void) -{ - u_int regs[4]; - - do_cpuid(0xc0000001, regs); - printf("\n VIA Padlock Features=0x%b", regs[3], - "\020" - "\003RNG" /* RNG */ - "\007AES" /* ACE */ - "\011AES-CTR" /* ACE2 */ - "\013SHA1,SHA256" /* PHE */ - "\015RSA" /* PMM */ - ); -} Property changes on: head/sys/i386/i386/identcpu.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/i386/i386/initcpu.c =================================================================== --- head/sys/i386/i386/initcpu.c (revision 271097) +++ head/sys/i386/i386/initcpu.c (revision 271098) @@ -1,1056 +1,1057 @@ /*- * Copyright (c) KATO Takenori, 1997, 1998. * * All rights reserved. Unpublished rights reserved under the copyright * laws of Japan. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer as * the first lines of this file unmodified. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_cpu.h" #include #include #include #include #include #include #include #include #include #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) #define CPU_ENABLE_SSE #endif #ifdef I486_CPU static void init_5x86(void); static void init_bluelightning(void); static void init_486dlc(void); static void init_cy486dx(void); #ifdef CPU_I486_ON_386 static void init_i486_on_386(void); #endif static void init_6x86(void); #endif /* I486_CPU */ #ifdef I686_CPU static void init_6x86MX(void); static void init_ppro(void); static void init_mendocino(void); #endif static int hw_instruction_sse; SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); /* * -1: automatic (default) * 0: keep enable CLFLUSH * 1: force disable CLFLUSH */ static int hw_clflush_disable = -1; int cpu; /* Are we 386, 386sx, 486, etc? */ u_int cpu_feature; /* Feature flags */ u_int cpu_feature2; /* Feature flags */ u_int amd_feature; /* AMD feature flags */ u_int amd_feature2; /* AMD feature flags */ u_int amd_pminfo; /* AMD advanced power management info */ u_int via_feature_rng; /* VIA RNG features */ u_int via_feature_xcrypt; /* VIA ACE features */ u_int cpu_high; /* Highest arg to CPUID */ u_int cpu_exthigh; /* Highest arg to extended CPUID */ u_int cpu_id; /* Stepping ID */ u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ u_int cpu_procinfo2; /* Multicore info */ char cpu_vendor[20]; /* CPU Origin code */ u_int cpu_vendor_id; /* CPU vendor ID */ #ifdef CPU_ENABLE_SSE u_int cpu_fxsr; /* SSE enabled */ u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ #endif u_int cpu_clflush_line_size = 32; +u_int cpu_stdext_feature; u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ u_int cyrix_did; /* Device ID of Cyrix CPU */ SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, &via_feature_rng, 0, "VIA RNG feature available in CPU"); SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU"); #ifdef I486_CPU /* * IBM Blue Lightning */ static void init_bluelightning(void) { register_t saveintr; #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) need_post_dma_flush = 1; #endif saveintr = intr_disable(); load_cr0(rcr0() | CR0_CD | CR0_NW); invd(); #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ #else wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ #endif /* Enables 13MB and 0-640KB cache. */ wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); #ifdef CPU_BLUELIGHTNING_3X wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ #else wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ #endif /* Enable caching in CR0. */ load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ invd(); intr_restore(saveintr); } /* * Cyrix 486SLC/DLC/SR/DR series */ static void init_486dlc(void) { register_t saveintr; u_char ccr0; saveintr = intr_disable(); invd(); ccr0 = read_cyrix_reg(CCR0); #ifndef CYRIX_CACHE_WORKS ccr0 |= CCR0_NC1 | CCR0_BARB; write_cyrix_reg(CCR0, ccr0); invd(); #else ccr0 &= ~CCR0_NC0; #ifndef CYRIX_CACHE_REALLY_WORKS ccr0 |= CCR0_NC1 | CCR0_BARB; #else ccr0 |= CCR0_NC1; #endif #ifdef CPU_DIRECT_MAPPED_CACHE ccr0 |= CCR0_CO; /* Direct mapped mode. */ #endif write_cyrix_reg(CCR0, ccr0); /* Clear non-cacheable region. */ write_cyrix_reg(NCR1+2, NCR_SIZE_0K); write_cyrix_reg(NCR2+2, NCR_SIZE_0K); write_cyrix_reg(NCR3+2, NCR_SIZE_0K); write_cyrix_reg(NCR4+2, NCR_SIZE_0K); write_cyrix_reg(0, 0); /* dummy write */ /* Enable caching in CR0. */ load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ invd(); #endif /* !CYRIX_CACHE_WORKS */ intr_restore(saveintr); } /* * Cyrix 486S/DX series */ static void init_cy486dx(void) { register_t saveintr; u_char ccr2; saveintr = intr_disable(); invd(); ccr2 = read_cyrix_reg(CCR2); #ifdef CPU_SUSP_HLT ccr2 |= CCR2_SUSP_HLT; #endif #ifdef PC98 /* Enables WB cache interface pin and Lock NW bit in CR0. */ ccr2 |= CCR2_WB | CCR2_LOCK_NW; /* Unlock NW bit in CR0. */ write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW); load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ #endif write_cyrix_reg(CCR2, ccr2); intr_restore(saveintr); } /* * Cyrix 5x86 */ static void init_5x86(void) { register_t saveintr; u_char ccr2, ccr3, ccr4, pcr0; saveintr = intr_disable(); load_cr0(rcr0() | CR0_CD | CR0_NW); wbinvd(); (void)read_cyrix_reg(CCR3); /* dummy */ /* Initialize CCR2. */ ccr2 = read_cyrix_reg(CCR2); ccr2 |= CCR2_WB; #ifdef CPU_SUSP_HLT ccr2 |= CCR2_SUSP_HLT; #else ccr2 &= ~CCR2_SUSP_HLT; #endif ccr2 |= CCR2_WT1; write_cyrix_reg(CCR2, ccr2); /* Initialize CCR4. */ ccr3 = read_cyrix_reg(CCR3); write_cyrix_reg(CCR3, CCR3_MAPEN0); ccr4 = read_cyrix_reg(CCR4); ccr4 |= CCR4_DTE; ccr4 |= CCR4_MEM; #ifdef CPU_FASTER_5X86_FPU ccr4 |= CCR4_FASTFPE; #else ccr4 &= ~CCR4_FASTFPE; #endif ccr4 &= ~CCR4_IOMASK; /******************************************************************** * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time * should be 0 for errata fix. ********************************************************************/ #ifdef CPU_IORT ccr4 |= CPU_IORT & CCR4_IOMASK; #endif write_cyrix_reg(CCR4, ccr4); /* Initialize PCR0. */ /**************************************************************** * WARNING: RSTK_EN and LOOP_EN could make your system unstable. * BTB_EN might make your system unstable. ****************************************************************/ pcr0 = read_cyrix_reg(PCR0); #ifdef CPU_RSTK_EN pcr0 |= PCR0_RSTK; #else pcr0 &= ~PCR0_RSTK; #endif #ifdef CPU_BTB_EN pcr0 |= PCR0_BTB; #else pcr0 &= ~PCR0_BTB; #endif #ifdef CPU_LOOP_EN pcr0 |= PCR0_LOOP; #else pcr0 &= ~PCR0_LOOP; #endif /**************************************************************** * WARNING: if you use a memory mapped I/O device, don't use * DISABLE_5X86_LSSER option, which may reorder memory mapped * I/O access. * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. ****************************************************************/ #ifdef CPU_DISABLE_5X86_LSSER pcr0 &= ~PCR0_LSSER; #else pcr0 |= PCR0_LSSER; #endif write_cyrix_reg(PCR0, pcr0); /* Restore CCR3. */ write_cyrix_reg(CCR3, ccr3); (void)read_cyrix_reg(0x80); /* dummy */ /* Unlock NW bit in CR0. */ write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ /* Lock NW bit in CR0. */ write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); intr_restore(saveintr); } #ifdef CPU_I486_ON_386 /* * There are i486 based upgrade products for i386 machines. * In this case, BIOS doesn't enable CPU cache. */ static void init_i486_on_386(void) { register_t saveintr; #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) need_post_dma_flush = 1; #endif saveintr = intr_disable(); load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ intr_restore(saveintr); } #endif /* * Cyrix 6x86 * * XXX - What should I do here? Please let me know. */ static void init_6x86(void) { register_t saveintr; u_char ccr3, ccr4; saveintr = intr_disable(); load_cr0(rcr0() | CR0_CD | CR0_NW); wbinvd(); /* Initialize CCR0. */ write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); /* Initialize CCR1. */ #ifdef CPU_CYRIX_NO_LOCK write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); #else write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); #endif /* Initialize CCR2. */ #ifdef CPU_SUSP_HLT write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); #else write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); #endif ccr3 = read_cyrix_reg(CCR3); write_cyrix_reg(CCR3, CCR3_MAPEN0); /* Initialize CCR4. */ ccr4 = read_cyrix_reg(CCR4); ccr4 |= CCR4_DTE; ccr4 &= ~CCR4_IOMASK; #ifdef CPU_IORT write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); #else write_cyrix_reg(CCR4, ccr4 | 7); #endif /* Initialize CCR5. */ #ifdef CPU_WT_ALLOC write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); #endif /* Restore CCR3. */ write_cyrix_reg(CCR3, ccr3); /* Unlock NW bit in CR0. */ write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); /* * Earlier revision of the 6x86 CPU could crash the system if * L1 cache is in write-back mode. */ if ((cyrix_did & 0xff00) > 0x1600) load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ else { /* Revision 2.6 and lower. */ #ifdef CYRIX_CACHE_REALLY_WORKS load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ #else load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ #endif } /* Lock NW bit in CR0. */ write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); intr_restore(saveintr); } #endif /* I486_CPU */ #ifdef I586_CPU /* * Rise mP6 */ static void init_rise(void) { /* * The CMPXCHG8B instruction is always available but hidden. */ cpu_feature |= CPUID_CX8; } /* * IDT WinChip C6/2/2A/2B/3 * * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf */ static void init_winchip(void) { u_int regs[4]; uint64_t fcr; fcr = rdmsr(0x0107); /* * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC. */ fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16); fcr &= ~(1ULL << 11); /* * Additioanlly, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. */ if (CPUID_TO_MODEL(cpu_id) >= 8) fcr |= (1 << 12) | (1 << 19) | (1 << 20); wrmsr(0x0107, fcr); do_cpuid(1, regs); cpu_feature = regs[3]; } #endif #ifdef I686_CPU /* * Cyrix 6x86MX (code-named M2) * * XXX - What should I do here? Please let me know. */ static void init_6x86MX(void) { register_t saveintr; u_char ccr3, ccr4; saveintr = intr_disable(); load_cr0(rcr0() | CR0_CD | CR0_NW); wbinvd(); /* Initialize CCR0. */ write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); /* Initialize CCR1. */ #ifdef CPU_CYRIX_NO_LOCK write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); #else write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); #endif /* Initialize CCR2. */ #ifdef CPU_SUSP_HLT write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); #else write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); #endif ccr3 = read_cyrix_reg(CCR3); write_cyrix_reg(CCR3, CCR3_MAPEN0); /* Initialize CCR4. */ ccr4 = read_cyrix_reg(CCR4); ccr4 &= ~CCR4_IOMASK; #ifdef CPU_IORT write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); #else write_cyrix_reg(CCR4, ccr4 | 7); #endif /* Initialize CCR5. */ #ifdef CPU_WT_ALLOC write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); #endif /* Restore CCR3. */ write_cyrix_reg(CCR3, ccr3); /* Unlock NW bit in CR0. */ write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ /* Lock NW bit in CR0. */ write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); intr_restore(saveintr); } static void init_ppro(void) { u_int64_t apicbase; /* * Local APIC should be disabled if it is not going to be used. */ apicbase = rdmsr(MSR_APICBASE); apicbase &= ~APICBASE_ENABLED; wrmsr(MSR_APICBASE, apicbase); } /* * Initialize BBL_CR_CTL3 (Control register 3: used to configure the * L2 cache). */ static void init_mendocino(void) { #ifdef CPU_PPRO2CELERON register_t saveintr; u_int64_t bbl_cr_ctl3; saveintr = intr_disable(); load_cr0(rcr0() | CR0_CD | CR0_NW); wbinvd(); bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); /* If the L2 cache is configured, do nothing. */ if (!(bbl_cr_ctl3 & 1)) { bbl_cr_ctl3 = 0x134052bLL; /* Set L2 Cache Latency (Default: 5). */ #ifdef CPU_CELERON_L2_LATENCY #if CPU_L2_LATENCY > 15 #error invalid CPU_L2_LATENCY. #endif bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; #else bbl_cr_ctl3 |= 5 << 1; #endif wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); } load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); intr_restore(saveintr); #endif /* CPU_PPRO2CELERON */ } /* * Initialize special VIA features */ static void init_via(void) { u_int regs[4], val; uint64_t fcr; /* * Explicitly enable CX8 and PGE on C3. * * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf */ if (CPUID_TO_MODEL(cpu_id) <= 9) fcr = (1 << 1) | (1 << 7); else fcr = 0; /* * Check extended CPUID for PadLock features. * * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf */ do_cpuid(0xc0000000, regs); if (regs[0] >= 0xc0000001) { do_cpuid(0xc0000001, regs); val = regs[3]; } else val = 0; /* Enable RNG if present. */ if ((val & VIA_CPUID_HAS_RNG) != 0) { via_feature_rng = VIA_HAS_RNG; wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); } /* Enable PadLock if present. */ if ((val & VIA_CPUID_HAS_ACE) != 0) via_feature_xcrypt |= VIA_HAS_AES; if ((val & VIA_CPUID_HAS_ACE2) != 0) via_feature_xcrypt |= VIA_HAS_AESCTR; if ((val & VIA_CPUID_HAS_PHE) != 0) via_feature_xcrypt |= VIA_HAS_SHA; if ((val & VIA_CPUID_HAS_PMM) != 0) via_feature_xcrypt |= VIA_HAS_MM; if (via_feature_xcrypt != 0) fcr |= 1 << 28; wrmsr(0x1107, rdmsr(0x1107) | fcr); } #endif /* I686_CPU */ #if defined(I586_CPU) || defined(I686_CPU) static void init_transmeta(void) { u_int regs[0]; /* Expose all hidden features. */ wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); do_cpuid(1, regs); cpu_feature = regs[3]; } #endif /* * Initialize CR4 (Control register 4) to enable SSE instructions. */ void enable_sse(void) { #if defined(CPU_ENABLE_SSE) if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { load_cr4(rcr4() | CR4_FXSR | CR4_XMM); cpu_fxsr = hw_instruction_sse = 1; } #endif } extern int elf32_nxstack; void initializecpu(void) { switch (cpu) { #ifdef I486_CPU case CPU_BLUE: init_bluelightning(); break; case CPU_486DLC: init_486dlc(); break; case CPU_CY486DX: init_cy486dx(); break; case CPU_M1SC: init_5x86(); break; #ifdef CPU_I486_ON_386 case CPU_486: init_i486_on_386(); break; #endif case CPU_M1: init_6x86(); break; #endif /* I486_CPU */ #ifdef I586_CPU case CPU_586: switch (cpu_vendor_id) { case CPU_VENDOR_CENTAUR: init_winchip(); break; case CPU_VENDOR_TRANSMETA: init_transmeta(); break; case CPU_VENDOR_RISE: init_rise(); break; } break; #endif #ifdef I686_CPU case CPU_M2: init_6x86MX(); break; case CPU_686: switch (cpu_vendor_id) { case CPU_VENDOR_INTEL: switch (cpu_id & 0xff0) { case 0x610: init_ppro(); break; case 0x660: init_mendocino(); break; } break; #ifdef CPU_ATHLON_SSE_HACK case CPU_VENDOR_AMD: /* * Sometimes the BIOS doesn't enable SSE instructions. * According to AMD document 20734, the mobile * Duron, the (mobile) Athlon 4 and the Athlon MP * support SSE. These correspond to cpu_id 0x66X * or 0x67X. */ if ((cpu_feature & CPUID_XMM) == 0 && ((cpu_id & ~0xf) == 0x660 || (cpu_id & ~0xf) == 0x670 || (cpu_id & ~0xf) == 0x680)) { u_int regs[4]; wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); do_cpuid(1, regs); cpu_feature = regs[3]; } break; #endif case CPU_VENDOR_CENTAUR: init_via(); break; case CPU_VENDOR_TRANSMETA: init_transmeta(); break; } #ifdef PAE if ((amd_feature & AMDID_NX) != 0) { uint64_t msr; msr = rdmsr(MSR_EFER) | EFER_NXE; wrmsr(MSR_EFER, msr); pg_nx = PG_NX; elf32_nxstack = 1; } #endif break; #endif default: break; } enable_sse(); /* * CPUID with %eax = 1, %ebx returns * Bits 15-8: CLFLUSH line size * (Value * 8 = cache line size in bytes) */ if ((cpu_feature & CPUID_CLFSH) != 0) cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; /* * XXXKIB: (temporary) hack to work around traps generated * when CLFLUSHing APIC register window under virtualization * environments. These environments tend to disable the * CPUID_SS feature even though the native CPU supports it. */ TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) cpu_feature &= ~CPUID_CLFSH; /* * Allow to disable CLFLUSH feature manually by * hw.clflush_disable tunable. */ if (hw_clflush_disable == 1) cpu_feature &= ~CPUID_CLFSH; #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) /* * OS should flush L1 cache by itself because no PC-98 supports * non-Intel CPUs. Use wbinvd instruction before DMA transfer * when need_pre_dma_flush = 1, use invd instruction after DMA * transfer when need_post_dma_flush = 1. If your CPU upgrade * product supports hardware cache control, you can add the * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. * This option eliminates unneeded cache flush instruction(s). */ if (cpu_vendor_id == CPU_VENDOR_CYRIX) { switch (cpu) { #ifdef I486_CPU case CPU_486DLC: need_post_dma_flush = 1; break; case CPU_M1SC: need_pre_dma_flush = 1; break; case CPU_CY486DX: need_pre_dma_flush = 1; #ifdef CPU_I486_ON_386 need_post_dma_flush = 1; #endif break; #endif default: break; } } else if (cpu_vendor_id == CPU_VENDOR_AMD) { switch (cpu_id & 0xFF0) { case 0x470: /* Enhanced Am486DX2 WB */ case 0x490: /* Enhanced Am486DX4 WB */ case 0x4F0: /* Am5x86 WB */ need_pre_dma_flush = 1; break; } } else if (cpu_vendor_id == CPU_VENDOR_IBM) { need_post_dma_flush = 1; } else { #ifdef CPU_I486_ON_386 need_pre_dma_flush = 1; #endif } #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */ } #if defined(I586_CPU) && defined(CPU_WT_ALLOC) /* * Enable write allocate feature of AMD processors. * Following two functions require the Maxmem variable being set. */ void enable_K5_wt_alloc(void) { u_int64_t msr; register_t saveintr; /* * Write allocate is supported only on models 1, 2, and 3, with * a stepping of 4 or greater. */ if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { saveintr = intr_disable(); msr = rdmsr(0x83); /* HWCR */ wrmsr(0x83, msr & !(0x10)); /* * We have to tell the chip where the top of memory is, * since video cards could have frame bufferes there, * memory-mapped I/O could be there, etc. */ if(Maxmem > 0) msr = Maxmem / 16; else msr = 0; msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; #ifdef PC98 if (!(inb(0x43b) & 4)) { wrmsr(0x86, 0x0ff00f0); msr |= AMD_WT_ALLOC_PRE; } #else /* * There is no way to know wheter 15-16M hole exists or not. * Therefore, we disable write allocate for this range. */ wrmsr(0x86, 0x0ff00f0); msr |= AMD_WT_ALLOC_PRE; #endif wrmsr(0x85, msr); msr=rdmsr(0x83); wrmsr(0x83, msr|0x10); /* enable write allocate */ intr_restore(saveintr); } } void enable_K6_wt_alloc(void) { quad_t size; u_int64_t whcr; register_t saveintr; saveintr = intr_disable(); wbinvd(); #ifdef CPU_DISABLE_CACHE /* * Certain K6-2 box becomes unstable when write allocation is * enabled. */ /* * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. * All other bits in TR12 have no effect on the processer's operation. * The I/O Trap Restart function (bit 9 of TR12) is always enabled * on the AMD-K6. */ wrmsr(0x0000000e, (u_int64_t)0x0008); #endif /* Don't assume that memory size is aligned with 4M. */ if (Maxmem > 0) size = ((Maxmem >> 8) + 3) >> 2; else size = 0; /* Limit is 508M bytes. */ if (size > 0x7f) size = 0x7f; whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); #if defined(PC98) || defined(NO_MEMORY_HOLE) if (whcr & (0x7fLL << 1)) { #ifdef PC98 /* * If bit 2 of port 0x43b is 0, disable wrte allocate for the * 15-16M range. */ if (!(inb(0x43b) & 4)) whcr &= ~0x0001LL; else #endif whcr |= 0x0001LL; } #else /* * There is no way to know wheter 15-16M hole exists or not. * Therefore, we disable write allocate for this range. */ whcr &= ~0x0001LL; #endif wrmsr(0x0c0000082, whcr); intr_restore(saveintr); } void enable_K6_2_wt_alloc(void) { quad_t size; u_int64_t whcr; register_t saveintr; saveintr = intr_disable(); wbinvd(); #ifdef CPU_DISABLE_CACHE /* * Certain K6-2 box becomes unstable when write allocation is * enabled. */ /* * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. * All other bits in TR12 have no effect on the processer's operation. * The I/O Trap Restart function (bit 9 of TR12) is always enabled * on the AMD-K6. */ wrmsr(0x0000000e, (u_int64_t)0x0008); #endif /* Don't assume that memory size is aligned with 4M. */ if (Maxmem > 0) size = ((Maxmem >> 8) + 3) >> 2; else size = 0; /* Limit is 4092M bytes. */ if (size > 0x3fff) size = 0x3ff; whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); #if defined(PC98) || defined(NO_MEMORY_HOLE) if (whcr & (0x3ffLL << 22)) { #ifdef PC98 /* * If bit 2 of port 0x43b is 0, disable wrte allocate for the * 15-16M range. */ if (!(inb(0x43b) & 4)) whcr &= ~(1LL << 16); else #endif whcr |= 1LL << 16; } #else /* * There is no way to know wheter 15-16M hole exists or not. * Therefore, we disable write allocate for this range. */ whcr &= ~(1LL << 16); #endif wrmsr(0x0c0000082, whcr); intr_restore(saveintr); } #endif /* I585_CPU && CPU_WT_ALLOC */ #include "opt_ddb.h" #ifdef DDB #include DB_SHOW_COMMAND(cyrixreg, cyrixreg) { register_t saveintr; u_int cr0; u_char ccr1, ccr2, ccr3; u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; cr0 = rcr0(); if (cpu_vendor_id == CPU_VENDOR_CYRIX) { saveintr = intr_disable(); if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { ccr0 = read_cyrix_reg(CCR0); } ccr1 = read_cyrix_reg(CCR1); ccr2 = read_cyrix_reg(CCR2); ccr3 = read_cyrix_reg(CCR3); if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { write_cyrix_reg(CCR3, CCR3_MAPEN0); ccr4 = read_cyrix_reg(CCR4); if ((cpu == CPU_M1) || (cpu == CPU_M2)) ccr5 = read_cyrix_reg(CCR5); else pcr0 = read_cyrix_reg(PCR0); write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ } intr_restore(saveintr); if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) printf("CCR0=%x, ", (u_int)ccr0); printf("CCR1=%x, CCR2=%x, CCR3=%x", (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { printf(", CCR4=%x, ", (u_int)ccr4); if (cpu == CPU_M1SC) printf("PCR0=%x\n", pcr0); else printf("CCR5=%x\n", ccr5); } } printf("CR0=%x\n", cr0); } #endif /* DDB */ Index: head/sys/i386/include/md_var.h =================================================================== --- head/sys/i386/include/md_var.h (revision 271097) +++ head/sys/i386/include/md_var.h (revision 271098) @@ -1,121 +1,122 @@ /*- * Copyright (c) 1995 Bruce D. Evans. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the author nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_MD_VAR_H_ #define _MACHINE_MD_VAR_H_ /* * Miscellaneous machine-dependent declarations. */ extern long Maxmem; extern u_int basemem; /* PA of original top of base memory */ extern int busdma_swi_pending; extern u_int cpu_exthigh; extern u_int cpu_feature; extern u_int cpu_feature2; extern u_int amd_feature; extern u_int amd_feature2; extern u_int amd_pminfo; extern u_int via_feature_rng; extern u_int via_feature_xcrypt; extern u_int cpu_clflush_line_size; +extern u_int cpu_stdext_feature; extern u_int cpu_fxsr; extern u_int cpu_high; extern u_int cpu_id; extern u_int cpu_mxcsr_mask; extern u_int cpu_procinfo; extern u_int cpu_procinfo2; extern char cpu_vendor[]; extern u_int cpu_vendor_id; extern u_int cpu_mon_mwait_flags; extern u_int cpu_mon_min_size; extern u_int cpu_mon_max_size; extern u_int cyrix_did; #if defined(I586_CPU) && !defined(NO_F00F_HACK) extern int has_f00f_bug; #endif extern char kstack[]; extern char sigcode[]; extern int szsigcode; #ifdef COMPAT_FREEBSD4 extern int szfreebsd4_sigcode; #endif #ifdef COMPAT_43 extern int szosigcode; #endif extern uint32_t *vm_page_dump; extern int vm_page_dump_size; extern int workaround_erratum383; typedef void alias_for_inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); struct thread; struct reg; struct fpreg; struct dbreg; struct dumperinfo; void bcopyb(const void *from, void *to, size_t len); void busdma_swi(void); void cpu_setregs(void); void cpu_switch_load_gs(void) __asm(__STRING(cpu_switch_load_gs)); void doreti_iret(void) __asm(__STRING(doreti_iret)); void doreti_iret_fault(void) __asm(__STRING(doreti_iret_fault)); void doreti_popl_ds(void) __asm(__STRING(doreti_popl_ds)); void doreti_popl_ds_fault(void) __asm(__STRING(doreti_popl_ds_fault)); void doreti_popl_es(void) __asm(__STRING(doreti_popl_es)); void doreti_popl_es_fault(void) __asm(__STRING(doreti_popl_es_fault)); void doreti_popl_fs(void) __asm(__STRING(doreti_popl_fs)); void doreti_popl_fs_fault(void) __asm(__STRING(doreti_popl_fs_fault)); void dump_add_page(vm_paddr_t); void dump_drop_page(vm_paddr_t); void finishidentcpu(void); #if defined(I586_CPU) && defined(CPU_WT_ALLOC) void enable_K5_wt_alloc(void); void enable_K6_wt_alloc(void); void enable_K6_2_wt_alloc(void); #endif void enable_sse(void); void fillw(int /*u_short*/ pat, void *base, size_t cnt); void initializecpu(void); void i686_pagezero(void *addr); void sse2_pagezero(void *addr); void init_AMD_Elan_sc520(void); int is_physical_memory(vm_paddr_t addr); int isa_nmi(int cd); vm_paddr_t kvtop(void *addr); void panicifcpuunsupported(void); void printcpuinfo(void); void setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int selec); int user_dbreg_trap(void); void minidumpsys(struct dumperinfo *); #endif /* !_MACHINE_MD_VAR_H_ */ Index: head/sys/x86/x86/identcpu.c =================================================================== --- head/sys/x86/x86/identcpu.c (nonexistent) +++ head/sys/x86/x86/identcpu.c (revision 271098) @@ -0,0 +1,1989 @@ +/*- + * Copyright (c) 1992 Terrence R. Lambert. + * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. + * Copyright (c) 1997 KATO Takenori. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_cpu.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef __i386__ +#define IDENTBLUE_CYRIX486 0 +#define IDENTBLUE_IBMCPU 1 +#define IDENTBLUE_CYRIXM2 2 + +static void identifycyrix(void); +static void print_transmeta_info(void); +#endif +static u_int find_cpu_vendor_id(void); +static void print_AMD_info(void); +static void print_INTEL_info(void); +static void print_INTEL_TLB(u_int data); +static void print_via_padlock_info(void); +static void print_vmx_info(void); + +int cpu_class; +char machine[] = MACHINE; + +#ifdef __amd64__ +#ifdef SCTL_MASK32 +extern int adaptive_machine_arch; +#endif + +static int +sysctl_hw_machine(SYSCTL_HANDLER_ARGS) +{ +#ifdef SCTL_MASK32 + static const char machine32[] = "i386"; +#endif + int error; + +#ifdef SCTL_MASK32 + if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) + error = SYSCTL_OUT(req, machine32, sizeof(machine32)); + else +#endif + error = SYSCTL_OUT(req, machine, sizeof(machine)); + return (error); + +} +SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, + NULL, 0, sysctl_hw_machine, "A", "Machine class"); +#else +SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, + machine, 0, "Machine class"); +#endif + +static char cpu_model[128]; +SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, + cpu_model, 0, "Machine model"); + +static int hw_clockrate; +SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, + &hw_clockrate, 0, "CPU instruction clock rate"); + +static eventhandler_tag tsc_post_tag; + +static char cpu_brand[48]; + +#ifdef __i386__ +#define MAX_BRAND_INDEX 8 + +static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { + NULL, /* No brand */ + "Intel Celeron", + "Intel Pentium III", + "Intel Pentium III Xeon", + NULL, + NULL, + NULL, + NULL, + "Intel Pentium 4" +}; +#endif + +static struct { + char *cpu_name; + int cpu_class; +} cpus[] = { +#ifdef __i386__ + { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ + { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ + { "i386DX", CPUCLASS_386 }, /* CPU_386 */ + { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ + { "i486DX", CPUCLASS_486 }, /* CPU_486 */ + { "Pentium", CPUCLASS_586 }, /* CPU_586 */ + { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ + { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ + { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ + { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ + { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ + { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ + { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ + { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ + { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ + { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ + { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ +#else + { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ + { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ +#endif +}; + +static struct { + char *vendor; + u_int vendor_id; +} cpu_vendors[] = { + { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ + { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ + { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ +#ifdef __i386__ + { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ + { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ + { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ + { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ + { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ + { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ + { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ +#if 0 + /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ + { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, +#endif +#endif +}; + +void +printcpuinfo(void) +{ + u_int regs[4], i; + char *brand; + + cpu_class = cpus[cpu].cpu_class; + printf("CPU: "); + strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); + + /* Check for extended CPUID information and a processor name. */ + if (cpu_exthigh >= 0x80000004) { + brand = cpu_brand; + for (i = 0x80000002; i < 0x80000005; i++) { + do_cpuid(i, regs); + memcpy(brand, regs, sizeof(regs)); + brand += sizeof(regs); + } + } + + switch (cpu_vendor_id) { + case CPU_VENDOR_INTEL: +#ifdef __i386__ + if ((cpu_id & 0xf00) > 0x300) { + u_int brand_index; + + cpu_model[0] = '\0'; + + switch (cpu_id & 0x3000) { + case 0x1000: + strcpy(cpu_model, "Overdrive "); + break; + case 0x2000: + strcpy(cpu_model, "Dual "); + break; + } + + switch (cpu_id & 0xf00) { + case 0x400: + strcat(cpu_model, "i486 "); + /* Check the particular flavor of 486 */ + switch (cpu_id & 0xf0) { + case 0x00: + case 0x10: + strcat(cpu_model, "DX"); + break; + case 0x20: + strcat(cpu_model, "SX"); + break; + case 0x30: + strcat(cpu_model, "DX2"); + break; + case 0x40: + strcat(cpu_model, "SL"); + break; + case 0x50: + strcat(cpu_model, "SX2"); + break; + case 0x70: + strcat(cpu_model, + "DX2 Write-Back Enhanced"); + break; + case 0x80: + strcat(cpu_model, "DX4"); + break; + } + break; + case 0x500: + /* Check the particular flavor of 586 */ + strcat(cpu_model, "Pentium"); + switch (cpu_id & 0xf0) { + case 0x00: + strcat(cpu_model, " A-step"); + break; + case 0x10: + strcat(cpu_model, "/P5"); + break; + case 0x20: + strcat(cpu_model, "/P54C"); + break; + case 0x30: + strcat(cpu_model, "/P24T"); + break; + case 0x40: + strcat(cpu_model, "/P55C"); + break; + case 0x70: + strcat(cpu_model, "/P54C"); + break; + case 0x80: + strcat(cpu_model, "/P55C (quarter-micron)"); + break; + default: + /* nothing */ + break; + } +#if defined(I586_CPU) && !defined(NO_F00F_HACK) + /* + * XXX - If/when Intel fixes the bug, this + * should also check the version of the + * CPU, not just that it's a Pentium. + */ + has_f00f_bug = 1; +#endif + break; + case 0x600: + /* Check the particular flavor of 686 */ + switch (cpu_id & 0xf0) { + case 0x00: + strcat(cpu_model, "Pentium Pro A-step"); + break; + case 0x10: + strcat(cpu_model, "Pentium Pro"); + break; + case 0x30: + case 0x50: + case 0x60: + strcat(cpu_model, + "Pentium II/Pentium II Xeon/Celeron"); + cpu = CPU_PII; + break; + case 0x70: + case 0x80: + case 0xa0: + case 0xb0: + strcat(cpu_model, + "Pentium III/Pentium III Xeon/Celeron"); + cpu = CPU_PIII; + break; + default: + strcat(cpu_model, "Unknown 80686"); + break; + } + break; + case 0xf00: + strcat(cpu_model, "Pentium 4"); + cpu = CPU_P4; + break; + default: + strcat(cpu_model, "unknown"); + break; + } + + /* + * If we didn't get a brand name from the extended + * CPUID, try to look it up in the brand table. + */ + if (cpu_high > 0 && *cpu_brand == '\0') { + brand_index = cpu_procinfo & CPUID_BRAND_INDEX; + if (brand_index <= MAX_BRAND_INDEX && + cpu_brandtable[brand_index] != NULL) + strcpy(cpu_brand, + cpu_brandtable[brand_index]); + } + } +#else + /* Please make up your mind folks! */ + strcat(cpu_model, "EM64T"); +#endif + break; + case CPU_VENDOR_AMD: + /* + * Values taken from AMD Processor Recognition + * http://www.amd.com/K6/k6docs/pdf/20734g.pdf + * (also describes ``Features'' encodings. + */ + strcpy(cpu_model, "AMD "); +#ifdef __i386__ + switch (cpu_id & 0xFF0) { + case 0x410: + strcat(cpu_model, "Standard Am486DX"); + break; + case 0x430: + strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); + break; + case 0x470: + strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); + break; + case 0x480: + strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); + break; + case 0x490: + strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); + break; + case 0x4E0: + strcat(cpu_model, "Am5x86 Write-Through"); + break; + case 0x4F0: + strcat(cpu_model, "Am5x86 Write-Back"); + break; + case 0x500: + strcat(cpu_model, "K5 model 0"); + break; + case 0x510: + strcat(cpu_model, "K5 model 1"); + break; + case 0x520: + strcat(cpu_model, "K5 PR166 (model 2)"); + break; + case 0x530: + strcat(cpu_model, "K5 PR200 (model 3)"); + break; + case 0x560: + strcat(cpu_model, "K6"); + break; + case 0x570: + strcat(cpu_model, "K6 266 (model 1)"); + break; + case 0x580: + strcat(cpu_model, "K6-2"); + break; + case 0x590: + strcat(cpu_model, "K6-III"); + break; + case 0x5a0: + strcat(cpu_model, "Geode LX"); + /* + * Make sure the TSC runs through suspension, + * otherwise we can't use it as timecounter + */ + wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); + break; + default: + strcat(cpu_model, "Unknown"); + break; + } +#if defined(I586_CPU) && defined(CPU_WT_ALLOC) + if ((cpu_id & 0xf00) == 0x500) { + if (((cpu_id & 0x0f0) > 0) + && ((cpu_id & 0x0f0) < 0x60) + && ((cpu_id & 0x00f) > 3)) + enable_K5_wt_alloc(); + else if (((cpu_id & 0x0f0) > 0x80) + || (((cpu_id & 0x0f0) == 0x80) + && (cpu_id & 0x00f) > 0x07)) + enable_K6_2_wt_alloc(); + else if ((cpu_id & 0x0f0) > 0x50) + enable_K6_wt_alloc(); + } +#endif +#else + if ((cpu_id & 0xf00) == 0xf00) + strcat(cpu_model, "AMD64 Processor"); + else + strcat(cpu_model, "Unknown"); +#endif + break; +#ifdef __i386__ + case CPU_VENDOR_CYRIX: + strcpy(cpu_model, "Cyrix "); + switch (cpu_id & 0xff0) { + case 0x440: + strcat(cpu_model, "MediaGX"); + break; + case 0x520: + strcat(cpu_model, "6x86"); + break; + case 0x540: + cpu_class = CPUCLASS_586; + strcat(cpu_model, "GXm"); + break; + case 0x600: + strcat(cpu_model, "6x86MX"); + break; + default: + /* + * Even though CPU supports the cpuid + * instruction, it can be disabled. + * Therefore, this routine supports all Cyrix + * CPUs. + */ + switch (cyrix_did & 0xf0) { + case 0x00: + switch (cyrix_did & 0x0f) { + case 0x00: + strcat(cpu_model, "486SLC"); + break; + case 0x01: + strcat(cpu_model, "486DLC"); + break; + case 0x02: + strcat(cpu_model, "486SLC2"); + break; + case 0x03: + strcat(cpu_model, "486DLC2"); + break; + case 0x04: + strcat(cpu_model, "486SRx"); + break; + case 0x05: + strcat(cpu_model, "486DRx"); + break; + case 0x06: + strcat(cpu_model, "486SRx2"); + break; + case 0x07: + strcat(cpu_model, "486DRx2"); + break; + case 0x08: + strcat(cpu_model, "486SRu"); + break; + case 0x09: + strcat(cpu_model, "486DRu"); + break; + case 0x0a: + strcat(cpu_model, "486SRu2"); + break; + case 0x0b: + strcat(cpu_model, "486DRu2"); + break; + default: + strcat(cpu_model, "Unknown"); + break; + } + break; + case 0x10: + switch (cyrix_did & 0x0f) { + case 0x00: + strcat(cpu_model, "486S"); + break; + case 0x01: + strcat(cpu_model, "486S2"); + break; + case 0x02: + strcat(cpu_model, "486Se"); + break; + case 0x03: + strcat(cpu_model, "486S2e"); + break; + case 0x0a: + strcat(cpu_model, "486DX"); + break; + case 0x0b: + strcat(cpu_model, "486DX2"); + break; + case 0x0f: + strcat(cpu_model, "486DX4"); + break; + default: + strcat(cpu_model, "Unknown"); + break; + } + break; + case 0x20: + if ((cyrix_did & 0x0f) < 8) + strcat(cpu_model, "6x86"); /* Where did you get it? */ + else + strcat(cpu_model, "5x86"); + break; + case 0x30: + strcat(cpu_model, "6x86"); + break; + case 0x40: + if ((cyrix_did & 0xf000) == 0x3000) { + cpu_class = CPUCLASS_586; + strcat(cpu_model, "GXm"); + } else + strcat(cpu_model, "MediaGX"); + break; + case 0x50: + strcat(cpu_model, "6x86MX"); + break; + case 0xf0: + switch (cyrix_did & 0x0f) { + case 0x0d: + strcat(cpu_model, "Overdrive CPU"); + break; + case 0x0e: + strcpy(cpu_model, "Texas Instruments 486SXL"); + break; + case 0x0f: + strcat(cpu_model, "486SLC/DLC"); + break; + default: + strcat(cpu_model, "Unknown"); + break; + } + break; + default: + strcat(cpu_model, "Unknown"); + break; + } + break; + } + break; + case CPU_VENDOR_RISE: + strcpy(cpu_model, "Rise "); + switch (cpu_id & 0xff0) { + case 0x500: /* 6401 and 6441 (Kirin) */ + case 0x520: /* 6510 (Lynx) */ + strcat(cpu_model, "mP6"); + break; + default: + strcat(cpu_model, "Unknown"); + } + break; +#endif + case CPU_VENDOR_CENTAUR: +#ifdef __i386__ + switch (cpu_id & 0xff0) { + case 0x540: + strcpy(cpu_model, "IDT WinChip C6"); + break; + case 0x580: + strcpy(cpu_model, "IDT WinChip 2"); + break; + case 0x590: + strcpy(cpu_model, "IDT WinChip 3"); + break; + case 0x660: + strcpy(cpu_model, "VIA C3 Samuel"); + break; + case 0x670: + if (cpu_id & 0x8) + strcpy(cpu_model, "VIA C3 Ezra"); + else + strcpy(cpu_model, "VIA C3 Samuel 2"); + break; + case 0x680: + strcpy(cpu_model, "VIA C3 Ezra-T"); + break; + case 0x690: + strcpy(cpu_model, "VIA C3 Nehemiah"); + break; + case 0x6a0: + case 0x6d0: + strcpy(cpu_model, "VIA C7 Esther"); + break; + case 0x6f0: + strcpy(cpu_model, "VIA Nano"); + break; + default: + strcpy(cpu_model, "VIA/IDT Unknown"); + } +#else + strcpy(cpu_model, "VIA "); + if ((cpu_id & 0xff0) == 0x6f0) + strcat(cpu_model, "Nano Processor"); + else + strcat(cpu_model, "Unknown"); +#endif + break; +#ifdef __i386__ + case CPU_VENDOR_IBM: + strcpy(cpu_model, "Blue Lightning CPU"); + break; + case CPU_VENDOR_NSC: + switch (cpu_id & 0xff0) { + case 0x540: + strcpy(cpu_model, "Geode SC1100"); + cpu = CPU_GEODE1100; + break; + default: + strcpy(cpu_model, "Geode/NSC unknown"); + break; + } + break; +#endif + default: + strcat(cpu_model, "Unknown"); + break; + } + + /* + * Replace cpu_model with cpu_brand minus leading spaces if + * we have one. + */ + brand = cpu_brand; + while (*brand == ' ') + ++brand; + if (*brand != '\0') + strcpy(cpu_model, brand); + + printf("%s (", cpu_model); + if (tsc_freq != 0) { + hw_clockrate = (tsc_freq + 5000) / 1000000; + printf("%jd.%02d-MHz ", + (intmax_t)(tsc_freq + 4999) / 1000000, + (u_int)((tsc_freq + 4999) / 10000) % 100); + } + switch(cpu_class) { +#ifdef __i386__ + case CPUCLASS_286: + printf("286"); + break; + case CPUCLASS_386: + printf("386"); + break; +#if defined(I486_CPU) + case CPUCLASS_486: + printf("486"); + break; +#endif +#if defined(I586_CPU) + case CPUCLASS_586: + printf("586"); + break; +#endif +#if defined(I686_CPU) + case CPUCLASS_686: + printf("686"); + break; +#endif +#else + case CPUCLASS_K8: + printf("K8"); + break; +#endif + default: + printf("Unknown"); /* will panic below... */ + } + printf("-class CPU)\n"); + if (*cpu_vendor) + printf(" Origin=\"%s\"", cpu_vendor); + if (cpu_id) + printf(" Id=0x%x", cpu_id); + + if (cpu_vendor_id == CPU_VENDOR_INTEL || + cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_CENTAUR || +#ifdef __i386__ + cpu_vendor_id == CPU_VENDOR_TRANSMETA || + cpu_vendor_id == CPU_VENDOR_RISE || + cpu_vendor_id == CPU_VENDOR_NSC || + (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || +#endif + 0) { + printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); + printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); + printf(" Stepping=%u", cpu_id & CPUID_STEPPING); +#ifdef __i386__ + if (cpu_vendor_id == CPU_VENDOR_CYRIX) + printf("\n DIR=0x%04x", cyrix_did); +#endif + + /* + * AMD CPUID Specification + * http://support.amd.com/us/Embedded_TechDocs/25481.pdf + * + * Intel Processor Identification and CPUID Instruction + * http://www.intel.com/assets/pdf/appnote/241618.pdf + */ + if (cpu_high > 0) { + + /* + * Here we should probably set up flags indicating + * whether or not various features are available. + * The interesting ones are probably VME, PSE, PAE, + * and PGE. The code already assumes without bothering + * to check that all CPUs >= Pentium have a TSC and + * MSRs. + */ + printf("\n Features=0x%b", cpu_feature, + "\020" + "\001FPU" /* Integral FPU */ + "\002VME" /* Extended VM86 mode support */ + "\003DE" /* Debugging Extensions (CR4.DE) */ + "\004PSE" /* 4MByte page tables */ + "\005TSC" /* Timestamp counter */ + "\006MSR" /* Machine specific registers */ + "\007PAE" /* Physical address extension */ + "\010MCE" /* Machine Check support */ + "\011CX8" /* CMPEXCH8 instruction */ + "\012APIC" /* SMP local APIC */ + "\013oldMTRR" /* Previous implementation of MTRR */ + "\014SEP" /* Fast System Call */ + "\015MTRR" /* Memory Type Range Registers */ + "\016PGE" /* PG_G (global bit) support */ + "\017MCA" /* Machine Check Architecture */ + "\020CMOV" /* CMOV instruction */ + "\021PAT" /* Page attributes table */ + "\022PSE36" /* 36 bit address space support */ + "\023PN" /* Processor Serial number */ + "\024CLFLUSH" /* Has the CLFLUSH instruction */ + "\025" + "\026DTS" /* Debug Trace Store */ + "\027ACPI" /* ACPI support */ + "\030MMX" /* MMX instructions */ + "\031FXSR" /* FXSAVE/FXRSTOR */ + "\032SSE" /* Streaming SIMD Extensions */ + "\033SSE2" /* Streaming SIMD Extensions #2 */ + "\034SS" /* Self snoop */ + "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ + "\036TM" /* Thermal Monitor clock slowdown */ + "\037IA64" /* CPU can execute IA64 instructions */ + "\040PBE" /* Pending Break Enable */ + ); + + if (cpu_feature2 != 0) { + printf("\n Features2=0x%b", cpu_feature2, + "\020" + "\001SSE3" /* SSE3 */ + "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ + "\003DTES64" /* 64-bit Debug Trace */ + "\004MON" /* MONITOR/MWAIT Instructions */ + "\005DS_CPL" /* CPL Qualified Debug Store */ + "\006VMX" /* Virtual Machine Extensions */ + "\007SMX" /* Safer Mode Extensions */ + "\010EST" /* Enhanced SpeedStep */ + "\011TM2" /* Thermal Monitor 2 */ + "\012SSSE3" /* SSSE3 */ + "\013CNXT-ID" /* L1 context ID available */ + "\014" + "\015FMA" /* Fused Multiply Add */ + "\016CX16" /* CMPXCHG16B Instruction */ + "\017xTPR" /* Send Task Priority Messages*/ + "\020PDCM" /* Perf/Debug Capability MSR */ + "\021" + "\022PCID" /* Process-context Identifiers*/ + "\023DCA" /* Direct Cache Access */ + "\024SSE4.1" /* SSE 4.1 */ + "\025SSE4.2" /* SSE 4.2 */ + "\026x2APIC" /* xAPIC Extensions */ + "\027MOVBE" /* MOVBE Instruction */ + "\030POPCNT" /* POPCNT Instruction */ + "\031TSCDLT" /* TSC-Deadline Timer */ + "\032AESNI" /* AES Crypto */ + "\033XSAVE" /* XSAVE/XRSTOR States */ + "\034OSXSAVE" /* OS-Enabled State Management*/ + "\035AVX" /* Advanced Vector Extensions */ + "\036F16C" /* Half-precision conversions */ + "\037RDRAND" /* RDRAND Instruction */ + "\040HV" /* Hypervisor */ + ); + } + + if (amd_feature != 0) { + printf("\n AMD Features=0x%b", amd_feature, + "\020" /* in hex */ + "\001" /* Same */ + "\002" /* Same */ + "\003" /* Same */ + "\004" /* Same */ + "\005" /* Same */ + "\006" /* Same */ + "\007" /* Same */ + "\010" /* Same */ + "\011" /* Same */ + "\012" /* Same */ + "\013" /* Undefined */ + "\014SYSCALL" /* Have SYSCALL/SYSRET */ + "\015" /* Same */ + "\016" /* Same */ + "\017" /* Same */ + "\020" /* Same */ + "\021" /* Same */ + "\022" /* Same */ + "\023" /* Reserved, unknown */ + "\024MP" /* Multiprocessor Capable */ + "\025NX" /* Has EFER.NXE, NX */ + "\026" /* Undefined */ + "\027MMX+" /* AMD MMX Extensions */ + "\030" /* Same */ + "\031" /* Same */ + "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ + "\033Page1GB" /* 1-GB large page support */ + "\034RDTSCP" /* RDTSCP */ + "\035" /* Undefined */ + "\036LM" /* 64 bit long mode */ + "\0373DNow!+" /* AMD 3DNow! Extensions */ + "\0403DNow!" /* AMD 3DNow! */ + ); + } + + if (amd_feature2 != 0) { + printf("\n AMD Features2=0x%b", amd_feature2, + "\020" + "\001LAHF" /* LAHF/SAHF in long mode */ + "\002CMP" /* CMP legacy */ + "\003SVM" /* Secure Virtual Mode */ + "\004ExtAPIC" /* Extended APIC register */ + "\005CR8" /* CR8 in legacy mode */ + "\006ABM" /* LZCNT instruction */ + "\007SSE4A" /* SSE4A */ + "\010MAS" /* Misaligned SSE mode */ + "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ + "\012OSVW" /* OS visible workaround */ + "\013IBS" /* Instruction based sampling */ + "\014XOP" /* XOP extended instructions */ + "\015SKINIT" /* SKINIT/STGI */ + "\016WDT" /* Watchdog timer */ + "\017" + "\020LWP" /* Lightweight Profiling */ + "\021FMA4" /* 4-operand FMA instructions */ + "\022TCE" /* Translation Cache Extension */ + "\023" + "\024NodeId" /* NodeId MSR support */ + "\025" + "\026TBM" /* Trailing Bit Manipulation */ + "\027Topology" /* Topology Extensions */ + "\030PCXC" /* Core perf count */ + "\031PNXC" /* NB perf count */ + "\032" + "\033DBE" /* Data Breakpoint extension */ + "\034PTSC" /* Performance TSC */ + "\035PL2I" /* L2I perf count */ + "\036" + "\037" + "\040" + ); + } + + if (cpu_stdext_feature != 0) { + printf("\n Structured Extended Features=0x%b", + cpu_stdext_feature, + "\020" + /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ + "\001FSGSBASE" + "\002TSCADJ" + /* Bit Manipulation Instructions */ + "\004BMI1" + /* Hardware Lock Elision */ + "\005HLE" + /* Advanced Vector Instructions 2 */ + "\006AVX2" + /* Supervisor Mode Execution Prot. */ + "\010SMEP" + /* Bit Manipulation Instructions */ + "\011BMI2" + "\012ERMS" + /* Invalidate Processor Context ID */ + "\013INVPCID" + /* Restricted Transactional Memory */ + "\014RTM" + /* Intel Memory Protection Extensions */ + "\017MPX" + /* AVX512 Foundation */ + "\021AVX512F" + /* Enhanced NRBG */ + "\023RDSEED" + /* ADCX + ADOX */ + "\024ADX" + /* Supervisor Mode Access Prevention */ + "\025SMAP" + "\030CLFLUSHOPT" + "\032PROCTRACE" + "\033AVX512PF" + "\034AVX512ER" + "\035AVX512CD" + "\036SHA" + ); + } + + if (via_feature_rng != 0 || via_feature_xcrypt != 0) + print_via_padlock_info(); + + if (cpu_feature2 & CPUID2_VMX) + print_vmx_info(); + + if ((cpu_feature & CPUID_HTT) && + cpu_vendor_id == CPU_VENDOR_AMD) + cpu_feature &= ~CPUID_HTT; + + /* + * If this CPU supports P-state invariant TSC then + * mention the capability. + */ + if (tsc_is_invariant) { + printf("\n TSC: P-state invariant"); + if (tsc_perf_stat) + printf(", performance statistics"); + } + + } +#ifdef __i386__ + } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { + printf(" DIR=0x%04x", cyrix_did); + printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); + printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); +#ifndef CYRIX_CACHE_REALLY_WORKS + if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) + printf("\n CPU cache: write-through mode"); +#endif +#endif + } + + /* Avoid ugly blank lines: only print newline when we have to. */ + if (*cpu_vendor || cpu_id) + printf("\n"); + + if (!bootverbose) + return; + + if (cpu_vendor_id == CPU_VENDOR_AMD) + print_AMD_info(); + else if (cpu_vendor_id == CPU_VENDOR_INTEL) + print_INTEL_info(); +#ifdef __i386__ + else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) + print_transmeta_info(); +#endif +} + +void +panicifcpuunsupported(void) +{ + +#ifdef __i386__ +#if !defined(lint) +#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) +#error This kernel is not configured for one of the supported CPUs +#endif +#else /* lint */ +#endif /* lint */ +#else /* __amd64__ */ +#ifndef HAMMER +#error "You need to specify a cpu type" +#endif +#endif + /* + * Now that we have told the user what they have, + * let them know if that machine type isn't configured. + */ + switch (cpu_class) { +#ifdef __i386__ + case CPUCLASS_286: /* a 286 should not make it this far, anyway */ + case CPUCLASS_386: +#if !defined(I486_CPU) + case CPUCLASS_486: +#endif +#if !defined(I586_CPU) + case CPUCLASS_586: +#endif +#if !defined(I686_CPU) + case CPUCLASS_686: +#endif +#else /* __amd64__ */ + case CPUCLASS_X86: +#ifndef HAMMER + case CPUCLASS_K8: +#endif +#endif + panic("CPU class not configured"); + default: + break; + } +} + +#ifdef __i386__ +static volatile u_int trap_by_rdmsr; + +/* + * Special exception 6 handler. + * The rdmsr instruction generates invalid opcodes fault on 486-class + * Cyrix CPU. Stacked eip register points the rdmsr instruction in the + * function identblue() when this handler is called. Stacked eip should + * be advanced. + */ +inthand_t bluetrap6; +#ifdef __GNUCLIKE_ASM +__asm +(" \n\ + .text \n\ + .p2align 2,0x90 \n\ + .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ +" __XSTRING(CNAME(bluetrap6)) ": \n\ + ss \n\ + movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ + addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ + iret \n\ +"); +#endif + +/* + * Special exception 13 handler. + * Accessing non-existent MSR generates general protection fault. + */ +inthand_t bluetrap13; +#ifdef __GNUCLIKE_ASM +__asm +(" \n\ + .text \n\ + .p2align 2,0x90 \n\ + .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ +" __XSTRING(CNAME(bluetrap13)) ": \n\ + ss \n\ + movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ + popl %eax /* discard error code */ \n\ + addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ + iret \n\ +"); +#endif + +/* + * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not + * support cpuid instruction. This function should be called after + * loading interrupt descriptor table register. + * + * I don't like this method that handles fault, but I couldn't get + * information for any other methods. Does blue giant know? + */ +static int +identblue(void) +{ + + trap_by_rdmsr = 0; + + /* + * Cyrix 486-class CPU does not support rdmsr instruction. + * The rdmsr instruction generates invalid opcode fault, and exception + * will be trapped by bluetrap6() on Cyrix 486-class CPU. The + * bluetrap6() set the magic number to trap_by_rdmsr. + */ + setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, + GSEL(GCODE_SEL, SEL_KPL)); + + /* + * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. + * In this case, rdmsr generates general protection fault, and + * exception will be trapped by bluetrap13(). + */ + setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, + GSEL(GCODE_SEL, SEL_KPL)); + + rdmsr(0x1002); /* Cyrix CPU generates fault. */ + + if (trap_by_rdmsr == 0xa8c1d) + return IDENTBLUE_CYRIX486; + else if (trap_by_rdmsr == 0xa89c4) + return IDENTBLUE_CYRIXM2; + return IDENTBLUE_IBMCPU; +} + + +/* + * identifycyrix() set lower 16 bits of cyrix_did as follows: + * + * F E D C B A 9 8 7 6 5 4 3 2 1 0 + * +-------+-------+---------------+ + * | SID | RID | Device ID | + * | (DIR 1) | (DIR 0) | + * +-------+-------+---------------+ + */ +static void +identifycyrix(void) +{ + register_t saveintr; + int ccr2_test = 0, dir_test = 0; + u_char ccr2, ccr3; + + saveintr = intr_disable(); + + ccr2 = read_cyrix_reg(CCR2); + write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); + read_cyrix_reg(CCR2); + if (read_cyrix_reg(CCR2) != ccr2) + ccr2_test = 1; + write_cyrix_reg(CCR2, ccr2); + + ccr3 = read_cyrix_reg(CCR3); + write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); + read_cyrix_reg(CCR3); + if (read_cyrix_reg(CCR3) != ccr3) + dir_test = 1; /* CPU supports DIRs. */ + write_cyrix_reg(CCR3, ccr3); + + if (dir_test) { + /* Device ID registers are available. */ + cyrix_did = read_cyrix_reg(DIR1) << 8; + cyrix_did += read_cyrix_reg(DIR0); + } else if (ccr2_test) + cyrix_did = 0x0010; /* 486S A-step */ + else + cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ + + intr_restore(saveintr); +} +#endif + +/* Update TSC freq with the value indicated by the caller. */ +static void +tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) +{ + + /* If there was an error during the transition, don't do anything. */ + if (status != 0) + return; + + /* Total setting for this level gives the new frequency in MHz. */ + hw_clockrate = level->total_set.freq; +} + +static void +hook_tsc_freq(void *arg __unused) +{ + + if (tsc_is_invariant) + return; + + tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, + tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); +} + +SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); + +/* + * Final stage of CPU identification. + */ +#ifdef __i386__ +void +finishidentcpu(void) +#else +void +identify_cpu(void) +#endif +{ + u_int regs[4], cpu_stdext_disable; +#ifdef __i386__ + u_char ccr3; +#endif + +#ifdef __amd64__ + do_cpuid(0, regs); + cpu_high = regs[0]; + ((u_int *)&cpu_vendor)[0] = regs[1]; + ((u_int *)&cpu_vendor)[1] = regs[3]; + ((u_int *)&cpu_vendor)[2] = regs[2]; + cpu_vendor[12] = '\0'; + + do_cpuid(1, regs); + cpu_id = regs[0]; + cpu_procinfo = regs[1]; + cpu_feature = regs[3]; + cpu_feature2 = regs[2]; +#endif + + cpu_vendor_id = find_cpu_vendor_id(); + + /* + * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID + * function number again if it is set from BIOS. It is necessary + * for probing correct CPU topology later. + * XXX This is only done on the BSP package. + */ + if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 && + ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) || + (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) { + uint64_t msr; + msr = rdmsr(MSR_IA32_MISC_ENABLE); + if ((msr & 0x400000ULL) != 0) { + wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); + do_cpuid(0, regs); + cpu_high = regs[0]; + } + } + + if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { + do_cpuid(5, regs); + cpu_mon_mwait_flags = regs[2]; + cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; + cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; + } + + if (cpu_high >= 7) { + cpuid_count(7, 0, regs); + cpu_stdext_feature = regs[1]; + + /* + * Some hypervisors fail to filter out unsupported + * extended features. For now, disable the + * extensions, activation of which requires setting a + * bit in CR4, and which VM monitors do not support. + */ + if (cpu_feature2 & CPUID2_HV) { + cpu_stdext_disable = CPUID_STDEXT_FSGSBASE | + CPUID_STDEXT_SMEP; + } else + cpu_stdext_disable = 0; + TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); + cpu_stdext_feature &= ~cpu_stdext_disable; + } + +#ifdef __i386__ + if (cpu_high > 0 && + (cpu_vendor_id == CPU_VENDOR_INTEL || + cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_TRANSMETA || + cpu_vendor_id == CPU_VENDOR_CENTAUR || + cpu_vendor_id == CPU_VENDOR_NSC)) { + do_cpuid(0x80000000, regs); + if (regs[0] >= 0x80000000) + cpu_exthigh = regs[0]; + } +#else + if (cpu_vendor_id == CPU_VENDOR_INTEL || + cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_CENTAUR) { + do_cpuid(0x80000000, regs); + cpu_exthigh = regs[0]; + } +#endif + if (cpu_exthigh >= 0x80000001) { + do_cpuid(0x80000001, regs); + amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); + amd_feature2 = regs[2]; + } + if (cpu_exthigh >= 0x80000007) { + do_cpuid(0x80000007, regs); + amd_pminfo = regs[3]; + } + if (cpu_exthigh >= 0x80000008) { + do_cpuid(0x80000008, regs); + cpu_procinfo2 = regs[2]; + } + +#ifdef __i386__ + if (cpu_vendor_id == CPU_VENDOR_CYRIX) { + if (cpu == CPU_486) { + /* + * These conditions are equivalent to: + * - CPU does not support cpuid instruction. + * - Cyrix/IBM CPU is detected. + */ + if (identblue() == IDENTBLUE_IBMCPU) { + strcpy(cpu_vendor, "IBM"); + cpu_vendor_id = CPU_VENDOR_IBM; + cpu = CPU_BLUE; + return; + } + } + switch (cpu_id & 0xf00) { + case 0x600: + /* + * Cyrix's datasheet does not describe DIRs. + * Therefor, I assume it does not have them + * and use the result of the cpuid instruction. + * XXX they seem to have it for now at least. -Peter + */ + identifycyrix(); + cpu = CPU_M2; + break; + default: + identifycyrix(); + /* + * This routine contains a trick. + * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. + */ + switch (cyrix_did & 0x00f0) { + case 0x00: + case 0xf0: + cpu = CPU_486DLC; + break; + case 0x10: + cpu = CPU_CY486DX; + break; + case 0x20: + if ((cyrix_did & 0x000f) < 8) + cpu = CPU_M1; + else + cpu = CPU_M1SC; + break; + case 0x30: + cpu = CPU_M1; + break; + case 0x40: + /* MediaGX CPU */ + cpu = CPU_M1SC; + break; + default: + /* M2 and later CPUs are treated as M2. */ + cpu = CPU_M2; + + /* + * enable cpuid instruction. + */ + ccr3 = read_cyrix_reg(CCR3); + write_cyrix_reg(CCR3, CCR3_MAPEN0); + write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); + write_cyrix_reg(CCR3, ccr3); + + do_cpuid(0, regs); + cpu_high = regs[0]; /* eax */ + do_cpuid(1, regs); + cpu_id = regs[0]; /* eax */ + cpu_feature = regs[3]; /* edx */ + break; + } + } + } else if (cpu == CPU_486 && *cpu_vendor == '\0') { + /* + * There are BlueLightning CPUs that do not change + * undefined flags by dividing 5 by 2. In this case, + * the CPU identification routine in locore.s leaves + * cpu_vendor null string and puts CPU_486 into the + * cpu. + */ + if (identblue() == IDENTBLUE_IBMCPU) { + strcpy(cpu_vendor, "IBM"); + cpu_vendor_id = CPU_VENDOR_IBM; + cpu = CPU_BLUE; + return; + } + } +#else + /* XXX */ + cpu = CPU_CLAWHAMMER; +#endif +} + +static u_int +find_cpu_vendor_id(void) +{ + int i; + + for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) + if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) + return (cpu_vendors[i].vendor_id); + return (0); +} + +static void +print_AMD_assoc(int i) +{ + if (i == 255) + printf(", fully associative\n"); + else + printf(", %d-way associative\n", i); +} + +static void +print_AMD_l2_assoc(int i) +{ + switch (i & 0x0f) { + case 0: printf(", disabled/not present\n"); break; + case 1: printf(", direct mapped\n"); break; + case 2: printf(", 2-way associative\n"); break; + case 4: printf(", 4-way associative\n"); break; + case 6: printf(", 8-way associative\n"); break; + case 8: printf(", 16-way associative\n"); break; + case 15: printf(", fully associative\n"); break; + default: printf(", reserved configuration\n"); break; + } +} + +static void +print_AMD_info(void) +{ +#ifdef __i386__ + uint64_t amd_whcr; +#endif + u_int regs[4]; + + if (cpu_exthigh >= 0x80000005) { + do_cpuid(0x80000005, regs); + printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); + print_AMD_assoc(regs[0] >> 24); + + printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); + print_AMD_assoc((regs[0] >> 8) & 0xff); + + printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); + print_AMD_assoc(regs[1] >> 24); + + printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); + print_AMD_assoc((regs[1] >> 8) & 0xff); + + printf("L1 data cache: %d kbytes", regs[2] >> 24); + printf(", %d bytes/line", regs[2] & 0xff); + printf(", %d lines/tag", (regs[2] >> 8) & 0xff); + print_AMD_assoc((regs[2] >> 16) & 0xff); + + printf("L1 instruction cache: %d kbytes", regs[3] >> 24); + printf(", %d bytes/line", regs[3] & 0xff); + printf(", %d lines/tag", (regs[3] >> 8) & 0xff); + print_AMD_assoc((regs[3] >> 16) & 0xff); + } + + if (cpu_exthigh >= 0x80000006) { + do_cpuid(0x80000006, regs); + if ((regs[0] >> 16) != 0) { + printf("L2 2MB data TLB: %d entries", + (regs[0] >> 16) & 0xfff); + print_AMD_l2_assoc(regs[0] >> 28); + printf("L2 2MB instruction TLB: %d entries", + regs[0] & 0xfff); + print_AMD_l2_assoc((regs[0] >> 28) & 0xf); + } else { + printf("L2 2MB unified TLB: %d entries", + regs[0] & 0xfff); + print_AMD_l2_assoc((regs[0] >> 28) & 0xf); + } + if ((regs[1] >> 16) != 0) { + printf("L2 4KB data TLB: %d entries", + (regs[1] >> 16) & 0xfff); + print_AMD_l2_assoc(regs[1] >> 28); + + printf("L2 4KB instruction TLB: %d entries", + (regs[1] >> 16) & 0xfff); + print_AMD_l2_assoc((regs[1] >> 28) & 0xf); + } else { + printf("L2 4KB unified TLB: %d entries", + (regs[1] >> 16) & 0xfff); + print_AMD_l2_assoc((regs[1] >> 28) & 0xf); + } + printf("L2 unified cache: %d kbytes", regs[2] >> 16); + printf(", %d bytes/line", regs[2] & 0xff); + printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); + print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); + } + +#ifdef __i386__ + if (((cpu_id & 0xf00) == 0x500) + && (((cpu_id & 0x0f0) > 0x80) + || (((cpu_id & 0x0f0) == 0x80) + && (cpu_id & 0x00f) > 0x07))) { + /* K6-2(new core [Stepping 8-F]), K6-III or later */ + amd_whcr = rdmsr(0xc0000082); + if (!(amd_whcr & (0x3ff << 22))) { + printf("Write Allocate Disable\n"); + } else { + printf("Write Allocate Enable Limit: %dM bytes\n", + (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); + printf("Write Allocate 15-16M bytes: %s\n", + (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); + } + } else if (((cpu_id & 0xf00) == 0x500) + && ((cpu_id & 0x0f0) > 0x50)) { + /* K6, K6-2(old core) */ + amd_whcr = rdmsr(0xc0000082); + if (!(amd_whcr & (0x7f << 1))) { + printf("Write Allocate Disable\n"); + } else { + printf("Write Allocate Enable Limit: %dM bytes\n", + (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); + printf("Write Allocate 15-16M bytes: %s\n", + (amd_whcr & 0x0001) ? "Enable" : "Disable"); + printf("Hardware Write Allocate Control: %s\n", + (amd_whcr & 0x0100) ? "Enable" : "Disable"); + } + } +#endif + /* + * Opteron Rev E shows a bug as in very rare occasions a read memory + * barrier is not performed as expected if it is followed by a + * non-atomic read-modify-write instruction. + * As long as that bug pops up very rarely (intensive machine usage + * on other operating systems generally generates one unexplainable + * crash any 2 months) and as long as a model specific fix would be + * impratical at this stage, print out a warning string if the broken + * model and family are identified. + */ + if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && + CPUID_TO_MODEL(cpu_id) <= 0x3f) + printf("WARNING: This architecture revision has known SMP " + "hardware bugs which may cause random instability\n"); +} + +static void +print_INTEL_info(void) +{ + u_int regs[4]; + u_int rounds, regnum; + u_int nwaycode, nway; + + if (cpu_high >= 2) { + rounds = 0; + do { + do_cpuid(0x2, regs); + if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) + break; /* we have a buggy CPU */ + + for (regnum = 0; regnum <= 3; ++regnum) { + if (regs[regnum] & (1<<31)) + continue; + if (regnum != 0) + print_INTEL_TLB(regs[regnum] & 0xff); + print_INTEL_TLB((regs[regnum] >> 8) & 0xff); + print_INTEL_TLB((regs[regnum] >> 16) & 0xff); + print_INTEL_TLB((regs[regnum] >> 24) & 0xff); + } + } while (--rounds > 0); + } + + if (cpu_exthigh >= 0x80000006) { + do_cpuid(0x80000006, regs); + nwaycode = (regs[2] >> 12) & 0x0f; + if (nwaycode >= 0x02 && nwaycode <= 0x08) + nway = 1 << (nwaycode / 2); + else + nway = 0; + printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", + (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); + } +} + +static void +print_INTEL_TLB(u_int data) +{ + switch (data) { + case 0x0: + case 0x40: + default: + break; + case 0x1: + printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); + break; + case 0x2: + printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); + break; + case 0x3: + printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); + break; + case 0x4: + printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); + break; + case 0x6: + printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); + break; + case 0x8: + printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); + break; + case 0xa: + printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); + break; + case 0xc: + printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); + break; + case 0x22: + printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x23: + printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x25: + printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x29: + printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x2c: + printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); + break; + case 0x30: + printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); + break; + case 0x39: + printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x3b: + printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x3c: + printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x41: + printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); + break; + case 0x42: + printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); + break; + case 0x43: + printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); + break; + case 0x44: + printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); + break; + case 0x45: + printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); + break; + case 0x46: + printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); + break; + case 0x47: + printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); + break; + case 0x50: + printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); + break; + case 0x51: + printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); + break; + case 0x52: + printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); + break; + case 0x5b: + printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); + break; + case 0x5c: + printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); + break; + case 0x5d: + printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); + break; + case 0x60: + printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x66: + printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x67: + printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x68: + printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x70: + printf("Trace cache: 12K-uops, 8-way set associative\n"); + break; + case 0x71: + printf("Trace cache: 16K-uops, 8-way set associative\n"); + break; + case 0x72: + printf("Trace cache: 32K-uops, 8-way set associative\n"); + break; + case 0x78: + printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); + break; + case 0x79: + printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x7a: + printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x7b: + printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x7c: + printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); + break; + case 0x7d: + printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); + break; + case 0x7f: + printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); + break; + case 0x82: + printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); + break; + case 0x83: + printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); + break; + case 0x84: + printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); + break; + case 0x85: + printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); + break; + case 0x86: + printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); + break; + case 0x87: + printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); + break; + case 0xb0: + printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); + break; + case 0xb3: + printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); + break; + } +} + +#ifdef __i386__ +static void +print_transmeta_info(void) +{ + u_int regs[4], nreg = 0; + + do_cpuid(0x80860000, regs); + nreg = regs[0]; + if (nreg >= 0x80860001) { + do_cpuid(0x80860001, regs); + printf(" Processor revision %u.%u.%u.%u\n", + (regs[1] >> 24) & 0xff, + (regs[1] >> 16) & 0xff, + (regs[1] >> 8) & 0xff, + regs[1] & 0xff); + } + if (nreg >= 0x80860002) { + do_cpuid(0x80860002, regs); + printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", + (regs[1] >> 24) & 0xff, + (regs[1] >> 16) & 0xff, + (regs[1] >> 8) & 0xff, + regs[1] & 0xff, + regs[2]); + } + if (nreg >= 0x80860006) { + char info[65]; + do_cpuid(0x80860003, (u_int*) &info[0]); + do_cpuid(0x80860004, (u_int*) &info[16]); + do_cpuid(0x80860005, (u_int*) &info[32]); + do_cpuid(0x80860006, (u_int*) &info[48]); + info[64] = 0; + printf(" %s\n", info); + } +} +#endif + +static void +print_via_padlock_info(void) +{ + u_int regs[4]; + + do_cpuid(0xc0000001, regs); + printf("\n VIA Padlock Features=0x%b", regs[3], + "\020" + "\003RNG" /* RNG */ + "\007AES" /* ACE */ + "\011AES-CTR" /* ACE2 */ + "\013SHA1,SHA256" /* PHE */ + "\015RSA" /* PMM */ + ); +} + +static uint32_t +vmx_settable(uint64_t basic, int msr, int true_msr) +{ + uint64_t val; + + if (basic & (1ULL << 55)) + val = rdmsr(true_msr); + else + val = rdmsr(msr); + + /* Just report the controls that can be set to 1. */ + return (val >> 32); +} + +static void +print_vmx_info(void) +{ + uint64_t basic, msr; + uint32_t entry, exit, mask, pin, proc, proc2; + int comma; + + printf("\n VT-x: "); + msr = rdmsr(MSR_IA32_FEATURE_CONTROL); + if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) + printf("(disabled in BIOS) "); + basic = rdmsr(MSR_VMX_BASIC); + pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, + MSR_VMX_TRUE_PINBASED_CTLS); + proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, + MSR_VMX_TRUE_PROCBASED_CTLS); + if (proc & PROCBASED_SECONDARY_CONTROLS) + proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, + MSR_VMX_PROCBASED_CTLS2); + else + proc2 = 0; + exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); + entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); + + if (!bootverbose) { + comma = 0; + if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && + entry & VM_ENTRY_LOAD_PAT) { + printf("%sPAT", comma ? "," : ""); + comma = 1; + } + if (proc & PROCBASED_HLT_EXITING) { + printf("%sHLT", comma ? "," : ""); + comma = 1; + } + if (proc & PROCBASED_MTF) { + printf("%sMTF", comma ? "," : ""); + comma = 1; + } + if (proc & PROCBASED_PAUSE_EXITING) { + printf("%sPAUSE", comma ? "," : ""); + comma = 1; + } + if (proc2 & PROCBASED2_ENABLE_EPT) { + printf("%sEPT", comma ? "," : ""); + comma = 1; + } + if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { + printf("%sUG", comma ? "," : ""); + comma = 1; + } + if (proc2 & PROCBASED2_ENABLE_VPID) { + printf("%sVPID", comma ? "," : ""); + comma = 1; + } + if (proc & PROCBASED_USE_TPR_SHADOW && + proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && + proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && + proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && + proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { + printf("%sVID", comma ? "," : ""); + comma = 1; + if (pin & PINBASED_POSTED_INTERRUPT) + printf(",PostIntr"); + } + return; + } + + mask = basic >> 32; + printf("Basic Features=0x%b", mask, + "\020" + "\02132PA" /* 32-bit physical addresses */ + "\022SMM" /* SMM dual-monitor */ + "\027INS/OUTS" /* VM-exit info for INS and OUTS */ + "\030TRUE" /* TRUE_CTLS MSRs */ + ); + printf("\n Pin-Based Controls=0x%b", pin, + "\020" + "\001ExtINT" /* External-interrupt exiting */ + "\004NMI" /* NMI exiting */ + "\006VNMI" /* Virtual NMIs */ + "\007PreTmr" /* Activate VMX-preemption timer */ + "\010PostIntr" /* Process posted interrupts */ + ); + printf("\n Primary Processor Controls=0x%b", proc, + "\020" + "\003INTWIN" /* Interrupt-window exiting */ + "\004TSCOff" /* Use TSC offsetting */ + "\010HLT" /* HLT exiting */ + "\012INVLPG" /* INVLPG exiting */ + "\013MWAIT" /* MWAIT exiting */ + "\014RDPMC" /* RDPMC exiting */ + "\015RDTSC" /* RDTSC exiting */ + "\020CR3-LD" /* CR3-load exiting */ + "\021CR3-ST" /* CR3-store exiting */ + "\024CR8-LD" /* CR8-load exiting */ + "\025CR8-ST" /* CR8-store exiting */ + "\026TPR" /* Use TPR shadow */ + "\027NMIWIN" /* NMI-window exiting */ + "\030MOV-DR" /* MOV-DR exiting */ + "\031IO" /* Unconditional I/O exiting */ + "\032IOmap" /* Use I/O bitmaps */ + "\034MTF" /* Monitor trap flag */ + "\035MSRmap" /* Use MSR bitmaps */ + "\036MONITOR" /* MONITOR exiting */ + "\037PAUSE" /* PAUSE exiting */ + ); + if (proc & PROCBASED_SECONDARY_CONTROLS) + printf("\n Secondary Processor Controls=0x%b", proc2, + "\020" + "\001APIC" /* Virtualize APIC accesses */ + "\002EPT" /* Enable EPT */ + "\003DT" /* Descriptor-table exiting */ + "\004RDTSCP" /* Enable RDTSCP */ + "\005x2APIC" /* Virtualize x2APIC mode */ + "\006VPID" /* Enable VPID */ + "\007WBINVD" /* WBINVD exiting */ + "\010UG" /* Unrestricted guest */ + "\011APIC-reg" /* APIC-register virtualization */ + "\012VID" /* Virtual-interrupt delivery */ + "\013PAUSE-loop" /* PAUSE-loop exiting */ + "\014RDRAND" /* RDRAND exiting */ + "\015INVPCID" /* Enable INVPCID */ + "\016VMFUNC" /* Enable VM functions */ + "\017VMCS" /* VMCS shadowing */ + "\020EPT#VE" /* EPT-violation #VE */ + "\021XSAVES" /* Enable XSAVES/XRSTORS */ + ); + printf("\n Exit Controls=0x%b", mask, + "\020" + "\003DR" /* Save debug controls */ + /* Ignore Host address-space size */ + "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ + "\020AckInt" /* Acknowledge interrupt on exit */ + "\023PAT-SV" /* Save MSR_PAT */ + "\024PAT-LD" /* Load MSR_PAT */ + "\025EFER-SV" /* Save MSR_EFER */ + "\026EFER-LD" /* Load MSR_EFER */ + "\027PTMR-SV" /* Save VMX-preemption timer value */ + ); + printf("\n Entry Controls=0x%b", mask, + "\020" + "\003DR" /* Save debug controls */ + /* Ignore IA-32e mode guest */ + /* Ignore Entry to SMM */ + /* Ignore Deactivate dual-monitor treatment */ + "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ + "\017PAT" /* Load MSR_PAT */ + "\020EFER" /* Load MSR_EFER */ + ); + if (proc & PROCBASED_SECONDARY_CONTROLS && + (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { + msr = rdmsr(MSR_VMX_EPT_VPID_CAP); + mask = msr; + printf("\n EPT Features=0x%b", mask, + "\020" + "\001XO" /* Execute-only translations */ + "\007PW4" /* Page-walk length of 4 */ + "\011UC" /* EPT paging-structure mem can be UC */ + "\017WB" /* EPT paging-structure mem can be WB */ + "\0212M" /* EPT PDE can map a 2-Mbyte page */ + "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ + "\025INVEPT" /* INVEPT is supported */ + "\026AD" /* Accessed and dirty flags for EPT */ + "\032single" /* INVEPT single-context type */ + "\033all" /* INVEPT all-context type */ + ); + mask = msr >> 32; + printf("\n VPID Features=0x%b", mask, + "\020" + "\001INVVPID" /* INVVPID is supported */ + "\011individual" /* INVVPID individual-address type */ + "\012single" /* INVVPID single-context type */ + "\013all" /* INVVPID all-context type */ + /* INVVPID single-context-retaining-globals type */ + "\014single-globals" + ); + } +} Property changes on: head/sys/x86/x86/identcpu.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property