Index: head/sys/arm/freescale/imx/imx51_ccm.c =================================================================== --- head/sys/arm/freescale/imx/imx51_ccm.c (revision 271054) +++ head/sys/arm/freescale/imx/imx51_ccm.c (revision 271055) @@ -1,582 +1,589 @@ /* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ /* * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved. * Written by Hashimoto Kenichi for Genetec Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 2012, 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Clock Controller Module (CCM) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define IMXCCMDEBUG #undef IMXCCMDEBUG #ifndef IMX51_OSC_FREQ #define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ #endif #ifndef IMX51_CKIL_FREQ #define IMX51_CKIL_FREQ 32768 #endif struct imxccm_softc { device_t sc_dev; struct resource *res[7]; u_int64_t pll_freq[IMX51_N_DPLLS]; }; struct imxccm_softc *ccm_softc = NULL; static uint64_t imx51_get_pll_freq(u_int); static int imxccm_match(device_t); static int imxccm_attach(device_t); static device_method_t imxccm_methods[] = { DEVMETHOD(device_probe, imxccm_match), DEVMETHOD(device_attach, imxccm_attach), DEVMETHOD_END }; static driver_t imxccm_driver = { "imxccm", imxccm_methods, sizeof(struct imxccm_softc), }; static devclass_t imxccm_devclass; EARLY_DRIVER_MODULE(imxccm, simplebus, imxccm_driver, imxccm_devclass, 0, 0, BUS_PASS_CPU); static struct resource_spec imxccm_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */ { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* DPLLIP1 */ { SYS_RES_MEMORY, 2, RF_ACTIVE }, /* DPLLIP2 */ { SYS_RES_MEMORY, 3, RF_ACTIVE }, /* DPLLIP3 */ { SYS_RES_IRQ, 0, RF_ACTIVE }, /* 71 */ { SYS_RES_IRQ, 1, RF_ACTIVE }, /* 72 */ { -1, 0 } }; static int imxccm_match(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,imx51-ccm") && !ofw_bus_is_compatible(dev, "fsl,imx53-ccm")) return (ENXIO); device_set_desc(dev, "Freescale Clock Control Module"); return (BUS_PROBE_DEFAULT); } static int imxccm_attach(device_t dev) { struct imxccm_softc *sc; sc = device_get_softc(dev); sc->sc_dev = dev; if (bus_alloc_resources(dev, imxccm_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } ccm_softc = sc; imx51_get_pll_freq(1); imx51_get_pll_freq(2); imx51_get_pll_freq(3); device_printf(dev, "PLL1=%lluMHz, PLL2=%lluMHz, PLL3=%lluMHz\n", sc->pll_freq[0] / 1000000, sc->pll_freq[1] / 1000000, sc->pll_freq[2] / 1000000); device_printf(dev, "CPU clock=%d, UART clock=%d\n", imx51_get_clock(IMX51CLK_ARM_ROOT), imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); device_printf(dev, "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n", imx51_get_clock(IMX51CLK_MAIN_BUS_CLK), imx51_get_clock(IMX51CLK_AHB_CLK_ROOT), imx51_get_clock(IMX51CLK_IPG_CLK_ROOT), imx51_get_clock(IMX51CLK_PERCLK_ROOT)); return (0); } u_int imx51_get_clock(enum imx51_clock clk) { u_int freq; u_int sel; uint32_t cacrr; /* ARM clock root register */ uint32_t ccsr; uint32_t cscdr1; uint32_t cscmr1; uint32_t cbcdr; uint32_t cbcmr; uint32_t cdcr; if (ccm_softc == NULL) return (0); switch (clk) { case IMX51CLK_PLL1: case IMX51CLK_PLL2: case IMX51CLK_PLL3: return ccm_softc->pll_freq[clk-IMX51CLK_PLL1]; case IMX51CLK_PLL1SW: ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0) return ccm_softc->pll_freq[1-1]; /* step clock */ /* FALLTHROUGH */ case IMX51CLK_PLL1STEP: ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) { case 0: return imx51_get_clock(IMX51CLK_LP_APM); case 1: return 0; /* XXX PLL bypass clock */ case 2: return ccm_softc->pll_freq[2-1] / (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >> CCSR_PLL2_DIV_PODF_SHIFT)); case 3: return ccm_softc->pll_freq[3-1] / (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >> CCSR_PLL3_DIV_PODF_SHIFT)); } /*NOTREACHED*/ case IMX51CLK_PLL2SW: ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0) return imx51_get_clock(IMX51CLK_PLL2); return 0; /* XXX PLL2 bypass clk */ case IMX51CLK_PLL3SW: ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0) return imx51_get_clock(IMX51CLK_PLL3); return 0; /* XXX PLL3 bypass clk */ case IMX51CLK_LP_APM: ccsr = bus_read_4(ccm_softc->res[0], CCMC_CCSR); return (ccsr & CCSR_LP_APM) ? imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ; case IMX51CLK_ARM_ROOT: freq = imx51_get_clock(IMX51CLK_PLL1SW); cacrr = bus_read_4(ccm_softc->res[0], CCMC_CACRR); return freq / (cacrr + 1); /* ... */ case IMX51CLK_MAIN_BUS_CLK_SRC: cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR); if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0) freq = imx51_get_clock(IMX51CLK_PLL2SW); else { freq = 0; cbcmr = bus_read_4(ccm_softc->res[0], CCMC_CBCMR); switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >> CBCMR_PERIPH_APM_SEL_SHIFT) { case 0: freq = imx51_get_clock(IMX51CLK_PLL1SW); break; case 1: freq = imx51_get_clock(IMX51CLK_PLL3SW); break; case 2: freq = imx51_get_clock(IMX51CLK_LP_APM); break; case 3: /* XXX: error */ break; } } return freq; case IMX51CLK_MAIN_BUS_CLK: freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); cdcr = bus_read_4(ccm_softc->res[0], CCMC_CDCR); return freq / (1 + ((cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >> CDCR_PERIPH_CLK_DVFS_PODF_SHIFT)); case IMX51CLK_AHB_CLK_ROOT: freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK); cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR); return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >> CBCDR_AHB_PODF_SHIFT)); case IMX51CLK_IPG_CLK_ROOT: freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR); return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >> CBCDR_IPG_PODF_SHIFT)); case IMX51CLK_PERCLK_ROOT: cbcmr = bus_read_4(ccm_softc->res[0], CCMC_CBCMR); if (cbcmr & CBCMR_PERCLK_IPG_SEL) return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); if (cbcmr & CBCMR_PERCLK_LP_APM_SEL) freq = imx51_get_clock(IMX51CLK_LP_APM); else freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); cbcdr = bus_read_4(ccm_softc->res[0], CCMC_CBCDR); #ifdef IMXCCMDEBUG printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr); #endif freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >> CBCDR_PERCLK_PRED1_SHIFT); freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >> CBCDR_PERCLK_PRED2_SHIFT); freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >> CBCDR_PERCLK_PODF_SHIFT); return freq; case IMX51CLK_UART_CLK_ROOT: cscdr1 = bus_read_4(ccm_softc->res[0], CCMC_CSCDR1); cscmr1 = bus_read_4(ccm_softc->res[0], CCMC_CSCMR1); #ifdef IMXCCMDEBUG printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1); #endif sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >> CSCMR1_UART_CLK_SEL_SHIFT; freq = 0; /* shut up GCC */ switch (sel) { case 0: case 1: case 2: freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); break; case 3: freq = imx51_get_clock(IMX51CLK_LP_APM); break; } return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >> CSCDR1_UART_CLK_PRED_SHIFT)) / (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >> CSCDR1_UART_CLK_PODF_SHIFT)); case IMX51CLK_IPU_HSP_CLK_ROOT: freq = 0; cbcmr = bus_read_4(ccm_softc->res[0], CCMC_CBCMR); switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >> CBCMR_IPU_HSP_CLK_SEL_SHIFT) { case 0: freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK); break; case 1: freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK); break; case 2: freq = imx51_get_clock( IMX51CLK_EMI_SLOW_CLK_ROOT); break; case 3: freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); break; } return freq; default: device_printf(ccm_softc->sc_dev, "clock %d: not supported yet\n", clk); return 0; } } static uint64_t imx51_get_pll_freq(u_int pll_no) { uint32_t dp_ctrl; uint32_t dp_op; uint32_t dp_mfd; uint32_t dp_mfn; uint32_t mfi; int32_t mfn; uint32_t mfd; uint32_t pdf; uint32_t ccr; uint64_t freq = 0; u_int ref = 0; KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS, ("Wrong PLL id")); dp_ctrl = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_CTL); if (dp_ctrl & DP_CTL_HFSM) { dp_op = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_HFS_OP); dp_mfd = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_HFS_MFD); dp_mfn = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_HFS_MFN); } else { dp_op = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_OP); dp_mfd = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_MFD); dp_mfn = bus_read_4(ccm_softc->res[pll_no], DPLL_DP_MFN); } pdf = dp_op & DP_OP_PDF_MASK; mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT); mfd = dp_mfd; if (dp_mfn & 0x04000000) /* 27bit signed value */ mfn = (uint32_t)(0xf8000000 | dp_mfn); else mfn = dp_mfn; switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) { case DP_CTL_REF_CLK_SEL_COSC: /* Internal Oscillator */ /* TODO: get from FDT "fsl,imx-osc" */ ref = 24000000; /* IMX51_OSC_FREQ */ break; case DP_CTL_REF_CLK_SEL_FPM: ccr = bus_read_4(ccm_softc->res[0], CCMC_CCR); if (ccr & CCR_FPM_MULT) /* TODO: get from FDT "fsl,imx-ckil" */ ref = 32768 * 1024; else /* TODO: get from FDT "fsl,imx-ckil" */ ref = 32768 * 512; break; default: ref = 0; } if (dp_ctrl & DP_CTL_REF_CLK_DIV) ref /= 2; ref *= 4; freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1); freq /= pdf + 1; if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN)) freq /= 2; #ifdef IMXCCMDEBUG printf("ref: %dKHz ", ref); printf("dp_ctl: %08x ", dp_ctrl); printf("pdf: %3d ", pdf); printf("mfi: %3d ", mfi); printf("mfd: %3d ", mfd); printf("mfn: %3d ", mfn); printf("pll: %d\n", (uint32_t)freq); #endif ccm_softc->pll_freq[pll_no-1] = freq; return (freq); } void imx51_clk_gating(int clk_src, int mode) { int field, group; uint32_t reg; group = CCMR_CCGR_MODULE(clk_src); field = clk_src % CCMR_CCGR_NSOURCE; reg = bus_read_4(ccm_softc->res[0], CCMC_CCGR(group)); reg &= ~(0x03 << field * 2); reg |= (mode << field * 2); bus_write_4(ccm_softc->res[0], CCMC_CCGR(group), reg); } int imx51_get_clk_gating(int clk_src) { uint32_t reg; reg = bus_read_4(ccm_softc->res[0], CCMC_CCGR(CCMR_CCGR_MODULE(clk_src))); return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03); } /* * Code from here down is temporary, in lieu of a SoC-independent clock API. */ void imx_ccm_usb_enable(device_t dev) { uint32_t regval; /* * Select PLL2 as the source for the USB clock. * The default is PLL3, but U-boot changes it to PLL2. */ regval = bus_read_4(ccm_softc->res[0], CCMC_CSCMR1); regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK; regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT; bus_write_4(ccm_softc->res[0], CCMC_CSCMR1, regval); /* * Set the USB clock pre-divider to div-by-5, post-divider to div-by-2. */ regval = bus_read_4(ccm_softc->res[0], CCMC_CSCDR1); regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK; regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK; regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT; regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT; bus_write_4(ccm_softc->res[0], CCMC_CSCDR1, regval); /* * The same two clocks gates are used on imx51 and imx53. */ imx51_clk_gating(CCGR_USBOH3_IPG_AHB_CLK, CCGR_CLK_MODE_ALWAYS); imx51_clk_gating(CCGR_USBOH3_60M_CLK, CCGR_CLK_MODE_ALWAYS); } void imx_ccm_usbphy_enable(device_t dev) { uint32_t regval; /* * Select PLL3 as the source for the USBPHY clock. U-boot does this * only for imx53, but the bit exists on imx51. That seems a bit * strange, but we'll go with it until more is known. */ if (imx_soc_type() == IMXSOC_53) { regval = bus_read_4(ccm_softc->res[0], CCMC_CSCMR1); regval |= 1 << CSCMR1_USBPHY_CLK_SEL_SHIFT; bus_write_4(ccm_softc->res[0], CCMC_CSCMR1, regval); } /* * For the imx51 there's just one phy gate control, enable it. */ if (imx_soc_type() == IMXSOC_51) { imx51_clk_gating(CCGR_USB_PHY_CLK, CCGR_CLK_MODE_ALWAYS); return; } /* * For imx53 we don't have a full set of clock defines yet, but the * datasheet says: * gate reg 4, bits 13-12 usb ph2 clock (usb_phy2_clk_enable) * gate reg 4, bits 11-10 usb ph1 clock (usb_phy1_clk_enable) * * We should use the fdt data for the device to figure out which of * the two we're working on, but for now just turn them both on. */ if (imx_soc_type() == IMXSOC_53) { imx51_clk_gating(__CCGR_NUM(4, 5), CCGR_CLK_MODE_ALWAYS); imx51_clk_gating(__CCGR_NUM(4, 6), CCGR_CLK_MODE_ALWAYS); return; } } uint32_t imx_ccm_ipg_hz(void) { return (imx51_get_clock(IMX51CLK_IPG_CLK_ROOT)); } uint32_t imx_ccm_sdhci_hz(void) { return (imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT)); } uint32_t imx_ccm_perclk_hz(void) { return (imx51_get_clock(IMX51CLK_PERCLK_ROOT)); } uint32_t imx_ccm_uart_hz(void) { return (imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); } + +uint32_t +imx_ccm_ahb_hz(void) +{ + + return (imx51_get_clock(IMX51CLK_AHB_CLK_ROOT)); +} Index: head/sys/arm/freescale/imx/imx6_ccm.c =================================================================== --- head/sys/arm/freescale/imx/imx6_ccm.c (revision 271054) +++ head/sys/arm/freescale/imx/imx6_ccm.c (revision 271055) @@ -1,259 +1,265 @@ /*- * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Clocks and power control driver for Freescale i.MX6 family of SoCs. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifndef CCGR_CLK_MODE_ALWAYS #define CCGR_CLK_MODE_OFF 0 #define CCGR_CLK_MODE_RUNMODE 1 #define CCGR_CLK_MODE_ALWAYS 3 #endif struct ccm_softc { device_t dev; struct resource *mem_res; }; static struct ccm_softc *ccm_sc; static inline uint32_t RD4(struct ccm_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } static int ccm_detach(device_t dev) { struct ccm_softc *sc; sc = device_get_softc(dev); if (sc->mem_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); return (0); } static int ccm_attach(device_t dev) { struct ccm_softc *sc; int err, rid; uint32_t reg; sc = device_get_softc(dev); err = 0; /* Allocate bus_space resources. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "Cannot allocate memory resources\n"); err = ENXIO; goto out; } ccm_sc = sc; /* * Configure the Low Power Mode setting to leave the ARM core power on * when a WFI instruction is executed. This lets the MPCore timers and * GIC continue to run, which is helpful when the only thing that can * wake you up is an MPCore Private Timer interrupt delivered via GIC. * * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be * required when the LPM bits are set to LPM_RUN. But experimentally * I've experienced a fairly rare lockup when not setting it. I was * unable to prove conclusively that the lockup was related to power * management or that this definitively fixes it. Revisit this. */ reg = RD4(sc, CCM_CGPR); reg |= CCM_CGPR_INT_MEM_CLK_LPM; WR4(sc, CCM_CGPR, reg); reg = RD4(sc, CCM_CLPCR); reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; WR4(sc, CCM_CLPCR, reg); err = 0; out: if (err != 0) ccm_detach(dev); return (err); } static int ccm_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0) return (ENXIO); device_set_desc(dev, "Freescale i.MX6 Clock Control Module"); return (BUS_PROBE_DEFAULT); } void imx_ccm_usb_enable(device_t _usbdev) { /* * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for * shifting and masking here, just set the low-order two bits to ALWAYS. */ WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); } void imx_ccm_usbphy_enable(device_t _phydev) { /* * XXX Which unit? * Right now it's not clear how to figure from fdt data which phy unit * we're supposed to operate on. Until this is worked out, just enable * both PHYs. */ #if 0 int phy_num, regoff; phy_num = 0; /* XXX */ switch (phy_num) { case 0: regoff = 0; break; case 1: regoff = 0x10; break; default: device_printf(ccm_sc->dev, "Bad PHY number %u,\n", phy_num); return; } imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); #else imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); #endif } uint32_t imx_ccm_ipg_hz(void) { return (66000000); } uint32_t imx_ccm_perclk_hz(void) { return (66000000); } uint32_t imx_ccm_sdhci_hz(void) { return (200000000); } uint32_t imx_ccm_uart_hz(void) { return (80000000); } +uint32_t +imx_ccm_ahb_hz(void) +{ + return (132000000); +} + static device_method_t ccm_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccm_probe), DEVMETHOD(device_attach, ccm_attach), DEVMETHOD(device_detach, ccm_detach), DEVMETHOD_END }; static driver_t ccm_driver = { "ccm", ccm_methods, sizeof(struct ccm_softc) }; static devclass_t ccm_devclass; DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0); Index: head/sys/arm/freescale/imx/imx_ccmvar.h =================================================================== --- head/sys/arm/freescale/imx/imx_ccmvar.h (revision 271054) +++ head/sys/arm/freescale/imx/imx_ccmvar.h (revision 271055) @@ -1,54 +1,55 @@ /*- * Copyright (c) 2014 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX_CCMVAR_H #define IMX_CCMVAR_H /* * We need a clock management system that works across unrelated SoCs and * devices. For now, to keep imx development moving, define some barebones * functionality that can be shared within the imx family by having each SoC * implement functions with a common name. * * The usb enable functions are best-effort. They turn on the usb otg, host, * and phy clocks in a SoC-specific manner, but it may take a lot more than that * to make usb work on a given board. In particular, it can require specific * pinmux setup of gpio pins connected to external phy parts, voltage regulators * and overcurrent detectors, and so on. On such boards, u-boot or other early * board setup code has to handle those things. */ uint32_t imx_ccm_ipg_hz(void); uint32_t imx_ccm_perclk_hz(void); uint32_t imx_ccm_sdhci_hz(void); uint32_t imx_ccm_uart_hz(void); +uint32_t imx_ccm_ahb_hz(void); void imx_ccm_usb_enable(device_t _usbdev); void imx_ccm_usbphy_enable(device_t _phydev); #endif