Index: head/sys/arm/conf/DIGI-CCWMX53 =================================================================== --- head/sys/arm/conf/DIGI-CCWMX53 (revision 264250) +++ head/sys/arm/conf/DIGI-CCWMX53 (revision 264251) @@ -1,182 +1,189 @@ # Kernel configuration for Digi ConnectCore Wi-i.MX53 boards # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident DIGI-CCWMX53 include "../freescale/imx/std.imx53" makeoptions WITHOUT_MODULES="ahc" makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols #options DEBUG options SCHED_4BSD # 4BSD scheduler #options PREEMPTION # Enable kernel thread preemption options INET # InterNETworking options INET6 # IPv6 communications protocols #options SCTP # Stream Control Transmission Protocol options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling #options MD_ROOT # MD is a potential root device options NFSCL # New Network Filesystem Client #options NFSD # New Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options TMPFS # Efficient memory filesystem options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem #options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options GEOM_PART_BSD # BSD partition scheme options GEOM_PART_MBR # MBR partition scheme options GEOM_PART_GPT # GUID Partition Tables. options GEOM_LABEL # Provides labelization #options COMPAT_FREEBSD5 # Compatible with FreeBSD5 #options COMPAT_FREEBSD6 # Compatible with FreeBSD6 #options COMPAT_FREEBSD7 # Compatible with FreeBSD7 options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options INCLUDE_CONFIG_FILE # Include this file in kernel options VFP # vfp/neon # required for netbooting #options BOOTP #options BOOTP_COMPAT #options BOOTP_NFSROOT #options BOOTP_NFSV3 #options BOOTP_WIRED_TO=ffec0 #options ROOTDEVNAME=\"ufs:ada0s2a\" # kernel/memory size reduction #options MUTEX_NOINLINE #options NO_FFS_SNAPSHOT #options NO_SWAPPING #options NO_SYSCTL_DESCR #options RWLOCK_NOINLINE # Debugging support. Always need this: options KDB # Enable kernel debugger support. # For minimum debugger support (stable branch) use: #options KDB_TRACE # Print a stack trace for a panic. # For full debugger support use this instead: options DDB # Support DDB. #options GDB # Support remote GDB. options DEADLKRES # Enable the deadlock resolver options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # Pseudo devices. device loop # Network loopback device random # Entropy device device ether # Ethernet support #device vlan # 802.1Q VLAN support #device tun # Packet tunnel. #device md # Memory "disks" #device gif # IPv6 and IPv4 tunneling #device faith # IPv6-to-IPv4 relaying (translation) #device firmware # firmware assist module # Ethernet device ffec # Freescale Fast Ethernet Controller device miibus # Standard mii bus # Serial (COM) ports device uart # Multi-uart driver options ALT_BREAK_TO_DEBUGGER device ata device atapci # Only for helper functions device imxata options ATA_STATIC_ID # Static device numbering device iomux # IO Multiplexor device gpio device gpioled device fsliic device iic device iicbus # SCSI peripherals device scbus # SCSI bus (required for SCSI) device da # Direct Access (disks) device cd # CD device pass # Passthrough device (direct SCSI access) # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. options USB_DEBUG # enable debug msgs device ehci # OHCI USB interface device usb # USB Bus (required) device umass # Disks/Mass storage - Requires scbus and da device uhid # "Human Interface Devices" #device ukbd # Allow keyboard like HIDs to control console device ums # USB Ethernet, requires miibus #device miibus #device aue # ADMtek USB Ethernet #device axe # ASIX Electronics USB Ethernet #device cdce # Generic USB over Ethernet #device cue # CATC USB Ethernet #device kue # Kawasaki LSI USB Ethernet #device rue # RealTek RTL8150 USB Ethernet #device udav # Davicom DM9601E USB # USB Wireless #device rum # Ralink Technology RT2501USB wireless NICs # Watchdog timer. # WARNING: can't be disabled!!! device imxwdt # Watchdog # Wireless NIC cards device wlan # 802.11 support device wlan_wep # 802.11 WEP support device wlan_ccmp # 802.11 CCMP support device wlan_tkip # 802.11 TKIP support device wlan_amrr # AMRR transmit rate control algorithm +# MMC +#device sdhci # SD controller +#device mmc # SD/MMC protocol +#device mmcsd # SDCard disk device + + # Flattened Device Tree options FDT options FDT_DTB_STATIC makeoptions FDT_DTS_FILE=digi-ccwmx53.dts # NOTE: serial console will be disabled if syscons enabled # Uncomment following lines for framebuffer/syscons support #device sc +#device vt #device kbdmux #options SC_DFLT_FONT # compile font in #makeoptions SC_DFLT_FONT=cp437 Index: head/sys/arm/freescale/imx/files.imx53 =================================================================== --- head/sys/arm/freescale/imx/files.imx53 (revision 264250) +++ head/sys/arm/freescale/imx/files.imx53 (revision 264251) @@ -1,56 +1,59 @@ # $FreeBSD$ arm/arm/bus_space_asm_generic.S standard arm/arm/bus_space_generic.c standard arm/arm/cpufunc_asm_armv5.S standard arm/arm/cpufunc_asm_arm11.S standard arm/arm/cpufunc_asm_armv7.S standard kern/kern_clocksource.c standard # Init arm/freescale/imx/imx_common.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx53_machdep.c standard arm/arm/bus_space-v6.c standard # Special serial console for debuging early boot code #arm/freescale/imx/console.c standard # UART driver (includes serial console support) dev/uart/uart_dev_imx.c optional uart # TrustZone Interrupt Controller arm/freescale/imx/tzic.c standard # IOMUX - external pins multiplexor arm/freescale/imx/imx51_iomux.c optional iomux # GPIO arm/freescale/imx/imx51_gpio.c optional gpio # Generic Periodic Timer arm/freescale/imx/imx_gpt.c standard # Clock Configuration Manager arm/freescale/imx/imx51_ccm.c standard # i.MX5xx PATA controller dev/ata/chipsets/ata-fsl.c optional imxata +# SDHCI/MMC +arm/freescale/imx/imx_sdhci.c optional sdhci + # USB OH3 controller (1 OTG, 3 EHCI) arm/freescale/imx/imx_nop_usbphy.c optional ehci dev/usb/controller/ehci_imx.c optional ehci # Watchdog arm/freescale/imx/imx_wdog.c optional imxwdt # i2c arm/freescale/imx/i2c.c optional fsliic # IPU - Image Processing Unit (frame buffer also) arm/freescale/imx/imx51_ipuv3.c optional sc arm/freescale/imx/imx51_ipuv3_fbd.c optional vt dev/vt/hw/fb/vt_early_fb.c optional vt # Fast Ethernet Controller dev/ffec/if_ffec.c optional ffec Index: head/sys/arm/freescale/imx/imx51_ipuv3.c =================================================================== --- head/sys/arm/freescale/imx/imx51_ipuv3.c (revision 264250) +++ head/sys/arm/freescale/imx/imx51_ipuv3.c (revision 264251) @@ -1,880 +1,897 @@ /*- * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2012, 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define IMX51_IPU_HSP_CLOCK 665000000 #define IPU3FB_FONT_HEIGHT 16 struct ipu3sc_softc { device_t dev; bus_addr_t pbase; bus_addr_t vbase; bus_space_tag_t iot; bus_space_handle_t ioh; bus_space_handle_t cm_ioh; bus_space_handle_t dp_ioh; bus_space_handle_t di0_ioh; bus_space_handle_t di1_ioh; bus_space_handle_t dctmpl_ioh; bus_space_handle_t dc_ioh; bus_space_handle_t dmfc_ioh; bus_space_handle_t idmac_ioh; bus_space_handle_t cpmem_ioh; }; struct video_adapter_softc { /* Videoadpater part */ video_adapter_t va; intptr_t fb_addr; intptr_t fb_paddr; unsigned int fb_size; int bpp; int depth; unsigned int height; unsigned int width; unsigned int stride; unsigned int xmargin; unsigned int ymargin; unsigned char *font; int initialized; }; static struct ipu3sc_softc *ipu3sc_softc; static struct video_adapter_softc va_softc; /* FIXME: not only 2 bytes color supported */ static uint16_t colors[16] = { 0x0000, /* black */ 0x001f, /* blue */ 0x07e0, /* green */ 0x07ff, /* cyan */ 0xf800, /* red */ 0xf81f, /* magenta */ 0x3800, /* brown */ 0xc618, /* light grey */ 0xc618, /* XXX: dark grey */ 0x001f, /* XXX: light blue */ 0x07e0, /* XXX: light green */ 0x07ff, /* XXX: light cyan */ 0xf800, /* XXX: light red */ 0xf81f, /* XXX: light magenta */ 0xffe0, /* yellow */ 0xffff, /* white */ }; static uint32_t colors_24[16] = { 0x000000,/* Black */ 0x000080,/* Blue */ 0x008000,/* Green */ 0x008080,/* Cyan */ 0x800000,/* Red */ 0x800080,/* Magenta */ 0xcc6600,/* brown */ 0xC0C0C0,/* Silver */ 0x808080,/* Gray */ 0x0000FF,/* Light Blue */ 0x00FF00,/* Light Green */ 0x00FFFF,/* Light Cyan */ 0xFF0000,/* Light Red */ 0xFF00FF,/* Light Magenta */ 0xFFFF00,/* Yellow */ 0xFFFFFF,/* White */ }; #define IPUV3_READ(ipuv3, module, reg) \ bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg)) #define IPUV3_WRITE(ipuv3, module, reg, val) \ bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val)) #define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40) #define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20) #define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000) #define IMX_IPU_DP0 0 #define IMX_IPU_DP1 1 #define CPMEM_CHANNEL(_dp, _ch, _w) \ (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \ CPMEM_WORD_OFFSET(_w)) #define CPMEM_OFFSET(_dp, _ch, _w, _o) \ (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o)) #define IPUV3_DEBUG 100 #ifdef IPUV3_DEBUG #define SUBMOD_DUMP_REG(_sc, _m, _l) \ { \ int i; \ printf("*** " #_m " ***\n"); \ for (i = 0; i <= (_l); i += 4) { \ if ((i % 32) == 0) \ printf("%04x: ", i & 0xffff); \ printf("0x%08x%c", IPUV3_READ((_sc), _m, i), \ ((i + 4) % 32)?' ':'\n'); \ } \ printf("\n"); \ } #endif #ifdef IPUV3_DEBUG int ipuv3_debug = IPUV3_DEBUG; #define DPRINTFN(n,x) if (ipuv3_debug>(n)) printf x; else #else #define DPRINTFN(n,x) #endif static int ipu3_fb_probe(device_t); static int ipu3_fb_attach(device_t); static int ipu3_fb_malloc(struct ipu3sc_softc *sc, size_t size) { sc->vbase = (uint32_t)contigmalloc(size, M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); sc->pbase = vtophys(sc->vbase); return (0); } static void ipu3_fb_init(void *arg) { struct ipu3sc_softc *sc = arg; struct video_adapter_softc *va_sc = &va_softc; uint64_t w0sh96; uint32_t w1sh96; /* FW W0[137:125] - 96 = [41:29] */ /* FH W0[149:138] - 96 = [53:42] */ w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16)); w0sh96 <<= 32; w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12)); va_sc->width = ((w0sh96 >> 29) & 0x1fff) + 1; va_sc->height = ((w0sh96 >> 42) & 0x0fff) + 1; /* SLY W1[115:102] - 96 = [19:6] */ w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12)); va_sc->stride = ((w1sh96 >> 6) & 0x3fff) + 1; printf("%dx%d [%d]\n", va_sc->width, va_sc->height, va_sc->stride); va_sc->fb_size = va_sc->height * va_sc->stride; ipu3_fb_malloc(sc, va_sc->fb_size); /* DP1 + config_ch_23 + word_2 */ IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0), ((sc->pbase >> 3) | ((sc->pbase >> 3) << 29)) & 0xffffffff); IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4), ((sc->pbase >> 3) >> 3) & 0xffffffff); va_sc->fb_addr = (intptr_t)sc->vbase; va_sc->fb_paddr = (intptr_t)sc->pbase; va_sc->bpp = va_sc->stride / va_sc->width; va_sc->depth = va_sc->bpp * 8; } static int ipu3_fb_probe(device_t dev) { int error; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,ipu3")) return (ENXIO); - device_set_desc(dev, "i.MX515 Image Processing Unit (FB)"); + device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)"); error = sc_probe_unit(device_get_unit(dev), device_get_flags(dev) | SC_AUTODETECT_KBD); if (error != 0) return (error); return (BUS_PROBE_DEFAULT); } static int ipu3_fb_attach(device_t dev) { struct ipu3sc_softc *sc = device_get_softc(dev); bus_space_tag_t iot; bus_space_handle_t ioh; + phandle_t node; + pcell_t reg; int err; + uintptr_t base; if (ipu3sc_softc) return (ENXIO); ipu3sc_softc = sc; - device_printf(dev, "\tclock gate status is %d\n", - imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); + if (bootverbose) + device_printf(dev, "clock gate status is %d\n", + imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); sc->dev = dev; err = (sc_attach_unit(device_get_unit(dev), device_get_flags(dev) | SC_AUTODETECT_KBD)); if (err) { device_printf(dev, "failed to attach syscons\n"); goto fail; } sc = device_get_softc(dev); sc->iot = iot = fdtbus_bs_tag; - device_printf(sc->dev, ": i.MX51 IPUV3 controller\n"); - + /* + * Retrieve the device address based on the start address in the + * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register + * address, so we just subtract IPU_CM_BASE to get the offset at which + * the IPU device was memory mapped. + * On i.MX53, the offset is 0. + */ + node = ofw_bus_get_node(dev); + if ((OF_getprop(node, "reg", ®, sizeof(reg))) <= 0) + base = 0; + else + base = fdt32_to_cpu(reg) - IPU_CM_BASE(0); /* map controller registers */ - err = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); if (err) goto fail_retarn_cm; sc->cm_ioh = ioh; /* map Display Multi FIFO Controller registers */ - err = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh); if (err) goto fail_retarn_dmfc; sc->dmfc_ioh = ioh; /* map Display Interface 0 registers */ - err = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh); if (err) goto fail_retarn_di0; sc->di0_ioh = ioh; /* map Display Interface 1 registers */ - err = bus_space_map(iot, IPU_DI1_BASE, IPU_DI0_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh); if (err) goto fail_retarn_di1; sc->di1_ioh = ioh; /* map Display Processor registers */ - err = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh); if (err) goto fail_retarn_dp; sc->dp_ioh = ioh; /* map Display Controller registers */ - err = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh); if (err) goto fail_retarn_dc; sc->dc_ioh = ioh; /* map Image DMA Controller registers */ - err = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0, + &ioh); if (err) goto fail_retarn_idmac; sc->idmac_ioh = ioh; /* map CPMEM registers */ - err = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0, + &ioh); if (err) goto fail_retarn_cpmem; sc->cpmem_ioh = ioh; /* map DCTEMPL registers */ - err = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0, + &ioh); if (err) goto fail_retarn_dctmpl; sc->dctmpl_ioh = ioh; #ifdef notyet sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO, ipuv3intr, sc); if (sc->ih == NULL) { device_printf(sc->dev, "unable to establish interrupt at irq %d\n", IMX51_INT_IPUV3); return (ENXIO); } #endif /* * We have to wait until interrupts are enabled. * Mailbox relies on it to get data from VideoCore */ ipu3_fb_init(sc); return (0); fail: return (ENXIO); fail_retarn_dctmpl: bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE); fail_retarn_cpmem: bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE); fail_retarn_idmac: bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE); fail_retarn_dp: bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE); fail_retarn_dc: bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE); fail_retarn_di1: bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE); fail_retarn_di0: bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE); fail_retarn_dmfc: bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE); fail_retarn_cm: device_printf(sc->dev, "failed to map registers (errno=%d)\n", err); return (err); } static device_method_t ipu3_fb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ipu3_fb_probe), DEVMETHOD(device_attach, ipu3_fb_attach), { 0, 0 } }; static devclass_t ipu3_fb_devclass; static driver_t ipu3_fb_driver = { "fb", ipu3_fb_methods, sizeof(struct ipu3sc_softc), }; DRIVER_MODULE(ipu3fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0); /* * Video driver routines and glue. */ static int ipu3fb_configure(int); static vi_probe_t ipu3fb_probe; static vi_init_t ipu3fb_init; static vi_get_info_t ipu3fb_get_info; static vi_query_mode_t ipu3fb_query_mode; static vi_set_mode_t ipu3fb_set_mode; static vi_save_font_t ipu3fb_save_font; static vi_load_font_t ipu3fb_load_font; static vi_show_font_t ipu3fb_show_font; static vi_save_palette_t ipu3fb_save_palette; static vi_load_palette_t ipu3fb_load_palette; static vi_set_border_t ipu3fb_set_border; static vi_save_state_t ipu3fb_save_state; static vi_load_state_t ipu3fb_load_state; static vi_set_win_org_t ipu3fb_set_win_org; static vi_read_hw_cursor_t ipu3fb_read_hw_cursor; static vi_set_hw_cursor_t ipu3fb_set_hw_cursor; static vi_set_hw_cursor_shape_t ipu3fb_set_hw_cursor_shape; static vi_blank_display_t ipu3fb_blank_display; static vi_mmap_t ipu3fb_mmap; static vi_ioctl_t ipu3fb_ioctl; static vi_clear_t ipu3fb_clear; static vi_fill_rect_t ipu3fb_fill_rect; static vi_bitblt_t ipu3fb_bitblt; static vi_diag_t ipu3fb_diag; static vi_save_cursor_palette_t ipu3fb_save_cursor_palette; static vi_load_cursor_palette_t ipu3fb_load_cursor_palette; static vi_copy_t ipu3fb_copy; static vi_putp_t ipu3fb_putp; static vi_putc_t ipu3fb_putc; static vi_puts_t ipu3fb_puts; static vi_putm_t ipu3fb_putm; static video_switch_t ipu3fbvidsw = { .probe = ipu3fb_probe, .init = ipu3fb_init, .get_info = ipu3fb_get_info, .query_mode = ipu3fb_query_mode, .set_mode = ipu3fb_set_mode, .save_font = ipu3fb_save_font, .load_font = ipu3fb_load_font, .show_font = ipu3fb_show_font, .save_palette = ipu3fb_save_palette, .load_palette = ipu3fb_load_palette, .set_border = ipu3fb_set_border, .save_state = ipu3fb_save_state, .load_state = ipu3fb_load_state, .set_win_org = ipu3fb_set_win_org, .read_hw_cursor = ipu3fb_read_hw_cursor, .set_hw_cursor = ipu3fb_set_hw_cursor, .set_hw_cursor_shape = ipu3fb_set_hw_cursor_shape, .blank_display = ipu3fb_blank_display, .mmap = ipu3fb_mmap, .ioctl = ipu3fb_ioctl, .clear = ipu3fb_clear, .fill_rect = ipu3fb_fill_rect, .bitblt = ipu3fb_bitblt, .diag = ipu3fb_diag, .save_cursor_palette = ipu3fb_save_cursor_palette, .load_cursor_palette = ipu3fb_load_cursor_palette, .copy = ipu3fb_copy, .putp = ipu3fb_putp, .putc = ipu3fb_putc, .puts = ipu3fb_puts, .putm = ipu3fb_putm, }; VIDEO_DRIVER(ipu3fb, ipu3fbvidsw, ipu3fb_configure); extern sc_rndr_sw_t txtrndrsw; RENDERER(ipu3fb, 0, txtrndrsw, gfb_set); RENDERER_MODULE(ipu3fb, gfb_set); static uint16_t ipu3fb_static_window[ROW*COL]; extern u_char dflt_font_16[]; static int ipu3fb_configure(int flags) { struct video_adapter_softc *sc; sc = &va_softc; if (sc->initialized) return 0; sc->width = 640; sc->height = 480; sc->bpp = 2; sc->stride = sc->width * sc->bpp; ipu3fb_init(0, &sc->va, 0); sc->initialized = 1; return (0); } static int ipu3fb_probe(int unit, video_adapter_t **adp, void *arg, int flags) { return (0); } static int ipu3fb_init(int unit, video_adapter_t *adp, int flags) { struct video_adapter_softc *sc; video_info_t *vi; sc = (struct video_adapter_softc *)adp; vi = &adp->va_info; vid_init_struct(adp, "ipu3fb", -1, unit); sc->font = dflt_font_16; vi->vi_cheight = IPU3FB_FONT_HEIGHT; vi->vi_cwidth = 8; vi->vi_width = sc->width/8; vi->vi_height = sc->height/vi->vi_cheight; /* * Clamp width/height to syscons maximums */ if (vi->vi_width > COL) vi->vi_width = COL; if (vi->vi_height > ROW) vi->vi_height = ROW; sc->xmargin = (sc->width - (vi->vi_width * vi->vi_cwidth)) / 2; sc->ymargin = (sc->height - (vi->vi_height * vi->vi_cheight))/2; adp->va_window = (vm_offset_t) ipu3fb_static_window; adp->va_flags |= V_ADP_FONT /* | V_ADP_COLOR | V_ADP_MODECHANGE */; adp->va_line_width = sc->stride; adp->va_buffer_size = sc->fb_size; vid_register(&sc->va); return (0); } static int ipu3fb_get_info(video_adapter_t *adp, int mode, video_info_t *info) { bcopy(&adp->va_info, info, sizeof(*info)); return (0); } static int ipu3fb_query_mode(video_adapter_t *adp, video_info_t *info) { return (0); } static int ipu3fb_set_mode(video_adapter_t *adp, int mode) { return (0); } static int ipu3fb_save_font(video_adapter_t *adp, int page, int size, int width, u_char *data, int c, int count) { return (0); } static int ipu3fb_load_font(video_adapter_t *adp, int page, int size, int width, u_char *data, int c, int count) { struct video_adapter_softc *sc; sc = (struct video_adapter_softc *)adp; sc->font = data; return (0); } static int ipu3fb_show_font(video_adapter_t *adp, int page) { return (0); } static int ipu3fb_save_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int ipu3fb_load_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int ipu3fb_set_border(video_adapter_t *adp, int border) { return (ipu3fb_blank_display(adp, border)); } static int ipu3fb_save_state(video_adapter_t *adp, void *p, size_t size) { return (0); } static int ipu3fb_load_state(video_adapter_t *adp, void *p) { return (0); } static int ipu3fb_set_win_org(video_adapter_t *adp, off_t offset) { return (0); } static int ipu3fb_read_hw_cursor(video_adapter_t *adp, int *col, int *row) { *col = *row = 0; return (0); } static int ipu3fb_set_hw_cursor(video_adapter_t *adp, int col, int row) { return (0); } static int ipu3fb_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, int celsize, int blink) { return (0); } static int ipu3fb_blank_display(video_adapter_t *adp, int mode) { return (0); } static int ipu3fb_mmap(video_adapter_t *adp, vm_ooffset_t offset, vm_paddr_t *paddr, int prot, vm_memattr_t *memattr) { struct video_adapter_softc *sc; sc = (struct video_adapter_softc *)adp; /* * This might be a legacy VGA mem request: if so, just point it at the * framebuffer, since it shouldn't be touched */ if (offset < sc->stride * sc->height) { *paddr = sc->fb_paddr + offset; return (0); } return (EINVAL); } static int ipu3fb_ioctl(video_adapter_t *adp, u_long cmd, caddr_t data) { struct video_adapter_softc *sc; struct fbtype *fb; sc = (struct video_adapter_softc *)adp; switch (cmd) { case FBIOGTYPE: fb = (struct fbtype *)data; fb->fb_type = FBTYPE_PCIMISC; fb->fb_height = sc->height; fb->fb_width = sc->width; fb->fb_depth = sc->depth; if (sc->depth <= 1 || sc->depth > 8) fb->fb_cmsize = 0; else fb->fb_cmsize = 1 << sc->depth; fb->fb_size = sc->fb_size; break; case FBIOSCURSOR: return (ENODEV); default: return (fb_commonioctl(adp, cmd, data)); } return (0); } static int ipu3fb_clear(video_adapter_t *adp) { return (ipu3fb_blank_display(adp, 0)); } static int ipu3fb_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) { return (0); } static int ipu3fb_bitblt(video_adapter_t *adp, ...) { return (0); } static int ipu3fb_diag(video_adapter_t *adp, int level) { return (0); } static int ipu3fb_save_cursor_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int ipu3fb_load_cursor_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int ipu3fb_copy(video_adapter_t *adp, vm_offset_t src, vm_offset_t dst, int n) { return (0); } static int ipu3fb_putp(video_adapter_t *adp, vm_offset_t off, uint32_t p, uint32_t a, int size, int bpp, int bit_ltor, int byte_ltor) { return (0); } static int ipu3fb_putc(video_adapter_t *adp, vm_offset_t off, uint8_t c, uint8_t a) { struct video_adapter_softc *sc; int col, row, bpp; int b, i, j, k; uint8_t *addr; u_char *p; uint32_t fg, bg, color; sc = (struct video_adapter_softc *)adp; bpp = sc->bpp; if (sc->fb_addr == 0) return (0); row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight; col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth; p = sc->font + c * IPU3FB_FONT_HEIGHT; addr = (uint8_t *)sc->fb_addr + (row + sc->ymargin) * (sc->stride) + bpp * (col + sc->xmargin); if (bpp == 2) { bg = colors[(a >> 4) & 0x0f]; fg = colors[a & 0x0f]; } else if (bpp == 3) { bg = colors_24[(a >> 4) & 0x0f]; fg = colors_24[a & 0x0f]; } else { return (ENXIO); } for (i = 0; i < IPU3FB_FONT_HEIGHT; i++) { for (j = 0, k = 7; j < 8; j++, k--) { if ((p[i] & (1 << k)) == 0) color = bg; else color = fg; /* FIXME: BPP maybe different */ for (b = 0; b < bpp; b ++) addr[bpp * j + b] = (color >> (b << 3)) & 0xff; } addr += (sc->stride); } return (0); } static int ipu3fb_puts(video_adapter_t *adp, vm_offset_t off, u_int16_t *s, int len) { int i; for (i = 0; i < len; i++) ipu3fb_putc(adp, off + i, s[i] & 0xff, (s[i] & 0xff00) >> 8); return (0); } static int ipu3fb_putm(video_adapter_t *adp, int x, int y, uint8_t *pixel_image, uint32_t pixel_mask, int size, int width) { return (0); } /* * Define a stub keyboard driver in case one hasn't been * compiled into the kernel */ #include #include static int dummy_kbd_configure(int flags); keyboard_switch_t ipu3dummysw; static int dummy_kbd_configure(int flags) { return (0); } KEYBOARD_DRIVER(ipu3dummy, ipu3dummysw, dummy_kbd_configure); Index: head/sys/arm/freescale/imx/imx51_ipuv3_fbd.c =================================================================== --- head/sys/arm/freescale/imx/imx51_ipuv3_fbd.c (revision 264250) +++ head/sys/arm/freescale/imx/imx51_ipuv3_fbd.c (revision 264251) @@ -1,349 +1,366 @@ /*- * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2012, 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "fb_if.h" #define IMX51_IPU_HSP_CLOCK 665000000 struct ipu3sc_softc { device_t dev; device_t sc_fbd; /* fbd child */ struct fb_info sc_info; bus_space_tag_t iot; bus_space_handle_t ioh; bus_space_handle_t cm_ioh; bus_space_handle_t dp_ioh; bus_space_handle_t di0_ioh; bus_space_handle_t di1_ioh; bus_space_handle_t dctmpl_ioh; bus_space_handle_t dc_ioh; bus_space_handle_t dmfc_ioh; bus_space_handle_t idmac_ioh; bus_space_handle_t cpmem_ioh; }; static struct ipu3sc_softc *ipu3sc_softc; #define IPUV3_READ(ipuv3, module, reg) \ bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg)) #define IPUV3_WRITE(ipuv3, module, reg, val) \ bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val)) #define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40) #define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20) #define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000) #define IMX_IPU_DP0 0 #define IMX_IPU_DP1 1 #define CPMEM_CHANNEL(_dp, _ch, _w) \ (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \ CPMEM_WORD_OFFSET(_w)) #define CPMEM_OFFSET(_dp, _ch, _w, _o) \ (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o)) static int ipu3_fb_probe(device_t); static int ipu3_fb_attach(device_t); static void ipu3_fb_init(struct ipu3sc_softc *sc) { uint64_t w0sh96; uint32_t w1sh96; /* FW W0[137:125] - 96 = [41:29] */ /* FH W0[149:138] - 96 = [53:42] */ w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16)); w0sh96 <<= 32; w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12)); sc->sc_info.fb_width = ((w0sh96 >> 29) & 0x1fff) + 1; sc->sc_info.fb_height = ((w0sh96 >> 42) & 0x0fff) + 1; /* SLY W1[115:102] - 96 = [19:6] */ w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12)); sc->sc_info.fb_stride = ((w1sh96 >> 6) & 0x3fff) + 1; printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, sc->sc_info.fb_stride); sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); /* DP1 + config_ch_23 + word_2 */ IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0), (((uint32_t)sc->sc_info.fb_pbase >> 3) | (((uint32_t)sc->sc_info.fb_pbase >> 3) << 29)) & 0xffffffff); IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4), (((uint32_t)sc->sc_info.fb_pbase >> 3) >> 3) & 0xffffffff); /* XXX: fetch or set it from/to IPU. */ sc->sc_info.fb_bpp = sc->sc_info.fb_depth = sc->sc_info.fb_stride / sc->sc_info.fb_width * 8; } /* Use own color map, because of different RGB offset. */ static int ipu3_fb_init_cmap(uint32_t *cmap, int bytespp) { switch (bytespp) { case 8: return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB, 0x7, 5, 0x7, 2, 0x3, 0)); case 15: return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB, 0x1f, 10, 0x1f, 5, 0x1f, 0)); case 16: return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB, 0x1f, 11, 0x3f, 5, 0x1f, 0)); case 24: case 32: /* Ignore alpha. */ return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB, 0xff, 16, 0xff, 8, 0xff, 0)); default: return (1); } } static int ipu3_fb_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,ipu3")) return (ENXIO); - device_set_desc(dev, "i.MX515 Image Processing Unit (FB)"); + device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)"); return (BUS_PROBE_DEFAULT); } static int ipu3_fb_attach(device_t dev) { struct ipu3sc_softc *sc = device_get_softc(dev); bus_space_tag_t iot; bus_space_handle_t ioh; - int err; + phandle_t node; + pcell_t reg; + int err; + uintptr_t base; ipu3sc_softc = sc; - device_printf(dev, "\tclock gate status is %d\n", - imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); + if (bootverbose) + device_printf(dev, "clock gate status is %d\n", + imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); sc->dev = dev; sc = device_get_softc(dev); sc->iot = iot = fdtbus_bs_tag; - device_printf(sc->dev, ": i.MX51 IPUV3 controller\n"); - + /* + * Retrieve the device address based on the start address in the + * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register + * address, so we just subtract IPU_CM_BASE to get the offset at which + * the IPU device was memory mapped. + * On i.MX53, the offset is 0. + */ + node = ofw_bus_get_node(dev); + if ((OF_getprop(node, "reg", ®, sizeof(reg))) <= 0) + base = 0; + else + base = fdt32_to_cpu(reg) - IPU_CM_BASE(0); /* map controller registers */ - err = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); if (err) goto fail_retarn_cm; sc->cm_ioh = ioh; /* map Display Multi FIFO Controller registers */ - err = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh); if (err) goto fail_retarn_dmfc; sc->dmfc_ioh = ioh; /* map Display Interface 0 registers */ - err = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh); if (err) goto fail_retarn_di0; sc->di0_ioh = ioh; /* map Display Interface 1 registers */ - err = bus_space_map(iot, IPU_DI1_BASE, IPU_DI0_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh); if (err) goto fail_retarn_di1; sc->di1_ioh = ioh; /* map Display Processor registers */ - err = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh); if (err) goto fail_retarn_dp; sc->dp_ioh = ioh; /* map Display Controller registers */ - err = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh); if (err) goto fail_retarn_dc; sc->dc_ioh = ioh; /* map Image DMA Controller registers */ - err = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0, + &ioh); if (err) goto fail_retarn_idmac; sc->idmac_ioh = ioh; /* map CPMEM registers */ - err = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0, + &ioh); if (err) goto fail_retarn_cpmem; sc->cpmem_ioh = ioh; /* map DCTEMPL registers */ - err = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh); + err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0, + &ioh); if (err) goto fail_retarn_dctmpl; sc->dctmpl_ioh = ioh; #ifdef notyet sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO, ipuv3intr, sc); if (sc->ih == NULL) { device_printf(sc->dev, "unable to establish interrupt at irq %d\n", IMX51_INT_IPUV3); return (ENXIO); } #endif /* * We have to wait until interrupts are enabled. * Mailbox relies on it to get data from VideoCore */ ipu3_fb_init(sc); sc->sc_info.fb_name = device_get_nameunit(dev); ipu3_fb_init_cmap(sc->sc_info.fb_cmap, sc->sc_info.fb_depth); sc->sc_info.fb_cmsize = 16; /* Ask newbus to attach framebuffer device to me. */ sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); if (sc->sc_fbd == NULL) device_printf(dev, "Can't attach fbd device\n"); return (bus_generic_attach(dev)); fail_retarn_dctmpl: bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE); fail_retarn_cpmem: bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE); fail_retarn_idmac: bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE); fail_retarn_dp: bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE); fail_retarn_dc: bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE); fail_retarn_di1: bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE); fail_retarn_di0: bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE); fail_retarn_dmfc: bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE); fail_retarn_cm: device_printf(sc->dev, "failed to map registers (errno=%d)\n", err); return (err); } static struct fb_info * ipu3_fb_getinfo(device_t dev) { struct ipu3sc_softc *sc = device_get_softc(dev); return (&sc->sc_info); } static device_method_t ipu3_fb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ipu3_fb_probe), DEVMETHOD(device_attach, ipu3_fb_attach), /* Framebuffer service methods */ DEVMETHOD(fb_getinfo, ipu3_fb_getinfo), { 0, 0 } }; static devclass_t ipu3_fb_devclass; static driver_t ipu3_fb_driver = { "fb", ipu3_fb_methods, sizeof(struct ipu3sc_softc), }; DRIVER_MODULE(fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0); Index: head/sys/arm/freescale/imx/imx51_ipuv3reg.h =================================================================== --- head/sys/arm/freescale/imx/imx51_ipuv3reg.h (revision 264250) +++ head/sys/arm/freescale/imx/imx51_ipuv3reg.h (revision 264251) @@ -1,919 +1,922 @@ /* $NetBSD: imx51_ipuv3reg.h,v 1.1 2012/04/17 10:19:57 bsh Exp $ */ /* * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. * Written by Hashimoto Kenichi for Genetec Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 2012, 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _ARM_IMX_IMX51_IPUV3REG_H #define _ARM_IMX_IMX51_IPUV3REG_H /* register offset address */ /* * CM * Control Module */ #define IPU_CM_CONF 0x00000000 #define CM_CONF_CSI_SEL 0x80000000 #define CM_CONF_IC_INPUT 0x40000000 #define CM_CONF_CSI1_DATA_SOURCE 0x20000000 #define CM_CONF_CSI0_DATA_SOURCE 0x10000000 #define CM_CONF_VDI_DMFC_SYNC 0x08000000 #define CM_CONF_IC_DMFC_SYNC 0x04000000 #define CM_CONF_IC_DMFC_SEL 0x02000000 #define CM_CONF_ISP_DOUBLE_FLOW 0x01000000 #define CM_CONF_IDMAC_DISABLE 0x00400000 #define CM_CONF_IPU_DIAGBUS_ON 0x00200000 #define CM_CONF_IPU_DIAGBUS_MODE 0x001f0000 #define CM_CONF_VDI_EN 0x00001000 #define CM_CONF_SISG_EN 0x00000800 #define CM_CONF_DMFC_EN 0x00000400 #define CM_CONF_DC_EN 0x00000200 #define CM_CONF_SMFC_EN 0x00000100 #define CM_CONF_DI1_EN 0x00000080 #define CM_CONF_DI0_EN 0x00000040 #define CM_CONF_DP_EN 0x00000020 #define CM_CONF_ISP_EN 0x00000010 #define CM_CONF_IRT_EN 0x00000008 #define CM_CONF_IC_EN 0x00000004 #define CM_CONF_CSI1_EN 0x00000002 #define CM_CONF_CSI0_EN 0x00000001 #define IPU_SISG_CTRL0 0x00000004 #define IPU_SISG_CTRL1 0x00000008 #define IPU_CM_INT_CTRL_1 0x0000003c #define IPU_CM_INT_CTRL_2 0x00000040 #define IPU_CM_INT_CTRL_3 0x00000044 #define IPU_CM_INT_CTRL_4 0x00000048 #define IPU_CM_INT_CTRL_5 0x0000004c #define IPU_CM_INT_CTRL_6 0x00000050 #define IPU_CM_INT_CTRL_7 0x00000054 #define IPU_CM_INT_CTRL_8 0x00000058 #define IPU_CM_INT_CTRL_9 0x0000005c #define IPU_CM_INT_CTRL_10 0x00000060 #define IPU_CM_INT_CTRL_11 0x00000064 #define IPU_CM_INT_CTRL_12 0x00000068 #define IPU_CM_INT_CTRL_13 0x0000006c #define IPU_CM_INT_CTRL_14 0x00000070 #define IPU_CM_INT_CTRL_15 0x00000074 #define IPU_CM_SDMA_EVENT_1 0x00000078 #define IPU_CM_SDMA_EVENT_2 0x0000007c #define IPU_CM_SDMA_EVENT_3 0x00000080 #define IPU_CM_SDMA_EVENT_4 0x00000084 #define IPU_CM_SDMA_EVENT_7 0x00000088 #define IPU_CM_SDMA_EVENT_8 0x0000008c #define IPU_CM_SDMA_EVENT_11 0x00000090 #define IPU_CM_SDMA_EVENT_12 0x00000094 #define IPU_CM_SDMA_EVENT_13 0x00000098 #define IPU_CM_SDMA_EVENT_14 0x0000009c #define IPU_CM_SRM_PRI1 0x000000a0 #define IPU_CM_SRM_PRI2 0x000000a4 #define IPU_CM_FS_PROC_FLOW1 0x000000a8 #define IPU_CM_FS_PROC_FLOW2 0x000000ac #define IPU_CM_FS_PROC_FLOW3 0x000000b0 #define IPU_CM_FS_DISP_FLOW1 0x000000b4 #define IPU_CM_FS_DISP_FLOW2 0x000000b8 #define IPU_CM_SKIP 0x000000bc #define IPU_CM_DISP_ALT_CONF 0x000000c0 #define IPU_CM_DISP_GEN 0x000000c4 #define CM_DISP_GEN_DI0_COUNTER_RELEASE 0x01000000 #define CM_DISP_GEN_DI1_COUNTER_RELEASE 0x00800000 #define CM_DISP_GEN_MCU_MAX_BURST_STOP 0x00400000 #define CM_DISP_GEN_MCU_T_SHIFT 18 #define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT) #define IPU_CM_DISP_ALT1 0x000000c8 #define IPU_CM_DISP_ALT2 0x000000cc #define IPU_CM_DISP_ALT3 0x000000d0 #define IPU_CM_DISP_ALT4 0x000000d4 #define IPU_CM_SNOOP 0x000000d8 #define IPU_CM_MEM_RST 0x000000dc #define CM_MEM_START 0x80000000 #define CM_MEM_EN 0x007fffff #define IPU_CM_PM 0x000000e0 #define IPU_CM_GPR 0x000000e4 #define CM_GPR_IPU_CH_BUF1_RDY1_CLR 0x80000000 #define CM_GPR_IPU_CH_BUF1_RDY0_CLR 0x40000000 #define CM_GPR_IPU_CH_BUF0_RDY1_CLR 0x20000000 #define CM_GPR_IPU_CH_BUF0_RDY0_CLR 0x10000000 #define CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR 0x08000000 #define CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR 0x04000000 #define CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR 0x02000000 #define CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR 0x01000000 #define CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS 0x00800000 #define CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS 0x00400000 #define CM_GPR_IPU_CH_BUF2_RDY1_CLR 0x00200000 #define CM_GPR_IPU_CH_BUF2_RDY0_CLR 0x00100000 #define CM_GPR_IPU_GP(n) __BIT((n)) #define IPU_CM_CH_DB_MODE_SEL_0 0x00000150 #define IPU_CM_CH_DB_MODE_SEL_1 0x00000154 #define IPU_CM_ALT_CH_DB_MODE_SEL_0 0x00000168 #define IPU_CM_ALT_CH_DB_MODE_SEL_1 0x0000016c #define IPU_CM_CH_TRB_MODE_SEL_0 0x00000178 #define IPU_CM_CH_TRB_MODE_SEL_1 0x0000017c #define IPU_CM_INT_STAT_1 0x00000200 #define IPU_CM_INT_STAT_2 0x00000204 #define IPU_CM_INT_STAT_3 0x00000208 #define IPU_CM_INT_STAT_4 0x0000020c #define IPU_CM_INT_STAT_5 0x00000210 #define IPU_CM_INT_STAT_6 0x00000214 #define IPU_CM_INT_STAT_7 0x00000218 #define IPU_CM_INT_STAT_8 0x0000021c #define IPU_CM_INT_STAT_9 0x00000220 #define IPU_CM_INT_STAT_10 0x00000224 #define IPU_CM_INT_STAT_11 0x00000228 #define IPU_CM_INT_STAT_12 0x0000022c #define IPU_CM_INT_STAT_13 0x00000230 #define IPU_CM_INT_STAT_14 0x00000234 #define IPU_CM_INT_STAT_15 0x00000238 #define IPU_CM_CUR_BUF_0 0x0000023c #define IPU_CM_CUR_BUF_1 0x00000240 #define IPU_CM_ALT_CUR_BUF_0 0x00000244 #define IPU_CM_ALT_CUR_BUF_1 0x00000248 #define IPU_CM_SRM_STAT 0x0000024c #define IPU_CM_PROC_TASKS_STAT 0x00000250 #define IPU_CM_DISP_TASKS_STAT 0x00000254 #define IPU_CM_TRIPLE_CUR_BUF_0 0x00000258 #define IPU_CM_TRIPLE_CUR_BUF_1 0x0000025c #define IPU_CM_TRIPLE_CUR_BUF_2 0x00000260 #define IPU_CM_TRIPLE_CUR_BUF_3 0x00000264 #define IPU_CM_CH_BUF0_RDY0 0x00000268 #define IPU_CM_CH_BUF0_RDY1 0x0000026c #define IPU_CM_CH_BUF1_RDY0 0x00000270 #define IPU_CM_CH_BUF1_RDY1 0x00000274 #define IPU_CM_ALT_CH_BUF0_RDY0 0x00000278 #define IPU_CM_ALT_CH_BUF0_RDY1 0x0000027c #define IPU_CM_ALT_CH_BUF1_RDY0 0x00000280 #define IPU_CM_ALT_CH_BUF1_RDY1 0x00000284 #define IPU_CM_CH_BUF2_RDY0 0x00000288 #define IPU_CM_CH_BUF2_RDY1 0x0000028c /* * IDMAC * Image DMA Controller */ #define IPU_IDMAC_CONF 0x00000000 #define IPU_IDMAC_CH_EN_1 0x00000004 #define IPU_IDMAC_CH_EN_2 0x00000008 #define IPU_IDMAC_SEP_ALPHA 0x0000000c #define IPU_IDMAC_ALT_SEP_ALPHA 0x00000010 #define IPU_IDMAC_CH_PRI_1 0x00000014 #define IPU_IDMAC_CH_PRI_2 0x00000018 #define IPU_IDMAC_WM_EN_1 0x0000001c #define IPU_IDMAC_WM_EN_2 0x00000020 #define IPU_IDMAC_LOCK_EN_1 0x00000024 #define IPU_IDMAC_LOCK_EN_2 0x00000028 #define IPU_IDMAC_SUB_ADDR_0 0x0000002c #define IPU_IDMAC_SUB_ADDR_1 0x00000030 #define IPU_IDMAC_SUB_ADDR_2 0x00000034 #define IPU_IDMAC_SUB_ADDR_3 0x00000038 #define IPU_IDMAC_SUB_ADDR_4 0x0000003c #define IPU_IDMAC_BNDM_EN_1 0x00000040 #define IPU_IDMAC_BNDM_EN_2 0x00000044 #define IPU_IDMAC_SC_CORD 0x00000048 #define IPU_IDMAC_SC_CORD1 0x0000004c #define IPU_IDMAC_CH_BUSY_1 0x00000100 #define IPU_IDMAC_CH_BUSY_2 0x00000104 #define CH_PANNEL_BG 23 #define CH_PANNEL_FG 27 /* * DP * Display Port */ #define IPU_DP_DEBUG_CNT 0x000000bc #define IPU_DP_DEBUG_STAT 0x000000c0 /* * IC * Image Converter */ #define IPU_IC_CONF 0x00000000 #define IPU_IC_PRP_ENC_RSC 0x00000004 #define IPU_IC_PRP_VF_RSC 0x00000008 #define IPU_IC_PP_RSC 0x0000000c #define IPU_IC_CMBP_1 0x00000010 #define IPU_IC_CMBP_2 0x00000014 #define IPU_IC_IDMAC_1 0x00000018 #define IPU_IC_IDMAC_2 0x0000001c #define IPU_IC_IDMAC_3 0x00000020 #define IPU_IC_IDMAC_4 0x00000024 /* * CSI * Camera Sensor Interface */ #define IPU_CSI0_SENS_CONF 0x00000000 #define IPU_CSI0_SENS_FRM_SIZE 0x00000004 #define IPU_CSI0_ACT_FRM_SIZE 0x00000008 #define IPU_CSI0_OUT_FRM_CTRL 0x0000000c #define IPU_CSI0_TST_CTRL 0x00000010 #define IPU_CSI0_CCIR_CODE_1 0x00000014 #define IPU_CSI0_CCIR_CODE_2 0x00000018 #define IPU_CSI0_CCIR_CODE_3 0x0000001c #define IPU_CSI0_DI 0x00000020 #define IPU_CSI0_SKIP 0x00000024 #define IPU_CSI0_CPD_CTRL 0x00000028 #define IPU_CSI0_CPD_OFFSET1 0x000000ec #define IPU_CSI0_CPD_OFFSET2 0x000000f0 #define IPU_CSI1_SENS_CONF 0x00000000 #define IPU_CSI1_SENS_FRM_SIZE 0x00000004 #define IPU_CSI1_ACT_FRM_SIZE 0x00000008 #define IPU_CSI1_OUT_FRM_CTRL 0x0000000c #define IPU_CSI1_TST_CTRL 0x00000010 #define IPU_CSI1_CCIR_CODE_1 0x00000014 #define IPU_CSI1_CCIR_CODE_2 0x00000018 #define IPU_CSI1_CCIR_CODE_3 0x0000001c #define IPU_CSI1_DI 0x00000020 #define IPU_CSI1_SKIP 0x00000024 #define IPU_CSI1_CPD_CTRL 0x00000028 #define IPU_CSI1_CPD_OFFSET1 0x000000ec #define IPU_CSI1_CPD_OFFSET2 0x000000f0 /* * DI * Display Interface */ #define IPU_DI_GENERAL 0x00000000 #define DI_GENERAL_DISP_Y_SEL 0x70000000 #define DI_GENERAL_CLOCK_STOP_MODE 0x0f000000 #define DI_GENERAL_DISP_CLOCK_INIT 0x00800000 #define DI_GENERAL_MASK_SEL 0x00400000 #define DI_GENERAL_VSYNC_EXT 0x00200000 #define DI_GENERAL_CLK_EXT 0x00100000 #define DI_GENERAL_WATCHDOG_MODE 0x000c0000 #define DI_GENERAL_POLARITY_DISP_CLK 0x00020000 #define DI_GENERAL_SYNC_COUNT_SEL 0x0000f000 #define DI_GENERAL_ERR_TREATMENT 0x00000800 #define DI_GENERAL_ERM_VSYNC_SEL 0x00000400 #define DI_GENERAL_POLARITY_CS(n) (1 << ((n) + 8)) #define DI_GENERAL_POLARITY(n) (1 << ((n) - 1)) #define IPU_DI_BS_CLKGEN0 0x00000004 #define DI_BS_CLKGEN0_OFFSET_SHIFT 16 #define IPU_DI_BS_CLKGEN1 0x00000008 #define DI_BS_CLKGEN1_DOWN_SHIFT 16 #define DI_BS_CLKGEN1_UP_SHIFT 0 #define IPU_DI_SW_GEN0(n) (0x0000000c + ((n) - 1) * 4) #define DI_SW_GEN0_RUN_VAL 0x7ff80000 #define DI_SW_GEN0_RUN_RESOL 0x00070000 #define DI_SW_GEN0_OFFSET_VAL 0x00007ff8 #define DI_SW_GEN0_OFFSET_RESOL 0x00000007 #define __DI_SW_GEN0(run_val, run_resol, offset_val, offset_resol) \ (((run_val) << 19) | ((run_resol) << 16) | \ ((offset_val) << 3) | (offset_resol)) #define IPU_DI_SW_GEN1(n) (0x00000030 + ((n) - 1) * 4) #define DI_SW_GEN1_CNT_POL_GEN_EN 0x60000000 #define DI_SW_GEN1_CNT_AUTO_RELOAD 0x10000000 #define DI_SW_GEN1_CNT_CLR_SEL 0x0e000000 #define DI_SW_GEN1_CNT_DOWN 0x01ff0000 #define DI_SW_GEN1_CNT_POL_TRIG_SEL 0x00007000 #define DI_SW_GEN1_CNT_POL_CLR_SEL 0x00000e00 #define DI_SW_GEN1_CNT_UP 0x000001ff #define __DI_SW_GEN1(pol_gen_en, auto_reload, clr_sel, down, pol_trig_sel, pol_clr_sel, up) \ (((pol_gen_en) << 29) | ((auto_reload) << 28) | \ ((clr_sel) << 25) | \ ((down) << 16) | ((pol_trig_sel) << 12) | \ ((pol_clr_sel) << 9) | (up)) #define IPU_DI_SYNC_AS_GEN 0x00000054 #define DI_SYNC_AS_GEN_SYNC_START_EN 0x10000000 #define DI_SYNC_AS_GEN_VSYNC_SEL 0x0000e000 #define DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT 13 #define DI_SYNC_AS_GEN_SYNC_STAR 0x00000fff #define IPU_DI_DW_GEN(n) (0x00000058 + (n) * 4) #define DI_DW_GEN_ACCESS_SIZE_SHIFT 24 #define DI_DW_GEN_COMPONNENT_SIZE_SHIFT 16 #define DI_DW_GEN_PIN_SHIFT(n) (((n) - 11) * 2) #define DI_DW_GEN_PIN(n) __BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \ DI_DW_GEN_PIN_SHIFT(n)) #define IPU_DI_DW_SET(n, m) (0x00000088 + (n) * 4 + (m) * 0x30) #define DI_DW_SET_DOWN_SHIFT 16 #define DI_DW_SET_UP_SHIFT 0 #define IPU_DI_STP_REP(n) (0x00000148 + ((n - 1) / 2) * 4) #define DI_STP_REP_SHIFT(n) (((n - 1) % 2) * 16) #define DI_STP_REP_MASK(n) (0x00000fff << DI_STP_REP_SHIFT((n))) #define IPU_DI_SER_CONF 0x0000015c #define IPU_DI_SSC 0x00000160 #define IPU_DI_POL 0x00000164 #define DI_POL_DRDY_POLARITY_17 0x00000040 #define DI_POL_DRDY_POLARITY_16 0x00000020 #define DI_POL_DRDY_POLARITY_15 0x00000010 #define DI_POL_DRDY_POLARITY_14 0x00000008 #define DI_POL_DRDY_POLARITY_13 0x00000004 #define DI_POL_DRDY_POLARITY_12 0x00000002 #define DI_POL_DRDY_POLARITY_11 0x00000001 #define IPU_DI_AW0 0x00000168 #define IPU_DI_AW1 0x0000016c #define IPU_DI_SCR_CONF 0x00000170 #define IPU_DI_STAT 0x00000174 /* * SMFC * Sensor Multi FIFO Controller */ #define IPU_SMFC_MAP 0x00000000 #define IPU_SMFC_WMC 0x00000004 #define IPU_SMFC_BS 0x00000008 /* * DC * Display Controller */ #define IPU_DC_READ_CH_CONF 0x00000000 #define IPU_DC_READ_CH_ADDR 0x00000004 #define IPU_DC_RL0_CH_0 0x00000008 #define IPU_DC_RL1_CH_0 0x0000000c #define IPU_DC_RL2_CH_0 0x00000010 #define IPU_DC_RL3_CH_0 0x00000014 #define IPU_DC_RL4_CH_0 0x00000018 #define IPU_DC_WR_CH_CONF_1 0x0000001c #define IPU_DC_WR_CH_ADDR_1 0x00000020 #define IPU_DC_RL0_CH_1 0x00000024 #define IPU_DC_RL1_CH_1 0x00000028 #define IPU_DC_RL2_CH_1 0x0000002c #define IPU_DC_RL3_CH_1 0x00000030 #define IPU_DC_RL4_CH_1 0x00000034 #define IPU_DC_WR_CH_CONF_2 0x00000038 #define IPU_DC_WR_CH_ADDR_2 0x0000003c #define IPU_DC_RL0_CH_2 0x00000040 #define IPU_DC_RL1_CH_2 0x00000044 #define IPU_DC_RL2_CH_2 0x00000048 #define IPU_DC_RL3_CH_2 0x0000004c #define IPU_DC_RL4_CH_2 0x00000050 #define IPU_DC_CMD_CH_CONF_3 0x00000054 #define IPU_DC_CMD_CH_CONF_4 0x00000058 #define IPU_DC_WR_CH_CONF_5 0x0000005c #define IPU_DC_WR_CH_ADDR_5 0x00000060 #define IPU_DC_RL0_CH_5 0x00000064 #define IPU_DC_RL1_CH_5 0x00000068 #define IPU_DC_RL2_CH_5 0x0000006c #define IPU_DC_RL3_CH_5 0x00000070 #define IPU_DC_RL4_CH_5 0x00000074 #define IPU_DC_WR_CH_CONF_6 0x00000078 #define IPU_DC_WR_CH_ADDR_6 0x0000007c #define IPU_DC_RL0_CH_6 0x00000080 #define IPU_DC_RL1_CH_6 0x00000084 #define IPU_DC_RL2_CH_6 0x00000088 #define IPU_DC_RL3_CH_6 0x0000008c #define IPU_DC_RL4_CH_6 0x00000090 #define IPU_DC_WR_CH_CONF1_8 0x00000094 #define IPU_DC_WR_CH_CONF2_8 0x00000098 #define IPU_DC_RL1_CH_8 0x0000009c #define IPU_DC_RL2_CH_8 0x000000a0 #define IPU_DC_RL3_CH_8 0x000000a4 #define IPU_DC_RL4_CH_8 0x000000a8 #define IPU_DC_RL5_CH_8 0x000000ac #define IPU_DC_RL6_CH_8 0x000000b0 #define IPU_DC_WR_CH_CONF1_9 0x000000b4 #define IPU_DC_WR_CH_CONF2_9 0x000000b8 #define IPU_DC_RL1_CH_9 0x000000bc #define IPU_DC_RL2_CH_9 0x000000c0 #define IPU_DC_RL3_CH_9 0x000000c4 #define IPU_DC_RL4_CH_9 0x000000c8 #define IPU_DC_RL5_CH_9 0x000000cc #define IPU_DC_RL6_CH_9 0x000000d0 #define IPU_DC_RL(chan_base, evt) ((chan_base) + (evt / 2) *0x4) #define DC_RL_CH_0 IPU_DC_RL0_CH_0 #define DC_RL_CH_1 IPU_DC_RL0_CH_1 #define DC_RL_CH_2 IPU_DC_RL0_CH_2 #define DC_RL_CH_5 IPU_DC_RL0_CH_5 #define DC_RL_CH_6 IPU_DC_RL0_CH_6 #define DC_RL_CH_8 IPU_DC_RL0_CH_8 #define DC_RL_EVT_NF 0 #define DC_RL_EVT_NL 1 #define DC_RL_EVT_EOF 2 #define DC_RL_EVT_NFIELD 3 #define DC_RL_EVT_EOL 4 #define DC_RL_EVT_EOFIELD 5 #define DC_RL_EVT_NEW_ADDR 6 #define DC_RL_EVT_NEW_CHAN 7 #define DC_RL_EVT_NEW_DATA 8 #define IPU_DC_GEN 0x000000d4 #define IPU_DC_DISP_CONF1_0 0x000000d8 #define IPU_DC_DISP_CONF1_1 0x000000dc #define IPU_DC_DISP_CONF1_2 0x000000e0 #define IPU_DC_DISP_CONF1_3 0x000000e4 #define IPU_DC_DISP_CONF2_0 0x000000e8 #define IPU_DC_DISP_CONF2_1 0x000000ec #define IPU_DC_DISP_CONF2_2 0x000000f0 #define IPU_DC_DISP_CONF2_3 0x000000f4 #define IPU_DC_DI0_CONF_1 0x000000f8 #define IPU_DC_DI0_CONF_2 0x000000fc #define IPU_DC_DI1_CONF_1 0x00000100 #define IPU_DC_DI1_CONF_2 0x00000104 #define IPU_DC_MAP_CONF_PNTR(n) (0x00000108 + (n) * 4) #define IPU_DC_MAP_CONF_0 0x00000108 #define IPU_DC_MAP_CONF_1 0x0000010c #define IPU_DC_MAP_CONF_2 0x00000110 #define IPU_DC_MAP_CONF_3 0x00000114 #define IPU_DC_MAP_CONF_4 0x00000118 #define IPU_DC_MAP_CONF_5 0x0000011c #define IPU_DC_MAP_CONF_6 0x00000120 #define IPU_DC_MAP_CONF_7 0x00000124 #define IPU_DC_MAP_CONF_8 0x00000128 #define IPU_DC_MAP_CONF_9 0x0000012c #define IPU_DC_MAP_CONF_10 0x00000130 #define IPU_DC_MAP_CONF_11 0x00000134 #define IPU_DC_MAP_CONF_12 0x00000138 #define IPU_DC_MAP_CONF_13 0x0000013c #define IPU_DC_MAP_CONF_14 0x00000140 #define IPU_DC_MAP_CONF_MASK(n) (0x00000144 + (n) * 4) #define IPU_DC_MAP_CONF_15 0x00000144 #define IPU_DC_MAP_CONF_16 0x00000148 #define IPU_DC_MAP_CONF_17 0x0000014c #define IPU_DC_MAP_CONF_18 0x00000150 #define IPU_DC_MAP_CONF_19 0x00000154 #define IPU_DC_MAP_CONF_20 0x00000158 #define IPU_DC_MAP_CONF_21 0x0000015c #define IPU_DC_MAP_CONF_22 0x00000160 #define IPU_DC_MAP_CONF_23 0x00000164 #define IPU_DC_MAP_CONF_24 0x00000168 #define IPU_DC_MAP_CONF_25 0x0000016c #define IPU_DC_MAP_CONF_26 0x00000170 #define IPU_DC_UGDE(m, n) (0x00000174 + (m) * 0x10 + (n) +4) #define IPU_DC_UGDE0_0 0x00000174 #define IPU_DC_UGDE0_1 0x00000178 #define IPU_DC_UGDE0_2 0x0000017c #define IPU_DC_UGDE0_3 0x00000180 #define IPU_DC_UGDE1_0 0x00000184 #define IPU_DC_UGDE1_1 0x00000188 #define IPU_DC_UGDE1_2 0x0000018c #define IPU_DC_UGDE1_3 0x00000190 #define IPU_DC_UGDE2_0 0x00000194 #define IPU_DC_UGDE2_1 0x00000198 #define IPU_DC_UGDE2_2 0x0000019c #define IPU_DC_UGDE2_3 0x000001a0 #define IPU_DC_UGDE3_0 0x000001a4 #define IPU_DC_UGDE3_1 0x000001a8 #define IPU_DC_UGDE3_2 0x000001ac #define IPU_DC_UGDE3_3 0x000001b0 #define IPU_DC_LLA0 0x000001b4 #define IPU_DC_LLA1 0x000001b8 #define IPU_DC_R_LLA0 0x000001bc #define IPU_DC_R_LLA1 0x000001c0 #define IPU_DC_WR_CH_ADDR_5_ALT 0x000001c4 #define IPU_DC_STAT 0x000001c8 /* * DMFC * Display Multi FIFO Controller */ #define IPU_DMFC_RD_CHAN 0x00000000 #define DMFC_RD_CHAN_PPW_C 0x03000000 #define DMFC_RD_CHAN_WM_DR_0 0x00e00000 #define DMFC_RD_CHAN_WM_SET_0 0x001c0000 #define DMFC_RD_CHAN_WM_EN_0 0x00020000 #define DMFC_RD_CHAN_BURST_SIZE_0 0x000000c0 #define IPU_DMFC_WR_CHAN 0x00000004 #define DMFC_WR_CHAN_BUSRT_SIZE_2C 0xc0000000 #define DMFC_WR_CHAN_FIFO_SIZE_2C 0x38000000 #define DMFC_WR_CHAN_ST_ADDR_2C 0x07000000 #define DMFC_WR_CHAN_BURST_SIZE_1C 0x00c00000 #define DMFC_WR_CHAN_FIFO_SIZE_1C 0x00380000 #define DMFC_WR_CHAN_ST_ADDR_1C 0x00070000 #define DMFC_WR_CHAN_BURST_SIZE_2 0x0000c000 #define DMFC_WR_CHAN_FIFO_SIZE_2 0x00003800 #define DMFC_WR_CHAN_ST_ADDR_2 0x00000700 #define DMFC_WR_CHAN_BURST_SIZE_1 0x000000c0 #define DMFC_WR_CHAN_FIFO_SIZE_1 0x00000038 #define DMFC_WR_CHAN_ST_ADDR_1 0x00000007 #define IPU_DMFC_WR_CHAN_DEF 0x00000008 #define DMFC_WR_CHAN_DEF_WM_CLR_2C 0xe0000000 #define DMFC_WR_CHAN_DEF_WM_SET_2C 0x1c000000 #define DMFC_WR_CHAN_DEF_WM_EN_2C 0x02000000 #define DMFC_WR_CHAN_DEF_WM_CLR_1C 0x00e00000 #define DMFC_WR_CHAN_DEF_WM_SET_1C 0x001c0000 #define DMFC_WR_CHAN_DEF_WM_EN_1C 0x00020000 #define DMFC_WR_CHAN_DEF_WM_CLR_2 0x0000e000 #define DMFC_WR_CHAN_DEF_WM_SET_2 0x00001c00 #define DMFC_WR_CHAN_DEF_WM_EN_2 0x00000200 #define DMFC_WR_CHAN_DEF_WM_CLR_1 0x000000e0 #define DMFC_WR_CHAN_DEF_WM_SET_1 0x0000000c #define DMFC_WR_CHAN_DEF_WM_EN_1 0x00000002 #define IPU_DMFC_DP_CHAN 0x0000000c #define DMFC_DP_CHAN_BUSRT_SIZE_6F 0xc0000000 #define DMFC_DP_CHAN_FIFO_SIZE_6F 0x38000000 #define DMFC_DP_CHAN_ST_ADDR_6F 0x07000000 #define DMFC_DP_CHAN_BURST_SIZE_6B 0x00c00000 #define DMFC_DP_CHAN_FIFO_SIZE_6B 0x00380000 #define DMFC_DP_CHAN_ST_ADDR_6B 0x00070000 #define DMFC_DP_CHAN_BURST_SIZE_5F 0x0000c000 #define DMFC_DP_CHAN_FIFO_SIZE_5F 0x00003800 #define DMFC_DP_CHAN_ST_ADDR_5F 0x00000700 #define DMFC_DP_CHAN_BURST_SIZE_5B 0x000000c0 #define DMFC_DP_CHAN_FIFO_SIZE_5B 0x00000038 #define DMFC_DP_CHAN_ST_ADDR_5B 0x00000007 #define IPU_DMFC_DP_CHAN_DEF 0x00000010 #define DMFC_DP_CHAN_DEF_WM_CLR_6F 0xe0000000 #define DMFC_DP_CHAN_DEF_WM_SET_6F 0x1c000000 #define DMFC_DP_CHAN_DEF_WM_EN_6F 0x02000000 #define DMFC_DP_CHAN_DEF_WM_CLR_6B 0x00e00000 #define DMFC_DP_CHAN_DEF_WM_SET_6B 0x001c0000 #define DMFC_DP_CHAN_DEF_WM_EN_6B 0x00020000 #define DMFC_DP_CHAN_DEF_WM_CLR_5F 0x0000e000 #define DMFC_DP_CHAN_DEF_WM_SET_5F 0x00001c00 #define DMFC_DP_CHAN_DEF_WM_EN_5F 0x00000200 #define DMFC_DP_CHAN_DEF_WM_CLR_5B 0x000000e0 #define DMFC_DP_CHAN_DEF_WM_SET_5B 0x0000001c #define DMFC_DP_CHAN_DEF_WM_EN_5B 0x00000002 #define IPU_DMFC_GENERAL1 0x00000014 #define DMFC_GENERAL1_WAIT4EOT_9 0x01000000 #define DMFC_GENERAL1_WAIT4EOT_6F 0x00800000 #define DMFC_GENERAL1_WAIT4EOT_6B 0x00400000 #define DMFC_GENERAL1_WAIT4EOT_5F 0x00200000 #define DMFC_GENERAL1_WAIT4EOT_5B 0x00100000 #define DMFC_GENERAL1_WAIT4EOT_4 0x00080000 #define DMFC_GENERAL1_WAIT4EOT_3 0x00040000 #define DMFC_GENERAL1_WAIT4EOT_2 0x00020000 #define DMFC_GENERAL1_WAIT4EOT_1 0x00010000 #define DMFC_GENERAL1_WM_CLR_9 0x0000e000 #define DMFC_GENERAL1_WM_SET_9 0x00001c00 #define DMFC_GENERAL1_BURST_SIZE_9 0x00000060 #define DMFC_GENERAL1_DCDP_SYNC_PR 0x00000003 #define DCDP_SYNC_PR_FORBIDDEN 0 #define DCDP_SYNC_PR_DC_DP 1 #define DCDP_SYNC_PR_DP_DC 2 #define DCDP_SYNC_PR_ROUNDROBIN 3 #define IPU_DMFC_GENERAL2 0x00000018 #define DMFC_GENERAL2_FRAME_HEIGHT_RD 0x1fff0000 #define DMFC_GENERAL2_FRAME_WIDTH_RD 0x00001fff #define IPU_DMFC_IC_CTRL 0x0000001c #define DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD 0xfff80000 #define DMFC_IC_CTRL_IC_FRAME_WIDTH_RD 0x0007ffc0 #define DMFC_IC_CTRL_IC_PPW_C 0x00000030 #define DMFC_IC_CTRL_IC_IN_PORT 0x00000007 #define IC_IN_PORT_CH28 0 #define IC_IN_PORT_CH41 1 #define IC_IN_PORT_DISABLE 2 #define IC_IN_PORT_CH23 4 #define IC_IN_PORT_CH27 5 #define IC_IN_PORT_CH24 6 #define IC_IN_PORT_CH29 7 #define IPU_DMFC_WR_CHAN_ALT 0x00000020 #define IPU_DMFC_WR_CHAN_DEF_ALT 0x00000024 #define IPU_DMFC_DP_CHAN_ALT 0x00000028 #define IPU_DMFC_DP_CHAN_DEF_ALT 0x0000002c #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT 0xe0000000 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT 0x1c000000 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT 0x02000000 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT 0x00e00000 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT 0x001c0000 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT 0x00020000 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT 0x000000e0 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT 0x0000001c #define DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT 0x00000002 #define IPU_DMFC_GENERAL1_ALT 0x00000030 #define DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT 0x00800000 #define DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT 0x00400000 #define DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT 0x00100000 #define DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT 0x00020000 #define IPU_DMFC_STAT 0x00000034 #define DMFC_STAT_IC_BUFFER_EMPTY 0x02000000 #define DMFC_STAT_IC_BUFFER_FULL 0x01000000 #define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n)) #define DMFC_STAT_FIFO_FULL(n) __BIT((n)) /* * VCI * Video De Interkacing Module */ #define IPU_VDI_FSIZE 0x00000000 #define IPU_VDI_C 0x00000004 /* * DP * Display Processor */ #define IPU_DP_COM_CONF_SYNC 0x00000000 #define DP_FG_EN_SYNC 0x00000001 #define DP_DP_GWAM_SYNC 0x00000004 #define IPU_DP_GRAPH_WIND_CTRL_SYNC 0x00000004 #define IPU_DP_FG_POS_SYNC 0x00000008 #define IPU_DP_CUR_POS_SYNC 0x0000000c #define IPU_DP_CUR_MAP_SYNC 0x00000010 #define IPU_DP_CSC_SYNC_0 0x00000054 #define IPU_DP_CSC_SYNC_1 0x00000058 #define IPU_DP_CUR_POS_ALT 0x0000005c #define IPU_DP_COM_CONF_ASYNC0 0x00000060 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC0 0x00000064 #define IPU_DP_FG_POS_ASYNC0 0x00000068 #define IPU_DP_CUR_POS_ASYNC0 0x0000006c #define IPU_DP_CUR_MAP_ASYNC0 0x00000070 #define IPU_DP_CSC_ASYNC0_0 0x000000b4 #define IPU_DP_CSC_ASYNC0_1 0x000000b8 #define IPU_DP_COM_CONF_ASYNC1 0x000000bc #define IPU_DP_GRAPH_WIND_CTRL_ASYNC1 0x000000c0 #define IPU_DP_FG_POS_ASYNC1 0x000000c4 #define IPU_DP_CUR_POS_ASYNC1 0x000000c8 #define IPU_DP_CUR_MAP_ASYNC1 0x000000cc #define IPU_DP_CSC_ASYNC1_0 0x00000110 #define IPU_DP_CSC_ASYNC1_1 0x00000114 /* IDMA parameter */ /* * non-Interleaved parameter * * param 0: XV W0[ 9: 0] * YV W0[18:10] * XB W0[31:19] * param 1: YB W0[43:32] * NSB W0[44] * CF W0[45] * UBO W0[61:46] * param 2: UBO W0[67:62] * VBO W0[89:68] * IOX W0[93:90] * RDRW W0[94] * Reserved W0[95] * param 3: Reserved W0[112:96] * S0 W0[113] * BNDM W0[116:114] * BM W0[118:117] * ROT W0[119] * HF W0[120] * VF W0[121] * THF W0[122] * CAP W0[123] * CAE W0[124] * FW W0[127:125] * param 4: FW W0[137:128] * FH W0[149:138] * param 5: EBA0 W1[28:0] * EBA1 W1[31:29] * param 6: EBA1 W1[57:32] * ILO W1[63:58] * param 7: ILO W1[77:64] * NPB W1[84:78] * PFS W1[88:85] * ALU W1[89] * ALBM W1[92:90] * ID W1[94:93] * TH W1[95] * param 8: TH W1[101:96] * SLY W1[115:102] * WID3 W1[127:125] * param 9: SLUV W1[141:128] * CRE W1[149] * * Interleaved parameter * * param 0: XV W0[ 9: 0] * YV W0[18:10] * XB W0[31:19] * param 1: YB W0[43:32] * NSB W0[44] * CF W0[45] * SX W0[57:46] * SY W0[61:58] * param 2: SY W0[68:62] * NS W0[78:69] * SDX W0[85:79] * SM W0[95:86] * param 3: SCC W0[96] * SCE W0[97] * SDY W0[104:98] * SDRX W0[105] * SDRY W0[106] * BPP W0[109:107] * DEC_SEL W0[111:110] * DIM W0[112] * SO W0[113] * BNDM W0[116:114] * BM W0[118:117] * ROT W0[119] * HF W0[120] * VF W0[121] * THF W0[122] * CAP W0[123] * CAE W0[124] * FW W0[127:125] * param 4: FW W0[137:128] * FH W0[149:138] * param 5: EBA0 W1[28:0] * EBA1 W1[31:29] * param 6: EBA1 W1[57:32] * ILO W1[63:58] * param 7: ILO W1[77:64] * NPB W1[84:78] * PFS W1[88:85] * ALU W1[89] * ALBM W1[92:90] * ID W1[94:93] * TH W1[95] * param 8: TH W1[101:96] * SL W1[115:102] * WID0 W1[118:116] * WID1 W1[121:119] * WID2 W1[124:122] * WID3 W1[127:125] * param 9: OFS0 W1[132:128] * OFS1 W1[137:133] * OFS2 W1[142:138] * OFS3 W1[147:143] * SXYS W1[148] * CRE W1[149] * DEC_SEL2 W1[150] */ #define __IDMA_PARAM(word, shift, size) \ ((((word) & 0xff) << 16) | (((shift) & 0xff) << 8) | ((size) & 0xff)) /* non-Interleaved parameter */ /* W0 */ #define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) #define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) #define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) #define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) #define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) #define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) #define IDMAC_Ch_PARAM_UBO __IDMA_PARAM(0, 46, 22) #define IDMAC_Ch_PARAM_VBO __IDMA_PARAM(0, 68, 22) #define IDMAC_Ch_PARAM_IOX __IDMA_PARAM(0, 90, 4) #define IDMAC_Ch_PARAM_RDRW __IDMA_PARAM(0, 94, 1) #define IDMAC_Ch_PARAM_S0 __IDMA_PARAM(0,113, 1) #define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) #define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) #define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) #define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) #define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) #define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) #define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) #define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) #define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) #define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) /* W1 */ #define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) #define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) #define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) #define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) #define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) #define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) #define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) #define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) #define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) #define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) #define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) #define IDMAC_Ch_PARAM_SLUV __IDMA_PARAM(1,128, 14) #define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) /* Interleaved parameter */ /* W0 */ #define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) #define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) #define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) #define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) #define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) #define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) #define IDMAC_Ch_PARAM_SX __IDMA_PARAM(0, 46, 12) #define IDMAC_Ch_PARAM_SY __IDMA_PARAM(0, 58, 11) #define IDMAC_Ch_PARAM_NS __IDMA_PARAM(0, 69, 10) #define IDMAC_Ch_PARAM_SDX __IDMA_PARAM(0, 79, 7) #define IDMAC_Ch_PARAM_SM __IDMA_PARAM(0, 86, 10) #define IDMAC_Ch_PARAM_SCC __IDMA_PARAM(0, 96, 1) #define IDMAC_Ch_PARAM_SCE __IDMA_PARAM(0, 97, 1) #define IDMAC_Ch_PARAM_SDY __IDMA_PARAM(0, 98, 7) #define IDMAC_Ch_PARAM_SDRX __IDMA_PARAM(0,105, 1) #define IDMAC_Ch_PARAM_SDRY __IDMA_PARAM(0,106, 1) #define IDMAC_Ch_PARAM_BPP __IDMA_PARAM(0,107, 3) #define IDMAC_Ch_PARAM_DEC_SEL __IDMA_PARAM(0,110, 2) #define IDMAC_Ch_PARAM_DIM __IDMA_PARAM(0,112, 1) #define IDMAC_Ch_PARAM_SO __IDMA_PARAM(0,113, 1) #define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) #define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) #define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) #define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) #define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) #define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) #define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) #define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) #define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) #define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) /* W1 */ #define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) #define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) #define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) #define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) #define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) #define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) #define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) #define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) #define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) #define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) #define IDMAC_Ch_PARAM_WID0 __IDMA_PARAM(1,116, 3) #define IDMAC_Ch_PARAM_WID1 __IDMA_PARAM(1,119, 3) #define IDMAC_Ch_PARAM_WID2 __IDMA_PARAM(1,122, 3) #define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) #define IDMAC_Ch_PARAM_OFS0 __IDMA_PARAM(1,128, 5) #define IDMAC_Ch_PARAM_OFS1 __IDMA_PARAM(1,133, 5) #define IDMAC_Ch_PARAM_OFS2 __IDMA_PARAM(1,138, 5) #define IDMAC_Ch_PARAM_OFS3 __IDMA_PARAM(1,143, 5) #define IDMAC_Ch_PARAM_SXYS __IDMA_PARAM(1,148, 1) #define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) #define IDMAC_Ch_PARAM_DEC_SEL2 __IDMA_PARAM(1,150, 1) /* XXX Temp */ #define GPUMEM_BASE 0x20000000 #define GPUMEM_SIZE 0x20000 #define GPU_BASE 0x30000000 #define GPU_SIZE 0x10000000 -/* Image Prossasing Unit */ -#define IPU_BASE 0x40000000 -#define IPU_CM_BASE (IPU_BASE + 0x1e000000) -#define IPU_CM_SIZE 0x8000 -#define IPU_IDMAC_BASE (IPU_BASE + 0x1e008000) -#define IPU_IDMAC_SIZE 0x8000 -#define IPU_DP_BASE (IPU_BASE + 0x1e018000) -#define IPU_DP_SIZE 0x8000 -#define IPU_IC_BASE (IPU_BASE + 0x1e020000) -#define IPU_IC_SIZE 0x8000 -#define IPU_IRT_BASE (IPU_BASE + 0x1e028000) -#define IPU_IRT_SIZE 0x8000 -#define IPU_CSI0_BASE (IPU_BASE + 0x1e030000) -#define IPU_CSI0_SIZE 0x8000 -#define IPU_CSI1_BASE (IPU_BASE + 0x1e038000) -#define IPU_CSI1_SIZE 0x8000 -#define IPU_DI0_BASE (IPU_BASE + 0x1e040000) -#define IPU_DI0_SIZE 0x8000 -#define IPU_DI1_BASE (IPU_BASE + 0x1e048000) -#define IPU_DI1_SIZE 0x8000 -#define IPU_SMFC_BASE (IPU_BASE + 0x1e050000) -#define IPU_SMFC_SIZE 0x8000 -#define IPU_DC_BASE (IPU_BASE + 0x1e058000) -#define IPU_DC_SIZE 0x8000 -#define IPU_DMFC_BASE (IPU_BASE + 0x1e060000) -#define IPU_DMFC_SIZE 0x8000 -#define IPU_VDI_BASE (IPU_BASE + 0x1e068000) -#define IPU_VDI_SIZE 0x8000 -#define IPU_CPMEM_BASE (IPU_BASE + 0x1f000000) -#define IPU_CPMEM_SIZE 0x20000 -#define IPU_LUT_BASE (IPU_BASE + 0x1f020000) -#define IPU_LUT_SIZE 0x20000 -#define IPU_SRM_BASE (IPU_BASE + 0x1f040000) -#define IPU_SRM_SIZE 0x20000 -#define IPU_TPM_BASE (IPU_BASE + 0x1f060000) -#define IPU_TPM_SIZE 0x20000 -#define IPU_DCTMPL_BASE (IPU_BASE + 0x1f080000) -#define IPU_DCTMPL_SIZE 0x20000 +/* + * Image Processing Unit + * + * All addresses are relative to the base SoC address. + */ +#define IPU_CM_BASE(_base) ((_base) + 0x1e000000) +#define IPU_CM_SIZE 0x8000 +#define IPU_IDMAC_BASE(_base) ((_base) + 0x1e008000) +#define IPU_IDMAC_SIZE 0x8000 +#define IPU_DP_BASE(_base) ((_base) + 0x1e018000) +#define IPU_DP_SIZE 0x8000 +#define IPU_IC_BASE(_base) ((_base) + 0x1e020000) +#define IPU_IC_SIZE 0x8000 +#define IPU_IRT_BASE(_base) ((_base) + 0x1e028000) +#define IPU_IRT_SIZE 0x8000 +#define IPU_CSI0_BASE(_base) ((_base) + 0x1e030000) +#define IPU_CSI0_SIZE 0x8000 +#define IPU_CSI1_BASE(_base) ((_base) + 0x1e038000) +#define IPU_CSI1_SIZE 0x8000 +#define IPU_DI0_BASE(_base) ((_base) + 0x1e040000) +#define IPU_DI0_SIZE 0x8000 +#define IPU_DI1_BASE(_base) ((_base) + 0x1e048000) +#define IPU_DI1_SIZE 0x8000 +#define IPU_SMFC_BASE(_base) ((_base) + 0x1e050000) +#define IPU_SMFC_SIZE 0x8000 +#define IPU_DC_BASE(_base) ((_base) + 0x1e058000) +#define IPU_DC_SIZE 0x8000 +#define IPU_DMFC_BASE(_base) ((_base) + 0x1e060000) +#define IPU_DMFC_SIZE 0x8000 +#define IPU_VDI_BASE(_base) ((_base) + 0x1e068000) +#define IPU_VDI_SIZE 0x8000 +#define IPU_CPMEM_BASE(_base) ((_base) + 0x1f000000) +#define IPU_CPMEM_SIZE 0x20000 +#define IPU_LUT_BASE(_base) ((_base) + 0x1f020000) +#define IPU_LUT_SIZE 0x20000 +#define IPU_SRM_BASE(_base) ((_base) + 0x1f040000) +#define IPU_SRM_SIZE 0x20000 +#define IPU_TPM_BASE(_base) ((_base) + 0x1f060000) +#define IPU_TPM_SIZE 0x20000 +#define IPU_DCTMPL_BASE(_base) ((_base) + 0x1f080000) +#define IPU_DCTMPL_SIZE 0x20000 #endif /* _ARM_IMX_IMX51_IPUV3REG_H */ Index: head/sys/boot/fdt/dts/arm/digi-ccwmx53.dts =================================================================== --- head/sys/boot/fdt/dts/arm/digi-ccwmx53.dts (revision 264250) +++ head/sys/boot/fdt/dts/arm/digi-ccwmx53.dts (revision 264251) @@ -1,133 +1,133 @@ /* * Copyright (c) 2012 The FreeBSD Foundation * Copyright (c) 2013 Rui Paulo * All rights reserved. * * This software was developed by Semihalf under sponsorship from * the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Digi ConnectCore Wi-i.MX53 * * $FreeBSD$ */ /dts-v1/; /include/ "imx53x.dtsi" / { model = "Digi ConnectCore Wi-i.MX53"; compatible = "digi,imx53-ccwm53"; memory { /* RAM 512M */ reg = <0x70000000 0x10000000 0xB0000000 0x10000000>; }; localbus@18000000 { - ipu3@18000000 { + ipu3@1E000000 { status = "okay"; }; }; soc@50000000 { aips@50000000 { spba@50000000 { esdhc@50004000 { clock-frequency = <216000000>; status = "okay"; }; esdhc@50008000 { clock-frequency = <216000000>; status = "okay"; }; SSI2: ssi@50014000 { status = "okay"; }; }; timer@53fa0000 { status = "okay"; }; /* UART1, console */ console: serial@53fbc000 { status = "okay"; clock-frequency = <0>; /* won't load w/o this */ }; clock@53fd4000 { status = "okay"; }; gpio@53f84000 { status = "okay"; }; gpio@53f88000 { status = "okay"; }; gpio@53f8c000 { status = "okay"; }; gpio@53f90000 { status = "okay"; }; usb@53f80000 /* OTG */ { status = "okay"; }; usb@53f80200 /* Host 1 */ { status = "okay"; }; wdog@53f98000 { status = "okay"; }; }; aips@60000000 { ethernet@63fec000 { status = "okay"; phy-mode = "rmii"; }; i2c@63fc4000 { status = "okay"; }; i2c@63fc8000 { status = "okay"; }; audmux@63fd4000 { status = "okay"; }; ide@63fe0000 { status = "okay"; }; }; }; aliases { SSI2 = &SSI2; }; chosen { bootargs = "-v"; stdin = &console; stdout = &console; }; }; Index: head/sys/boot/fdt/dts/arm/imx53-qsb.dts =================================================================== --- head/sys/boot/fdt/dts/arm/imx53-qsb.dts (revision 264250) +++ head/sys/boot/fdt/dts/arm/imx53-qsb.dts (revision 264251) @@ -1,134 +1,134 @@ /* * Copyright (c) 2012 The FreeBSD Foundation * Copyright (c) 2013 Rui Paulo * All rights reserved. * * This software was developed by Semihalf under sponsorship from * the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Freescale i.MX53 Quick Start Board * In u-boot, this board is known as "MX53LOCO" for some reason. * * $FreeBSD$ */ /dts-v1/; /include/ "imx53x.dtsi" / { model = "Freescale i.MX53 Quick Start Board"; compatible = "fsl,imx53-qsb", "fsl,imx53"; memory { /* RAM is 2 banks of 512M each. */ reg = <0x70000000 0x20000000 0xb0000000 0x20000000>; }; localbus@18000000 { - ipu3@18000000 { + ipu3@1E000000 { status = "okay"; }; }; soc@50000000 { aips@50000000 { spba@50000000 { esdhc@50004000 { clock-frequency = <216000000>; status = "okay"; }; esdhc@50008000 { clock-frequency = <216000000>; status = "okay"; }; SSI2: ssi@50014000 { status = "okay"; }; }; timer@53fa0000 { status = "okay"; }; /* UART1, console */ console: serial@53fbc000 { status = "okay"; clock-frequency = <0>; /* won't load w/o this */ }; clock@53fd4000 { status = "okay"; }; gpio@53f84000 { status = "okay"; }; gpio@53f88000 { status = "okay"; }; gpio@53f8c000 { status = "okay"; }; gpio@53f90000 { status = "okay"; }; usb@53f80000 /* OTG */ { status = "okay"; }; usb@53f80200 /* Host 1 */ { status = "okay"; }; wdog@53f98000 { status = "okay"; }; }; aips@60000000 { ethernet@63fec000 { status = "okay"; phy-mode = "rmii"; }; i2c@63fc4000 { status = "okay"; }; i2c@63fc8000 { status = "okay"; }; audmux@63fd4000 { status = "okay"; }; ide@63fe0000 { status = "okay"; }; }; }; aliases { SSI2 = &SSI2; }; chosen { bootargs = "-v"; stdin = &console; stdout = &console; }; }; Index: head/sys/boot/fdt/dts/arm/imx53x.dtsi =================================================================== --- head/sys/boot/fdt/dts/arm/imx53x.dtsi (revision 264250) +++ head/sys/boot/fdt/dts/arm/imx53x.dtsi (revision 264251) @@ -1,702 +1,702 @@ /* * Copyright (c) 2012 The FreeBSD Foundation * Copyright (c) 2013 Rui Paulo * All rights reserved. * * This software was developed by Semihalf under sponsorship from * the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Freescale i.MX535 Device Tree Source. * * $FreeBSD$ */ / { #address-cells = <1>; #size-cells = <1>; aliases { soc = &SOC; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "ARM,MCIMX535"; reg = <0x0>; d-cache-line-size = <32>; i-cache-line-size = <32>; d-cache-size = <0x8000>; i-cache-size = <0x8000>; l2-cache-line-size = <32>; l2-cache-line = <0x40000>; timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; }; }; localbus@0fffc000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; /* This reflects CPU decode windows setup. */ ranges; tzic: tz-interrupt-controller@0fffc000 { compatible = "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x0fffc000 0x00004000>; }; /* * 40000000 40000FFF 4K Debug ROM * 40001000 40001FFF 4K ETB * 40002000 40002FFF 4K ETM * 40003000 40003FFF 4K TPIU * 40004000 40004FFF 4K CTI0 * 40005000 40005FFF 4K CTI1 * 40006000 40006FFF 4K CTI2 * 40007000 40007FFF 4K CTI3 * 40008000 40008FFF 4K ARM Debug Unit * * 0FFFC000 0FFFCFFF 0x4000 TZIC */ }; SOC: soc@50000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&tzic>; ranges; aips@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&tzic>; ranges; /* Required by many devices, so better to stay first */ /* 53FD4000 0x4000 CCM */ clock@53fd4000 { compatible = "fsl,imx53-ccm"; /* 63F80000 0x4000 DPLLIP1 */ /* 63F84000 0x4000 DPLLIP2 */ /* 63F88000 0x4000 DPLLIP3 */ reg = <0x53fd4000 0x4000 0x63F80000 0x4000 0x63F84000 0x4000 0x63F88000 0x4000>; interrupt-parent = <&tzic>; interrupts = <71 72>; status = "disabled"; }; /* * GPIO modules moved up - to have it attached for * drivers which rely on GPIO */ /* 53F84000 0x4000 GPIO1 */ gpio1: gpio@53f84000 { compatible = "fsl,imx53-gpio"; reg = <0x53f84000 0x4000>; interrupt-parent = <&tzic>; interrupts = <50 51 42 43 44 45 46 47 48 49>; /* TODO: use <> also */ gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; }; /* 53F88000 0x4000 GPIO2 */ gpio2: gpio@53f88000 { compatible = "fsl,imx53-gpio"; reg = <0x53f88000 0x4000>; interrupt-parent = <&tzic>; interrupts = <52 53>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; }; /* 53F8C000 0x4000 GPIO3 */ gpio3: gpio@53f8c000 { compatible = "fsl,imx53-gpio"; reg = <0x53f8c000 0x4000>; interrupt-parent = <&tzic>; interrupts = <54 55>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; }; /* 53F90000 0x4000 GPIO4 */ gpio4: gpio@53f90000 { compatible = "fsl,imx53-gpio"; reg = <0x53f90000 0x4000>; interrupt-parent = <&tzic>; interrupts = <56 57>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; }; /* 53FDC000 0x4000 GPIO5 */ gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio"; reg = <0x53fdc000 0x4000>; interrupt-parent = <&tzic>; interrupts = <103 104>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; }; /* 53FE0000 0x4000 GPIO6 */ gpio6: gpio@53fe0000 { compatible = "fsl,imx53-gpio"; reg = <0x53fe0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <105 106>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; }; /* 53FE4000 0x4000 GPIO5 */ gpio7: gpio@53fe4000 { compatible = "fsl,imx53-gpio"; reg = <0x53fe4000 0x4000>; interrupt-parent = <&tzic>; interrupts = <107 108>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <1>; }; spba@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&tzic>; ranges; /* 50004000 0x4000 ESDHC 1 */ esdhc@50004000 { compatible = "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupt-parent = <&tzic>; interrupts = <1>; status = "disabled"; }; /* 50008000 0x4000 ESDHC 2 */ esdhc@50008000 { compatible = "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupt-parent = <&tzic>; interrupts = <2>; status = "disabled"; }; /* 5000C000 0x4000 UART 3 */ uart3: serial@5000c000 { compatible = "fsl,imx53-uart", "fsl,imx-uart"; reg = <0x5000c000 0x4000>; interrupt-parent = <&tzic>; interrupts = <33>; status = "disabled"; }; /* 50010000 0x4000 eCSPI1 */ ecspi@50010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-ecspi"; reg = <0x50010000 0x4000>; interrupt-parent = <&tzic>; interrupts = <36>; status = "disabled"; }; /* 50014000 0x4000 SSI2 irq30 */ SSI2: ssi@50014000 { compatible = "fsl,imx53-ssi"; reg = <0x50014000 0x4000>; interrupt-parent = <&tzic>; interrupts = <30>; status = "disabled"; }; /* 50020000 0x4000 ESDHC 3 */ esdhc@50020000 { compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupt-parent = <&tzic>; interrupts = <3>; status = "disabled"; }; /* 50024000 0x4000 ESDHC 4 */ esdhc@50024000 { compatible = "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupt-parent = <&tzic>; interrupts = <4>; status = "disabled"; }; /* 50028000 0x4000 SPDIF */ /* 91 SPDIF */ /* 50030000 0x4000 PATA (PORT UDMA) irq70 */ /* 50034000 0x4000 SLM */ /* 50038000 0x4000 HSI2C */ /* 64 HS-I2C */ /* 5003C000 0x4000 SPBA */ }; usbphy0: usbphy@0 { compatible = "usb-nop-xceiv"; status = "okay"; }; usbphy1: usbphy@1 { compatible = "usb-nop-xceiv"; status = "okay"; }; usbotg: usb@53f80000 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; fsl,usbphy = <&usbphy0>; status = "disabled"; }; usbh1: usb@53f80200 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80200 0x0200>; interrupts = <14>; fsl,usbphy = <&usbphy1>; status = "disabled"; }; usbh2: usb@53f80400 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80400 0x0200>; interrupts = <16>; status = "disabled"; }; usbh3: usb@53f80600 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80600 0x0200>; interrupts = <17>; status = "disabled"; }; usbmisc: usbmisc@53f80800 { #index-cells = <1>; compatible = "fsl,imx53-usbmisc"; reg = <0x53f80800 0x200>; }; /* 53F98000 0x4000 WDOG1 */ wdog@53f98000 { compatible = "fsl,imx53-wdt"; reg = <0x53f98000 0x4000>; interrupt-parent = <&tzic>; interrupts = <58>; status = "disabled"; }; /* 53F9C000 0x4000 WDOG2 (TZ) */ wdog@53f9c000 { compatible = "fsl,imx53-wdt"; reg = <0x53f9c000 0x4000>; interrupt-parent = <&tzic>; interrupts = <59>; status = "disabled"; }; /* 53F94000 0x4000 KPP */ keyboard@53f94000 { compatible = "fsl,imx53-kpp"; reg = <0x53f94000 0x4000>; interrupt-parent = <&tzic>; interrupts = <60>; status = "disabled"; }; /* 53FA0000 0x4000 GPT */ timer@53fa0000 { compatible = "fsl,imx53-gpt"; reg = <0x53fa0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <39>; status = "disabled"; }; /* 53FA4000 0x4000 SRTC */ rtc@53fa4000 { compatible = "fsl,imx53-srtc"; reg = <0x53fa4000 0x4000>; interrupt-parent = <&tzic>; interrupts = <24 25>; status = "disabled"; }; /* 53FA8000 0x4000 IOMUXC */ iomux@53fa8000 { compatible = "fsl,imx53-iomux"; reg = <0x53fa8000 0x4000>; interrupt-parent = <&tzic>; interrupts = <7>; }; /* 53FAC000 0x4000 EPIT1 */ epit1: timer@53fac000 { compatible = "fsl,imx53-epit"; reg = <0x53fac000 0x4000>; interrupt-parent = <&tzic>; interrupts = <40>; status = "disabled"; }; /* 53FB0000 0x4000 EPIT2 */ epit2: timer@53fb0000 { compatible = "fsl,imx53-epit"; reg = <0x53fb0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <41>; status = "disabled"; }; /* 53FB4000 0x4000 PWM1 */ pwm@53fb4000 { compatible = "fsl,imx53-pwm"; reg = <0x53fb4000 0x4000>; interrupt-parent = <&tzic>; interrupts = <61>; status = "disabled"; }; /* 53FB8000 0x4000 PWM2 */ pwm@53fb8000 { compatible = "fsl,imx53-pwm"; reg = <0x53fb8000 0x4000>; interrupt-parent = <&tzic>; interrupts = <94>; status = "disabled"; }; /* 53FBC000 0x4000 UART 1 */ uart1: serial@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx-uart"; reg = <0x53fbc000 0x4000>; interrupt-parent = <&tzic>; interrupts = <31>; status = "disabled"; }; /* 53FC0000 0x4000 UART 2 */ uart2: serial@53fc0000 { compatible = "fsl,imx53-uart", "fsl,imx-uart"; reg = <0x53fc0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <32>; status = "disabled"; }; /* 53FC0000 0x4000 UART 4 */ uart4: serial@53ff0000 { compatible = "fsl,imx53-uart", "fsl,imx-uart"; reg = <0x53ff0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <13>; status = "disabled"; }; /* 53FD0000 0x4000 SRC */ reset@53fd0000 { compatible = "fsl,imx53-src"; reg = <0x53fd0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <75>; status = "disabled"; }; /* 53FD8000 0x4000 GPC */ power@53fd8000 { compatible = "fsl,imx53-gpc"; reg = <0x53fd8000 0x4000>; interrupt-parent = <&tzic>; interrupts = <73 74>; status = "disabled"; }; /* 53FE8000 0x4000 PATA (PORT PIO) */ /* 70 PATA Parallel ATA host controller interrupt */ ide@53fe8000 { compatible = "fsl,imx53-ata"; reg = <0x83fe0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <70>; status = "disabled"; }; }; aips@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&tzic>; ranges; /* 53FC0000 0x4000 UART 5 */ uart5: serial@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx-uart"; reg = <0x63f90000 0x4000>; interrupt-parent = <&tzic>; interrupts = <32>; status = "disabled"; }; /* 63F94000 0x4000 AHBMAX */ /* 63F98000 0x4000 IIM */ /* * 69 IIM Interrupt request to the processor. * Indicates to the processor that program or * explicit. */ /* 63F9C000 0x4000 CSU */ /* * 27 CSU Interrupt Request 1. Indicates to the * processor that one or more alarm inputs were. */ /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */ /* irq76 Neon Monitor Interrupt */ /* irq77 Performance Unit Interrupt */ /* irq78 CTI IRQ */ /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */ /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */ /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */ /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */ /* 63FA4000 0x4000 OWIRE irq88 */ /* 63FA8000 0x4000 FIRI irq93 */ /* 63FAC000 0x4000 eCSPI2 */ ecspi@63fac000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-ecspi"; reg = <0x63fac000 0x4000>; interrupt-parent = <&tzic>; interrupts = <37>; status = "disabled"; }; /* 63FB0000 0x4000 SDMA */ sdma@63fb0000 { compatible = "fsl,imx53-sdma"; reg = <0x63fb0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <6>; }; /* 63FB4000 0x4000 SCC */ /* 21 SCC Security Monitor High Priority Interrupt. */ /* 22 SCC Secure (TrustZone) Interrupt. */ /* 23 SCC Regular (Non-Secure) Interrupt. */ /* 63FB8000 0x4000 ROMCP */ /* 63FBC000 0x4000 RTIC */ /* * 26 RTIC RTIC (Trust Zone) Interrupt Request. * Indicates that the RTIC has completed hashing the */ /* 63FC0000 0x4000 CSPI */ cspi@63fc0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-cspi"; reg = <0x63fc0000 0x4000>; interrupt-parent = <&tzic>; interrupts = <38>; status = "disabled"; }; /* 63FC4000 0x4000 I2C2 */ i2c@63fc4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; reg = <0x63fc4000 0x4000>; interrupt-parent = <&tzic>; interrupts = <63>; status = "disabled"; }; /* 63FC8000 0x4000 I2C1 */ i2c@63fc8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c"; reg = <0x63fc8000 0x4000>; interrupt-parent = <&tzic>; interrupts = <62>; status = "disabled"; }; /* 63FCC000 0x4000 SSI1 */ /* 29 SSI1 SSI-1 Interrupt Request */ SSI1: ssi@63fcc000 { compatible = "fsl,imx53-ssi"; reg = <0x63fcc000 0x4000>; interrupt-parent = <&tzic>; interrupts = <29>; status = "disabled"; }; /* 63FD0000 0x4000 AUDMUX */ audmux@63fd4000 { compatible = "fsl,imx53-audmux"; reg = <0x63fd4000 0x4000>; status = "disabled"; }; /* 63FD8000 0x4000 EXTMC */ /* 8 EXTMC (NFC) */ /* 15 EXTMC */ /* 97 EXTMC Boot sequence completed interrupt */ /* * 101 EMI Indicates all pages have been transferred * to NFC during an auto program operation. */ /* 83FE4000 0x4000 SIM */ /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */ /* 68 SIM intr composed of tc, etc, tfe, and rdrf */ /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */ /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */ /* 63FE4000 0x4000 MLB */ /* 63FE8000 0x4000 SSI3 */ /* 96 SSI3 SSI-3 Interrupt Request */ SSI3: ssi@63fe8000 { compatible = "fsl,imx51-ssi"; reg = <0x63fe8000 0x4000>; interrupt-parent = <&tzic>; interrupts = <96>; status = "disabled"; }; /* 63FEC000 0x4000 FEC */ ethernet@63fec000 { compatible = "fsl,imx53-fec"; reg = <0x63fec000 0x4000>; interrupt-parent = <&tzic>; interrupts = <87>; status = "disabled"; }; /* 63FF0000 0x4000 TVE */ /* 92 TVE */ /* 63FF4000 0x4000 VPU */ /* 9 VPU */ /* 100 VPU Idle interrupt from VPU */ /* 63FF8000 0x4000 SAHARA */ /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */ /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr */ }; }; localbus@18000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - vga: ipu3@18000000 { + vga: ipu3@1E000000 { compatible = "fsl,ipu3"; reg = < - 0x18000000 0x08000 /* CM */ - 0x18008000 0x08000 /* IDMAC */ - 0x18018000 0x08000 /* DP */ - 0x18020000 0x08000 /* IC */ - 0x18028000 0x08000 /* IRT */ - 0x18030000 0x08000 /* CSI0 */ - 0x18038000 0x08000 /* CSI1 */ - 0x18040000 0x08000 /* DI0 */ - 0x18048000 0x08000 /* DI1 */ - 0x18050000 0x08000 /* SMFC */ - 0x18058000 0x08000 /* DC */ - 0x18060000 0x08000 /* DMFC */ - 0x18068000 0x08000 /* VDI */ - 0x19000000 0x20000 /* CPMEM */ - 0x19020000 0x20000 /* LUT */ - 0x19040000 0x20000 /* SRM */ - 0x19060000 0x20000 /* TPM */ - 0x19080000 0x20000 /* DCTMPL */ + 0x1E000000 0x08000 /* CM */ + 0x1E008000 0x08000 /* IDMAC */ + 0x1E018000 0x08000 /* DP */ + 0x1E020000 0x08000 /* IC */ + 0x1E028000 0x08000 /* IRT */ + 0x1E030000 0x08000 /* CSI0 */ + 0x1E038000 0x08000 /* CSI1 */ + 0x1E040000 0x08000 /* DI0 */ + 0x1E048000 0x08000 /* DI1 */ + 0x1E050000 0x08000 /* SMFC */ + 0x1E058000 0x08000 /* DC */ + 0x1E060000 0x08000 /* DMFC */ + 0x1E068000 0x08000 /* VDI */ + 0x1F000000 0x20000 /* CPMEM */ + 0x1F020000 0x20000 /* LUT */ + 0x1F040000 0x20000 /* SRM */ + 0x1F060000 0x20000 /* TPM */ + 0x1F080000 0x20000 /* DCTMPL */ >; interrupt-parent = <&tzic>; interrupts = < 10 /* IPUEX Error */ 11 /* IPUEX Sync */ >; status = "disabled"; }; }; }; /* TODO: Not mapped interrupts 5 DAP 84 GPU2D (OpenVG) general interrupt 85 GPU2D (OpenVG) busy signal (for S/W power gating feasibility) 12 GPU3D 102 GPU3D Idle interrupt from GPU3D (for S/W power gating) 90 SJC */