Index: head/sys/arm/arm/exception.S =================================================================== --- head/sys/arm/arm/exception.S (revision 252310) +++ head/sys/arm/arm/exception.S (revision 252311) @@ -1,266 +1,266 @@ /* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */ /*- * Copyright (c) 1994-1997 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * exception.S * * Low level handlers for exception vectors * * Created : 24/09/94 * * Based on kate/display/abort.s * */ #include "assym.s" #include #include #include __FBSDID("$FreeBSD$"); .text .align 0 AST_LOCALS /* * reset_entry: * * Handler for Reset exception. */ ASENTRY_NP(reset_entry) adr r0, Lreset_panicmsg bl _C_LABEL(panic) /* NOTREACHED */ Lreset_panicmsg: .asciz "Reset vector called, LR = 0x%08x" .balign 4 END(reset_entry) /* * swi_entry * * Handler for the Software Interrupt exception. */ ASENTRY_NP(swi_entry) STOP_UNWINDING /* Don't unwind past here */ PUSHFRAME mov r0, sp /* Pass the frame to any function */ mov r6, sp /* Backup the stack pointer */ bic sp, sp, #7 /* Align the stack pointer */ bl _C_LABEL(swi_handler) /* It's a SWI ! */ mov sp, r6 /* Restore the stack */ DO_AST PULLFRAME movs pc, lr /* Exit */ END(swi_entry) /* * prefetch_abort_entry: * * Handler for the Prefetch Abort exception. */ ASENTRY_NP(prefetch_abort_entry) #ifdef __XSCALE__ nop /* Make absolutely sure any pending */ nop /* imprecise aborts have occurred. */ #endif sub lr, lr, #0x00000004 /* Adjust the lr */ PUSHFRAMEINSVC ldr r1, Lprefetch_abort_handler_address adr lr, exception_exit mov r0, sp /* pass the stack pointer as r0 */ ldr pc, [r1] Lprefetch_abort_handler_address: .word _C_LABEL(prefetch_abort_handler_address) .data .global _C_LABEL(prefetch_abort_handler_address) _C_LABEL(prefetch_abort_handler_address): .word abortprefetch .text abortprefetch: adr r0, abortprefetchmsg b _C_LABEL(panic) abortprefetchmsg: .asciz "abortprefetch" .align 0 END(prefetch_abort_entry) /* * data_abort_entry: * * Handler for the Data Abort exception. */ ASENTRY_NP(data_abort_entry) #ifdef __XSCALE__ nop /* Make absolutely sure any pending */ nop /* imprecise aborts have occurred. */ #endif sub lr, lr, #0x00000008 /* Adjust the lr */ PUSHFRAMEINSVC /* Push trap frame and switch */ /* to SVC32 mode */ ldr r1, Ldata_abort_handler_address adr lr, exception_exit mov r0, sp /* pass the stack pointer as r0 */ ldr pc, [r1] Ldata_abort_handler_address: .word _C_LABEL(data_abort_handler_address) .data .global _C_LABEL(data_abort_handler_address) _C_LABEL(data_abort_handler_address): .word abortdata .text abortdata: adr r0, abortdatamsg b _C_LABEL(panic) abortdatamsg: .asciz "abortdata" .align 0 END(data_abort_entry) /* * address_exception_entry: * * Handler for the Address Exception exception. * * NOTE: This exception isn't really used on arm32. We * print a warning message to the console and then treat * it like a Data Abort. */ ASENTRY_NP(address_exception_entry) mrs r1, cpsr_all mrs r2, spsr_all mov r3, lr adr r0, Laddress_exception_msg bl _C_LABEL(printf) /* XXX CLOBBERS LR!! */ b data_abort_entry Laddress_exception_msg: .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n" .balign 4 END(address_exception_entry) /* * General exception exit handler * (Placed here to be within range of all the references to it) * * It exits straight away if not returning to USR mode. * This loops around delivering any pending ASTs. * Interrupts are disabled at suitable points to avoid ASTs * being posted between testing and exit to user mode. * * This function uses PULLFRAMEFROMSVCANDEXIT and DO_AST and can * only be called if the exception handler used PUSHFRAMEINSVC. * * For EABI, don't try to unwind any further than this. This is a * stopgap measure to avoid getting stuck in a loop in the unwinder, * which happens because we don't yet provide the proper unwind info * here that describes which registers are being restored. */ ASENTRY_NP(exception_exit) - STOP_UNWINDING + UNWINDSVCFRAME DO_AST PULLFRAMEFROMSVCANDEXIT END(exception_exit) /* * undefined_entry: * * Handler for the Undefined Instruction exception. * * We indirect the undefined vector via the handler address * in the data area. Entry to the undefined handler must * look like direct entry from the vector. */ ASENTRY_NP(undefined_entry) stmfd sp!, {r0, r1} ldr r0, Lundefined_handler_indirection ldr r1, [sp], #0x0004 str r1, [r0, #0x0000] ldr r1, [sp], #0x0004 str r1, [r0, #0x0004] ldmia r0, {r0, r1, pc} Lundefined_handler_indirection: .word Lundefined_handler_indirection_data END(undefined_entry) /* * assembly bounce code for calling the kernel * undefined instruction handler. This uses * a standard trap frame and is called in SVC mode. */ ENTRY_NP(undefinedinstruction_bounce) PUSHFRAMEINSVC mov r0, sp adr lr, exception_exit b _C_LABEL(undefinedinstruction) .data .align 0 /* * Indirection data * 2 words use for preserving r0 and r1 * 3rd word contains the undefined handler address. */ Lundefined_handler_indirection_data: .word 0 .word 0 .global _C_LABEL(undefined_handler_address) _C_LABEL(undefined_handler_address): .word _C_LABEL(undefinedinstruction_bounce) END(undefinedinstruction_bounce) Index: head/sys/arm/include/asmacros.h =================================================================== --- head/sys/arm/include/asmacros.h (revision 252310) +++ head/sys/arm/include/asmacros.h (revision 252311) @@ -1,259 +1,268 @@ /* $NetBSD: frame.h,v 1.6 2003/10/05 19:44:58 matt Exp $ */ /*- * Copyright (c) 1994-1997 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_ASMACROS_H_ #define _MACHINE_ASMACROS_H_ #include #ifdef _KERNEL #ifdef LOCORE #include "opt_global.h" /* * ASM macros for pushing and pulling trapframes from the stack * * These macros are used to handle the irqframe and trapframe structures * defined above. */ /* * PUSHFRAME - macro to push a trap frame on the stack in the current mode * Since the current mode is used, the SVC lr field is not defined. * * NOTE: r13 and r14 are stored separately as a work around for the * SA110 rev 2 STM^ bug */ #ifdef ARM_TP_ADDRESS #define PUSHFRAME \ str lr, [sp, #-4]!; /* Push the return address */ \ sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ stmia sp, {r0-r12}; /* Push the user mode registers */ \ add r0, sp, #(4*13); /* Adjust the stack pointer */ \ stmia r0, {r13-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ mrs r0, spsr_all; /* Put the SPSR on the stack */ \ str r0, [sp, #-4]!; \ ldr r0, =ARM_RAS_START; \ mov r1, #0; \ str r1, [r0]; \ mov r1, #0xffffffff; \ str r1, [r0, #4]; #else #define PUSHFRAME \ str lr, [sp, #-4]!; /* Push the return address */ \ sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ stmia sp, {r0-r12}; /* Push the user mode registers */ \ add r0, sp, #(4*13); /* Adjust the stack pointer */ \ stmia r0, {r13-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ mrs r0, spsr_all; /* Put the SPSR on the stack */ \ str r0, [sp, #-4]!; #endif /* * PULLFRAME - macro to pull a trap frame from the stack in the current mode * Since the current mode is used, the SVC lr field is ignored. */ #ifdef ARM_TP_ADDRESS #define PULLFRAME \ ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ msr spsr_all, r0; \ ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ mov r0, r0; /* NOP for previous instruction */ \ add sp, sp, #(4*17); /* Adjust the stack pointer */ \ ldr lr, [sp], #0x0004; /* Pull the return address */ #else #define PULLFRAME \ ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ msr spsr_all, r0; \ clrex; \ ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ mov r0, r0; /* NOP for previous instruction */ \ add sp, sp, #(4*17); /* Adjust the stack pointer */ \ ldr lr, [sp], #0x0004; /* Pull the return address */ #endif /* * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode * This should only be used if the processor is not currently in SVC32 * mode. The processor mode is switched to SVC mode and the trap frame is * stored. The SVC lr field is used to store the previous value of * lr in SVC mode. * * NOTE: r13 and r14 are stored separately as a work around for the * SA110 rev 2 STM^ bug */ #ifdef ARM_TP_ADDRESS #define PUSHFRAMEINSVC \ stmdb sp, {r0-r3}; /* Save 4 registers */ \ mov r0, lr; /* Save xxx32 r14 */ \ mov r1, sp; /* Save xxx32 sp */ \ mrs r3, spsr; /* Save xxx32 spsr */ \ mrs r2, cpsr; /* Get the CPSR */ \ bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ orr r2, r2, #(PSR_SVC32_MODE); \ msr cpsr_c, r2; /* Punch into SVC mode */ \ mov r2, sp; /* Save SVC sp */ \ str r0, [sp, #-4]!; /* Push return address */ \ str lr, [sp, #-4]!; /* Push SVC lr */ \ str r2, [sp, #-4]!; /* Push SVC sp */ \ msr spsr_all, r3; /* Restore correct spsr */ \ ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ stmia sp, {r0-r12}; /* Push the user mode registers */ \ add r0, sp, #(4*13); /* Adjust the stack pointer */ \ stmia r0, {r13-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \ ldr r4, [r5, #4]; /* reset it to point at the */ \ cmp r4, #0xffffffff; /* end of memory if necessary; */ \ movne r1, #0xffffffff; /* leave value in r4 for later */ \ strne r1, [r5, #4]; /* comparision against PC. */ \ ldr r3, [r5]; /* Retrieve global RAS_START */ \ cmp r3, #0; /* and reset it if non-zero. */ \ movne r1, #0; /* If non-zero RAS_START and */ \ strne r1, [r5]; /* PC was lower than RAS_END, */ \ ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \ cmpne r4, r1; /* execution later resumes at */ \ strhi r3, [r0, #16]; /* the RAS_START location. */ \ mrs r0, spsr_all; \ str r0, [sp, #-4]! #else #define PUSHFRAMEINSVC \ stmdb sp, {r0-r3}; /* Save 4 registers */ \ mov r0, lr; /* Save xxx32 r14 */ \ mov r1, sp; /* Save xxx32 sp */ \ mrs r3, spsr; /* Save xxx32 spsr */ \ mrs r2, cpsr; /* Get the CPSR */ \ bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ orr r2, r2, #(PSR_SVC32_MODE); \ msr cpsr_c, r2; /* Punch into SVC mode */ \ mov r2, sp; /* Save SVC sp */ \ str r0, [sp, #-4]!; /* Push return address */ \ str lr, [sp, #-4]!; /* Push SVC lr */ \ str r2, [sp, #-4]!; /* Push SVC sp */ \ msr spsr_all, r3; /* Restore correct spsr */ \ ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ stmia sp, {r0-r12}; /* Push the user mode registers */ \ add r0, sp, #(4*13); /* Adjust the stack pointer */ \ stmia r0, {r13-r14}^; /* Push the user mode registers */ \ mov r0, r0; /* NOP for previous instruction */ \ mrs r0, spsr_all; /* Put the SPSR on the stack */ \ str r0, [sp, #-4]! #endif /* * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack * in SVC32 mode and restore the saved processor mode and PC. * This should be used when the SVC lr register needs to be restored on * exit. */ #ifdef ARM_TP_ADDRESS #define PULLFRAMEFROMSVCANDEXIT \ ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ msr spsr_all, r0; /* restore SPSR */ \ ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ mov r0, r0; /* NOP for previous instruction */ \ add sp, sp, #(4*15); /* Adjust the stack pointer */ \ ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ #else #define PULLFRAMEFROMSVCANDEXIT \ ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ msr spsr_all, r0; /* restore SPSR */ \ clrex; \ ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ mov r0, r0; /* NOP for previous instruction */ \ add sp, sp, #(4*15); /* Adjust the stack pointer */ \ ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ -#endif +#endif +#if defined(__ARM_EABI__) +#define UNWINDSVCFRAME \ + .save {r13-r15}; /* Restore sp, lr, pc */ \ + .pad #(2*4); /* Skip user sp and lr */ \ + .save {r0-r12}; /* Restore r0-r12 */ \ + .pad #(4) /* Skip spsr */ +#else +#define UNWINDSVCFRAME +#endif #define DATA(name) \ .data ; \ _ALIGN_DATA ; \ .globl name ; \ .type name, %object ; \ name: #ifdef _ARM_ARCH_6 #define AST_LOCALS #define GET_CURTHREAD_PTR(tmp) \ mrc p15, 0, tmp, c13, c0, 4; \ add tmp, tmp, #(PC_CURTHREAD) #else #define AST_LOCALS ;\ .Lcurthread: ;\ .word _C_LABEL(__pcpu) + PC_CURTHREAD #define GET_CURTHREAD_PTR(tmp) \ ldr tmp, .Lcurthread #endif #define DO_AST \ ldr r0, [sp] /* Get the SPSR from stack */ ;\ mrs r4, cpsr /* save CPSR */ ;\ orr r1, r4, #(I32_bit|F32_bit) ;\ msr cpsr_c, r1 /* Disable interrupts */ ;\ and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ teq r0, #(PSR_USR32_MODE) ;\ bne 2f /* Nope, get out now */ ;\ bic r4, r4, #(I32_bit|F32_bit) ;\ 1: GET_CURTHREAD_PTR(r5) ;\ ldr r5, [r5] ;\ ldr r1, [r5, #(TD_FLAGS)] ;\ and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED) ;\ teq r1, #0x00000000 ;\ beq 2f /* Nope. Just bail */ ;\ msr cpsr_c, r4 /* Restore interrupts */ ;\ mov r0, sp ;\ bl _C_LABEL(ast) /* ast(frame) */ ;\ orr r0, r4, #(I32_bit|F32_bit) ;\ msr cpsr_c, r0 ;\ b 1b ;\ 2: #endif /* LOCORE */ #endif /* _KERNEL */ #endif /* !_MACHINE_ASMACROS_H_ */