Index: stable/9/lib/libpmc/Makefile =================================================================== --- stable/9/lib/libpmc/Makefile (revision 242593) +++ stable/9/lib/libpmc/Makefile (revision 242594) @@ -1,76 +1,77 @@ # $FreeBSD$ LIB= pmc SRCS= libpmc.c pmclog.c INCS= pmc.h pmclog.h MAN= pmc.3 MAN+= pmc_allocate.3 MAN+= pmc_attach.3 MAN+= pmc_capabilities.3 MAN+= pmc_configure_logfile.3 MAN+= pmc_disable.3 MAN+= pmc_event_names_of_class.3 MAN+= pmc_get_driver_stats.3 MAN+= pmc_get_msr.3 MAN+= pmc_init.3 MAN+= pmc_name_of_capability.3 MAN+= pmc_read.3 MAN+= pmc_set.3 MAN+= pmc_start.3 MAN+= pmclog.3 MAN+= pmc.soft.3 # PMC-dependent manual pages .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" MAN+= pmc.atom.3 MAN+= pmc.core.3 MAN+= pmc.core2.3 MAN+= pmc.iaf.3 MAN+= pmc.ivybridge.3 MAN+= pmc.ucf.3 MAN+= pmc.k7.3 MAN+= pmc.k8.3 MAN+= pmc.p4.3 MAN+= pmc.p5.3 MAN+= pmc.p6.3 MAN+= pmc.corei7.3 MAN+= pmc.corei7uc.3 MAN+= pmc.sandybridge.3 MAN+= pmc.sandybridgeuc.3 +MAN+= pmc.sandybridgexeon.3 MAN+= pmc.westmere.3 MAN+= pmc.westmereuc.3 MAN+= pmc.tsc.3 .elif ${MACHINE_CPUARCH} == "arm" && ${CPUTYPE} == "xscale" MAN+= pmc.xscale.3 .endif MLINKS+= \ pmc_allocate.3 pmc_release.3 \ pmc_attach.3 pmc_detach.3 \ pmc_capabilities.3 pmc_ncpu.3 \ pmc_capabilities.3 pmc_npmc.3 \ pmc_capabilities.3 pmc_pmcinfo.3 \ pmc_capabilities.3 pmc_cpuinfo.3 \ pmc_capabilities.3 pmc_width.3 \ pmc_configure_logfile.3 pmc_flush_logfile.3 \ pmc_configure_logfile.3 pmc_writelog.3 \ pmc_disable.3 pmc_enable.3 \ pmc_name_of_capability.3 pmc_name_of_class.3 \ pmc_name_of_capability.3 pmc_name_of_cputype.3 \ pmc_name_of_capability.3 pmc_name_of_disposition.3 \ pmc_name_of_capability.3 pmc_name_of_event.3 \ pmc_name_of_capability.3 pmc_name_of_mode.3 \ pmc_name_of_capability.3 pmc_name_of_state.3 \ pmc_read.3 pmc_rw.3 \ pmc_read.3 pmc_write.3 \ pmc_start.3 pmc_stop.3 MLINKS+= \ pmclog.3 pmclog_open.3 \ pmclog.3 pmclog_close.3 \ pmclog.3 pmclog_feed.3 \ pmclog.3 pmclog_read.3 .include Index: stable/9/lib/libpmc/libpmc.c =================================================================== --- stable/9/lib/libpmc/libpmc.c (revision 242593) +++ stable/9/lib/libpmc/libpmc.c (revision 242594) @@ -1,3356 +1,3377 @@ /*- * Copyright (c) 2003-2008 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "libpmcinternal.h" /* Function prototypes */ #if defined(__i386__) static int k7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__amd64__) || defined(__i386__) static int iaf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__i386__) static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__amd64__) || defined(__i386__) static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__XSCALE__) static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif #if defined(__mips__) static int mips24k_allocate_pmc(enum pmc_event _pe, char* ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif /* __mips__ */ static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #if defined(__powerpc__) static int ppc7450_allocate_pmc(enum pmc_event _pe, char* ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif /* __powerpc__ */ #define PMC_CALL(cmd, params) \ syscall(pmc_syscall, PMC_OP_##cmd, (params)) /* * Event aliases provide a way for the user to ask for generic events * like "cache-misses", or "instructions-retired". These aliases are * mapped to the appropriate canonical event descriptions using a * lookup table. */ struct pmc_event_alias { const char *pm_alias; const char *pm_spec; }; static const struct pmc_event_alias *pmc_mdep_event_aliases; /* * The pmc_event_descr structure maps symbolic names known to the user * to integer codes used by the PMC KLD. */ struct pmc_event_descr { const char *pm_ev_name; enum pmc_event pm_ev_code; }; /* * The pmc_class_descr structure maps class name prefixes for * event names to event tables and other PMC class data. */ struct pmc_class_descr { const char *pm_evc_name; size_t pm_evc_name_size; enum pmc_class pm_evc_class; const struct pmc_event_descr *pm_evc_event_table; size_t pm_evc_event_table_size; int (*pm_evc_allocate_pmc)(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pa); }; #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0])) #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table) #undef __PMC_EV #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N }, /* * PMC_CLASSDEP_TABLE(NAME, CLASS) * * Define a table mapping event names and aliases to HWPMC event IDs. */ #define PMC_CLASSDEP_TABLE(N, C) \ static const struct pmc_event_descr N##_event_table[] = \ { \ __PMC_EV_##C() \ } PMC_CLASSDEP_TABLE(iaf, IAF); PMC_CLASSDEP_TABLE(k7, K7); PMC_CLASSDEP_TABLE(k8, K8); PMC_CLASSDEP_TABLE(p4, P4); PMC_CLASSDEP_TABLE(p5, P5); PMC_CLASSDEP_TABLE(p6, P6); PMC_CLASSDEP_TABLE(xscale, XSCALE); PMC_CLASSDEP_TABLE(mips24k, MIPS24K); PMC_CLASSDEP_TABLE(ucf, UCF); PMC_CLASSDEP_TABLE(ppc7450, PPC7450); static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT]; #undef __PMC_EV_ALIAS #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE }, static const struct pmc_event_descr atom_event_table[] = { __PMC_EV_ALIAS_ATOM() }; static const struct pmc_event_descr core_event_table[] = { __PMC_EV_ALIAS_CORE() }; static const struct pmc_event_descr core2_event_table[] = { __PMC_EV_ALIAS_CORE2() }; static const struct pmc_event_descr corei7_event_table[] = { __PMC_EV_ALIAS_COREI7() }; static const struct pmc_event_descr ivybridge_event_table[] = { __PMC_EV_ALIAS_IVYBRIDGE() }; static const struct pmc_event_descr sandybridge_event_table[] = { __PMC_EV_ALIAS_SANDYBRIDGE() }; +static const struct pmc_event_descr sandybridge_xeon_event_table[] = +{ + __PMC_EV_ALIAS_SANDYBRIDGE_XEON() +}; + static const struct pmc_event_descr westmere_event_table[] = { __PMC_EV_ALIAS_WESTMERE() }; static const struct pmc_event_descr corei7uc_event_table[] = { __PMC_EV_ALIAS_COREI7UC() }; static const struct pmc_event_descr sandybridgeuc_event_table[] = { __PMC_EV_ALIAS_SANDYBRIDGEUC() }; static const struct pmc_event_descr westmereuc_event_table[] = { __PMC_EV_ALIAS_WESTMEREUC() }; /* * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) * * Map a CPU to the PMC classes it supports. */ #define PMC_MDEP_TABLE(N,C,...) \ static const enum pmc_class N##_pmc_classes[] = { \ PMC_CLASS_##C, __VA_ARGS__ \ } PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); +PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450); PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); static const struct pmc_event_descr tsc_event_table[] = { __PMC_EV_TSC() }; #undef PMC_CLASS_TABLE_DESC #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \ static const struct pmc_class_descr NAME##_class_table_descr = \ { \ .pm_evc_name = #CLASS "-", \ .pm_evc_name_size = sizeof(#CLASS "-") - 1, \ .pm_evc_class = PMC_CLASS_##CLASS , \ .pm_evc_event_table = EVENTS##_event_table , \ .pm_evc_event_table_size = \ PMC_EVENT_TABLE_SIZE(EVENTS), \ .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \ } #if defined(__i386__) || defined(__amd64__) PMC_CLASS_TABLE_DESC(iaf, IAF, iaf, iaf); PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); PMC_CLASS_TABLE_DESC(core, IAP, core, iap); PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); +PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); #endif #if defined(__i386__) PMC_CLASS_TABLE_DESC(k7, K7, k7, k7); #endif #if defined(__i386__) || defined(__amd64__) PMC_CLASS_TABLE_DESC(k8, K8, k8, k8); PMC_CLASS_TABLE_DESC(p4, P4, p4, p4); #endif #if defined(__i386__) PMC_CLASS_TABLE_DESC(p5, P5, p5, p5); PMC_CLASS_TABLE_DESC(p6, P6, p6, p6); #endif #if defined(__i386__) || defined(__amd64__) PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); #endif #if defined(__XSCALE__) PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); #endif #if defined(__mips__) PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips24k); #endif /* __mips__ */ #if defined(__powerpc__) PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, ppc7450); #endif static struct pmc_class_descr soft_class_table_descr = { .pm_evc_name = "SOFT-", .pm_evc_name_size = sizeof("SOFT-") - 1, .pm_evc_class = PMC_CLASS_SOFT, .pm_evc_event_table = NULL, .pm_evc_event_table_size = 0, .pm_evc_allocate_pmc = soft_allocate_pmc }; #undef PMC_CLASS_TABLE_DESC static const struct pmc_class_descr **pmc_class_table; #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass static const enum pmc_class *pmc_mdep_class_list; static size_t pmc_mdep_class_list_size; /* * Mapping tables, mapping enumeration values to human readable * strings. */ static const char * pmc_capability_names[] = { #undef __PMC_CAP #define __PMC_CAP(N,V,D) #N , __PMC_CAPS() }; static const char * pmc_class_names[] = { #undef __PMC_CLASS #define __PMC_CLASS(C) #C , __PMC_CLASSES() }; struct pmc_cputype_map { enum pmc_cputype pm_cputype; const char *pm_name; }; static const struct pmc_cputype_map pmc_cputype_names[] = { #undef __PMC_CPU #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } , __PMC_CPUS() }; static const char * pmc_disposition_names[] = { #undef __PMC_DISP #define __PMC_DISP(D) #D , __PMC_DISPOSITIONS() }; static const char * pmc_mode_names[] = { #undef __PMC_MODE #define __PMC_MODE(M,N) #M , __PMC_MODES() }; static const char * pmc_state_names[] = { #undef __PMC_STATE #define __PMC_STATE(S) #S , __PMC_STATES() }; /* * Filled in by pmc_init(). */ static int pmc_syscall = -1; static struct pmc_cpuinfo cpu_info; static struct pmc_op_getdyneventinfo soft_event_info; /* Event masks for events */ struct pmc_masks { const char *pm_name; const uint64_t pm_value; }; #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) } #define NULLMASK { .pm_name = NULL } #if defined(__amd64__) || defined(__i386__) static int pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask) { const struct pmc_masks *pm; char *q, *r; int c; if (pmask == NULL) /* no mask keywords */ return (-1); q = strchr(p, '='); /* skip '=' */ if (*++q == '\0') /* no more data */ return (-1); c = 0; /* count of mask keywords seen */ while ((r = strsep(&q, "+")) != NULL) { for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name); pm++) ; if (pm->pm_name == NULL) /* not found */ return (-1); *evmask |= pm->pm_value; c++; } return (c); } #endif #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0) #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0) #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S } #if defined(__i386__) /* * AMD K7 (Athlon) CPUs. */ static struct pmc_event_alias k7_aliases[] = { EV_ALIAS("branches", "k7-retired-branches"), EV_ALIAS("branch-mispredicts", "k7-retired-branches-mispredicted"), EV_ALIAS("cycles", "tsc"), EV_ALIAS("dc-misses", "k7-dc-misses"), EV_ALIAS("ic-misses", "k7-ic-misses"), EV_ALIAS("instructions", "k7-retired-instructions"), EV_ALIAS("interrupts", "k7-hardware-interrupts"), EV_ALIAS(NULL, NULL) }; #define K7_KW_COUNT "count" #define K7_KW_EDGE "edge" #define K7_KW_INV "inv" #define K7_KW_OS "os" #define K7_KW_UNITMASK "unitmask" #define K7_KW_USR "usr" static int k7_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { char *e, *p, *q; int c, has_unitmask; uint32_t count, unitmask; pmc_config->pm_md.pm_amd.pm_amd_config = 0; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); if (pe == PMC_EV_K7_DC_REFILLS_FROM_L2 || pe == PMC_EV_K7_DC_REFILLS_FROM_SYSTEM || pe == PMC_EV_K7_DC_WRITEBACKS) { has_unitmask = 1; unitmask = AMD_PMC_UNITMASK_MOESI; } else unitmask = has_unitmask = 0; while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWPREFIXMATCH(p, K7_KW_COUNT "=")) { q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); pmc_config->pm_caps |= PMC_CAP_THRESHOLD; pmc_config->pm_md.pm_amd.pm_amd_config |= AMD_PMC_TO_COUNTER(count); } else if (KWMATCH(p, K7_KW_EDGE)) { pmc_config->pm_caps |= PMC_CAP_EDGE; } else if (KWMATCH(p, K7_KW_INV)) { pmc_config->pm_caps |= PMC_CAP_INVERT; } else if (KWMATCH(p, K7_KW_OS)) { pmc_config->pm_caps |= PMC_CAP_SYSTEM; } else if (KWPREFIXMATCH(p, K7_KW_UNITMASK "=")) { if (has_unitmask == 0) return (-1); unitmask = 0; q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); while ((c = tolower(*q++)) != 0) if (c == 'm') unitmask |= AMD_PMC_UNITMASK_M; else if (c == 'o') unitmask |= AMD_PMC_UNITMASK_O; else if (c == 'e') unitmask |= AMD_PMC_UNITMASK_E; else if (c == 's') unitmask |= AMD_PMC_UNITMASK_S; else if (c == 'i') unitmask |= AMD_PMC_UNITMASK_I; else if (c == '+') continue; else return (-1); if (unitmask == 0) return (-1); } else if (KWMATCH(p, K7_KW_USR)) { pmc_config->pm_caps |= PMC_CAP_USER; } else return (-1); } if (has_unitmask) { pmc_config->pm_caps |= PMC_CAP_QUALIFIER; pmc_config->pm_md.pm_amd.pm_amd_config |= AMD_PMC_TO_UNITMASK(unitmask); } return (0); } #endif #if defined(__amd64__) || defined(__i386__) /* * Intel Core (Family 6, Model E) PMCs. */ static struct pmc_event_alias core_aliases[] = { EV_ALIAS("branches", "iap-br-instr-ret"), EV_ALIAS("branch-mispredicts", "iap-br-mispred-ret"), EV_ALIAS("cycles", "tsc-tsc"), EV_ALIAS("ic-misses", "iap-icache-misses"), EV_ALIAS("instructions", "iap-instr-ret"), EV_ALIAS("interrupts", "iap-core-hw-int-rx"), EV_ALIAS("unhalted-cycles", "iap-unhalted-core-cycles"), EV_ALIAS(NULL, NULL) }; /* * Intel Core2 (Family 6, Model F), Core2Extreme (Family 6, Model 17H) * and Atom (Family 6, model 1CH) PMCs. * * We map aliases to events on the fixed-function counters if these * are present. Note that not all CPUs in this family contain fixed-function * counters. */ static struct pmc_event_alias core2_aliases[] = { EV_ALIAS("branches", "iap-br-inst-retired.any"), EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), EV_ALIAS("cycles", "tsc-tsc"), EV_ALIAS("ic-misses", "iap-l1i-misses"), EV_ALIAS("instructions", "iaf-instr-retired.any"), EV_ALIAS("interrupts", "iap-hw-int-rcv"), EV_ALIAS("unhalted-cycles", "iaf-cpu-clk-unhalted.core"), EV_ALIAS(NULL, NULL) }; static struct pmc_event_alias core2_aliases_without_iaf[] = { EV_ALIAS("branches", "iap-br-inst-retired.any"), EV_ALIAS("branch-mispredicts", "iap-br-inst-retired.mispred"), EV_ALIAS("cycles", "tsc-tsc"), EV_ALIAS("ic-misses", "iap-l1i-misses"), EV_ALIAS("instructions", "iap-inst-retired.any_p"), EV_ALIAS("interrupts", "iap-hw-int-rcv"), EV_ALIAS("unhalted-cycles", "iap-cpu-clk-unhalted.core_p"), EV_ALIAS(NULL, NULL) }; #define atom_aliases core2_aliases #define atom_aliases_without_iaf core2_aliases_without_iaf #define corei7_aliases core2_aliases #define corei7_aliases_without_iaf core2_aliases_without_iaf #define ivybridge_aliases core2_aliases #define ivybridge_aliases_without_iaf core2_aliases_without_iaf #define sandybridge_aliases core2_aliases #define sandybridge_aliases_without_iaf core2_aliases_without_iaf +#define sandybridge_xeon_aliases core2_aliases +#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf #define westmere_aliases core2_aliases #define westmere_aliases_without_iaf core2_aliases_without_iaf #define IAF_KW_OS "os" #define IAF_KW_USR "usr" #define IAF_KW_ANYTHREAD "anythread" /* * Parse an event specifier for Intel fixed function counters. */ static int iaf_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { char *p; (void) pe; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); pmc_config->pm_md.pm_iaf.pm_iaf_flags = 0; while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWMATCH(p, IAF_KW_OS)) pmc_config->pm_caps |= PMC_CAP_SYSTEM; else if (KWMATCH(p, IAF_KW_USR)) pmc_config->pm_caps |= PMC_CAP_USER; else if (KWMATCH(p, IAF_KW_ANYTHREAD)) pmc_config->pm_md.pm_iaf.pm_iaf_flags |= IAF_ANY; else return (-1); } return (0); } /* * Core/Core2 support. */ #define IAP_KW_AGENT "agent" #define IAP_KW_ANYTHREAD "anythread" #define IAP_KW_CACHESTATE "cachestate" #define IAP_KW_CMASK "cmask" #define IAP_KW_CORE "core" #define IAP_KW_EDGE "edge" #define IAP_KW_INV "inv" #define IAP_KW_OS "os" #define IAP_KW_PREFETCH "prefetch" #define IAP_KW_SNOOPRESPONSE "snoopresponse" #define IAP_KW_SNOOPTYPE "snooptype" #define IAP_KW_TRANSITION "trans" #define IAP_KW_USR "usr" #define IAP_KW_RSP "rsp" static struct pmc_masks iap_core_mask[] = { PMCMASK(all, (0x3 << 14)), PMCMASK(this, (0x1 << 14)), NULLMASK }; static struct pmc_masks iap_agent_mask[] = { PMCMASK(this, 0), PMCMASK(any, (0x1 << 13)), NULLMASK }; static struct pmc_masks iap_prefetch_mask[] = { PMCMASK(both, (0x3 << 12)), PMCMASK(only, (0x1 << 12)), PMCMASK(exclude, 0), NULLMASK }; static struct pmc_masks iap_cachestate_mask[] = { PMCMASK(i, (1 << 8)), PMCMASK(s, (1 << 9)), PMCMASK(e, (1 << 10)), PMCMASK(m, (1 << 11)), NULLMASK }; static struct pmc_masks iap_snoopresponse_mask[] = { PMCMASK(clean, (1 << 8)), PMCMASK(hit, (1 << 9)), PMCMASK(hitm, (1 << 11)), NULLMASK }; static struct pmc_masks iap_snooptype_mask[] = { PMCMASK(cmp2s, (1 << 8)), PMCMASK(cmp2i, (1 << 9)), NULLMASK }; static struct pmc_masks iap_transition_mask[] = { PMCMASK(any, 0x00), PMCMASK(frequency, 0x10), NULLMASK }; static struct pmc_masks iap_rsp_mask_i7_wm[] = { PMCMASK(DMND_DATA_RD, (1 << 0)), PMCMASK(DMND_RFO, (1 << 1)), PMCMASK(DMND_IFETCH, (1 << 2)), PMCMASK(WB, (1 << 3)), PMCMASK(PF_DATA_RD, (1 << 4)), PMCMASK(PF_RFO, (1 << 5)), PMCMASK(PF_IFETCH, (1 << 6)), PMCMASK(OTHER, (1 << 7)), PMCMASK(UNCORE_HIT, (1 << 8)), PMCMASK(OTHER_CORE_HIT_SNP, (1 << 9)), PMCMASK(OTHER_CORE_HITM, (1 << 10)), PMCMASK(REMOTE_CACHE_FWD, (1 << 12)), PMCMASK(REMOTE_DRAM, (1 << 13)), PMCMASK(LOCAL_DRAM, (1 << 14)), PMCMASK(NON_DRAM, (1 << 15)), NULLMASK }; -static struct pmc_masks iap_rsp_mask_sb_ib[] = { +static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), PMCMASK(REQ_DMND_RFO, (1ULL << 1)), PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), PMCMASK(REQ_WB, (1ULL << 3)), PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), PMCMASK(REQ_PF_RFO, (1ULL << 5)), PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), PMCMASK(REQ_PF_LLC_DATA_RD, (1ULL << 7)), PMCMASK(REQ_PF_LLC_RFO, (1ULL << 8)), PMCMASK(REQ_PF_LLC_IFETCH, (1ULL << 9)), PMCMASK(REQ_BUS_LOCKS, (1ULL << 10)), PMCMASK(REQ_STRM_ST, (1ULL << 11)), PMCMASK(REQ_OTHER, (1ULL << 15)), PMCMASK(RES_ANY, (1ULL << 16)), PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), PMCMASK(RES_SNOOP_SNPI_NONE, (1ULL << 31)), PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), PMCMASK(RES_NON_DRAM, (1ULL << 37)), NULLMASK }; static int iap_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { char *e, *p, *q; uint64_t cachestate, evmask, rsp; int count, n; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_QUALIFIER); pmc_config->pm_md.pm_iap.pm_iap_config = 0; cachestate = evmask = rsp = 0; /* Parse additional modifiers if present */ while ((p = strsep(&ctrspec, ",")) != NULL) { n = 0; if (KWPREFIXMATCH(p, IAP_KW_CMASK "=")) { q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); pmc_config->pm_caps |= PMC_CAP_THRESHOLD; pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_CMASK(count); } else if (KWMATCH(p, IAP_KW_EDGE)) { pmc_config->pm_caps |= PMC_CAP_EDGE; } else if (KWMATCH(p, IAP_KW_INV)) { pmc_config->pm_caps |= PMC_CAP_INVERT; } else if (KWMATCH(p, IAP_KW_OS)) { pmc_config->pm_caps |= PMC_CAP_SYSTEM; } else if (KWMATCH(p, IAP_KW_USR)) { pmc_config->pm_caps |= PMC_CAP_USER; } else if (KWMATCH(p, IAP_KW_ANYTHREAD)) { pmc_config->pm_md.pm_iap.pm_iap_config |= IAP_ANY; } else if (KWPREFIXMATCH(p, IAP_KW_CORE "=")) { n = pmc_parse_mask(iap_core_mask, p, &evmask); if (n != 1) return (-1); } else if (KWPREFIXMATCH(p, IAP_KW_AGENT "=")) { n = pmc_parse_mask(iap_agent_mask, p, &evmask); if (n != 1) return (-1); } else if (KWPREFIXMATCH(p, IAP_KW_PREFETCH "=")) { n = pmc_parse_mask(iap_prefetch_mask, p, &evmask); if (n != 1) return (-1); } else if (KWPREFIXMATCH(p, IAP_KW_CACHESTATE "=")) { n = pmc_parse_mask(iap_cachestate_mask, p, &cachestate); } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_CORE && KWPREFIXMATCH(p, IAP_KW_TRANSITION "=")) { n = pmc_parse_mask(iap_transition_mask, p, &evmask); if (n != 1) return (-1); } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM || cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2 || cpu_info.pm_cputype == PMC_CPU_INTEL_CORE2EXTREME) { if (KWPREFIXMATCH(p, IAP_KW_SNOOPRESPONSE "=")) { n = pmc_parse_mask(iap_snoopresponse_mask, p, &evmask); } else if (KWPREFIXMATCH(p, IAP_KW_SNOOPTYPE "=")) { n = pmc_parse_mask(iap_snooptype_mask, p, &evmask); } else return (-1); } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_COREI7 || cpu_info.pm_cputype == PMC_CPU_INTEL_WESTMERE) { if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { n = pmc_parse_mask(iap_rsp_mask_i7_wm, p, &rsp); } else return (-1); } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE || - cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE) { + cpu_info.pm_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || + cpu_info.pm_cputype == PMC_CPU_INTEL_IVYBRIDGE) { if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { - n = pmc_parse_mask(iap_rsp_mask_sb_ib, p, &rsp); + n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); } else return (-1); } else return (-1); if (n < 0) /* Parsing failed. */ return (-1); } pmc_config->pm_md.pm_iap.pm_iap_config |= evmask; /* * If the event requires a 'cachestate' qualifier but was not * specified by the user, use a sensible default. */ switch (pe) { case PMC_EV_IAP_EVENT_28H: /* Core, Core2, Atom */ case PMC_EV_IAP_EVENT_29H: /* Core, Core2, Atom */ case PMC_EV_IAP_EVENT_2AH: /* Core, Core2, Atom */ case PMC_EV_IAP_EVENT_2BH: /* Atom, Core2 */ case PMC_EV_IAP_EVENT_2EH: /* Core, Core2, Atom */ case PMC_EV_IAP_EVENT_30H: /* Core, Core2, Atom */ case PMC_EV_IAP_EVENT_32H: /* Core */ case PMC_EV_IAP_EVENT_40H: /* Core */ case PMC_EV_IAP_EVENT_41H: /* Core */ case PMC_EV_IAP_EVENT_42H: /* Core, Core2, Atom */ if (cachestate == 0) cachestate = (0xF << 8); break; case PMC_EV_IAP_EVENT_77H: /* Atom */ /* IAP_EVENT_77H only accepts a cachestate qualifier on the * Atom processor */ if(cpu_info.pm_cputype == PMC_CPU_INTEL_ATOM && cachestate == 0) cachestate = (0xF << 8); break; default: break; } pmc_config->pm_md.pm_iap.pm_iap_config |= cachestate; pmc_config->pm_md.pm_iap.pm_iap_rsp = rsp; return (0); } /* * Intel Uncore. */ static int ucf_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { (void) pe; (void) ctrspec; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); pmc_config->pm_md.pm_ucf.pm_ucf_flags = 0; return (0); } #define UCP_KW_CMASK "cmask" #define UCP_KW_EDGE "edge" #define UCP_KW_INV "inv" static int ucp_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { char *e, *p, *q; int count, n; (void) pe; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_QUALIFIER); pmc_config->pm_md.pm_ucp.pm_ucp_config = 0; /* Parse additional modifiers if present */ while ((p = strsep(&ctrspec, ",")) != NULL) { n = 0; if (KWPREFIXMATCH(p, UCP_KW_CMASK "=")) { q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); pmc_config->pm_caps |= PMC_CAP_THRESHOLD; pmc_config->pm_md.pm_ucp.pm_ucp_config |= UCP_CMASK(count); } else if (KWMATCH(p, UCP_KW_EDGE)) { pmc_config->pm_caps |= PMC_CAP_EDGE; } else if (KWMATCH(p, UCP_KW_INV)) { pmc_config->pm_caps |= PMC_CAP_INVERT; } else return (-1); if (n < 0) /* Parsing failed. */ return (-1); } return (0); } /* * AMD K8 PMCs. * * These are very similar to AMD K7 PMCs, but support more kinds of * events. */ static struct pmc_event_alias k8_aliases[] = { EV_ALIAS("branches", "k8-fr-retired-taken-branches"), EV_ALIAS("branch-mispredicts", "k8-fr-retired-taken-branches-mispredicted"), EV_ALIAS("cycles", "tsc"), EV_ALIAS("dc-misses", "k8-dc-miss"), EV_ALIAS("ic-misses", "k8-ic-miss"), EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"), EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"), EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"), EV_ALIAS(NULL, NULL) }; #define __K8MASK(N,V) PMCMASK(N,(1 << (V))) /* * Parsing tables */ /* fp dispatched fpu ops */ static const struct pmc_masks k8_mask_fdfo[] = { __K8MASK(add-pipe-excluding-junk-ops, 0), __K8MASK(multiply-pipe-excluding-junk-ops, 1), __K8MASK(store-pipe-excluding-junk-ops, 2), __K8MASK(add-pipe-junk-ops, 3), __K8MASK(multiply-pipe-junk-ops, 4), __K8MASK(store-pipe-junk-ops, 5), NULLMASK }; /* ls segment register loads */ static const struct pmc_masks k8_mask_lsrl[] = { __K8MASK(es, 0), __K8MASK(cs, 1), __K8MASK(ss, 2), __K8MASK(ds, 3), __K8MASK(fs, 4), __K8MASK(gs, 5), __K8MASK(hs, 6), NULLMASK }; /* ls locked operation */ static const struct pmc_masks k8_mask_llo[] = { __K8MASK(locked-instructions, 0), __K8MASK(cycles-in-request, 1), __K8MASK(cycles-to-complete, 2), NULLMASK }; /* dc refill from {l2,system} and dc copyback */ static const struct pmc_masks k8_mask_dc[] = { __K8MASK(invalid, 0), __K8MASK(shared, 1), __K8MASK(exclusive, 2), __K8MASK(owner, 3), __K8MASK(modified, 4), NULLMASK }; /* dc one bit ecc error */ static const struct pmc_masks k8_mask_dobee[] = { __K8MASK(scrubber, 0), __K8MASK(piggyback, 1), NULLMASK }; /* dc dispatched prefetch instructions */ static const struct pmc_masks k8_mask_ddpi[] = { __K8MASK(load, 0), __K8MASK(store, 1), __K8MASK(nta, 2), NULLMASK }; /* dc dcache accesses by locks */ static const struct pmc_masks k8_mask_dabl[] = { __K8MASK(accesses, 0), __K8MASK(misses, 1), NULLMASK }; /* bu internal l2 request */ static const struct pmc_masks k8_mask_bilr[] = { __K8MASK(ic-fill, 0), __K8MASK(dc-fill, 1), __K8MASK(tlb-reload, 2), __K8MASK(tag-snoop, 3), __K8MASK(cancelled, 4), NULLMASK }; /* bu fill request l2 miss */ static const struct pmc_masks k8_mask_bfrlm[] = { __K8MASK(ic-fill, 0), __K8MASK(dc-fill, 1), __K8MASK(tlb-reload, 2), NULLMASK }; /* bu fill into l2 */ static const struct pmc_masks k8_mask_bfil[] = { __K8MASK(dirty-l2-victim, 0), __K8MASK(victim-from-l2, 1), NULLMASK }; /* fr retired fpu instructions */ static const struct pmc_masks k8_mask_frfi[] = { __K8MASK(x87, 0), __K8MASK(mmx-3dnow, 1), __K8MASK(packed-sse-sse2, 2), __K8MASK(scalar-sse-sse2, 3), NULLMASK }; /* fr retired fastpath double op instructions */ static const struct pmc_masks k8_mask_frfdoi[] = { __K8MASK(low-op-pos-0, 0), __K8MASK(low-op-pos-1, 1), __K8MASK(low-op-pos-2, 2), NULLMASK }; /* fr fpu exceptions */ static const struct pmc_masks k8_mask_ffe[] = { __K8MASK(x87-reclass-microfaults, 0), __K8MASK(sse-retype-microfaults, 1), __K8MASK(sse-reclass-microfaults, 2), __K8MASK(sse-and-x87-microtraps, 3), NULLMASK }; /* nb memory controller page access event */ static const struct pmc_masks k8_mask_nmcpae[] = { __K8MASK(page-hit, 0), __K8MASK(page-miss, 1), __K8MASK(page-conflict, 2), NULLMASK }; /* nb memory controller turnaround */ static const struct pmc_masks k8_mask_nmct[] = { __K8MASK(dimm-turnaround, 0), __K8MASK(read-to-write-turnaround, 1), __K8MASK(write-to-read-turnaround, 2), NULLMASK }; /* nb memory controller bypass saturation */ static const struct pmc_masks k8_mask_nmcbs[] = { __K8MASK(memory-controller-hi-pri-bypass, 0), __K8MASK(memory-controller-lo-pri-bypass, 1), __K8MASK(dram-controller-interface-bypass, 2), __K8MASK(dram-controller-queue-bypass, 3), NULLMASK }; /* nb sized commands */ static const struct pmc_masks k8_mask_nsc[] = { __K8MASK(nonpostwrszbyte, 0), __K8MASK(nonpostwrszdword, 1), __K8MASK(postwrszbyte, 2), __K8MASK(postwrszdword, 3), __K8MASK(rdszbyte, 4), __K8MASK(rdszdword, 5), __K8MASK(rdmodwr, 6), NULLMASK }; /* nb probe result */ static const struct pmc_masks k8_mask_npr[] = { __K8MASK(probe-miss, 0), __K8MASK(probe-hit, 1), __K8MASK(probe-hit-dirty-no-memory-cancel, 2), __K8MASK(probe-hit-dirty-with-memory-cancel, 3), NULLMASK }; /* nb hypertransport bus bandwidth */ static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */ __K8MASK(command, 0), __K8MASK(data, 1), __K8MASK(buffer-release, 2), __K8MASK(nop, 3), NULLMASK }; #undef __K8MASK #define K8_KW_COUNT "count" #define K8_KW_EDGE "edge" #define K8_KW_INV "inv" #define K8_KW_MASK "mask" #define K8_KW_OS "os" #define K8_KW_USR "usr" static int k8_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { char *e, *p, *q; int n; uint32_t count; uint64_t evmask; const struct pmc_masks *pm, *pmask; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); pmc_config->pm_md.pm_amd.pm_amd_config = 0; pmask = NULL; evmask = 0; #define __K8SETMASK(M) pmask = k8_mask_##M /* setup parsing tables */ switch (pe) { case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: __K8SETMASK(fdfo); break; case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD: __K8SETMASK(lsrl); break; case PMC_EV_K8_LS_LOCKED_OPERATION: __K8SETMASK(llo); break; case PMC_EV_K8_DC_REFILL_FROM_L2: case PMC_EV_K8_DC_REFILL_FROM_SYSTEM: case PMC_EV_K8_DC_COPYBACK: __K8SETMASK(dc); break; case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR: __K8SETMASK(dobee); break; case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS: __K8SETMASK(ddpi); break; case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: __K8SETMASK(dabl); break; case PMC_EV_K8_BU_INTERNAL_L2_REQUEST: __K8SETMASK(bilr); break; case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS: __K8SETMASK(bfrlm); break; case PMC_EV_K8_BU_FILL_INTO_L2: __K8SETMASK(bfil); break; case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: __K8SETMASK(frfi); break; case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: __K8SETMASK(frfdoi); break; case PMC_EV_K8_FR_FPU_EXCEPTIONS: __K8SETMASK(ffe); break; case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT: __K8SETMASK(nmcpae); break; case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND: __K8SETMASK(nmct); break; case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION: __K8SETMASK(nmcbs); break; case PMC_EV_K8_NB_SIZED_COMMANDS: __K8SETMASK(nsc); break; case PMC_EV_K8_NB_PROBE_RESULT: __K8SETMASK(npr); break; case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH: case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH: case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH: __K8SETMASK(nhbb); break; default: break; /* no options defined */ } while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) { q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); pmc_config->pm_caps |= PMC_CAP_THRESHOLD; pmc_config->pm_md.pm_amd.pm_amd_config |= AMD_PMC_TO_COUNTER(count); } else if (KWMATCH(p, K8_KW_EDGE)) { pmc_config->pm_caps |= PMC_CAP_EDGE; } else if (KWMATCH(p, K8_KW_INV)) { pmc_config->pm_caps |= PMC_CAP_INVERT; } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) { if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) return (-1); pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } else if (KWMATCH(p, K8_KW_OS)) { pmc_config->pm_caps |= PMC_CAP_SYSTEM; } else if (KWMATCH(p, K8_KW_USR)) { pmc_config->pm_caps |= PMC_CAP_USER; } else return (-1); } /* other post processing */ switch (pe) { case PMC_EV_K8_FP_DISPATCHED_FPU_OPS: case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED: case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS: case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS: case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS: case PMC_EV_K8_FR_FPU_EXCEPTIONS: /* XXX only available in rev B and later */ break; case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS: /* XXX only available in rev C and later */ break; case PMC_EV_K8_LS_LOCKED_OPERATION: /* XXX CPU Rev A,B evmask is to be zero */ if (evmask & (evmask - 1)) /* > 1 bit set */ return (-1); if (evmask == 0) { evmask = 0x01; /* Rev C and later: #instrs */ pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } break; default: if (evmask == 0 && pmask != NULL) { for (pm = pmask; pm->pm_name; pm++) evmask |= pm->pm_value; pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } } if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) pmc_config->pm_md.pm_amd.pm_amd_config = AMD_PMC_TO_UNITMASK(evmask); return (0); } #endif #if defined(__amd64__) || defined(__i386__) /* * Intel P4 PMCs */ static struct pmc_event_alias p4_aliases[] = { EV_ALIAS("branches", "p4-branch-retired,mask=mmtp+mmtm"), EV_ALIAS("branch-mispredicts", "p4-mispred-branch-retired"), EV_ALIAS("cycles", "tsc"), EV_ALIAS("instructions", "p4-instr-retired,mask=nbogusntag+nbogustag"), EV_ALIAS("unhalted-cycles", "p4-global-power-events"), EV_ALIAS(NULL, NULL) }; #define P4_KW_ACTIVE "active" #define P4_KW_ACTIVE_ANY "any" #define P4_KW_ACTIVE_BOTH "both" #define P4_KW_ACTIVE_NONE "none" #define P4_KW_ACTIVE_SINGLE "single" #define P4_KW_BUSREQTYPE "busreqtype" #define P4_KW_CASCADE "cascade" #define P4_KW_EDGE "edge" #define P4_KW_INV "complement" #define P4_KW_OS "os" #define P4_KW_MASK "mask" #define P4_KW_PRECISE "precise" #define P4_KW_TAG "tag" #define P4_KW_THRESHOLD "threshold" #define P4_KW_USR "usr" #define __P4MASK(N,V) PMCMASK(N, (1 << (V))) static const struct pmc_masks p4_mask_tcdm[] = { /* tc deliver mode */ __P4MASK(dd, 0), __P4MASK(db, 1), __P4MASK(di, 2), __P4MASK(bd, 3), __P4MASK(bb, 4), __P4MASK(bi, 5), __P4MASK(id, 6), __P4MASK(ib, 7), NULLMASK }; static const struct pmc_masks p4_mask_bfr[] = { /* bpu fetch request */ __P4MASK(tcmiss, 0), NULLMASK, }; static const struct pmc_masks p4_mask_ir[] = { /* itlb reference */ __P4MASK(hit, 0), __P4MASK(miss, 1), __P4MASK(hit-uc, 2), NULLMASK }; static const struct pmc_masks p4_mask_memcan[] = { /* memory cancel */ __P4MASK(st-rb-full, 2), __P4MASK(64k-conf, 3), NULLMASK }; static const struct pmc_masks p4_mask_memcomp[] = { /* memory complete */ __P4MASK(lsc, 0), __P4MASK(ssc, 1), NULLMASK }; static const struct pmc_masks p4_mask_lpr[] = { /* load port replay */ __P4MASK(split-ld, 1), NULLMASK }; static const struct pmc_masks p4_mask_spr[] = { /* store port replay */ __P4MASK(split-st, 1), NULLMASK }; static const struct pmc_masks p4_mask_mlr[] = { /* mob load replay */ __P4MASK(no-sta, 1), __P4MASK(no-std, 3), __P4MASK(partial-data, 4), __P4MASK(unalgn-addr, 5), NULLMASK }; static const struct pmc_masks p4_mask_pwt[] = { /* page walk type */ __P4MASK(dtmiss, 0), __P4MASK(itmiss, 1), NULLMASK }; static const struct pmc_masks p4_mask_bcr[] = { /* bsq cache reference */ __P4MASK(rd-2ndl-hits, 0), __P4MASK(rd-2ndl-hite, 1), __P4MASK(rd-2ndl-hitm, 2), __P4MASK(rd-3rdl-hits, 3), __P4MASK(rd-3rdl-hite, 4), __P4MASK(rd-3rdl-hitm, 5), __P4MASK(rd-2ndl-miss, 8), __P4MASK(rd-3rdl-miss, 9), __P4MASK(wr-2ndl-miss, 10), NULLMASK }; static const struct pmc_masks p4_mask_ia[] = { /* ioq allocation */ __P4MASK(all-read, 5), __P4MASK(all-write, 6), __P4MASK(mem-uc, 7), __P4MASK(mem-wc, 8), __P4MASK(mem-wt, 9), __P4MASK(mem-wp, 10), __P4MASK(mem-wb, 11), __P4MASK(own, 13), __P4MASK(other, 14), __P4MASK(prefetch, 15), NULLMASK }; static const struct pmc_masks p4_mask_iae[] = { /* ioq active entries */ __P4MASK(all-read, 5), __P4MASK(all-write, 6), __P4MASK(mem-uc, 7), __P4MASK(mem-wc, 8), __P4MASK(mem-wt, 9), __P4MASK(mem-wp, 10), __P4MASK(mem-wb, 11), __P4MASK(own, 13), __P4MASK(other, 14), __P4MASK(prefetch, 15), NULLMASK }; static const struct pmc_masks p4_mask_fda[] = { /* fsb data activity */ __P4MASK(drdy-drv, 0), __P4MASK(drdy-own, 1), __P4MASK(drdy-other, 2), __P4MASK(dbsy-drv, 3), __P4MASK(dbsy-own, 4), __P4MASK(dbsy-other, 5), NULLMASK }; static const struct pmc_masks p4_mask_ba[] = { /* bsq allocation */ __P4MASK(req-type0, 0), __P4MASK(req-type1, 1), __P4MASK(req-len0, 2), __P4MASK(req-len1, 3), __P4MASK(req-io-type, 5), __P4MASK(req-lock-type, 6), __P4MASK(req-cache-type, 7), __P4MASK(req-split-type, 8), __P4MASK(req-dem-type, 9), __P4MASK(req-ord-type, 10), __P4MASK(mem-type0, 11), __P4MASK(mem-type1, 12), __P4MASK(mem-type2, 13), NULLMASK }; static const struct pmc_masks p4_mask_sia[] = { /* sse input assist */ __P4MASK(all, 15), NULLMASK }; static const struct pmc_masks p4_mask_psu[] = { /* packed sp uop */ __P4MASK(all, 15), NULLMASK }; static const struct pmc_masks p4_mask_pdu[] = { /* packed dp uop */ __P4MASK(all, 15), NULLMASK }; static const struct pmc_masks p4_mask_ssu[] = { /* scalar sp uop */ __P4MASK(all, 15), NULLMASK }; static const struct pmc_masks p4_mask_sdu[] = { /* scalar dp uop */ __P4MASK(all, 15), NULLMASK }; static const struct pmc_masks p4_mask_64bmu[] = { /* 64 bit mmx uop */ __P4MASK(all, 15), NULLMASK }; static const struct pmc_masks p4_mask_128bmu[] = { /* 128 bit mmx uop */ __P4MASK(all, 15), NULLMASK }; static const struct pmc_masks p4_mask_xfu[] = { /* X87 fp uop */ __P4MASK(all, 15), NULLMASK }; static const struct pmc_masks p4_mask_xsmu[] = { /* x87 simd moves uop */ __P4MASK(allp0, 3), __P4MASK(allp2, 4), NULLMASK }; static const struct pmc_masks p4_mask_gpe[] = { /* global power events */ __P4MASK(running, 0), NULLMASK }; static const struct pmc_masks p4_mask_tmx[] = { /* TC ms xfer */ __P4MASK(cisc, 0), NULLMASK }; static const struct pmc_masks p4_mask_uqw[] = { /* uop queue writes */ __P4MASK(from-tc-build, 0), __P4MASK(from-tc-deliver, 1), __P4MASK(from-rom, 2), NULLMASK }; static const struct pmc_masks p4_mask_rmbt[] = { /* retired mispred branch type */ __P4MASK(conditional, 1), __P4MASK(call, 2), __P4MASK(return, 3), __P4MASK(indirect, 4), NULLMASK }; static const struct pmc_masks p4_mask_rbt[] = { /* retired branch type */ __P4MASK(conditional, 1), __P4MASK(call, 2), __P4MASK(retired, 3), __P4MASK(indirect, 4), NULLMASK }; static const struct pmc_masks p4_mask_rs[] = { /* resource stall */ __P4MASK(sbfull, 5), NULLMASK }; static const struct pmc_masks p4_mask_wb[] = { /* WC buffer */ __P4MASK(wcb-evicts, 0), __P4MASK(wcb-full-evict, 1), NULLMASK }; static const struct pmc_masks p4_mask_fee[] = { /* front end event */ __P4MASK(nbogus, 0), __P4MASK(bogus, 1), NULLMASK }; static const struct pmc_masks p4_mask_ee[] = { /* execution event */ __P4MASK(nbogus0, 0), __P4MASK(nbogus1, 1), __P4MASK(nbogus2, 2), __P4MASK(nbogus3, 3), __P4MASK(bogus0, 4), __P4MASK(bogus1, 5), __P4MASK(bogus2, 6), __P4MASK(bogus3, 7), NULLMASK }; static const struct pmc_masks p4_mask_re[] = { /* replay event */ __P4MASK(nbogus, 0), __P4MASK(bogus, 1), NULLMASK }; static const struct pmc_masks p4_mask_insret[] = { /* instr retired */ __P4MASK(nbogusntag, 0), __P4MASK(nbogustag, 1), __P4MASK(bogusntag, 2), __P4MASK(bogustag, 3), NULLMASK }; static const struct pmc_masks p4_mask_ur[] = { /* uops retired */ __P4MASK(nbogus, 0), __P4MASK(bogus, 1), NULLMASK }; static const struct pmc_masks p4_mask_ut[] = { /* uop type */ __P4MASK(tagloads, 1), __P4MASK(tagstores, 2), NULLMASK }; static const struct pmc_masks p4_mask_br[] = { /* branch retired */ __P4MASK(mmnp, 0), __P4MASK(mmnm, 1), __P4MASK(mmtp, 2), __P4MASK(mmtm, 3), NULLMASK }; static const struct pmc_masks p4_mask_mbr[] = { /* mispred branch retired */ __P4MASK(nbogus, 0), NULLMASK }; static const struct pmc_masks p4_mask_xa[] = { /* x87 assist */ __P4MASK(fpsu, 0), __P4MASK(fpso, 1), __P4MASK(poao, 2), __P4MASK(poau, 3), __P4MASK(prea, 4), NULLMASK }; static const struct pmc_masks p4_mask_machclr[] = { /* machine clear */ __P4MASK(clear, 0), __P4MASK(moclear, 2), __P4MASK(smclear, 3), NULLMASK }; /* P4 event parser */ static int p4_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { char *e, *p, *q; int count, has_tag, has_busreqtype, n; uint32_t cccractivemask; uint64_t evmask; const struct pmc_masks *pm, *pmask; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); pmc_config->pm_md.pm_p4.pm_p4_cccrconfig = pmc_config->pm_md.pm_p4.pm_p4_escrconfig = 0; pmask = NULL; evmask = 0; cccractivemask = 0x3; has_tag = has_busreqtype = 0; #define __P4SETMASK(M) do { \ pmask = p4_mask_##M; \ } while (0) switch (pe) { case PMC_EV_P4_TC_DELIVER_MODE: __P4SETMASK(tcdm); break; case PMC_EV_P4_BPU_FETCH_REQUEST: __P4SETMASK(bfr); break; case PMC_EV_P4_ITLB_REFERENCE: __P4SETMASK(ir); break; case PMC_EV_P4_MEMORY_CANCEL: __P4SETMASK(memcan); break; case PMC_EV_P4_MEMORY_COMPLETE: __P4SETMASK(memcomp); break; case PMC_EV_P4_LOAD_PORT_REPLAY: __P4SETMASK(lpr); break; case PMC_EV_P4_STORE_PORT_REPLAY: __P4SETMASK(spr); break; case PMC_EV_P4_MOB_LOAD_REPLAY: __P4SETMASK(mlr); break; case PMC_EV_P4_PAGE_WALK_TYPE: __P4SETMASK(pwt); break; case PMC_EV_P4_BSQ_CACHE_REFERENCE: __P4SETMASK(bcr); break; case PMC_EV_P4_IOQ_ALLOCATION: __P4SETMASK(ia); has_busreqtype = 1; break; case PMC_EV_P4_IOQ_ACTIVE_ENTRIES: __P4SETMASK(iae); has_busreqtype = 1; break; case PMC_EV_P4_FSB_DATA_ACTIVITY: __P4SETMASK(fda); break; case PMC_EV_P4_BSQ_ALLOCATION: __P4SETMASK(ba); break; case PMC_EV_P4_SSE_INPUT_ASSIST: __P4SETMASK(sia); break; case PMC_EV_P4_PACKED_SP_UOP: __P4SETMASK(psu); break; case PMC_EV_P4_PACKED_DP_UOP: __P4SETMASK(pdu); break; case PMC_EV_P4_SCALAR_SP_UOP: __P4SETMASK(ssu); break; case PMC_EV_P4_SCALAR_DP_UOP: __P4SETMASK(sdu); break; case PMC_EV_P4_64BIT_MMX_UOP: __P4SETMASK(64bmu); break; case PMC_EV_P4_128BIT_MMX_UOP: __P4SETMASK(128bmu); break; case PMC_EV_P4_X87_FP_UOP: __P4SETMASK(xfu); break; case PMC_EV_P4_X87_SIMD_MOVES_UOP: __P4SETMASK(xsmu); break; case PMC_EV_P4_GLOBAL_POWER_EVENTS: __P4SETMASK(gpe); break; case PMC_EV_P4_TC_MS_XFER: __P4SETMASK(tmx); break; case PMC_EV_P4_UOP_QUEUE_WRITES: __P4SETMASK(uqw); break; case PMC_EV_P4_RETIRED_MISPRED_BRANCH_TYPE: __P4SETMASK(rmbt); break; case PMC_EV_P4_RETIRED_BRANCH_TYPE: __P4SETMASK(rbt); break; case PMC_EV_P4_RESOURCE_STALL: __P4SETMASK(rs); break; case PMC_EV_P4_WC_BUFFER: __P4SETMASK(wb); break; case PMC_EV_P4_BSQ_ACTIVE_ENTRIES: case PMC_EV_P4_B2B_CYCLES: case PMC_EV_P4_BNR: case PMC_EV_P4_SNOOP: case PMC_EV_P4_RESPONSE: break; case PMC_EV_P4_FRONT_END_EVENT: __P4SETMASK(fee); break; case PMC_EV_P4_EXECUTION_EVENT: __P4SETMASK(ee); break; case PMC_EV_P4_REPLAY_EVENT: __P4SETMASK(re); break; case PMC_EV_P4_INSTR_RETIRED: __P4SETMASK(insret); break; case PMC_EV_P4_UOPS_RETIRED: __P4SETMASK(ur); break; case PMC_EV_P4_UOP_TYPE: __P4SETMASK(ut); break; case PMC_EV_P4_BRANCH_RETIRED: __P4SETMASK(br); break; case PMC_EV_P4_MISPRED_BRANCH_RETIRED: __P4SETMASK(mbr); break; case PMC_EV_P4_X87_ASSIST: __P4SETMASK(xa); break; case PMC_EV_P4_MACHINE_CLEAR: __P4SETMASK(machclr); break; default: return (-1); } /* process additional flags */ while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWPREFIXMATCH(p, P4_KW_ACTIVE)) { q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); if (strcasecmp(q, P4_KW_ACTIVE_NONE) == 0) cccractivemask = 0x0; else if (strcasecmp(q, P4_KW_ACTIVE_SINGLE) == 0) cccractivemask = 0x1; else if (strcasecmp(q, P4_KW_ACTIVE_BOTH) == 0) cccractivemask = 0x2; else if (strcasecmp(q, P4_KW_ACTIVE_ANY) == 0) cccractivemask = 0x3; else return (-1); } else if (KWPREFIXMATCH(p, P4_KW_BUSREQTYPE)) { if (has_busreqtype == 0) return (-1); q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); evmask = (evmask & ~0x1F) | (count & 0x1F); } else if (KWMATCH(p, P4_KW_CASCADE)) pmc_config->pm_caps |= PMC_CAP_CASCADE; else if (KWMATCH(p, P4_KW_EDGE)) pmc_config->pm_caps |= PMC_CAP_EDGE; else if (KWMATCH(p, P4_KW_INV)) pmc_config->pm_caps |= PMC_CAP_INVERT; else if (KWPREFIXMATCH(p, P4_KW_MASK "=")) { if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) return (-1); pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } else if (KWMATCH(p, P4_KW_OS)) pmc_config->pm_caps |= PMC_CAP_SYSTEM; else if (KWMATCH(p, P4_KW_PRECISE)) pmc_config->pm_caps |= PMC_CAP_PRECISE; else if (KWPREFIXMATCH(p, P4_KW_TAG "=")) { if (has_tag == 0) return (-1); q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); pmc_config->pm_caps |= PMC_CAP_TAGGING; pmc_config->pm_md.pm_p4.pm_p4_escrconfig |= P4_ESCR_TO_TAG_VALUE(count); } else if (KWPREFIXMATCH(p, P4_KW_THRESHOLD "=")) { q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); pmc_config->pm_caps |= PMC_CAP_THRESHOLD; pmc_config->pm_md.pm_p4.pm_p4_cccrconfig &= ~P4_CCCR_THRESHOLD_MASK; pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= P4_CCCR_TO_THRESHOLD(count); } else if (KWMATCH(p, P4_KW_USR)) pmc_config->pm_caps |= PMC_CAP_USER; else return (-1); } /* other post processing */ if (pe == PMC_EV_P4_IOQ_ALLOCATION || pe == PMC_EV_P4_FSB_DATA_ACTIVITY || pe == PMC_EV_P4_BSQ_ALLOCATION) pmc_config->pm_caps |= PMC_CAP_EDGE; /* fill in thread activity mask */ pmc_config->pm_md.pm_p4.pm_p4_cccrconfig |= P4_CCCR_TO_ACTIVE_THREAD(cccractivemask); if (evmask) pmc_config->pm_caps |= PMC_CAP_QUALIFIER; switch (pe) { case PMC_EV_P4_FSB_DATA_ACTIVITY: if ((evmask & 0x06) == 0x06 || (evmask & 0x18) == 0x18) return (-1); /* can't have own+other bits together */ if (evmask == 0) /* default:drdy-{drv,own}+dbsy{drv,own} */ evmask = 0x1D; break; case PMC_EV_P4_MACHINE_CLEAR: /* only one bit is allowed to be set */ if ((evmask & (evmask - 1)) != 0) return (-1); if (evmask == 0) { evmask = 0x1; /* 'CLEAR' */ pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } break; default: if (evmask == 0 && pmask) { for (pm = pmask; pm->pm_name; pm++) evmask |= pm->pm_value; pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } } pmc_config->pm_md.pm_p4.pm_p4_escrconfig = P4_ESCR_TO_EVENT_MASK(evmask); return (0); } #endif #if defined(__i386__) /* * Pentium style PMCs */ static struct pmc_event_alias p5_aliases[] = { EV_ALIAS("branches", "p5-taken-branches"), EV_ALIAS("cycles", "tsc"), EV_ALIAS("dc-misses", "p5-data-read-miss-or-write-miss"), EV_ALIAS("ic-misses", "p5-code-cache-miss"), EV_ALIAS("instructions", "p5-instructions-executed"), EV_ALIAS("interrupts", "p5-hardware-interrupts"), EV_ALIAS("unhalted-cycles", "p5-number-of-cycles-not-in-halt-state"), EV_ALIAS(NULL, NULL) }; static int p5_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { return (-1 || pe || ctrspec || pmc_config); /* shut up gcc */ } /* * Pentium Pro style PMCs. These PMCs are found in Pentium II, Pentium III, * and Pentium M CPUs. */ static struct pmc_event_alias p6_aliases[] = { EV_ALIAS("branches", "p6-br-inst-retired"), EV_ALIAS("branch-mispredicts", "p6-br-miss-pred-retired"), EV_ALIAS("cycles", "tsc"), EV_ALIAS("dc-misses", "p6-dcu-lines-in"), EV_ALIAS("ic-misses", "p6-ifu-fetch-miss"), EV_ALIAS("instructions", "p6-inst-retired"), EV_ALIAS("interrupts", "p6-hw-int-rx"), EV_ALIAS("unhalted-cycles", "p6-cpu-clk-unhalted"), EV_ALIAS(NULL, NULL) }; #define P6_KW_CMASK "cmask" #define P6_KW_EDGE "edge" #define P6_KW_INV "inv" #define P6_KW_OS "os" #define P6_KW_UMASK "umask" #define P6_KW_USR "usr" static struct pmc_masks p6_mask_mesi[] = { PMCMASK(m, 0x01), PMCMASK(e, 0x02), PMCMASK(s, 0x04), PMCMASK(i, 0x08), NULLMASK }; static struct pmc_masks p6_mask_mesihw[] = { PMCMASK(m, 0x01), PMCMASK(e, 0x02), PMCMASK(s, 0x04), PMCMASK(i, 0x08), PMCMASK(nonhw, 0x00), PMCMASK(hw, 0x10), PMCMASK(both, 0x30), NULLMASK }; static struct pmc_masks p6_mask_hw[] = { PMCMASK(nonhw, 0x00), PMCMASK(hw, 0x10), PMCMASK(both, 0x30), NULLMASK }; static struct pmc_masks p6_mask_any[] = { PMCMASK(self, 0x00), PMCMASK(any, 0x20), NULLMASK }; static struct pmc_masks p6_mask_ekp[] = { PMCMASK(nta, 0x00), PMCMASK(t1, 0x01), PMCMASK(t2, 0x02), PMCMASK(wos, 0x03), NULLMASK }; static struct pmc_masks p6_mask_pps[] = { PMCMASK(packed-and-scalar, 0x00), PMCMASK(scalar, 0x01), NULLMASK }; static struct pmc_masks p6_mask_mite[] = { PMCMASK(packed-multiply, 0x01), PMCMASK(packed-shift, 0x02), PMCMASK(pack, 0x04), PMCMASK(unpack, 0x08), PMCMASK(packed-logical, 0x10), PMCMASK(packed-arithmetic, 0x20), NULLMASK }; static struct pmc_masks p6_mask_fmt[] = { PMCMASK(mmxtofp, 0x00), PMCMASK(fptommx, 0x01), NULLMASK }; static struct pmc_masks p6_mask_sr[] = { PMCMASK(es, 0x01), PMCMASK(ds, 0x02), PMCMASK(fs, 0x04), PMCMASK(gs, 0x08), NULLMASK }; static struct pmc_masks p6_mask_eet[] = { PMCMASK(all, 0x00), PMCMASK(freq, 0x02), NULLMASK }; static struct pmc_masks p6_mask_efur[] = { PMCMASK(all, 0x00), PMCMASK(loadop, 0x01), PMCMASK(stdsta, 0x02), NULLMASK }; static struct pmc_masks p6_mask_essir[] = { PMCMASK(sse-packed-single, 0x00), PMCMASK(sse-packed-single-scalar-single, 0x01), PMCMASK(sse2-packed-double, 0x02), PMCMASK(sse2-scalar-double, 0x03), NULLMASK }; static struct pmc_masks p6_mask_esscir[] = { PMCMASK(sse-packed-single, 0x00), PMCMASK(sse-scalar-single, 0x01), PMCMASK(sse2-packed-double, 0x02), PMCMASK(sse2-scalar-double, 0x03), NULLMASK }; /* P6 event parser */ static int p6_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { char *e, *p, *q; uint64_t evmask; int count, n; const struct pmc_masks *pm, *pmask; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); pmc_config->pm_md.pm_ppro.pm_ppro_config = 0; evmask = 0; #define P6MASKSET(M) pmask = p6_mask_ ## M switch(pe) { case PMC_EV_P6_L2_IFETCH: P6MASKSET(mesi); break; case PMC_EV_P6_L2_LD: P6MASKSET(mesi); break; case PMC_EV_P6_L2_ST: P6MASKSET(mesi); break; case PMC_EV_P6_L2_RQSTS: P6MASKSET(mesi); break; case PMC_EV_P6_BUS_DRDY_CLOCKS: case PMC_EV_P6_BUS_LOCK_CLOCKS: case PMC_EV_P6_BUS_TRAN_BRD: case PMC_EV_P6_BUS_TRAN_RFO: case PMC_EV_P6_BUS_TRANS_WB: case PMC_EV_P6_BUS_TRAN_IFETCH: case PMC_EV_P6_BUS_TRAN_INVAL: case PMC_EV_P6_BUS_TRAN_PWR: case PMC_EV_P6_BUS_TRANS_P: case PMC_EV_P6_BUS_TRANS_IO: case PMC_EV_P6_BUS_TRAN_DEF: case PMC_EV_P6_BUS_TRAN_BURST: case PMC_EV_P6_BUS_TRAN_ANY: case PMC_EV_P6_BUS_TRAN_MEM: P6MASKSET(any); break; case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: case PMC_EV_P6_EMON_KNI_PREF_MISS: P6MASKSET(ekp); break; case PMC_EV_P6_EMON_KNI_INST_RETIRED: case PMC_EV_P6_EMON_KNI_COMP_INST_RET: P6MASKSET(pps); break; case PMC_EV_P6_MMX_INSTR_TYPE_EXEC: P6MASKSET(mite); break; case PMC_EV_P6_FP_MMX_TRANS: P6MASKSET(fmt); break; case PMC_EV_P6_SEG_RENAME_STALLS: case PMC_EV_P6_SEG_REG_RENAMES: P6MASKSET(sr); break; case PMC_EV_P6_EMON_EST_TRANS: P6MASKSET(eet); break; case PMC_EV_P6_EMON_FUSED_UOPS_RET: P6MASKSET(efur); break; case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: P6MASKSET(essir); break; case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: P6MASKSET(esscir); break; default: pmask = NULL; break; } /* Pentium M PMCs have a few events with different semantics */ if (cpu_info.pm_cputype == PMC_CPU_INTEL_PM) { if (pe == PMC_EV_P6_L2_LD || pe == PMC_EV_P6_L2_LINES_IN || pe == PMC_EV_P6_L2_LINES_OUT) P6MASKSET(mesihw); else if (pe == PMC_EV_P6_L2_M_LINES_OUTM) P6MASKSET(hw); } /* Parse additional modifiers if present */ while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWPREFIXMATCH(p, P6_KW_CMASK "=")) { q = strchr(p, '='); if (*++q == '\0') /* skip '=' */ return (-1); count = strtol(q, &e, 0); if (e == q || *e != '\0') return (-1); pmc_config->pm_caps |= PMC_CAP_THRESHOLD; pmc_config->pm_md.pm_ppro.pm_ppro_config |= P6_EVSEL_TO_CMASK(count); } else if (KWMATCH(p, P6_KW_EDGE)) { pmc_config->pm_caps |= PMC_CAP_EDGE; } else if (KWMATCH(p, P6_KW_INV)) { pmc_config->pm_caps |= PMC_CAP_INVERT; } else if (KWMATCH(p, P6_KW_OS)) { pmc_config->pm_caps |= PMC_CAP_SYSTEM; } else if (KWPREFIXMATCH(p, P6_KW_UMASK "=")) { evmask = 0; if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0) return (-1); if ((pe == PMC_EV_P6_BUS_DRDY_CLOCKS || pe == PMC_EV_P6_BUS_LOCK_CLOCKS || pe == PMC_EV_P6_BUS_TRAN_BRD || pe == PMC_EV_P6_BUS_TRAN_RFO || pe == PMC_EV_P6_BUS_TRAN_IFETCH || pe == PMC_EV_P6_BUS_TRAN_INVAL || pe == PMC_EV_P6_BUS_TRAN_PWR || pe == PMC_EV_P6_BUS_TRAN_DEF || pe == PMC_EV_P6_BUS_TRAN_BURST || pe == PMC_EV_P6_BUS_TRAN_ANY || pe == PMC_EV_P6_BUS_TRAN_MEM || pe == PMC_EV_P6_BUS_TRANS_IO || pe == PMC_EV_P6_BUS_TRANS_P || pe == PMC_EV_P6_BUS_TRANS_WB || pe == PMC_EV_P6_EMON_EST_TRANS || pe == PMC_EV_P6_EMON_FUSED_UOPS_RET || pe == PMC_EV_P6_EMON_KNI_COMP_INST_RET || pe == PMC_EV_P6_EMON_KNI_INST_RETIRED || pe == PMC_EV_P6_EMON_KNI_PREF_DISPATCHED || pe == PMC_EV_P6_EMON_KNI_PREF_MISS || pe == PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED || pe == PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED || pe == PMC_EV_P6_FP_MMX_TRANS) && (n > 1)) /* Only one mask keyword is allowed. */ return (-1); pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } else if (KWMATCH(p, P6_KW_USR)) { pmc_config->pm_caps |= PMC_CAP_USER; } else return (-1); } /* post processing */ switch (pe) { /* * The following events default to an evmask of 0 */ /* default => 'self' */ case PMC_EV_P6_BUS_DRDY_CLOCKS: case PMC_EV_P6_BUS_LOCK_CLOCKS: case PMC_EV_P6_BUS_TRAN_BRD: case PMC_EV_P6_BUS_TRAN_RFO: case PMC_EV_P6_BUS_TRANS_WB: case PMC_EV_P6_BUS_TRAN_IFETCH: case PMC_EV_P6_BUS_TRAN_INVAL: case PMC_EV_P6_BUS_TRAN_PWR: case PMC_EV_P6_BUS_TRANS_P: case PMC_EV_P6_BUS_TRANS_IO: case PMC_EV_P6_BUS_TRAN_DEF: case PMC_EV_P6_BUS_TRAN_BURST: case PMC_EV_P6_BUS_TRAN_ANY: case PMC_EV_P6_BUS_TRAN_MEM: /* default => 'nta' */ case PMC_EV_P6_EMON_KNI_PREF_DISPATCHED: case PMC_EV_P6_EMON_KNI_PREF_MISS: /* default => 'packed and scalar' */ case PMC_EV_P6_EMON_KNI_INST_RETIRED: case PMC_EV_P6_EMON_KNI_COMP_INST_RET: /* default => 'mmx to fp transitions' */ case PMC_EV_P6_FP_MMX_TRANS: /* default => 'SSE Packed Single' */ case PMC_EV_P6_EMON_SSE_SSE2_INST_RETIRED: case PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED: /* default => 'all fused micro-ops' */ case PMC_EV_P6_EMON_FUSED_UOPS_RET: /* default => 'all transitions' */ case PMC_EV_P6_EMON_EST_TRANS: break; case PMC_EV_P6_MMX_UOPS_EXEC: evmask = 0x0F; /* only value allowed */ break; default: /* * For all other events, set the default event mask * to a logical OR of all the allowed event mask bits. */ if (evmask == 0 && pmask) { for (pm = pmask; pm->pm_name; pm++) evmask |= pm->pm_value; pmc_config->pm_caps |= PMC_CAP_QUALIFIER; } break; } if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) pmc_config->pm_md.pm_ppro.pm_ppro_config |= P6_EVSEL_TO_UMASK(evmask); return (0); } #endif #if defined(__i386__) || defined(__amd64__) static int tsc_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { if (pe != PMC_EV_TSC_TSC) return (-1); /* TSC events must be unqualified. */ if (ctrspec && *ctrspec != '\0') return (-1); pmc_config->pm_md.pm_amd.pm_amd_config = 0; pmc_config->pm_caps |= PMC_CAP_READ; return (0); } #endif static struct pmc_event_alias generic_aliases[] = { EV_ALIAS("instructions", "SOFT-CLOCK.HARD"), EV_ALIAS(NULL, NULL) }; static int soft_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) { (void)ctrspec; (void)pmc_config; if (pe < PMC_EV_SOFT_FIRST || pe > PMC_EV_SOFT_LAST) return (-1); pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); return (0); } #if defined(__XSCALE__) static struct pmc_event_alias xscale_aliases[] = { EV_ALIAS("branches", "BRANCH_RETIRED"), EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), EV_ALIAS("dc-misses", "DC_MISS"), EV_ALIAS("ic-misses", "IC_MISS"), EV_ALIAS("instructions", "INSTR_RETIRED"), EV_ALIAS(NULL, NULL) }; static int xscale_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) { switch (pe) { default: break; } return (0); } #endif #if defined(__mips__) static struct pmc_event_alias mips24k_aliases[] = { EV_ALIAS("instructions", "INSTR_EXECUTED"), EV_ALIAS("branches", "BRANCH_COMPLETED"), EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), EV_ALIAS(NULL, NULL) }; #define MIPS24K_KW_OS "os" #define MIPS24K_KW_USR "usr" #define MIPS24K_KW_ANYTHREAD "anythread" static int mips24k_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) { char *p; (void) pe; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWMATCH(p, MIPS24K_KW_OS)) pmc_config->pm_caps |= PMC_CAP_SYSTEM; else if (KWMATCH(p, MIPS24K_KW_USR)) pmc_config->pm_caps |= PMC_CAP_USER; else if (KWMATCH(p, MIPS24K_KW_ANYTHREAD)) pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); else return (-1); } return (0); } #endif /* __mips__ */ #if defined(__powerpc__) static struct pmc_event_alias ppc7450_aliases[] = { EV_ALIAS("instructions", "INSTR_COMPLETED"), EV_ALIAS("branches", "BRANCHES_COMPLETED"), EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"), EV_ALIAS(NULL, NULL) }; #define PPC7450_KW_OS "os" #define PPC7450_KW_USR "usr" #define PPC7450_KW_ANYTHREAD "anythread" static int ppc7450_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, struct pmc_op_pmcallocate *pmc_config __unused) { char *p; (void) pe; pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); while ((p = strsep(&ctrspec, ",")) != NULL) { if (KWMATCH(p, PPC7450_KW_OS)) pmc_config->pm_caps |= PMC_CAP_SYSTEM; else if (KWMATCH(p, PPC7450_KW_USR)) pmc_config->pm_caps |= PMC_CAP_USER; else if (KWMATCH(p, PPC7450_KW_ANYTHREAD)) pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); else return (-1); } return (0); } #endif /* __powerpc__ */ /* * Match an event name `name' with its canonical form. * * Matches are case insensitive and spaces, periods, underscores and * hyphen characters are considered to match each other. * * Returns 1 for a match, 0 otherwise. */ static int pmc_match_event_name(const char *name, const char *canonicalname) { int cc, nc; const unsigned char *c, *n; c = (const unsigned char *) canonicalname; n = (const unsigned char *) name; for (; (nc = *n) && (cc = *c); n++, c++) { if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') && (cc == ' ' || cc == '_' || cc == '-' || cc == '.')) continue; if (toupper(nc) == toupper(cc)) continue; return (0); } if (*n == '\0' && *c == '\0') return (1); return (0); } /* * Match an event name against all the event named supported by a * PMC class. * * Returns an event descriptor pointer on match or NULL otherwise. */ static const struct pmc_event_descr * pmc_match_event_class(const char *name, const struct pmc_class_descr *pcd) { size_t n; const struct pmc_event_descr *ev; ev = pcd->pm_evc_event_table; for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++) if (pmc_match_event_name(name, ev->pm_ev_name)) return (ev); return (NULL); } static int pmc_mdep_is_compatible_class(enum pmc_class pc) { size_t n; for (n = 0; n < pmc_mdep_class_list_size; n++) if (pmc_mdep_class_list[n] == pc) return (1); return (0); } /* * API entry points */ int pmc_allocate(const char *ctrspec, enum pmc_mode mode, uint32_t flags, int cpu, pmc_id_t *pmcid) { size_t n; int retval; char *r, *spec_copy; const char *ctrname; const struct pmc_event_descr *ev; const struct pmc_event_alias *alias; struct pmc_op_pmcallocate pmc_config; const struct pmc_class_descr *pcd; spec_copy = NULL; retval = -1; if (mode != PMC_MODE_SS && mode != PMC_MODE_TS && mode != PMC_MODE_SC && mode != PMC_MODE_TC) { errno = EINVAL; goto out; } /* replace an event alias with the canonical event specifier */ if (pmc_mdep_event_aliases) for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++) if (!strcasecmp(ctrspec, alias->pm_alias)) { spec_copy = strdup(alias->pm_spec); break; } if (spec_copy == NULL) spec_copy = strdup(ctrspec); r = spec_copy; ctrname = strsep(&r, ","); /* * If a explicit class prefix was given by the user, restrict the * search for the event to the specified PMC class. */ ev = NULL; for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) { pcd = pmc_class_table[n]; if (pmc_mdep_is_compatible_class(pcd->pm_evc_class) && strncasecmp(ctrname, pcd->pm_evc_name, pcd->pm_evc_name_size) == 0) { if ((ev = pmc_match_event_class(ctrname + pcd->pm_evc_name_size, pcd)) == NULL) { errno = EINVAL; goto out; } break; } } /* * Otherwise, search for this event in all compatible PMC * classes. */ for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) { pcd = pmc_class_table[n]; if (pmc_mdep_is_compatible_class(pcd->pm_evc_class)) ev = pmc_match_event_class(ctrname, pcd); } if (ev == NULL) { errno = EINVAL; goto out; } bzero(&pmc_config, sizeof(pmc_config)); pmc_config.pm_ev = ev->pm_ev_code; pmc_config.pm_class = pcd->pm_evc_class; pmc_config.pm_cpu = cpu; pmc_config.pm_mode = mode; pmc_config.pm_flags = flags; if (PMC_IS_SAMPLING_MODE(mode)) pmc_config.pm_caps |= PMC_CAP_INTERRUPT; if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) { errno = EINVAL; goto out; } if (PMC_CALL(PMCALLOCATE, &pmc_config) < 0) goto out; *pmcid = pmc_config.pm_pmcid; retval = 0; out: if (spec_copy) free(spec_copy); return (retval); } int pmc_attach(pmc_id_t pmc, pid_t pid) { struct pmc_op_pmcattach pmc_attach_args; pmc_attach_args.pm_pmc = pmc; pmc_attach_args.pm_pid = pid; return (PMC_CALL(PMCATTACH, &pmc_attach_args)); } int pmc_capabilities(pmc_id_t pmcid, uint32_t *caps) { unsigned int i; enum pmc_class cl; cl = PMC_ID_TO_CLASS(pmcid); for (i = 0; i < cpu_info.pm_nclass; i++) if (cpu_info.pm_classes[i].pm_class == cl) { *caps = cpu_info.pm_classes[i].pm_caps; return (0); } errno = EINVAL; return (-1); } int pmc_configure_logfile(int fd) { struct pmc_op_configurelog cla; cla.pm_logfd = fd; if (PMC_CALL(CONFIGURELOG, &cla) < 0) return (-1); return (0); } int pmc_cpuinfo(const struct pmc_cpuinfo **pci) { if (pmc_syscall == -1) { errno = ENXIO; return (-1); } *pci = &cpu_info; return (0); } int pmc_detach(pmc_id_t pmc, pid_t pid) { struct pmc_op_pmcattach pmc_detach_args; pmc_detach_args.pm_pmc = pmc; pmc_detach_args.pm_pid = pid; return (PMC_CALL(PMCDETACH, &pmc_detach_args)); } int pmc_disable(int cpu, int pmc) { struct pmc_op_pmcadmin ssa; ssa.pm_cpu = cpu; ssa.pm_pmc = pmc; ssa.pm_state = PMC_STATE_DISABLED; return (PMC_CALL(PMCADMIN, &ssa)); } int pmc_enable(int cpu, int pmc) { struct pmc_op_pmcadmin ssa; ssa.pm_cpu = cpu; ssa.pm_pmc = pmc; ssa.pm_state = PMC_STATE_FREE; return (PMC_CALL(PMCADMIN, &ssa)); } /* * Return a list of events known to a given PMC class. 'cl' is the * PMC class identifier, 'eventnames' is the returned list of 'const * char *' pointers pointing to the names of the events. 'nevents' is * the number of event name pointers returned. * * The space for 'eventnames' is allocated using malloc(3). The caller * is responsible for freeing this space when done. */ int pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, int *nevents) { int count; const char **names; const struct pmc_event_descr *ev; switch (cl) { case PMC_CLASS_IAF: ev = iaf_event_table; count = PMC_EVENT_TABLE_SIZE(iaf); break; case PMC_CLASS_IAP: /* * Return the most appropriate set of event name * spellings for the current CPU. */ switch (cpu_info.pm_cputype) { default: case PMC_CPU_INTEL_ATOM: ev = atom_event_table; count = PMC_EVENT_TABLE_SIZE(atom); break; case PMC_CPU_INTEL_CORE: ev = core_event_table; count = PMC_EVENT_TABLE_SIZE(core); break; case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: ev = core2_event_table; count = PMC_EVENT_TABLE_SIZE(core2); break; case PMC_CPU_INTEL_COREI7: ev = corei7_event_table; count = PMC_EVENT_TABLE_SIZE(corei7); break; case PMC_CPU_INTEL_IVYBRIDGE: ev = ivybridge_event_table; count = PMC_EVENT_TABLE_SIZE(ivybridge); break; case PMC_CPU_INTEL_SANDYBRIDGE: ev = sandybridge_event_table; count = PMC_EVENT_TABLE_SIZE(sandybridge); break; + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: + ev = sandybridge_xeon_event_table; + count = PMC_EVENT_TABLE_SIZE(sandybridge_xeon); + break; case PMC_CPU_INTEL_WESTMERE: ev = westmere_event_table; count = PMC_EVENT_TABLE_SIZE(westmere); break; } break; case PMC_CLASS_UCF: ev = ucf_event_table; count = PMC_EVENT_TABLE_SIZE(ucf); break; case PMC_CLASS_UCP: /* * Return the most appropriate set of event name * spellings for the current CPU. */ switch (cpu_info.pm_cputype) { default: case PMC_CPU_INTEL_COREI7: ev = corei7uc_event_table; count = PMC_EVENT_TABLE_SIZE(corei7uc); break; case PMC_CPU_INTEL_SANDYBRIDGE: ev = sandybridgeuc_event_table; count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); break; case PMC_CPU_INTEL_WESTMERE: ev = westmereuc_event_table; count = PMC_EVENT_TABLE_SIZE(westmereuc); break; } break; case PMC_CLASS_TSC: ev = tsc_event_table; count = PMC_EVENT_TABLE_SIZE(tsc); break; case PMC_CLASS_K7: ev = k7_event_table; count = PMC_EVENT_TABLE_SIZE(k7); break; case PMC_CLASS_K8: ev = k8_event_table; count = PMC_EVENT_TABLE_SIZE(k8); break; case PMC_CLASS_P4: ev = p4_event_table; count = PMC_EVENT_TABLE_SIZE(p4); break; case PMC_CLASS_P5: ev = p5_event_table; count = PMC_EVENT_TABLE_SIZE(p5); break; case PMC_CLASS_P6: ev = p6_event_table; count = PMC_EVENT_TABLE_SIZE(p6); break; case PMC_CLASS_XSCALE: ev = xscale_event_table; count = PMC_EVENT_TABLE_SIZE(xscale); break; case PMC_CLASS_MIPS24K: ev = mips24k_event_table; count = PMC_EVENT_TABLE_SIZE(mips24k); break; case PMC_CLASS_PPC7450: ev = ppc7450_event_table; count = PMC_EVENT_TABLE_SIZE(ppc7450); break; case PMC_CLASS_SOFT: ev = soft_event_table; count = soft_event_info.pm_nevent; break; default: errno = EINVAL; return (-1); } if ((names = malloc(count * sizeof(const char *))) == NULL) return (-1); *eventnames = names; *nevents = count; for (;count--; ev++, names++) *names = ev->pm_ev_name; return (0); } int pmc_flush_logfile(void) { return (PMC_CALL(FLUSHLOG,0)); } int pmc_close_logfile(void) { return (PMC_CALL(CLOSELOG,0)); } int pmc_get_driver_stats(struct pmc_driverstats *ds) { struct pmc_op_getdriverstats gms; if (PMC_CALL(GETDRIVERSTATS, &gms) < 0) return (-1); /* copy out fields in the current userland<->library interface */ ds->pm_intr_ignored = gms.pm_intr_ignored; ds->pm_intr_processed = gms.pm_intr_processed; ds->pm_intr_bufferfull = gms.pm_intr_bufferfull; ds->pm_syscalls = gms.pm_syscalls; ds->pm_syscall_errors = gms.pm_syscall_errors; ds->pm_buffer_requests = gms.pm_buffer_requests; ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed; ds->pm_log_sweeps = gms.pm_log_sweeps; return (0); } int pmc_get_msr(pmc_id_t pmc, uint32_t *msr) { struct pmc_op_getmsr gm; gm.pm_pmcid = pmc; if (PMC_CALL(PMCGETMSR, &gm) < 0) return (-1); *msr = gm.pm_msr; return (0); } int pmc_init(void) { int error, pmc_mod_id; unsigned int n; uint32_t abi_version; struct module_stat pmc_modstat; struct pmc_op_getcpuinfo op_cpu_info; #if defined(__amd64__) || defined(__i386__) int cpu_has_iaf_counters; unsigned int t; #endif if (pmc_syscall != -1) /* already inited */ return (0); /* retrieve the system call number from the KLD */ if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0) return (-1); pmc_modstat.version = sizeof(struct module_stat); if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0) return (-1); pmc_syscall = pmc_modstat.data.intval; /* check the kernel module's ABI against our compiled-in version */ abi_version = PMC_VERSION; if (PMC_CALL(GETMODULEVERSION, &abi_version) < 0) return (pmc_syscall = -1); /* ignore patch & minor numbers for the comparision */ if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) { errno = EPROGMISMATCH; return (pmc_syscall = -1); } if (PMC_CALL(GETCPUINFO, &op_cpu_info) < 0) return (pmc_syscall = -1); cpu_info.pm_cputype = op_cpu_info.pm_cputype; cpu_info.pm_ncpu = op_cpu_info.pm_ncpu; cpu_info.pm_npmc = op_cpu_info.pm_npmc; cpu_info.pm_nclass = op_cpu_info.pm_nclass; for (n = 0; n < cpu_info.pm_nclass; n++) cpu_info.pm_classes[n] = op_cpu_info.pm_classes[n]; pmc_class_table = malloc(PMC_CLASS_TABLE_SIZE * sizeof(struct pmc_class_descr *)); if (pmc_class_table == NULL) return (-1); for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) pmc_class_table[n] = NULL; /* * Get soft events list. */ soft_event_info.pm_class = PMC_CLASS_SOFT; if (PMC_CALL(GETDYNEVENTINFO, &soft_event_info) < 0) return (pmc_syscall = -1); /* Map soft events to static list. */ for (n = 0; n < soft_event_info.pm_nevent; n++) { soft_event_table[n].pm_ev_name = soft_event_info.pm_events[n].pm_ev_name; soft_event_table[n].pm_ev_code = soft_event_info.pm_events[n].pm_ev_code; } soft_class_table_descr.pm_evc_event_table_size = \ soft_event_info.pm_nevent; soft_class_table_descr.pm_evc_event_table = \ soft_event_table; /* * Fill in the class table. */ n = 0; /* Fill soft events information. */ pmc_class_table[n++] = &soft_class_table_descr; #if defined(__amd64__) || defined(__i386__) if (cpu_info.pm_cputype != PMC_CPU_GENERIC) pmc_class_table[n++] = &tsc_class_table_descr; /* * Check if this CPU has fixed function counters. */ cpu_has_iaf_counters = 0; for (t = 0; t < cpu_info.pm_nclass; t++) if (cpu_info.pm_classes[t].pm_class == PMC_CLASS_IAF && cpu_info.pm_classes[t].pm_num > 0) cpu_has_iaf_counters = 1; #endif #define PMC_MDEP_INIT(C) do { \ pmc_mdep_event_aliases = C##_aliases; \ pmc_mdep_class_list = C##_pmc_classes; \ pmc_mdep_class_list_size = \ PMC_TABLE_SIZE(C##_pmc_classes); \ } while (0) #define PMC_MDEP_INIT_INTEL_V2(C) do { \ PMC_MDEP_INIT(C); \ pmc_class_table[n++] = &iaf_class_table_descr; \ if (!cpu_has_iaf_counters) \ pmc_mdep_event_aliases = \ C##_aliases_without_iaf; \ pmc_class_table[n] = &C##_class_table_descr; \ } while (0) /* Configure the event name parser. */ switch (cpu_info.pm_cputype) { #if defined(__i386__) case PMC_CPU_AMD_K7: PMC_MDEP_INIT(k7); pmc_class_table[n] = &k7_class_table_descr; break; case PMC_CPU_INTEL_P5: PMC_MDEP_INIT(p5); pmc_class_table[n] = &p5_class_table_descr; break; case PMC_CPU_INTEL_P6: /* P6 ... Pentium M CPUs have */ case PMC_CPU_INTEL_PII: /* similar PMCs. */ case PMC_CPU_INTEL_PIII: case PMC_CPU_INTEL_PM: PMC_MDEP_INIT(p6); pmc_class_table[n] = &p6_class_table_descr; break; #endif #if defined(__amd64__) || defined(__i386__) case PMC_CPU_AMD_K8: PMC_MDEP_INIT(k8); pmc_class_table[n] = &k8_class_table_descr; break; case PMC_CPU_INTEL_ATOM: PMC_MDEP_INIT_INTEL_V2(atom); break; case PMC_CPU_INTEL_CORE: PMC_MDEP_INIT(core); pmc_class_table[n] = &core_class_table_descr; break; case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: PMC_MDEP_INIT_INTEL_V2(core2); break; case PMC_CPU_INTEL_COREI7: pmc_class_table[n++] = &ucf_class_table_descr; pmc_class_table[n++] = &corei7uc_class_table_descr; PMC_MDEP_INIT_INTEL_V2(corei7); break; case PMC_CPU_INTEL_IVYBRIDGE: PMC_MDEP_INIT_INTEL_V2(ivybridge); break; case PMC_CPU_INTEL_SANDYBRIDGE: pmc_class_table[n++] = &ucf_class_table_descr; pmc_class_table[n++] = &sandybridgeuc_class_table_descr; PMC_MDEP_INIT_INTEL_V2(sandybridge); break; + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: + PMC_MDEP_INIT_INTEL_V2(sandybridge_xeon); + break; case PMC_CPU_INTEL_WESTMERE: pmc_class_table[n++] = &ucf_class_table_descr; pmc_class_table[n++] = &westmereuc_class_table_descr; PMC_MDEP_INIT_INTEL_V2(westmere); break; case PMC_CPU_INTEL_PIV: PMC_MDEP_INIT(p4); pmc_class_table[n] = &p4_class_table_descr; break; #endif case PMC_CPU_GENERIC: PMC_MDEP_INIT(generic); break; #if defined(__XSCALE__) case PMC_CPU_INTEL_XSCALE: PMC_MDEP_INIT(xscale); pmc_class_table[n] = &xscale_class_table_descr; break; #endif #if defined(__mips__) case PMC_CPU_MIPS_24K: PMC_MDEP_INIT(mips24k); pmc_class_table[n] = &mips24k_class_table_descr; break; #endif /* __mips__ */ #if defined(__powerpc__) case PMC_CPU_PPC_7450: PMC_MDEP_INIT(ppc7450); pmc_class_table[n] = &ppc7450_class_table_descr; break; #endif default: /* * Some kind of CPU this version of the library knows nothing * about. This shouldn't happen since the abi version check * should have caught this. */ errno = ENXIO; return (pmc_syscall = -1); } return (0); } const char * pmc_name_of_capability(enum pmc_caps cap) { int i; /* * 'cap' should have a single bit set and should be in * range. */ if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST || cap > PMC_CAP_LAST) { errno = EINVAL; return (NULL); } i = ffs(cap); return (pmc_capability_names[i - 1]); } const char * pmc_name_of_class(enum pmc_class pc) { if ((int) pc >= PMC_CLASS_FIRST && pc <= PMC_CLASS_LAST) return (pmc_class_names[pc]); errno = EINVAL; return (NULL); } const char * pmc_name_of_cputype(enum pmc_cputype cp) { size_t n; for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++) if (cp == pmc_cputype_names[n].pm_cputype) return (pmc_cputype_names[n].pm_name); errno = EINVAL; return (NULL); } const char * pmc_name_of_disposition(enum pmc_disp pd) { if ((int) pd >= PMC_DISP_FIRST && pd <= PMC_DISP_LAST) return (pmc_disposition_names[pd]); errno = EINVAL; return (NULL); } const char * _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) { const struct pmc_event_descr *ev, *evfence; ev = evfence = NULL; if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { ev = iaf_event_table; evfence = iaf_event_table + PMC_EVENT_TABLE_SIZE(iaf); } else if (pe >= PMC_EV_IAP_FIRST && pe <= PMC_EV_IAP_LAST) { switch (cpu) { case PMC_CPU_INTEL_ATOM: ev = atom_event_table; evfence = atom_event_table + PMC_EVENT_TABLE_SIZE(atom); break; case PMC_CPU_INTEL_CORE: ev = core_event_table; evfence = core_event_table + PMC_EVENT_TABLE_SIZE(core); break; case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: ev = core2_event_table; evfence = core2_event_table + PMC_EVENT_TABLE_SIZE(core2); break; case PMC_CPU_INTEL_COREI7: ev = corei7_event_table; evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); break; case PMC_CPU_INTEL_IVYBRIDGE: ev = ivybridge_event_table; evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); break; case PMC_CPU_INTEL_SANDYBRIDGE: ev = sandybridge_event_table; evfence = sandybridge_event_table + PMC_EVENT_TABLE_SIZE(sandybridge); + break; + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: + ev = sandybridge_xeon_event_table; + evfence = sandybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(sandybridge_xeon); break; case PMC_CPU_INTEL_WESTMERE: ev = westmere_event_table; evfence = westmere_event_table + PMC_EVENT_TABLE_SIZE(westmere); break; default: /* Unknown CPU type. */ break; } } else if (pe >= PMC_EV_UCF_FIRST && pe <= PMC_EV_UCF_LAST) { ev = ucf_event_table; evfence = ucf_event_table + PMC_EVENT_TABLE_SIZE(ucf); } else if (pe >= PMC_EV_UCP_FIRST && pe <= PMC_EV_UCP_LAST) { switch (cpu) { case PMC_CPU_INTEL_COREI7: ev = corei7uc_event_table; evfence = corei7uc_event_table + PMC_EVENT_TABLE_SIZE(corei7uc); break; case PMC_CPU_INTEL_SANDYBRIDGE: ev = sandybridgeuc_event_table; evfence = sandybridgeuc_event_table + PMC_EVENT_TABLE_SIZE(sandybridgeuc); break; case PMC_CPU_INTEL_WESTMERE: ev = westmereuc_event_table; evfence = westmereuc_event_table + PMC_EVENT_TABLE_SIZE(westmereuc); break; default: /* Unknown CPU type. */ break; } } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) { ev = k7_event_table; evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7); } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) { ev = k8_event_table; evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8); } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) { ev = p4_event_table; evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4); } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) { ev = p5_event_table; evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5); } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) { ev = p6_event_table; evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { ev = xscale_event_table; evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { ev = mips24k_event_table; evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { ev = ppc7450_event_table; evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); } else if (pe == PMC_EV_TSC_TSC) { ev = tsc_event_table; evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc); } else if (pe >= PMC_EV_SOFT_FIRST && pe <= PMC_EV_SOFT_LAST) { ev = soft_event_table; evfence = soft_event_table + soft_event_info.pm_nevent; } for (; ev != evfence; ev++) if (pe == ev->pm_ev_code) return (ev->pm_ev_name); return (NULL); } const char * pmc_name_of_event(enum pmc_event pe) { const char *n; if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL) return (n); errno = EINVAL; return (NULL); } const char * pmc_name_of_mode(enum pmc_mode pm) { if ((int) pm >= PMC_MODE_FIRST && pm <= PMC_MODE_LAST) return (pmc_mode_names[pm]); errno = EINVAL; return (NULL); } const char * pmc_name_of_state(enum pmc_state ps) { if ((int) ps >= PMC_STATE_FIRST && ps <= PMC_STATE_LAST) return (pmc_state_names[ps]); errno = EINVAL; return (NULL); } int pmc_ncpu(void) { if (pmc_syscall == -1) { errno = ENXIO; return (-1); } return (cpu_info.pm_ncpu); } int pmc_npmc(int cpu) { if (pmc_syscall == -1) { errno = ENXIO; return (-1); } if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) { errno = EINVAL; return (-1); } return (cpu_info.pm_npmc); } int pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci) { int nbytes, npmc; struct pmc_op_getpmcinfo *pmci; if ((npmc = pmc_npmc(cpu)) < 0) return (-1); nbytes = sizeof(struct pmc_op_getpmcinfo) + npmc * sizeof(struct pmc_info); if ((pmci = calloc(1, nbytes)) == NULL) return (-1); pmci->pm_cpu = cpu; if (PMC_CALL(GETPMCINFO, pmci) < 0) { free(pmci); return (-1); } /* kernel<->library, library<->userland interfaces are identical */ *ppmci = (struct pmc_pmcinfo *) pmci; return (0); } int pmc_read(pmc_id_t pmc, pmc_value_t *value) { struct pmc_op_pmcrw pmc_read_op; pmc_read_op.pm_pmcid = pmc; pmc_read_op.pm_flags = PMC_F_OLDVALUE; pmc_read_op.pm_value = -1; if (PMC_CALL(PMCRW, &pmc_read_op) < 0) return (-1); *value = pmc_read_op.pm_value; return (0); } int pmc_release(pmc_id_t pmc) { struct pmc_op_simple pmc_release_args; pmc_release_args.pm_pmcid = pmc; return (PMC_CALL(PMCRELEASE, &pmc_release_args)); } int pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep) { struct pmc_op_pmcrw pmc_rw_op; pmc_rw_op.pm_pmcid = pmc; pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE; pmc_rw_op.pm_value = newvalue; if (PMC_CALL(PMCRW, &pmc_rw_op) < 0) return (-1); *oldvaluep = pmc_rw_op.pm_value; return (0); } int pmc_set(pmc_id_t pmc, pmc_value_t value) { struct pmc_op_pmcsetcount sc; sc.pm_pmcid = pmc; sc.pm_count = value; if (PMC_CALL(PMCSETCOUNT, &sc) < 0) return (-1); return (0); } int pmc_start(pmc_id_t pmc) { struct pmc_op_simple pmc_start_args; pmc_start_args.pm_pmcid = pmc; return (PMC_CALL(PMCSTART, &pmc_start_args)); } int pmc_stop(pmc_id_t pmc) { struct pmc_op_simple pmc_stop_args; pmc_stop_args.pm_pmcid = pmc; return (PMC_CALL(PMCSTOP, &pmc_stop_args)); } int pmc_width(pmc_id_t pmcid, uint32_t *width) { unsigned int i; enum pmc_class cl; cl = PMC_ID_TO_CLASS(pmcid); for (i = 0; i < cpu_info.pm_nclass; i++) if (cpu_info.pm_classes[i].pm_class == cl) { *width = cpu_info.pm_classes[i].pm_width; return (0); } errno = EINVAL; return (-1); } int pmc_write(pmc_id_t pmc, pmc_value_t value) { struct pmc_op_pmcrw pmc_write_op; pmc_write_op.pm_pmcid = pmc; pmc_write_op.pm_flags = PMC_F_NEWVALUE; pmc_write_op.pm_value = value; return (PMC_CALL(PMCRW, &pmc_write_op)); } int pmc_writelog(uint32_t userdata) { struct pmc_op_writelog wl; wl.pm_userdata = userdata; return (PMC_CALL(WRITELOG, &wl)); } Index: stable/9/lib/libpmc/pmc.ivybridge.3 =================================================================== --- stable/9/lib/libpmc/pmc.ivybridge.3 (revision 242593) +++ stable/9/lib/libpmc/pmc.ivybridge.3 (revision 242594) @@ -1,880 +1,881 @@ .\" Copyright (c) 2012 Fabien Thomas. All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" -.Dd August 24, 2012 +.Dd October 19, 2012 .Dt PMC.IVYBRIDGE 3 .Os .Sh NAME .Nm pmc.ivybridge .Nd measurement events for .Tn Intel .Tn Ivy Bridge family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Ivy Bridge" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Ivy Bridge PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" Intel(R) 64 and IA-32 Architectures Software Developers Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-043US" .%D May 2012 .%Q "Intel Corporation" .Re .Ss IVYBRIDGE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss IVYBRIDGE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNPI_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM Target was non-DRAM system address. This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Ivy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H loads blocked by overlapping with store buffer that cannot be forwarded . .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store- address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK .Pq Event 08H , Umask 81H Misses in all TLB levels that cause a page walk of any page size from demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED .Pq Event 08H , Umask 82H Misses in all TLB levels that caused page walk completed of any size by demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION .Pq Event 08H , Umask 84H Cycle PMH is busy with a walk due to demand loads. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1to count stalled cycles. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H Number of flags-merge uops allocated. Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SINGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H , Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H , Umask 40H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H , Umask 80H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask C0H Counts all L2 HW prefetcher requests. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H , Umask 01H RFOs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq Event 27H , Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq Event 27H , Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.MISS .Pq Event 28H , Umask 01H Not rejected writebacks that missed LLC. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H , Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H , Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li L2_L1D_WB_RQSTS.ALL .Pq Event 28H , Umask 0FH Not rejected writebacks from L1D to L2 cache lines in any state. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences. Counter 2 only. Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 01H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were eliminated. .It Li MOVE_ELIMINATION.SIMD_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is in ring 0. Use Edge to count transition. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li TLB_ACCESS.LOAD_STLB_HIT .Pq Event 5FH , Umask 01H Counts load operations that missed 1st level DTLB but hit the 2nd level. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD .Pq Event 60H , Umask 02H Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Can combine Umask 04H and 20H. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Can combine Umask 08H and 10H Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. Can combine Umask 04H, 08H. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered four uops. Set Cmask = 4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered four uops. Set Cmask = 4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H Number of cache load STLB hits. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. .It Li BR_INST_EXEC.COND .Pq Event 88H , Umask 01H Qualify conditional near branch instructions executed, but not necessarily retired. Must combine with umask 40H, 80H. .It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H , Umask 02H Qualify all unconditional near branch instructions excluding calls and indirect branches. Must combine with umask 80H. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H , Umask 04H Qualify executed indirect near branch instructions that are not calls nor returns. Must combine with umask 80H. .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H , Umask 08H Qualify indirect near branches that have a return mnemonic. Must combine with umask 80H. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H , Umask 10H Qualify unconditional near call branch instructions, excluding non call branch, executed. Must combine with umask 80H. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H , Umask 20H Qualify indirect near calls, including both register and memory indirect, executed. Must combine with umask 80H. .It Li BR_INST_EXEC.NONTAKEN .Pq Event 88H , Umask 40H Qualify non-taken near branches executed. Applicable to umask 01H only. .It Li BR_INST_EXEC.TAKEN .Pq Event 88H , Umask 80H Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H, 10H, 20H. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). .It Li BR_MISP_EXEC.COND .Pq Event 89H , Umask 01H Qualify conditional near branch instructions mispredicted. Must combine with umask 40H, 80H. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H , Umask 04H Qualify mispredicted indirect near branch instructions that are not calls nor returns. Must combine with umask 80H. .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H , Umask 08H Qualify mispredicted indirect near branches that have a return mnemonic. Must combine with umask 80H. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H , Umask 10H Qualify mispredicted unconditional near call branch instructions, excluding non call branch, executed. Must combine with umask 80H. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H , Umask 20H Qualify mispredicted indirect near calls, including both register and memory indirect, executed. Must combine with umask 80H. .It Li BR_MISP_EXEC.NONTAKEN .Pq Event 89H , Umask 40H Qualify mispredicted non-taken near branches executed. Applicable to umask 01H only. .It Li BR_MISP_EXEC.TAKEN .Pq Event 89H , Umask 80H Qualify mispredicted taken near branches executed. Must combine with 01H,02H, 04H, 08H, 10H, 20H. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH Counts all near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w. .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H , Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H , Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H , Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H , Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H , Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H , Umask 30H Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH , Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH , Umask 08H DSB Fill encountered > 3 DSB lines. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.THREAD .Pq Event B1H , Umask 01H Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. Do not need to set ANY. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Off-core Response Performance Monitoring. PMC0 only. Requires programming MSR 01A6H. .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Off-core Response Performance Monitoring. PMC3 only. Requires programming MSR 01A7H. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread- specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. PMC1 only. Must quiesce other PMCs. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H , Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 10H Number of transitions from AVX- 256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. Supports PEBS, use Any=1 for core granular. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. Supports PEBS. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. Supports PEBS. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H , Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H , Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Sample loads with specified latency threshold. PMC3 only. Specify threshold in MSR 0x3F6. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH , Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H , Umask 01H Qualify retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H. Supports PEBS. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H , Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H , Umask 10H Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H , Umask 20H Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H , Umask 40H Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.ALL .Pq Event D0H , Umask 80H Qualify any retired memory uops. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. Supports PEBS. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops with LLC cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. Supports PEBS. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. Counting does not cover rejects. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H , Umask 04H Clean L2 cache lines evicted by the MLC prefetcher. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H , Umask 08H Dirty L2 cache lines evicted by the MLC prefetcher. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.iaf 3 , .Xr pmc.ucf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , +.Xr pmc.sandybridgexeon 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org . The support for the Ivy Bridge microarchitecture was written by .An "Fabien Thomas" .Aq fabient@FreeBSD.org . Index: stable/9/lib/libpmc/pmc.sandybridge.3 =================================================================== --- stable/9/lib/libpmc/pmc.sandybridge.3 (revision 242593) +++ stable/9/lib/libpmc/pmc.sandybridge.3 (revision 242594) @@ -1,957 +1,958 @@ .\" Copyright (c) 2012 Davide Italiano .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" -.Dd February 12, 2012 +.Dd October 19, 2012 .Dt PMC.SANDYBRIDGE 3 .Os .Sh NAME .Nm pmc.sandybridge .Nd measurement events for .Tn Intel .Tn Sandy Bridge family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Sandy Bridge" CPUs contain PMCs conforming to the version 3 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .It Li PMC_CLASS_TSC These PMCs are documented in .Xr pmc.tsc 3 . .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Sandy Bridge PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-039US" .%D May 2011 .%Q "Intel Corporation" .Re .Ss SANDY BRIDGE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss SANDY BRIDGE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNPI_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM Target was non-DRAM system address. This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Sandy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.DATA_UNKNOWN .Pq EVENT_03H, Umask 01H Blocked loads due to store buffer blocks with unknown data. .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H, Umask 02H Loads blocked by overlapping with store buffer that cannot be forwarded. .It Li LD_BLOCKS.NO_SR .Pq Event 03H, Umask 08H # of Split loads blocked due to resource not available. .It Li LD_BLOCKS.ALL_BLOCK .Pq EVENT_03H, Umask 10H Number of cases where any load is blocked but has no DCU miss. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H, Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H, Umask 02H Speculative cache-line split Store-address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H, Umask 01H False dependencies in MOB due to partial compare on address. .It Li LD_BLOCKS_PARTIAL.ALL_STA_BLOCK .Pq Event 07H, Umask 08H The number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type. .It LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H, Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H, Umask 02H Misses in all TLB levels that caused page walk completed of any size. .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H, Umask 04H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H, Umask 10H Number of cache load STLB hits. No page walk. .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH, Umask 03H Cycles waiting to recover after Machine Clears or JEClear. Set Cmask = 1. Set Edge to count occurrences .It Li INT_MISC.RAT_STALL_CYCLES .Pq Event 0DH, Umask 40H Cycles RAT external stall is sent to IDQ for this thread. .It Li UOPS_ISSUED.ANY .Pq Event 0EH, Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core. Set Cmask = 1, Inv = 1 to count stalled cycles .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H, Umask 01H Counts number of X87 uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE .Pq Event 10H, Umask 10H Counts number of SSE* double precision FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE .Pq Event 10H, Umask 20H Counts number of SSE* single precision FP scalar uops executed. .It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE .Pq Event 10H, Umask 40H Counts number of SSE* single precision FP packed uops executed. .It LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE .Pq Event 10H, Umask 80H Counts number of SSE* double precision FP scalar uops executed. .It Li SIMD_FP_256.PACKED_SINGLE .Pq Event 11H, Umask 01H Counts 256-bit packed single-precision floating-point instructions. .It Li SIMD_FP_256.PACKED_DOUBLE .Pq Event 11H, Umask 02H Counts 256-bit packed double-precision floating-point instructions. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H, Umask 01H Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. .It Li INSTS_WRITTEN_TO_IQ.INSTS .Pq Event 17H, Umask 01H Counts the number of instructions written into the IQ every cycle. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H, Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H, Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H, Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H, Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H, Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H, Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H, Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H, Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H, Umask 40H Requests from L2 Hardware prefetcher that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H, Umask 80H Requests from L2 Hardware prefetcher that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H, Umask C0H Any requests from L2 Hardware prefetchers. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H, Umask 01H RFOs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_E .Pq Event 27H, Umask 04H RFOs that hit cache lines in E state. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq EVENT_27H, Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq EVENT_27H, Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H, Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H, Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH, Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH, Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH, Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH, Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H, Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences. Counter 2 only; Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H, Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H, Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H, Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H, Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH, Umask 01H Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PER.HW_PF .Pq Event 4CH, Umask 02H Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li HW_PRE_REQ.DL1_MISS .Pq Event 4EH, Umask 02H Hardware Prefetch requests that miss the L1D cache. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for example. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. .It Li L1D.REPLACEMENT .Pq Event 51H, Umask 01H Counts the number of lines brought into the L1 data cache. .It Li L1D.ALLOCATED_IN_M .Pq Event 51H, Umask 02H Counts the number of allocations of modified L1D cache lines. .It Li L1D.EVICTION .Pq Event 51H, Umask 04H Counts the number of modified lines evicted from the L1 data cache due to replacement. .It Li L1D.ALL_M_REPLACEMENT .Pq Event 51H, Umask 08H Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement. .It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP .Pq Event 59H, Umask 20H Increments the number of flags-merge uops in flight each cycle. Set Cmask = 1 to count cycles. .It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW .Pq Event 59H, Umask 40H Cycles with at least one slow LEA uop allocated. .It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP .Pq Event 59H, Umask 80H Number of Multiply packed/scalar single precision uops allocated. .It Li RESOURCE_STALLS2.ALL_FL_EMPTY .Pq Event 5BH, Umask 0CH Cycles stalled due to free list empty. .It Li RESOURCE_STALLS2.ALL_PRF_CONTROL .Pq Event 5BH, Umask 0FH Cycles stalled due to control structures full for physical registers. .It Li RESOURCE_STALLS2.BOB_FULL .Pq Event 5BH, Umask 40H Cycles Allocator is stalled due to Branch Order Buffer. .It Li RESOURCE_STALLS2.OOO_RSRC .Pq Event 5BH, Umask 4FH Cycles stalled due to out of order resources full. .It Li CPL_CYCLES.RING0 .Pq Event 5CH, Umask 01H Unhalted core cycles when the thread is in ring 0. Use Edge to count transition .It Li CPL_CYCLES.RING123 .Pq Event 5CH, Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH, Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H, Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H, Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H, Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H, Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H, Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H, Umask 02H Counts cycles the IDQ is empty. .It Li IQD.MITE_UOPS .Pq Event 79H, Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. Can combine Umask 04H and 20H .It Li IDQ.DSB_UOPS .Pq Event 79H, Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. Can combine Umask 08H and 10H .It Li IDQ.MS_DSB_UOPS .Pq Event 79H, Umask 10H Increment each cycle # of uops delivered to IDQ when MS busy by DSB. Set Cmask = 1 to count cycles MS is busy. Set Cmask=1 and Edge=1 to count MS activations. Can combine Umask 08H and 10H .It Li IDQ.MS_MITE_UOPS .Pq Event 79H, Umask 20H Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H and 20H .It Li IDQ.MS_UOPS .Pq Event 79H, Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H and 30H .It Li ICACHE.MISSES .Pq Event 80H, Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H, Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H, Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H, Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H, Umask 10H Number of cache load STLB hits. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H, Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H, Umask 04H Stall cycles due to IQ is full. .It Li BR_INST_EXEC.COND .Pq Event 88H, Umask 01H Qualify conditional near branch instructions executed, but not necessarily retired. Must combine with umask 40H, 80H .It Li BR_INST_EXEC.DIRECT_JMP .Pq Event 88H, Umask 02H Qualify all unconditional near branch instructions excluding calls and indirect branches. Must combine with umask 80H .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 88H, Umask 04H Qualify executed indirect near branch instructions that are not calls nor returns. Must combine with umask 80H .It Li BR_INST_EXEC.RETURN_NEAR .Pq Event 88H, Umask 08H Qualify indirect near branches that have a return mnemonic. Must combine with umask 80H .It Li BR_INST_EXEC.DIRECT_NEAR_CALL .Pq Event 88H, Umask 10H Qualify unconditional near call branch instructions, excluding non call branch, executed. Must combine with umask 80H .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL .Pq Event 88H, Umask 20H Qualify indirect near calls, including both register and memory indirect, executed. Must combine with umask 80H .It Li BR_INST_EXEC.NONTAKEN .Pq Event 88H, Umask 40H Qualify non-taken near branches executed. Applicable to umask 01H only .It Li BR_INST_EXEC.TAKEN .Pq Event 88H, Umask 80H Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H, 10H, 20H .It Li BR_INST_EXE.ALL_BRANCHES .Pq Event 88H, Umask FFH Counts all near executed branches (not necessarily retired). .It Li BR_MISP_EXEC.COND .Pq Event 89H, Umask 01H Qualify conditional near branch instructions mispredicted. Must combine with umask 40H, 80H .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET .Pq Event 89H, Umask 04H Qualify mispredicted indirect near branch instructions that are not calls nor returns. Must combine with umask 80H .It Li BR_MISP_EXEC.RETURN_NEAR .Pq Event 89H, Umask 08H Qualify mispredicted indirect near branches that have a return mnemonic. Must combine with umask 80H .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL .Pq Event 89H, Umask 10H Qualify mispredicted unconditional near call branch instructions, excluding non call branch, executed. Must combine with umask 80H .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL .Pq Event 89H, Umask 20H Qualify mispredicted indirect near calls, including both register and memory indirect, executed. Must combine with umask 80H .It Li BR_MISP_EXEC.NONTAKEN .Pq Event 89H, Umask 40H Qualify mispredicted non-taken near branches executed. Applicable to umask 01H only .It Li BR_MISP_EXEC.TAKEN .Pq Event 89H, Umask 80H Qualify mispredicted taken near branches executed. Must combine with 01H,02H, 04H, 08H, 10H, 20H .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H, Umask FFH Counts all near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH, Umask 01H Count number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H, Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H, Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H, Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H, Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H, Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H, Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H, Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H, Umask 30H .Pq Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H, Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H, Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H, Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.LB .Pq Event A2H, Umask 02H Counts the cycles of stall due to lack of load buffers. .It Li RESOURCE_STALLS.LB .Pq Event A2H, Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H, Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync) .It Li RESOURCE_STALLS.ROB .Pq Event A2H, Umask 10H Cycles stalled due to re-order buffer full. .It Li RESOURCE_STALLS.FCSW .Pq Event A2H, Umask 20H Cycles stalled due to writing the FPU control word. .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H, Umask 40H Cycles stalled due to the MXCSR register rename occurring to close to a previous MXCSR rename. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H, Umask 80H Cycles stalled while execution was stalled due to other resource issues. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH, Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH, Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.OTHER_CANCEL .Pq Event ACH, Umask 02H Cases of cancelling valid DSB fill not because of exceeding way limit. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH, Umask 08H DSB Fill encountered > 3 DSB lines. .It Li DSB_FILL.ALL_CANCEL .Pq Event ACH, Umask 0AH Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit. .It Li ITLB.ITLB_FLUSH .Pq Event AEH, Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H, Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H, Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H, Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_DISPATCHED.THREAD .Pq Event B1H, Umask 01H Counts total number of uops to be dispatched per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_DISPATCHED.CORE .Pq Event B1H, Umask 02H Counts total number of uops to be dispatched per-core each cycle. Do not need to set ANY .It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL .Pq Event B2H, Umask 01H Offcore requests buffer cannot take more entries for this thread core. .It Li AGU_BYPASS_CANCEL.COUNT .Pq Event B6H, Umask 01H Counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another page. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H, Umask 01H Off-core Response Performance Monitoring; PMC0 only. Requires programming MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH, Umask 01H Off-core Response Performance Monitoring. PMC3 only. Requires programming MSR 01A7H .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH, Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH, Umask 20H Count number of STLB flush attempts. .It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES .Pq Event BFH, Umask 05H Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports. cmask=1 .It Li INST_RETIRED.ANY_P .Pq Event C0H, Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.PREC_DIST .Pq Event C0H, Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution PMC1 only; Must quiesce other PMCs. .It Li INST_RETIRED.X87 .Pq Event C0H, Umask 02H X87 instruction retired event. .It Li OTHER_ASSISTS.ITLB_MISS_RETIRED .Pq Event C1H, Umask 02H Instructions that experienced an ITLB miss. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H, Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H, Umask 10H Number of transitions from AVX256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H, Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H, Umask 01H Counts the number of micro-ops retired. Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H, Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H, Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H, Umask 04H Counts the number of times that a program writes to a code section. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H, Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCH .Pq Event C4H, Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H, Umask 01H Counts the number of conditional branch instructions retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H, Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H, Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H, Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H, Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H, Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H, Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H, Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H, Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H, Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCH .Pq Event C5H, Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H, Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H, Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH, Umask 02H Number of X87 assists due to output value. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH, Umask 04H Number of X87 assists due to input value. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH, Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH, Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH, Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH, Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH, Umask 01H Sample loads with specified latency threshold. PMC3 only. Specify threshold in MSR 0x3F6. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH, Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H, Umask 01H Qualify retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H, Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H, Umask 10H Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H, Umask 20H Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H, Umask 40H Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED_ALL .Pq Event D0H, Umask 80H Qualify any retired memory uops. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H, Umask 01H Retired load uops with L1 cache hits as data sources. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H, Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H, Umask 04H Retired load uops which data sources were data hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H, Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H, Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H, Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H, Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H, Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS .Pq Event D4H, Umask 02H Retired load uops with unknown information as data source in cache serviced the load. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H, Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RF0 .Pq Event F0H, Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H, Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H, Umask 08H L2 or LLC HW prefetches that access L2 cache. .It Li L2_TRANS.L1D_WB .Pq Event F0H, Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H, Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H, Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H, Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H, Umask 01H L2 cache lines in I state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.S .Pq Event F1H, Umask 02H L2 cache lines in S state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.E .Pq Event F1H, Umask 04H L2 cache lines in E state filling L2. Counting does not cover rejects. .It Li L2_LINES-IN.ALL .Pq Event F1H, Umask 07H L2 cache lines filling L2. Counting does not cover rejects. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H, Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H, Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H, Umask 04H Clean L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H, Umask 08H Dirty L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.DIRTY_ALL .Pq Event F2H, Umask 0AH Dirty L2 cache lines filling the L2. Counting does not cover rejects. .It Li SQ_MISC.SPLIT_LOCK .Pq Event F4H, Umask 10H Split locks in SQ. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridgeuc 3 , +.Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org. The support for the Sandy Bridge microarchitecture was written by .An "Davide Italiano" .Aq davide@FreeBSD.org . Index: stable/9/lib/libpmc/pmc.sandybridgeuc.3 =================================================================== --- stable/9/lib/libpmc/pmc.sandybridgeuc.3 (revision 242593) +++ stable/9/lib/libpmc/pmc.sandybridgeuc.3 (revision 242594) @@ -1,234 +1,235 @@ .\" Copyright (c) 2012 Davide Italiano .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" -.Dd February 12, 2012 +.Dd October 19, 2012 .Dt PMC.SANDYBRIDGEUC 3 .Os .Sh NAME .Nm pmc.sandybridgeuc .Nd uncore measurement events for .Tn Intel .Tn Sandy Bridge family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Sandy Bridge" CPUs contain PMCs conforming to version 3 of the .Tn Intel performance measurement architecture. These CPUs contain two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_UCP" .It Li PMC_CLASS_UCF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_UCP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Sandy Bridge PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-039US" .%D May 2011 .%Q "Intel Corporation" .Re .Ss SANDYBRIDGE UNCORE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.ucf 3 . Not all CPUs in this family implement fixed-function counters. .Ss SANDYBRIDGE UNCORE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta \&No .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta \&No .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta \&No .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .El .Ss Event Specifiers (Programmable PMCs) Sandy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li CBO_XSNP_RESPONSE.RSPIHITI .Pq Event 22H, Umask 01H Snoop responses received from processor cores to requests initiated by this Cbox. Must combine with one of the umask values of 20H, 40H, 80H .It Li CBO_XSNP_RESPONSE.RSPIHITFSE .Pq Event 22H, Umask 02H Must combine with one of the umask values of 20H, 40H, 80H .It Li CBO_XSNP_RESPONSE.RSPSHITFSE .Pq Event 22H, Umask 04H Must combine with one of the umask values of 20H, 40H, 80H .It Li CBO_XSNP_RESPONSE.RSPSFWDM .Pq Event 22H, Umask 08H .It Li CBO_XSNP_RESPONSE.RSPIFWDM .Pq Event 22H, Umask 01H .It Li CBO_XSNP_RESPONSE.AND_EXTERNAL .Pq Event 22H, Umask 20H Filter on cross-core snoops resulted in external snoop request. Must combine with at least one of 01H, 02H, 04H, 08H, 10H .It Li CBO_XSNP_RESPONSE.AND_XCORE .Pq Event 22H, Umask 40H Filter on cross-core snoops resulted in core request. Must combine with at least one of 01H, 02H, 04H, 08H, 10H .It Li CBO_XSNP_RESPONSE.AND_XCORE .Pq Event 22H, Umask 80H Filter on cross-core snoops resulted in LLC evictions. Must combine with at least one of 01H, 02H, 04H, 08H, 10H .It Li CBO_CACHE_LOOKUP.M .Pq Event 34H, Umask 01H LLC lookup request that access cache and found line in M-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H .It Li CBO_CACHE_LOOKUP.E .Pq Event 34H, Umask 02H LLC lookup request that access cache and found line in E-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H .It Li CBO_CACHE_LOOKUP.S .Pq Event 34H, Umask 04H LLC lookup request that access cache and found line in S-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H .It Li CBO_CACHE_LOOKUP.I .Pq Event 34H, Umask 08H LLC lookup request that access cache and found line in I-state. Must combine with one of the umask values of 10H, 20H, 40H, 80H .It Li CBO_CACHE_LOOKUP.AND_READ .Pq Event 34H, Umask 10H Filter on processor core initiated cacheable read requests. Must combine with at least one of 01H, 02H, 04H, 08H .It Li CBO_CACHE_LOOKUP_AND_READ2 .Pq Event 34H, Umask 20H Filter on processor core initiated cacheable write requests. Must combine with at least one of 01H, 02H, 04H, 08H .It Li CBO_CACHE_LOOKUP.AND_EXTSNP .Pq Event 34H, Umask 40H Filter on external snoop requests. Must combine with at least one of 01H, 02H, 04H, 08H .It Li CBO_CACHE_LOOKUP.AND_ANY .Pq Event 34H, Umask 80H Filter on any IRQ or IPQ initiated requests including uncacheable, noncoherent requests. Must combine with at least one of 01H, 02H, 04H, 08H .It Li IMPH_CBO_TRK_OCCUPANCY.ALL .Pq Event 80H, Umask 01H Counts cycles weighted by the number of core-outgoing valid entries. Valid entries are between allocation to the first of IDIO or DRSO messages. Accounts for coherent and incoherent traffic. Counter 0 only .It Li IMPH_CBO_TRK_REQUEST.ALL .Pq Event 81H, Umask 01H Counts the number of core-outgoing entries. Accounts for coherent and incoherent traffic. .It Li IMPH_CBO_TRK_REQUEST.WRITES .Pq Event 81H, Umask 20H Counts the number of allocated write entries, include full, partial, and evictions. .It Li IMPH_CBO_TRK_REQUEST.EVICTIONS .Pq Event 81H, Umask 80H Counts the number of evictions allocated. .It Li IMPH_COH_TRK_OCCUPANCY.ALL .Pq Event 83H, Umask 01H Counts cycles weighted by the number of core-outgoing valid entries in the coherent tracker queue. Counter 0 only .It Li IMPH_COH_TRK_REQUEST.ALL .Pq Event 84H, Umask 01H Counts the number of core-outgoing entries in the coherent tracker queue. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridge 3 , +.Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org . The support for the .Lb Sandy Bridge microarchitecture was added by .An "Davide Italiano" .Aq davide@FreeBSD.org . Index: stable/9/lib/libpmc/pmc.sandybridgexeon.3 =================================================================== --- stable/9/lib/libpmc/pmc.sandybridgexeon.3 (nonexistent) +++ stable/9/lib/libpmc/pmc.sandybridgexeon.3 (revision 242594) @@ -0,0 +1,1023 @@ +.\" Copyright (c) 2012 Hiren Panchasara +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd October 18, 2012 +.Dt PMC.SANDYBRIDGEXEON 3 +.Os +.Sh NAME +.Nm pmc.sandybridgexeon +.Nd measurement events for +.Tn Intel +.Tn Sandy Bridge Xeon +family CPUs +.Sh LIBRARY +.Lb libpmc +.Sh SYNOPSIS +.In pmc.h +.Sh DESCRIPTION +.Tn Intel +.Tn "Sandy Bridge Xeon" +CPUs contain PMCs conforming to version 2 of the +.Tn Intel +performance measurement architecture. +These CPUs may contain up to two classes of PMCs: +.Bl -tag -width "Li PMC_CLASS_IAP" +.It Li PMC_CLASS_IAF +Fixed-function counters that count only one hardware event per counter. +.It Li PMC_CLASS_IAP +Programmable counters that may be configured to count one of a defined +set of hardware events. +.El +.Pp +The number of PMCs available in each class and their widths need to be +determined at run time by calling +.Xr pmc_cpuinfo 3 . +.Pp +Intel Sandy Bridge Xeon PMCs are documented in +.Rs +.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" +.%T "Volume 3B: System Programming Guide, Part 2" +.%N "Order Number: 253669-043US" +.%D August 2012 +.%Q "Intel Corporation" +.Re +.Ss SANDYBRIDGE XEON FIXED FUNCTION PMCS +These PMCs and their supported events are documented in +.Xr pmc.iaf 3 . +.Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS +The programmable PMCs support the following capabilities: +.Bl -column "PMC_CAP_INTERRUPT" "Support" +.It Em Capability Ta Em Support +.It PMC_CAP_CASCADE Ta \&No +.It PMC_CAP_EDGE Ta Yes +.It PMC_CAP_INTERRUPT Ta Yes +.It PMC_CAP_INVERT Ta Yes +.It PMC_CAP_READ Ta Yes +.It PMC_CAP_PRECISE Ta \&No +.It PMC_CAP_SYSTEM Ta Yes +.It PMC_CAP_TAGGING Ta \&No +.It PMC_CAP_THRESHOLD Ta Yes +.It PMC_CAP_USER Ta Yes +.It PMC_CAP_WRITE Ta Yes +.El +.Ss Event Qualifiers +Event specifiers for these PMCs support the following common +qualifiers: +.Bl -tag -width indent +.It Li rsp= Ns Ar value +Configure the Off-core Response bits. +.Bl -tag -width indent +.It Li REQ_DMND_DATA_RD +Counts the number of demand and DCU prefetch data reads of full and partial +cachelines as well as demand data page table entry cacheline reads. Does not +count L2 data read prefetches or instruction fetches. +.It Li REQ_DMND_RFO +Counts the number of demand and DCU prefetch reads for ownership (RFO) +requests generated by a write to data cacheline. Does not count L2 RFO +prefetches. +.It Li REQ_DMND_IFETCH +Counts the number of demand and DCU prefetch instruction cacheline reads. +Does not count L2 code read prefetches. +.It Li REQ_WB +Counts the number of writeback (modified to exclusive) transactions. +.It Li REQ_PF_DATA_RD +Counts the number of data cacheline reads generated by L2 prefetchers. +.It Li REQ_PF_RFO +Counts the number of RFO requests generated by L2 prefetchers. +.It Li REQ_PF_IFETCH +Counts the number of code reads generated by L2 prefetchers. +.It Li REQ_PF_LLC_DATA_RD +L2 prefetcher to L3 for loads. +.It Li REQ_PF_LLC_RFO +RFO requests generated by L2 prefetcher +.It Li REQ_PF_LLC_IFETCH +L2 prefetcher to L3 for instruction fetches. +.It Li REQ_BUS_LOCKS +Bus lock and split lock requests. +.It Li REQ_STRM_ST +Streaming store requests. +.It Li REQ_OTHER +Any other request that crosses IDI, including I/O. +.It Li RES_ANY +Catch all value for any response types. +.It Li RES_SUPPLIER_NO_SUPP +No Supplier Information available. +.It Li RES_SUPPLIER_LLC_HITM +M-state initial lookup stat in L3. +.It Li RES_SUPPLIER_LLC_HITE +E-state. +.It Li RES_SUPPLIER_LLC_HITS +S-state. +.It Li RES_SUPPLIER_LLC_HITF +F-state. +.It Li RES_SUPPLIER_LOCAL +Local DRAM Controller. +.It Li RES_SNOOP_SNPI_NONE +No details on snoop-related information. +.It Li RES_SNOOP_SNP_NO_NEEDED +No snoop was needed to satisfy the request. +.It Li RES_SNOOP_SNP_MISS +A snoop was needed and it missed all snooped caches: +-For LLC Hit, ReslHitl was returned by all cores +-For LLC Miss, Rspl was returned by all sockets and data was returned from +DRAM. +.It Li RES_SNOOP_HIT_NO_FWD +A snoop was needed and it hits in at least one snooped cache. Hit denotes a +cache-line was valid before snoop effect. This includes: +-Snoop Hit w/ Invalidation (LLC Hit, RFO) +-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) +-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) +In the LLC Miss case, data is returned from DRAM. +.It Li RES_SNOOP_HIT_FWD +A snoop was needed and data was forwarded from a remote socket. +This includes: +-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). +.It Li RES_SNOOP_HITM +A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a +cache-line was in modified state before effect as a results of snoop. This +includes: +-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) +-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) +-Snoop MtoS (LLC Hit, IFetch/Data_RD). +.It Li RES_NON_DRAM +Target was non-DRAM system address. This includes MMIO transactions. +.El +.It Li cmask= Ns Ar value +Configure the PMC to increment only if the number of configured +events measured in a cycle is greater than or equal to +.Ar value . +.It Li edge +Configure the PMC to count the number of de-asserted to asserted +transitions of the conditions expressed by the other qualifiers. +If specified, the counter will increment only once whenever a +condition becomes true, irrespective of the number of clocks during +which the condition remains true. +.It Li inv +Invert the sense of comparison when the +.Dq Li cmask +qualifier is present, making the counter increment when the number of +events per cycle is less than the value specified by the +.Dq Li cmask +qualifier. +.It Li os +Configure the PMC to count events happening at processor privilege +level 0. +.It Li usr +Configure the PMC to count events occurring at privilege levels 1, 2 +or 3. +.El +.Pp +If neither of the +.Dq Li os +or +.Dq Li usr +qualifiers are specified, the default is to enable both. +.Ss Event Specifiers (Programmable PMCs) +Sandy Bridge Xeon programmable PMCs support the following events: +.Bl -tag -width indent +.It Li LD_BLOCKS.DATA_UNKNOWN +.Pq Event 03H , Umask 01H +blocked loads due to store buffer blocks with unknown data. +.It Li LD_BLOCKS.STORE_FORWARD +.Pq Event 03H , Umask 02H +loads blocked by overlapping with store buffer that cannot +be forwarded . +.It Li LD_BLOCKS.NO_SR +.Pq Event 03H , Umask 08H +# of Split loads blocked due to resource not available. +.It Li LD_BLOCKS.ALL_BLOCK +.Pq Event 03H , Umask 10H +Number of cases where any load is blocked but has no +DCU miss. +.It Li MISALIGN_MEM_REF.LOADS +.Pq Event 05H , Umask 01H +Speculative cache-line split load uops dispatched to +L1D. +.It Li MISALIGN_MEM_REF.STORES +.Pq Event 05H , Umask 02H +Speculative cache-line split Store- address uops +dispatchedto L1D. +.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS +.Pq Event 07H , Umask 01H +False dependencies in MOB due to partial compare on +address. +.It Li LD_BLOCKS_PARTIAL.ALL_STALL_BLOCK +.Pq Event 07H , Umask 08H +The number of times that load operations are temporarily +blocked because of older stores, with addresses that are +not yet known. A load operation may incur more than one +block of this type. +.It Li TLB_LOAD_MISSES.MISS_CAUSES_A_WALK +.Pq Event 08H , Umask 01H +Misses in all TLB levels that cause a page walk of any +page size. +.It Li TLB_LOAD_MISSES.WALK_COMPLETED +.Pq Event 08H , Umask 02H +Misses in all TLB levels that caused page walk completed +of any size. +.It Li DTLB_LOAD_MISSES.WALK_DURATION +.Pq Event 08H , Umask 04H +Cycle PMH is busy with a walk. +.It Li DTLB_LOAD_MISSES.STLB_HIT +.Pq Event 08H , Umask 10H +Number of cache load STLB hits. No page walk. +.It Li INT_MISC.RECOVERY_CYCLES +.Pq Event 0DH , Umask 03H +Cycles waiting to recover after Machine Clears or EClear. +Set Cmask= 1. +.It Li INT_MISC.RAT_STALL_CYCLES +.Pq Event 0DH , Umask 40H +Cycles RAT external stall is sent to IDQ for this thread. +.It Li UOPS_ISSUED.ANY +.Pq Event 0EH , Umask 01H +Increments each cycle the # of Uops issued by the +RAT to RS. +Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles +of this core. +.It Li FP_COMP_OPS_EXE.X87 +.Pq Event 10H , Umask 01H +Counts number of X87 uops executed. +.It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE +.Pq Event 10H , Umask 10H +Counts number of SSE* double precision FP packed +uops executed. +.It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE +.Pq Event 10H , Umask 20H +Counts number of SSE* single precision FP scalar +uops executed. +.It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE +.Pq Event 10H , Umask 40H +Counts number of SSE* single precision FP packed +uops executed. +.It Li FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE +.Pq Event 10H , Umask 80H +Counts number of SSE* double precision FP scalar +uops executed. +.It Li SIMD_FP_256.PACKED_SINGLE +.Pq Event 11H , Umask 01H +Counts 256-bit packed single-precision floating- +point instructions. +.It Li SIMD_FP_256.PACKED_DOUBLE +.Pq Event 11H , Umask 02H +Counts 256-bit packed double-precision floating- +point instructions. +.It Li ARITH.FPU_DIV_ACTIVE +.Pq Event 14H , Umask 01H +Cycles that the divider is active, includes INT and FP. +Set 'edge =1, cmask=1' to count the number of +divides. +.It Li INSTS_WRITTEN_TO_IQ.INSTS +.Pq Event 17H , Umask 01H +Counts the number of instructions written into the +IQ every cycle. +.It Li L2_RQSTS.DEMAND_DATA_RD_HIT +.Pq Event 24H , Umask 01H +Demand Data Read requests that hit L2 cache. +.It Li L2_RQSTS.ALL_DEMAND_DATA_RD +.Pq Event 24H , Umask 03H +Counts any demand and L1 HW prefetch data load +requests to L2. +.It Li L2_RQSTS.RFO_HITS +.Pq Event 24H , Umask 04H +Counts the number of store RFO requests that +hit the L2 cache. +.It Li L2_RQSTS.RFO_MISS +.Pq Event 24H , Umask 08H +Counts the number of store RFO requests that +miss the L2 cache. +.It Li L2_RQSTS.ALL_RFO +.Pq Event 24H , Umask 0CH +Counts all L2 store RFO requests. +.It Li L2_RQSTS.CODE_RD_HIT +.Pq Event 24H , Umask 10H +Number of instruction fetches that hit the L2 +cache. +.It Li L2_RQSTS.CODE_RD_MISS +.Pq Event 24H , Umask 20H +Number of instruction fetches that missed the L2 +cache. +.It Li L2_RQSTS.ALL_CODE_RD +.Pq Event 24H , Umask 30H +Counts all L2 code requests. +.It Li L2_RQSTS.PF_HIT +.Pq Event 24H , Umask 40H +Requests from L2 Hardware prefetcher that hit L2. +.It Li L2_RQSTS.PF_MISS +.Pq Event 24H , Umask 80H +Requests from L2 Hardware prefetcher that missed +L2. +.It Li L2_RQSTS.ALL_PF +.Pq Event 24H , Umask C0H +Any requests from L2 Hardware prefetchers. +.It Li L2_STORE_LOCK_RQSTS.MISS +.Pq Event 27H , Umask 01H +ROs that miss cache lines. +.It Li L2_STORE_LOCK_RQSTS.HIT_E +.Pq Event 27H , Umask 04H +RFOs that hit cache lines in E state. +.It Li L2_STORE_LOCK_RQSTS.HIT_M +.Pq Event 27H , Umask 08H +RFOs that hit cache lines in M state. +.It Li L2_STORE_LOCK_RQSTS.ALL +.Pq Event 27H , Umask 0FH +RFOs that access cache lines in any state. +.It Li L2_L1D_WB_RQSTS.MISS +.Pq Event 28H , Umask 01H +Not rejected writebacks from L1D to L2 cache lines +that missed L2. +.It Li L2_L1D_WB_RQSTS.HIT_S +.Pq Event 28H , Umask 02H +Not rejected writebacks from L1D to L2 cache lines +in S state. +.It Li L2_L1D_WB_RQSTS.HIT_E +.Pq Event 28H , Umask 04H +Not rejected writebacks from L1D to L2 cache lines +in E state. +.It Li L2_L1D_WB_RQSTS.HIT_M +.Pq Event 28H , Umask 08H +Not rejected writebacks from L1D to L2 cache lines +in M state. +.It Li L2_L1D_WB_RQSTS.ALL +.Pq Event 28H , Umask 0FH +Not rejected writebacks from L1D to L2 cache. +.It Li LONGEST_LAT_CACHE.REFERENCE +.Pq Event 2EH , Umask 4FH +This event counts requests originating from the +core that reference +a cache line in the last level cache. +.It Li LONGEST_LAT_CACHE.MISS +.Pq Event 2EH , Umask 41H +This event counts each cache miss condition for +references to the last level cache. +.It Li CPU_CLK_UNHALTED.THREAD_P +.Pq Event 3CH , Umask 00H +Counts the number of thread cycles while the +thread is not in a halt state. The thread enters +the halt state when it is running the HLT +instruction. The core frequency may change from +time to time due to power or thermal throttling. +.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK +.Pq Event 3CH , Umask 01H +Increments at the frequency of XCLK (100 MHz) +when not halted. +.It Li L1D_PEND_MISS.PENDING +.Pq Event 48H , Umask 01H +Increments the number of outstanding L1D misses +every cycle. +Set Cmaks = 1 and Edge =1 to count occurrences. +.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK +.Pq Event 49H , Umask 01H +Miss in all TLB levels causes an page walk of +any page size (4K/2M/4M/1G). +.It Li DTLB_STORE_MISSES.WALK_COMPLETED +.Pq Event 49H , Umask 02H +Miss in all TLB levels causes a page walk that +completes of any page size (4K/2M/4M/1G). +.It Li DTLB_STORE_MISSES.WALK_DURATION +.Pq Event 49H , Umask 04H +Cycles PMH is busy with this walk. +.It Li DTLB_STORE_MISSES.STLB_HIT +.Pq Event 49H , Umask 10H +Store operations that miss the first TLB level +but hit the second and do not cause page walks. +.It Li LOAD_HIT_PRE.SW_PF +.Pq Event 4CH , Umask 01H +Not SW-prefetch load dispatches that hit fill +buffer allocated for S/W prefetch. +.It Li LOAD_HIT_PER.HW_PF +.Pq Event 4CH , Umask 02H +Not SW-prefetch load dispatches that hit fill +buffer allocated for H/W prefetch. +.It Li HW_PRE_REQ.DL1_MISS +.Pq Event 4EH , Umask 02H +Hardware Prefetch requests that miss the L1D +cache. A request is being counted each time +it access the cache & miss it, including if +a block is applicable or if hit the Fill +Buffer for example. +.It Li L1D.REPLACEMENT +.Pq Event 51H , Umask 01H +Counts the number of lines brought into the +L1 data cache. +.It Li L1D.ALLOCATED_IN_M +.Pq Event 51H , Umask 02H +Counts the number of allocations of modified +L1D cache lines. +.It Li L1D.EVICTION +.Pq Event 51H , Umask 04H +Counts the number of modified lines evicted +from the L1 data cache due to replacement. +.It Li L1D.ALL_M_REPLACEMENT +.Pq Event 51H , Umask 08H +Cache lines in M state evicted out of L1D due +to Snoop HitM or dirty line replacement. +.It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP +.Pq Event 59H , Umask 0CH +Increments the number of flags-merge uops in +flight each cycle. +Set Cmask = 1 to count cycles. +.It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW +.Pq Event 59H , Umask 0FH +Cycles with at least one slow LEA uop allocated. +.It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP +.Pq Event 59H , Umask 40H +Number of Multiply packed/scalar single precision +uops allocated. +.It Li RESOURCE_STALLS2.ALL_FL_EMPTY +.Pq Event 5BH , Umask 0CH +Cycles stalled due to free list empty. +.It Li RESOURCE_STALLS2.ALL_PRF_CONTROL +.Pq Event 5BH , Umask 0FH +Cycles stalled due to control structures full for +physical registers. +.It Li RESOURCE_STALLS2.BOB_FULL +.Pq Event 5BH , Umask 40H +Cycles Allocator is stalled due Branch Order Buffer. +.It Li RESOURCE_STALLS2.OOO_RSRC +.Pq Event 5BH , Umask 4FH +Cycles stalled due to out of order resources full. +.It Li CPL_CYCLES.RING0 +.Pq Event 5CH , Umask 01H +Unhalted core cycles when the thread is in ring 0. +.It Li CPL_CYCLES.RING123 +.Pq Event 5CH , Umask 02H +Unhalted core cycles when the thread is not in ring +0. +.It Li RS_EVENTS.EMPTY_CYCLES +.Pq Event 5EH , Umask 01H +Cycles the RS is empty for the thread. +.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD +.Pq Event 60H , Umask 01H +Offcore outstanding Demand Data Read +transactions in SQ to uncore. Set Cmask=1 to count +cycles. +.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO +.Pq Event 60H , Umask 04H +Offcore outstanding RFO store transactions in SQ to +uncore. Set Cmask=1 to count cycles. +.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD +.Pq Event 60H , Umask 08H +Offcore outstanding cacheable data read +transactions in SQ to uncore. Set Cmask=1 to count +cycles. +.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION +.Pq Event 63H , Umask 01H +Cycles in which the L1D and L2 are locked, due to a +UC lock or split lock. +.It Li LOCK_CYCLES.CACHE_LOCK_DURATION +.Pq Event 63H , Umask 02H +Cycles in which the L1D is locked. +.It Li IDQ.EMPTY +.Pq Event 79H , Umask 02H +Counts cycles the IDQ is empty. +.It Li IDQ.MITE_UOPS +.Pq Event 79H , Umask 04H +Increment each cycle # of uops delivered to IDQ +from MITE path. +Set Cmask = 1 to count cycles. +.It Li IDQ.DSB_UOPS +.Pq Event 79H , Umask 08H +Increment each cycle. # of uops delivered to IDQ +from DSB path. +Set Cmask = 1 to count cycles. +.It Li IDQ.MS_DSB_UOPS +.Pq Event 79H , Umask 10H +Increment each cycle # of uops delivered to IDQ +when MS busy by DSB. Set Cmask = 1 to count +cycles MS is busy. Set Cmask=1 and Edge =1 to +count MS activations. +.It Li IDQ.MS_MITE_UOPS +.Pq Event 79H , Umask 20H +Increment each cycle # of uops delivered to IDQ +when MS is busy by MITE. Set Cmask = 1 to count +cycles. +.It Li IDQ.MS_UOPS +.Pq Event 79H , Umask 30H +Increment each cycle # of uops delivered to IDQ +from MS by either DSB or MITE. Set Cmask = 1 to +count cycles. +.It Li ICACHE.MISSES +.Pq Event 80H , Umask 02H +Number of Instruction Cache, Streaming Buffer and +Victim Cache Misses. Includes UC accesses. +.It Li ITLB_MISSES.MISS_CAUSES_A_WALK +.Pq Event 85H , Umask 01H +Misses in all ITLB levels that cause page walks. +.It Li ITLB_MISSES.WALK_COMPLETED +.Pq Event 85H , Umask 02H +Misses in all ITLB levels that cause completed page +walks. +.It Li ITLB_MISSES.WALK_DURATION +.Pq Event 85H , Umask 04H +Cycle PMH is busy with a walk. +.It Li ITLB_MISSES.STLB_HIT +.Pq Event 85H , Umask 10H +Number of cache load STLB hits. No page walk. +.It Li ILD_STALL.LCP +.Pq Event 87H , Umask 01H +Stalls caused by changing prefix length of the +instruction. +.It Li ILD_STALL.IQ_FULL +.Pq Event 87H , Umask 04H +Stall cycles due to IQ is full. +.It Li BR_INST_EXEC.COND +.Pq Event 88H , Umask 01H +Qualify conditional near branch instructions +executed, but not necessarily retired. +.It Li BR_INST_EXEC.DIRECT_JMP +.Pq Event 88H , Umask 02H +Qualify all unconditional near branch instructions +excluding calls and indirect branches. +.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET +.Pq Event 88H , Umask 04H +Qualify executed indirect near branch instructions +that are not calls nor returns. +.It Li BR_INST_EXEC.RETURN_NEAR +.Pq Event 88H , Umask 08H +Qualify indirect near branches that have a return +mnemonic. +.It Li BR_INST_EXEC.DIRECT_NEAR_CALL +.Pq Event 88H , Umask 10H +Qualify unconditional near call branch instructions, +excluding non call branch, executed. +.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL +.Pq Event 88H , Umask 20H +Qualify indirect near calls, including both register +and memory indirect, executed. +.It Li BR_INST_EXEC.NONTAKEN +.Pq Event 88H , Umask 40H +Qualify non-taken near branches executed. +.It Li BR_INST_EXEC.TAKEN +.Pq Event 88H , Umask 80H +Qualify taken near branches executed. Must +combine with 01H,02H, 04H, 08H, 10H, 20H. +.It Li BR_INST_EXE.ALL_BRANCHES +.Pq Event 88H , Umask FFH +Counts all near executed branches (not necessarily +retired). +.It Li BR_MISP_EXEC.COND +.Pq Event 89H , Umask 01H +Qualify conditional near branch instructions +mispredicted. +.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET +.Pq Event 89H , Umask 04H +Qualify mispredicted indirect near branch +instructions that are not calls nor returns. +.It Li BR_MISP_EXEC.RETURN_NEAR +.Pq Event 89H , Umask 08H +Qualify mispredicted indirect near branches that +have a return mnemonic. +.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL +.Pq Event 89H , Umask 10H +Qualify mispredicted unconditional near call branch +instructions, excluding non call branch, executed. +.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL +.Pq Event 89H , Umask 20H +Qualify mispredicted indirect near calls, including +both register and memory indirect, executed. +.It Li BR_MISP_EXEC.NONTAKEN +.Pq Event 89H , Umask 40H +Qualify mispredicted non-taken near branches +executed,. +.It Li BR_MISP_EXEC.TAKEN +.Pq Event 89H , Umask 80H +Qualify mispredicted taken near branches executed. +Must combine with 01H,02H, 04H, 08H, 10H, 20H +.It Li BR_MISP_EXEC.ALL_BRANCHES +.Pq Event 89H , Umask FFH +Counts all near executed branches (not necessarily +retired). +.It Li IDQ_UOPS_NOT_DELIVERED.CORE +.Pq Event 9CH , Umask 01H +Count number of non-delivered uops to RAT per +thread. +.It Li UOPS_DISPATCHED_PORT.PORT_0 +.Pq Event A1H , Umask 01H +Cycles which a Uop is dispatched on port 0. +.It Li UOPS_DISPATCHED_PORT.PORT_1 +.Pq Event A1H , Umask 02H +Cycles which a Uop is dispatched on port 1. +.It Li UOPS_DISPATCHED_PORT.PORT_2_LD +.Pq Event A1H , Umask 04H +Cycles which a load uop is dispatched on port 2. +.It Li UOPS_DISPATCHED_PORT.PORT_2_STA +.Pq Event A1H , Umask 08H +Cycles which a store address uop is dispatched on +port 2. +.It Li UOPS_DISPATCHED_PORT.PORT_2 +.Pq Event A1H , Umask 0CH +Cycles which a Uop is dispatched on port 2. +.It Li UOPS_DISPATCHED_PORT.PORT_3_LD +.Pq Event A1H , Umask 10H +Cycles which a load uop is dispatched on port 3. +.It Li UOPS_DISPATCHED_PORT.PORT_3_STA +.Pq Event A1H , Umask 20H +Cycles which a store address uop is dispatched on +port 3. +.It Li UOPS_DISPATCHED_PORT.PORT_3 +.Pq Event A1H , Umask 30H +Cycles which a Uop is dispatched on port 3. +.It Li UOPS_DISPATCHED_PORT.PORT_4 +.Pq Event A1H , Umask 40H +Cycles which a Uop is dispatched on port 4. +.It Li UOPS_DISPATCHED_PORT.PORT_5 +.Pq Event A1H , Umask 80H +Cycles which a Uop is dispatched on port 5. +.It Li RESOURCE_STALLS.ANY +.Pq Event A2H , Umask 01H +Cycles Allocation is stalled due to Resource Related +reason. +.It Li RESOURCE_STALLS.LB +.Pq Event A2H , Umask 01H +Counts the cycles of stall due to lack of load buffers. +.It Li RESOURCE_STALLS.RS +.Pq Event A2H , Umask 04H +Cycles stalled due to no eligible RS entry available. +.It Li RESOURCE_STALLS.SB +.Pq Event A2H , Umask 08H +Cycles stalled due to no store buffers available. (not +including draining form sync). +.It Li RESOURCE_STALLS.ROB +.Pq Event A2H , Umask 10H +Cycles stalled due to re-order buffer full. +.It Li RESOURCE_STALLS.FCSW +.Pq Event A2H , Umask 20H +Cycles stalled due to writing the FPU control word. +.It Li RESOURCE_STALLS.MXCSR +.Pq Event A2H , Umask 40H +Cycles stalled due to the MXCSR register rename +occurring to close to a previous MXCSR rename. +.It Li RESOURCE_STALLS.OTHER +.Pq Event A2H , Umask 80H +Cycles stalled while execution was stalled due to +other resource issues. +.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING +.Pq Event A3H , Umask 01H +Cycles with pending L2 miss loads. Set AnyThread +to count per core. +.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING +.Pq Event A3H , Umask 02H +Cycles with pending L1 cache miss loads.Set +AnyThread to count per core. +.It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH +.Pq Event A3H , Umask 04H +Cycles of dispatch stalls. Set AnyThread to count per +core. +.It Li DSB2MITE_SWITCHES.COUNT +.Pq Event ABH , Umask 01H +Number of DSB to MITE switches. +.It Li DSB2MITE_SWITCHES.PENALTY_CYCLES +.Pq Event ABH , Umask 02H +Cycles DSB to MITE switches caused delay. +.It Li DSB_FILL.OTHER_CANCEL +.Pq Event ACH , Umask 02H +Cases of cancelling valid DSB fill not because of +exceeding way limit. +.It Li DSB_FILL.EXCEED_DSB_LINES +.Pq Event ACH , Umask 08H +DSB Fill encountered > 3 DSB lines. +.It Li DSB_FILL.ALL_CANCEL +.Pq Event ACH , Umask 0AH +Cases of cancelling valid Decode Stream Buffer +(DSB) fill not because of exceeding way limit. +.It Li ITLB.ITLB_FLUSH +.Pq Event AEH , Umask 01H +Counts the number of ITLB flushes, includes +4k/2M/4M pages. +.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD +.Pq Event B0H , Umask 01H +Demand data read requests sent to uncore. +.It Li OFFCORE_REQUESTS.DEMAND_RFO +.Pq Event B0H , Umask 04H +Demand RFO read requests sent to uncore, including +regular RFOs, locks, ItoM. +.It Li OFFCORE_REQUESTS.ALL_DATA_RD +.Pq Event B0H , Umask 08H +Data read requests sent to uncore (demand and +prefetch). +.It Li UOPS_DISPATCHED.THREAD +.Pq Event B1H , Umask 01H +Counts total number of uops to be dispatched per- +thread each cycle. Set Cmask = 1, INV =1 to count +stall cycles. +.It Li UOPS_DISPATCHED.CORE +.Pq Event B1H , Umask 02H +Counts total number of uops to be dispatched per- +core each cycle. +.It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL +.Pq Event B2H , Umask 01H +Offcore requests buffer cannot take more entries +for this thread core. +.It Li AGU_BYPASS_CANCEL.COUNT +.Pq Event B6H , Umask 01H +Counts executed load operations with all the +following traits: 1. addressing of the format [base + +offset], 2. the offset is between 1 and 2047, 3. the +address specified in the base register is in one page +and the address [base+offset] is in another page. +.It Li OFF_CORE_RESPONSE_0 +.Pq Event B7H , Umask 01H +(Event B7H, Umask 01H) Off-core Response Performance +Monitoring; PMC0 only. Requires programming MSR 01A6H +.It Li OFF_CORE_RESPONSE_1 +.Pq Event BBH , Umask 01H +(Event BBH, Umask 01H) Off-core Response Performance +Monitoring; PMC3 only. Requires programming MSR 01A7H +.It Li TLB_FLUSH.DTLB_THREAD +.Pq Event BDH , Umask 01H +DTLB flush attempts of the thread-specific entries. +.It Li TLB_FLUSH.STLB_ANY +.Pq Event BDH , Umask 20H +Count number of STLB flush attempts. +.It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES +.Pq Event BFH , Umask 05H +Cycles when dispatched loads are cancelled due to +L1D bank conflicts with other load ports. +.It Li INST_RETIRED.ANY_P +.Pq Event C0H , Umask 00H +Number of instructions at retirement. +.It Li INST_RETIRED.ALL +.Pq Event C0H , Umask 01H +Precise instruction retired event with HW to reduce +effect of PEBS shadow in IP distribution. +.It Li OTHER_ASSISTS.ITLB_MISS_RETIRED +.Pq Event C1H , Umask 02H +Instructions that experienced an ITLB miss. +.It Li OTHER_ASSISTS.AVX_STORE +.Pq Event C1H , Umask 08H +Number of assists associated with 256-bit AVX +store operations. +.It Li OTHER_ASSISTS.AVX_TO_SSE +.Pq Event C1H , Umask 10H +Number of transitions from AVX-256 to legacy SSE +when penalty applicable. +.It Li OTHER_ASSISTS.SSE_TO_AVX +.Pq Event C1H , Umask 20H +Number of transitions from SSE to AVX-256 when +penalty applicable. +.It Li UOPS_RETIRED.ALL +.Pq Event C2H , Umask 01H +Counts the number of micro-ops retired, Use +cmask=1 and invert to count active cycles or stalled +cycles. +.It Li UOPS_RETIRED.RETIRE_SLOTS +.Pq Event C2H , Umask 02H +Counts the number of retirement slots used each +cycle. +.It Li MACHINE_CLEARS.MEMORY_ORDERING +.Pq Event C3H , Umask 02H +Counts the number of machine clears due to +memory order conflicts. +.It Li MACHINE_CLEARS.SMC +.Pq Event C3H , Umask 04H +Counts the number of times that a program writes +to a code section. +.It Li MACHINE_CLEARS.MASKMOV +.Pq Event C3H , Umask 20H +Counts the number of executed AVX masked load +operations that refer to an illegal address range +with the mask bits set to 0. +.It Li BR_INST_RETIRED.ALL_BRANCH +.Pq Event C4H , Umask 00H +Branch instructions at retirement. +.It Li BR_INST_RETIRED.CONDITIONAL +.Pq Event C4H , Umask 01H +Counts the number of conditional branch +instructions retired. +.It Li BR_INST_RETIRED.NEAR_CALL +.Pq Event C4H , Umask 02H +Direct and indirect near call instructions retired. +.It Li BR_INST_RETIRED.ALL_BRANCHES +.Pq Event C4H , Umask 04H +Counts the number of branch instructions retired. +.It Li BR_INST_RETIRED.NEAR_RETURN +.Pq Event C4H , Umask 08H +Counts the number of near return instructions +retired. +.It Li BR_INST_RETIRED.NOT_TAKEN +.Pq Event C4H , Umask 10H +Counts the number of not taken branch instructions +retired. +.It Li BR_INST_RETIRED.NEAR_TAKEN +.Pq Event C4H , Umask 20H +Number of near taken branches retired. +.It Li BR_INST_RETIRED.FAR_BRANCH +.Pq Event C4H , Umask 40H +Number of far branches retired. +.It Li BR_MISP_RETIRED.ALL_BRANCHES +.Pq Event C5H , Umask 00H +Mispredicted branch instructions at retirement. +.It Li BR_MISP_RETIRED.CONDITIONAL +.Pq Event C5H , Umask 01H +Mispredicted conditional branch instructions retired. +.It Li BR_MISP_RETIRED.NEAR_CALL +.Pq Event C5H , Umask 02H +Direct and indirect mispredicted near call +instructions retired. +.It Li BR_MISP_RETIRED.ALL_BRANCHES +.Pq Event C5H , Umask 04H +Mispredicted macro branch instructions retired. +.It Li BR_MISP_RETIRED.NOT_TAKEN +.Pq Event C5H , Umask 10H +Mispredicted not taken branch instructions retired. +.It Li BR_MISP_RETIRED.TAKEN +.Pq Event C5H , Umask 20H +Mispredicted taken branch instructions retired. +.It Li FP_ASSIST.X87_OUTPUT +.Pq Event CAH , Umask 02H +Number of X87 assists due to output value. +.It Li FP_ASSIST.X87_INPUT +.Pq Event CAH , Umask 04H +Number of X87 assists due to input value. +.It Li FP_ASSIST.SIMD_OUTPUT +.Pq Event CAH , Umask 08H + Number of SIMD FP assists due to output values. +.It Li FP_ASSIST.SIMD_INPUT +.Pq Event CAH , Umask 10H +Number of SIMD FP assists due to input values. +.It Li FP_ASSIST.ANY 1EH +.Pq Event CAH , Umask +Cycles with any input/output SSE* or FP assists. +.It Li ROB_MISC_EVENTS.LBR_INSERTS +.Pq Event CCH , Umask 20H +Count cases of saving new LBR records by +hardware. +.It Li MEM_TRANS_RETIRED.LOAD_LATENCY +.Pq Event CDH , Umask 01H +Sample loads with specified latency threshold. +PMC3 only. +.It Li MEM_TRANS_RETIRED.PRECISE_STORE +.Pq Event CDH , Umask 02H +Sample stores and collect precise store operation +via PEBS record. PMC3 only. +.It Li MEM_UOP_RETIRED.LOADS +.Pq Event D0H , Umask 10H +Qualify retired memory uops that are loads. +Combine with umask 10H, 20H, 40H, 80H. +.It Li MEM_UOP_RETIRED.STORES +.Pq Event D0H , Umask 02H +Qualify retired memory uops that are stores. +Combine with umask 10H, 20H, 40H, 80H. +.It Li MEM_UOP_RETIRED.STLB_MISS +.Pq Event D0H , Umask +Qualify retired memory uops with STLB miss. Must +combine with umask 01H, 02H, to produce counts. +.It Li MEM_UOP_RETIRED.LOCK +.Pq Event D0H , Umask +Qualify retired memory uops with lock. Must +combine with umask 01H, 02H, to produce counts. +.It Li MEM_UOP_RETIRED.SPLIT +.Pq Event D0H , Umask +Qualify retired memory uops with line split. Must +combine with umask 01H, 02H, to produce counts. +.It Li MEM_UOP_RETIRED_ALL +.Pq Event D0H , Umask +Qualify any retired memory uops. Must combine +with umask 01H, 02H, to produce counts. +.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT +.Pq Event D1H , Umask 01H +Retired load uops with L1 cache hits as data +sources. +.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT +.Pq Event D1H , Umask 02H +Retired load uops with L2 cache hits as data +sources. +.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT +.Pq Event D1H , Umask 04H +Retired load uops which data sources were data hits +in LLC without snoops required. +.It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS +.Pq Event D1H , Umask 20H +Retired load uops which data sources were data +missed LLC (excluding unknown data source). +.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB +.Pq Event D1H , Umask 40H +Retired load uops which data sources were load +uops missed L1 but hit FB due to preceding miss to +the same cache line with data not ready. +.It Li MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS +.Pq Event D4H , Umask 02H +Retired load uops with unknown information as data +source in cache serviced the load. +.It Li BACLEARS.ANY +.Pq Event E6H , Umask 01H +Counts the number of times the front end is re- +steered, mainly when the BPU cannot provide a +correct prediction and this is corrected by other +branch handling mechanisms at the front end. +.It Li L2_TRANS.DEMAND_DATA_RD +.Pq Event F0H , Umask 01H +Demand Data Read requests that access L2 cache. +.It Li L2_TRANS.RFO +.Pq Event F0H , Umask 02H +RFO requests that access L2 cache. +.It Li L2_TRANS.CODE_RD +.Pq Event F0H , Umask 04H +L2 cache accesses when fetching instructions. +.It Li L2_TRANS.ALL_PF +.Pq Event F0H , Umask 08H +L2 or LLC HW prefetches that access L2 cache. +.It Li L2_TRANS.L1D_WB +.Pq Event F0H , Umask 10H +L1D writebacks that access L2 cache. +.It Li L2_TRANS.L2_FILL +.Pq Event F0H , Umask 20H +L2 fill requests that access L2 cache. +.It Li L2_TRANS.L2_WB +.Pq Event F0H , Umask 40H +L2 writebacks that access L2 cache. +.It Li L2_TRANS.ALL_REQUESTS +.Pq Event F0H , Umask 80H +Transactions accessing L2 pipe. +.It Li L2_LINES_IN.I +.Pq Event F1H , Umask 01H +L2 cache lines in I state filling L2. +.It Li L2_LINES_IN.S +.Pq Event F1H , Umask 02H +L2 cache lines in S state filling L2. +.It Li L2_LINES_IN.E +.Pq Event F1H , Umask 04H +L2 cache lines in E state filling L2. +.It Li L2_LINES-IN.ALL +.Pq Event F1H , Umask 07H +L2 cache lines filling L2. +.It Li L2_LINES_OUT.DEMAND_CLEAN +.Pq Event F2H , Umask 01H +Clean L2 cache lines evicted by demand. +.It Li L2_LINES_OUT.DEMAND_DIRTY +.Pq Event F2H , Umask 02H +Dirty L2 cache lines evicted by demand. +.It Li L2_LINES_OUT.PF_CLEAN +.Pq Event F2H , Umask 04H +Clean L2 cache lines evicted by L2 prefetch. +.It Li L2_LINES_OUT.PF_DIRTY +.Pq Event F2H , Umask 08H +Dirty L2 cache lines evicted by L2 prefetch. +.It Li L2_LINES_OUT.DIRTY_ALL +.Pq Event F2H , Umask 0AH +Dirty L2 cache lines filling the L2. +.It Li SQ_MISC.SPLIT_LOCK +.Pq Event F4H , Umask 10H +Split locks in SQ. +.El +.Sh SEE ALSO +.Xr pmc 3 , +.Xr pmc.atom 3 , +.Xr pmc.core 3 , +.Xr pmc.iaf 3 , +.Xr pmc.ucf 3 , +.Xr pmc.k7 3 , +.Xr pmc.k8 3 , +.Xr pmc.p4 3 , +.Xr pmc.p5 3 , +.Xr pmc.p6 3 , +.Xr pmc.corei7 3 , +.Xr pmc.corei7uc 3 , +.Xr pmc.ivybridge 3 , +.Xr pmc.sandybridge 3 , +.Xr pmc.sandybridgeuc 3 , +.Xr pmc.westmere 3 , +.Xr pmc.westmereuc 3 , +.Xr pmc.soft 3 , +.Xr pmc.tsc 3 , +.Xr pmc_cpuinfo 3 , +.Xr pmclog 3 , +.Xr hwpmc 4 +.Sh HISTORY +The +.Nm pmc +library first appeared in +.Fx 6.0 . +.Sh AUTHORS +The +.Lb libpmc +library was written by +.An "Joseph Koshy" +.Aq jkoshy@FreeBSD.org . +The support for the Sandy Bridge Xeon +microarchitecture was written by +.An "Hiren Panchasara" +.Aq hiren.panchasara@gmail.com . Property changes on: stable/9/lib/libpmc/pmc.sandybridgexeon.3 ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: stable/9/lib/libpmc =================================================================== --- stable/9/lib/libpmc (revision 242593) +++ stable/9/lib/libpmc (revision 242594) Property changes on: stable/9/lib/libpmc ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/lib/libpmc:r241738,241741,241745 Index: stable/9/sys/dev/hwpmc/hwpmc_core.c =================================================================== --- stable/9/sys/dev/hwpmc/hwpmc_core.c (revision 242593) +++ stable/9/sys/dev/hwpmc/hwpmc_core.c (revision 242594) @@ -1,2515 +1,2609 @@ /*- * Copyright (c) 2008 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Intel Core, Core 2 and Atom PMCs. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #define CORE_CPUID_REQUEST 0xA #define CORE_CPUID_REQUEST_SIZE 0x4 #define CORE_CPUID_EAX 0x0 #define CORE_CPUID_EBX 0x1 #define CORE_CPUID_ECX 0x2 #define CORE_CPUID_EDX 0x3 #define IAF_PMC_CAPS \ (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT) #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) /* * "Architectural" events defined by Intel. The values of these * symbols correspond to positions in the bitmask returned by * the CPUID.0AH instruction. */ enum core_arch_events { CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, CORE_AE_BRANCH_MISSES_RETIRED = 6, CORE_AE_INSTRUCTION_RETIRED = 1, CORE_AE_LLC_MISSES = 4, CORE_AE_LLC_REFERENCE = 3, CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, CORE_AE_UNHALTED_CORE_CYCLES = 0 }; static enum pmc_cputype core_cputype; struct core_cpu { volatile uint32_t pc_resync; volatile uint32_t pc_iafctrl; /* Fixed function control. */ volatile uint64_t pc_globalctrl; /* Global control register. */ struct pmc_hw pc_corepmcs[]; }; static struct core_cpu **core_pcpu; static uint32_t core_architectural_events; static uint64_t core_pmcmask; static int core_iaf_ri; /* relative index of fixed counters */ static int core_iaf_width; static int core_iaf_npmc; static int core_iap_width; static int core_iap_npmc; static int core_pcpu_noop(struct pmc_mdep *md, int cpu) { (void) md; (void) cpu; return (0); } static int core_pcpu_init(struct pmc_mdep *md, int cpu) { struct pmc_cpu *pc; struct core_cpu *cc; struct pmc_hw *phw; int core_ri, n, npmc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; if (core_cputype != PMC_CPU_INTEL_CORE) npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), M_PMC, M_WAITOK | M_ZERO); core_pcpu[cpu] = cc; pc = pmc_pcpu[cpu]; KASSERT(pc != NULL && cc != NULL, ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n + core_ri); phw->phw_pmc = NULL; pc->pc_hwpmcs[n + core_ri] = phw; } return (0); } static int core_pcpu_fini(struct pmc_mdep *md, int cpu) { int core_ri, n, npmc; struct pmc_cpu *pc; struct core_cpu *cc; uint64_t msr = 0; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); if ((cc = core_pcpu[cpu]) == NULL) return (0); core_pcpu[cpu] = NULL; pc = pmc_pcpu[cpu]; KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, cpu)); npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; for (n = 0; n < npmc; n++) { msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + n, msr); } if (core_cputype != PMC_CPU_INTEL_CORE) { msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr); npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; } for (n = 0; n < npmc; n++) pc->pc_hwpmcs[n + core_ri] = NULL; free(cc, M_PMC); return (0); } /* * Fixed function counters. */ static pmc_value_t iaf_perfctr_value_to_reload_count(pmc_value_t v) { v &= (1ULL << core_iaf_width) - 1; return (1ULL << core_iaf_width) - v; } static pmc_value_t iaf_reload_count_to_perfctr_value(pmc_value_t rlc) { return (1ULL << core_iaf_width) - rlc; } static int iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { enum pmc_event ev; uint32_t caps, flags, validflags; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); if (ri < 0 || ri > core_iaf_npmc) return (EINVAL); caps = a->pm_caps; if (a->pm_class != PMC_CLASS_IAF || (caps & IAF_PMC_CAPS) != caps) return (EINVAL); ev = pm->pm_event; if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) return (EINVAL); if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) return (EINVAL); if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) return (EINVAL); if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) return (EINVAL); flags = a->pm_md.pm_iaf.pm_iaf_flags; validflags = IAF_MASK; if (core_cputype != PMC_CPU_INTEL_ATOM) validflags &= ~IAF_ANY; if ((flags & ~validflags) != 0) return (EINVAL); if (caps & PMC_CAP_INTERRUPT) flags |= IAF_PMI; if (caps & PMC_CAP_SYSTEM) flags |= IAF_OS; if (caps & PMC_CAP_USER) flags |= IAF_USR; if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) flags |= (IAF_OS | IAF_USR); pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); return (0); } static int iaf_config_pmc(int cpu, int ri, struct pmc *pm) { KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, cpu)); core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; return (0); } static int iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; struct pmc_hw *phw; char iaf_name[PMC_NAME_MAX]; phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, NULL)) != 0) return (error); pi->pm_class = PMC_CLASS_IAF; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return (0); } static int iaf_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; return (0); } static int iaf_get_msr(int ri, uint32_t *msr) { KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[iaf,%d] ri %d out of range", __LINE__, ri)); *msr = IAF_RI_TO_MSR(ri); return (0); } static int iaf_read_pmc(int cpu, int ri, pmc_value_t *v) { struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, ri, ri + core_iaf_ri)); tmp = rdpmc(IAF_RI_TO_MSR(ri)); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = iaf_perfctr_value_to_reload_count(tmp); else *v = tmp; PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, IAF_RI_TO_MSR(ri), *v); return (0); } static int iaf_release_pmc(int cpu, int ri, struct pmc *pmc) { PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); return (0); } static int iaf_start_pmc(int cpu, int ri) { struct pmc *pm; struct core_cpu *iafc; uint64_t msr = 0; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); iafc = core_pcpu[cpu]; pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); do { iafc->pc_resync = 0; iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & IAF_GLOBAL_CTRL_MASK)); } while (iafc->pc_resync != 0); PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); return (0); } static int iaf_stop_pmc(int cpu, int ri) { uint32_t fc; struct core_cpu *iafc; uint64_t msr = 0; PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); iafc = core_pcpu[cpu]; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); fc = (IAF_MASK << (ri * 4)); if (core_cputype != PMC_CPU_INTEL_ATOM) fc &= ~IAF_ANY; iafc->pc_iafctrl &= ~fc; PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); do { iafc->pc_resync = 0; iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & IAF_GLOBAL_CTRL_MASK)); } while (iafc->pc_resync != 0); PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); return (0); } static int iaf_write_pmc(int cpu, int ri, pmc_value_t v) { struct core_cpu *cc; struct pmc *pm; uint64_t msr; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = iaf_reload_count_to_perfctr_value(v); /* Turn off fixed counters */ msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr); wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); /* Turn on fixed counters */ msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, (uintmax_t) rdmsr(IAF_CTRL), (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); return (0); } static void iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; pcd->pcd_caps = IAF_PMC_CAPS; pcd->pcd_class = PMC_CLASS_IAF; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = iaf_allocate_pmc; pcd->pcd_config_pmc = iaf_config_pmc; pcd->pcd_describe = iaf_describe; pcd->pcd_get_config = iaf_get_config; pcd->pcd_get_msr = iaf_get_msr; pcd->pcd_pcpu_fini = core_pcpu_noop; pcd->pcd_pcpu_init = core_pcpu_noop; pcd->pcd_read_pmc = iaf_read_pmc; pcd->pcd_release_pmc = iaf_release_pmc; pcd->pcd_start_pmc = iaf_start_pmc; pcd->pcd_stop_pmc = iaf_stop_pmc; pcd->pcd_write_pmc = iaf_write_pmc; md->pmd_npmc += npmc; } /* * Intel programmable PMCs. */ /* * Event descriptor tables. * * For each event id, we track: * * 1. The CPUs that the event is valid for. * * 2. If the event uses a fixed UMASK, the value of the umask field. * If the event doesn't use a fixed UMASK, a mask of legal bits * to check against. */ struct iap_event_descr { enum pmc_event iap_ev; unsigned char iap_evcode; unsigned char iap_umask; unsigned int iap_flags; }; #define IAP_F_CC (1 << 0) /* CPU: Core */ #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ #define IAP_F_CA (1 << 3) /* CPU: Atom */ #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ #define IAP_F_WM (1 << 5) /* CPU: Westmere */ #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ -#define IAP_F_FM (1 << 8) /* Fixed mask */ +#define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ +#define IAP_F_FM (1 << 9) /* Fixed mask */ #define IAP_F_ALLCPUSCORE2 \ (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) /* Sub fields of UMASK that this event supports. */ #define IAP_M_CORE (1 << 0) /* Core specificity */ #define IAP_M_AGENT (1 << 1) /* Agent specificity */ #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ #define IAP_M_MESI (1 << 3) /* MESI */ #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ #define IAP_M_TRANSITION (1 << 6) /* Transition */ #define IAP_F_CORE (0x3 << 14) /* Core specificity */ #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ #define IAP_F_MESI (0xF << 8) /* MESI */ #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ #define IAP_PREFETCH_RESERVED (0x2 << 12) #define IAP_CORE_THIS (0x1 << 14) #define IAP_CORE_ALL (0x3 << 14) #define IAP_F_CMASK 0xFF000000 static struct iap_event_descr iap_events[] = { #undef IAPDESCR #define IAPDESCR(N,EV,UM,FLAGS) { \ .iap_ev = PMC_EV_IAP_EVENT_##N, \ .iap_evcode = (EV), \ .iap_umask = (UM), \ .iap_flags = (FLAGS) \ } IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), - IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB), + IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | + IAP_F_SBX), IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), - IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB), - IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB), + IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | + IAP_F_SBX), IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), - IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB), - IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA), IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), - IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB), + IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | + IAP_F_SBX), IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_WM | IAP_F_SB), + IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), - IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O), IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB), IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB), IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB), IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), - IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB), - IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB), + IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), - IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB), IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB), IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB), IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | - IAP_F_WM | IAP_F_SB), + IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), - IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), - IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), - IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), - IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB), - IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB), + IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | - IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB), + IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | + IAP_F_SBX), IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), - IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), - IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB), - IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | + IAP_F_SBX), + IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), - IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB), - IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB), + IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX), + IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), + IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX), IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CA | IAP_F_CC2), IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7), IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), - IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7), IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), - IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB), IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB), IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB), IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB), - IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB), - IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB), - IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB), + IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), - IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB), - IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB), - IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB), - IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB), + IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), - IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), - IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB), IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB), IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, IAP_F_CA | IAP_F_CC2), IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), - IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB), IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB), IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB), IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | - IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB), - IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), - IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), - IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), - IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), + IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX), + IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX), + IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX), + IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), - IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB), - IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB), + IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IB), IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB), IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_WM | IAP_F_I7O), IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_WM | IAP_F_I7O), IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_WM | IAP_F_I7O), IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), - IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB), + IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), - IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), - IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB), + IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB), IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), - IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB), - IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), - IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), - IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | + IAP_F_IB | IAP_F_SBX), IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), - IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB), - IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | + IAP_F_IB | IAP_F_SBX), + IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB), - IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), - IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), - IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB), - IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), + IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), - IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB), + IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | + IAP_F_IB | IAP_F_SBX), IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX), + IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB), IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), - IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB), + IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX), + IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX), IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | - IAP_F_WM), + IAP_F_WM | IAP_F_SBX), IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), - IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB), + IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX), IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB), - IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB), + IAP_F_SB | IAP_F_IB | IAP_F_SBX), + IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB), + IAP_F_SB | IAP_F_SBX), IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), }; static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); static pmc_value_t iap_perfctr_value_to_reload_count(pmc_value_t v) { v &= (1ULL << core_iap_width) - 1; return (1ULL << core_iap_width) - v; } static pmc_value_t iap_reload_count_to_perfctr_value(pmc_value_t rlc) { return (1ULL << core_iap_width) - rlc; } static int iap_pmc_has_overflowed(int ri) { uint64_t v; /* * We treat a Core (i.e., Intel architecture v1) PMC as has * having overflowed if its MSB is zero. */ v = rdpmc(ri); return ((v & (1ULL << (core_iap_width - 1))) == 0); } /* * Check an event against the set of supported architectural events. * * Returns 1 if the event is architectural and unsupported on this * CPU. Returns 0 otherwise. */ static int iap_architectural_event_is_unsupported(enum pmc_event pe) { enum core_arch_events ae; switch (pe) { case PMC_EV_IAP_EVENT_3CH_00H: ae = CORE_AE_UNHALTED_CORE_CYCLES; break; case PMC_EV_IAP_EVENT_C0H_00H: ae = CORE_AE_INSTRUCTION_RETIRED; break; case PMC_EV_IAP_EVENT_3CH_01H: ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; break; case PMC_EV_IAP_EVENT_2EH_4FH: ae = CORE_AE_LLC_REFERENCE; break; case PMC_EV_IAP_EVENT_2EH_41H: ae = CORE_AE_LLC_MISSES; break; case PMC_EV_IAP_EVENT_C4H_00H: ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; break; case PMC_EV_IAP_EVENT_C5H_00H: ae = CORE_AE_BRANCH_MISSES_RETIRED; break; default: /* Non architectural event. */ return (0); } return ((core_architectural_events & (1 << ae)) == 0); } static int iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; switch (pe) { /* * Events valid only on counter 0, 1. */ case PMC_EV_IAP_EVENT_40H_01H: case PMC_EV_IAP_EVENT_40H_02H: case PMC_EV_IAP_EVENT_40H_04H: case PMC_EV_IAP_EVENT_40H_08H: case PMC_EV_IAP_EVENT_40H_0FH: case PMC_EV_IAP_EVENT_41H_02H: case PMC_EV_IAP_EVENT_41H_04H: case PMC_EV_IAP_EVENT_41H_08H: case PMC_EV_IAP_EVENT_42H_01H: case PMC_EV_IAP_EVENT_42H_02H: case PMC_EV_IAP_EVENT_42H_04H: case PMC_EV_IAP_EVENT_42H_08H: case PMC_EV_IAP_EVENT_43H_01H: case PMC_EV_IAP_EVENT_43H_02H: case PMC_EV_IAP_EVENT_51H_01H: case PMC_EV_IAP_EVENT_51H_02H: case PMC_EV_IAP_EVENT_51H_04H: case PMC_EV_IAP_EVENT_51H_08H: case PMC_EV_IAP_EVENT_63H_01H: case PMC_EV_IAP_EVENT_63H_02H: mask = 0x3; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; switch (pe) { /* * Events valid only on counter 0. */ case PMC_EV_IAP_EVENT_60H_01H: case PMC_EV_IAP_EVENT_60H_02H: case PMC_EV_IAP_EVENT_60H_04H: case PMC_EV_IAP_EVENT_60H_08H: case PMC_EV_IAP_EVENT_B3H_01H: case PMC_EV_IAP_EVENT_B3H_02H: case PMC_EV_IAP_EVENT_B3H_04H: mask = 0x1; break; /* * Events valid only on counter 0, 1. */ case PMC_EV_IAP_EVENT_4CH_01H: case PMC_EV_IAP_EVENT_4EH_01H: case PMC_EV_IAP_EVENT_4EH_02H: case PMC_EV_IAP_EVENT_4EH_04H: case PMC_EV_IAP_EVENT_51H_01H: case PMC_EV_IAP_EVENT_51H_02H: case PMC_EV_IAP_EVENT_51H_04H: case PMC_EV_IAP_EVENT_51H_08H: case PMC_EV_IAP_EVENT_63H_01H: case PMC_EV_IAP_EVENT_63H_02H: mask = 0x3; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int -iap_event_sb_ib_ok_on_counter(enum pmc_event pe, int ri) +iap_event_sb_sbx_ib_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; switch (pe) { /* Events valid only on counter 0. */ case PMC_EV_IAP_EVENT_B7H_01H: mask = 0x1; break; /* Events valid only on counter 1. */ case PMC_EV_IAP_EVENT_C0H_01H: mask = 0x1; break; /* Events valid only on counter 2. */ case PMC_EV_IAP_EVENT_48H_01H: + case PMC_EV_IAP_EVENT_A2H_02H: mask = 0x4; break; /* Events valid only on counter 3. */ case PMC_EV_IAP_EVENT_BBH_01H: case PMC_EV_IAP_EVENT_CDH_01H: case PMC_EV_IAP_EVENT_CDH_02H: mask = 0x8; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_event_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; switch (pe) { /* * Events valid only on counter 0. */ case PMC_EV_IAP_EVENT_10H_00H: case PMC_EV_IAP_EVENT_14H_00H: case PMC_EV_IAP_EVENT_18H_00H: case PMC_EV_IAP_EVENT_B3H_01H: case PMC_EV_IAP_EVENT_B3H_02H: case PMC_EV_IAP_EVENT_B3H_04H: case PMC_EV_IAP_EVENT_C1H_00H: case PMC_EV_IAP_EVENT_CBH_01H: case PMC_EV_IAP_EVENT_CBH_02H: mask = (1 << 0); break; /* * Events valid only on counter 1. */ case PMC_EV_IAP_EVENT_11H_00H: case PMC_EV_IAP_EVENT_12H_00H: case PMC_EV_IAP_EVENT_13H_00H: mask = (1 << 1); break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { int n, model; enum pmc_event ev; struct iap_event_descr *ie; uint32_t c, caps, config, cpuflag, evsel, mask; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index value %d", __LINE__, ri)); /* check requested capabilities */ caps = a->pm_caps; if ((IAP_PMC_CAPS & caps) != caps) return (EPERM); ev = pm->pm_event; if (iap_architectural_event_is_unsupported(ev)) return (EOPNOTSUPP); /* * A small number of events are not supported in all the * processors based on a given microarchitecture. */ if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) return (EINVAL); } switch (core_cputype) { case PMC_CPU_INTEL_COREI7: if (iap_event_corei7_ok_on_counter(ev, ri) == 0) return (EINVAL); break; case PMC_CPU_INTEL_SANDYBRIDGE: + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE: - if (iap_event_sb_ib_ok_on_counter(ev, ri) == 0) + if (iap_event_sb_sbx_ib_ok_on_counter(ev, ri) == 0) return (EINVAL); break; case PMC_CPU_INTEL_WESTMERE: if (iap_event_westmere_ok_on_counter(ev, ri) == 0) return (EINVAL); break; default: if (iap_event_ok_on_counter(ev, ri) == 0) return (EINVAL); } /* * Look for an event descriptor with matching CPU and event id * fields. */ switch (core_cputype) { default: case PMC_CPU_INTEL_ATOM: cpuflag = IAP_F_CA; break; case PMC_CPU_INTEL_CORE: cpuflag = IAP_F_CC; break; case PMC_CPU_INTEL_CORE2: cpuflag = IAP_F_CC2; break; case PMC_CPU_INTEL_CORE2EXTREME: cpuflag = IAP_F_CC2 | IAP_F_CC2E; break; case PMC_CPU_INTEL_COREI7: cpuflag = IAP_F_I7; break; case PMC_CPU_INTEL_IVYBRIDGE: cpuflag = IAP_F_IB; break; case PMC_CPU_INTEL_SANDYBRIDGE: cpuflag = IAP_F_SB; break; + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: + cpuflag = IAP_F_SBX; + break; case PMC_CPU_INTEL_WESTMERE: cpuflag = IAP_F_WM; break; } for (n = 0, ie = iap_events; n < niap_events; n++, ie++) if (ie->iap_ev == ev && ie->iap_flags & cpuflag) break; if (n == niap_events) return (EINVAL); /* * A matching event descriptor has been found, so start * assembling the contents of the event select register. */ evsel = ie->iap_evcode; config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; /* * If the event uses a fixed umask value, reject any umask * bits set by the user. */ if (ie->iap_flags & IAP_F_FM) { if (IAP_UMASK(config) != 0) return (EINVAL); evsel |= (ie->iap_umask << 8); } else { /* * Otherwise, the UMASK value needs to be taken from * the MD fields of the allocation request. Reject * requests that specify reserved bits. */ mask = 0; if (ie->iap_umask & IAP_M_CORE) { if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && c != IAP_CORE_THIS) return (EINVAL); mask |= IAP_F_CORE; } if (ie->iap_umask & IAP_M_AGENT) mask |= IAP_F_AGENT; if (ie->iap_umask & IAP_M_PREFETCH) { if ((c = (config & IAP_F_PREFETCH)) == IAP_PREFETCH_RESERVED) return (EINVAL); mask |= IAP_F_PREFETCH; } if (ie->iap_umask & IAP_M_MESI) mask |= IAP_F_MESI; if (ie->iap_umask & IAP_M_SNOOPRESPONSE) mask |= IAP_F_SNOOPRESPONSE; if (ie->iap_umask & IAP_M_SNOOPTYPE) mask |= IAP_F_SNOOPTYPE; if (ie->iap_umask & IAP_M_TRANSITION) mask |= IAP_F_TRANSITION; /* * If bits outside of the allowed set of umask bits * are set, reject the request. */ if (config & ~mask) return (EINVAL); evsel |= (config & mask); } /* * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. */ if (core_cputype == PMC_CPU_INTEL_ATOM || - core_cputype == PMC_CPU_INTEL_SANDYBRIDGE) + core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || + core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) evsel |= (config & IAP_ANY); else if (config & IAP_ANY) return (EINVAL); /* * Check offcore response configuration. */ if (a->pm_md.pm_iap.pm_iap_rsp != 0) { if (ev != PMC_EV_IAP_EVENT_B7H_01H && ev != PMC_EV_IAP_EVENT_BBH_01H) return (EINVAL); if (core_cputype == PMC_CPU_INTEL_COREI7 && ev == PMC_EV_IAP_EVENT_BBH_01H) return (EINVAL); if ((core_cputype == PMC_CPU_INTEL_COREI7 || core_cputype == PMC_CPU_INTEL_WESTMERE) && a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) return (EINVAL); else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || - core_cputype == PMC_CPU_INTEL_IVYBRIDGE) && + core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || + core_cputype == PMC_CPU_INTEL_IVYBRIDGE) && a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) return (EINVAL); pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; } if (caps & PMC_CAP_THRESHOLD) evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); if (caps & PMC_CAP_USER) evsel |= IAP_USR; if (caps & PMC_CAP_SYSTEM) evsel |= IAP_OS; if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) evsel |= (IAP_OS | IAP_USR); if (caps & PMC_CAP_EDGE) evsel |= IAP_EDGE; if (caps & PMC_CAP_INVERT) evsel |= IAP_INV; if (caps & PMC_CAP_INTERRUPT) evsel |= IAP_INT; pm->pm_md.pm_iap.pm_iap_evsel = evsel; return (0); } static int iap_config_pmc(int cpu, int ri, struct pmc *pm) { KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, cpu)); core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; return (0); } static int iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; struct pmc_hw *phw; char iap_name[PMC_NAME_MAX]; phw = &core_pcpu[cpu]->pc_corepmcs[ri]; (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, NULL)) != 0) return (error); pi->pm_class = PMC_CLASS_IAP; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return (0); } static int iap_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; return (0); } static int iap_get_msr(int ri, uint32_t *msr) { KASSERT(ri >= 0 && ri < core_iap_npmc, ("[iap,%d] ri %d out of range", __LINE__, ri)); *msr = ri; return (0); } static int iap_read_pmc(int cpu, int ri, pmc_value_t *v) { struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); tmp = rdpmc(ri); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = iap_perfctr_value_to_reload_count(tmp); else *v = tmp & ((1ULL << core_iap_width) - 1); PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, ri, *v); return (0); } static int iap_release_pmc(int cpu, int ri, struct pmc *pm) { (void) pm; PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); return (0); } static int iap_start_pmc(int cpu, int ri) { struct pmc *pm; uint32_t evsel; struct core_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] starting cpu%d,ri%d with no pmc configured", __LINE__, cpu, ri)); PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); evsel = pm->pm_md.pm_iap.pm_iap_evsel; PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", cpu, ri, IAP_EVSEL0 + ri, evsel); /* Event specific configuration. */ switch (pm->pm_event) { case PMC_EV_IAP_EVENT_B7H_01H: wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); break; case PMC_EV_IAP_EVENT_BBH_01H: wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); break; default: break; } wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); if (core_cputype == PMC_CPU_INTEL_CORE) return (0); do { cc->pc_resync = 0; cc->pc_globalctrl |= (1ULL << ri); wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); } while (cc->pc_resync != 0); return (0); } static int iap_stop_pmc(int cpu, int ri) { struct pmc *pm; struct core_cpu *cc; uint64_t msr; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, cpu, ri)); PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ if (core_cputype == PMC_CPU_INTEL_CORE) return (0); msr = 0; do { cc->pc_resync = 0; cc->pc_globalctrl &= ~(1ULL << ri); msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); } while (cc->pc_resync != 0); return (0); } static int iap_write_pmc(int cpu, int ri, pmc_value_t v) { struct pmc *pm; struct core_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, cpu, ri)); PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, IAP_PMC0 + ri, v); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = iap_reload_count_to_perfctr_value(v); /* * Write the new value to the counter. The counter will be in * a stopped state when the pcd_write() entry point is called. */ wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); return (0); } static void iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, int flags) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); PMCDBG(MDP,INI,1, "%s", "iap-initialize"); /* Remember the set of architectural events supported. */ core_architectural_events = ~flags; pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; pcd->pcd_caps = IAP_PMC_CAPS; pcd->pcd_class = PMC_CLASS_IAP; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = iap_allocate_pmc; pcd->pcd_config_pmc = iap_config_pmc; pcd->pcd_describe = iap_describe; pcd->pcd_get_config = iap_get_config; pcd->pcd_get_msr = iap_get_msr; pcd->pcd_pcpu_fini = core_pcpu_fini; pcd->pcd_pcpu_init = core_pcpu_init; pcd->pcd_read_pmc = iap_read_pmc; pcd->pcd_release_pmc = iap_release_pmc; pcd->pcd_start_pmc = iap_start_pmc; pcd->pcd_stop_pmc = iap_stop_pmc; pcd->pcd_write_pmc = iap_write_pmc; md->pmd_npmc += npmc; } static int core_intr(int cpu, struct trapframe *tf) { pmc_value_t v; struct pmc *pm; struct core_cpu *cc; int error, found_interrupt, ri; uint64_t msr; PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, TRAPF_USERMODE(tf)); found_interrupt = 0; cc = core_pcpu[cpu]; for (ri = 0; ri < core_iap_npmc; ri++) { if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; if (!iap_pmc_has_overflowed(ri)) continue; found_interrupt = 1; if (pm->pm_state != PMC_STATE_RUNNING) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); v = pm->pm_sc.pm_reloadcount; v = iaf_reload_count_to_perfctr_value(v); /* * Stop the counter, reload it but only restart it if * the PMC is not stalled. */ msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + ri, msr); wrmsr(IAP_PMC0 + ri, v); if (error) continue; wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN)); } if (found_interrupt) lapic_reenable_pmc(); atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : &pmc_stats.pm_intr_ignored, 1); return (found_interrupt); } static int core2_intr(int cpu, struct trapframe *tf) { int error, found_interrupt, n; uint64_t flag, intrstatus, intrenable, msr; struct pmc *pm; struct core_cpu *cc; pmc_value_t v; PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, TRAPF_USERMODE(tf)); /* * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which * PMCs have a pending PMI interrupt. We take a 'snapshot' of * the current set of interrupting PMCs and process these * after stopping them. */ intrstatus = rdmsr(IA_GLOBAL_STATUS); intrenable = intrstatus & core_pmcmask; PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, (uintmax_t) intrstatus); found_interrupt = 0; cc = core_pcpu[cpu]; KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); cc->pc_globalctrl &= ~intrenable; cc->pc_resync = 1; /* MSRs now potentially out of sync. */ /* * Stop PMCs and clear overflow status bits. */ msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr); wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | IA_GLOBAL_STATUS_FLAG_OVFBUF | IA_GLOBAL_STATUS_FLAG_CONDCHG); /* * Look for interrupts from fixed function PMCs. */ for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; n++, flag <<= 1) { if ((intrstatus & flag) == 0) continue; found_interrupt = 1; pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); if (error) intrenable &= ~flag; v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); /* Reload sampling count. */ wrmsr(IAF_CTR0 + n, v); PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); } /* * Process interrupts from the programmable counters. */ for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { if ((intrstatus & flag) == 0) continue; found_interrupt = 1; pm = cc->pc_corepmcs[n].phw_pmc; if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); if (error) intrenable &= ~flag; v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, (uintmax_t) v); /* Reload sampling count. */ wrmsr(IAP_PMC0 + n, v); } /* * Reenable all non-stalled PMCs. */ PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, (uintmax_t) intrenable); cc->pc_globalctrl |= intrenable; wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), (uintmax_t) rdmsr(IA_GLOBAL_CTRL), (uintmax_t) rdmsr(IA_GLOBAL_STATUS), (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); if (found_interrupt) lapic_reenable_pmc(); atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : &pmc_stats.pm_intr_ignored, 1); return (found_interrupt); } int pmc_core_initialize(struct pmc_mdep *md, int maxcpu) { int cpuid[CORE_CPUID_REQUEST_SIZE]; int ipa_version, flags, nflags; do_cpuid(CORE_CPUID_REQUEST, cpuid); ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", md->pmd_cputype, maxcpu, ipa_version); if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */ return (EPROGMISMATCH); core_cputype = md->pmd_cputype; core_pmcmask = 0; /* * Initialize programmable counters. */ KASSERT(ipa_version >= 1, ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; core_pmcmask |= ((1ULL << core_iap_npmc) - 1); nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); /* * Initialize fixed function counters, if present. */ if (core_cputype != PMC_CPU_INTEL_CORE) { KASSERT(ipa_version >= 2, ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); core_iaf_ri = core_iap_npmc; core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; } PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, core_iaf_ri); core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, M_ZERO | M_WAITOK); /* * Choose the appropriate interrupt handler. */ if (ipa_version == 1) md->pmd_intr = core_intr; else md->pmd_intr = core2_intr; md->pmd_pcpu_fini = NULL; md->pmd_pcpu_init = NULL; return (0); } void pmc_core_finalize(struct pmc_mdep *md) { PMCDBG(MDP,INI,1, "%s", "core-finalize"); free(core_pcpu, M_PMC); core_pcpu = NULL; } Index: stable/9/sys/dev/hwpmc/hwpmc_intel.c =================================================================== --- stable/9/sys/dev/hwpmc/hwpmc_intel.c (revision 242593) +++ stable/9/sys/dev/hwpmc/hwpmc_intel.c (revision 242594) @@ -1,311 +1,317 @@ /*- * Copyright (c) 2008 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Common code for handling Intel CPUs. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include static int intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) { (void) pc; PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); /* allow the RDPMC instruction if needed */ if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) load_cr4(rcr4() | CR4_PCE); PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); return 0; } static int intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) { (void) pc; (void) pp; /* can be NULL */ PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, (uintmax_t) rcr4()); /* always turn off the RDPMC instruction */ load_cr4(rcr4() & ~CR4_PCE); return 0; } struct pmc_mdep * pmc_intel_initialize(void) { struct pmc_mdep *pmc_mdep; enum pmc_cputype cputype; int error, model, nclasses, ncpus; KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, ("[intel,%d] Initializing non-intel processor", __LINE__)); PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); cputype = -1; nclasses = 2; model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); switch (cpu_id & 0xF00) { #if defined(__i386__) case 0x500: /* Pentium family processors */ cputype = PMC_CPU_INTEL_P5; break; #endif case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ switch (model) { #if defined(__i386__) case 0x1: cputype = PMC_CPU_INTEL_P6; break; case 0x3: case 0x5: cputype = PMC_CPU_INTEL_PII; break; case 0x6: case 0x16: cputype = PMC_CPU_INTEL_CL; break; case 0x7: case 0x8: case 0xA: case 0xB: cputype = PMC_CPU_INTEL_PIII; break; case 0x9: case 0xD: cputype = PMC_CPU_INTEL_PM; break; #endif case 0xE: cputype = PMC_CPU_INTEL_CORE; break; case 0xF: cputype = PMC_CPU_INTEL_CORE2; nclasses = 3; break; case 0x17: cputype = PMC_CPU_INTEL_CORE2EXTREME; nclasses = 3; break; case 0x1C: /* Per Intel document 320047-002. */ cputype = PMC_CPU_INTEL_ATOM; nclasses = 3; break; case 0x1A: case 0x1E: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */ case 0x1F: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */ case 0x2E: cputype = PMC_CPU_INTEL_COREI7; nclasses = 5; break; case 0x25: /* Per Intel document 253669-033US 12/2009. */ case 0x2C: /* Per Intel document 253669-033US 12/2009. */ cputype = PMC_CPU_INTEL_WESTMERE; nclasses = 5; break; case 0x2A: /* Per Intel document 253669-039US 05/2011. */ cputype = PMC_CPU_INTEL_SANDYBRIDGE; nclasses = 5; break; + case 0x2D: /* Per Intel document 253669-044US 08/2012. */ + cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; + nclasses = 3; + break; case 0x3A: /* Per Intel document 253669-043US 05/2012. */ cputype = PMC_CPU_INTEL_IVYBRIDGE; nclasses = 3; break; } break; #if defined(__i386__) || defined(__amd64__) case 0xF00: /* P4 */ if (model >= 0 && model <= 6) /* known models */ cputype = PMC_CPU_INTEL_PIV; break; } #endif if ((int) cputype == -1) { printf("pmc: Unknown Intel CPU.\n"); return (NULL); } /* Allocate base class and initialize machine dependent struct */ pmc_mdep = pmc_mdep_alloc(nclasses); pmc_mdep->pmd_cputype = cputype; pmc_mdep->pmd_switch_in = intel_switch_in; pmc_mdep->pmd_switch_out = intel_switch_out; ncpus = pmc_cpu_max(); error = pmc_tsc_initialize(pmc_mdep, ncpus); if (error) goto error; switch (cputype) { #if defined(__i386__) || defined(__amd64__) /* * Intel Core, Core 2 and Atom processors. */ case PMC_CPU_INTEL_ATOM: case PMC_CPU_INTEL_CORE: case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: error = pmc_core_initialize(pmc_mdep, ncpus); break; /* * Intel Pentium 4 Processors, and P4/EMT64 processors. */ case PMC_CPU_INTEL_PIV: error = pmc_p4_initialize(pmc_mdep, ncpus); break; #endif #if defined(__i386__) /* * P6 Family Processors */ case PMC_CPU_INTEL_P6: case PMC_CPU_INTEL_CL: case PMC_CPU_INTEL_PII: case PMC_CPU_INTEL_PIII: case PMC_CPU_INTEL_PM: error = pmc_p6_initialize(pmc_mdep, ncpus); break; /* * Intel Pentium PMCs. */ case PMC_CPU_INTEL_P5: error = pmc_p5_initialize(pmc_mdep, ncpus); break; #endif default: KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); } /* * Init the uncore class. */ #if defined(__i386__) || defined(__amd64__) switch (cputype) { /* * Intel Corei7 and Westmere processors. */ case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: error = pmc_uncore_initialize(pmc_mdep, ncpus); break; default: break; } #endif error: if (error) { free(pmc_mdep, M_PMC); pmc_mdep = NULL; } return (pmc_mdep); } void pmc_intel_finalize(struct pmc_mdep *md) { pmc_tsc_finalize(md); switch (md->pmd_cputype) { #if defined(__i386__) || defined(__amd64__) case PMC_CPU_INTEL_ATOM: case PMC_CPU_INTEL_CORE: case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_SANDYBRIDGE_XEON: pmc_core_finalize(md); break; case PMC_CPU_INTEL_PIV: pmc_p4_finalize(md); break; #endif #if defined(__i386__) case PMC_CPU_INTEL_P6: case PMC_CPU_INTEL_CL: case PMC_CPU_INTEL_PII: case PMC_CPU_INTEL_PIII: case PMC_CPU_INTEL_PM: pmc_p6_finalize(md); break; case PMC_CPU_INTEL_P5: pmc_p5_finalize(md); break; #endif default: KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); } /* * Uncore. */ #if defined(__i386__) || defined(__amd64__) switch (md->pmd_cputype) { case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: pmc_uncore_finalize(md); break; default: break; } #endif } Index: stable/9/sys/dev/hwpmc/pmc_events.h =================================================================== --- stable/9/sys/dev/hwpmc/pmc_events.h (revision 242593) +++ stable/9/sys/dev/hwpmc/pmc_events.h (revision 242594) @@ -1,3900 +1,4121 @@ /*- * Copyright (c) 2005 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_HWPMC_PMC_EVENTS_H_ #define _DEV_HWPMC_PMC_EVENTS_H_ /* * Note: Documentation on adding events can be found both in * the source tree at src/share/doc/papers/hwpmc/hwpmc.ms * as well as on-line at: * * http://wiki.freebsd.org/PmcTools/PmcHardwareHowTo * * Please refer to those resources before you attempt to modify * this file or the hwpmc driver/subsystem. */ /* * PMC event codes. * * __PMC_EV(CLASS, SYMBOLIC-NAME) * */ /* * AMD K7 Events, from "The AMD Athlon(tm) Processor x86 Code * Optimization Guide" [Doc#22007K, Feb 2002] */ #define __PMC_EV_K7() \ __PMC_EV(K7, DC_ACCESSES) \ __PMC_EV(K7, DC_MISSES) \ __PMC_EV(K7, DC_REFILLS_FROM_L2) \ __PMC_EV(K7, DC_REFILLS_FROM_SYSTEM) \ __PMC_EV(K7, DC_WRITEBACKS) \ __PMC_EV(K7, L1_DTLB_MISS_AND_L2_DTLB_HITS) \ __PMC_EV(K7, L1_AND_L2_DTLB_MISSES) \ __PMC_EV(K7, MISALIGNED_REFERENCES) \ __PMC_EV(K7, IC_FETCHES) \ __PMC_EV(K7, IC_MISSES) \ __PMC_EV(K7, L1_ITLB_MISSES) \ __PMC_EV(K7, L1_L2_ITLB_MISSES) \ __PMC_EV(K7, RETIRED_INSTRUCTIONS) \ __PMC_EV(K7, RETIRED_OPS) \ __PMC_EV(K7, RETIRED_BRANCHES) \ __PMC_EV(K7, RETIRED_BRANCHES_MISPREDICTED) \ __PMC_EV(K7, RETIRED_TAKEN_BRANCHES) \ __PMC_EV(K7, RETIRED_TAKEN_BRANCHES_MISPREDICTED) \ __PMC_EV(K7, RETIRED_FAR_CONTROL_TRANSFERS) \ __PMC_EV(K7, RETIRED_RESYNC_BRANCHES) \ __PMC_EV(K7, INTERRUPTS_MASKED_CYCLES) \ __PMC_EV(K7, INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \ __PMC_EV(K7, HARDWARE_INTERRUPTS) #define PMC_EV_K7_FIRST PMC_EV_K7_DC_ACCESSES #define PMC_EV_K7_LAST PMC_EV_K7_HARDWARE_INTERRUPTS /* * Intel P4 Events, from "IA-32 Intel(r) Architecture Software * Developer's Manual, Volume 3: System Programming Guide" [245472-012] */ #define __PMC_EV_P4() \ __PMC_EV(P4, TC_DELIVER_MODE) \ __PMC_EV(P4, BPU_FETCH_REQUEST) \ __PMC_EV(P4, ITLB_REFERENCE) \ __PMC_EV(P4, MEMORY_CANCEL) \ __PMC_EV(P4, MEMORY_COMPLETE) \ __PMC_EV(P4, LOAD_PORT_REPLAY) \ __PMC_EV(P4, STORE_PORT_REPLAY) \ __PMC_EV(P4, MOB_LOAD_REPLAY) \ __PMC_EV(P4, PAGE_WALK_TYPE) \ __PMC_EV(P4, BSQ_CACHE_REFERENCE) \ __PMC_EV(P4, IOQ_ALLOCATION) \ __PMC_EV(P4, IOQ_ACTIVE_ENTRIES) \ __PMC_EV(P4, FSB_DATA_ACTIVITY) \ __PMC_EV(P4, BSQ_ALLOCATION) \ __PMC_EV(P4, BSQ_ACTIVE_ENTRIES) \ __PMC_EV(P4, SSE_INPUT_ASSIST) \ __PMC_EV(P4, PACKED_SP_UOP) \ __PMC_EV(P4, PACKED_DP_UOP) \ __PMC_EV(P4, SCALAR_SP_UOP) \ __PMC_EV(P4, SCALAR_DP_UOP) \ __PMC_EV(P4, 64BIT_MMX_UOP) \ __PMC_EV(P4, 128BIT_MMX_UOP) \ __PMC_EV(P4, X87_FP_UOP) \ __PMC_EV(P4, X87_SIMD_MOVES_UOP) \ __PMC_EV(P4, GLOBAL_POWER_EVENTS) \ __PMC_EV(P4, TC_MS_XFER) \ __PMC_EV(P4, UOP_QUEUE_WRITES) \ __PMC_EV(P4, RETIRED_MISPRED_BRANCH_TYPE) \ __PMC_EV(P4, RETIRED_BRANCH_TYPE) \ __PMC_EV(P4, RESOURCE_STALL) \ __PMC_EV(P4, WC_BUFFER) \ __PMC_EV(P4, B2B_CYCLES) \ __PMC_EV(P4, BNR) \ __PMC_EV(P4, SNOOP) \ __PMC_EV(P4, RESPONSE) \ __PMC_EV(P4, FRONT_END_EVENT) \ __PMC_EV(P4, EXECUTION_EVENT) \ __PMC_EV(P4, REPLAY_EVENT) \ __PMC_EV(P4, INSTR_RETIRED) \ __PMC_EV(P4, UOPS_RETIRED) \ __PMC_EV(P4, UOP_TYPE) \ __PMC_EV(P4, BRANCH_RETIRED) \ __PMC_EV(P4, MISPRED_BRANCH_RETIRED) \ __PMC_EV(P4, X87_ASSIST) \ __PMC_EV(P4, MACHINE_CLEAR) #define PMC_EV_P4_FIRST PMC_EV_P4_TC_DELIVER_MODE #define PMC_EV_P4_LAST PMC_EV_P4_MACHINE_CLEAR /* Intel Pentium Pro, P-II, P-III and Pentium-M style events */ #define __PMC_EV_P6() \ __PMC_EV(P6, DATA_MEM_REFS) \ __PMC_EV(P6, DCU_LINES_IN) \ __PMC_EV(P6, DCU_M_LINES_IN) \ __PMC_EV(P6, DCU_M_LINES_OUT) \ __PMC_EV(P6, DCU_MISS_OUTSTANDING) \ __PMC_EV(P6, IFU_FETCH) \ __PMC_EV(P6, IFU_FETCH_MISS) \ __PMC_EV(P6, ITLB_MISS) \ __PMC_EV(P6, IFU_MEM_STALL) \ __PMC_EV(P6, ILD_STALL) \ __PMC_EV(P6, L2_IFETCH) \ __PMC_EV(P6, L2_LD) \ __PMC_EV(P6, L2_ST) \ __PMC_EV(P6, L2_LINES_IN) \ __PMC_EV(P6, L2_LINES_OUT) \ __PMC_EV(P6, L2_M_LINES_INM) \ __PMC_EV(P6, L2_M_LINES_OUTM) \ __PMC_EV(P6, L2_RQSTS) \ __PMC_EV(P6, L2_ADS) \ __PMC_EV(P6, L2_DBUS_BUSY) \ __PMC_EV(P6, L2_DBUS_BUSY_RD) \ __PMC_EV(P6, BUS_DRDY_CLOCKS) \ __PMC_EV(P6, BUS_LOCK_CLOCKS) \ __PMC_EV(P6, BUS_REQ_OUTSTANDING) \ __PMC_EV(P6, BUS_TRAN_BRD) \ __PMC_EV(P6, BUS_TRAN_RFO) \ __PMC_EV(P6, BUS_TRANS_WB) \ __PMC_EV(P6, BUS_TRAN_IFETCH) \ __PMC_EV(P6, BUS_TRAN_INVAL) \ __PMC_EV(P6, BUS_TRAN_PWR) \ __PMC_EV(P6, BUS_TRANS_P) \ __PMC_EV(P6, BUS_TRANS_IO) \ __PMC_EV(P6, BUS_TRAN_DEF) \ __PMC_EV(P6, BUS_TRAN_BURST) \ __PMC_EV(P6, BUS_TRAN_ANY) \ __PMC_EV(P6, BUS_TRAN_MEM) \ __PMC_EV(P6, BUS_DATA_RCV) \ __PMC_EV(P6, BUS_BNR_DRV) \ __PMC_EV(P6, BUS_HIT_DRV) \ __PMC_EV(P6, BUS_HITM_DRV) \ __PMC_EV(P6, BUS_SNOOP_STALL) \ __PMC_EV(P6, FLOPS) \ __PMC_EV(P6, FP_COMPS_OPS_EXE) \ __PMC_EV(P6, FP_ASSIST) \ __PMC_EV(P6, MUL) \ __PMC_EV(P6, DIV) \ __PMC_EV(P6, CYCLES_DIV_BUSY) \ __PMC_EV(P6, LD_BLOCKS) \ __PMC_EV(P6, SB_DRAINS) \ __PMC_EV(P6, MISALIGN_MEM_REF) \ __PMC_EV(P6, EMON_KNI_PREF_DISPATCHED) \ __PMC_EV(P6, EMON_KNI_PREF_MISS) \ __PMC_EV(P6, INST_RETIRED) \ __PMC_EV(P6, UOPS_RETIRED) \ __PMC_EV(P6, INST_DECODED) \ __PMC_EV(P6, EMON_KNI_INST_RETIRED) \ __PMC_EV(P6, EMON_KNI_COMP_INST_RET) \ __PMC_EV(P6, HW_INT_RX) \ __PMC_EV(P6, CYCLES_INT_MASKED) \ __PMC_EV(P6, CYCLES_INT_PENDING_AND_MASKED) \ __PMC_EV(P6, BR_INST_RETIRED) \ __PMC_EV(P6, BR_MISS_PRED_RETIRED) \ __PMC_EV(P6, BR_TAKEN_RETIRED) \ __PMC_EV(P6, BR_MISS_PRED_TAKEN_RET) \ __PMC_EV(P6, BR_INST_DECODED) \ __PMC_EV(P6, BTB_MISSES) \ __PMC_EV(P6, BR_BOGUS) \ __PMC_EV(P6, BACLEARS) \ __PMC_EV(P6, RESOURCE_STALLS) \ __PMC_EV(P6, PARTIAL_RAT_STALLS) \ __PMC_EV(P6, SEGMENT_REG_LOADS) \ __PMC_EV(P6, CPU_CLK_UNHALTED) \ __PMC_EV(P6, MMX_INSTR_EXEC) \ __PMC_EV(P6, MMX_SAT_INSTR_EXEC) \ __PMC_EV(P6, MMX_UOPS_EXEC) \ __PMC_EV(P6, MMX_INSTR_TYPE_EXEC) \ __PMC_EV(P6, FP_MMX_TRANS) \ __PMC_EV(P6, MMX_ASSIST) \ __PMC_EV(P6, MMX_INSTR_RET) \ __PMC_EV(P6, SEG_RENAME_STALLS) \ __PMC_EV(P6, SEG_REG_RENAMES) \ __PMC_EV(P6, RET_SEG_RENAMES) \ __PMC_EV(P6, EMON_EST_TRANS) \ __PMC_EV(P6, EMON_THERMAL_TRIP) \ __PMC_EV(P6, BR_INST_EXEC) \ __PMC_EV(P6, BR_MISSP_EXEC) \ __PMC_EV(P6, BR_BAC_MISSP_EXEC) \ __PMC_EV(P6, BR_CND_EXEC) \ __PMC_EV(P6, BR_CND_MISSP_EXEC) \ __PMC_EV(P6, BR_IND_EXEC) \ __PMC_EV(P6, BR_IND_MISSP_EXEC) \ __PMC_EV(P6, BR_RET_EXEC) \ __PMC_EV(P6, BR_RET_MISSP_EXEC) \ __PMC_EV(P6, BR_RET_BAC_MISSP_EXEC) \ __PMC_EV(P6, BR_CALL_EXEC) \ __PMC_EV(P6, BR_CALL_MISSP_EXEC) \ __PMC_EV(P6, BR_IND_CALL_EXEC) \ __PMC_EV(P6, EMON_SIMD_INSTR_RETIRED) \ __PMC_EV(P6, EMON_SYNCH_UOPS) \ __PMC_EV(P6, EMON_ESP_UOPS) \ __PMC_EV(P6, EMON_FUSED_UOPS_RET) \ __PMC_EV(P6, EMON_UNFUSION) \ __PMC_EV(P6, EMON_PREF_RQSTS_UP) \ __PMC_EV(P6, EMON_PREF_RQSTS_DN) \ __PMC_EV(P6, EMON_SSE_SSE2_INST_RETIRED) \ __PMC_EV(P6, EMON_SSE_SSE2_COMP_INST_RETIRED) #define PMC_EV_P6_FIRST PMC_EV_P6_DATA_MEM_REFS #define PMC_EV_P6_LAST PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED /* AMD K8 PMCs */ #define __PMC_EV_K8() \ __PMC_EV(K8, FP_DISPATCHED_FPU_OPS) \ __PMC_EV(K8, FP_CYCLES_WITH_NO_FPU_OPS_RETIRED) \ __PMC_EV(K8, FP_DISPATCHED_FPU_FAST_FLAG_OPS) \ __PMC_EV(K8, LS_SEGMENT_REGISTER_LOAD) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \ __PMC_EV(K8, LS_BUFFER2_FULL) \ __PMC_EV(K8, LS_LOCKED_OPERATION) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_LATE_CANCEL) \ __PMC_EV(K8, LS_RETIRED_CFLUSH_INSTRUCTIONS) \ __PMC_EV(K8, LS_RETIRED_CPUID_INSTRUCTIONS) \ __PMC_EV(K8, DC_ACCESS) \ __PMC_EV(K8, DC_MISS) \ __PMC_EV(K8, DC_REFILL_FROM_L2) \ __PMC_EV(K8, DC_REFILL_FROM_SYSTEM) \ __PMC_EV(K8, DC_COPYBACK) \ __PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_HIT) \ __PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_MISS) \ __PMC_EV(K8, DC_MISALIGNED_DATA_REFERENCE) \ __PMC_EV(K8, DC_MICROARCHITECTURAL_LATE_CANCEL) \ __PMC_EV(K8, DC_MICROARCHITECTURAL_EARLY_CANCEL) \ __PMC_EV(K8, DC_ONE_BIT_ECC_ERROR) \ __PMC_EV(K8, DC_DISPATCHED_PREFETCH_INSTRUCTIONS) \ __PMC_EV(K8, DC_DCACHE_ACCESSES_BY_LOCKS) \ __PMC_EV(K8, BU_CPU_CLK_UNHALTED) \ __PMC_EV(K8, BU_INTERNAL_L2_REQUEST) \ __PMC_EV(K8, BU_FILL_REQUEST_L2_MISS) \ __PMC_EV(K8, BU_FILL_INTO_L2) \ __PMC_EV(K8, IC_FETCH) \ __PMC_EV(K8, IC_MISS) \ __PMC_EV(K8, IC_REFILL_FROM_L2) \ __PMC_EV(K8, IC_REFILL_FROM_SYSTEM) \ __PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_HIT) \ __PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_MISS) \ __PMC_EV(K8, IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \ __PMC_EV(K8, IC_INSTRUCTION_FETCH_STALL) \ __PMC_EV(K8, IC_RETURN_STACK_HIT) \ __PMC_EV(K8, IC_RETURN_STACK_OVERFLOW) \ __PMC_EV(K8, FR_RETIRED_X86_INSTRUCTIONS) \ __PMC_EV(K8, FR_RETIRED_UOPS) \ __PMC_EV(K8, FR_RETIRED_BRANCHES) \ __PMC_EV(K8, FR_RETIRED_BRANCHES_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_FAR_CONTROL_TRANSFERS) \ __PMC_EV(K8, FR_RETIRED_RESYNCS) \ __PMC_EV(K8, FR_RETIRED_NEAR_RETURNS) \ __PMC_EV(K8, FR_RETIRED_NEAR_RETURNS_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE) \ __PMC_EV(K8, FR_RETIRED_FPU_INSTRUCTIONS) \ __PMC_EV(K8, FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS) \ __PMC_EV(K8, FR_INTERRUPTS_MASKED_CYCLES) \ __PMC_EV(K8, FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \ __PMC_EV(K8, FR_TAKEN_HARDWARE_INTERRUPTS) \ __PMC_EV(K8, FR_DECODER_EMPTY) \ __PMC_EV(K8, FR_DISPATCH_STALLS) \ __PMC_EV(K8, FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE) \ __PMC_EV(K8, FR_DISPATCH_STALL_FOR_SERIALIZATION) \ __PMC_EV(K8, FR_DISPATCH_STALL_FOR_SEGMENT_LOAD) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FPU_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_LS_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING) \ __PMC_EV(K8, FR_FPU_EXCEPTIONS) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR0) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR1) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR2) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR3) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_TURNAROUND) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_BYPASS_SATURATION) \ __PMC_EV(K8, NB_SIZED_COMMANDS) \ __PMC_EV(K8, NB_PROBE_RESULT) \ __PMC_EV(K8, NB_HT_BUS0_BANDWIDTH) \ __PMC_EV(K8, NB_HT_BUS1_BANDWIDTH) \ __PMC_EV(K8, NB_HT_BUS2_BANDWIDTH) #define PMC_EV_K8_FIRST PMC_EV_K8_FP_DISPATCHED_FPU_OPS #define PMC_EV_K8_LAST PMC_EV_K8_NB_HT_BUS2_BANDWIDTH /* * Intel Pentium and Pentium MMX events, from the "Intel 64 and IA-32 * Architectures Software Developer's Manual, Volume 3B: System Programming * Guide, Part 2, August 2007". */ #define __PMC_EV_P5() \ __PMC_EV(P5, DATA_READ) \ __PMC_EV(P5, DATA_WRITE) \ __PMC_EV(P5, DATA_TLB_MISS) \ __PMC_EV(P5, DATA_READ_MISS) \ __PMC_EV(P5, DATA_WRITE_MISS) \ __PMC_EV(P5, WRITE_HIT_TO_M_OR_E_STATE_LINES) \ __PMC_EV(P5, DATA_CACHE_LINES_WRITTEN_BACK) \ __PMC_EV(P5, EXTERNAL_SNOOPS) \ __PMC_EV(P5, EXTERNAL_DATA_CACHE_SNOOP_HITS) \ __PMC_EV(P5, MEMORY_ACCESSES_IN_BOTH_PIPES) \ __PMC_EV(P5, BANK_CONFLICTS) \ __PMC_EV(P5, MISALIGNED_DATA_OR_IO_REFERENCES) \ __PMC_EV(P5, CODE_READ) \ __PMC_EV(P5, CODE_TLB_MISS) \ __PMC_EV(P5, CODE_CACHE_MISS) \ __PMC_EV(P5, ANY_SEGMENT_REGISTER_LOADED) \ __PMC_EV(P5, BRANCHES) \ __PMC_EV(P5, BTB_HITS) \ __PMC_EV(P5, TAKEN_BRANCH_OR_BTB_HIT) \ __PMC_EV(P5, PIPELINE_FLUSHES) \ __PMC_EV(P5, INSTRUCTIONS_EXECUTED) \ __PMC_EV(P5, INSTRUCTIONS_EXECUTED_V_PIPE) \ __PMC_EV(P5, BUS_CYCLE_DURATION) \ __PMC_EV(P5, WRITE_BUFFER_FULL_STALL_DURATION) \ __PMC_EV(P5, WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION) \ __PMC_EV(P5, STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE) \ __PMC_EV(P5, LOCKED_BUS_CYCLE) \ __PMC_EV(P5, IO_READ_OR_WRITE_CYCLE) \ __PMC_EV(P5, NONCACHEABLE_MEMORY_READS) \ __PMC_EV(P5, PIPELINE_AGI_STALLS) \ __PMC_EV(P5, FLOPS) \ __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR0_REGISTER) \ __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR1_REGISTER) \ __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR2_REGISTER) \ __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR3_REGISTER) \ __PMC_EV(P5, HARDWARE_INTERRUPTS) \ __PMC_EV(P5, DATA_READ_OR_WRITE) \ __PMC_EV(P5, DATA_READ_MISS_OR_WRITE_MISS) \ __PMC_EV(P5, BUS_OWNERSHIP_LATENCY) \ __PMC_EV(P5, BUS_OWNERSHIP_TRANSFERS) \ __PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_U_PIPE) \ __PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_V_PIPE) \ __PMC_EV(P5, CACHE_M_LINE_SHARING) \ __PMC_EV(P5, CACHE_LINE_SHARING) \ __PMC_EV(P5, EMMS_INSTRUCTIONS_EXECUTED) \ __PMC_EV(P5, TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS) \ __PMC_EV(P5, BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY) \ __PMC_EV(P5, WRITES_TO_NONCACHEABLE_MEMORY) \ __PMC_EV(P5, SATURATING_MMX_INSTRUCTIONS_EXECUTED) \ __PMC_EV(P5, SATURATIONS_PERFORMED) \ __PMC_EV(P5, NUMBER_OF_CYCLES_NOT_IN_HALT_STATE) \ __PMC_EV(P5, DATA_CACHE_TLB_MISS_STALL_DURATION) \ __PMC_EV(P5, MMX_INSTRUCTION_DATA_READS) \ __PMC_EV(P5, MMX_INSTRUCTION_DATA_READ_MISSES) \ __PMC_EV(P5, FLOATING_POINT_STALLS_DURATION) \ __PMC_EV(P5, TAKEN_BRANCHES) \ __PMC_EV(P5, D1_STARVATION_AND_FIFO_IS_EMPTY) \ __PMC_EV(P5, D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO) \ __PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITES) \ __PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITE_MISSES) \ __PMC_EV(P5, PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS) \ __PMC_EV(P5, \ PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB_STAGE) \ __PMC_EV(P5, MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS) \ __PMC_EV(P5, PIPELINE_STALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS) \ __PMC_EV(P5, MISPREDICTED_OR_UNPREDICTED_RETURNS) \ __PMC_EV(P5, PREDICTED_RETURNS) \ __PMC_EV(P5, MMX_MULTIPLY_UNIT_INTERLOCK) \ __PMC_EV(P5, MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION) \ __PMC_EV(P5, RETURNS) \ __PMC_EV(P5, BTB_FALSE_ENTRIES) \ __PMC_EV(P5, BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH) \ __PMC_EV(P5, \ FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS) \ __PMC_EV(P5, STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE) #define PMC_EV_P5_FIRST PMC_EV_P5_DATA_READ #define PMC_EV_P5_LAST \ PMC_EV_P5_STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE /* * Events supported by Intel architectural fixed function counters, * from the "Intel 64 and IA-32 Architectures Software Developer's * Manual Volume 3B: System Programming Guide, Part 2", July 2008. */ #define __PMC_EV_IAF() \ __PMC_EV(IAF, INSTR_RETIRED_ANY) \ __PMC_EV(IAF, CPU_CLK_UNHALTED_CORE) \ __PMC_EV(IAF, CPU_CLK_UNHALTED_REF) #define PMC_EV_IAF_FIRST PMC_EV_IAF_INSTR_RETIRED_ANY #define PMC_EV_IAF_LAST PMC_EV_IAF_CPU_CLK_UNHALTED_REF #define __PMC_EV_ALIAS_IAF() \ __PMC_EV_ALIAS("instruction-retired", IAF_INSTR_RETIRED_ANY) \ __PMC_EV_ALIAS("unhalted-core-cycles", IAF_CPU_CLK_UNHALTED_CORE) \ __PMC_EV_ALIAS("unhalted-reference-cycles", IAF_CPU_CLK_UNHALTED_REF) /* * Events supported by programmable function counters present in * Intel Atom, Core and Core2 CPUs, from the "Intel 64 and IA-32 * Architectures Software Developer's Manual Volume 3B: System Programming * Guide, Part 2", July 2008. * * These PMCs select events with a combination of an event code and * unit mask. Quirks that need to be taken care of include: * - The set of (event code, umask) combinations supported by a processor * varies according to the processor model. * - A given (event code, umask) combination need not measure the same * hardware event in all processor models. * - Event names in vendor documentation for an (event code, umask) pair * may vary according to the CPU model. * - Identically named events can map to different (event code, umask) * pairs on different CPUs. * - New (event code, umask) combinations continue to be added as CPUs * evolve. The interface between hwpmc(4) and libpmc(3) needs to be * robust with respect to ABI changes. * * The IAP_EVENT_* symbols below define the ABI between userland and kernel. * New (event code, * umask) combinations used in new CPUs would be added * to the end of the list. Vendor names for events are mapped to IAP_EVENT_* * symbols using aliases. The final disambiguation of semantics based on * the CPU model happens inside hwpmc(4). */ #define __PMC_EV_IAP() \ __PMC_EV(IAP, EVENT_02H_01H) \ __PMC_EV(IAP, EVENT_02H_81H) \ __PMC_EV(IAP, EVENT_03H_00H) \ __PMC_EV(IAP, EVENT_03H_01H) \ __PMC_EV(IAP, EVENT_03H_02H) \ __PMC_EV(IAP, EVENT_03H_04H) \ __PMC_EV(IAP, EVENT_03H_08H) \ __PMC_EV(IAP, EVENT_03H_10H) \ __PMC_EV(IAP, EVENT_03H_20H) \ __PMC_EV(IAP, EVENT_04H_00H) \ __PMC_EV(IAP, EVENT_04H_01H) \ __PMC_EV(IAP, EVENT_04H_02H) \ __PMC_EV(IAP, EVENT_04H_07H) \ __PMC_EV(IAP, EVENT_04H_08H) \ __PMC_EV(IAP, EVENT_05H_00H) \ __PMC_EV(IAP, EVENT_05H_01H) \ __PMC_EV(IAP, EVENT_05H_02H) \ __PMC_EV(IAP, EVENT_05H_03H) \ __PMC_EV(IAP, EVENT_06H_00H) \ __PMC_EV(IAP, EVENT_06H_01H) \ __PMC_EV(IAP, EVENT_06H_02H) \ __PMC_EV(IAP, EVENT_06H_04H) \ __PMC_EV(IAP, EVENT_06H_08H) \ __PMC_EV(IAP, EVENT_06H_0FH) \ __PMC_EV(IAP, EVENT_07H_00H) \ __PMC_EV(IAP, EVENT_07H_01H) \ __PMC_EV(IAP, EVENT_07H_02H) \ __PMC_EV(IAP, EVENT_07H_03H) \ __PMC_EV(IAP, EVENT_07H_06H) \ __PMC_EV(IAP, EVENT_07H_08H) \ __PMC_EV(IAP, EVENT_08H_01H) \ __PMC_EV(IAP, EVENT_08H_02H) \ __PMC_EV(IAP, EVENT_08H_04H) \ __PMC_EV(IAP, EVENT_08H_05H) \ __PMC_EV(IAP, EVENT_08H_06H) \ __PMC_EV(IAP, EVENT_08H_07H) \ __PMC_EV(IAP, EVENT_08H_08H) \ __PMC_EV(IAP, EVENT_08H_09H) \ __PMC_EV(IAP, EVENT_08H_10H) \ __PMC_EV(IAP, EVENT_08H_20H) \ __PMC_EV(IAP, EVENT_08H_40H) \ __PMC_EV(IAP, EVENT_08H_80H) \ __PMC_EV(IAP, EVENT_08H_81H) \ __PMC_EV(IAP, EVENT_08H_82H) \ __PMC_EV(IAP, EVENT_08H_84H) \ __PMC_EV(IAP, EVENT_09H_01H) \ __PMC_EV(IAP, EVENT_09H_02H) \ __PMC_EV(IAP, EVENT_09H_04H) \ __PMC_EV(IAP, EVENT_09H_08H) \ __PMC_EV(IAP, EVENT_0BH_01H) \ __PMC_EV(IAP, EVENT_0BH_02H) \ __PMC_EV(IAP, EVENT_0BH_10H) \ __PMC_EV(IAP, EVENT_0CH_01H) \ __PMC_EV(IAP, EVENT_0CH_02H) \ __PMC_EV(IAP, EVENT_0CH_03H) \ __PMC_EV(IAP, EVENT_0DH_03H) \ __PMC_EV(IAP, EVENT_0DH_40H) \ __PMC_EV(IAP, EVENT_0EH_01H) \ __PMC_EV(IAP, EVENT_0EH_02H) \ __PMC_EV(IAP, EVENT_0EH_10H) \ __PMC_EV(IAP, EVENT_0EH_20H) \ __PMC_EV(IAP, EVENT_0EH_40H) \ __PMC_EV(IAP, EVENT_0FH_01H) \ __PMC_EV(IAP, EVENT_0FH_02H) \ __PMC_EV(IAP, EVENT_0FH_08H) \ __PMC_EV(IAP, EVENT_0FH_10H) \ __PMC_EV(IAP, EVENT_0FH_20H) \ __PMC_EV(IAP, EVENT_0FH_80H) \ __PMC_EV(IAP, EVENT_10H_00H) \ __PMC_EV(IAP, EVENT_10H_01H) \ __PMC_EV(IAP, EVENT_10H_02H) \ __PMC_EV(IAP, EVENT_10H_04H) \ __PMC_EV(IAP, EVENT_10H_08H) \ __PMC_EV(IAP, EVENT_10H_10H) \ __PMC_EV(IAP, EVENT_10H_20H) \ __PMC_EV(IAP, EVENT_10H_40H) \ __PMC_EV(IAP, EVENT_10H_80H) \ __PMC_EV(IAP, EVENT_10H_81H) \ __PMC_EV(IAP, EVENT_11H_00H) \ __PMC_EV(IAP, EVENT_11H_01H) \ __PMC_EV(IAP, EVENT_11H_02H) \ __PMC_EV(IAP, EVENT_11H_81H) \ __PMC_EV(IAP, EVENT_12H_00H) \ __PMC_EV(IAP, EVENT_12H_01H) \ __PMC_EV(IAP, EVENT_12H_02H) \ __PMC_EV(IAP, EVENT_12H_04H) \ __PMC_EV(IAP, EVENT_12H_08H) \ __PMC_EV(IAP, EVENT_12H_10H) \ __PMC_EV(IAP, EVENT_12H_20H) \ __PMC_EV(IAP, EVENT_12H_40H) \ __PMC_EV(IAP, EVENT_12H_81H) \ __PMC_EV(IAP, EVENT_13H_00H) \ __PMC_EV(IAP, EVENT_13H_01H) \ __PMC_EV(IAP, EVENT_13H_02H) \ __PMC_EV(IAP, EVENT_13H_04H) \ __PMC_EV(IAP, EVENT_13H_07H) \ __PMC_EV(IAP, EVENT_13H_81H) \ __PMC_EV(IAP, EVENT_14H_00H) \ __PMC_EV(IAP, EVENT_14H_01H) \ __PMC_EV(IAP, EVENT_14H_02H) \ __PMC_EV(IAP, EVENT_17H_01H) \ __PMC_EV(IAP, EVENT_18H_00H) \ __PMC_EV(IAP, EVENT_18H_01H) \ __PMC_EV(IAP, EVENT_19H_00H) \ __PMC_EV(IAP, EVENT_19H_01H) \ __PMC_EV(IAP, EVENT_19H_02H) \ __PMC_EV(IAP, EVENT_1DH_01H) \ __PMC_EV(IAP, EVENT_1DH_02H) \ __PMC_EV(IAP, EVENT_1DH_04H) \ __PMC_EV(IAP, EVENT_1EH_01H) \ __PMC_EV(IAP, EVENT_20H_01H) \ __PMC_EV(IAP, EVENT_21H) \ __PMC_EV(IAP, EVENT_22H) \ __PMC_EV(IAP, EVENT_23H) \ __PMC_EV(IAP, EVENT_24H) \ __PMC_EV(IAP, EVENT_24H_01H) \ __PMC_EV(IAP, EVENT_24H_02H) \ __PMC_EV(IAP, EVENT_24H_03H) \ __PMC_EV(IAP, EVENT_24H_04H) \ __PMC_EV(IAP, EVENT_24H_08H) \ __PMC_EV(IAP, EVENT_24H_0CH) \ __PMC_EV(IAP, EVENT_24H_10H) \ __PMC_EV(IAP, EVENT_24H_20H) \ __PMC_EV(IAP, EVENT_24H_30H) \ __PMC_EV(IAP, EVENT_24H_40H) \ __PMC_EV(IAP, EVENT_24H_80H) \ __PMC_EV(IAP, EVENT_24H_AAH) \ __PMC_EV(IAP, EVENT_24H_C0H) \ __PMC_EV(IAP, EVENT_24H_FFH) \ __PMC_EV(IAP, EVENT_25H) \ __PMC_EV(IAP, EVENT_26H) \ __PMC_EV(IAP, EVENT_26H_01H) \ __PMC_EV(IAP, EVENT_26H_02H) \ __PMC_EV(IAP, EVENT_26H_04H) \ __PMC_EV(IAP, EVENT_26H_08H) \ __PMC_EV(IAP, EVENT_26H_0FH) \ __PMC_EV(IAP, EVENT_26H_10H) \ __PMC_EV(IAP, EVENT_26H_20H) \ __PMC_EV(IAP, EVENT_26H_40H) \ __PMC_EV(IAP, EVENT_26H_80H) \ __PMC_EV(IAP, EVENT_26H_F0H) \ __PMC_EV(IAP, EVENT_26H_FFH) \ __PMC_EV(IAP, EVENT_27H) \ __PMC_EV(IAP, EVENT_27H_01H) \ __PMC_EV(IAP, EVENT_27H_02H) \ __PMC_EV(IAP, EVENT_27H_04H) \ __PMC_EV(IAP, EVENT_27H_08H) \ __PMC_EV(IAP, EVENT_27H_0EH) \ __PMC_EV(IAP, EVENT_27H_0FH) \ __PMC_EV(IAP, EVENT_27H_10H) \ __PMC_EV(IAP, EVENT_27H_20H) \ __PMC_EV(IAP, EVENT_27H_40H) \ __PMC_EV(IAP, EVENT_27H_80H) \ __PMC_EV(IAP, EVENT_27H_E0H) \ __PMC_EV(IAP, EVENT_27H_F0H) \ __PMC_EV(IAP, EVENT_28H) \ __PMC_EV(IAP, EVENT_28H_01H) \ __PMC_EV(IAP, EVENT_28H_02H) \ __PMC_EV(IAP, EVENT_28H_04H) \ __PMC_EV(IAP, EVENT_28H_08H) \ __PMC_EV(IAP, EVENT_28H_0FH) \ __PMC_EV(IAP, EVENT_29H) \ __PMC_EV(IAP, EVENT_2AH) \ __PMC_EV(IAP, EVENT_2BH) \ __PMC_EV(IAP, EVENT_2EH) \ __PMC_EV(IAP, EVENT_2EH_01H) \ __PMC_EV(IAP, EVENT_2EH_02H) \ __PMC_EV(IAP, EVENT_2EH_41H) \ __PMC_EV(IAP, EVENT_2EH_4FH) \ __PMC_EV(IAP, EVENT_30H) \ __PMC_EV(IAP, EVENT_32H) \ __PMC_EV(IAP, EVENT_3AH) \ __PMC_EV(IAP, EVENT_3AH_00H) \ __PMC_EV(IAP, EVENT_3BH_C0H) \ __PMC_EV(IAP, EVENT_3CH_00H) \ __PMC_EV(IAP, EVENT_3CH_01H) \ __PMC_EV(IAP, EVENT_3CH_02H) \ __PMC_EV(IAP, EVENT_3DH_01H) \ __PMC_EV(IAP, EVENT_40H) \ __PMC_EV(IAP, EVENT_40H_01H) \ __PMC_EV(IAP, EVENT_40H_02H) \ __PMC_EV(IAP, EVENT_40H_04H) \ __PMC_EV(IAP, EVENT_40H_08H) \ __PMC_EV(IAP, EVENT_40H_0FH) \ __PMC_EV(IAP, EVENT_40H_21H) \ __PMC_EV(IAP, EVENT_41H) \ __PMC_EV(IAP, EVENT_41H_01H) \ __PMC_EV(IAP, EVENT_41H_02H) \ __PMC_EV(IAP, EVENT_41H_04H) \ __PMC_EV(IAP, EVENT_41H_08H) \ __PMC_EV(IAP, EVENT_41H_0FH) \ __PMC_EV(IAP, EVENT_41H_22H) \ __PMC_EV(IAP, EVENT_42H) \ __PMC_EV(IAP, EVENT_42H_01H) \ __PMC_EV(IAP, EVENT_42H_02H) \ __PMC_EV(IAP, EVENT_42H_04H) \ __PMC_EV(IAP, EVENT_42H_08H) \ __PMC_EV(IAP, EVENT_42H_10H) \ __PMC_EV(IAP, EVENT_43H_01H) \ __PMC_EV(IAP, EVENT_43H_02H) \ __PMC_EV(IAP, EVENT_44H_02H) \ __PMC_EV(IAP, EVENT_45H_0FH) \ __PMC_EV(IAP, EVENT_46H_00H) \ __PMC_EV(IAP, EVENT_47H_00H) \ __PMC_EV(IAP, EVENT_48H_00H) \ __PMC_EV(IAP, EVENT_48H_01H) \ __PMC_EV(IAP, EVENT_48H_02H) \ __PMC_EV(IAP, EVENT_49H_00H) \ __PMC_EV(IAP, EVENT_49H_01H) \ __PMC_EV(IAP, EVENT_49H_02H) \ __PMC_EV(IAP, EVENT_49H_04H) \ __PMC_EV(IAP, EVENT_49H_10H) \ __PMC_EV(IAP, EVENT_49H_20H) \ __PMC_EV(IAP, EVENT_49H_40H) \ __PMC_EV(IAP, EVENT_49H_80H) \ __PMC_EV(IAP, EVENT_4BH_00H) \ __PMC_EV(IAP, EVENT_4BH_01H) \ __PMC_EV(IAP, EVENT_4BH_02H) \ __PMC_EV(IAP, EVENT_4BH_03H) \ __PMC_EV(IAP, EVENT_4BH_08H) \ __PMC_EV(IAP, EVENT_4CH_00H) \ __PMC_EV(IAP, EVENT_4CH_01H) \ __PMC_EV(IAP, EVENT_4CH_02H) \ __PMC_EV(IAP, EVENT_4DH_01H) \ __PMC_EV(IAP, EVENT_4EH_01H) \ __PMC_EV(IAP, EVENT_4EH_02H) \ __PMC_EV(IAP, EVENT_4EH_04H) \ __PMC_EV(IAP, EVENT_4EH_10H) \ __PMC_EV(IAP, EVENT_4FH_00H) \ __PMC_EV(IAP, EVENT_4FH_02H) \ __PMC_EV(IAP, EVENT_4FH_04H) \ __PMC_EV(IAP, EVENT_4FH_08H) \ __PMC_EV(IAP, EVENT_4FH_10H) \ __PMC_EV(IAP, EVENT_51H_01H) \ __PMC_EV(IAP, EVENT_51H_02H) \ __PMC_EV(IAP, EVENT_51H_04H) \ __PMC_EV(IAP, EVENT_51H_08H) \ __PMC_EV(IAP, EVENT_52H_01H) \ __PMC_EV(IAP, EVENT_53H_01H) \ __PMC_EV(IAP, EVENT_58H_01H) \ __PMC_EV(IAP, EVENT_58H_02H) \ __PMC_EV(IAP, EVENT_58H_04H) \ __PMC_EV(IAP, EVENT_58H_08H) \ __PMC_EV(IAP, EVENT_59H_20H) \ __PMC_EV(IAP, EVENT_59H_40H) \ __PMC_EV(IAP, EVENT_59H_80H) \ __PMC_EV(IAP, EVENT_5BH_0CH) \ __PMC_EV(IAP, EVENT_5BH_0FH) \ __PMC_EV(IAP, EVENT_5BH_40H) \ __PMC_EV(IAP, EVENT_5BH_4FH) \ __PMC_EV(IAP, EVENT_5CH_01H) \ __PMC_EV(IAP, EVENT_5CH_02H) \ __PMC_EV(IAP, EVENT_5EH_01H) \ __PMC_EV(IAP, EVENT_5FH_01H) \ __PMC_EV(IAP, EVENT_60H) \ __PMC_EV(IAP, EVENT_60H_01H) \ __PMC_EV(IAP, EVENT_60H_02H) \ __PMC_EV(IAP, EVENT_60H_04H) \ __PMC_EV(IAP, EVENT_60H_08H) \ __PMC_EV(IAP, EVENT_61H) \ __PMC_EV(IAP, EVENT_61H_00H) \ __PMC_EV(IAP, EVENT_62H) \ __PMC_EV(IAP, EVENT_62H_00H) \ __PMC_EV(IAP, EVENT_63H) \ __PMC_EV(IAP, EVENT_63H_01H) \ __PMC_EV(IAP, EVENT_63H_02H) \ __PMC_EV(IAP, EVENT_64H) \ __PMC_EV(IAP, EVENT_64H_40H) \ __PMC_EV(IAP, EVENT_65H) \ __PMC_EV(IAP, EVENT_66H) \ __PMC_EV(IAP, EVENT_67H) \ __PMC_EV(IAP, EVENT_68H) \ __PMC_EV(IAP, EVENT_69H) \ __PMC_EV(IAP, EVENT_6AH) \ __PMC_EV(IAP, EVENT_6BH) \ __PMC_EV(IAP, EVENT_6CH) \ __PMC_EV(IAP, EVENT_6CH_01H) \ __PMC_EV(IAP, EVENT_6DH) \ __PMC_EV(IAP, EVENT_6EH) \ __PMC_EV(IAP, EVENT_6FH) \ __PMC_EV(IAP, EVENT_70H) \ __PMC_EV(IAP, EVENT_77H) \ __PMC_EV(IAP, EVENT_78H) \ __PMC_EV(IAP, EVENT_79H_02H) \ __PMC_EV(IAP, EVENT_79H_04H) \ __PMC_EV(IAP, EVENT_79H_08H) \ __PMC_EV(IAP, EVENT_79H_10H) \ __PMC_EV(IAP, EVENT_79H_20H) \ __PMC_EV(IAP, EVENT_79H_30H) \ __PMC_EV(IAP, EVENT_79H_18H) \ __PMC_EV(IAP, EVENT_79H_24H) \ __PMC_EV(IAP, EVENT_79H_3CH) \ __PMC_EV(IAP, EVENT_7AH) \ __PMC_EV(IAP, EVENT_7BH) \ __PMC_EV(IAP, EVENT_7DH) \ __PMC_EV(IAP, EVENT_7EH) \ __PMC_EV(IAP, EVENT_7EH_00H) \ __PMC_EV(IAP, EVENT_7FH) \ __PMC_EV(IAP, EVENT_80H_00H) \ __PMC_EV(IAP, EVENT_80H_01H) \ __PMC_EV(IAP, EVENT_80H_02H) \ __PMC_EV(IAP, EVENT_80H_03H) \ __PMC_EV(IAP, EVENT_80H_04H) \ __PMC_EV(IAP, EVENT_80H_10H) \ __PMC_EV(IAP, EVENT_81H_00H) \ __PMC_EV(IAP, EVENT_81H_01H) \ __PMC_EV(IAP, EVENT_81H_02H) \ __PMC_EV(IAP, EVENT_82H_01H) \ __PMC_EV(IAP, EVENT_82H_02H) \ __PMC_EV(IAP, EVENT_82H_04H) \ __PMC_EV(IAP, EVENT_82H_10H) \ __PMC_EV(IAP, EVENT_82H_12H) \ __PMC_EV(IAP, EVENT_82H_40H) \ __PMC_EV(IAP, EVENT_83H_01H) \ __PMC_EV(IAP, EVENT_83H_02H) \ __PMC_EV(IAP, EVENT_85H_00H) \ __PMC_EV(IAP, EVENT_85H_01H) \ __PMC_EV(IAP, EVENT_85H_02H) \ __PMC_EV(IAP, EVENT_85H_04H) \ __PMC_EV(IAP, EVENT_85H_10H) \ __PMC_EV(IAP, EVENT_85H_20H) \ __PMC_EV(IAP, EVENT_85H_40H) \ __PMC_EV(IAP, EVENT_85H_80H) \ __PMC_EV(IAP, EVENT_86H_00H) \ __PMC_EV(IAP, EVENT_87H_00H) \ __PMC_EV(IAP, EVENT_87H_01H) \ __PMC_EV(IAP, EVENT_87H_02H) \ __PMC_EV(IAP, EVENT_87H_04H) \ __PMC_EV(IAP, EVENT_87H_08H) \ __PMC_EV(IAP, EVENT_87H_0FH) \ __PMC_EV(IAP, EVENT_88H_00H) \ __PMC_EV(IAP, EVENT_88H_01H) \ __PMC_EV(IAP, EVENT_88H_02H) \ __PMC_EV(IAP, EVENT_88H_04H) \ __PMC_EV(IAP, EVENT_88H_07H) \ __PMC_EV(IAP, EVENT_88H_08H) \ __PMC_EV(IAP, EVENT_88H_10H) \ __PMC_EV(IAP, EVENT_88H_20H) \ __PMC_EV(IAP, EVENT_88H_30H) \ __PMC_EV(IAP, EVENT_88H_40H) \ __PMC_EV(IAP, EVENT_88H_80H) \ __PMC_EV(IAP, EVENT_88H_7FH) \ __PMC_EV(IAP, EVENT_88H_FFH) \ __PMC_EV(IAP, EVENT_89H_00H) \ __PMC_EV(IAP, EVENT_89H_01H) \ __PMC_EV(IAP, EVENT_89H_02H) \ __PMC_EV(IAP, EVENT_89H_04H) \ __PMC_EV(IAP, EVENT_89H_07H) \ __PMC_EV(IAP, EVENT_89H_08H) \ __PMC_EV(IAP, EVENT_89H_10H) \ __PMC_EV(IAP, EVENT_89H_20H) \ __PMC_EV(IAP, EVENT_89H_30H) \ __PMC_EV(IAP, EVENT_89H_40H) \ __PMC_EV(IAP, EVENT_89H_80H) \ __PMC_EV(IAP, EVENT_89H_7FH) \ __PMC_EV(IAP, EVENT_89H_FFH) \ __PMC_EV(IAP, EVENT_8AH_00H) \ __PMC_EV(IAP, EVENT_8BH_00H) \ __PMC_EV(IAP, EVENT_8CH_00H) \ __PMC_EV(IAP, EVENT_8DH_00H) \ __PMC_EV(IAP, EVENT_8EH_00H) \ __PMC_EV(IAP, EVENT_8FH_00H) \ __PMC_EV(IAP, EVENT_90H_00H) \ __PMC_EV(IAP, EVENT_91H_00H) \ __PMC_EV(IAP, EVENT_92H_00H) \ __PMC_EV(IAP, EVENT_93H_00H) \ __PMC_EV(IAP, EVENT_94H_00H) \ __PMC_EV(IAP, EVENT_97H_00H) \ __PMC_EV(IAP, EVENT_98H_00H) \ __PMC_EV(IAP, EVENT_9CH_01H) \ __PMC_EV(IAP, EVENT_A0H_00H) \ __PMC_EV(IAP, EVENT_A1H_01H) \ __PMC_EV(IAP, EVENT_A1H_02H) \ __PMC_EV(IAP, EVENT_A1H_04H) \ __PMC_EV(IAP, EVENT_A1H_08H) \ __PMC_EV(IAP, EVENT_A1H_0CH) \ __PMC_EV(IAP, EVENT_A1H_10H) \ __PMC_EV(IAP, EVENT_A1H_20H) \ __PMC_EV(IAP, EVENT_A1H_30H) \ __PMC_EV(IAP, EVENT_A1H_40H) \ __PMC_EV(IAP, EVENT_A1H_80H) \ __PMC_EV(IAP, EVENT_A2H_00H) \ __PMC_EV(IAP, EVENT_A2H_01H) \ __PMC_EV(IAP, EVENT_A2H_02H) \ __PMC_EV(IAP, EVENT_A2H_04H) \ __PMC_EV(IAP, EVENT_A2H_08H) \ __PMC_EV(IAP, EVENT_A2H_10H) \ __PMC_EV(IAP, EVENT_A2H_20H) \ __PMC_EV(IAP, EVENT_A2H_40H) \ __PMC_EV(IAP, EVENT_A2H_80H) \ +__PMC_EV(IAP, EVENT_A3H_01H) \ +__PMC_EV(IAP, EVENT_A3H_02H) \ +__PMC_EV(IAP, EVENT_A3H_04H) \ __PMC_EV(IAP, EVENT_A6H_01H) \ __PMC_EV(IAP, EVENT_A7H_01H) \ __PMC_EV(IAP, EVENT_A8H_01H) \ __PMC_EV(IAP, EVENT_AAH_01H) \ __PMC_EV(IAP, EVENT_AAH_02H) \ __PMC_EV(IAP, EVENT_AAH_03H) \ __PMC_EV(IAP, EVENT_AAH_08H) \ __PMC_EV(IAP, EVENT_ABH_01H) \ __PMC_EV(IAP, EVENT_ABH_02H) \ __PMC_EV(IAP, EVENT_ACH_02H) \ __PMC_EV(IAP, EVENT_ACH_08H) \ __PMC_EV(IAP, EVENT_ACH_0AH) \ __PMC_EV(IAP, EVENT_AEH_01H) \ __PMC_EV(IAP, EVENT_B0H_00H) \ __PMC_EV(IAP, EVENT_B0H_01H) \ __PMC_EV(IAP, EVENT_B0H_02H) \ __PMC_EV(IAP, EVENT_B0H_04H) \ __PMC_EV(IAP, EVENT_B0H_08H) \ __PMC_EV(IAP, EVENT_B0H_10H) \ __PMC_EV(IAP, EVENT_B0H_20H) \ __PMC_EV(IAP, EVENT_B0H_40H) \ __PMC_EV(IAP, EVENT_B0H_80H) \ __PMC_EV(IAP, EVENT_B1H_00H) \ __PMC_EV(IAP, EVENT_B1H_01H) \ __PMC_EV(IAP, EVENT_B1H_02H) \ __PMC_EV(IAP, EVENT_B1H_04H) \ __PMC_EV(IAP, EVENT_B1H_08H) \ __PMC_EV(IAP, EVENT_B1H_10H) \ __PMC_EV(IAP, EVENT_B1H_1FH) \ __PMC_EV(IAP, EVENT_B1H_20H) \ __PMC_EV(IAP, EVENT_B1H_3FH) \ __PMC_EV(IAP, EVENT_B1H_40H) \ __PMC_EV(IAP, EVENT_B1H_80H) \ __PMC_EV(IAP, EVENT_B2H_01H) \ __PMC_EV(IAP, EVENT_B3H_01H) \ __PMC_EV(IAP, EVENT_B3H_02H) \ __PMC_EV(IAP, EVENT_B3H_04H) \ __PMC_EV(IAP, EVENT_B3H_08H) \ __PMC_EV(IAP, EVENT_B3H_10H) \ __PMC_EV(IAP, EVENT_B3H_20H) \ __PMC_EV(IAP, EVENT_B3H_81H) \ __PMC_EV(IAP, EVENT_B3H_82H) \ __PMC_EV(IAP, EVENT_B3H_84H) \ __PMC_EV(IAP, EVENT_B3H_88H) \ __PMC_EV(IAP, EVENT_B3H_90H) \ __PMC_EV(IAP, EVENT_B3H_A0H) \ __PMC_EV(IAP, EVENT_B4H_01H) \ __PMC_EV(IAP, EVENT_B4H_02H) \ __PMC_EV(IAP, EVENT_B4H_04H) \ __PMC_EV(IAP, EVENT_B6H_01H) \ __PMC_EV(IAP, EVENT_B7H_01H) \ __PMC_EV(IAP, EVENT_B8H_01H) \ __PMC_EV(IAP, EVENT_B8H_02H) \ __PMC_EV(IAP, EVENT_B8H_04H) \ __PMC_EV(IAP, EVENT_BAH_01H) \ __PMC_EV(IAP, EVENT_BAH_02H) \ __PMC_EV(IAP, EVENT_BBH_01H) \ __PMC_EV(IAP, EVENT_BDH_01H) \ __PMC_EV(IAP, EVENT_BDH_20H) \ __PMC_EV(IAP, EVENT_BFH_05H) \ __PMC_EV(IAP, EVENT_C0H_00H) \ __PMC_EV(IAP, EVENT_C0H_01H) \ __PMC_EV(IAP, EVENT_C0H_02H) \ __PMC_EV(IAP, EVENT_C0H_04H) \ __PMC_EV(IAP, EVENT_C0H_08H) \ __PMC_EV(IAP, EVENT_C1H_00H) \ __PMC_EV(IAP, EVENT_C1H_01H) \ __PMC_EV(IAP, EVENT_C1H_02H) \ __PMC_EV(IAP, EVENT_C1H_08H) \ __PMC_EV(IAP, EVENT_C1H_10H) \ __PMC_EV(IAP, EVENT_C1H_20H) \ __PMC_EV(IAP, EVENT_C1H_FEH) \ __PMC_EV(IAP, EVENT_C2H_00H) \ __PMC_EV(IAP, EVENT_C2H_01H) \ __PMC_EV(IAP, EVENT_C2H_02H) \ __PMC_EV(IAP, EVENT_C2H_04H) \ __PMC_EV(IAP, EVENT_C2H_07H) \ __PMC_EV(IAP, EVENT_C2H_08H) \ __PMC_EV(IAP, EVENT_C2H_0FH) \ __PMC_EV(IAP, EVENT_C2H_10H) \ __PMC_EV(IAP, EVENT_C3H_00H) \ __PMC_EV(IAP, EVENT_C3H_01H) \ __PMC_EV(IAP, EVENT_C3H_02H) \ __PMC_EV(IAP, EVENT_C3H_04H) \ __PMC_EV(IAP, EVENT_C3H_10H) \ __PMC_EV(IAP, EVENT_C3H_20H) \ __PMC_EV(IAP, EVENT_C4H_00H) \ __PMC_EV(IAP, EVENT_C4H_01H) \ __PMC_EV(IAP, EVENT_C4H_02H) \ __PMC_EV(IAP, EVENT_C4H_04H) \ __PMC_EV(IAP, EVENT_C4H_08H) \ __PMC_EV(IAP, EVENT_C4H_0CH) \ __PMC_EV(IAP, EVENT_C4H_0FH) \ __PMC_EV(IAP, EVENT_C4H_10H) \ __PMC_EV(IAP, EVENT_C4H_20H) \ __PMC_EV(IAP, EVENT_C4H_40H) \ __PMC_EV(IAP, EVENT_C5H_00H) \ __PMC_EV(IAP, EVENT_C5H_01H) \ __PMC_EV(IAP, EVENT_C5H_02H) \ __PMC_EV(IAP, EVENT_C5H_04H) \ __PMC_EV(IAP, EVENT_C5H_10H) \ __PMC_EV(IAP, EVENT_C5H_20H) \ __PMC_EV(IAP, EVENT_C6H_00H) \ __PMC_EV(IAP, EVENT_C6H_01H) \ __PMC_EV(IAP, EVENT_C6H_02H) \ __PMC_EV(IAP, EVENT_C7H_00H) \ __PMC_EV(IAP, EVENT_C7H_01H) \ __PMC_EV(IAP, EVENT_C7H_02H) \ __PMC_EV(IAP, EVENT_C7H_04H) \ __PMC_EV(IAP, EVENT_C7H_08H) \ __PMC_EV(IAP, EVENT_C7H_10H) \ __PMC_EV(IAP, EVENT_C7H_1FH) \ __PMC_EV(IAP, EVENT_C8H_00H) \ __PMC_EV(IAP, EVENT_C8H_20H) \ __PMC_EV(IAP, EVENT_C9H_00H) \ __PMC_EV(IAP, EVENT_CAH_00H) \ __PMC_EV(IAP, EVENT_CAH_01H) \ __PMC_EV(IAP, EVENT_CAH_02H) \ __PMC_EV(IAP, EVENT_CAH_04H) \ __PMC_EV(IAP, EVENT_CAH_08H) \ __PMC_EV(IAP, EVENT_CAH_10H) \ __PMC_EV(IAP, EVENT_CAH_1EH) \ __PMC_EV(IAP, EVENT_CBH_01H) \ __PMC_EV(IAP, EVENT_CBH_02H) \ __PMC_EV(IAP, EVENT_CBH_04H) \ __PMC_EV(IAP, EVENT_CBH_08H) \ __PMC_EV(IAP, EVENT_CBH_10H) \ __PMC_EV(IAP, EVENT_CBH_40H) \ __PMC_EV(IAP, EVENT_CBH_80H) \ __PMC_EV(IAP, EVENT_CCH_00H) \ __PMC_EV(IAP, EVENT_CCH_01H) \ __PMC_EV(IAP, EVENT_CCH_02H) \ __PMC_EV(IAP, EVENT_CCH_03H) \ __PMC_EV(IAP, EVENT_CCH_20H) \ __PMC_EV(IAP, EVENT_CDH_00H) \ __PMC_EV(IAP, EVENT_CDH_01H) \ __PMC_EV(IAP, EVENT_CDH_02H) \ __PMC_EV(IAP, EVENT_CEH_00H) \ __PMC_EV(IAP, EVENT_CFH_00H) \ __PMC_EV(IAP, EVENT_D0H_00H) \ __PMC_EV(IAP, EVENT_D0H_01H) \ __PMC_EV(IAP, EVENT_D0H_02H) \ __PMC_EV(IAP, EVENT_D0H_10H) \ __PMC_EV(IAP, EVENT_D0H_20H) \ __PMC_EV(IAP, EVENT_D0H_40H) \ __PMC_EV(IAP, EVENT_D0H_80H) \ __PMC_EV(IAP, EVENT_D1H_01H) \ __PMC_EV(IAP, EVENT_D1H_02H) \ __PMC_EV(IAP, EVENT_D1H_04H) \ __PMC_EV(IAP, EVENT_D1H_08H) \ +__PMC_EV(IAP, EVENT_D1H_20H) \ __PMC_EV(IAP, EVENT_D1H_40H) \ __PMC_EV(IAP, EVENT_D2H_01H) \ __PMC_EV(IAP, EVENT_D2H_02H) \ __PMC_EV(IAP, EVENT_D2H_04H) \ __PMC_EV(IAP, EVENT_D2H_08H) \ __PMC_EV(IAP, EVENT_D2H_0FH) \ __PMC_EV(IAP, EVENT_D2H_10H) \ __PMC_EV(IAP, EVENT_D3H_01H) \ +__PMC_EV(IAP, EVENT_D3H_04H) \ __PMC_EV(IAP, EVENT_D4H_01H) \ __PMC_EV(IAP, EVENT_D4H_02H) \ __PMC_EV(IAP, EVENT_D4H_04H) \ __PMC_EV(IAP, EVENT_D4H_08H) \ __PMC_EV(IAP, EVENT_D4H_0FH) \ __PMC_EV(IAP, EVENT_D5H_01H) \ __PMC_EV(IAP, EVENT_D5H_02H) \ __PMC_EV(IAP, EVENT_D5H_04H) \ __PMC_EV(IAP, EVENT_D5H_08H) \ __PMC_EV(IAP, EVENT_D5H_0FH) \ __PMC_EV(IAP, EVENT_D7H_00H) \ __PMC_EV(IAP, EVENT_D8H_00H) \ __PMC_EV(IAP, EVENT_D8H_01H) \ __PMC_EV(IAP, EVENT_D8H_02H) \ __PMC_EV(IAP, EVENT_D8H_03H) \ __PMC_EV(IAP, EVENT_D8H_04H) \ __PMC_EV(IAP, EVENT_D9H_00H) \ __PMC_EV(IAP, EVENT_D9H_01H) \ __PMC_EV(IAP, EVENT_D9H_02H) \ __PMC_EV(IAP, EVENT_D9H_03H) \ __PMC_EV(IAP, EVENT_DAH_00H) \ __PMC_EV(IAP, EVENT_DAH_01H) \ __PMC_EV(IAP, EVENT_DAH_02H) \ __PMC_EV(IAP, EVENT_DBH_00H) \ __PMC_EV(IAP, EVENT_DBH_01H) \ __PMC_EV(IAP, EVENT_DCH_01H) \ __PMC_EV(IAP, EVENT_DCH_02H) \ __PMC_EV(IAP, EVENT_DCH_04H) \ __PMC_EV(IAP, EVENT_DCH_08H) \ __PMC_EV(IAP, EVENT_DCH_10H) \ __PMC_EV(IAP, EVENT_DCH_1FH) \ __PMC_EV(IAP, EVENT_E0H_00H) \ __PMC_EV(IAP, EVENT_E0H_01H) \ __PMC_EV(IAP, EVENT_E2H_00H) \ __PMC_EV(IAP, EVENT_E4H_00H) \ __PMC_EV(IAP, EVENT_E4H_01H) \ __PMC_EV(IAP, EVENT_E5H_01H) \ __PMC_EV(IAP, EVENT_E6H_00H) \ __PMC_EV(IAP, EVENT_E6H_01H) \ __PMC_EV(IAP, EVENT_E6H_02H) \ __PMC_EV(IAP, EVENT_E8H_01H) \ __PMC_EV(IAP, EVENT_E8H_02H) \ __PMC_EV(IAP, EVENT_E8H_03H) \ __PMC_EV(IAP, EVENT_ECH_01H) \ __PMC_EV(IAP, EVENT_F0H_00H) \ __PMC_EV(IAP, EVENT_F0H_01H) \ __PMC_EV(IAP, EVENT_F0H_02H) \ __PMC_EV(IAP, EVENT_F0H_04H) \ __PMC_EV(IAP, EVENT_F0H_08H) \ __PMC_EV(IAP, EVENT_F0H_10H) \ __PMC_EV(IAP, EVENT_F0H_20H) \ __PMC_EV(IAP, EVENT_F0H_40H) \ __PMC_EV(IAP, EVENT_F0H_80H) \ __PMC_EV(IAP, EVENT_F1H_01H) \ __PMC_EV(IAP, EVENT_F1H_02H) \ __PMC_EV(IAP, EVENT_F1H_04H) \ __PMC_EV(IAP, EVENT_F1H_07H) \ __PMC_EV(IAP, EVENT_F2H_01H) \ __PMC_EV(IAP, EVENT_F2H_02H) \ __PMC_EV(IAP, EVENT_F2H_04H) \ __PMC_EV(IAP, EVENT_F2H_08H) \ __PMC_EV(IAP, EVENT_F2H_0AH) \ __PMC_EV(IAP, EVENT_F2H_0FH) \ __PMC_EV(IAP, EVENT_F3H_01H) \ __PMC_EV(IAP, EVENT_F3H_02H) \ __PMC_EV(IAP, EVENT_F3H_04H) \ __PMC_EV(IAP, EVENT_F3H_08H) \ __PMC_EV(IAP, EVENT_F3H_10H) \ __PMC_EV(IAP, EVENT_F3H_20H) \ __PMC_EV(IAP, EVENT_F4H_01H) \ __PMC_EV(IAP, EVENT_F4H_02H) \ __PMC_EV(IAP, EVENT_F4H_04H) \ __PMC_EV(IAP, EVENT_F4H_08H) \ __PMC_EV(IAP, EVENT_F4H_10H) \ __PMC_EV(IAP, EVENT_F6H_01H) \ __PMC_EV(IAP, EVENT_F7H_01H) \ __PMC_EV(IAP, EVENT_F7H_02H) \ __PMC_EV(IAP, EVENT_F7H_04H) \ __PMC_EV(IAP, EVENT_F8H_00H) \ __PMC_EV(IAP, EVENT_F8H_01H) \ __PMC_EV(IAP, EVENT_FDH_01H) \ __PMC_EV(IAP, EVENT_FDH_02H) \ __PMC_EV(IAP, EVENT_FDH_04H) \ __PMC_EV(IAP, EVENT_FDH_08H) \ __PMC_EV(IAP, EVENT_FDH_10H) \ __PMC_EV(IAP, EVENT_FDH_20H) \ __PMC_EV(IAP, EVENT_FDH_40H) #define PMC_EV_IAP_FIRST PMC_EV_IAP_EVENT_02H_01H #define PMC_EV_IAP_LAST PMC_EV_IAP_EVENT_FDH_40H /* * Map "architectural" event names to event ids. */ #define __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("branch-instruction-retired", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("branch-misses-retired", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("instruction-retired", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("llc-misses", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("llc-reference", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("unhalted-reference-cycles", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_EVENT_3CH_00H) /* * Aliases for Atom PMCs. */ #define __PMC_EV_ALIAS_ATOM() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("BACLEARS", IAP_EVENT_E6H_01H) \ __PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_00H) \ __PMC_EV_ALIAS("BR_BAC_MISSP_EXEC", IAP_EVENT_8AH_00H) \ __PMC_EV_ALIAS("BR_CALL_EXEC", IAP_EVENT_92H_00H) \ __PMC_EV_ALIAS("BR_CALL_MISSP_EXEC", IAP_EVENT_93H_00H) \ __PMC_EV_ALIAS("BR_CND_EXEC", IAP_EVENT_8BH_00H) \ __PMC_EV_ALIAS("BR_CND_MISSP_EXEC", IAP_EVENT_8CH_00H) \ __PMC_EV_ALIAS("BR_IND_CALL_EXEC", IAP_EVENT_94H_00H) \ __PMC_EV_ALIAS("BR_IND_EXEC", IAP_EVENT_8DH_00H) \ __PMC_EV_ALIAS("BR_IND_MISSP_EXEC", IAP_EVENT_8EH_00H) \ __PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ __PMC_EV_ALIAS("BR_INST_EXEC", IAP_EVENT_88H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ANY", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ANY1", IAP_EVENT_C4H_0FH) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN", \ IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN",IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN", IAP_EVENT_C4H_0CH) \ __PMC_EV_ALIAS("BR_MISSP_EXEC", IAP_EVENT_89H_00H) \ __PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC", IAP_EVENT_91H_00H) \ __PMC_EV_ALIAS("BR_RET_EXEC", IAP_EVENT_8FH_00H) \ __PMC_EV_ALIAS("BR_RET_MISSP_EXEC", IAP_EVENT_90H_00H) \ __PMC_EV_ALIAS("BR_TKN_BUBBLE_1", IAP_EVENT_97H_00H) \ __PMC_EV_ALIAS("BR_TKN_BUBBLE_2", IAP_EVENT_98H_00H) \ __PMC_EV_ALIAS("BUSQ_EMPTY", IAP_EVENT_7DH) \ __PMC_EV_ALIAS("BUS_BNR_DRV", IAP_EVENT_61H) \ __PMC_EV_ALIAS("BUS_DATA_RCV", IAP_EVENT_64H) \ __PMC_EV_ALIAS("BUS_DRDY_CLOCKS", IAP_EVENT_62H) \ __PMC_EV_ALIAS("BUS_HITM_DRV", IAP_EVENT_7BH) \ __PMC_EV_ALIAS("BUS_HIT_DRV", IAP_EVENT_7AH) \ __PMC_EV_ALIAS("BUS_IO_WAIT", IAP_EVENT_7FH) \ __PMC_EV_ALIAS("BUS_LOCK_CLOCKS", IAP_EVENT_63H) \ __PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING", IAP_EVENT_60H) \ __PMC_EV_ALIAS("BUS_TRANS_ANY", IAP_EVENT_70H) \ __PMC_EV_ALIAS("BUS_TRANS_BRD", IAP_EVENT_65H) \ __PMC_EV_ALIAS("BUS_TRANS_BURST", IAP_EVENT_6EH) \ __PMC_EV_ALIAS("BUS_TRANS_DEF", IAP_EVENT_6DH) \ __PMC_EV_ALIAS("BUS_TRANS_IFETCH", IAP_EVENT_68H) \ __PMC_EV_ALIAS("BUS_TRANS_INVAL", IAP_EVENT_69H) \ __PMC_EV_ALIAS("BUS_TRANS_IO", IAP_EVENT_6CH) \ __PMC_EV_ALIAS("BUS_TRANS_MEM", IAP_EVENT_6FH) \ __PMC_EV_ALIAS("BUS_TRANS_P", IAP_EVENT_6BH) \ __PMC_EV_ALIAS("BUS_TRANS_PWR", IAP_EVENT_6AH) \ __PMC_EV_ALIAS("BUS_TRANS_RFO", IAP_EVENT_66H) \ __PMC_EV_ALIAS("BUS_TRANS_WB", IAP_EVENT_67H) \ __PMC_EV_ALIAS("CMP_SNOOP", IAP_EVENT_78H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER", IAP_EVENT_3CH_02H) \ __PMC_EV_ALIAS("CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_MASKED", \ IAP_EVENT_C6H_01H) \ __PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", \ IAP_EVENT_C6H_02H) \ __PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H) \ __PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS", IAP_EVENT_08H_07H) \ __PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_LD", IAP_EVENT_08H_05H) \ __PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_ST", IAP_EVENT_08H_06H) \ __PMC_EV_ALIAS("DATA_TLB_MISSES.UTLB_MISS_LD", IAP_EVENT_08H_09H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.FP", IAP_EVENT_19H_00H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.LOAD", IAP_EVENT_19H_01H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.SIMD", IAP_EVENT_19H_02H) \ __PMC_EV_ALIAS("DIV", IAP_EVENT_13H_00H) \ __PMC_EV_ALIAS("DIV.AR", IAP_EVENT_13H_81H) \ __PMC_EV_ALIAS("DIV.S", IAP_EVENT_13H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_MISSES.MISS_LD", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.MISS_ST", IAP_EVENT_08H_08H) \ __PMC_EV_ALIAS("EIST_TRANS", IAP_EVENT_3AH_00H) \ __PMC_EV_ALIAS("ESP.ADDITIONS", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("ESP.SYNCH", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("EXT_SNOOP", IAP_EVENT_77H) \ __PMC_EV_ALIAS("FP_ASSIST", IAP_EVENT_11H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.AR", IAP_EVENT_11H_81H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE", IAP_EVENT_10H_00H) \ __PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP", IAP_EVENT_CCH_02H) \ __PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("HW_INT_RCV", IAP_EVENT_C8H_00H) \ __PMC_EV_ALIAS("ICACHE.ACCESSES", IAP_EVENT_80H_03H) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("IDLE_DURING_DIV", IAP_EVENT_18H_00H) \ __PMC_EV_ALIAS("ILD_STALL", IAP_EVENT_87H_00H) \ __PMC_EV_ALIAS("INST_QUEUE.FULL", IAP_EVENT_83H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.LOADS", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.OTHER", IAP_EVENT_C0H_04H) \ __PMC_EV_ALIAS("INST_RETIRED.STORES", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("ITLB.FLUSH", IAP_EVENT_82H_04H) \ __PMC_EV_ALIAS("ITLB.LARGE_MISS", IAP_EVENT_82H_10H) \ __PMC_EV_ALIAS("ITLB.MISSES", IAP_EVENT_82H_02H) \ __PMC_EV_ALIAS("ITLB.SMALL_MISS", IAP_EVENT_82H_02H) \ __PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C9H_00H) \ __PMC_EV_ALIAS("L1D_ALL_CACHE_REF", IAP_EVENT_43H_02H) \ __PMC_EV_ALIAS("L1D_ALL_REF", IAP_EVENT_43H_01H) \ __PMC_EV_ALIAS("L1D_CACHE.LD", IAP_EVENT_40H_21H) \ __PMC_EV_ALIAS("L1D_CACHE.ST", IAP_EVENT_41H_22H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK", IAP_EVENT_42H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H) \ __PMC_EV_ALIAS("L1D_M_EVICT", IAP_EVENT_47H_00H) \ __PMC_EV_ALIAS("L1D_M_REPL", IAP_EVENT_46H_00H) \ __PMC_EV_ALIAS("L1D_PEND_MISS", IAP_EVENT_48H_00H) \ __PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_10H) \ __PMC_EV_ALIAS("L1D_REPL", IAP_EVENT_45H_0FH) \ __PMC_EV_ALIAS("L1D_SPLIT.LOADS", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("L1D_SPLIT.STORES", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("L1I_MISSES", IAP_EVENT_81H_00H) \ __PMC_EV_ALIAS("L1I_READS", IAP_EVENT_80H_00H) \ __PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ __PMC_EV_ALIAS("L2_DBUS_BUSY_RD", IAP_EVENT_23H) \ __PMC_EV_ALIAS("L2_IFETCH", IAP_EVENT_28H) \ __PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ __PMC_EV_ALIAS("L2_LINES_IN", IAP_EVENT_24H) \ __PMC_EV_ALIAS("L2_LINES_OUT", IAP_EVENT_26H) \ __PMC_EV_ALIAS("L2_LOCK", IAP_EVENT_2BH) \ __PMC_EV_ALIAS("L2_M_LINES_IN", IAP_EVENT_25H) \ __PMC_EV_ALIAS("L2_M_LINES_OUT", IAP_EVENT_27H) \ __PMC_EV_ALIAS("L2_NO_REQ", IAP_EVENT_32H) \ __PMC_EV_ALIAS("L2_REJECT_BUSQ", IAP_EVENT_30H) \ __PMC_EV_ALIAS("L2_RQSTS", IAP_EVENT_2EH) \ __PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ __PMC_EV_ALIAS("LOAD_BLOCK.L1D", IAP_EVENT_03H_20H) \ __PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STA", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_04H) \ __PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_00H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACRO_INSTS.ALL_DECODED", IAP_EVENT_AAH_03H) \ __PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_02H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET", IAP_EVENT_09H_01H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS", IAP_EVENT_09H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_04H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS", IAP_EVENT_CBH_08H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS", IAP_EVENT_CBH_02H) \ __PMC_EV_ALIAS("MUL", IAP_EVENT_12H_00H) \ __PMC_EV_ALIAS("MUL.AR", IAP_EVENT_12H_81H) \ __PMC_EV_ALIAS("MUL.S", IAP_EVENT_12H_01H) \ __PMC_EV_ALIAS("PAGE_WALKS.CYCLES", IAP_EVENT_0CH_03H) \ __PMC_EV_ALIAS("PAGE_WALKS.WALKS", IAP_EVENT_0CH_03H) \ __PMC_EV_ALIAS("PREFETCH.PREFETCHNTA", IAP_EVENT_07H_08H) \ __PMC_EV_ALIAS("PREFETCH.PREFETCHT0", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("PREFETCH.SW_L2", IAP_EVENT_07H_06H) \ __PMC_EV_ALIAS("PREF_RQSTS_DN", IAP_EVENT_F8H_00H) \ __PMC_EV_ALIAS("PREF_RQSTS_UP", IAP_EVENT_F0H_00H) \ __PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("RAT_STALLS.FPSW", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES", IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_DCH_1FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR", IAP_EVENT_DCH_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_DCH_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST", IAP_EVENT_DCH_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_DCH_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED", IAP_EVENT_A0H_00H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("SB_DRAIN_CYCLES", IAP_EVENT_04H_01H) \ __PMC_EV_ALIAS("SEGMENT_REG_LOADS.ANY", IAP_EVENT_06H_00H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.ANY", IAP_EVENT_D5H_0FH) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.DS", IAP_EVENT_D5H_02H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.ES", IAP_EVENT_D5H_01H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.FS", IAP_EVENT_D5H_04H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.GS", IAP_EVENT_D5H_08H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY", IAP_EVENT_D4H_0FH) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.DS", IAP_EVENT_D4H_02H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.ES", IAP_EVENT_D4H_01H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.FS", IAP_EVENT_D4H_04H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.GS", IAP_EVENT_D4H_08H) \ __PMC_EV_ALIAS("SIMD_ASSIST", IAP_EVENT_CDH_00H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", \ IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE", \ IAP_EVENT_CAH_01H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", \ IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", \ IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("SIMD_INSTR_RETIRED", IAP_EVENT_CEH_00H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY", IAP_EVENT_C7H_1FH) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR", IAP_EVENT_C7H_10H) \ __PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED", IAP_EVENT_CFH_00H) \ __PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.AR", IAP_EVENT_B1H_80H) \ __PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.S", IAP_EVENT_B1H_00H) \ __PMC_EV_ALIAS("SIMD_UOPS_EXEC.AR", IAP_EVENT_B0H_80H) \ __PMC_EV_ALIAS("SIMD_UOPS_EXEC.S", IAP_EVENT_B0H_00H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", IAP_EVENT_B3H_A0H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", IAP_EVENT_B3H_20H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.AR", IAP_EVENT_B3H_90H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.S", IAP_EVENT_B3H_10H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.AR", IAP_EVENT_B3H_81H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.S", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.AR", IAP_EVENT_B3H_84H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.S", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.AR", IAP_EVENT_B3H_82H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.S", IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.AR", IAP_EVENT_B3H_88H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.S", IAP_EVENT_B3H_08H) \ __PMC_EV_ALIAS("SNOOP_STALL_DRV", IAP_EVENT_7EH) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.L2", IAP_EVENT_07H_02H) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.STORES", IAP_EVENT_07H_03H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.L1", IAP_EVENT_4BH_01H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.L2", IAP_EVENT_4BH_02H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.NTA", IAP_EVENT_4BH_00H) \ __PMC_EV_ALIAS("STORE_BLOCK.ORDER", IAP_EVENT_04H_02H) \ __PMC_EV_ALIAS("STORE_BLOCK.SNOOP", IAP_EVENT_04H_08H) \ __PMC_EV_ALIAS("STORE_FORWARDS.GOOD", IAP_EVENT_02H_81H) \ __PMC_EV_ALIAS("THERMAL_TRIP", IAP_EVENT_3BH_C0H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_10H) \ __PMC_EV_ALIAS("UOPS_RETIRED.FUSED", IAP_EVENT_C2H_07H) \ __PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION", IAP_EVENT_C2H_04H) \ __PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED", IAP_EVENT_C2H_08H) \ __PMC_EV_ALIAS("UOPS_RETIRED.STD_STA", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.AR", IAP_EVENT_10H_81H) \ __PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.S", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("X87_OPS_RETIRED.ANY", IAP_EVENT_C1H_FEH) \ __PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH", IAP_EVENT_C1H_01H) /* * Aliases for Core PMC events. */ #define __PMC_EV_ALIAS_CORE() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("BAClears", IAP_EVENT_E6H_00H) \ __PMC_EV_ALIAS("BTB_Misses", IAP_EVENT_E2H_00H) \ __PMC_EV_ALIAS("Br_BAC_Missp_Exec", IAP_EVENT_8AH_00H) \ __PMC_EV_ALIAS("Br_Bogus", IAP_EVENT_E4H_00H) \ __PMC_EV_ALIAS("Br_Call_Exec", IAP_EVENT_92H_00H) \ __PMC_EV_ALIAS("Br_Call_Missp_Exec", IAP_EVENT_93H_00H) \ __PMC_EV_ALIAS("Br_Cnd_Exec", IAP_EVENT_8BH_00H) \ __PMC_EV_ALIAS("Br_Cnd_Missp_Exec", IAP_EVENT_8CH_00H) \ __PMC_EV_ALIAS("Br_Ind_Call_Exec", IAP_EVENT_94H_00H) \ __PMC_EV_ALIAS("Br_Ind_Exec", IAP_EVENT_8DH_00H) \ __PMC_EV_ALIAS("Br_Ind_Missp_Exec", IAP_EVENT_8EH_00H) \ __PMC_EV_ALIAS("Br_Inst_Exec", IAP_EVENT_88H_00H) \ __PMC_EV_ALIAS("Br_Instr_Decoded", IAP_EVENT_E0H_00H) \ __PMC_EV_ALIAS("Br_Instr_Ret", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("Br_MisPred_Ret", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("Br_MisPred_Taken_Ret", IAP_EVENT_CAH_00H) \ __PMC_EV_ALIAS("Br_Missp_Exec", IAP_EVENT_89H_00H) \ __PMC_EV_ALIAS("Br_Ret_BAC_Missp_Exec", IAP_EVENT_91H_00H) \ __PMC_EV_ALIAS("Br_Ret_Exec", IAP_EVENT_8FH_00H) \ __PMC_EV_ALIAS("Br_Ret_Missp_Exec", IAP_EVENT_90H_00H) \ __PMC_EV_ALIAS("Br_Taken_Ret", IAP_EVENT_C9H_00H) \ __PMC_EV_ALIAS("Bus_BNR_Clocks", IAP_EVENT_61H_00H) \ __PMC_EV_ALIAS("Bus_DRDY_Clocks", IAP_EVENT_62H_00H) \ __PMC_EV_ALIAS("Bus_Data_Rcv", IAP_EVENT_64H_40H) \ __PMC_EV_ALIAS("Bus_Locks_Clocks", IAP_EVENT_63H) \ __PMC_EV_ALIAS("Bus_Not_In_Use", IAP_EVENT_7DH) \ __PMC_EV_ALIAS("Bus_Req_Outstanding", IAP_EVENT_60H) \ __PMC_EV_ALIAS("Bus_Snoop_Stall", IAP_EVENT_7EH_00H) \ __PMC_EV_ALIAS("Bus_Snoops", IAP_EVENT_77H) \ __PMC_EV_ALIAS("Bus_Trans_Any", IAP_EVENT_70H) \ __PMC_EV_ALIAS("Bus_Trans_Brd", IAP_EVENT_65H) \ __PMC_EV_ALIAS("Bus_Trans_Burst", IAP_EVENT_6EH) \ __PMC_EV_ALIAS("Bus_Trans_Def", IAP_EVENT_6DH) \ __PMC_EV_ALIAS("Bus_Trans_IO", IAP_EVENT_6CH) \ __PMC_EV_ALIAS("Bus_Trans_Ifetch", IAP_EVENT_68H) \ __PMC_EV_ALIAS("Bus_Trans_Inval", IAP_EVENT_69H) \ __PMC_EV_ALIAS("Bus_Trans_Mem", IAP_EVENT_6FH) \ __PMC_EV_ALIAS("Bus_Trans_P", IAP_EVENT_6BH) \ __PMC_EV_ALIAS("Bus_Trans_Pwr", IAP_EVENT_6AH) \ __PMC_EV_ALIAS("Bus_Trans_RFO", IAP_EVENT_66H) \ __PMC_EV_ALIAS("Bus_Trans_WB", IAP_EVENT_67H) \ __PMC_EV_ALIAS("Cycles_Div_Busy", IAP_EVENT_14H_00H) \ __PMC_EV_ALIAS("Cycles_Int_Masked", IAP_EVENT_C6H_00H) \ __PMC_EV_ALIAS("Cycles_Int_Pending_Masked", IAP_EVENT_C7H_00H) \ __PMC_EV_ALIAS("DCU_Snoop_To_Share", IAP_EVENT_78H) \ __PMC_EV_ALIAS("DCache_Cache_LD", IAP_EVENT_40H) \ __PMC_EV_ALIAS("DCache_Cache_Lock", IAP_EVENT_42H) \ __PMC_EV_ALIAS("DCache_Cache_ST", IAP_EVENT_41H) \ __PMC_EV_ALIAS("DCache_M_Evict", IAP_EVENT_47H_00H) \ __PMC_EV_ALIAS("DCache_M_Repl", IAP_EVENT_46H_00H) \ __PMC_EV_ALIAS("DCache_Pend_Miss", IAP_EVENT_48H_00H) \ __PMC_EV_ALIAS("DCache_Repl", IAP_EVENT_45H_0FH) \ __PMC_EV_ALIAS("Data_Mem_Cache_Ref", IAP_EVENT_44H_02H) \ __PMC_EV_ALIAS("Data_Mem_Ref", IAP_EVENT_43H_01H) \ __PMC_EV_ALIAS("Dbus_Busy", IAP_EVENT_22H) \ __PMC_EV_ALIAS("Dbus_Busy_Rd", IAP_EVENT_23H) \ __PMC_EV_ALIAS("Div", IAP_EVENT_13H_00H) \ __PMC_EV_ALIAS("Dtlb_Miss", IAP_EVENT_49H_00H) \ __PMC_EV_ALIAS("ESP_Uops", IAP_EVENT_D7H_00H) \ __PMC_EV_ALIAS("EST_Trans", IAP_EVENT_3AH) \ __PMC_EV_ALIAS("FP_Assist", IAP_EVENT_11H_00H) \ __PMC_EV_ALIAS("FP_Comp_Instr_Ret", IAP_EVENT_C1H_00H) \ __PMC_EV_ALIAS("FP_Comps_Op_Exe", IAP_EVENT_10H_00H) \ __PMC_EV_ALIAS("FP_MMX_Trans", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("Fused_Ld_Uops_Ret", IAP_EVENT_DAH_01H) \ __PMC_EV_ALIAS("Fused_St_Uops_Ret", IAP_EVENT_DAH_02H) \ __PMC_EV_ALIAS("Fused_Uops_Ret", IAP_EVENT_DAH_00H) \ __PMC_EV_ALIAS("HW_Int_Rx", IAP_EVENT_C8H_00H) \ __PMC_EV_ALIAS("ICache_Misses", IAP_EVENT_81H_00H) \ __PMC_EV_ALIAS("ICache_Reads", IAP_EVENT_80H_00H) \ __PMC_EV_ALIAS("IFU_Mem_Stall", IAP_EVENT_86H_00H) \ __PMC_EV_ALIAS("ILD_Stall", IAP_EVENT_87H_00H) \ __PMC_EV_ALIAS("ITLB_Misses", IAP_EVENT_85H_00H) \ __PMC_EV_ALIAS("Instr_Decoded", IAP_EVENT_D0H_00H) \ __PMC_EV_ALIAS("Instr_Ret", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("L1_Pref_Req", IAP_EVENT_4FH_00H) \ __PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ __PMC_EV_ALIAS("L2_IFetch", IAP_EVENT_28H) \ __PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ __PMC_EV_ALIAS("L2_Lines_In", IAP_EVENT_24H) \ __PMC_EV_ALIAS("L2_Lines_Out", IAP_EVENT_26H) \ __PMC_EV_ALIAS("L2_M_Lines_In", IAP_EVENT_25H) \ __PMC_EV_ALIAS("L2_M_Lines_Out", IAP_EVENT_27H) \ __PMC_EV_ALIAS("L2_No_Request_Cycles", IAP_EVENT_32H) \ __PMC_EV_ALIAS("L2_Reject_Cycles", IAP_EVENT_30H) \ __PMC_EV_ALIAS("L2_Rqsts", IAP_EVENT_2EH) \ __PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ __PMC_EV_ALIAS("LD_Blocks", IAP_EVENT_03H_00H) \ __PMC_EV_ALIAS("LLC_Misses", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("LLC_Reference", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("MMX_Assist", IAP_EVENT_CDH_00H) \ __PMC_EV_ALIAS("MMX_FP_Trans", IAP_EVENT_CCH_00H) \ __PMC_EV_ALIAS("MMX_Instr_Exec", IAP_EVENT_B0H_00H) \ __PMC_EV_ALIAS("MMX_Instr_Ret", IAP_EVENT_CEH_00H) \ __PMC_EV_ALIAS("Misalign_Mem_Ref", IAP_EVENT_05H_00H) \ __PMC_EV_ALIAS("Mul", IAP_EVENT_12H_00H) \ __PMC_EV_ALIAS("NonHlt_Ref_Cycles", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("Pref_Rqsts_Dn", IAP_EVENT_F8H_00H) \ __PMC_EV_ALIAS("Pref_Rqsts_Up", IAP_EVENT_F0H_00H) \ __PMC_EV_ALIAS("Resource_Stall", IAP_EVENT_A2H_00H) \ __PMC_EV_ALIAS("SD_Drains", IAP_EVENT_04H_00H) \ __PMC_EV_ALIAS("SIMD_FP_DP_P_Comp_Ret", IAP_EVENT_D9H_02H) \ __PMC_EV_ALIAS("SIMD_FP_DP_P_Ret", IAP_EVENT_D8H_02H) \ __PMC_EV_ALIAS("SIMD_FP_DP_S_Comp_Ret", IAP_EVENT_D9H_03H) \ __PMC_EV_ALIAS("SIMD_FP_DP_S_Ret", IAP_EVENT_D8H_03H) \ __PMC_EV_ALIAS("SIMD_FP_SP_P_Comp_Ret", IAP_EVENT_D9H_00H) \ __PMC_EV_ALIAS("SIMD_FP_SP_Ret", IAP_EVENT_D8H_00H) \ __PMC_EV_ALIAS("SIMD_FP_SP_S_Comp_Ret", IAP_EVENT_D9H_01H) \ __PMC_EV_ALIAS("SIMD_FP_SP_S_Ret", IAP_EVENT_D8H_01H) \ __PMC_EV_ALIAS("SIMD_Int_128_Ret", IAP_EVENT_D8H_04H) \ __PMC_EV_ALIAS("SIMD_Int_Pari_Exec", IAP_EVENT_B3H_20H) \ __PMC_EV_ALIAS("SIMD_Int_Pck_Exec", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("SIMD_Int_Plog_Exec", IAP_EVENT_B3H_10H) \ __PMC_EV_ALIAS("SIMD_Int_Pmul_Exec", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SIMD_Int_Psft_Exec", IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SIMD_Int_Sat_Exec", IAP_EVENT_B1H_00H) \ __PMC_EV_ALIAS("SIMD_Int_Upck_Exec", IAP_EVENT_B3H_08H) \ __PMC_EV_ALIAS("SMC_Detected", IAP_EVENT_C3H_00H) \ __PMC_EV_ALIAS("SSE_NTStores_Miss", IAP_EVENT_4BH_03H) \ __PMC_EV_ALIAS("SSE_NTStores_Ret", IAP_EVENT_07H_03H) \ __PMC_EV_ALIAS("SSE_PrefNta_Miss", IAP_EVENT_4BH_00H) \ __PMC_EV_ALIAS("SSE_PrefNta_Ret", IAP_EVENT_07H_00H) \ __PMC_EV_ALIAS("SSE_PrefT1_Miss", IAP_EVENT_4BH_01H) \ __PMC_EV_ALIAS("SSE_PrefT1_Ret", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("SSE_PrefT2_Miss", IAP_EVENT_4BH_02H) \ __PMC_EV_ALIAS("SSE_PrefT2_Ret", IAP_EVENT_07H_02H) \ __PMC_EV_ALIAS("Seg_Reg_Loads", IAP_EVENT_06H_00H) \ __PMC_EV_ALIAS("Serial_Execution_Cycles", IAP_EVENT_3CH_02H) \ __PMC_EV_ALIAS("Thermal_Trip", IAP_EVENT_3BH_C0H) \ __PMC_EV_ALIAS("Unfusion", IAP_EVENT_DBH_00H) \ __PMC_EV_ALIAS("Unhalted_Core_Cycles", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("Uops_Ret", IAP_EVENT_C2H_00H) /* * Aliases for Core2 PMC events. */ #define __PMC_EV_ALIAS_CORE2() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("BACLEARS", IAP_EVENT_E6H_00H) \ __PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_00H) \ __PMC_EV_ALIAS("BR_BAC_MISSP_EXEC", IAP_EVENT_8AH_00H) \ __PMC_EV_ALIAS("BR_CALL_EXEC", IAP_EVENT_92H_00H) \ __PMC_EV_ALIAS("BR_CALL_MISSP_EXEC", IAP_EVENT_93H_00H) \ __PMC_EV_ALIAS("BR_CND_EXEC", IAP_EVENT_8BH_00H) \ __PMC_EV_ALIAS("BR_CND_MISSP_EXEC", IAP_EVENT_8CH_00H) \ __PMC_EV_ALIAS("BR_IND_CALL_EXEC", IAP_EVENT_94H_00H) \ __PMC_EV_ALIAS("BR_IND_EXEC", IAP_EVENT_8DH_00H) \ __PMC_EV_ALIAS("BR_IND_MISSP_EXEC", IAP_EVENT_8EH_00H) \ __PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_00H) \ __PMC_EV_ALIAS("BR_INST_EXEC", IAP_EVENT_88H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ANY", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN", \ IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN", \ IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN", \ IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN", \ IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN", IAP_EVENT_C4H_0CH) \ __PMC_EV_ALIAS("BR_MISSP_EXEC", IAP_EVENT_89H_00H) \ __PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC", IAP_EVENT_91H_00H) \ __PMC_EV_ALIAS("BR_RET_EXEC", IAP_EVENT_8FH_00H) \ __PMC_EV_ALIAS("BR_RET_MISSP_EXEC", IAP_EVENT_90H_00H) \ __PMC_EV_ALIAS("BR_TKN_BUBBLE_1", IAP_EVENT_97H_00H) \ __PMC_EV_ALIAS("BR_TKN_BUBBLE_2", IAP_EVENT_98H_00H) \ __PMC_EV_ALIAS("BUSQ_EMPTY", IAP_EVENT_7DH) \ __PMC_EV_ALIAS("BUS_BNR_DRV", IAP_EVENT_61H) \ __PMC_EV_ALIAS("BUS_DATA_RCV", IAP_EVENT_64H) \ __PMC_EV_ALIAS("BUS_DRDY_CLOCKS", IAP_EVENT_62H) \ __PMC_EV_ALIAS("BUS_HITM_DRV", IAP_EVENT_7BH) \ __PMC_EV_ALIAS("BUS_HIT_DRV", IAP_EVENT_7AH) \ __PMC_EV_ALIAS("BUS_IO_WAIT", IAP_EVENT_7FH) \ __PMC_EV_ALIAS("BUS_LOCK_CLOCKS", IAP_EVENT_63H) \ __PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING", \ IAP_EVENT_60H) \ __PMC_EV_ALIAS("BUS_TRANS_ANY", IAP_EVENT_70H) \ __PMC_EV_ALIAS("BUS_TRANS_BRD", IAP_EVENT_65H) \ __PMC_EV_ALIAS("BUS_TRANS_BURST", IAP_EVENT_6EH) \ __PMC_EV_ALIAS("BUS_TRANS_DEF", IAP_EVENT_6DH) \ __PMC_EV_ALIAS("BUS_TRANS_IFETCH", IAP_EVENT_68H) \ __PMC_EV_ALIAS("BUS_TRANS_INVAL", IAP_EVENT_69H) \ __PMC_EV_ALIAS("BUS_TRANS_IO", IAP_EVENT_6CH) \ __PMC_EV_ALIAS("BUS_TRANS_MEM", IAP_EVENT_6FH) \ __PMC_EV_ALIAS("BUS_TRANS_P", IAP_EVENT_6BH) \ __PMC_EV_ALIAS("BUS_TRANS_PWR", IAP_EVENT_6AH) \ __PMC_EV_ALIAS("BUS_TRANS_RFO", IAP_EVENT_66H) \ __PMC_EV_ALIAS("BUS_TRANS_WB", IAP_EVENT_67H) \ __PMC_EV_ALIAS("CMP_SNOOP", IAP_EVENT_78H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", \ IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER", \ IAP_EVENT_3CH_02H) \ __PMC_EV_ALIAS("CYCLES_DIV_BUSY", IAP_EVENT_14H_00H) \ __PMC_EV_ALIAS("CYCLES_INT_MASKED", IAP_EVENT_C6H_01H) \ __PMC_EV_ALIAS("CYCLES_INT_PENDING_AND_MASKED", \ IAP_EVENT_C6H_02H) \ __PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.FP", IAP_EVENT_19H_00H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.LOAD", IAP_EVENT_19H_01H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.SIMD", IAP_EVENT_19H_02H) \ __PMC_EV_ALIAS("DIV", IAP_EVENT_13H_00H) \ __PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_MISSES.MISS_LD", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.MISS_ST", IAP_EVENT_08H_08H) \ __PMC_EV_ALIAS("EIST_TRANS", IAP_EVENT_3AH_00H) \ __PMC_EV_ALIAS("ESP.ADDITIONS", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("ESP.SYNCH", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("EXT_SNOOP", IAP_EVENT_77H) \ __PMC_EV_ALIAS("FP_ASSIST", IAP_EVENT_11H_00H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE", IAP_EVENT_10H_00H) \ __PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP", IAP_EVENT_CCH_02H) \ __PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("HW_INT_RCV", IAP_EVENT_C8H_00H) \ __PMC_EV_ALIAS("IDLE_DURING_DIV", IAP_EVENT_18H_00H) \ __PMC_EV_ALIAS("ILD_STALL", IAP_EVENT_87H_00H) \ __PMC_EV_ALIAS("INST_QUEUE.FULL", IAP_EVENT_83H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.LOADS", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.OTHER", IAP_EVENT_C0H_04H) \ __PMC_EV_ALIAS("INST_RETIRED.STORES", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.VM_H", IAP_EVENT_C0H_08H) \ __PMC_EV_ALIAS("ITLB.FLUSH", IAP_EVENT_82H_40H) \ __PMC_EV_ALIAS("ITLB.LARGE_MISS", IAP_EVENT_82H_10H) \ __PMC_EV_ALIAS("ITLB.MISSES", IAP_EVENT_82H_12H) \ __PMC_EV_ALIAS("ITLB.SMALL_MISS", IAP_EVENT_82H_02H) \ __PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C9H_00H) \ __PMC_EV_ALIAS("L1D_ALL_CACHE_REF", IAP_EVENT_43H_02H) \ __PMC_EV_ALIAS("L1D_ALL_REF", IAP_EVENT_43H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LD", IAP_EVENT_40H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK", IAP_EVENT_42H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H) \ __PMC_EV_ALIAS("L1D_CACHE_ST", IAP_EVENT_41H) \ __PMC_EV_ALIAS("L1D_M_EVICT", IAP_EVENT_47H_00H) \ __PMC_EV_ALIAS("L1D_M_REPL", IAP_EVENT_46H_00H) \ __PMC_EV_ALIAS("L1D_PEND_MISS", IAP_EVENT_48H_00H) \ __PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_10H) \ __PMC_EV_ALIAS("L1D_REPL", IAP_EVENT_45H_0FH) \ __PMC_EV_ALIAS("L1D_SPLIT.LOADS", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("L1D_SPLIT.STORES", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("L1I_MISSES", IAP_EVENT_81H_00H) \ __PMC_EV_ALIAS("L1I_READS", IAP_EVENT_80H_00H) \ __PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ __PMC_EV_ALIAS("L2_DBUS_BUSY_RD", IAP_EVENT_23H) \ __PMC_EV_ALIAS("L2_IFETCH", IAP_EVENT_28H) \ __PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ __PMC_EV_ALIAS("L2_LINES_IN", IAP_EVENT_24H) \ __PMC_EV_ALIAS("L2_LINES_OUT", IAP_EVENT_26H) \ __PMC_EV_ALIAS("L2_LOCK", IAP_EVENT_2BH) \ __PMC_EV_ALIAS("L2_M_LINES_IN", IAP_EVENT_25H) \ __PMC_EV_ALIAS("L2_M_LINES_OUT", IAP_EVENT_27H) \ __PMC_EV_ALIAS("L2_NO_REQ", IAP_EVENT_32H) \ __PMC_EV_ALIAS("L2_REJECT_BUSQ", IAP_EVENT_30H) \ __PMC_EV_ALIAS("L2_RQSTS", IAP_EVENT_2EH) \ __PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE", \ IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI", \ IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ __PMC_EV_ALIAS("LOAD_BLOCK.L1D", IAP_EVENT_03H_20H) \ __PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", \ IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STA", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_04H) \ __PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_00H) \ __PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_NUKES.SMC", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_08H) \ __PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_AAH_01H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET", \ IAP_EVENT_09H_01H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS", \ IAP_EVENT_09H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", \ IAP_EVENT_CBH_10H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_LINE_MISS", \ IAP_EVENT_CBH_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_MISS", \ IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS", \ IAP_EVENT_CBH_08H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS", \ IAP_EVENT_CBH_04H) \ __PMC_EV_ALIAS("MUL", IAP_EVENT_12H_00H) \ __PMC_EV_ALIAS("PAGE_WALKS.COUNT", IAP_EVENT_0CH_01H) \ __PMC_EV_ALIAS("PAGE_WALKS.CYCLES", IAP_EVENT_0CH_02H) \ __PMC_EV_ALIAS("PREF_RQSTS_DN", IAP_EVENT_F8H_00H) \ __PMC_EV_ALIAS("PREF_RQSTS_UP", IAP_EVENT_F0H_00H) \ __PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("RAT_STALLS.FPSW", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.OTHER_SERIALIZATION_STALLS", \ IAP_EVENT_D2H_10H) \ __PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES", \ IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", \ IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_DCH_1FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR", \ IAP_EVENT_DCH_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_DCH_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST", IAP_EVENT_DCH_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", \ IAP_EVENT_DCH_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED", IAP_EVENT_A0H_00H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("SB_DRAIN_CYCLES", IAP_EVENT_04H_01H) \ __PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_06H_00H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.ANY", IAP_EVENT_D5H_0FH) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.DS", IAP_EVENT_D5H_02H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.ES", IAP_EVENT_D5H_01H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.FS", IAP_EVENT_D5H_04H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.GS", IAP_EVENT_D5H_08H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY", IAP_EVENT_D4H_0FH) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.DS", IAP_EVENT_D4H_02H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.ES", IAP_EVENT_D4H_01H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.FS", IAP_EVENT_D4H_04H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.GS", IAP_EVENT_D4H_08H) \ __PMC_EV_ALIAS("SIMD_ASSIST", IAP_EVENT_CDH_00H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", \ IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE", \ IAP_EVENT_CAH_01H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", \ IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", \ IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("SIMD_INSTR_RETIRED", IAP_EVENT_CEH_00H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY", IAP_EVENT_C7H_1FH) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", \ IAP_EVENT_C7H_04H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", \ IAP_EVENT_C7H_01H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", \ IAP_EVENT_C7H_08H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", \ IAP_EVENT_C7H_02H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR", IAP_EVENT_C7H_10H) \ __PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED", IAP_EVENT_CFH_00H) \ __PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC", IAP_EVENT_B1H_00H) \ __PMC_EV_ALIAS("SIMD_UOPS_EXEC", IAP_EVENT_B0H_00H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC", IAP_EVENT_B3H_20H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL", IAP_EVENT_B3H_10H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT", IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK", IAP_EVENT_B3H_08H) \ __PMC_EV_ALIAS("SNOOP_STALL_DRV", IAP_EVENT_7EH) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.L1", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.L2", IAP_EVENT_07H_02H) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.NTA", IAP_EVENT_07H_00H) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.STORES", IAP_EVENT_07H_03H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.L1", IAP_EVENT_4BH_01H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.L2", IAP_EVENT_4BH_02H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.NTA", IAP_EVENT_4BH_00H) \ __PMC_EV_ALIAS("STORE_BLOCK.ORDER", IAP_EVENT_04H_02H) \ __PMC_EV_ALIAS("STORE_BLOCK.SNOOP", IAP_EVENT_04H_08H) \ __PMC_EV_ALIAS("THERMAL_TRIP", IAP_EVENT_3BH_C0H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_0FH) \ __PMC_EV_ALIAS("UOPS_RETIRED.FUSED", IAP_EVENT_C2H_07H) \ __PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION", IAP_EVENT_C2H_04H) \ __PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED", IAP_EVENT_C2H_08H) \ __PMC_EV_ALIAS("UOPS_RETIRED.STD_STA", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("X87_OPS_RETIRED.ANY", IAP_EVENT_C1H_FEH) \ __PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH", IAP_EVENT_C1H_01H) /* * Core i7 and Xeon 5500 events removed between 253669-031US June 2009 * and 253669-040US October 2011. */ #define __PMC_EV_ALIAS_COREI7_OLD() \ __PMC_EV_ALIAS("SB_FORWARD.ANY", IAP_EVENT_02H_01H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_01H) \ __PMC_EV_ALIAS("LOAD_BLOCK.ADDRESS_OFFSET", IAP_EVENT_03H_04H) \ __PMC_EV_ALIAS("SB_DRAIN.CYCLES", IAP_EVENT_04H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOAD", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORE", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.ANY", IAP_EVENT_05H_03H) \ __PMC_EV_ALIAS("STORE_BLOCKS.NOT_STA", IAP_EVENT_06H_01H) \ __PMC_EV_ALIAS("STORE_BLOCKS.STA", IAP_EVENT_06H_02H) \ __PMC_EV_ALIAS("STORE_BLOCKS.ANY", IAP_EVENT_06H_0FH) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDP_MISS", IAP_EVENT_08H_40H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.RESET", IAP_EVENT_09H_01H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.SUCCESS", IAP_EVENT_09H_02H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCHDOG", IAP_EVENT_09H_04H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCH_CYCLES", IAP_EVENT_09H_08H)\ __PMC_EV_ALIAS("HW_INT.RCV", IAP_EVENT_1DH_01H) \ __PMC_EV_ALIAS("HW_INT.CYCLES_MASKED", IAP_EVENT_1DH_02H) \ __PMC_EV_ALIAS("HW_INT.CYCLES_PENDING_AND_MASKED", IAP_EVENT_1DH_04H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.E_STATE", IAP_EVENT_27H_04H) \ __PMC_EV_ALIAS("UOPS_DECODED.DEC0", IAP_EVENT_3DH_01H) \ __PMC_EV_ALIAS("L1D_CACHE_ST.I_STATE", IAP_EVENT_41H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_ST.MESI", IAP_EVENT_41H_0FH) \ __PMC_EV_ALIAS("L1D_PEND_MISS.LOAD_BUFFERS_FULL", IAP_EVENT_48H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.PDP_MISS", IAP_EVENT_49H_40H) \ __PMC_EV_ALIAS("SSE_MEM_EXEC.NTA", IAP_EVENT_4BH_01H) \ __PMC_EV_ALIAS("SSE_MEM_EXEC.STREAMING_STORES", IAP_EVENT_4BH_08H) \ __PMC_EV_ALIAS("SFENCE_CYCLES", IAP_EVENT_4DH_01H) \ __PMC_EV_ALIAS("EPT.EPDE_MISS", IAP_EVENT_4FH_02H) \ __PMC_EV_ALIAS("EPT.EPDPE_HIT", IAP_EVENT_4FH_04H) \ __PMC_EV_ALIAS("EPT.EPDPE_MISS", IAP_EVENT_4FH_08H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", \ IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("IFU_IVC.FULL", IAP_EVENT_81H_01H) \ __PMC_EV_ALIAS("IFU_IVC.L1I_EVICTION", IAP_EVENT_81H_02H) \ __PMC_EV_ALIAS("L1I_OPPORTUNISTIC_HITS", IAP_EVENT_83H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.PMH_BUSY_CYCLES", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ITLB_MISSES.PDE_MISS", IAP_EVENT_85H_20H) \ __PMC_EV_ALIAS("ITLB_MISSES.PDP_MISS", IAP_EVENT_85H_40H) \ __PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.UNCACHED_MEM", IAP_EVENT_B0H_20H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", \ IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("PIC_ACCESSES.TPR_READS", IAP_EVENT_BAH_01H) \ __PMC_EV_ALIAS("PIC_ACCESSES.TPR_WRITES", IAP_EVENT_BAH_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.FUSION_ASSIST", IAP_EVENT_C3H_10H) \ __PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_01H) \ __PMC_EV_ALIAS("BPU_CLEARS.ANY", IAP_EVENT_E8H_03H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.HIT", IAP_EVENT_F3H_01H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.ALLOC", IAP_EVENT_F3H_02H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.DATA_TRIGGER", IAP_EVENT_F3H_04H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.CODE_TRIGGER", IAP_EVENT_F3H_08H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.DCA_TRIGGER", IAP_EVENT_F3H_10H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.KICK_START", IAP_EVENT_F3H_20H) \ __PMC_EV_ALIAS("SQ_MISC.PROMOTION", IAP_EVENT_F4H_01H) \ __PMC_EV_ALIAS("SQ_MISC.PROMOTION_POST_GO", IAP_EVENT_F4H_02H) \ __PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H) \ __PMC_EV_ALIAS("SQ_MISC.FILL_DROPPED", IAP_EVENT_F4H_08H) \ __PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_F8H_01H) /* * Aliases for Core i7 and Xeon 5500 PMC events (253669-033US December 2009) */ #define __PMC_EV_ALIAS_COREI7() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H) \ __PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H) \ __PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H) \ __PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", \ IAP_EVENT_08H_80H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD", \ IAP_EVENT_0BH_10H) \ __PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN", \ IAP_EVENT_0FH_01H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", \ IAP_EVENT_0FH_02H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", \ IAP_EVENT_0FH_08H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", \ IAP_EVENT_0FH_10H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_20H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", \ IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", \ IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H) \ __PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H) \ __PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H) \ __PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H) \ __PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H) \ __PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H) \ __PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H) \ __PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H) \ __PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H) \ __PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH) \ __PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH) \ __PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH) \ __PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H) \ __PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H) \ __PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H) \ __PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH) \ __PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.I_STATE", IAP_EVENT_40H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.S_STATE", IAP_EVENT_40H_02H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.E_STATE", IAP_EVENT_40H_04H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.M_STATE", IAP_EVENT_40H_08H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.MESI", IAP_EVENT_40H_0FH) \ __PMC_EV_ALIAS("L1D_CACHE_ST.S_STATE", IAP_EVENT_41H_02H) \ __PMC_EV_ALIAS("L1D_CACHE_ST.E_STATE", IAP_EVENT_41H_04H) \ __PMC_EV_ALIAS("L1D_CACHE_ST.M_STATE", IAP_EVENT_41H_08H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK.HIT", IAP_EVENT_42H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK.S_STATE", IAP_EVENT_42H_02H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK.E_STATE", IAP_EVENT_42H_04H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK.M_STATE", IAP_EVENT_42H_08H) \ __PMC_EV_ALIAS("L1D_ALL_REF.ANY", IAP_EVENT_43H_01H) \ __PMC_EV_ALIAS("L1D_ALL_REF.CACHEABLE", IAP_EVENT_43H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("DTLB_MISSES.PDE_MISS", IAP_EVENT_49H_20H) \ __PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H) \ __PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H) \ __PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H) \ __PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H) \ __PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H) \ __PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H) \ __PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H) \ __PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H) \ __PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H) \ __PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H) \ __PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H) \ __PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ __PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H) \ __PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH) \ __PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H) \ __PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H) \ __PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH) \ __PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ __PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H) \ __PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", \ IAP_EVENT_B1H_1FH) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H) \ __PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", \ IAP_EVENT_CBH_08H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H) \ __PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H) \ __PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H) \ __PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H) \ __PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ __PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H) \ __PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H) \ __PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H) \ __PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H) \ __PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H) \ __PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH) \ __PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \ __PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H) \ __PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H) \ __PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \ __PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H) \ __PMC_EV_ALIAS_COREI7_OLD() /* * Aliases for Westmere PMC events (253669-033US December 2009) */ #define __PMC_EV_ALIAS_WESTMERE() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H) \ __PMC_EV_ALIAS("MISALIGN_MEMORY.STORE", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H) \ __PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H) \ __PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_CYCLES", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD", \ IAP_EVENT_0BH_10H) \ __PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_HITM", IAP_EVENT_0FH_02H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", \ IAP_EVENT_0FH_08H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_10H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", IAP_EVENT_0FH_20H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", \ IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", \ IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H) \ __PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H) \ __PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H) \ __PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H) \ __PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H) \ __PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H) \ __PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H) \ __PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H) \ __PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H) \ __PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH) \ __PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH) \ __PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH) \ __PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H) \ __PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H) \ __PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H) \ __PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH) \ __PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_02H) \ __PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_01H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.WALK_CYCLES", IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H) \ __PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H) \ __PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H) \ __PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \ __PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H) \ __PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H) \ __PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H) \ __PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", \ IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H) \ __PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H) \ __PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H) \ __PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H) \ __PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ __PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H) \ __PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH) \ __PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H) \ __PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H) \ __PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH) \ __PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ __PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H) \ __PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", \ IAP_EVENT_B1H_1FH) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", \ IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS.CODE", IAP_EVENT_B4H_01H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS.DATA", IAP_EVENT_B4H_02H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS.INVALIDATE", IAP_EVENT_B4H_04H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ANY_P", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ANY_P", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H) \ __PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", \ IAP_EVENT_CBH_08H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H) \ __PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("UOPS_DECODED.STALL_CYCLES", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H) \ __PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H) \ __PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H) \ __PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ __PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H) \ __PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H) \ __PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H) \ __PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H) \ __PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H) \ __PMC_EV_ALIAS("THREAD_ACTIVE", IAP_EVENT_ECH_01H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H) \ __PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH) \ __PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H) \ __PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \ __PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H) \ __PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H) \ __PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \ __PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H) #define __PMC_EV_ALIAS_IVYBRIDGE() \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK", IAP_EVENT_08H_81H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED", IAP_EVENT_08H_82H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION", IAP_EVENT_08H_84H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ __PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ __PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", IAP_EVENT_58H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", IAP_EVENT_58H_02H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_04H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_ELIMINATED", IAP_EVENT_58H_08H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ __PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ __PMC_EV_ALIAS("TLB_ACCESS.LOAD_STLB_HIT", IAP_EVENT_5FH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ __PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ __PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ __PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ __PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ __PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_4_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ __PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_88H_04H) \ __PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ __PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ __PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_89H_04H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ __PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ __PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ __PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", IAP_EVENT_D3H_01H) \ __PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ __PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) /* * Aliases for Sandy Bridge PMC events (253669-039US May 2011) */ #define __PMC_EV_ALIAS_SANDYBRIDGE() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H) \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ __PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ __PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("LOAD_HIT_PER.HW_PF", IAP_EVENT_4CH_02H) \ __PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H) \ __PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H) \ __PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H) \ __PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH) \ __PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ __PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", IAP_EVENT_60H_01H)\ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ __PMC_EV_ALIAS("IQD.MITE_UOPS", IAP_EVENT_79H_04H) \ __PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ __PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ __PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ __PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ __PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_88H_04H) \ __PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ __PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ __PMC_EV_ALIAS("BR_INST_EXE.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ __PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_89H_04H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ __PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H) \ __PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ __PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH) \ __PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \ __PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ __PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ __PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED_ALL", IAP_EVENT_D0H_80H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS", IAP_EVENT_D4H_02H) \ __PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANS.RF0", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ __PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES-IN.ALL", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) \ __PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) +/* + * Aliases for Sandy Bridge Xeon PMC events (253669-044US August 2012) + */ +#define __PMC_EV_ALIAS_SANDYBRIDGE_XEON() \ +__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ +__PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H) \ +__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ +__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ +__PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H) \ +__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ +__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ +__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ +__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ +__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ +__PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H) \ +__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ +__PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ +__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", IAP_EVENT_10H_10H) \ +__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", IAP_EVENT_10H_20H) \ +__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ +__PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ +__PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ +__PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ +__PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ +__PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H) \ +__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ +__PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ +__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ +__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ +__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ +__PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ +__PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ +__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ +__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H) \ +__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ +__PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ +__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \ +__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_S", IAP_EVENT_28H_02H) \ +__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ +__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ +__PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \ +__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ +__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ +__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ +__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ +__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_49H_01H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ +__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ +__PMC_EV_ALIAS("LOAD_HIT_PER.HW_PF", IAP_EVENT_4CH_02H) \ +__PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H) \ +__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ +__PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H) \ +__PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H) \ +__PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H) \ +__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H) \ +__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H) \ +__PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH) \ +__PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH) \ +__PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH) \ +__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ +__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ +__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", IAP_EVENT_60H_01H)\ +__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", IAP_EVENT_60H_04H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", IAP_EVENT_60H_08H) \ +__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", IAP_EVENT_63H_01H) \ +__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ +__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ +__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ +__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ +__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ +__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ +__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ +__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ +__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ +__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ +__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ +__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ +__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ +__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_88H_04H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ +__PMC_EV_ALIAS("BR_INST_EXE.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_89H_04H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ +__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_02H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ +__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ +__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_02H) \ +__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", IAP_EVENT_A3H_04H) \ +__PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ +__PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ +__PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H) \ +__PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ +__PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH) \ +__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H) \ +__PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \ +__PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H) \ +__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ +__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ +__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ +__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ +__PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H) \ +__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ +__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ +__PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H) \ +__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ +__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ +__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ +__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ +__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ +__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ +__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ +__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ +__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ +__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ +__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ +__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ +__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ +__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ +__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ +__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED_ALL", IAP_EVENT_D0H_80H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", IAP_EVENT_D3H_01H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", IAP_EVENT_D3H_04H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", IAP_EVENT_D4H_02H) \ +__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_01H) \ +__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ +__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ +__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ +__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ +__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ +__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ +__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ +__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ +__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ +__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ +__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ +__PMC_EV_ALIAS("L2_LINES-IN.ALL", IAP_EVENT_F1H_07H) \ +__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ +__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ +__PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ +__PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \ +__PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) \ +__PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) /* timestamp counters. */ #define __PMC_EV_TSC() \ __PMC_EV(TSC, TSC) #define PMC_EV_TSC_FIRST PMC_EV_TSC_TSC #define PMC_EV_TSC_LAST PMC_EV_TSC_TSC /* * Software events are dynamicaly defined. */ #define PMC_EV_DYN_COUNT 0x1000 #define PMC_EV_SOFT_FIRST 0x20000 #define PMC_EV_SOFT_LAST (PMC_EV_SOFT_FIRST + PMC_EV_DYN_COUNT - 1) #define __PMC_EV_UCF() \ __PMC_EV(UCF, UCLOCK) #define PMC_EV_UCF_FIRST PMC_EV_UCF_UCLOCK #define PMC_EV_UCF_LAST PMC_EV_UCF_UCLOCK #define __PMC_EV_UCP() \ __PMC_EV(UCP, EVENT_00H_01H) \ __PMC_EV(UCP, EVENT_00H_02H) \ __PMC_EV(UCP, EVENT_00H_04H) \ __PMC_EV(UCP, EVENT_01H_01H) \ __PMC_EV(UCP, EVENT_01H_02H) \ __PMC_EV(UCP, EVENT_01H_04H) \ __PMC_EV(UCP, EVENT_02H_01H) \ __PMC_EV(UCP, EVENT_03H_01H) \ __PMC_EV(UCP, EVENT_03H_02H) \ __PMC_EV(UCP, EVENT_03H_04H) \ __PMC_EV(UCP, EVENT_03H_08H) \ __PMC_EV(UCP, EVENT_03H_10H) \ __PMC_EV(UCP, EVENT_03H_20H) \ __PMC_EV(UCP, EVENT_03H_40H) \ __PMC_EV(UCP, EVENT_04H_01H) \ __PMC_EV(UCP, EVENT_04H_02H) \ __PMC_EV(UCP, EVENT_04H_04H) \ __PMC_EV(UCP, EVENT_04H_08H) \ __PMC_EV(UCP, EVENT_04H_10H) \ __PMC_EV(UCP, EVENT_05H_01H) \ __PMC_EV(UCP, EVENT_05H_02H) \ __PMC_EV(UCP, EVENT_05H_04H) \ __PMC_EV(UCP, EVENT_06H_01H) \ __PMC_EV(UCP, EVENT_06H_02H) \ __PMC_EV(UCP, EVENT_06H_04H) \ __PMC_EV(UCP, EVENT_06H_08H) \ __PMC_EV(UCP, EVENT_06H_10H) \ __PMC_EV(UCP, EVENT_06H_20H) \ __PMC_EV(UCP, EVENT_07H_01H) \ __PMC_EV(UCP, EVENT_07H_02H) \ __PMC_EV(UCP, EVENT_07H_04H) \ __PMC_EV(UCP, EVENT_07H_08H) \ __PMC_EV(UCP, EVENT_07H_10H) \ __PMC_EV(UCP, EVENT_07H_20H) \ __PMC_EV(UCP, EVENT_07H_24H) \ __PMC_EV(UCP, EVENT_08H_01H) \ __PMC_EV(UCP, EVENT_08H_02H) \ __PMC_EV(UCP, EVENT_08H_04H) \ __PMC_EV(UCP, EVENT_08H_03H) \ __PMC_EV(UCP, EVENT_09H_01H) \ __PMC_EV(UCP, EVENT_09H_02H) \ __PMC_EV(UCP, EVENT_09H_04H) \ __PMC_EV(UCP, EVENT_09H_03H) \ __PMC_EV(UCP, EVENT_0AH_01H) \ __PMC_EV(UCP, EVENT_0AH_02H) \ __PMC_EV(UCP, EVENT_0AH_04H) \ __PMC_EV(UCP, EVENT_0AH_08H) \ __PMC_EV(UCP, EVENT_0AH_0FH) \ __PMC_EV(UCP, EVENT_0BH_01H) \ __PMC_EV(UCP, EVENT_0BH_02H) \ __PMC_EV(UCP, EVENT_0BH_04H) \ __PMC_EV(UCP, EVENT_0BH_08H) \ __PMC_EV(UCP, EVENT_0BH_10H) \ __PMC_EV(UCP, EVENT_0BH_1FH) \ __PMC_EV(UCP, EVENT_0CH_01H) \ __PMC_EV(UCP, EVENT_0CH_02H) \ __PMC_EV(UCP, EVENT_0CH_04H_E) \ __PMC_EV(UCP, EVENT_0CH_04H_F) \ __PMC_EV(UCP, EVENT_0CH_04H_M) \ __PMC_EV(UCP, EVENT_0CH_04H_S) \ __PMC_EV(UCP, EVENT_0CH_08H_E) \ __PMC_EV(UCP, EVENT_0CH_08H_F) \ __PMC_EV(UCP, EVENT_0CH_08H_M) \ __PMC_EV(UCP, EVENT_0CH_08H_S) \ __PMC_EV(UCP, EVENT_20H_01H) \ __PMC_EV(UCP, EVENT_20H_02H) \ __PMC_EV(UCP, EVENT_20H_04H) \ __PMC_EV(UCP, EVENT_20H_08H) \ __PMC_EV(UCP, EVENT_20H_10H) \ __PMC_EV(UCP, EVENT_20H_20H) \ __PMC_EV(UCP, EVENT_21H_01H) \ __PMC_EV(UCP, EVENT_21H_02H) \ __PMC_EV(UCP, EVENT_21H_04H) \ __PMC_EV(UCP, EVENT_22H_01H) \ __PMC_EV(UCP, EVENT_22H_02H) \ __PMC_EV(UCP, EVENT_22H_04H) \ __PMC_EV(UCP, EVENT_22H_08H) \ __PMC_EV(UCP, EVENT_22H_20H) \ __PMC_EV(UCP, EVENT_22H_40H) \ __PMC_EV(UCP, EVENT_22H_80H) \ __PMC_EV(UCP, EVENT_23H_01H) \ __PMC_EV(UCP, EVENT_23H_02H) \ __PMC_EV(UCP, EVENT_23H_04H) \ __PMC_EV(UCP, EVENT_24H_02H) \ __PMC_EV(UCP, EVENT_24H_04H) \ __PMC_EV(UCP, EVENT_25H_01H) \ __PMC_EV(UCP, EVENT_25H_02H) \ __PMC_EV(UCP, EVENT_25H_04H) \ __PMC_EV(UCP, EVENT_26H_01H) \ __PMC_EV(UCP, EVENT_27H_01H) \ __PMC_EV(UCP, EVENT_27H_02H) \ __PMC_EV(UCP, EVENT_27H_04H) \ __PMC_EV(UCP, EVENT_27H_08H) \ __PMC_EV(UCP, EVENT_27H_10H) \ __PMC_EV(UCP, EVENT_27H_20H) \ __PMC_EV(UCP, EVENT_28H_01H) \ __PMC_EV(UCP, EVENT_28H_02H) \ __PMC_EV(UCP, EVENT_28H_04H) \ __PMC_EV(UCP, EVENT_28H_08H) \ __PMC_EV(UCP, EVENT_28H_10H) \ __PMC_EV(UCP, EVENT_28H_20H) \ __PMC_EV(UCP, EVENT_29H_01H) \ __PMC_EV(UCP, EVENT_29H_02H) \ __PMC_EV(UCP, EVENT_29H_04H) \ __PMC_EV(UCP, EVENT_29H_08H) \ __PMC_EV(UCP, EVENT_29H_10H) \ __PMC_EV(UCP, EVENT_29H_20H) \ __PMC_EV(UCP, EVENT_2AH_01H) \ __PMC_EV(UCP, EVENT_2AH_02H) \ __PMC_EV(UCP, EVENT_2AH_04H) \ __PMC_EV(UCP, EVENT_2AH_07H) \ __PMC_EV(UCP, EVENT_2BH_01H) \ __PMC_EV(UCP, EVENT_2BH_02H) \ __PMC_EV(UCP, EVENT_2BH_04H) \ __PMC_EV(UCP, EVENT_2BH_07H) \ __PMC_EV(UCP, EVENT_2CH_01H) \ __PMC_EV(UCP, EVENT_2CH_02H) \ __PMC_EV(UCP, EVENT_2CH_04H) \ __PMC_EV(UCP, EVENT_2CH_07H) \ __PMC_EV(UCP, EVENT_2DH_01H) \ __PMC_EV(UCP, EVENT_2DH_02H) \ __PMC_EV(UCP, EVENT_2DH_04H) \ __PMC_EV(UCP, EVENT_2DH_07H) \ __PMC_EV(UCP, EVENT_2EH_01H) \ __PMC_EV(UCP, EVENT_2EH_02H) \ __PMC_EV(UCP, EVENT_2EH_04H) \ __PMC_EV(UCP, EVENT_2EH_07H) \ __PMC_EV(UCP, EVENT_2FH_01H) \ __PMC_EV(UCP, EVENT_2FH_02H) \ __PMC_EV(UCP, EVENT_2FH_04H) \ __PMC_EV(UCP, EVENT_2FH_07H) \ __PMC_EV(UCP, EVENT_2FH_08H) \ __PMC_EV(UCP, EVENT_2FH_10H) \ __PMC_EV(UCP, EVENT_2FH_20H) \ __PMC_EV(UCP, EVENT_2FH_38H) \ __PMC_EV(UCP, EVENT_30H_01H) \ __PMC_EV(UCP, EVENT_30H_02H) \ __PMC_EV(UCP, EVENT_30H_04H) \ __PMC_EV(UCP, EVENT_30H_07H) \ __PMC_EV(UCP, EVENT_31H_01H) \ __PMC_EV(UCP, EVENT_31H_02H) \ __PMC_EV(UCP, EVENT_31H_04H) \ __PMC_EV(UCP, EVENT_31H_07H) \ __PMC_EV(UCP, EVENT_32H_01H) \ __PMC_EV(UCP, EVENT_32H_02H) \ __PMC_EV(UCP, EVENT_32H_04H) \ __PMC_EV(UCP, EVENT_32H_07H) \ __PMC_EV(UCP, EVENT_33H_01H) \ __PMC_EV(UCP, EVENT_33H_02H) \ __PMC_EV(UCP, EVENT_33H_04H) \ __PMC_EV(UCP, EVENT_33H_07H) \ __PMC_EV(UCP, EVENT_34H_01H) \ __PMC_EV(UCP, EVENT_34H_02H) \ __PMC_EV(UCP, EVENT_34H_04H) \ __PMC_EV(UCP, EVENT_34H_08H) \ __PMC_EV(UCP, EVENT_34H_10H) \ __PMC_EV(UCP, EVENT_34H_20H) \ __PMC_EV(UCP, EVENT_34H_40H) \ __PMC_EV(UCP, EVENT_34H_80H) \ __PMC_EV(UCP, EVENT_35H_01H) \ __PMC_EV(UCP, EVENT_35H_02H) \ __PMC_EV(UCP, EVENT_35H_04H) \ __PMC_EV(UCP, EVENT_40H_01H) \ __PMC_EV(UCP, EVENT_40H_02H) \ __PMC_EV(UCP, EVENT_40H_04H) \ __PMC_EV(UCP, EVENT_40H_08H) \ __PMC_EV(UCP, EVENT_40H_10H) \ __PMC_EV(UCP, EVENT_40H_20H) \ __PMC_EV(UCP, EVENT_40H_07H) \ __PMC_EV(UCP, EVENT_40H_38H) \ __PMC_EV(UCP, EVENT_41H_01H) \ __PMC_EV(UCP, EVENT_41H_02H) \ __PMC_EV(UCP, EVENT_41H_04H) \ __PMC_EV(UCP, EVENT_41H_08H) \ __PMC_EV(UCP, EVENT_41H_10H) \ __PMC_EV(UCP, EVENT_41H_20H) \ __PMC_EV(UCP, EVENT_41H_07H) \ __PMC_EV(UCP, EVENT_41H_38H) \ __PMC_EV(UCP, EVENT_42H_01H) \ __PMC_EV(UCP, EVENT_42H_02H) \ __PMC_EV(UCP, EVENT_42H_04H) \ __PMC_EV(UCP, EVENT_42H_08H) \ __PMC_EV(UCP, EVENT_43H_01H) \ __PMC_EV(UCP, EVENT_43H_02H) \ __PMC_EV(UCP, EVENT_60H_01H) \ __PMC_EV(UCP, EVENT_60H_02H) \ __PMC_EV(UCP, EVENT_60H_04H) \ __PMC_EV(UCP, EVENT_61H_01H) \ __PMC_EV(UCP, EVENT_61H_02H) \ __PMC_EV(UCP, EVENT_61H_04H) \ __PMC_EV(UCP, EVENT_62H_01H) \ __PMC_EV(UCP, EVENT_62H_02H) \ __PMC_EV(UCP, EVENT_62H_04H) \ __PMC_EV(UCP, EVENT_63H_01H) \ __PMC_EV(UCP, EVENT_63H_02H) \ __PMC_EV(UCP, EVENT_63H_04H) \ __PMC_EV(UCP, EVENT_63H_08H) \ __PMC_EV(UCP, EVENT_63H_10H) \ __PMC_EV(UCP, EVENT_63H_20H) \ __PMC_EV(UCP, EVENT_64H_01H) \ __PMC_EV(UCP, EVENT_64H_02H) \ __PMC_EV(UCP, EVENT_64H_04H) \ __PMC_EV(UCP, EVENT_64H_08H) \ __PMC_EV(UCP, EVENT_64H_10H) \ __PMC_EV(UCP, EVENT_64H_20H) \ __PMC_EV(UCP, EVENT_65H_01H) \ __PMC_EV(UCP, EVENT_65H_02H) \ __PMC_EV(UCP, EVENT_65H_04H) \ __PMC_EV(UCP, EVENT_66H_01H) \ __PMC_EV(UCP, EVENT_66H_02H) \ __PMC_EV(UCP, EVENT_66H_04H) \ __PMC_EV(UCP, EVENT_67H_01H) \ __PMC_EV(UCP, EVENT_80H_01H) \ __PMC_EV(UCP, EVENT_80H_02H) \ __PMC_EV(UCP, EVENT_80H_04H) \ __PMC_EV(UCP, EVENT_80H_08H) \ __PMC_EV(UCP, EVENT_81H_01H) \ __PMC_EV(UCP, EVENT_81H_02H) \ __PMC_EV(UCP, EVENT_81H_04H) \ __PMC_EV(UCP, EVENT_81H_08H) \ __PMC_EV(UCP, EVENT_81H_20H) \ __PMC_EV(UCP, EVENT_81H_80H) \ __PMC_EV(UCP, EVENT_82H_01H) \ __PMC_EV(UCP, EVENT_83H_01H) \ __PMC_EV(UCP, EVENT_83H_02H) \ __PMC_EV(UCP, EVENT_83H_04H) \ __PMC_EV(UCP, EVENT_83H_08H) \ __PMC_EV(UCP, EVENT_84H_01H) \ __PMC_EV(UCP, EVENT_84H_02H) \ __PMC_EV(UCP, EVENT_84H_04H) \ __PMC_EV(UCP, EVENT_84H_08H) \ __PMC_EV(UCP, EVENT_85H_02H) \ __PMC_EV(UCP, EVENT_86H_01H) #define PMC_EV_UCP_FIRST PMC_EV_UCP_EVENT_00H_01H #define PMC_EV_UCP_LAST PMC_EV_UCP_EVENT_86H_01H #define __PMC_EV_ALIAS_COREI7UC() \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", UCP_EVENT_01H_04H) \ __PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H) \ __PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H) \ __PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H) \ __PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H) \ __PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H) \ __PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H) \ __PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H) \ __PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H) \ __PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H) \ __PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H) \ __PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H) \ __PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H) \ __PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H) \ __PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H) \ __PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H) \ __PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H) \ __PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H) \ __PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H) \ __PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H) \ __PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH) \ __PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H) \ __PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H) \ __PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H) \ __PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H) \ __PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H) \ __PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH) \ __PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H) \ __PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H) \ __PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H) \ __PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H) \ __PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H) \ __PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H) \ __PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H) \ __PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H) \ __PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH0", UCP_EVENT_27H_01H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH1", UCP_EVENT_27H_02H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH2", UCP_EVENT_27H_04H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH0", UCP_EVENT_27H_08H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH1", UCP_EVENT_27H_10H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH2", UCP_EVENT_27H_20H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H) \ __PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H) \ __PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", UCP_EVENT_40H_01H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", UCP_EVENT_40H_02H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", UCP_EVENT_40H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", UCP_EVENT_40H_08H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", UCP_EVENT_40H_10H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", UCP_EVENT_40H_20H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", UCP_EVENT_41H_01H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", UCP_EVENT_41H_02H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", UCP_EVENT_41H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", UCP_EVENT_41H_08H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", UCP_EVENT_41H_10H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", UCP_EVENT_41H_20H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H) \ __PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H) \ __PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H) #define __PMC_EV_ALIAS_WESTMEREUC() \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", UCP_EVENT_01H_04H) \ __PMC_EV_ALIAS("GQ_OCCUPANCY.READ_TRACKER", UCP_EVENT_02H_01H) \ __PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H) \ __PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H) \ __PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H) \ __PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H) \ __PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H) \ __PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H) \ __PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H) \ __PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H) \ __PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H) \ __PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H) \ __PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H) \ __PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H) \ __PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H) \ __PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H) \ __PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H) \ __PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H) \ __PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H) \ __PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H) \ __PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H) \ __PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH) \ __PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H) \ __PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H) \ __PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H) \ __PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H) \ __PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H) \ __PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S", UCP_EVENT_0CH_01H) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I", UCP_EVENT_0CH_02H) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_E", UCP_EVENT_0CH_04H_E) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_F", UCP_EVENT_0CH_04H_F) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_M", UCP_EVENT_0CH_04H_M) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_S", UCP_EVENT_0CH_04H_S) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_E", UCP_EVENT_0CH_08H_E) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_F", UCP_EVENT_0CH_08H_F) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_M", UCP_EVENT_0CH_08H_M) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_S", UCP_EVENT_0CH_08H_S) \ __PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H) \ __PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H) \ __PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H) \ __PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H) \ __PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H) \ __PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H) \ __PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H) \ __PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H) \ __PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.ANY", UCP_EVENT_2AH_07H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H) \ __PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H) \ __PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H) \ __PMC_EV_ALIAS("IMC_RETRY.CH0", UCP_EVENT_32H_01H) \ __PMC_EV_ALIAS("IMC_RETRY.CH1", UCP_EVENT_32H_02H) \ __PMC_EV_ALIAS("IMC_RETRY.CH2", UCP_EVENT_32H_04H) \ __PMC_EV_ALIAS("IMC_RETRY.ANY", UCP_EVENT_32H_07H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.IOH", UCP_EVENT_33H_01H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.REMOTE", UCP_EVENT_33H_02H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.ANY", UCP_EVENT_33H_07H) \ __PMC_EV_ALIAS("QHL_SLEEPS.IOH_ORDER", UCP_EVENT_34H_01H) \ __PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_ORDER", UCP_EVENT_34H_02H) \ __PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_ORDER", UCP_EVENT_34H_04H) \ __PMC_EV_ALIAS("QHL_SLEEPS.IOH_CONFLICT", UCP_EVENT_34H_08H) \ __PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_CONFLICT", UCP_EVENT_34H_10H) \ __PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_CONFLICT", UCP_EVENT_34H_20H) \ __PMC_EV_ALIAS("ADDR_OPCODE_MATCH.IOH", UCP_EVENT_35H_01H) \ __PMC_EV_ALIAS("ADDR_OPCODE_MATCH.REMOTE", UCP_EVENT_35H_02H) \ __PMC_EV_ALIAS("ADDR_OPCODE_MATCH.LOCAL", UCP_EVENT_35H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", UCP_EVENT_40H_01H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", UCP_EVENT_40H_02H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", UCP_EVENT_40H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", UCP_EVENT_40H_08H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", UCP_EVENT_40H_10H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", UCP_EVENT_40H_20H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", UCP_EVENT_41H_01H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", UCP_EVENT_41H_02H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", UCP_EVENT_41H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", UCP_EVENT_41H_08H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", UCP_EVENT_41H_10H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", UCP_EVENT_41H_20H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_0", UCP_EVENT_42H_01H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_1", UCP_EVENT_42H_04H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H) \ __PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H) \ __PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H) \ __PMC_EV_ALIAS("DRAM_THERMAL_THROTTLED", UCP_EVENT_67H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_0", UCP_EVENT_80H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_1", UCP_EVENT_80H_02H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_2", UCP_EVENT_80H_04H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_3", UCP_EVENT_80H_08H) \ __PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_0", UCP_EVENT_81H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_1", UCP_EVENT_81H_02H) \ __PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_2", UCP_EVENT_81H_04H) \ __PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_3", UCP_EVENT_81H_08H) \ __PMC_EV_ALIAS("PROCHOT_ASSERTION", UCP_EVENT_82H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_0", UCP_EVENT_83H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_1", UCP_EVENT_83H_02H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_2", UCP_EVENT_83H_04H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_3", UCP_EVENT_83H_08H) \ __PMC_EV_ALIAS("TURBO_MODE.CORE_0", UCP_EVENT_84H_01H) \ __PMC_EV_ALIAS("TURBO_MODE.CORE_1", UCP_EVENT_84H_02H) \ __PMC_EV_ALIAS("TURBO_MODE.CORE_2", UCP_EVENT_84H_04H) \ __PMC_EV_ALIAS("TURBO_MODE.CORE_3", UCP_EVENT_84H_08H) \ __PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_ENABLE", UCP_EVENT_85H_02H) \ __PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_DISABLE", UCP_EVENT_86H_01H) #define __PMC_EV_ALIAS_SANDYBRIDGEUC() \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITI", UCP_EVENT_22H_01H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITFSE", UCP_EVENT_22H_02H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSHITFSE", UCP_EVENT_22H_04H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSFWDM", UCP_EVENT_22H_08H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_EXTERNAL", UCP_EVENT_22H_20H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_XCORE", UCP_EVENT_22H_40H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE_AND_XCORE2", UCP_EVENT_22H_80H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.E", UCP_EVENT_34H_02H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.S", UCP_EVENT_34H_04H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_READ", UCP_EVENT_34H_10H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP_AND_READ2", UCP_EVENT_34H_20H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_EXTSNP", UCP_EVENT_34H_40H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_ANY", UCP_EVENT_34H_80H) \ __PMC_EV_ALIAS("IMPH_CB0_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \ __PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \ __PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \ __PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \ __PMC_EV_ALIAS("IMPH_C0H_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H) /* * Intel XScale events from: * * Intel XScale Core Developer's Manual * January, 2004, #27347302 * * 3rd Generation Intel XScale Microarchitecture * Developer's Manual * May 2007, #31628302 * * First 14 events are for 1st and 2nd Generation Intel XScale cores. The * remaining are available only on 3rd Generation Intel XScale cores. */ #define __PMC_EV_XSCALE() \ __PMC_EV(XSCALE, IC_FETCH) \ __PMC_EV(XSCALE, IC_MISS) \ __PMC_EV(XSCALE, DATA_DEPENDENCY_STALLED) \ __PMC_EV(XSCALE, ITLB_MISS) \ __PMC_EV(XSCALE, DTLB_MISS) \ __PMC_EV(XSCALE, BRANCH_RETIRED) \ __PMC_EV(XSCALE, BRANCH_MISPRED) \ __PMC_EV(XSCALE, INSTR_RETIRED) \ __PMC_EV(XSCALE, DC_FULL_CYCLE) \ __PMC_EV(XSCALE, DC_FULL_CONTIG) \ __PMC_EV(XSCALE, DC_ACCESS) \ __PMC_EV(XSCALE, DC_MISS) \ __PMC_EV(XSCALE, DC_WRITEBACK) \ __PMC_EV(XSCALE, PC_CHANGE) \ __PMC_EV(XSCALE, BRANCH_RETIRED_ALL) \ __PMC_EV(XSCALE, INSTR_CYCLE) \ __PMC_EV(XSCALE, CP_STALL) \ __PMC_EV(XSCALE, PC_CHANGE_ALL) \ __PMC_EV(XSCALE, PIPELINE_FLUSH) \ __PMC_EV(XSCALE, BACKEND_STALL) \ __PMC_EV(XSCALE, MULTIPLIER_USE) \ __PMC_EV(XSCALE, MULTIPLIER_STALLED) \ __PMC_EV(XSCALE, DATA_CACHE_STALLED) \ __PMC_EV(XSCALE, L2_CACHE_REQ) \ __PMC_EV(XSCALE, L2_CACHE_MISS) \ __PMC_EV(XSCALE, ADDRESS_BUS_TRANS) \ __PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS) \ __PMC_EV(XSCALE, DATA_BUS_TRANS) #define PMC_EV_XSCALE_FIRST PMC_EV_XSCALE_IC_FETCH #define PMC_EV_XSCALE_LAST PMC_EV_XSCALE_DATA_BUS_TRANS /* * MIPS Events from "Programming the MIPS32 24K Core Family", * Document Number: MD00355 Revision 04.63 December 19, 2008 * These events are kept in the order found in Table 7.4. * For counters which are different between the left hand * column (0/2) and the right hand column (1/3) the left * hand is given first, e.g. BRANCH_COMPLETED and BRANCH_MISPRED * in the definition below. */ #define __PMC_EV_MIPS24K() \ __PMC_EV(MIPS24K, CYCLE) \ __PMC_EV(MIPS24K, INSTR_EXECUTED) \ __PMC_EV(MIPS24K, BRANCH_COMPLETED) \ __PMC_EV(MIPS24K, BRANCH_MISPRED) \ __PMC_EV(MIPS24K, RETURN) \ __PMC_EV(MIPS24K, RETURN_MISPRED) \ __PMC_EV(MIPS24K, RETURN_NOT_31) \ __PMC_EV(MIPS24K, RETURN_NOTPRED) \ __PMC_EV(MIPS24K, ITLB_ACCESS) \ __PMC_EV(MIPS24K, ITLB_MISS) \ __PMC_EV(MIPS24K, DTLB_ACCESS) \ __PMC_EV(MIPS24K, DTLB_MISS) \ __PMC_EV(MIPS24K, JTLB_IACCESS) \ __PMC_EV(MIPS24K, JTLB_IMISS) \ __PMC_EV(MIPS24K, JTLB_DACCESS) \ __PMC_EV(MIPS24K, JTLB_DMISS) \ __PMC_EV(MIPS24K, IC_FETCH) \ __PMC_EV(MIPS24K, IC_MISS) \ __PMC_EV(MIPS24K, DC_LOADSTORE) \ __PMC_EV(MIPS24K, DC_WRITEBACK) \ __PMC_EV(MIPS24K, DC_MISS) \ __PMC_EV(MIPS24K, STORE_MISS) \ __PMC_EV(MIPS24K, LOAD_MISS) \ __PMC_EV(MIPS24K, INTEGER_COMPLETED) \ __PMC_EV(MIPS24K, FP_COMPLETED) \ __PMC_EV(MIPS24K, LOAD_COMPLETED) \ __PMC_EV(MIPS24K, STORE_COMPLETED) \ __PMC_EV(MIPS24K, BARRIER_COMPLETED) \ __PMC_EV(MIPS24K, MIPS16_COMPLETED) \ __PMC_EV(MIPS24K, NOP_COMPLETED) \ __PMC_EV(MIPS24K, INTEGER_MULDIV_COMPLETED)\ __PMC_EV(MIPS24K, RF_STALL) \ __PMC_EV(MIPS24K, INSTR_REFETCH) \ __PMC_EV(MIPS24K, STORE_COND_COMPLETED) \ __PMC_EV(MIPS24K, STORE_COND_FAILED) \ __PMC_EV(MIPS24K, ICACHE_REQUESTS) \ __PMC_EV(MIPS24K, ICACHE_HIT) \ __PMC_EV(MIPS24K, L2_WRITEBACK) \ __PMC_EV(MIPS24K, L2_ACCESS) \ __PMC_EV(MIPS24K, L2_MISS) \ __PMC_EV(MIPS24K, L2_ERR_CORRECTED) \ __PMC_EV(MIPS24K, EXCEPTIONS) \ __PMC_EV(MIPS24K, RF_CYCLES_STALLED) \ __PMC_EV(MIPS24K, IFU_CYCLES_STALLED) \ __PMC_EV(MIPS24K, ALU_CYCLES_STALLED) \ __PMC_EV(MIPS24K, UNCACHED_LOAD) \ __PMC_EV(MIPS24K, UNCACHED_STORE) \ __PMC_EV(MIPS24K, CP2_REG_TO_REG_COMPLETED)\ __PMC_EV(MIPS24K, MFTC_COMPLETED) \ __PMC_EV(MIPS24K, IC_BLOCKED_CYCLES) \ __PMC_EV(MIPS24K, DC_BLOCKED_CYCLES) \ __PMC_EV(MIPS24K, L2_IMISS_STALL_CYCLES) \ __PMC_EV(MIPS24K, L2_DMISS_STALL_CYCLES) \ __PMC_EV(MIPS24K, DMISS_CYCLES) \ __PMC_EV(MIPS24K, L2_MISS_CYCLES) \ __PMC_EV(MIPS24K, UNCACHED_BLOCK_CYCLES) \ __PMC_EV(MIPS24K, MDU_STALL_CYCLES) \ __PMC_EV(MIPS24K, FPU_STALL_CYCLES) \ __PMC_EV(MIPS24K, CP2_STALL_CYCLES) \ __PMC_EV(MIPS24K, COREXTEND_STALL_CYCLES) \ __PMC_EV(MIPS24K, ISPRAM_STALL_CYCLES) \ __PMC_EV(MIPS24K, DSPRAM_STALL_CYCLES) \ __PMC_EV(MIPS24K, CACHE_STALL_CYCLES) \ __PMC_EV(MIPS24K, LOAD_TO_USE_STALLS) \ __PMC_EV(MIPS24K, BASE_MISPRED_STALLS) \ __PMC_EV(MIPS24K, CPO_READ_STALLS) \ __PMC_EV(MIPS24K, BRANCH_MISPRED_CYCLES) \ __PMC_EV(MIPS24K, IFETCH_BUFFER_FULL) \ __PMC_EV(MIPS24K, FETCH_BUFFER_ALLOCATED) \ __PMC_EV(MIPS24K, EJTAG_ITRIGGER) \ __PMC_EV(MIPS24K, EJTAG_DTRIGGER) \ __PMC_EV(MIPS24K, FSB_LT_QUARTER) \ __PMC_EV(MIPS24K, FSB_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, FSB_GT_HALF) \ __PMC_EV(MIPS24K, FSB_FULL_PIPELINE_STALLS)\ __PMC_EV(MIPS24K, LDQ_LT_QUARTER) \ __PMC_EV(MIPS24K, LDQ_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, LDQ_GT_HALF) \ __PMC_EV(MIPS24K, LDQ_FULL_PIPELINE_STALLS)\ __PMC_EV(MIPS24K, WBB_LT_QUARTER) \ __PMC_EV(MIPS24K, WBB_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, WBB_GT_HALF) \ __PMC_EV(MIPS24K, WBB_FULL_PIPELINE_STALLS) \ __PMC_EV(MIPS24K, REQUEST_LATENCY) \ __PMC_EV(MIPS24K, REQUEST_COUNT) #define PMC_EV_MIPS24K_FIRST PMC_EV_MIPS24K_CYCLE #define PMC_EV_MIPS24K_LAST PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS #define __PMC_EV_PPC7450() \ __PMC_EV(PPC7450, CYCLE) \ __PMC_EV(PPC7450, INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLB_BIT_TRANSITIONS) \ __PMC_EV(PPC7450, INSTR_DISPATCHED) \ __PMC_EV(PPC7450, PMON_EXCEPT) \ __PMC_EV(PPC7450, PMON_SIG) \ __PMC_EV(PPC7450, VPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VFPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VIU1_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VIU2_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTVSCR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTVRSAVE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VPU_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VFPU_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VIU1_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VIU2_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, MFVSCR_SYNC_CYCLES) \ __PMC_EV(PPC7450, VSCR_SAT_SET) \ __PMC_EV(PPC7450, STORE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L1_DATA_SNOOPS) \ __PMC_EV(PPC7450, UNRESOLVED_BRANCHES) \ __PMC_EV(PPC7450, SPEC_BUFFER_CYCLES) \ __PMC_EV(PPC7450, BRANCH_UNIT_STALL_CYCLES) \ __PMC_EV(PPC7450, TRUE_BRANCH_TARGET_HITS) \ __PMC_EV(PPC7450, BRANCH_LINK_STAC_PREDICTED) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_DISPATCHES) \ __PMC_EV(PPC7450, CYCLES_THREE_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES) \ __PMC_EV(PPC7450, THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES) \ __PMC_EV(PPC7450, CYCLES_NO_COMPLETED_INSTRS) \ __PMC_EV(PPC7450, IU2_INSTR_COMPLETED) \ __PMC_EV(PPC7450, BRANCHES_COMPLETED) \ __PMC_EV(PPC7450, EIEIO_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTSPR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LS_LM_COMPLETED) \ __PMC_EV(PPC7450, ITLB_HW_TABLE_SEARCH_CYCLES) \ __PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_ACCESSES) \ __PMC_EV(PPC7450, INSTR_BKPT_MATCHES) \ __PMC_EV(PPC7450, L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_ON_MODIFIED) \ __PMC_EV(PPC7450, LOAD_MISS_ALIAS) \ __PMC_EV(PPC7450, LOAD_MISS_ALIAS_ON_TOUCH) \ __PMC_EV(PPC7450, TOUCH_ALIAS) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT_QUEUE) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HITS) \ __PMC_EV(PPC7450, WRITE_THROUGH_STORES) \ __PMC_EV(PPC7450, CACHE_INHIBITED_STORES) \ __PMC_EV(PPC7450, L1_DATA_LOAD_HIT) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_HIT) \ __PMC_EV(PPC7450, L1_DATA_STORE_HIT) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_HITS) \ __PMC_EV(PPC7450, DST_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, REFRESHED_DSTS) \ __PMC_EV(PPC7450, SUCCESSFUL_DST_TABLE_SEARCHES) \ __PMC_EV(PPC7450, DSS_INSTR_COMPLETED) \ __PMC_EV(PPC7450, DST_STREAM_0_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, VTQ_SUSPENDS_DUE_TO_CTX_CHANGE) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH_HIT) \ __PMC_EV(PPC7450, VEC_LOAD_INSTR_COMPLETED) \ __PMC_EV(PPC7450, FP_STORE_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FPU_RENORMALIZATION) \ __PMC_EV(PPC7450, FPU_DENORMALIZATION) \ __PMC_EV(PPC7450, FP_STORE_CAUSES_STALL_IN_LSU) \ __PMC_EV(PPC7450, LD_ST_TRUE_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_INDEXED_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_ALIAS_VS_FSQ_WB0_WB1) \ __PMC_EV(PPC7450, LSU_ALIAS_VS_CSQ) \ __PMC_EV(PPC7450, LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0) \ __PMC_EV(PPC7450, LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0) \ __PMC_EV(PPC7450, LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1) \ __PMC_EV(PPC7450, LSU_TOUCH_ALIAS_VS_CSQ) \ __PMC_EV(PPC7450, LSU_LMQ_FULL_STALL) \ __PMC_EV(PPC7450, FP_LOAD_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FP_LOAD_DOUBLE_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, LSU_RA_LATCH_STALL) \ __PMC_EV(PPC7450, LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_LMQ_INDEX_ALIAS) \ __PMC_EV(PPC7450, LSU_STORE_QUEUE_INDEX_ALIAS) \ __PMC_EV(PPC7450, LSU_CSQ_FORWARDING) \ __PMC_EV(PPC7450, LSU_MISALIGNED_LOAD_FINISH) \ __PMC_EV(PPC7450, LSU_MISALIGN_STORE_COMPLETED) \ __PMC_EV(PPC7450, LSU_MISALIGN_STALL) \ __PMC_EV(PPC7450, FP_ONE_QUARTER_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_ONE_HALF_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_ALL_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_DENORMALIZED_RESULT) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_MISSES) \ __PMC_EV(PPC7450, DISPATCHES_TO_FPR_ISSUE_QUEUE) \ __PMC_EV(PPC7450, LSU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LOAD_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SS_SM_INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLBIE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LWARX_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MFSPR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, REFETCH_SERIALIZATION) \ __PMC_EV(PPC7450, COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, CYCLES_ONE_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, CYCLES_TWO_INSTR_COMPLETED) \ __PMC_EV(PPC7450, ITLB_NON_SPECULATIVE_MISSES) \ __PMC_EV(PPC7450, CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS) \ __PMC_EV(PPC7450, L1_DATA_LOAD_ACCESS_MISS) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_MISS) \ __PMC_EV(PPC7450, L1_DATA_STORE_MISS) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_MISS_CYCLES) \ __PMC_EV(PPC7450, L1_DATA_CYCLES_USED) \ __PMC_EV(PPC7450, DST_STREAM_1_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, VTQ_STREAM_CANCELED_PREMATURELY) \ __PMC_EV(PPC7450, VTQ_RESUMES_DUE_TO_CTX_CHANGE) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH_MISS) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH) \ __PMC_EV(PPC7450, TLBIE_SNOOPS) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_RELOADS) \ __PMC_EV(PPC7450, L1_DATA_CACHE_RELOADS) \ __PMC_EV(PPC7450, L1_DATA_CACHE_CASTOUTS_TO_L2) \ __PMC_EV(PPC7450, STORE_MERGE_GATHER) \ __PMC_EV(PPC7450, CACHEABLE_STORE_MERGE_TO_32_BYTES) \ __PMC_EV(PPC7450, DATA_BKPT_MATCHES) \ __PMC_EV(PPC7450, FALL_THROUGH_BRANCHES_PROCESSED) \ __PMC_EV(PPC7450, FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, SECOND_SPECULATION_BUFFER_ACTIVE) \ __PMC_EV(PPC7450, BPU_STALL_ON_LR_DEPENDENCY) \ __PMC_EV(PPC7450, BTIC_MISS) \ __PMC_EV(PPC7450, BRANCH_LINK_STACK_CORRECTLY_RESOLVED) \ __PMC_EV(PPC7450, FPR_ISSUE_STALLED) \ __PMC_EV(PPC7450, SWITCHES_BETWEEN_PRIV_USER) \ __PMC_EV(PPC7450, LSU_COMPLETES_FP_STORE_SINGLE) \ __PMC_EV(PPC7450, VR_ISSUE_QUEUE_DISPATCHES) \ __PMC_EV(PPC7450, VR_STALLS) \ __PMC_EV(PPC7450, GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, FPR_ISSUE_QUEUE_ENTRIES) \ __PMC_EV(PPC7450, FPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, STWCX_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LS_LM_INSTR_PIECES) \ __PMC_EV(PPC7450, ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, DTLB_MISSES) \ __PMC_EV(PPC7450, CANCELLED_L1_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L1_DATA_CACHE_OP_HIT) \ __PMC_EV(PPC7450, L1_DATA_LOAD_MISS_CYCLES) \ __PMC_EV(PPC7450, L1_DATA_PUSHES) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_MISS) \ __PMC_EV(PPC7450, VT2_FETCHES) \ __PMC_EV(PPC7450, TAKEN_BRANCHES_PROCESSED) \ __PMC_EV(PPC7450, BRANCH_FLUSHES) \ __PMC_EV(PPC7450, SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, THIRD_SPECULATION_BUFFER_ACTIVE) \ __PMC_EV(PPC7450, BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY) \ __PMC_EV(PPC7450, FAST_BTIC_HIT) \ __PMC_EV(PPC7450, BRANCH_LINK_STACK_MISPREDICTED) \ __PMC_EV(PPC7450, CYCLES_THREE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, CYCLES_NO_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_STALLED) \ __PMC_EV(PPC7450, IU1_INSTR_COMPLETED) \ __PMC_EV(PPC7450, DSSALL_INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLBSYNC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SYNC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SS_SM_INSTR_PIECES) \ __PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES) \ __PMC_EV(PPC7450, SNOOP_RETRIES) \ __PMC_EV(PPC7450, SUCCESSFUL_STWCX) \ __PMC_EV(PPC7450, DST_STREAM_3_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, MISPREDICTED_BRANCHES) \ __PMC_EV(PPC7450, FOLDED_BRANCHES) \ __PMC_EV(PPC7450, FP_STORE_DOUBLE_COMPLETES_IN_LSU) \ __PMC_EV(PPC7450, L2_CACHE_HITS) \ __PMC_EV(PPC7450, L3_CACHE_HITS) \ __PMC_EV(PPC7450, L2_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_DATA_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_DATA_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_LOAD_HITS) \ __PMC_EV(PPC7450, L2_STORE_HITS) \ __PMC_EV(PPC7450, L3_LOAD_HITS) \ __PMC_EV(PPC7450, L3_STORE_HITS) \ __PMC_EV(PPC7450, L2_TOUCH_HITS) \ __PMC_EV(PPC7450, L3_TOUCH_HITS) \ __PMC_EV(PPC7450, SNOOP_MODIFIED) \ __PMC_EV(PPC7450, SNOOP_VALID) \ __PMC_EV(PPC7450, INTERVENTION) \ __PMC_EV(PPC7450, L2_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_CACHE_CASTOUTS) \ __PMC_EV(PPC7450, L3_CACHE_CASTOUTS) \ __PMC_EV(PPC7450, L2SQ_FULL_CYCLES) \ __PMC_EV(PPC7450, L3SQ_FULL_CYCLES) \ __PMC_EV(PPC7450, RAQ_FULL_CYCLES) \ __PMC_EV(PPC7450, WAQ_FULL_CYCLES) \ __PMC_EV(PPC7450, L1_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, L2_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, L3_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, EXTERNAL_PUSHES) \ __PMC_EV(PPC7450, EXTERNAL_SNOOP_RETRY) \ __PMC_EV(PPC7450, DTQ_FULL_CYCLES) \ __PMC_EV(PPC7450, BUS_RETRY) \ __PMC_EV(PPC7450, L2_VALID_REQUEST) \ __PMC_EV(PPC7450, BORDQ_FULL) \ __PMC_EV(PPC7450, BUS_TAS_FOR_READS) \ __PMC_EV(PPC7450, BUS_TAS_FOR_WRITES) \ __PMC_EV(PPC7450, BUS_READS_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_WRITES_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_READS_WRITES_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_L1_RETRY) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_COLLISION) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_INTERVENTION_ORDERING) \ __PMC_EV(PPC7450, SNOOP_REQUESTS) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_REQUEST) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_LOAD) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_STORE) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_FULL) #define PMC_EV_PPC7450_FIRST PMC_EV_PPC7450_CYCLE #define PMC_EV_PPC7450_LAST PMC_EV_PPC7450_PREFETCH_ENGINE_FULL /* * All known PMC events. * * PMC event numbers are allocated sparsely to allow new PMC events to * be added to a PMC class without breaking ABI compatibility. The * current allocation scheme is: * * START #EVENTS DESCRIPTION * 0 0x1000 Reserved * 0x1000 0x0001 TSC * 0x2000 0x0080 AMD K7 events * 0x2080 0x0100 AMD K8 events * 0x10000 0x0080 INTEL architectural fixed-function events * 0x10080 0x0F80 INTEL architectural programmable events * 0x11000 0x0080 INTEL Pentium 4 events * 0x11080 0x0080 INTEL Pentium MMX events * 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events * 0x11200 0x00FF INTEL XScale events * 0x11300 0x00FF MIPS 24K events * 0x20000 0x1000 Software events */ #define __PMC_EVENTS() \ __PMC_EV_BLOCK(TSC, 0x01000) \ __PMC_EV_TSC() \ __PMC_EV_BLOCK(K7, 0x2000) \ __PMC_EV_K7() \ __PMC_EV_BLOCK(K8, 0x2080) \ __PMC_EV_K8() \ __PMC_EV_BLOCK(IAF, 0x10000) \ __PMC_EV_IAF() \ __PMC_EV_BLOCK(IAP, 0x10080) \ __PMC_EV_IAP() \ __PMC_EV_BLOCK(P4, 0x11000) \ __PMC_EV_P4() \ __PMC_EV_BLOCK(P5, 0x11080) \ __PMC_EV_P5() \ __PMC_EV_BLOCK(P6, 0x11100) \ __PMC_EV_P6() \ __PMC_EV_BLOCK(XSCALE, 0x11200) \ __PMC_EV_XSCALE() \ __PMC_EV_BLOCK(MIPS24K, 0x11300) \ __PMC_EV_MIPS24K() \ __PMC_EV_BLOCK(UCF, 0x12000) \ __PMC_EV_UCF() \ __PMC_EV_BLOCK(UCP, 0x12080) \ __PMC_EV_UCP() \ __PMC_EV_BLOCK(PPC7450, 0x13000) \ __PMC_EV_PPC7450() \ #define PMC_EVENT_FIRST PMC_EV_TSC_TSC #define PMC_EVENT_LAST PMC_EV_SOFT_LAST #endif /* _DEV_HWPMC_PMC_EVENTS_H_ */ Index: stable/9/sys/dev =================================================================== --- stable/9/sys/dev (revision 242593) +++ stable/9/sys/dev (revision 242594) Property changes on: stable/9/sys/dev ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/dev:r241738,241741 Index: stable/9/sys/sys/pmc.h =================================================================== --- stable/9/sys/sys/pmc.h (revision 242593) +++ stable/9/sys/sys/pmc.h (revision 242594) @@ -1,1094 +1,1095 @@ /*- * Copyright (c) 2003-2008, Joseph Koshy * Copyright (c) 2007 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by A. Joseph Koshy under * sponsorship from the FreeBSD Foundation and Google, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SYS_PMC_H_ #define _SYS_PMC_H_ #include #include #include #define PMC_MODULE_NAME "hwpmc" #define PMC_NAME_MAX 64 /* HW counter name size */ #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ /* * Kernel<->userland API version number [MMmmpppp] * * Major numbers are to be incremented when an incompatible change to * the ABI occurs that older clients will not be able to handle. * * Minor numbers are incremented when a backwards compatible change * occurs that allows older correct programs to run unchanged. For * example, when support for a new PMC type is added. * * The patch version is incremented for every bug fix. */ #define PMC_VERSION_MAJOR 0x03 #define PMC_VERSION_MINOR 0x01 #define PMC_VERSION_PATCH 0x0000 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) /* * Kinds of CPUs known. * * We keep track of CPU variants that need to be distinguished in * some way for PMC operations. CPU names are grouped by manufacturer * and numbered sparsely in order to minimize changes to the ABI involved * when new CPUs are added. */ #define __PMC_CPUS() \ __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ + __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ __PMC_CPU(GENERIC, 0x400, "Generic") enum pmc_cputype { #undef __PMC_CPU #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, __PMC_CPUS() }; #define PMC_CPU_FIRST PMC_CPU_AMD_K7 #define PMC_CPU_LAST PMC_CPU_GENERIC /* * Classes of PMCs */ #define __PMC_CLASSES() \ __PMC_CLASS(TSC) /* CPU Timestamp counter */ \ __PMC_CLASS(K7) /* AMD K7 performance counters */ \ __PMC_CLASS(K8) /* AMD K8 performance counters */ \ __PMC_CLASS(P5) /* Intel Pentium counters */ \ __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \ __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \ __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \ __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \ __PMC_CLASS(UCF) /* Intel Uncore fixed function */ \ __PMC_CLASS(UCP) /* Intel Uncore programmable */ \ __PMC_CLASS(XSCALE) /* Intel XScale counters */ \ __PMC_CLASS(MIPS24K) /* MIPS 24K */ \ __PMC_CLASS(PPC7450) /* Motorola MPC7450 class */ \ __PMC_CLASS(SOFT) /* Software events */ enum pmc_class { #undef __PMC_CLASS #define __PMC_CLASS(N) PMC_CLASS_##N , __PMC_CLASSES() }; #define PMC_CLASS_FIRST PMC_CLASS_TSC #define PMC_CLASS_LAST PMC_CLASS_SOFT /* * A PMC can be in the following states: * * Hardware states: * DISABLED -- administratively prohibited from being used. * FREE -- HW available for use * Software states: * ALLOCATED -- allocated * STOPPED -- allocated, but not counting events * RUNNING -- allocated, and in operation; 'pm_runcount' * holds the number of CPUs using this PMC at * a given instant * DELETED -- being destroyed */ #define __PMC_HWSTATES() \ __PMC_STATE(DISABLED) \ __PMC_STATE(FREE) #define __PMC_SWSTATES() \ __PMC_STATE(ALLOCATED) \ __PMC_STATE(STOPPED) \ __PMC_STATE(RUNNING) \ __PMC_STATE(DELETED) #define __PMC_STATES() \ __PMC_HWSTATES() \ __PMC_SWSTATES() enum pmc_state { #undef __PMC_STATE #define __PMC_STATE(S) PMC_STATE_##S, __PMC_STATES() __PMC_STATE(MAX) }; #define PMC_STATE_FIRST PMC_STATE_DISABLED #define PMC_STATE_LAST PMC_STATE_DELETED /* * An allocated PMC may used as a 'global' counter or as a * 'thread-private' one. Each such mode of use can be in either * statistical sampling mode or in counting mode. Thus a PMC in use * * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling * SC i.e., SYSTEM COUNTER -- system-wide counting mode * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling * TC i.e., THREAD COUNTER -- thread virtual, counting mode * * Statistical profiling modes rely on the PMC periodically delivering * a interrupt to the CPU (when the configured number of events have * been measured), so the PMC must have the ability to generate * interrupts. * * In counting modes, the PMC counts its configured events, with the * value of the PMC being read whenever needed by its owner process. * * The thread specific modes "virtualize" the PMCs -- the PMCs appear * to be thread private and count events only when the profiled thread * actually executes on the CPU. * * The system-wide "global" modes keep the PMCs running all the time * and are used to measure the behaviour of the whole system. */ #define __PMC_MODES() \ __PMC_MODE(SS, 0) \ __PMC_MODE(SC, 1) \ __PMC_MODE(TS, 2) \ __PMC_MODE(TC, 3) enum pmc_mode { #undef __PMC_MODE #define __PMC_MODE(M,N) PMC_MODE_##M = N, __PMC_MODES() }; #define PMC_MODE_FIRST PMC_MODE_SS #define PMC_MODE_LAST PMC_MODE_TC #define PMC_IS_COUNTING_MODE(mode) \ ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) #define PMC_IS_SYSTEM_MODE(mode) \ ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) #define PMC_IS_SAMPLING_MODE(mode) \ ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) #define PMC_IS_VIRTUAL_MODE(mode) \ ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) /* * PMC row disposition */ #define __PMC_DISPOSITIONS(N) \ __PMC_DISP(STANDALONE) /* global/disabled counters */ \ __PMC_DISP(FREE) /* free/available */ \ __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ __PMC_DISP(UNKNOWN) /* sentinel */ enum pmc_disp { #undef __PMC_DISP #define __PMC_DISP(D) PMC_DISP_##D , __PMC_DISPOSITIONS() }; #define PMC_DISP_FIRST PMC_DISP_STANDALONE #define PMC_DISP_LAST PMC_DISP_THREAD /* * Counter capabilities * * __PMC_CAPS(NAME, VALUE, DESCRIPTION) */ #define __PMC_CAPS() \ __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ __PMC_CAP(USER, 1, "count user-mode events") \ __PMC_CAP(SYSTEM, 2, "count system-mode events") \ __PMC_CAP(EDGE, 3, "do edge detection of events") \ __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ __PMC_CAP(READ, 5, "read PMC counter") \ __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ __PMC_CAP(INVERT, 7, "invert comparision sense") \ __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ __PMC_CAP(PRECISE, 9, "perform precise sampling") \ __PMC_CAP(TAGGING, 10, "tag upstream events") \ __PMC_CAP(CASCADE, 11, "cascade counters") enum pmc_caps { #undef __PMC_CAP #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , __PMC_CAPS() }; #define PMC_CAP_FIRST PMC_CAP_INTERRUPT #define PMC_CAP_LAST PMC_CAP_CASCADE /* * PMC Event Numbers * * These are generated from the definitions in "dev/hwpmc/pmc_events.h". */ enum pmc_event { #undef __PMC_EV #undef __PMC_EV_BLOCK #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , __PMC_EVENTS() }; /* * PMC SYSCALL INTERFACE */ /* * "PMC_OPS" -- these are the commands recognized by the kernel * module, and are used when performing a system call from userland. */ #define __PMC_OPS() \ __PMC_OP(CONFIGURELOG, "Set log file") \ __PMC_OP(FLUSHLOG, "Flush log file") \ __PMC_OP(GETCPUINFO, "Get system CPU information") \ __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ __PMC_OP(GETMODULEVERSION, "Get module version") \ __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ __PMC_OP(PMCADMIN, "Set PMC state") \ __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ __PMC_OP(PMCRELEASE, "Release a PMC") \ __PMC_OP(PMCRW, "Read/Set a PMC") \ __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ __PMC_OP(PMCSTART, "Start a PMC") \ __PMC_OP(PMCSTOP, "Stop a PMC") \ __PMC_OP(WRITELOG, "Write a cookie to the log file") \ __PMC_OP(CLOSELOG, "Close log file") \ __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") enum pmc_ops { #undef __PMC_OP #define __PMC_OP(N, D) PMC_OP_##N, __PMC_OPS() }; /* * Flags used in operations on PMCs. */ #define PMC_F_FORCE 0x00000001 /*OP ADMIN force operation */ #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ #define PMC_F_KGMON 0x00000040 /*OP ALLOCATE kgmon(8) profiling */ /* V2 API */ #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ /* internal flags */ #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ #define PMC_CALLCHAIN_DEPTH_MAX 32 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ /* * Cookies used to denote allocated PMCs, and the values of PMCs. */ typedef uint32_t pmc_id_t; typedef uint64_t pmc_value_t; #define PMC_ID_INVALID (~ (pmc_id_t) 0) /* * PMC IDs have the following format: * * +--------+----------+-----------+-----------+ * | CPU | PMC MODE | PMC CLASS | ROW INDEX | * +--------+----------+-----------+-----------+ * * where each field is 8 bits wide. Field 'CPU' is set to the * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode * PMCs. Field 'PMC MODE' is the allocated PMC mode. Field 'PMC * CLASS' is the class of the PMC. Field 'ROW INDEX' is the row index * for the PMC. * * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total * number of hardware PMCs on this cpu. */ #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) #define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8) #define PMC_ID_TO_MODE(ID) (((ID) & 0xFF0000) >> 16) #define PMC_ID_TO_CPU(ID) (((ID) & 0xFF000000) >> 24) #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ ((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) | \ (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF)) /* * Data structures for system calls supported by the pmc driver. */ /* * OP PMCALLOCATE * * Allocate a PMC on the named CPU. */ #define PMC_CPU_ANY ~0 struct pmc_op_pmcallocate { uint32_t pm_caps; /* PMC_CAP_* */ uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ enum pmc_class pm_class; /* class of PMC desired */ enum pmc_event pm_ev; /* [enum pmc_event] desired */ uint32_t pm_flags; /* additional modifiers PMC_F_* */ enum pmc_mode pm_mode; /* desired mode */ pmc_id_t pm_pmcid; /* [return] process pmc id */ union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ }; /* * OP PMCADMIN * * Set the administrative state (i.e., whether enabled or disabled) of * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an * absolute PMC number and need not have been first allocated by the * calling process. */ struct pmc_op_pmcadmin { int pm_cpu; /* CPU# */ uint32_t pm_flags; /* flags */ int pm_pmc; /* PMC# */ enum pmc_state pm_state; /* desired state */ }; /* * OP PMCATTACH / OP PMCDETACH * * Attach/detach a PMC and a process. */ struct pmc_op_pmcattach { pmc_id_t pm_pmc; /* PMC to attach to */ pid_t pm_pid; /* target process */ }; /* * OP PMCSETCOUNT * * Set the sampling rate (i.e., the reload count) for statistical counters. * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. */ struct pmc_op_pmcsetcount { pmc_value_t pm_count; /* initial/sample count */ pmc_id_t pm_pmcid; /* PMC id to set */ }; /* * OP PMCRW * * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs * to have been previously allocated using PMCALLOCATE. */ struct pmc_op_pmcrw { uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ pmc_id_t pm_pmcid; /* pmc id */ pmc_value_t pm_value; /* new&returned value */ }; /* * OP GETPMCINFO * * retrieve PMC state for a named CPU. The caller is expected to * allocate 'npmc' * 'struct pmc_info' bytes of space for the return * values. */ struct pmc_info { char pm_name[PMC_NAME_MAX]; /* pmc name */ enum pmc_class pm_class; /* enum pmc_class */ int pm_enabled; /* whether enabled */ enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ pid_t pm_ownerpid; /* owner, or -1 */ enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ enum pmc_event pm_event; /* current event */ uint32_t pm_flags; /* current flags */ pmc_value_t pm_reloadcount; /* sampling counters only */ }; struct pmc_op_getpmcinfo { int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ }; /* * OP GETCPUINFO * * Retrieve system CPU information. */ struct pmc_classinfo { enum pmc_class pm_class; /* class id */ uint32_t pm_caps; /* counter capabilities */ uint32_t pm_width; /* width of the PMC */ uint32_t pm_num; /* number of PMCs in class */ }; struct pmc_op_getcpuinfo { enum pmc_cputype pm_cputype; /* what kind of CPU */ uint32_t pm_ncpu; /* max CPU number */ uint32_t pm_npmc; /* #PMCs per CPU */ uint32_t pm_nclass; /* #classes of PMCs */ struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; }; /* * OP CONFIGURELOG * * Configure a log file for writing system-wide statistics to. */ struct pmc_op_configurelog { int pm_flags; int pm_logfd; /* logfile fd (or -1) */ }; /* * OP GETDRIVERSTATS * * Retrieve pmc(4) driver-wide statistics. */ struct pmc_op_getdriverstats { int pm_intr_ignored; /* #interrupts ignored */ int pm_intr_processed; /* #interrupts processed */ int pm_intr_bufferfull; /* #interrupts with ENOSPC */ int pm_syscalls; /* #syscalls */ int pm_syscall_errors; /* #syscalls with errors */ int pm_buffer_requests; /* #buffer requests */ int pm_buffer_requests_failed; /* #failed buffer requests */ int pm_log_sweeps; /* #sample buffer processing passes */ }; /* * OP RELEASE / OP START / OP STOP * * Simple operations on a PMC id. */ struct pmc_op_simple { pmc_id_t pm_pmcid; }; /* * OP WRITELOG * * Flush the current log buffer and write 4 bytes of user data to it. */ struct pmc_op_writelog { uint32_t pm_userdata; }; /* * OP GETMSR * * Retrieve the machine specific address assoicated with the allocated * PMC. This number can be used subsequently with a read-performance-counter * instruction. */ struct pmc_op_getmsr { uint32_t pm_msr; /* machine specific address */ pmc_id_t pm_pmcid; /* allocated pmc id */ }; /* * OP GETDYNEVENTINFO * * Retrieve a PMC dynamic class events list. */ struct pmc_dyn_event_descr { char pm_ev_name[PMC_NAME_MAX]; enum pmc_event pm_ev_code; }; struct pmc_op_getdyneventinfo { enum pmc_class pm_class; unsigned int pm_nevent; struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; }; #ifdef _KERNEL #include #include #include #define PMC_HASH_SIZE 16 #define PMC_MTXPOOL_SIZE 32 #define PMC_LOG_BUFFER_SIZE 4 #define PMC_NLOGBUFFERS 64 #define PMC_NSAMPLES 512 #define PMC_CALLCHAIN_DEPTH 8 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." /* * Locking keys * * (b) - pmc_bufferlist_mtx (spin lock) * (k) - pmc_kthread_mtx (sleep lock) * (o) - po->po_mtx (spin lock) */ /* * PMC commands */ struct pmc_syscall_args { uint32_t pmop_code; /* one of PMC_OP_* */ void *pmop_data; /* syscall parameter */ }; /* * Interface to processor specific s1tuff */ /* * struct pmc_descr * * Machine independent (i.e., the common parts) of a human readable * PMC description. */ struct pmc_descr { char pd_name[PMC_NAME_MAX]; /* name */ uint32_t pd_caps; /* capabilities */ enum pmc_class pd_class; /* class of the PMC */ uint32_t pd_width; /* width in bits */ }; /* * struct pmc_target * * This structure records all the target processes associated with a * PMC. */ struct pmc_target { LIST_ENTRY(pmc_target) pt_next; struct pmc_process *pt_process; /* target descriptor */ }; /* * struct pmc * * Describes each allocated PMC. * * Each PMC has precisely one owner, namely the process that allocated * the PMC. * * A PMC may be attached to multiple target processes. The * 'pm_targets' field links all the target processes being monitored * by this PMC. * * The 'pm_savedvalue' field is protected by a mutex. * * On a multi-cpu machine, multiple target threads associated with a * process-virtual PMC could be concurrently executing on different * CPUs. The 'pm_runcount' field is atomically incremented every time * the PMC gets scheduled on a CPU and atomically decremented when it * get descheduled. Deletion of a PMC is only permitted when this * field is '0'. * */ struct pmc { LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ LIST_ENTRY(pmc) pm_next; /* owner's list */ /* * System-wide PMCs are allocated on a CPU and are not moved * around. For system-wide PMCs we record the CPU the PMC was * allocated on in the 'CPU' field of the pmc ID. * * Virtual PMCs run on whichever CPU is currently executing * their targets' threads. For these PMCs we need to save * their current PMC counter values when they are taken off * CPU. */ union { pmc_value_t pm_savedvalue; /* Virtual PMCS */ } pm_gv; /* * For sampling mode PMCs, we keep track of the PMC's "reload * count", which is the counter value to be loaded in when * arming the PMC for the next counting session. For counting * modes on PMCs that are read-only (e.g., the x86 TSC), we * keep track of the initial value at the start of * counting-mode operation. */ union { pmc_value_t pm_reloadcount; /* sampling PMC modes */ pmc_value_t pm_initial; /* counting PMC modes */ } pm_sc; uint32_t pm_stalled; /* marks stalled sampling PMCs */ uint32_t pm_caps; /* PMC capabilities */ enum pmc_event pm_event; /* event being measured */ uint32_t pm_flags; /* additional flags PMC_F_... */ struct pmc_owner *pm_owner; /* owner thread state */ int pm_runcount; /* #cpus currently on */ enum pmc_state pm_state; /* current PMC state */ /* * The PMC ID field encodes the row-index for the PMC, its * mode, class and the CPU# associated with the PMC. */ pmc_id_t pm_id; /* allocated PMC id */ /* md extensions */ union pmc_md_pmc pm_md; }; /* * Accessor macros for 'struct pmc' */ #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) /* * struct pmc_process * * Record a 'target' process being profiled. * * The target process being profiled could be different from the owner * process which allocated the PMCs. Each target process descriptor * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' * array. The size of this structure is thus PMC architecture * dependent. * */ struct pmc_targetstate { struct pmc *pp_pmc; /* target PMC */ pmc_value_t pp_pmcval; /* per-process value */ }; struct pmc_process { LIST_ENTRY(pmc_process) pp_next; /* hash chain */ int pp_refcnt; /* reference count */ uint32_t pp_flags; /* flags PMC_PP_* */ struct proc *pp_proc; /* target thread */ struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ }; #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 /* * struct pmc_owner * * We associate a PMC with an 'owner' process. * * A process can be associated with 0..NCPUS*NHWPMC PMCs during its * lifetime, where NCPUS is the numbers of CPUS in the system and * NHWPMC is the number of hardware PMCs per CPU. These are * maintained in the list headed by the 'po_pmcs' to save on space. * */ struct pmc_owner { LIST_ENTRY(pmc_owner) po_next; /* hash chain */ LIST_ENTRY(pmc_owner) po_ssnext; /* list of SS PMC owners */ LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ struct mtx po_mtx; /* spin lock for (o) */ struct proc *po_owner; /* owner proc */ uint32_t po_flags; /* (k) flags PMC_PO_* */ struct proc *po_kthread; /* (k) helper kthread */ struct pmclog_buffer *po_curbuf; /* current log buffer */ struct file *po_file; /* file reference */ int po_error; /* recorded error */ short po_sscount; /* # SS PMCs owned */ short po_logprocmaps; /* global mappings done */ }; #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 /* * struct pmc_hw -- describe the state of the PMC hardware * * When in use, a HW PMC is associated with one allocated 'struct pmc' * pointed to by field 'phw_pmc'. When inactive, this field is NULL. * * On an SMP box, one or more HW PMC's in process virtual mode with * the same 'phw_pmc' could be executing on different CPUs. In order * to handle this case correctly, we need to ensure that only * incremental counts get added to the saved value in the associated * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC * value at the time the hardware is started during this context * switch (i.e., the difference between the new (hardware) count and * the saved count is atomically added to the count field in 'struct * pmc' at context switch time). * */ struct pmc_hw { uint32_t phw_state; /* see PHW_* macros below */ struct pmc *phw_pmc; /* current thread PMC */ }; #define PMC_PHW_RI_MASK 0x000000FF #define PMC_PHW_CPU_SHIFT 8 #define PMC_PHW_CPU_MASK 0x0000FF00 #define PMC_PHW_FLAGS_SHIFT 16 #define PMC_PHW_FLAGS_MASK 0xFFFF0000 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ PMC_PHW_CPU_MASK) #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ PMC_PHW_CPU_SHIFT) #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ PMC_PHW_FLAGS_MASK) #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ PMC_PHW_FLAGS_SHIFT) #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) /* * struct pmc_sample * * Space for N (tunable) PC samples and associated control data. */ struct pmc_sample { uint16_t ps_nsamples; /* callchain depth */ uint8_t ps_cpu; /* cpu number */ uint8_t ps_flags; /* other flags */ pid_t ps_pid; /* process PID or -1 */ struct thread *ps_td; /* which thread */ struct pmc *ps_pmc; /* interrupting PMC */ uintptr_t *ps_pc; /* (const) callchain start */ }; #define PMC_SAMPLE_FREE ((uint16_t) 0) #define PMC_SAMPLE_INUSE ((uint16_t) 0xFFFF) struct pmc_samplebuffer { struct pmc_sample * volatile ps_read; /* read pointer */ struct pmc_sample * volatile ps_write; /* write pointer */ uintptr_t *ps_callchains; /* all saved call chains */ struct pmc_sample *ps_fence; /* one beyond ps_samples[] */ struct pmc_sample ps_samples[]; /* array of sample entries */ }; /* * struct pmc_cpustate * * A CPU is modelled as a collection of HW PMCs with space for additional * flags. */ struct pmc_cpu { uint32_t pc_state; /* physical cpu number + flags */ struct pmc_samplebuffer *pc_sb[2]; /* space for samples */ struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ }; #define PMC_PCPU_CPU_MASK 0x000000FF #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 #define PMC_PCPU_FLAGS_SHIFT 8 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) /* * struct pmc_binding * * CPU binding information. */ struct pmc_binding { int pb_bound; /* is bound? */ int pb_cpu; /* if so, to which CPU */ }; struct pmc_mdep; /* * struct pmc_classdep * * PMC class-dependent operations. */ struct pmc_classdep { uint32_t pcd_caps; /* class capabilities */ enum pmc_class pcd_class; /* class id */ int pcd_num; /* number of PMCs */ int pcd_ri; /* row index of the first PMC in class */ int pcd_width; /* width of the PMC */ /* configuring/reading/writing the hardware PMCs */ int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value); int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value); /* pmc allocation/release */ int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, const struct pmc_op_pmcallocate *_a); int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); /* starting and stopping PMCs */ int (*pcd_start_pmc)(int _cpu, int _ri); int (*pcd_stop_pmc)(int _cpu, int _ri); /* description */ int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, struct pmc **_ppmc); /* class-dependent initialization & finalization */ int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); /* machine-specific interface */ int (*pcd_get_msr)(int _ri, uint32_t *_msr); }; /* * struct pmc_mdep * * Machine dependent bits needed per CPU type. */ struct pmc_mdep { uint32_t pmd_cputype; /* from enum pmc_cputype */ uint32_t pmd_npmc; /* number of PMCs per CPU */ uint32_t pmd_nclass; /* number of PMC classes present */ /* * Machine dependent methods. */ /* per-cpu initialization and finalization */ int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu); int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); /* thread context switch in/out */ int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); /* handle a PMC interrupt */ int (*pmd_intr)(int _cpu, struct trapframe *_tf); /* * PMC class dependent information. */ struct pmc_classdep pmd_classdep[]; }; /* * Per-CPU state. This is an array of 'mp_ncpu' pointers * to struct pmc_cpu descriptors. */ extern struct pmc_cpu **pmc_pcpu; /* driver statistics */ extern struct pmc_op_getdriverstats pmc_stats; #if defined(DEBUG) /* debug flags, major flag groups */ struct pmc_debugflags { int pdb_CPU; int pdb_CSW; int pdb_LOG; int pdb_MDP; int pdb_MOD; int pdb_OWN; int pdb_PMC; int pdb_PRC; int pdb_SAM; }; extern struct pmc_debugflags pmc_debugflags; #define PMC_DEBUG_STRSIZE 128 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0 } #define PMCDBG(M,N,L,F,...) do { \ if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ printf(#M ":" #N ":" #L ": " F "\n", __VA_ARGS__); \ } while (0) /* Major numbers */ #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ #define PMC_DEBUG_MAJ_CSW 1 /* context switches */ #define PMC_DEBUG_MAJ_LOG 2 /* logging */ #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ #define PMC_DEBUG_MAJ_OWN 5 /* owner */ #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ #define PMC_DEBUG_MAJ_PRC 7 /* processes */ #define PMC_DEBUG_MAJ_SAM 8 /* sampling */ /* Minor numbers */ /* Common (8 bits) */ #define PMC_DEBUG_MIN_ALL 0 /* allocation */ #define PMC_DEBUG_MIN_REL 1 /* release */ #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ #define PMC_DEBUG_MIN_INI 3 /* init */ #define PMC_DEBUG_MIN_FND 4 /* find */ /* MODULE */ #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ /* OWN */ #define PMC_DEBUG_MIN_ORM 8 /* owner remove */ #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ /* PROCESSES */ #define PMC_DEBUG_MIN_TLK 8 /* link target */ #define PMC_DEBUG_MIN_TUL 9 /* unlink target */ #define PMC_DEBUG_MIN_EXT 10 /* process exit */ #define PMC_DEBUG_MIN_EXC 11 /* process exec */ #define PMC_DEBUG_MIN_FRK 12 /* process fork */ #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ #define PMC_DEBUG_MIN_SIG 14 /* signalling */ /* CONTEXT SWITCHES */ #define PMC_DEBUG_MIN_SWI 8 /* switch in */ #define PMC_DEBUG_MIN_SWO 9 /* switch out */ /* PMC */ #define PMC_DEBUG_MIN_REG 8 /* pmc register */ #define PMC_DEBUG_MIN_ALR 9 /* allocate row */ /* MACHINE DEPENDENT LAYER */ #define PMC_DEBUG_MIN_REA 8 /* read */ #define PMC_DEBUG_MIN_WRI 9 /* write */ #define PMC_DEBUG_MIN_CFG 10 /* config */ #define PMC_DEBUG_MIN_STA 11 /* start */ #define PMC_DEBUG_MIN_STO 12 /* stop */ #define PMC_DEBUG_MIN_INT 13 /* interrupts */ /* CPU */ #define PMC_DEBUG_MIN_BND 8 /* bind */ #define PMC_DEBUG_MIN_SEL 9 /* select */ /* LOG */ #define PMC_DEBUG_MIN_GTB 8 /* get buf */ #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ #define PMC_DEBUG_MIN_FLS 10 /* flush */ #define PMC_DEBUG_MIN_SAM 11 /* sample */ #define PMC_DEBUG_MIN_CLO 12 /* close */ #else #define PMCDBG(M,N,L,F,...) /* nothing */ #endif /* declare a dedicated memory pool */ MALLOC_DECLARE(M_PMC); /* * Functions */ struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ int pmc_getrowdisp(int _ri); int pmc_process_interrupt(int _cpu, int _soft, struct pmc *_pm, struct trapframe *_tf, int _inuserspace); int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, struct trapframe *_tf); int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, struct trapframe *_tf); struct pmc_mdep *pmc_mdep_alloc(int nclasses); void pmc_mdep_free(struct pmc_mdep *md); #endif /* _KERNEL */ #endif /* _SYS_PMC_H_ */ Index: stable/9/sys =================================================================== --- stable/9/sys (revision 242593) +++ stable/9/sys (revision 242594) Property changes on: stable/9/sys ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys:r241738,241741