Index: head/sys/dev/agp/agp.c =================================================================== --- head/sys/dev/agp/agp.c (revision 235781) +++ head/sys/dev/agp/agp.c (revision 235782) @@ -1,988 +1,998 @@ /*- * Copyright (c) 2000 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_agp.h" #include "opt_bus.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include MODULE_VERSION(agp, 1); MALLOC_DEFINE(M_AGP, "agp", "AGP data structures"); /* agp_drv.c */ static d_open_t agp_open; static d_close_t agp_close; static d_ioctl_t agp_ioctl; static d_mmap_t agp_mmap; static struct cdevsw agp_cdevsw = { .d_version = D_VERSION, .d_flags = D_NEEDGIANT, .d_open = agp_open, .d_close = agp_close, .d_ioctl = agp_ioctl, .d_mmap = agp_mmap, .d_name = "agp", }; static devclass_t agp_devclass; /* Helper functions for implementing chipset mini drivers. */ void agp_flush_cache() { #if defined(__i386__) || defined(__amd64__) wbinvd(); #endif } u_int8_t agp_find_caps(device_t dev) { int capreg; if (pci_find_cap(dev, PCIY_AGP, &capreg) != 0) capreg = 0; return (capreg); } /* * Find an AGP display device (if any). */ static device_t agp_find_display(void) { devclass_t pci = devclass_find("pci"); device_t bus, dev = 0; device_t *kids; int busnum, numkids, i; for (busnum = 0; busnum < devclass_get_maxunit(pci); busnum++) { bus = devclass_get_device(pci, busnum); if (!bus) continue; if (device_get_children(bus, &kids, &numkids) != 0) continue; for (i = 0; i < numkids; i++) { dev = kids[i]; if (pci_get_class(dev) == PCIC_DISPLAY && pci_get_subclass(dev) == PCIS_DISPLAY_VGA) if (agp_find_caps(dev)) { free(kids, M_TEMP); return dev; } } free(kids, M_TEMP); } return 0; } struct agp_gatt * agp_alloc_gatt(device_t dev) { u_int32_t apsize = AGP_GET_APERTURE(dev); u_int32_t entries = apsize >> AGP_PAGE_SHIFT; struct agp_gatt *gatt; if (bootverbose) device_printf(dev, "allocating GATT for aperture of size %dM\n", apsize / (1024*1024)); if (entries == 0) { device_printf(dev, "bad aperture size\n"); return NULL; } gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_NOWAIT); if (!gatt) return 0; gatt->ag_entries = entries; gatt->ag_virtual = contigmalloc(entries * sizeof(u_int32_t), M_AGP, 0, 0, ~0, PAGE_SIZE, 0); if (!gatt->ag_virtual) { if (bootverbose) device_printf(dev, "contiguous allocation failed\n"); free(gatt, M_AGP); return 0; } bzero(gatt->ag_virtual, entries * sizeof(u_int32_t)); gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); agp_flush_cache(); return gatt; } void agp_free_gatt(struct agp_gatt *gatt) { contigfree(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t), M_AGP); free(gatt, M_AGP); } static u_int agp_max[][2] = { {0, 0}, {32, 4}, {64, 28}, {128, 96}, {256, 204}, {512, 440}, {1024, 942}, {2048, 1920}, {4096, 3932} }; #define agp_max_size (sizeof(agp_max) / sizeof(agp_max[0])) /** * Sets the PCI resource which represents the AGP aperture. * * If not called, the default AGP aperture resource of AGP_APBASE will * be used. Must be called before agp_generic_attach(). */ void agp_set_aperture_resource(device_t dev, int rid) { struct agp_softc *sc = device_get_softc(dev); sc->as_aperture_rid = rid; } int agp_generic_attach(device_t dev) { struct agp_softc *sc = device_get_softc(dev); int i; u_int memsize; /* * Find and map the aperture, RF_SHAREABLE for DRM but not RF_ACTIVE * because the kernel doesn't need to map it. */ if (sc->as_aperture_rid != -1) { if (sc->as_aperture_rid == 0) sc->as_aperture_rid = AGP_APBASE; sc->as_aperture = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->as_aperture_rid, RF_SHAREABLE); if (!sc->as_aperture) return ENOMEM; } /* * Work out an upper bound for agp memory allocation. This * uses a heurisitc table from the Linux driver. */ memsize = ptoa(Maxmem) >> 20; for (i = 0; i < agp_max_size; i++) { if (memsize <= agp_max[i][0]) break; } - if (i == agp_max_size) i = agp_max_size - 1; + if (i == agp_max_size) + i = agp_max_size - 1; sc->as_maxmem = agp_max[i][1] << 20U; /* * The lock is used to prevent re-entry to * agp_generic_bind_memory() since that function can sleep. */ mtx_init(&sc->as_lock, "agp lock", NULL, MTX_DEF); /* * Initialise stuff for the userland device. */ agp_devclass = devclass_find("agp"); TAILQ_INIT(&sc->as_memory); sc->as_nextid = 1; sc->as_devnode = make_dev(&agp_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "agpgart"); sc->as_devnode->si_drv1 = dev; return 0; } void agp_free_cdev(device_t dev) { struct agp_softc *sc = device_get_softc(dev); destroy_dev(sc->as_devnode); } void agp_free_res(device_t dev) { struct agp_softc *sc = device_get_softc(dev); if (sc->as_aperture != NULL) bus_release_resource(dev, SYS_RES_MEMORY, sc->as_aperture_rid, sc->as_aperture); mtx_destroy(&sc->as_lock); agp_flush_cache(); } int agp_generic_detach(device_t dev) { agp_free_cdev(dev); agp_free_res(dev); return 0; } /** * Default AGP aperture size detection which simply returns the size of * the aperture's PCI resource. */ u_int32_t agp_generic_get_aperture(device_t dev) { struct agp_softc *sc = device_get_softc(dev); return rman_get_size(sc->as_aperture); } /** * Default AGP aperture size setting function, which simply doesn't allow * changes to resource size. */ int agp_generic_set_aperture(device_t dev, u_int32_t aperture) { u_int32_t current_aperture; current_aperture = AGP_GET_APERTURE(dev); if (current_aperture != aperture) return EINVAL; else return 0; } /* * This does the enable logic for v3, with the same topology * restrictions as in place for v2 -- one bus, one device on the bus. */ static int agp_v3_enable(device_t dev, device_t mdev, u_int32_t mode) { u_int32_t tstatus, mstatus; u_int32_t command; int rq, sba, fw, rate, arqsz, cal; tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4); mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4); /* Set RQ to the min of mode, tstatus and mstatus */ rq = AGP_MODE_GET_RQ(mode); if (AGP_MODE_GET_RQ(tstatus) < rq) rq = AGP_MODE_GET_RQ(tstatus); if (AGP_MODE_GET_RQ(mstatus) < rq) rq = AGP_MODE_GET_RQ(mstatus); /* * ARQSZ - Set the value to the maximum one. * Don't allow the mode register to override values. */ arqsz = AGP_MODE_GET_ARQSZ(mode); if (AGP_MODE_GET_ARQSZ(tstatus) > rq) rq = AGP_MODE_GET_ARQSZ(tstatus); if (AGP_MODE_GET_ARQSZ(mstatus) > rq) rq = AGP_MODE_GET_ARQSZ(mstatus); /* Calibration cycle - don't allow override by mode register */ cal = AGP_MODE_GET_CAL(tstatus); if (AGP_MODE_GET_CAL(mstatus) < cal) cal = AGP_MODE_GET_CAL(mstatus); /* SBA must be supported for AGP v3. */ sba = 1; /* Set FW if all three support it. */ fw = (AGP_MODE_GET_FW(tstatus) & AGP_MODE_GET_FW(mstatus) & AGP_MODE_GET_FW(mode)); /* Figure out the max rate */ rate = (AGP_MODE_GET_RATE(tstatus) & AGP_MODE_GET_RATE(mstatus) & AGP_MODE_GET_RATE(mode)); if (rate & AGP_MODE_V3_RATE_8x) rate = AGP_MODE_V3_RATE_8x; else rate = AGP_MODE_V3_RATE_4x; if (bootverbose) device_printf(dev, "Setting AGP v3 mode %d\n", rate * 4); pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, 0, 4); /* Construct the new mode word and tell the hardware */ command = 0; command = AGP_MODE_SET_RQ(0, rq); command = AGP_MODE_SET_ARQSZ(command, arqsz); command = AGP_MODE_SET_CAL(command, cal); command = AGP_MODE_SET_SBA(command, sba); command = AGP_MODE_SET_FW(command, fw); command = AGP_MODE_SET_RATE(command, rate); command = AGP_MODE_SET_MODE_3(command, 1); command = AGP_MODE_SET_AGP(command, 1); pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, command, 4); pci_write_config(mdev, agp_find_caps(mdev) + AGP_COMMAND, command, 4); return 0; } static int agp_v2_enable(device_t dev, device_t mdev, u_int32_t mode) { u_int32_t tstatus, mstatus; u_int32_t command; int rq, sba, fw, rate; tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4); mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4); /* Set RQ to the min of mode, tstatus and mstatus */ rq = AGP_MODE_GET_RQ(mode); if (AGP_MODE_GET_RQ(tstatus) < rq) rq = AGP_MODE_GET_RQ(tstatus); if (AGP_MODE_GET_RQ(mstatus) < rq) rq = AGP_MODE_GET_RQ(mstatus); /* Set SBA if all three can deal with SBA */ sba = (AGP_MODE_GET_SBA(tstatus) & AGP_MODE_GET_SBA(mstatus) & AGP_MODE_GET_SBA(mode)); /* Similar for FW */ fw = (AGP_MODE_GET_FW(tstatus) & AGP_MODE_GET_FW(mstatus) & AGP_MODE_GET_FW(mode)); /* Figure out the max rate */ rate = (AGP_MODE_GET_RATE(tstatus) & AGP_MODE_GET_RATE(mstatus) & AGP_MODE_GET_RATE(mode)); if (rate & AGP_MODE_V2_RATE_4x) rate = AGP_MODE_V2_RATE_4x; else if (rate & AGP_MODE_V2_RATE_2x) rate = AGP_MODE_V2_RATE_2x; else rate = AGP_MODE_V2_RATE_1x; if (bootverbose) device_printf(dev, "Setting AGP v2 mode %d\n", rate); /* Construct the new mode word and tell the hardware */ command = 0; command = AGP_MODE_SET_RQ(0, rq); command = AGP_MODE_SET_SBA(command, sba); command = AGP_MODE_SET_FW(command, fw); command = AGP_MODE_SET_RATE(command, rate); command = AGP_MODE_SET_AGP(command, 1); pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, command, 4); pci_write_config(mdev, agp_find_caps(mdev) + AGP_COMMAND, command, 4); return 0; } int agp_generic_enable(device_t dev, u_int32_t mode) { device_t mdev = agp_find_display(); u_int32_t tstatus, mstatus; if (!mdev) { AGP_DPF("can't find display\n"); return ENXIO; } tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4); mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4); /* * Check display and bridge for AGP v3 support. AGP v3 allows * more variety in topology than v2, e.g. multiple AGP devices * attached to one bridge, or multiple AGP bridges in one * system. This doesn't attempt to address those situations, * but should work fine for a classic single AGP slot system * with AGP v3. */ if (AGP_MODE_GET_MODE_3(mode) && AGP_MODE_GET_MODE_3(tstatus) && AGP_MODE_GET_MODE_3(mstatus)) return (agp_v3_enable(dev, mdev, mode)); else return (agp_v2_enable(dev, mdev, mode)); } struct agp_memory * agp_generic_alloc_memory(device_t dev, int type, vm_size_t size) { struct agp_softc *sc = device_get_softc(dev); struct agp_memory *mem; if ((size & (AGP_PAGE_SIZE - 1)) != 0) return 0; if (sc->as_allocated + size > sc->as_maxmem) return 0; if (type != 0) { printf("agp_generic_alloc_memory: unsupported type %d\n", type); return 0; } mem = malloc(sizeof *mem, M_AGP, M_WAITOK); mem->am_id = sc->as_nextid++; mem->am_size = size; mem->am_type = 0; mem->am_obj = vm_object_allocate(OBJT_DEFAULT, atop(round_page(size))); mem->am_physical = 0; mem->am_offset = 0; mem->am_is_bound = 0; TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link); sc->as_allocated += size; return mem; } int agp_generic_free_memory(device_t dev, struct agp_memory *mem) { struct agp_softc *sc = device_get_softc(dev); if (mem->am_is_bound) return EBUSY; sc->as_allocated -= mem->am_size; TAILQ_REMOVE(&sc->as_memory, mem, am_link); vm_object_deallocate(mem->am_obj); free(mem, M_AGP); return 0; } int agp_generic_bind_memory(device_t dev, struct agp_memory *mem, vm_offset_t offset) { struct agp_softc *sc = device_get_softc(dev); vm_offset_t i, j, k; vm_page_t m; int error; /* Do some sanity checks first. */ if ((offset & (AGP_PAGE_SIZE - 1)) != 0 || offset + mem->am_size > AGP_GET_APERTURE(dev)) { device_printf(dev, "binding memory at bad offset %#x\n", (int)offset); return EINVAL; } /* * Allocate the pages early, before acquiring the lock, * because vm_page_grab() may sleep and we can't hold a mutex * while sleeping. */ VM_OBJECT_LOCK(mem->am_obj); for (i = 0; i < mem->am_size; i += PAGE_SIZE) { /* * Find a page from the object and wire it * down. This page will be mapped using one or more * entries in the GATT (assuming that PAGE_SIZE >= * AGP_PAGE_SIZE. If this is the first call to bind, * the pages will be allocated and zeroed. */ m = vm_page_grab(mem->am_obj, OFF_TO_IDX(i), VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY); AGP_DPF("found page pa=%#jx\n", (uintmax_t)VM_PAGE_TO_PHYS(m)); } VM_OBJECT_UNLOCK(mem->am_obj); mtx_lock(&sc->as_lock); if (mem->am_is_bound) { device_printf(dev, "memory already bound\n"); error = EINVAL; VM_OBJECT_LOCK(mem->am_obj); i = 0; goto bad; } /* * Bind the individual pages and flush the chipset's * TLB. */ VM_OBJECT_LOCK(mem->am_obj); for (i = 0; i < mem->am_size; i += PAGE_SIZE) { m = vm_page_lookup(mem->am_obj, OFF_TO_IDX(i)); /* * Install entries in the GATT, making sure that if * AGP_PAGE_SIZE < PAGE_SIZE and mem->am_size is not * aligned to PAGE_SIZE, we don't modify too many GATT * entries. */ for (j = 0; j < PAGE_SIZE && i + j < mem->am_size; j += AGP_PAGE_SIZE) { vm_offset_t pa = VM_PAGE_TO_PHYS(m) + j; AGP_DPF("binding offset %#jx to pa %#jx\n", (uintmax_t)offset + i + j, (uintmax_t)pa); error = AGP_BIND_PAGE(dev, offset + i + j, pa); if (error) { /* * Bail out. Reverse all the mappings * and unwire the pages. */ for (k = 0; k < i + j; k += AGP_PAGE_SIZE) AGP_UNBIND_PAGE(dev, offset + k); goto bad; } } vm_page_wakeup(m); } VM_OBJECT_UNLOCK(mem->am_obj); /* * Flush the cpu cache since we are providing a new mapping * for these pages. */ agp_flush_cache(); /* * Make sure the chipset gets the new mappings. */ AGP_FLUSH_TLB(dev); mem->am_offset = offset; mem->am_is_bound = 1; mtx_unlock(&sc->as_lock); return 0; bad: mtx_unlock(&sc->as_lock); VM_OBJECT_LOCK_ASSERT(mem->am_obj, MA_OWNED); for (k = 0; k < mem->am_size; k += PAGE_SIZE) { m = vm_page_lookup(mem->am_obj, OFF_TO_IDX(k)); if (k >= i) vm_page_wakeup(m); vm_page_lock(m); vm_page_unwire(m, 0); vm_page_unlock(m); } VM_OBJECT_UNLOCK(mem->am_obj); return error; } int agp_generic_unbind_memory(device_t dev, struct agp_memory *mem) { struct agp_softc *sc = device_get_softc(dev); vm_page_t m; int i; mtx_lock(&sc->as_lock); if (!mem->am_is_bound) { device_printf(dev, "memory is not bound\n"); mtx_unlock(&sc->as_lock); return EINVAL; } /* * Unbind the individual pages and flush the chipset's * TLB. Unwire the pages so they can be swapped. */ for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) AGP_UNBIND_PAGE(dev, mem->am_offset + i); VM_OBJECT_LOCK(mem->am_obj); for (i = 0; i < mem->am_size; i += PAGE_SIZE) { m = vm_page_lookup(mem->am_obj, atop(i)); vm_page_lock(m); vm_page_unwire(m, 0); vm_page_unlock(m); } VM_OBJECT_UNLOCK(mem->am_obj); agp_flush_cache(); AGP_FLUSH_TLB(dev); mem->am_offset = 0; mem->am_is_bound = 0; mtx_unlock(&sc->as_lock); return 0; } /* Helper functions for implementing user/kernel api */ static int agp_acquire_helper(device_t dev, enum agp_acquire_state state) { struct agp_softc *sc = device_get_softc(dev); if (sc->as_state != AGP_ACQUIRE_FREE) return EBUSY; sc->as_state = state; return 0; } static int agp_release_helper(device_t dev, enum agp_acquire_state state) { struct agp_softc *sc = device_get_softc(dev); if (sc->as_state == AGP_ACQUIRE_FREE) return 0; if (sc->as_state != state) return EBUSY; sc->as_state = AGP_ACQUIRE_FREE; return 0; } static struct agp_memory * agp_find_memory(device_t dev, int id) { struct agp_softc *sc = device_get_softc(dev); struct agp_memory *mem; AGP_DPF("searching for memory block %d\n", id); TAILQ_FOREACH(mem, &sc->as_memory, am_link) { AGP_DPF("considering memory block %d\n", mem->am_id); if (mem->am_id == id) return mem; } return 0; } /* Implementation of the userland ioctl api */ static int agp_info_user(device_t dev, agp_info *info) { struct agp_softc *sc = device_get_softc(dev); bzero(info, sizeof *info); info->bridge_id = pci_get_devid(dev); info->agp_mode = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4); if (sc->as_aperture) info->aper_base = rman_get_start(sc->as_aperture); else info->aper_base = 0; info->aper_size = AGP_GET_APERTURE(dev) >> 20; info->pg_total = info->pg_system = sc->as_maxmem >> AGP_PAGE_SHIFT; info->pg_used = sc->as_allocated >> AGP_PAGE_SHIFT; return 0; } static int agp_setup_user(device_t dev, agp_setup *setup) { return AGP_ENABLE(dev, setup->agp_mode); } static int agp_allocate_user(device_t dev, agp_allocate *alloc) { struct agp_memory *mem; mem = AGP_ALLOC_MEMORY(dev, alloc->type, alloc->pg_count << AGP_PAGE_SHIFT); if (mem) { alloc->key = mem->am_id; alloc->physical = mem->am_physical; return 0; } else { return ENOMEM; } } static int agp_deallocate_user(device_t dev, int id) { struct agp_memory *mem = agp_find_memory(dev, id); if (mem) { AGP_FREE_MEMORY(dev, mem); return 0; } else { return ENOENT; } } static int agp_bind_user(device_t dev, agp_bind *bind) { struct agp_memory *mem = agp_find_memory(dev, bind->key); if (!mem) return ENOENT; return AGP_BIND_MEMORY(dev, mem, bind->pg_start << AGP_PAGE_SHIFT); } static int agp_unbind_user(device_t dev, agp_unbind *unbind) { struct agp_memory *mem = agp_find_memory(dev, unbind->key); if (!mem) return ENOENT; return AGP_UNBIND_MEMORY(dev, mem); } static int +agp_chipset_flush(device_t dev) +{ + + return (AGP_CHIPSET_FLUSH(dev)); +} + +static int agp_open(struct cdev *kdev, int oflags, int devtype, struct thread *td) { device_t dev = kdev->si_drv1; struct agp_softc *sc = device_get_softc(dev); if (!sc->as_isopen) { sc->as_isopen = 1; device_busy(dev); } return 0; } static int agp_close(struct cdev *kdev, int fflag, int devtype, struct thread *td) { device_t dev = kdev->si_drv1; struct agp_softc *sc = device_get_softc(dev); struct agp_memory *mem; /* * Clear the GATT and force release on last close */ while ((mem = TAILQ_FIRST(&sc->as_memory)) != 0) { if (mem->am_is_bound) AGP_UNBIND_MEMORY(dev, mem); AGP_FREE_MEMORY(dev, mem); } if (sc->as_state == AGP_ACQUIRE_USER) agp_release_helper(dev, AGP_ACQUIRE_USER); sc->as_isopen = 0; device_unbusy(dev); return 0; } static int agp_ioctl(struct cdev *kdev, u_long cmd, caddr_t data, int fflag, struct thread *td) { device_t dev = kdev->si_drv1; switch (cmd) { case AGPIOC_INFO: return agp_info_user(dev, (agp_info *) data); case AGPIOC_ACQUIRE: return agp_acquire_helper(dev, AGP_ACQUIRE_USER); case AGPIOC_RELEASE: return agp_release_helper(dev, AGP_ACQUIRE_USER); case AGPIOC_SETUP: return agp_setup_user(dev, (agp_setup *)data); case AGPIOC_ALLOCATE: return agp_allocate_user(dev, (agp_allocate *)data); case AGPIOC_DEALLOCATE: return agp_deallocate_user(dev, *(int *) data); case AGPIOC_BIND: return agp_bind_user(dev, (agp_bind *)data); case AGPIOC_UNBIND: return agp_unbind_user(dev, (agp_unbind *)data); + case AGPIOC_CHIPSET_FLUSH: + return agp_chipset_flush(dev); } return EINVAL; } static int agp_mmap(struct cdev *kdev, vm_ooffset_t offset, vm_paddr_t *paddr, int prot, vm_memattr_t *memattr) { device_t dev = kdev->si_drv1; struct agp_softc *sc = device_get_softc(dev); if (offset > AGP_GET_APERTURE(dev)) return -1; if (sc->as_aperture == NULL) return -1; *paddr = rman_get_start(sc->as_aperture) + offset; return 0; } /* Implementation of the kernel api */ device_t agp_find_device() { device_t *children, child; int i, count; if (!agp_devclass) return NULL; if (devclass_get_devices(agp_devclass, &children, &count) != 0) return NULL; child = NULL; for (i = 0; i < count; i++) { if (device_is_attached(children[i])) { child = children[i]; break; } } free(children, M_TEMP); return child; } enum agp_acquire_state agp_state(device_t dev) { struct agp_softc *sc = device_get_softc(dev); return sc->as_state; } void agp_get_info(device_t dev, struct agp_info *info) { struct agp_softc *sc = device_get_softc(dev); info->ai_mode = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4); if (sc->as_aperture != NULL) info->ai_aperture_base = rman_get_start(sc->as_aperture); else info->ai_aperture_base = 0; info->ai_aperture_size = AGP_GET_APERTURE(dev); info->ai_memory_allowed = sc->as_maxmem; info->ai_memory_used = sc->as_allocated; } int agp_acquire(device_t dev) { return agp_acquire_helper(dev, AGP_ACQUIRE_KERNEL); } int agp_release(device_t dev) { return agp_release_helper(dev, AGP_ACQUIRE_KERNEL); } int agp_enable(device_t dev, u_int32_t mode) { return AGP_ENABLE(dev, mode); } void *agp_alloc_memory(device_t dev, int type, vm_size_t bytes) { return (void *) AGP_ALLOC_MEMORY(dev, type, bytes); } void agp_free_memory(device_t dev, void *handle) { struct agp_memory *mem = (struct agp_memory *) handle; AGP_FREE_MEMORY(dev, mem); } int agp_bind_memory(device_t dev, void *handle, vm_offset_t offset) { struct agp_memory *mem = (struct agp_memory *) handle; return AGP_BIND_MEMORY(dev, mem, offset); } int agp_unbind_memory(device_t dev, void *handle) { struct agp_memory *mem = (struct agp_memory *) handle; return AGP_UNBIND_MEMORY(dev, mem); } void agp_memory_info(device_t dev, void *handle, struct agp_memory_info *mi) { struct agp_memory *mem = (struct agp_memory *) handle; mi->ami_size = mem->am_size; mi->ami_physical = mem->am_physical; mi->ami_offset = mem->am_offset; mi->ami_is_bound = mem->am_is_bound; } Index: head/sys/dev/agp/agp_i810.c =================================================================== --- head/sys/dev/agp/agp_i810.c (revision 235781) +++ head/sys/dev/agp/agp_i810.c (revision 235782) @@ -1,1149 +1,2565 @@ /*- * Copyright (c) 2000 Doug Rabson * Copyright (c) 2000 Ruslan Ermilov + * Copyright (c) 2011 The FreeBSD Foundation * All rights reserved. * + * Portions of this software were developed by Konstantin Belousov + * under sponsorship from the FreeBSD Foundation. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Fixes for 830/845G support: David Dawes * 852GM/855GM/865G support added by David Dawes + * + * This is generic Intel GTT handling code, morphed from the AGP + * bridge code. */ #include __FBSDID("$FreeBSD$"); #include "opt_bus.h" +#if 0 +#define KTR_AGP_I810 KTR_DEV +#else +#define KTR_AGP_I810 0 +#endif + #include #include #include #include +#include #include #include #include #include #include #include #include +#include #include #include +#include #include #include #include #include #include #include #include #include #include MALLOC_DECLARE(M_AGP); +struct agp_i810_match; + +static int agp_i810_check_active(device_t bridge_dev); +static int agp_i830_check_active(device_t bridge_dev); +static int agp_i915_check_active(device_t bridge_dev); +static int agp_sb_check_active(device_t bridge_dev); + +static void agp_82852_set_desc(device_t dev, + const struct agp_i810_match *match); +static void agp_i810_set_desc(device_t dev, const struct agp_i810_match *match); + +static void agp_i810_dump_regs(device_t dev); +static void agp_i830_dump_regs(device_t dev); +static void agp_i855_dump_regs(device_t dev); +static void agp_i915_dump_regs(device_t dev); +static void agp_i965_dump_regs(device_t dev); +static void agp_sb_dump_regs(device_t dev); + +static int agp_i810_get_stolen_size(device_t dev); +static int agp_i830_get_stolen_size(device_t dev); +static int agp_i915_get_stolen_size(device_t dev); +static int agp_sb_get_stolen_size(device_t dev); + +static int agp_i810_get_gtt_mappable_entries(device_t dev); +static int agp_i830_get_gtt_mappable_entries(device_t dev); +static int agp_i915_get_gtt_mappable_entries(device_t dev); + +static int agp_i810_get_gtt_total_entries(device_t dev); +static int agp_i965_get_gtt_total_entries(device_t dev); +static int agp_gen5_get_gtt_total_entries(device_t dev); +static int agp_sb_get_gtt_total_entries(device_t dev); + +static int agp_i810_install_gatt(device_t dev); +static int agp_i830_install_gatt(device_t dev); + +static void agp_i810_deinstall_gatt(device_t dev); +static void agp_i830_deinstall_gatt(device_t dev); + +static void agp_i810_install_gtt_pte(device_t dev, u_int index, + vm_offset_t physical, int flags); +static void agp_i830_install_gtt_pte(device_t dev, u_int index, + vm_offset_t physical, int flags); +static void agp_i915_install_gtt_pte(device_t dev, u_int index, + vm_offset_t physical, int flags); +static void agp_i965_install_gtt_pte(device_t dev, u_int index, + vm_offset_t physical, int flags); +static void agp_g4x_install_gtt_pte(device_t dev, u_int index, + vm_offset_t physical, int flags); +static void agp_sb_install_gtt_pte(device_t dev, u_int index, + vm_offset_t physical, int flags); + +static void agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte); +static void agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte); +static void agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte); +static void agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte); +static void agp_sb_write_gtt(device_t dev, u_int index, uint32_t pte); + +static u_int32_t agp_i810_read_gtt_pte(device_t dev, u_int index); +static u_int32_t agp_i915_read_gtt_pte(device_t dev, u_int index); +static u_int32_t agp_i965_read_gtt_pte(device_t dev, u_int index); +static u_int32_t agp_g4x_read_gtt_pte(device_t dev, u_int index); + +static vm_paddr_t agp_i810_read_gtt_pte_paddr(device_t dev, u_int index); +static vm_paddr_t agp_i915_read_gtt_pte_paddr(device_t dev, u_int index); +static vm_paddr_t agp_sb_read_gtt_pte_paddr(device_t dev, u_int index); + +static int agp_i810_set_aperture(device_t dev, u_int32_t aperture); +static int agp_i830_set_aperture(device_t dev, u_int32_t aperture); +static int agp_i915_set_aperture(device_t dev, u_int32_t aperture); + +static int agp_i810_chipset_flush_setup(device_t dev); +static int agp_i915_chipset_flush_setup(device_t dev); +static int agp_i965_chipset_flush_setup(device_t dev); + +static void agp_i810_chipset_flush_teardown(device_t dev); +static void agp_i915_chipset_flush_teardown(device_t dev); +static void agp_i965_chipset_flush_teardown(device_t dev); + +static void agp_i810_chipset_flush(device_t dev); +static void agp_i830_chipset_flush(device_t dev); +static void agp_i915_chipset_flush(device_t dev); + enum { CHIP_I810, /* i810/i815 */ CHIP_I830, /* 830M/845G */ CHIP_I855, /* 852GM/855GM/865G */ CHIP_I915, /* 915G/915GM */ CHIP_I965, /* G965 */ CHIP_G33, /* G33/Q33/Q35 */ CHIP_IGD, /* Pineview */ CHIP_G4X, /* G45/Q45 */ + CHIP_SB, /* SandyBridge */ }; /* The i810 through i855 have the registers at BAR 1, and the GATT gets * allocated by us. The i915 has registers in BAR 0 and the GATT is at the * start of the stolen memory, and should only be accessed by the OS through * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB * is registers, second 512KB is GATT. */ static struct resource_spec agp_i810_res_spec[] = { { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE }, { -1, 0 } }; static struct resource_spec agp_i915_res_spec[] = { { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE }, { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE }, { -1, 0 } }; static struct resource_spec agp_i965_res_spec[] = { { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE }, { -1, 0 } }; +static struct resource_spec agp_g4x_res_spec[] = { + { SYS_RES_MEMORY, AGP_G4X_MMADR, RF_ACTIVE | RF_SHAREABLE }, + { SYS_RES_MEMORY, AGP_G4X_GTTADR, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + struct agp_i810_softc { struct agp_softc agp; u_int32_t initial_aperture; /* aperture size at startup */ struct agp_gatt *gatt; - int chiptype; /* i810-like or i830 */ u_int32_t dcache_size; /* i810 only */ - u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */ + u_int32_t stolen; /* number of i830/845 gtt + entries for stolen memory */ + u_int stolen_size; /* BIOS-reserved graphics memory */ + u_int gtt_total_entries; /* Total number of gtt ptes */ + u_int gtt_mappable_entries; /* Number of gtt ptes mappable by CPU */ device_t bdev; /* bridge device */ - void *argb_cursor; /* contigmalloc area for ARGB cursor */ - - struct resource_spec * sc_res_spec; struct resource *sc_res[2]; + const struct agp_i810_match *match; + int sc_flush_page_rid; + struct resource *sc_flush_page_res; + void *sc_flush_page_vaddr; + int sc_bios_allocated_flush_page; }; +static device_t intel_agp; + +struct agp_i810_driver { + int chiptype; + int gen; + int busdma_addr_mask_sz; + struct resource_spec *res_spec; + int (*check_active)(device_t); + void (*set_desc)(device_t, const struct agp_i810_match *); + void (*dump_regs)(device_t); + int (*get_stolen_size)(device_t); + int (*get_gtt_total_entries)(device_t); + int (*get_gtt_mappable_entries)(device_t); + int (*install_gatt)(device_t); + void (*deinstall_gatt)(device_t); + void (*write_gtt)(device_t, u_int, uint32_t); + void (*install_gtt_pte)(device_t, u_int, vm_offset_t, int); + u_int32_t (*read_gtt_pte)(device_t, u_int); + vm_paddr_t (*read_gtt_pte_paddr)(device_t , u_int); + int (*set_aperture)(device_t, u_int32_t); + int (*chipset_flush_setup)(device_t); + void (*chipset_flush_teardown)(device_t); + void (*chipset_flush)(device_t); +}; + +static const struct agp_i810_driver agp_i810_i810_driver = { + .chiptype = CHIP_I810, + .gen = 1, + .busdma_addr_mask_sz = 32, + .res_spec = agp_i810_res_spec, + .check_active = agp_i810_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i810_dump_regs, + .get_stolen_size = agp_i810_get_stolen_size, + .get_gtt_mappable_entries = agp_i810_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i810_get_gtt_total_entries, + .install_gatt = agp_i810_install_gatt, + .deinstall_gatt = agp_i810_deinstall_gatt, + .write_gtt = agp_i810_write_gtt, + .install_gtt_pte = agp_i810_install_gtt_pte, + .read_gtt_pte = agp_i810_read_gtt_pte, + .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, + .set_aperture = agp_i810_set_aperture, + .chipset_flush_setup = agp_i810_chipset_flush_setup, + .chipset_flush_teardown = agp_i810_chipset_flush_teardown, + .chipset_flush = agp_i810_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_i815_driver = { + .chiptype = CHIP_I810, + .gen = 2, + .busdma_addr_mask_sz = 32, + .res_spec = agp_i810_res_spec, + .check_active = agp_i810_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i810_dump_regs, + .get_stolen_size = agp_i810_get_stolen_size, + .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i810_get_gtt_total_entries, + .install_gatt = agp_i810_install_gatt, + .deinstall_gatt = agp_i810_deinstall_gatt, + .write_gtt = agp_i810_write_gtt, + .install_gtt_pte = agp_i810_install_gtt_pte, + .read_gtt_pte = agp_i810_read_gtt_pte, + .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, + .set_aperture = agp_i810_set_aperture, + .chipset_flush_setup = agp_i810_chipset_flush_setup, + .chipset_flush_teardown = agp_i810_chipset_flush_teardown, + .chipset_flush = agp_i830_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_i830_driver = { + .chiptype = CHIP_I830, + .gen = 2, + .busdma_addr_mask_sz = 32, + .res_spec = agp_i810_res_spec, + .check_active = agp_i830_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i830_dump_regs, + .get_stolen_size = agp_i830_get_stolen_size, + .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i810_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_i810_write_gtt, + .install_gtt_pte = agp_i830_install_gtt_pte, + .read_gtt_pte = agp_i810_read_gtt_pte, + .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, + .set_aperture = agp_i830_set_aperture, + .chipset_flush_setup = agp_i810_chipset_flush_setup, + .chipset_flush_teardown = agp_i810_chipset_flush_teardown, + .chipset_flush = agp_i830_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_i855_driver = { + .chiptype = CHIP_I855, + .gen = 2, + .busdma_addr_mask_sz = 32, + .res_spec = agp_i810_res_spec, + .check_active = agp_i830_check_active, + .set_desc = agp_82852_set_desc, + .dump_regs = agp_i855_dump_regs, + .get_stolen_size = agp_i915_get_stolen_size, + .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i810_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_i810_write_gtt, + .install_gtt_pte = agp_i830_install_gtt_pte, + .read_gtt_pte = agp_i810_read_gtt_pte, + .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, + .set_aperture = agp_i830_set_aperture, + .chipset_flush_setup = agp_i810_chipset_flush_setup, + .chipset_flush_teardown = agp_i810_chipset_flush_teardown, + .chipset_flush = agp_i830_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_i865_driver = { + .chiptype = CHIP_I855, + .gen = 2, + .busdma_addr_mask_sz = 32, + .res_spec = agp_i810_res_spec, + .check_active = agp_i830_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i855_dump_regs, + .get_stolen_size = agp_i915_get_stolen_size, + .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i810_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_i810_write_gtt, + .install_gtt_pte = agp_i830_install_gtt_pte, + .read_gtt_pte = agp_i810_read_gtt_pte, + .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr, + .set_aperture = agp_i915_set_aperture, + .chipset_flush_setup = agp_i810_chipset_flush_setup, + .chipset_flush_teardown = agp_i810_chipset_flush_teardown, + .chipset_flush = agp_i830_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_i915_driver = { + .chiptype = CHIP_I915, + .gen = 3, + .busdma_addr_mask_sz = 32, + .res_spec = agp_i915_res_spec, + .check_active = agp_i915_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i915_dump_regs, + .get_stolen_size = agp_i915_get_stolen_size, + .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i810_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_i915_write_gtt, + .install_gtt_pte = agp_i915_install_gtt_pte, + .read_gtt_pte = agp_i915_read_gtt_pte, + .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, + .set_aperture = agp_i915_set_aperture, + .chipset_flush_setup = agp_i915_chipset_flush_setup, + .chipset_flush_teardown = agp_i915_chipset_flush_teardown, + .chipset_flush = agp_i915_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_g965_driver = { + .chiptype = CHIP_I965, + .gen = 4, + .busdma_addr_mask_sz = 36, + .res_spec = agp_i965_res_spec, + .check_active = agp_i915_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i965_dump_regs, + .get_stolen_size = agp_i915_get_stolen_size, + .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i965_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_i965_write_gtt, + .install_gtt_pte = agp_i965_install_gtt_pte, + .read_gtt_pte = agp_i965_read_gtt_pte, + .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, + .set_aperture = agp_i915_set_aperture, + .chipset_flush_setup = agp_i965_chipset_flush_setup, + .chipset_flush_teardown = agp_i965_chipset_flush_teardown, + .chipset_flush = agp_i915_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_g33_driver = { + .chiptype = CHIP_G33, + .gen = 3, + .busdma_addr_mask_sz = 36, + .res_spec = agp_i915_res_spec, + .check_active = agp_i915_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i965_dump_regs, + .get_stolen_size = agp_i915_get_stolen_size, + .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i965_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_i915_write_gtt, + .install_gtt_pte = agp_i915_install_gtt_pte, + .read_gtt_pte = agp_i915_read_gtt_pte, + .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, + .set_aperture = agp_i915_set_aperture, + .chipset_flush_setup = agp_i965_chipset_flush_setup, + .chipset_flush_teardown = agp_i965_chipset_flush_teardown, + .chipset_flush = agp_i915_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_igd_driver = { + .chiptype = CHIP_IGD, + .gen = 3, + .busdma_addr_mask_sz = 36, + .res_spec = agp_i915_res_spec, + .check_active = agp_i915_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i915_dump_regs, + .get_stolen_size = agp_i915_get_stolen_size, + .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_i965_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_i915_write_gtt, + .install_gtt_pte = agp_i915_install_gtt_pte, + .read_gtt_pte = agp_i915_read_gtt_pte, + .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, + .set_aperture = agp_i915_set_aperture, + .chipset_flush_setup = agp_i965_chipset_flush_setup, + .chipset_flush_teardown = agp_i965_chipset_flush_teardown, + .chipset_flush = agp_i915_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_g4x_driver = { + .chiptype = CHIP_G4X, + .gen = 5, + .busdma_addr_mask_sz = 36, + .res_spec = agp_i965_res_spec, + .check_active = agp_i915_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_i965_dump_regs, + .get_stolen_size = agp_i915_get_stolen_size, + .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_gen5_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_g4x_write_gtt, + .install_gtt_pte = agp_g4x_install_gtt_pte, + .read_gtt_pte = agp_g4x_read_gtt_pte, + .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr, + .set_aperture = agp_i915_set_aperture, + .chipset_flush_setup = agp_i965_chipset_flush_setup, + .chipset_flush_teardown = agp_i965_chipset_flush_teardown, + .chipset_flush = agp_i915_chipset_flush, +}; + +static const struct agp_i810_driver agp_i810_sb_driver = { + .chiptype = CHIP_SB, + .gen = 6, + .busdma_addr_mask_sz = 40, + .res_spec = agp_g4x_res_spec, + .check_active = agp_sb_check_active, + .set_desc = agp_i810_set_desc, + .dump_regs = agp_sb_dump_regs, + .get_stolen_size = agp_sb_get_stolen_size, + .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries, + .get_gtt_total_entries = agp_sb_get_gtt_total_entries, + .install_gatt = agp_i830_install_gatt, + .deinstall_gatt = agp_i830_deinstall_gatt, + .write_gtt = agp_sb_write_gtt, + .install_gtt_pte = agp_sb_install_gtt_pte, + .read_gtt_pte = agp_g4x_read_gtt_pte, + .read_gtt_pte_paddr = agp_sb_read_gtt_pte_paddr, + .set_aperture = agp_i915_set_aperture, + .chipset_flush_setup = agp_i810_chipset_flush_setup, + .chipset_flush_teardown = agp_i810_chipset_flush_teardown, + .chipset_flush = agp_i810_chipset_flush, +}; + /* For adding new devices, devid is the id of the graphics controller * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the * second head should never be added. The bridge_offset is the offset to * subtract from devid to get the id of the hostb that the device is on. */ static const struct agp_i810_match { int devid; - int chiptype; - int bridge_offset; char *name; + const struct agp_i810_driver *driver; } agp_i810_matches[] = { - {0x71218086, CHIP_I810, 0x00010000, - "Intel 82810 (i810 GMCH) SVGA controller"}, - {0x71238086, CHIP_I810, 0x00010000, - "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"}, - {0x71258086, CHIP_I810, 0x00010000, - "Intel 82810E (i810E GMCH) SVGA controller"}, - {0x11328086, CHIP_I810, 0x00020000, - "Intel 82815 (i815 GMCH) SVGA controller"}, - {0x35778086, CHIP_I830, 0x00020000, - "Intel 82830M (830M GMCH) SVGA controller"}, - {0x25628086, CHIP_I830, 0x00020000, - "Intel 82845M (845M GMCH) SVGA controller"}, - {0x35828086, CHIP_I855, 0x00020000, - "Intel 82852/855GM SVGA controller"}, - {0x25728086, CHIP_I855, 0x00020000, - "Intel 82865G (865G GMCH) SVGA controller"}, - {0x25828086, CHIP_I915, 0x00020000, - "Intel 82915G (915G GMCH) SVGA controller"}, - {0x258A8086, CHIP_I915, 0x00020000, - "Intel E7221 SVGA controller"}, - {0x25928086, CHIP_I915, 0x00020000, - "Intel 82915GM (915GM GMCH) SVGA controller"}, - {0x27728086, CHIP_I915, 0x00020000, - "Intel 82945G (945G GMCH) SVGA controller"}, - {0x27A28086, CHIP_I915, 0x00020000, - "Intel 82945GM (945GM GMCH) SVGA controller"}, - {0x27AE8086, CHIP_I915, 0x00020000, - "Intel 945GME SVGA controller"}, - {0x29728086, CHIP_I965, 0x00020000, - "Intel 946GZ SVGA controller"}, - {0x29828086, CHIP_I965, 0x00020000, - "Intel G965 SVGA controller"}, - {0x29928086, CHIP_I965, 0x00020000, - "Intel Q965 SVGA controller"}, - {0x29A28086, CHIP_I965, 0x00020000, - "Intel G965 SVGA controller"}, - {0x29B28086, CHIP_G33, 0x00020000, - "Intel Q35 SVGA controller"}, - {0x29C28086, CHIP_G33, 0x00020000, - "Intel G33 SVGA controller"}, - {0x29D28086, CHIP_G33, 0x00020000, - "Intel Q33 SVGA controller"}, - {0xA0018086, CHIP_IGD, 0x00010000, - "Intel Pineview SVGA controller"}, - {0xA0118086, CHIP_IGD, 0x00010000, - "Intel Pineview (M) SVGA controller"}, - {0x2A028086, CHIP_I965, 0x00020000, - "Intel GM965 SVGA controller"}, - {0x2A128086, CHIP_I965, 0x00020000, - "Intel GME965 SVGA controller"}, - {0x2A428086, CHIP_G4X, 0x00020000, - "Intel GM45 SVGA controller"}, - {0x2E028086, CHIP_G4X, 0x00020000, - "Intel Eaglelake SVGA controller"}, - {0x2E128086, CHIP_G4X, 0x00020000, - "Intel Q45 SVGA controller"}, - {0x2E228086, CHIP_G4X, 0x00020000, - "Intel G45 SVGA controller"}, - {0x2E328086, CHIP_G4X, 0x00020000, - "Intel G41 SVGA controller"}, - {0x00428086, CHIP_G4X, 0x00020000, - "Intel Ironlake (D) SVGA controller"}, - {0x00468086, CHIP_G4X, 0x00020000, - "Intel Ironlake (M) SVGA controller"}, - {0, 0, 0, NULL} + { + .devid = 0x71218086, + .name = "Intel 82810 (i810 GMCH) SVGA controller", + .driver = &agp_i810_i810_driver + }, + { + .devid = 0x71238086, + .name = "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller", + .driver = &agp_i810_i810_driver + }, + { + .devid = 0x71258086, + .name = "Intel 82810E (i810E GMCH) SVGA controller", + .driver = &agp_i810_i810_driver + }, + { + .devid = 0x11328086, + .name = "Intel 82815 (i815 GMCH) SVGA controller", + .driver = &agp_i810_i815_driver + }, + { + .devid = 0x35778086, + .name = "Intel 82830M (830M GMCH) SVGA controller", + .driver = &agp_i810_i830_driver + }, + { + .devid = 0x25628086, + .name = "Intel 82845M (845M GMCH) SVGA controller", + .driver = &agp_i810_i830_driver + }, + { + .devid = 0x35828086, + .name = "Intel 82852/855GM SVGA controller", + .driver = &agp_i810_i855_driver + }, + { + .devid = 0x25728086, + .name = "Intel 82865G (865G GMCH) SVGA controller", + .driver = &agp_i810_i865_driver + }, + { + .devid = 0x25828086, + .name = "Intel 82915G (915G GMCH) SVGA controller", + .driver = &agp_i810_i915_driver + }, + { + .devid = 0x258A8086, + .name = "Intel E7221 SVGA controller", + .driver = &agp_i810_i915_driver + }, + { + .devid = 0x25928086, + .name = "Intel 82915GM (915GM GMCH) SVGA controller", + .driver = &agp_i810_i915_driver + }, + { + .devid = 0x27728086, + .name = "Intel 82945G (945G GMCH) SVGA controller", + .driver = &agp_i810_i915_driver + }, + { + .devid = 0x27A28086, + .name = "Intel 82945GM (945GM GMCH) SVGA controller", + .driver = &agp_i810_i915_driver + }, + { + .devid = 0x27AE8086, + .name = "Intel 945GME SVGA controller", + .driver = &agp_i810_i915_driver + }, + { + .devid = 0x29728086, + .name = "Intel 946GZ SVGA controller", + .driver = &agp_i810_g965_driver + }, + { + .devid = 0x29828086, + .name = "Intel G965 SVGA controller", + .driver = &agp_i810_g965_driver + }, + { + .devid = 0x29928086, + .name = "Intel Q965 SVGA controller", + .driver = &agp_i810_g965_driver + }, + { + .devid = 0x29A28086, + .name = "Intel G965 SVGA controller", + .driver = &agp_i810_g965_driver + }, + { + .devid = 0x29B28086, + .name = "Intel Q35 SVGA controller", + .driver = &agp_i810_g33_driver + }, + { + .devid = 0x29C28086, + .name = "Intel G33 SVGA controller", + .driver = &agp_i810_g33_driver + }, + { + .devid = 0x29D28086, + .name = "Intel Q33 SVGA controller", + .driver = &agp_i810_g33_driver + }, + { + .devid = 0xA0018086, + .name = "Intel Pineview SVGA controller", + .driver = &agp_i810_igd_driver + }, + { + .devid = 0xA0118086, + .name = "Intel Pineview (M) SVGA controller", + .driver = &agp_i810_igd_driver + }, + { + .devid = 0x2A028086, + .name = "Intel GM965 SVGA controller", + .driver = &agp_i810_g965_driver + }, + { + .devid = 0x2A128086, + .name = "Intel GME965 SVGA controller", + .driver = &agp_i810_g965_driver + }, + { + .devid = 0x2A428086, + .name = "Intel GM45 SVGA controller", + .driver = &agp_i810_g4x_driver + }, + { + .devid = 0x2E028086, + .name = "Intel Eaglelake SVGA controller", + .driver = &agp_i810_g4x_driver + }, + { + .devid = 0x2E128086, + .name = "Intel Q45 SVGA controller", + .driver = &agp_i810_g4x_driver + }, + { + .devid = 0x2E228086, + .name = "Intel G45 SVGA controller", + .driver = &agp_i810_g4x_driver + }, + { + .devid = 0x2E328086, + .name = "Intel G41 SVGA controller", + .driver = &agp_i810_g4x_driver + }, + { + .devid = 0x00428086, + .name = "Intel Ironlake (D) SVGA controller", + .driver = &agp_i810_g4x_driver + }, + { + .devid = 0x00468086, + .name = "Intel Ironlake (M) SVGA controller", + .driver = &agp_i810_g4x_driver + }, + { + .devid = 0x01028086, + .name = "SandyBridge desktop GT1 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01128086, + .name = "SandyBridge desktop GT2 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01228086, + .name = "SandyBridge desktop GT2+ IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01068086, + .name = "SandyBridge mobile GT1 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01168086, + .name = "SandyBridge mobile GT2 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01268086, + .name = "SandyBridge mobile GT2+ IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01088086, + .name = "SandyBridge server IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01528086, + .name = "IvyBridge desktop GT1 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01628086, + .name = "IvyBridge desktop GT2 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01568086, + .name = "IvyBridge mobile GT1 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x01668086, + .name = "IvyBridge mobile GT2 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0x015a8086, + .name = "IvyBridge server GT1 IG", + .driver = &agp_i810_sb_driver + }, + { + .devid = 0, + } }; static const struct agp_i810_match* agp_i810_match(device_t dev) { int i, devid; if (pci_get_class(dev) != PCIC_DISPLAY || pci_get_subclass(dev) != PCIS_DISPLAY_VGA) - return NULL; + return (NULL); devid = pci_get_devid(dev); for (i = 0; agp_i810_matches[i].devid != 0; i++) { if (agp_i810_matches[i].devid == devid) - break; + break; } if (agp_i810_matches[i].devid == 0) - return NULL; + return (NULL); else - return &agp_i810_matches[i]; + return (&agp_i810_matches[i]); } /* * Find bridge device. */ static device_t agp_i810_find_bridge(device_t dev) { - device_t *children, child; - int nchildren, i; - u_int32_t devid; - const struct agp_i810_match *match; - - match = agp_i810_match(dev); - devid = match->devid - match->bridge_offset; - if (device_get_children(device_get_parent(device_get_parent(dev)), - &children, &nchildren)) - return 0; - - for (i = 0; i < nchildren; i++) { - child = children[i]; - - if (pci_get_devid(child) == devid) { - free(children, M_TEMP); - return child; - } - } - free(children, M_TEMP); - return 0; + return (pci_find_dbsf(0, 0, 0, 0)); } static void agp_i810_identify(driver_t *driver, device_t parent) { if (device_find_child(parent, "agp", -1) == NULL && agp_i810_match(parent)) device_add_child(parent, "agp", -1); } static int +agp_i810_check_active(device_t bridge_dev) +{ + u_int8_t smram; + + smram = pci_read_config(bridge_dev, AGP_I810_SMRAM, 1); + if ((smram & AGP_I810_SMRAM_GMS) == AGP_I810_SMRAM_GMS_DISABLED) + return (ENXIO); + return (0); +} + +static int +agp_i830_check_active(device_t bridge_dev) +{ + int gcc1; + + gcc1 = pci_read_config(bridge_dev, AGP_I830_GCC1, 1); + if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED) + return (ENXIO); + return (0); +} + +static int +agp_i915_check_active(device_t bridge_dev) +{ + int deven; + + deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4); + if ((deven & AGP_I915_DEVEN_D2F0) == AGP_I915_DEVEN_D2F0_DISABLED) + return (ENXIO); + return (0); +} + +static int +agp_sb_check_active(device_t bridge_dev) +{ + int deven; + + deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4); + if ((deven & AGP_SB_DEVEN_D2EN) == AGP_SB_DEVEN_D2EN_DISABLED) + return (ENXIO); + return (0); +} + +static void +agp_82852_set_desc(device_t dev, const struct agp_i810_match *match) +{ + + switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) { + case AGP_I855_GME: + device_set_desc(dev, + "Intel 82855GME (855GME GMCH) SVGA controller"); + break; + case AGP_I855_GM: + device_set_desc(dev, + "Intel 82855GM (855GM GMCH) SVGA controller"); + break; + case AGP_I852_GME: + device_set_desc(dev, + "Intel 82852GME (852GME GMCH) SVGA controller"); + break; + case AGP_I852_GM: + device_set_desc(dev, + "Intel 82852GM (852GM GMCH) SVGA controller"); + break; + default: + device_set_desc(dev, + "Intel 8285xM (85xGM GMCH) SVGA controller"); + break; + } +} + +static void +agp_i810_set_desc(device_t dev, const struct agp_i810_match *match) +{ + + device_set_desc(dev, match->name); +} + +static int agp_i810_probe(device_t dev) { device_t bdev; const struct agp_i810_match *match; - u_int8_t smram; - int gcc1, deven; + int err; if (resource_disabled("agp", device_get_unit(dev))) return (ENXIO); match = agp_i810_match(dev); if (match == NULL) - return ENXIO; + return (ENXIO); bdev = agp_i810_find_bridge(dev); - if (!bdev) { + if (bdev == NULL) { if (bootverbose) printf("I810: can't find bridge device\n"); - return ENXIO; + return (ENXIO); } /* * checking whether internal graphics device has been activated. */ - switch (match->chiptype) { - case CHIP_I810: - smram = pci_read_config(bdev, AGP_I810_SMRAM, 1); - if ((smram & AGP_I810_SMRAM_GMS) == - AGP_I810_SMRAM_GMS_DISABLED) { - if (bootverbose) - printf("I810: disabled, not probing\n"); - return ENXIO; - } - break; - case CHIP_I830: - case CHIP_I855: - gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1); - if ((gcc1 & AGP_I830_GCC1_DEV2) == - AGP_I830_GCC1_DEV2_DISABLED) { - if (bootverbose) - printf("I830: disabled, not probing\n"); - return ENXIO; - } - break; - case CHIP_I915: - case CHIP_I965: - case CHIP_G33: - case CHIP_IGD: - case CHIP_G4X: - deven = pci_read_config(bdev, AGP_I915_DEVEN, 4); - if ((deven & AGP_I915_DEVEN_D2F0) == - AGP_I915_DEVEN_D2F0_DISABLED) { - if (bootverbose) - printf("I915: disabled, not probing\n"); - return ENXIO; - } - break; + err = match->driver->check_active(bdev); + if (err != 0) { + if (bootverbose) + printf("i810: disabled, not probing\n"); + return (err); } - if (match->devid == 0x35828086) { - switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) { - case AGP_I855_GME: - device_set_desc(dev, - "Intel 82855GME (855GME GMCH) SVGA controller"); - break; - case AGP_I855_GM: - device_set_desc(dev, - "Intel 82855GM (855GM GMCH) SVGA controller"); - break; - case AGP_I852_GME: - device_set_desc(dev, - "Intel 82852GME (852GME GMCH) SVGA controller"); - break; - case AGP_I852_GM: - device_set_desc(dev, - "Intel 82852GM (852GM GMCH) SVGA controller"); - break; - default: - device_set_desc(dev, - "Intel 8285xM (85xGM GMCH) SVGA controller"); - break; - } - } else { - device_set_desc(dev, match->name); - } - - return BUS_PROBE_DEFAULT; + match->driver->set_desc(dev, match); + return (BUS_PROBE_DEFAULT); } static void agp_i810_dump_regs(device_t dev) { struct agp_i810_softc *sc = device_get_softc(dev); device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); + device_printf(dev, "AGP_I810_MISCC: 0x%04x\n", + pci_read_config(sc->bdev, AGP_I810_MISCC, 2)); +} - switch (sc->chiptype) { - case CHIP_I810: - device_printf(dev, "AGP_I810_MISCC: 0x%04x\n", - pci_read_config(sc->bdev, AGP_I810_MISCC, 2)); +static void +agp_i830_dump_regs(device_t dev) +{ + struct agp_i810_softc *sc = device_get_softc(dev); + + device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", + bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); + device_printf(dev, "AGP_I830_GCC1: 0x%02x\n", + pci_read_config(sc->bdev, AGP_I830_GCC1, 1)); +} + +static void +agp_i855_dump_regs(device_t dev) +{ + struct agp_i810_softc *sc = device_get_softc(dev); + + device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", + bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); + device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", + pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); +} + +static void +agp_i915_dump_regs(device_t dev) +{ + struct agp_i810_softc *sc = device_get_softc(dev); + + device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n", + bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL)); + device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", + pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); + device_printf(dev, "AGP_I915_MSAC: 0x%02x\n", + pci_read_config(sc->bdev, AGP_I915_MSAC, 1)); +} + +static void +agp_i965_dump_regs(device_t dev) +{ + struct agp_i810_softc *sc = device_get_softc(dev); + + device_printf(dev, "AGP_I965_PGTBL_CTL2: %08x\n", + bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2)); + device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", + pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); + device_printf(dev, "AGP_I965_MSAC: 0x%02x\n", + pci_read_config(sc->bdev, AGP_I965_MSAC, 1)); +} + +static void +agp_sb_dump_regs(device_t dev) +{ + struct agp_i810_softc *sc = device_get_softc(dev); + + device_printf(dev, "AGP_SNB_GFX_MODE: %08x\n", + bus_read_4(sc->sc_res[0], AGP_SNB_GFX_MODE)); + device_printf(dev, "AGP_SNB_GCC1: 0x%04x\n", + pci_read_config(sc->bdev, AGP_SNB_GCC1, 2)); +} + +static int +agp_i810_get_stolen_size(device_t dev) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + sc->stolen = 0; + sc->stolen_size = 0; + return (0); +} + +static int +agp_i830_get_stolen_size(device_t dev) +{ + struct agp_i810_softc *sc; + unsigned int gcc1; + + sc = device_get_softc(dev); + + gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1); + switch (gcc1 & AGP_I830_GCC1_GMS) { + case AGP_I830_GCC1_GMS_STOLEN_512: + sc->stolen = (512 - 132) * 1024 / 4096; + sc->stolen_size = 512 * 1024; break; - case CHIP_I830: - device_printf(dev, "AGP_I830_GCC1: 0x%02x\n", - pci_read_config(sc->bdev, AGP_I830_GCC1, 1)); + case AGP_I830_GCC1_GMS_STOLEN_1024: + sc->stolen = (1024 - 132) * 1024 / 4096; + sc->stolen_size = 1024 * 1024; break; + case AGP_I830_GCC1_GMS_STOLEN_8192: + sc->stolen = (8192 - 132) * 1024 / 4096; + sc->stolen_size = 8192 * 1024; + break; + default: + sc->stolen = 0; + device_printf(dev, + "unknown memory configuration, disabling (GCC1 %x)\n", + gcc1); + return (EINVAL); + } + return (0); +} + +static int +agp_i915_get_stolen_size(device_t dev) +{ + struct agp_i810_softc *sc; + unsigned int gcc1, stolen, gtt_size; + + sc = device_get_softc(dev); + + /* + * Stolen memory is set up at the beginning of the aperture by + * the BIOS, consisting of the GATT followed by 4kb for the + * BIOS display. + */ + switch (sc->match->driver->chiptype) { case CHIP_I855: - device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", - pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); + gtt_size = 128; break; case CHIP_I915: + gtt_size = 256; + break; case CHIP_I965: + switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) & + AGP_I810_PGTBL_SIZE_MASK) { + case AGP_I810_PGTBL_SIZE_128KB: + gtt_size = 128; + break; + case AGP_I810_PGTBL_SIZE_256KB: + gtt_size = 256; + break; + case AGP_I810_PGTBL_SIZE_512KB: + gtt_size = 512; + break; + case AGP_I965_PGTBL_SIZE_1MB: + gtt_size = 1024; + break; + case AGP_I965_PGTBL_SIZE_2MB: + gtt_size = 2048; + break; + case AGP_I965_PGTBL_SIZE_1_5MB: + gtt_size = 1024 + 512; + break; + default: + device_printf(dev, "Bad PGTBL size\n"); + return (EINVAL); + } + break; case CHIP_G33: + gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2); + switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) { + case AGP_G33_MGGC_GGMS_SIZE_1M: + gtt_size = 1024; + break; + case AGP_G33_MGGC_GGMS_SIZE_2M: + gtt_size = 2048; + break; + default: + device_printf(dev, "Bad PGTBL size\n"); + return (EINVAL); + } + break; case CHIP_IGD: case CHIP_G4X: - device_printf(dev, "AGP_I855_GCC1: 0x%02x\n", - pci_read_config(sc->bdev, AGP_I855_GCC1, 1)); - device_printf(dev, "AGP_I915_MSAC: 0x%02x\n", - pci_read_config(sc->bdev, AGP_I915_MSAC, 1)); + gtt_size = 0; break; + default: + device_printf(dev, "Bad chiptype\n"); + return (EINVAL); } - device_printf(dev, "Aperture resource size: %d bytes\n", - AGP_GET_APERTURE(dev)); + + /* GCC1 is called MGGC on i915+ */ + gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1); + switch (gcc1 & AGP_I855_GCC1_GMS) { + case AGP_I855_GCC1_GMS_STOLEN_1M: + stolen = 1024; + break; + case AGP_I855_GCC1_GMS_STOLEN_4M: + stolen = 4 * 1024; + break; + case AGP_I855_GCC1_GMS_STOLEN_8M: + stolen = 8 * 1024; + break; + case AGP_I855_GCC1_GMS_STOLEN_16M: + stolen = 16 * 1024; + break; + case AGP_I855_GCC1_GMS_STOLEN_32M: + stolen = 32 * 1024; + break; + case AGP_I915_GCC1_GMS_STOLEN_48M: + stolen = sc->match->driver->gen > 2 ? 48 * 1024 : 0; + break; + case AGP_I915_GCC1_GMS_STOLEN_64M: + stolen = sc->match->driver->gen > 2 ? 64 * 1024 : 0; + break; + case AGP_G33_GCC1_GMS_STOLEN_128M: + stolen = sc->match->driver->gen > 2 ? 128 * 1024 : 0; + break; + case AGP_G33_GCC1_GMS_STOLEN_256M: + stolen = sc->match->driver->gen > 2 ? 256 * 1024 : 0; + break; + case AGP_G4X_GCC1_GMS_STOLEN_96M: + if (sc->match->driver->chiptype == CHIP_I965 || + sc->match->driver->chiptype == CHIP_G4X) + stolen = 96 * 1024; + else + stolen = 0; + break; + case AGP_G4X_GCC1_GMS_STOLEN_160M: + if (sc->match->driver->chiptype == CHIP_I965 || + sc->match->driver->chiptype == CHIP_G4X) + stolen = 160 * 1024; + else + stolen = 0; + break; + case AGP_G4X_GCC1_GMS_STOLEN_224M: + if (sc->match->driver->chiptype == CHIP_I965 || + sc->match->driver->chiptype == CHIP_G4X) + stolen = 224 * 1024; + else + stolen = 0; + break; + case AGP_G4X_GCC1_GMS_STOLEN_352M: + if (sc->match->driver->chiptype == CHIP_I965 || + sc->match->driver->chiptype == CHIP_G4X) + stolen = 352 * 1024; + else + stolen = 0; + break; + default: + device_printf(dev, + "unknown memory configuration, disabling (GCC1 %x)\n", + gcc1); + return (EINVAL); + } + + gtt_size += 4; + sc->stolen_size = stolen * 1024; + sc->stolen = (stolen - gtt_size) * 1024 / 4096; + + return (0); } static int -agp_i810_attach(device_t dev) +agp_sb_get_stolen_size(device_t dev) { - struct agp_i810_softc *sc = device_get_softc(dev); - struct agp_gatt *gatt; - const struct agp_i810_match *match; - int error; + struct agp_i810_softc *sc; + uint16_t gmch_ctl; - sc->bdev = agp_i810_find_bridge(dev); - if (!sc->bdev) - return ENOENT; + sc = device_get_softc(dev); + gmch_ctl = pci_read_config(sc->bdev, AGP_SNB_GCC1, 2); + switch (gmch_ctl & AGP_SNB_GMCH_GMS_STOLEN_MASK) { + case AGP_SNB_GMCH_GMS_STOLEN_32M: + sc->stolen_size = 32 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_64M: + sc->stolen_size = 64 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_96M: + sc->stolen_size = 96 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_128M: + sc->stolen_size = 128 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_160M: + sc->stolen_size = 160 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_192M: + sc->stolen_size = 192 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_224M: + sc->stolen_size = 224 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_256M: + sc->stolen_size = 256 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_288M: + sc->stolen_size = 288 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_320M: + sc->stolen_size = 320 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_352M: + sc->stolen_size = 352 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_384M: + sc->stolen_size = 384 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_416M: + sc->stolen_size = 416 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_448M: + sc->stolen_size = 448 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_480M: + sc->stolen_size = 480 * 1024 * 1024; + break; + case AGP_SNB_GMCH_GMS_STOLEN_512M: + sc->stolen_size = 512 * 1024 * 1024; + break; + } + sc->stolen = (sc->stolen_size - 4) / 4096; + return (0); +} - match = agp_i810_match(dev); - sc->chiptype = match->chiptype; +static int +agp_i810_get_gtt_mappable_entries(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t ap; + uint16_t miscc; - switch (sc->chiptype) { - case CHIP_I810: - case CHIP_I830: - case CHIP_I855: - sc->sc_res_spec = agp_i810_res_spec; - agp_set_aperture_resource(dev, AGP_APBASE); + sc = device_get_softc(dev); + miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); + if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32) + ap = 32; + else + ap = 64; + sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT; + return (0); +} + +static int +agp_i830_get_gtt_mappable_entries(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t ap; + uint16_t gmch_ctl; + + sc = device_get_softc(dev); + gmch_ctl = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); + if ((gmch_ctl & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) + ap = 64; + else + ap = 128; + sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT; + return (0); +} + +static int +agp_i915_get_gtt_mappable_entries(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t ap; + + sc = device_get_softc(dev); + ap = AGP_GET_APERTURE(dev); + sc->gtt_mappable_entries = ap >> AGP_PAGE_SHIFT; + return (0); +} + +static int +agp_i810_get_gtt_total_entries(device_t dev) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + sc->gtt_total_entries = sc->gtt_mappable_entries; + return (0); +} + +static int +agp_i965_get_gtt_total_entries(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t pgetbl_ctl; + int error; + + sc = device_get_softc(dev); + error = 0; + pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); + switch (pgetbl_ctl & AGP_I810_PGTBL_SIZE_MASK) { + case AGP_I810_PGTBL_SIZE_128KB: + sc->gtt_total_entries = 128 * 1024 / 4; break; - case CHIP_I915: - case CHIP_G33: - case CHIP_IGD: - sc->sc_res_spec = agp_i915_res_spec; - agp_set_aperture_resource(dev, AGP_I915_GMADR); + case AGP_I810_PGTBL_SIZE_256KB: + sc->gtt_total_entries = 256 * 1024 / 4; break; - case CHIP_I965: - case CHIP_G4X: - sc->sc_res_spec = agp_i965_res_spec; - agp_set_aperture_resource(dev, AGP_I915_GMADR); + case AGP_I810_PGTBL_SIZE_512KB: + sc->gtt_total_entries = 512 * 1024 / 4; break; + /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ + case AGP_I810_PGTBL_SIZE_1MB: + sc->gtt_total_entries = 1024 * 1024 / 4; + break; + case AGP_I810_PGTBL_SIZE_2MB: + sc->gtt_total_entries = 2 * 1024 * 1024 / 4; + break; + case AGP_I810_PGTBL_SIZE_1_5MB: + sc->gtt_total_entries = (1024 + 512) * 1024 / 4; + break; + default: + device_printf(dev, "Unknown page table size\n"); + error = ENXIO; } + return (error); +} - error = agp_generic_attach(dev); - if (error) - return error; +static void +agp_gen5_adjust_pgtbl_size(device_t dev, uint32_t sz) +{ + struct agp_i810_softc *sc; + uint32_t pgetbl_ctl, pgetbl_ctl2; - if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 && - sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X && - ptoa((vm_paddr_t)Maxmem) > 0xfffffffful) - { - device_printf(dev, "agp_i810.c does not support physical " - "memory above 4GB.\n"); - return ENOENT; + sc = device_get_softc(dev); + + /* Disable per-process page table. */ + pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2); + pgetbl_ctl2 &= ~AGP_I810_PGTBL_ENABLED; + bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2); + + /* Write the new ggtt size. */ + pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); + pgetbl_ctl &= ~AGP_I810_PGTBL_SIZE_MASK; + pgetbl_ctl |= sz; + bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl); +} + +static int +agp_gen5_get_gtt_total_entries(device_t dev) +{ + struct agp_i810_softc *sc; + uint16_t gcc1; + + sc = device_get_softc(dev); + + gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); + switch (gcc1 & AGP_G4x_GCC1_SIZE_MASK) { + case AGP_G4x_GCC1_SIZE_1M: + case AGP_G4x_GCC1_SIZE_VT_1M: + agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1MB); + break; + case AGP_G4x_GCC1_SIZE_VT_1_5M: + agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1_5MB); + break; + case AGP_G4x_GCC1_SIZE_2M: + case AGP_G4x_GCC1_SIZE_VT_2M: + agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_2MB); + break; + default: + device_printf(dev, "Unknown page table size\n"); + return (ENXIO); } - if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) { - agp_generic_detach(dev); - return ENODEV; + return (agp_i965_get_gtt_total_entries(dev)); +} + +static int +agp_sb_get_gtt_total_entries(device_t dev) +{ + struct agp_i810_softc *sc; + uint16_t gcc1; + + sc = device_get_softc(dev); + + gcc1 = pci_read_config(sc->bdev, AGP_SNB_GCC1, 2); + switch (gcc1 & AGP_SNB_GTT_SIZE_MASK) { + default: + case AGP_SNB_GTT_SIZE_0M: + printf("Bad GTT size mask: 0x%04x\n", gcc1); + return (ENXIO); + case AGP_SNB_GTT_SIZE_1M: + sc->gtt_total_entries = 1024 * 1024 / 4; + break; + case AGP_SNB_GTT_SIZE_2M: + sc->gtt_total_entries = 2 * 1024 * 1024 / 4; + break; } + return (0); +} - sc->initial_aperture = AGP_GET_APERTURE(dev); +static int +agp_i810_install_gatt(device_t dev) +{ + struct agp_i810_softc *sc; - gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT); - if (!gatt) { - bus_release_resources(dev, sc->sc_res_spec, sc->sc_res); - agp_generic_detach(dev); - return ENOMEM; + sc = device_get_softc(dev); + + /* Some i810s have on-chip memory called dcache. */ + if ((bus_read_1(sc->sc_res[0], AGP_I810_DRT) & AGP_I810_DRT_POPULATED) + != 0) + sc->dcache_size = 4 * 1024 * 1024; + else + sc->dcache_size = 0; + + /* According to the specs the gatt on the i810 must be 64k. */ + sc->gatt->ag_virtual = contigmalloc(64 * 1024, M_AGP, 0, 0, ~0, + PAGE_SIZE, 0); + if (sc->gatt->ag_virtual == NULL) { + if (bootverbose) + device_printf(dev, "contiguous allocation failed\n"); + return (ENOMEM); } - sc->gatt = gatt; - gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT; + bzero(sc->gatt->ag_virtual, sc->gatt->ag_entries * sizeof(u_int32_t)); + sc->gatt->ag_physical = vtophys((vm_offset_t)sc->gatt->ag_virtual); + agp_flush_cache(); + /* Install the GATT. */ + bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, + sc->gatt->ag_physical | 1); + return (0); +} - if ( sc->chiptype == CHIP_I810 ) { - /* Some i810s have on-chip memory called dcache */ - if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) & - AGP_I810_DRT_POPULATED) - sc->dcache_size = 4 * 1024 * 1024; - else - sc->dcache_size = 0; +static int +agp_i830_install_gatt(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t pgtblctl; - /* According to the specs the gatt on the i810 must be 64k */ - gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0, - 0, ~0, PAGE_SIZE, 0); - if (!gatt->ag_virtual) { - if (bootverbose) - device_printf(dev, "contiguous allocation failed\n"); - bus_release_resources(dev, sc->sc_res_spec, - sc->sc_res); - free(gatt, M_AGP); - agp_generic_detach(dev); - return ENOMEM; - } - bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t)); + sc = device_get_softc(dev); + + /* + * The i830 automatically initializes the 128k gatt on boot. + * GATT address is already in there, make sure it's enabled. + */ + pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); + pgtblctl |= 1; + bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); - gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); - agp_flush_cache(); - /* Install the GATT. */ - bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, - gatt->ag_physical | 1); - } else if ( sc->chiptype == CHIP_I830 ) { - /* The i830 automatically initializes the 128k gatt on boot. */ - unsigned int gcc1, pgtblctl; - - gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1); - switch (gcc1 & AGP_I830_GCC1_GMS) { - case AGP_I830_GCC1_GMS_STOLEN_512: - sc->stolen = (512 - 132) * 1024 / 4096; - break; - case AGP_I830_GCC1_GMS_STOLEN_1024: - sc->stolen = (1024 - 132) * 1024 / 4096; - break; - case AGP_I830_GCC1_GMS_STOLEN_8192: - sc->stolen = (8192 - 132) * 1024 / 4096; - break; - default: - sc->stolen = 0; - device_printf(dev, "unknown memory configuration, disabling\n"); - bus_release_resources(dev, sc->sc_res_spec, - sc->sc_res); - free(gatt, M_AGP); - agp_generic_detach(dev); - return EINVAL; - } + sc->gatt->ag_physical = pgtblctl & ~1; + return (0); +} - /* GATT address is already in there, make sure it's enabled */ - pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); - pgtblctl |= 1; - bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); +static int +agp_i810_attach(device_t dev) +{ + struct agp_i810_softc *sc; + int error; - gatt->ag_physical = pgtblctl & ~1; - } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 || - sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 || - sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) { - unsigned int gcc1, pgtblctl, stolen, gtt_size; + sc = device_get_softc(dev); + sc->bdev = agp_i810_find_bridge(dev); + if (sc->bdev == NULL) + return (ENOENT); - /* Stolen memory is set up at the beginning of the aperture by - * the BIOS, consisting of the GATT followed by 4kb for the - * BIOS display. - */ - switch (sc->chiptype) { - case CHIP_I855: - gtt_size = 128; - break; - case CHIP_I915: - gtt_size = 256; - break; - case CHIP_I965: - switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) & - AGP_I810_PGTBL_SIZE_MASK) { - case AGP_I810_PGTBL_SIZE_128KB: - gtt_size = 128; - break; - case AGP_I810_PGTBL_SIZE_256KB: - gtt_size = 256; - break; - case AGP_I810_PGTBL_SIZE_512KB: - gtt_size = 512; - break; - case AGP_I965_PGTBL_SIZE_1MB: - gtt_size = 1024; - break; - case AGP_I965_PGTBL_SIZE_2MB: - gtt_size = 2048; - break; - case AGP_I965_PGTBL_SIZE_1_5MB: - gtt_size = 1024 + 512; - break; - default: - device_printf(dev, "Bad PGTBL size\n"); - bus_release_resources(dev, sc->sc_res_spec, - sc->sc_res); - free(gatt, M_AGP); - agp_generic_detach(dev); - return EINVAL; - } - break; - case CHIP_G33: - gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2); - switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) { - case AGP_G33_MGGC_GGMS_SIZE_1M: - gtt_size = 1024; - break; - case AGP_G33_MGGC_GGMS_SIZE_2M: - gtt_size = 2048; - break; - default: - device_printf(dev, "Bad PGTBL size\n"); - bus_release_resources(dev, sc->sc_res_spec, - sc->sc_res); - free(gatt, M_AGP); - agp_generic_detach(dev); - return EINVAL; - } - break; - case CHIP_IGD: - case CHIP_G4X: - gtt_size = 0; - break; - default: - device_printf(dev, "Bad chiptype\n"); - bus_release_resources(dev, sc->sc_res_spec, - sc->sc_res); - free(gatt, M_AGP); - agp_generic_detach(dev); - return EINVAL; - } + sc->match = agp_i810_match(dev); - /* GCC1 is called MGGC on i915+ */ - gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1); - switch (gcc1 & AGP_I855_GCC1_GMS) { - case AGP_I855_GCC1_GMS_STOLEN_1M: - stolen = 1024; - break; - case AGP_I855_GCC1_GMS_STOLEN_4M: - stolen = 4 * 1024; - break; - case AGP_I855_GCC1_GMS_STOLEN_8M: - stolen = 8 * 1024; - break; - case AGP_I855_GCC1_GMS_STOLEN_16M: - stolen = 16 * 1024; - break; - case AGP_I855_GCC1_GMS_STOLEN_32M: - stolen = 32 * 1024; - break; - case AGP_I915_GCC1_GMS_STOLEN_48M: - if (sc->chiptype == CHIP_I915 || - sc->chiptype == CHIP_I965 || - sc->chiptype == CHIP_G33 || - sc->chiptype == CHIP_IGD || - sc->chiptype == CHIP_G4X) { - stolen = 48 * 1024; - } else { - stolen = 0; - } - break; - case AGP_I915_GCC1_GMS_STOLEN_64M: - if (sc->chiptype == CHIP_I915 || - sc->chiptype == CHIP_I965 || - sc->chiptype == CHIP_G33 || - sc->chiptype == CHIP_IGD || - sc->chiptype == CHIP_G4X) { - stolen = 64 * 1024; - } else { - stolen = 0; - } - break; - case AGP_G33_GCC1_GMS_STOLEN_128M: - if (sc->chiptype == CHIP_I965 || - sc->chiptype == CHIP_G33 || - sc->chiptype == CHIP_IGD || - sc->chiptype == CHIP_G4X) { - stolen = 128 * 1024; - } else { - stolen = 0; - } - break; - case AGP_G33_GCC1_GMS_STOLEN_256M: - if (sc->chiptype == CHIP_I965 || - sc->chiptype == CHIP_G33 || - sc->chiptype == CHIP_IGD || - sc->chiptype == CHIP_G4X) { - stolen = 256 * 1024; - } else { - stolen = 0; - } - break; - case AGP_G4X_GCC1_GMS_STOLEN_96M: - if (sc->chiptype == CHIP_I965 || - sc->chiptype == CHIP_G4X) { - stolen = 96 * 1024; - } else { - stolen = 0; - } - break; - case AGP_G4X_GCC1_GMS_STOLEN_160M: - if (sc->chiptype == CHIP_I965 || - sc->chiptype == CHIP_G4X) { - stolen = 160 * 1024; - } else { - stolen = 0; - } - break; - case AGP_G4X_GCC1_GMS_STOLEN_224M: - if (sc->chiptype == CHIP_I965 || - sc->chiptype == CHIP_G4X) { - stolen = 224 * 1024; - } else { - stolen = 0; - } - break; - case AGP_G4X_GCC1_GMS_STOLEN_352M: - if (sc->chiptype == CHIP_I965 || - sc->chiptype == CHIP_G4X) { - stolen = 352 * 1024; - } else { - stolen = 0; - } - break; - default: - device_printf(dev, "unknown memory configuration, " - "disabling\n"); - bus_release_resources(dev, sc->sc_res_spec, - sc->sc_res); - free(gatt, M_AGP); - agp_generic_detach(dev); - return EINVAL; - } + agp_set_aperture_resource(dev, sc->match->driver->gen <= 2 ? + AGP_APBASE : AGP_I915_GMADR); + error = agp_generic_attach(dev); + if (error) + return (error); - gtt_size += 4; + if (ptoa((vm_paddr_t)Maxmem) > + (1ULL << sc->match->driver->busdma_addr_mask_sz) - 1) { + device_printf(dev, "agp_i810 does not support physical " + "memory above %ju.\n", (uintmax_t)(1ULL << + sc->match->driver->busdma_addr_mask_sz) - 1); + return (ENOENT); + } - sc->stolen = (stolen - gtt_size) * 1024 / 4096; + if (bus_alloc_resources(dev, sc->match->driver->res_spec, sc->sc_res)) { + agp_generic_detach(dev); + return (ENODEV); + } - /* GATT address is already in there, make sure it's enabled */ - pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); - pgtblctl |= 1; - bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); + sc->initial_aperture = AGP_GET_APERTURE(dev); + sc->gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_WAITOK); + sc->gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT; - gatt->ag_physical = pgtblctl & ~1; + if ((error = sc->match->driver->get_stolen_size(dev)) != 0 || + (error = sc->match->driver->install_gatt(dev)) != 0 || + (error = sc->match->driver->get_gtt_mappable_entries(dev)) != 0 || + (error = sc->match->driver->get_gtt_total_entries(dev)) != 0 || + (error = sc->match->driver->chipset_flush_setup(dev)) != 0) { + bus_release_resources(dev, sc->match->driver->res_spec, + sc->sc_res); + free(sc->gatt, M_AGP); + agp_generic_detach(dev); + return (error); } + intel_agp = dev; device_printf(dev, "aperture size is %dM", sc->initial_aperture / 1024 / 1024); if (sc->stolen > 0) printf(", detected %dk stolen memory\n", sc->stolen * 4); else printf("\n"); + if (bootverbose) { + sc->match->driver->dump_regs(dev); + device_printf(dev, "Mappable GTT entries: %d\n", + sc->gtt_mappable_entries); + device_printf(dev, "Total GTT entries: %d\n", + sc->gtt_total_entries); + } + return (0); +} - if (0) - agp_i810_dump_regs(dev); +static void +agp_i810_deinstall_gatt(device_t dev) +{ + struct agp_i810_softc *sc; - return 0; + sc = device_get_softc(dev); + bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0); + contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP); } +static void +agp_i830_deinstall_gatt(device_t dev) +{ + struct agp_i810_softc *sc; + unsigned int pgtblctl; + + sc = device_get_softc(dev); + pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); + pgtblctl &= ~1; + bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); +} + static int agp_i810_detach(device_t dev) { - struct agp_i810_softc *sc = device_get_softc(dev); + struct agp_i810_softc *sc; + sc = device_get_softc(dev); agp_free_cdev(dev); /* Clear the GATT base. */ - if ( sc->chiptype == CHIP_I810 ) { - bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0); - } else { - unsigned int pgtblctl; - pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL); - pgtblctl &= ~1; - bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl); - } + sc->match->driver->deinstall_gatt(dev); + sc->match->driver->chipset_flush_teardown(dev); + /* Put the aperture back the way it started. */ AGP_SET_APERTURE(dev, sc->initial_aperture); - if ( sc->chiptype == CHIP_I810 ) { - contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP); - } free(sc->gatt, M_AGP); - - bus_release_resources(dev, sc->sc_res_spec, sc->sc_res); + bus_release_resources(dev, sc->match->driver->res_spec, sc->sc_res); agp_free_res(dev); - return 0; + return (0); } static int agp_i810_resume(device_t dev) { struct agp_i810_softc *sc; sc = device_get_softc(dev); AGP_SET_APERTURE(dev, sc->initial_aperture); /* Install the GATT. */ bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, sc->gatt->ag_physical | 1); return (bus_generic_resume(dev)); } /** * Sets the PCI resource size of the aperture on i830-class and below chipsets, * while returning failure on later chipsets when an actual change is * requested. * * This whole function is likely bogus, as the kernel would probably need to * reconfigure the placement of the AGP aperture if a larger size is requested, * which doesn't happen currently. */ static int agp_i810_set_aperture(device_t dev, u_int32_t aperture) { - struct agp_i810_softc *sc = device_get_softc(dev); - u_int16_t miscc, gcc1; + struct agp_i810_softc *sc; + u_int16_t miscc; - switch (sc->chiptype) { - case CHIP_I810: - /* - * Double check for sanity. - */ - if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) { - device_printf(dev, "bad aperture size %d\n", aperture); - return EINVAL; - } + sc = device_get_softc(dev); + /* + * Double check for sanity. + */ + if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) { + device_printf(dev, "bad aperture size %d\n", aperture); + return (EINVAL); + } - miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); - miscc &= ~AGP_I810_MISCC_WINSIZE; - if (aperture == 32 * 1024 * 1024) - miscc |= AGP_I810_MISCC_WINSIZE_32; - else - miscc |= AGP_I810_MISCC_WINSIZE_64; + miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); + miscc &= ~AGP_I810_MISCC_WINSIZE; + if (aperture == 32 * 1024 * 1024) + miscc |= AGP_I810_MISCC_WINSIZE_32; + else + miscc |= AGP_I810_MISCC_WINSIZE_64; - pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2); - break; - case CHIP_I830: - if (aperture != 64 * 1024 * 1024 && - aperture != 128 * 1024 * 1024) { - device_printf(dev, "bad aperture size %d\n", aperture); - return EINVAL; - } - gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); - gcc1 &= ~AGP_I830_GCC1_GMASIZE; - if (aperture == 64 * 1024 * 1024) - gcc1 |= AGP_I830_GCC1_GMASIZE_64; - else - gcc1 |= AGP_I830_GCC1_GMASIZE_128; + pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2); + return (0); +} - pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2); - break; - case CHIP_I855: - case CHIP_I915: - case CHIP_I965: - case CHIP_G33: - case CHIP_IGD: - case CHIP_G4X: - return agp_generic_set_aperture(dev, aperture); +static int +agp_i830_set_aperture(device_t dev, u_int32_t aperture) +{ + struct agp_i810_softc *sc; + u_int16_t gcc1; + + sc = device_get_softc(dev); + + if (aperture != 64 * 1024 * 1024 && + aperture != 128 * 1024 * 1024) { + device_printf(dev, "bad aperture size %d\n", aperture); + return (EINVAL); } + gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); + gcc1 &= ~AGP_I830_GCC1_GMASIZE; + if (aperture == 64 * 1024 * 1024) + gcc1 |= AGP_I830_GCC1_GMASIZE_64; + else + gcc1 |= AGP_I830_GCC1_GMASIZE_128; - return 0; + pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2); + return (0); } +static int +agp_i915_set_aperture(device_t dev, u_int32_t aperture) +{ + + return (agp_generic_set_aperture(dev, aperture)); +} + +static int +agp_i810_method_set_aperture(device_t dev, u_int32_t aperture) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + return (sc->match->driver->set_aperture(dev, aperture)); +} + /** - * Writes a GTT entry mapping the page at the given offset from the beginning - * of the aperture to the given physical address. + * Writes a GTT entry mapping the page at the given offset from the + * beginning of the aperture to the given physical address. Setup the + * caching mode according to flags. + * + * For gen 1, 2 and 3, GTT start is located at AGP_I810_GTT offset + * from corresponding BAR start. For gen 4, offset is 512KB + + * AGP_I810_GTT, for gen 5 and 6 it is 2MB + AGP_I810_GTT. + * + * Also, the bits of the physical page address above 4GB needs to be + * placed into bits 40-32 of PTE. */ static void -agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical, - int enabled) +agp_i810_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, + int flags) { - struct agp_i810_softc *sc = device_get_softc(dev); - u_int32_t pte; + uint32_t pte; - pte = (u_int32_t)physical | 1; - if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 || - sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) { - pte |= (physical & 0x0000000f00000000ull) >> 28; - } else { - /* If we do actually have memory above 4GB on an older system, - * crash cleanly rather than scribble on system memory, - * so we know we need to fix it. - */ - KASSERT((pte & 0x0000000f00000000ull) == 0, - (">4GB physical address in agp")); - } + pte = (u_int32_t)physical | I810_PTE_VALID; + if (flags == AGP_DCACHE_MEMORY) + pte |= I810_PTE_LOCAL; + else if (flags == AGP_USER_CACHED_MEMORY) + pte |= I830_PTE_SYSTEM_CACHED; + agp_i810_write_gtt(dev, index, pte); +} - switch (sc->chiptype) { - case CHIP_I810: - case CHIP_I830: - case CHIP_I855: - bus_write_4(sc->sc_res[0], - AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte); - break; - case CHIP_I915: - case CHIP_G33: - case CHIP_IGD: - bus_write_4(sc->sc_res[1], - (offset >> AGP_PAGE_SHIFT) * 4, pte); - break; - case CHIP_I965: - bus_write_4(sc->sc_res[0], - (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte); - break; - case CHIP_G4X: - bus_write_4(sc->sc_res[0], - (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte); - break; - } +static void +agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + bus_write_4(sc->sc_res[0], AGP_I810_GTT + index * 4, pte); + CTR2(KTR_AGP_I810, "810_pte %x %x", index, pte); } +static void +agp_i830_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, + int flags) +{ + uint32_t pte; + + pte = (u_int32_t)physical | I810_PTE_VALID; + if (flags == AGP_USER_CACHED_MEMORY) + pte |= I830_PTE_SYSTEM_CACHED; + agp_i810_write_gtt(dev, index, pte); +} + +static void +agp_i915_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, + int flags) +{ + uint32_t pte; + + pte = (u_int32_t)physical | I810_PTE_VALID; + if (flags == AGP_USER_CACHED_MEMORY) + pte |= I830_PTE_SYSTEM_CACHED; + pte |= (physical & 0x0000000f00000000ull) >> 28; + agp_i915_write_gtt(dev, index, pte); +} + +static void +agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + bus_write_4(sc->sc_res[1], index * 4, pte); + CTR2(KTR_AGP_I810, "915_pte %x %x", index, pte); +} + +static void +agp_i965_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, + int flags) +{ + uint32_t pte; + + pte = (u_int32_t)physical | I810_PTE_VALID; + if (flags == AGP_USER_CACHED_MEMORY) + pte |= I830_PTE_SYSTEM_CACHED; + pte |= (physical & 0x0000000f00000000ull) >> 28; + agp_i965_write_gtt(dev, index, pte); +} + +static void +agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte); + CTR2(KTR_AGP_I810, "965_pte %x %x", index, pte); +} + +static void +agp_g4x_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, + int flags) +{ + uint32_t pte; + + pte = (u_int32_t)physical | I810_PTE_VALID; + if (flags == AGP_USER_CACHED_MEMORY) + pte |= I830_PTE_SYSTEM_CACHED; + pte |= (physical & 0x0000000f00000000ull) >> 28; + agp_g4x_write_gtt(dev, index, pte); +} + +static void +agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte); + CTR2(KTR_AGP_I810, "g4x_pte %x %x", index, pte); +} + +static void +agp_sb_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical, + int flags) +{ + int type_mask, gfdt; + uint32_t pte; + + pte = (u_int32_t)physical | I810_PTE_VALID; + type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; + gfdt = (flags & AGP_USER_CACHED_MEMORY_GFDT) != 0 ? GEN6_PTE_GFDT : 0; + + if (type_mask == AGP_USER_MEMORY) + pte |= GEN6_PTE_UNCACHED; + else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) + pte |= GEN6_PTE_LLC_MLC | gfdt; + else + pte |= GEN6_PTE_LLC | gfdt; + + pte |= (physical & 0x000000ff00000000ull) >> 28; + agp_sb_write_gtt(dev, index, pte); +} + +static void +agp_sb_write_gtt(device_t dev, u_int index, uint32_t pte) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte); + CTR2(KTR_AGP_I810, "sb_pte %x %x", index, pte); +} + static int agp_i810_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) { struct agp_i810_softc *sc = device_get_softc(dev); + u_int index; if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) { - device_printf(dev, "failed: offset is 0x%08jx, shift is %d, entries is %d\n", (intmax_t)offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries); - return EINVAL; + device_printf(dev, "failed: offset is 0x%08jx, " + "shift is %d, entries is %d\n", (intmax_t)offset, + AGP_PAGE_SHIFT, sc->gatt->ag_entries); + return (EINVAL); } - - if ( sc->chiptype != CHIP_I810 ) { - if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { - device_printf(dev, "trying to bind into stolen memory"); - return EINVAL; - } + index = offset >> AGP_PAGE_SHIFT; + if (sc->stolen != 0 && index < sc->stolen) { + device_printf(dev, "trying to bind into stolen memory\n"); + return (EINVAL); } - - agp_i810_write_gtt_entry(dev, offset, physical, 1); - - return 0; + sc->match->driver->install_gtt_pte(dev, index, physical, 0); + return (0); } static int agp_i810_unbind_page(device_t dev, vm_offset_t offset) { - struct agp_i810_softc *sc = device_get_softc(dev); + struct agp_i810_softc *sc; + u_int index; + sc = device_get_softc(dev); if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) - return EINVAL; - - if ( sc->chiptype != CHIP_I810 ) { - if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { - device_printf(dev, "trying to unbind from stolen memory"); - return EINVAL; - } + return (EINVAL); + index = offset >> AGP_PAGE_SHIFT; + if (sc->stolen != 0 && index < sc->stolen) { + device_printf(dev, "trying to unbind from stolen memory\n"); + return (EINVAL); } + sc->match->driver->install_gtt_pte(dev, index, 0, 0); + return (0); +} - agp_i810_write_gtt_entry(dev, offset, 0, 0); +static u_int32_t +agp_i810_read_gtt_pte(device_t dev, u_int index) +{ + struct agp_i810_softc *sc; + u_int32_t pte; - return 0; + sc = device_get_softc(dev); + pte = bus_read_4(sc->sc_res[0], AGP_I810_GTT + index * 4); + return (pte); } +static u_int32_t +agp_i915_read_gtt_pte(device_t dev, u_int index) +{ + struct agp_i810_softc *sc; + u_int32_t pte; + + sc = device_get_softc(dev); + pte = bus_read_4(sc->sc_res[1], index * 4); + return (pte); +} + +static u_int32_t +agp_i965_read_gtt_pte(device_t dev, u_int index) +{ + struct agp_i810_softc *sc; + u_int32_t pte; + + sc = device_get_softc(dev); + pte = bus_read_4(sc->sc_res[0], index * 4 + (512 * 1024)); + return (pte); +} + +static u_int32_t +agp_g4x_read_gtt_pte(device_t dev, u_int index) +{ + struct agp_i810_softc *sc; + u_int32_t pte; + + sc = device_get_softc(dev); + pte = bus_read_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024)); + return (pte); +} + +static vm_paddr_t +agp_i810_read_gtt_pte_paddr(device_t dev, u_int index) +{ + struct agp_i810_softc *sc; + u_int32_t pte; + vm_paddr_t res; + + sc = device_get_softc(dev); + pte = sc->match->driver->read_gtt_pte(dev, index); + res = pte & ~PAGE_MASK; + return (res); +} + +static vm_paddr_t +agp_i915_read_gtt_pte_paddr(device_t dev, u_int index) +{ + struct agp_i810_softc *sc; + u_int32_t pte; + vm_paddr_t res; + + sc = device_get_softc(dev); + pte = sc->match->driver->read_gtt_pte(dev, index); + res = (pte & ~PAGE_MASK) | ((pte & 0xf0) << 28); + return (res); +} + +static vm_paddr_t +agp_sb_read_gtt_pte_paddr(device_t dev, u_int index) +{ + struct agp_i810_softc *sc; + u_int32_t pte; + vm_paddr_t res; + + sc = device_get_softc(dev); + pte = sc->match->driver->read_gtt_pte(dev, index); + res = (pte & ~PAGE_MASK) | ((pte & 0xff0) << 28); + return (res); +} + /* * Writing via memory mapped registers already flushes all TLBs. */ static void agp_i810_flush_tlb(device_t dev) { } static int agp_i810_enable(device_t dev, u_int32_t mode) { - return 0; + return (0); } static struct agp_memory * agp_i810_alloc_memory(device_t dev, int type, vm_size_t size) { - struct agp_i810_softc *sc = device_get_softc(dev); + struct agp_i810_softc *sc; struct agp_memory *mem; + vm_page_t m; - if ((size & (AGP_PAGE_SIZE - 1)) != 0) - return 0; + sc = device_get_softc(dev); - if (sc->agp.as_allocated + size > sc->agp.as_maxmem) - return 0; + if ((size & (AGP_PAGE_SIZE - 1)) != 0 || + sc->agp.as_allocated + size > sc->agp.as_maxmem) + return (0); if (type == 1) { /* * Mapping local DRAM into GATT. */ - if ( sc->chiptype != CHIP_I810 ) - return 0; + if (sc->match->driver->chiptype != CHIP_I810) + return (0); if (size != sc->dcache_size) - return 0; + return (0); } else if (type == 2) { /* * Type 2 is the contiguous physical memory type, that hands * back a physical address. This is used for cursors on i810. * Hand back as many single pages with physical as the user * wants, but only allow one larger allocation (ARGB cursor) * for simplicity. */ if (size != AGP_PAGE_SIZE) { if (sc->argb_cursor != NULL) - return 0; + return (0); /* Allocate memory for ARGB cursor, if we can. */ sc->argb_cursor = contigmalloc(size, M_AGP, 0, 0, ~0, PAGE_SIZE, 0); if (sc->argb_cursor == NULL) - return 0; + return (0); } } mem = malloc(sizeof *mem, M_AGP, M_WAITOK); mem->am_id = sc->agp.as_nextid++; mem->am_size = size; mem->am_type = type; if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE)) mem->am_obj = vm_object_allocate(OBJT_DEFAULT, - atop(round_page(size))); + atop(round_page(size))); else mem->am_obj = 0; if (type == 2) { if (size == AGP_PAGE_SIZE) { /* * Allocate and wire down the page now so that we can * get its physical address. */ - vm_page_t m; - VM_OBJECT_LOCK(mem->am_obj); m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY | VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY); VM_OBJECT_UNLOCK(mem->am_obj); mem->am_physical = VM_PAGE_TO_PHYS(m); } else { /* Our allocation is already nicely wired down for us. * Just grab the physical address. */ mem->am_physical = vtophys(sc->argb_cursor); } - } else { + } else mem->am_physical = 0; - } mem->am_offset = 0; mem->am_is_bound = 0; TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link); sc->agp.as_allocated += size; - return mem; + return (mem); } static int agp_i810_free_memory(device_t dev, struct agp_memory *mem) { - struct agp_i810_softc *sc = device_get_softc(dev); + struct agp_i810_softc *sc; + vm_page_t m; if (mem->am_is_bound) - return EBUSY; + return (EBUSY); + sc = device_get_softc(dev); + if (mem->am_type == 2) { if (mem->am_size == AGP_PAGE_SIZE) { /* * Unwire the page which we wired in alloc_memory. */ - vm_page_t m; - VM_OBJECT_LOCK(mem->am_obj); m = vm_page_lookup(mem->am_obj, 0); vm_page_lock(m); vm_page_unwire(m, 0); vm_page_unlock(m); VM_OBJECT_UNLOCK(mem->am_obj); } else { contigfree(sc->argb_cursor, mem->am_size, M_AGP); sc->argb_cursor = NULL; } } sc->agp.as_allocated -= mem->am_size; TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link); if (mem->am_obj) vm_object_deallocate(mem->am_obj); free(mem, M_AGP); - return 0; + return (0); } static int -agp_i810_bind_memory(device_t dev, struct agp_memory *mem, - vm_offset_t offset) +agp_i810_bind_memory(device_t dev, struct agp_memory *mem, vm_offset_t offset) { - struct agp_i810_softc *sc = device_get_softc(dev); + struct agp_i810_softc *sc; vm_offset_t i; /* Do some sanity checks first. */ if ((offset & (AGP_PAGE_SIZE - 1)) != 0 || offset + mem->am_size > AGP_GET_APERTURE(dev)) { device_printf(dev, "binding memory at bad offset %#x\n", (int)offset); - return EINVAL; + return (EINVAL); } + sc = device_get_softc(dev); if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { mtx_lock(&sc->agp.as_lock); if (mem->am_is_bound) { mtx_unlock(&sc->agp.as_lock); - return EINVAL; + return (EINVAL); } /* The memory's already wired down, just stick it in the GTT. */ for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { - agp_i810_write_gtt_entry(dev, offset + i, - mem->am_physical + i, 1); + sc->match->driver->install_gtt_pte(dev, (offset + i) >> + AGP_PAGE_SHIFT, mem->am_physical + i, 0); } agp_flush_cache(); mem->am_offset = offset; mem->am_is_bound = 1; mtx_unlock(&sc->agp.as_lock); - return 0; + return (0); } if (mem->am_type != 1) - return agp_generic_bind_memory(dev, mem, offset); + return (agp_generic_bind_memory(dev, mem, offset)); - if ( sc->chiptype != CHIP_I810 ) - return EINVAL; - - for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { + /* + * Mapping local DRAM into GATT. + */ + if (sc->match->driver->chiptype != CHIP_I810) + return (EINVAL); + for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) bus_write_4(sc->sc_res[0], AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3); - } - return 0; + return (0); } static int agp_i810_unbind_memory(device_t dev, struct agp_memory *mem) { - struct agp_i810_softc *sc = device_get_softc(dev); + struct agp_i810_softc *sc; vm_offset_t i; + sc = device_get_softc(dev); + if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { mtx_lock(&sc->agp.as_lock); if (!mem->am_is_bound) { mtx_unlock(&sc->agp.as_lock); - return EINVAL; + return (EINVAL); } for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { - agp_i810_write_gtt_entry(dev, mem->am_offset + i, - 0, 0); + sc->match->driver->install_gtt_pte(dev, + (mem->am_offset + i) >> AGP_PAGE_SHIFT, 0, 0); } agp_flush_cache(); mem->am_is_bound = 0; mtx_unlock(&sc->agp.as_lock); - return 0; + return (0); } if (mem->am_type != 1) - return agp_generic_unbind_memory(dev, mem); + return (agp_generic_unbind_memory(dev, mem)); - if ( sc->chiptype != CHIP_I810 ) - return EINVAL; - + if (sc->match->driver->chiptype != CHIP_I810) + return (EINVAL); for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { - bus_write_4(sc->sc_res[0], - AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0); + sc->match->driver->install_gtt_pte(dev, i >> AGP_PAGE_SHIFT, + 0, 0); } - - return 0; + return (0); } static device_method_t agp_i810_methods[] = { /* Device interface */ DEVMETHOD(device_identify, agp_i810_identify), DEVMETHOD(device_probe, agp_i810_probe), DEVMETHOD(device_attach, agp_i810_attach), DEVMETHOD(device_detach, agp_i810_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, agp_i810_resume), /* AGP interface */ DEVMETHOD(agp_get_aperture, agp_generic_get_aperture), - DEVMETHOD(agp_set_aperture, agp_i810_set_aperture), + DEVMETHOD(agp_set_aperture, agp_i810_method_set_aperture), DEVMETHOD(agp_bind_page, agp_i810_bind_page), DEVMETHOD(agp_unbind_page, agp_i810_unbind_page), DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb), DEVMETHOD(agp_enable, agp_i810_enable), DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory), DEVMETHOD(agp_free_memory, agp_i810_free_memory), DEVMETHOD(agp_bind_memory, agp_i810_bind_memory), DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory), + DEVMETHOD(agp_chipset_flush, agp_intel_gtt_chipset_flush), { 0, 0 } }; static driver_t agp_i810_driver = { "agp", agp_i810_methods, sizeof(struct agp_i810_softc), }; static devclass_t agp_devclass; DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0); MODULE_DEPEND(agp_i810, agp, 1, 1, 1); MODULE_DEPEND(agp_i810, pci, 1, 1, 1); + +extern vm_page_t bogus_page; + +void +agp_intel_gtt_clear_range(device_t dev, u_int first_entry, u_int num_entries) +{ + struct agp_i810_softc *sc; + u_int i; + + sc = device_get_softc(dev); + for (i = 0; i < num_entries; i++) + sc->match->driver->install_gtt_pte(dev, first_entry + i, + VM_PAGE_TO_PHYS(bogus_page), 0); + sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1); +} + +void +agp_intel_gtt_insert_pages(device_t dev, u_int first_entry, u_int num_entries, + vm_page_t *pages, u_int flags) +{ + struct agp_i810_softc *sc; + u_int i; + + sc = device_get_softc(dev); + for (i = 0; i < num_entries; i++) { + MPASS(pages[i]->valid == VM_PAGE_BITS_ALL); + MPASS(pages[i]->wire_count > 0); + sc->match->driver->install_gtt_pte(dev, first_entry + i, + VM_PAGE_TO_PHYS(pages[i]), flags); + } + sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1); +} + +struct intel_gtt +agp_intel_gtt_get(device_t dev) +{ + struct agp_i810_softc *sc; + struct intel_gtt res; + + sc = device_get_softc(dev); + res.stolen_size = sc->stolen_size; + res.gtt_total_entries = sc->gtt_total_entries; + res.gtt_mappable_entries = sc->gtt_mappable_entries; + res.do_idle_maps = 0; + res.scratch_page_dma = VM_PAGE_TO_PHYS(bogus_page); + return (res); +} + +static int +agp_i810_chipset_flush_setup(device_t dev) +{ + + return (0); +} + +static void +agp_i810_chipset_flush_teardown(device_t dev) +{ + + /* Nothing to do. */ +} + +static void +agp_i810_chipset_flush(device_t dev) +{ + + /* Nothing to do. */ +} + +static void +agp_i830_chipset_flush(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t hic; + int i; + + sc = device_get_softc(dev); + pmap_invalidate_cache(); + hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC); + bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1 << 31)); + for (i = 0; i < 20000 /* 1 sec */; i++) { + hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC); + if ((hic & (1 << 31)) != 0) + break; + DELAY(50); + } +} + +static int +agp_i915_chipset_flush_alloc_page(device_t dev, uint64_t start, uint64_t end) +{ + struct agp_i810_softc *sc; + device_t vga; + + sc = device_get_softc(dev); + vga = device_get_parent(dev); + sc->sc_flush_page_rid = 100; + sc->sc_flush_page_res = BUS_ALLOC_RESOURCE(device_get_parent(vga), dev, + SYS_RES_MEMORY, &sc->sc_flush_page_rid, start, end, PAGE_SIZE, + RF_ACTIVE); + if (sc->sc_flush_page_res == NULL) { + device_printf(dev, "Failed to allocate flush page at 0x%jx\n", + (uintmax_t)start); + return (EINVAL); + } + sc->sc_flush_page_vaddr = rman_get_virtual(sc->sc_flush_page_res); + if (bootverbose) { + device_printf(dev, "Allocated flush page phys 0x%jx virt %p\n", + (uintmax_t)rman_get_start(sc->sc_flush_page_res), + sc->sc_flush_page_vaddr); + } + return (0); +} + +static void +agp_i915_chipset_flush_free_page(device_t dev) +{ + struct agp_i810_softc *sc; + device_t vga; + + sc = device_get_softc(dev); + vga = device_get_parent(dev); + if (sc->sc_flush_page_res == NULL) + return; + BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY, + sc->sc_flush_page_rid, sc->sc_flush_page_res); + BUS_RELEASE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY, + sc->sc_flush_page_rid, sc->sc_flush_page_res); +} + +static int +agp_i915_chipset_flush_setup(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t temp; + int error; + + sc = device_get_softc(dev); + temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4); + if ((temp & 1) != 0) { + temp &= ~1; + if (bootverbose) + device_printf(dev, + "Found already configured flush page at 0x%jx\n", + (uintmax_t)temp); + sc->sc_bios_allocated_flush_page = 1; + /* + * In the case BIOS initialized the flush pointer (?) + * register, expect that BIOS also set up the resource + * for the page. + */ + error = agp_i915_chipset_flush_alloc_page(dev, temp, + temp + PAGE_SIZE - 1); + if (error != 0) + return (error); + } else { + sc->sc_bios_allocated_flush_page = 0; + error = agp_i915_chipset_flush_alloc_page(dev, 0, 0xffffffff); + if (error != 0) + return (error); + temp = rman_get_start(sc->sc_flush_page_res); + pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp | 1, 4); + } + return (0); +} + +static void +agp_i915_chipset_flush_teardown(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t temp; + + sc = device_get_softc(dev); + if (sc->sc_flush_page_res == NULL) + return; + if (!sc->sc_bios_allocated_flush_page) { + temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4); + temp &= ~1; + pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp, 4); + } + agp_i915_chipset_flush_free_page(dev); +} + +static int +agp_i965_chipset_flush_setup(device_t dev) +{ + struct agp_i810_softc *sc; + uint64_t temp; + uint32_t temp_hi, temp_lo; + int error; + + sc = device_get_softc(dev); + + temp_hi = pci_read_config(sc->bdev, AGP_I965_IFPADDR + 4, 4); + temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4); + + if ((temp_lo & 1) != 0) { + temp = ((uint64_t)temp_hi << 32) | (temp_lo & ~1); + if (bootverbose) + device_printf(dev, + "Found already configured flush page at 0x%jx\n", + (uintmax_t)temp); + sc->sc_bios_allocated_flush_page = 1; + /* + * In the case BIOS initialized the flush pointer (?) + * register, expect that BIOS also set up the resource + * for the page. + */ + error = agp_i915_chipset_flush_alloc_page(dev, temp, + temp + PAGE_SIZE - 1); + if (error != 0) + return (error); + } else { + sc->sc_bios_allocated_flush_page = 0; + error = agp_i915_chipset_flush_alloc_page(dev, 0, ~0); + if (error != 0) + return (error); + temp = rman_get_start(sc->sc_flush_page_res); + pci_write_config(sc->bdev, AGP_I965_IFPADDR + 4, + (temp >> 32) & UINT32_MAX, 4); + pci_write_config(sc->bdev, AGP_I965_IFPADDR, + (temp & UINT32_MAX) | 1, 4); + } + return (0); +} + +static void +agp_i965_chipset_flush_teardown(device_t dev) +{ + struct agp_i810_softc *sc; + uint32_t temp_lo; + + sc = device_get_softc(dev); + if (sc->sc_flush_page_res == NULL) + return; + if (!sc->sc_bios_allocated_flush_page) { + temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4); + temp_lo &= ~1; + pci_write_config(sc->bdev, AGP_I965_IFPADDR, temp_lo, 4); + } + agp_i915_chipset_flush_free_page(dev); +} + +static void +agp_i915_chipset_flush(device_t dev) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + *(uint32_t *)sc->sc_flush_page_vaddr = 1; +} + +int +agp_intel_gtt_chipset_flush(device_t dev) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(dev); + sc->match->driver->chipset_flush(dev); + return (0); +} + +void +agp_intel_gtt_unmap_memory(device_t dev, struct sglist *sg_list) +{ +} + +int +agp_intel_gtt_map_memory(device_t dev, vm_page_t *pages, u_int num_entries, + struct sglist **sg_list) +{ + struct agp_i810_softc *sc; + struct sglist *sg; + int i; +#if 0 + int error; + bus_dma_tag_t dmat; +#endif + + if (*sg_list != NULL) + return (0); + sc = device_get_softc(dev); + sg = sglist_alloc(num_entries, M_WAITOK /* XXXKIB */); + for (i = 0; i < num_entries; i++) { + sg->sg_segs[i].ss_paddr = VM_PAGE_TO_PHYS(pages[i]); + sg->sg_segs[i].ss_len = PAGE_SIZE; + } + +#if 0 + error = bus_dma_tag_create(bus_get_dma_tag(dev), + 1 /* alignment */, 0 /* boundary */, + 1ULL << sc->match->busdma_addr_mask_sz /* lowaddr */, + BUS_SPACE_MAXADDR /* highaddr */, + NULL /* filtfunc */, NULL /* filtfuncarg */, + BUS_SPACE_MAXADDR /* maxsize */, + BUS_SPACE_UNRESTRICTED /* nsegments */, + BUS_SPACE_MAXADDR /* maxsegsz */, + 0 /* flags */, NULL /* lockfunc */, NULL /* lockfuncarg */, + &dmat); + if (error != 0) { + sglist_free(sg); + return (error); + } + /* XXXKIB */ +#endif + *sg_list = sg; + return (0); +} + +void +agp_intel_gtt_insert_sg_entries(device_t dev, struct sglist *sg_list, + u_int first_entry, u_int flags) +{ + struct agp_i810_softc *sc; + vm_paddr_t spaddr; + size_t slen; + u_int i, j; + + sc = device_get_softc(dev); + for (i = j = 0; j < sg_list->sg_nseg; j++) { + spaddr = sg_list->sg_segs[i].ss_paddr; + slen = sg_list->sg_segs[i].ss_len; + for (; slen > 0; i++) { + sc->match->driver->install_gtt_pte(dev, first_entry + i, + spaddr, flags); + spaddr += AGP_PAGE_SIZE; + slen -= AGP_PAGE_SIZE; + } + } + sc->match->driver->read_gtt_pte(dev, first_entry + i - 1); +} + +void +intel_gtt_clear_range(u_int first_entry, u_int num_entries) +{ + + agp_intel_gtt_clear_range(intel_agp, first_entry, num_entries); +} + +void +intel_gtt_insert_pages(u_int first_entry, u_int num_entries, vm_page_t *pages, + u_int flags) +{ + + agp_intel_gtt_insert_pages(intel_agp, first_entry, num_entries, + pages, flags); +} + +struct intel_gtt +intel_gtt_get(void) +{ + + return (agp_intel_gtt_get(intel_agp)); +} + +int +intel_gtt_chipset_flush(void) +{ + + return (agp_intel_gtt_chipset_flush(intel_agp)); +} + +void +intel_gtt_unmap_memory(struct sglist *sg_list) +{ + + agp_intel_gtt_unmap_memory(intel_agp, sg_list); +} + +int +intel_gtt_map_memory(vm_page_t *pages, u_int num_entries, + struct sglist **sg_list) +{ + + return (agp_intel_gtt_map_memory(intel_agp, pages, num_entries, + sg_list)); +} + +void +intel_gtt_insert_sg_entries(struct sglist *sg_list, u_int first_entry, + u_int flags) +{ + + agp_intel_gtt_insert_sg_entries(intel_agp, sg_list, first_entry, flags); +} + +device_t +intel_gtt_get_bridge_device(void) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(intel_agp); + return (sc->bdev); +} + +vm_paddr_t +intel_gtt_read_pte_paddr(u_int entry) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(intel_agp); + return (sc->match->driver->read_gtt_pte_paddr(intel_agp, entry)); +} + +u_int32_t +intel_gtt_read_pte(u_int entry) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(intel_agp); + return (sc->match->driver->read_gtt_pte(intel_agp, entry)); +} + +void +intel_gtt_write(u_int entry, uint32_t val) +{ + struct agp_i810_softc *sc; + + sc = device_get_softc(intel_agp); + return (sc->match->driver->write_gtt(intel_agp, entry, val)); +} Index: head/sys/dev/agp/agp_i810.h =================================================================== --- head/sys/dev/agp/agp_i810.h (nonexistent) +++ head/sys/dev/agp/agp_i810.h (revision 235782) @@ -0,0 +1,101 @@ +/*- + * Copyright (c) 2011 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by Konstantin Belousov under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef AGP_AGP_I810_H +#define AGP_AGP_I810_H + +#include +#include + +#include +#include + +/* Special gtt memory types */ +#define AGP_DCACHE_MEMORY 1 +#define AGP_PHYS_MEMORY 2 + +/* New caching attributes for gen6/sandybridge */ +#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2) +#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4) + +/* flag for GFDT type */ +#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) + +struct intel_gtt { + /* Size of memory reserved for graphics by the BIOS */ + u_int stolen_size; + /* Total number of gtt entries. */ + u_int gtt_total_entries; + /* + * Part of the gtt that is mappable by the cpu, for those + * chips where this is not the full gtt. + */ + u_int gtt_mappable_entries; + + /* + * Always false. + */ + u_int do_idle_maps; + + /* + * Share the scratch page dma with ppgtts. + */ + vm_paddr_t scratch_page_dma; +}; + +struct intel_gtt agp_intel_gtt_get(device_t dev); +int agp_intel_gtt_chipset_flush(device_t dev); +void agp_intel_gtt_unmap_memory(device_t dev, struct sglist *sg_list); +void agp_intel_gtt_clear_range(device_t dev, u_int first_entry, + u_int num_entries); +int agp_intel_gtt_map_memory(device_t dev, vm_page_t *pages, u_int num_entries, + struct sglist **sg_list); +void agp_intel_gtt_insert_sg_entries(device_t dev, struct sglist *sg_list, + u_int pg_start, u_int flags); +void agp_intel_gtt_insert_pages(device_t dev, u_int first_entry, + u_int num_entries, vm_page_t *pages, u_int flags); + +struct intel_gtt intel_gtt_get(void); +int intel_gtt_chipset_flush(void); +void intel_gtt_unmap_memory(struct sglist *sg_list); +void intel_gtt_clear_range(u_int first_entry, u_int num_entries); +int intel_gtt_map_memory(vm_page_t *pages, u_int num_entries, + struct sglist **sg_list); +void intel_gtt_insert_sg_entries(struct sglist *sg_list, u_int pg_start, + u_int flags); +void intel_gtt_insert_pages(u_int first_entry, u_int num_entries, + vm_page_t *pages, u_int flags); +vm_paddr_t intel_gtt_read_pte_paddr(u_int entry); +u_int32_t intel_gtt_read_pte(u_int entry); +device_t intel_gtt_get_bridge_device(void); +void intel_gtt_write(u_int entry, uint32_t val); + +#endif Property changes on: head/sys/dev/agp/agp_i810.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/agp/agp_if.m =================================================================== --- head/sys/dev/agp/agp_if.m (revision 235781) +++ head/sys/dev/agp/agp_if.m (revision 235782) @@ -1,134 +1,146 @@ #- # Copyright (c) 2000 Doug Rabson # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS # OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF # SUCH DAMAGE. # # $FreeBSD$ # #include # # The AGP interface is used internally to the agp driver to isolate the # differences between various AGP chipsets into chipset mini drivers. It # should not be used outside the AGP driver. The kernel api for accessing # AGP functionality is described in # INTERFACE agp; +CODE { + static int + null_agp_chipset_flush(device_t dev) + { + return (ENXIO); + } +}; + # # Return the current aperture size. # METHOD u_int32_t get_aperture { device_t dev; }; # # Set the size of the aperture. Return EINVAL on error or 0 on success. # METHOD int set_aperture { device_t dev; u_int32_t aperture; }; # # Bind a single page in the AGP aperture to a given physical address. # The offset is a byte offset within the aperture which must be # aligned to an AGP page boundary. # METHOD int bind_page { device_t dev; vm_offset_t offset; vm_offset_t physical; }; # # Unbind a single page in the AGP aperture. # METHOD int unbind_page { device_t dev; vm_offset_t offset; }; # # Flush the GATT TLB. This is used after a call to bind_page to # ensure that any mappings cached in the chipset are discarded. # METHOD void flush_tlb { device_t dev; }; # # Enable the agp hardware with the relavent mode. The mode bits are # defined in # METHOD int enable { device_t dev; u_int32_t mode; }; # # Allocate memory of a given type. The type is a chipset-specific # code which is used by certain integrated agp graphics chips # (basically just the i810 for now) to access special features of # the chipset. An opaque handle representing the memory region is # returned and can be used as an argument to free_memory, bind_memory # and unbind_memory. # # The size is specified in bytes but must be a multiple of the AGP # page size. # METHOD struct agp_memory * alloc_memory { device_t dev; int type; vm_size_t size; }; # # Free a memory region previously allocated with alloc_memory. Return # EBUSY if the memory is bound. # METHOD int free_memory { device_t dev; struct agp_memory *mem; }; # # Bind a memory region to a specific byte offset within the chipset's # AGP aperture. This effectively defines a range of contiguous # physical address which alias the (possibly uncontiguous) pages in # the memory region. # METHOD int bind_memory { device_t dev; struct agp_memory *mem; vm_offset_t offset; }; # # Unbind a memory region bound with bind_memory. # METHOD int unbind_memory { device_t dev; struct agp_memory *handle; }; + +METHOD int chipset_flush { + device_t dev; +} DEFAULT null_agp_chipset_flush; Index: head/sys/dev/agp/agppriv.h =================================================================== --- head/sys/dev/agp/agppriv.h (revision 235781) +++ head/sys/dev/agp/agppriv.h (revision 235782) @@ -1,109 +1,109 @@ /*- * Copyright (c) 2000 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _PCI_AGPPRIV_H_ #define _PCI_AGPPRIV_H_ /* * This file *must not* be included by code outside the agp driver itself. */ #include #include #ifdef AGP_DEBUG #define AGP_DPF(fmt, ...) do { \ printf("agp: " fmt, ##__VA_ARGS__); \ } while (0) #else #define AGP_DPF(fmt, ...) do {} while (0) #endif #include "agp_if.h" /* * Data structure to describe an AGP memory allocation. */ TAILQ_HEAD(agp_memory_list, agp_memory); struct agp_memory { TAILQ_ENTRY(agp_memory) am_link; /* wiring for the tailq */ int am_id; /* unique id for block */ vm_size_t am_size; /* number of bytes allocated */ int am_type; /* chipset specific type */ struct vm_object *am_obj; /* VM object owning pages */ vm_offset_t am_physical; /* bogus hack for i810 */ vm_offset_t am_offset; /* page offset if bound */ int am_is_bound; /* non-zero if bound */ }; /* * All chipset drivers must have this at the start of their softc. */ struct agp_softc { struct resource *as_aperture; /* location of aperture */ int as_aperture_rid; u_int32_t as_maxmem; /* allocation upper bound */ u_int32_t as_allocated; /* amount allocated */ enum agp_acquire_state as_state; struct agp_memory_list as_memory; /* list of allocated memory */ int as_nextid; /* next memory block id */ int as_isopen; /* user device is open */ - struct cdev *as_devnode; /* from make_dev */ + struct cdev *as_devnode; /* from make_dev */ struct mtx as_lock; /* lock for access to GATT */ }; struct agp_gatt { u_int32_t ag_entries; u_int32_t *ag_virtual; vm_offset_t ag_physical; }; void agp_flush_cache(void); u_int8_t agp_find_caps(device_t dev); struct agp_gatt *agp_alloc_gatt(device_t dev); void agp_set_aperture_resource(device_t dev, int rid); void agp_free_cdev(device_t dev); void agp_free_gatt(struct agp_gatt *gatt); void agp_free_res(device_t dev); int agp_generic_attach(device_t dev); int agp_generic_detach(device_t dev); u_int32_t agp_generic_get_aperture(device_t dev); int agp_generic_set_aperture(device_t dev, u_int32_t aperture); int agp_generic_enable(device_t dev, u_int32_t mode); struct agp_memory *agp_generic_alloc_memory(device_t dev, int type, vm_size_t size); int agp_generic_free_memory(device_t dev, struct agp_memory *mem); int agp_generic_bind_memory(device_t dev, struct agp_memory *mem, vm_offset_t offset); int agp_generic_unbind_memory(device_t dev, struct agp_memory *mem); #endif /* !_PCI_AGPPRIV_H_ */ Index: head/sys/dev/agp/agpreg.h =================================================================== --- head/sys/dev/agp/agpreg.h (revision 235781) +++ head/sys/dev/agp/agpreg.h (revision 235782) @@ -1,342 +1,419 @@ /*- * Copyright (c) 2000 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _PCI_AGPREG_H_ #define _PCI_AGPREG_H_ /* * Offsets for various AGP configuration registers. */ #define AGP_APBASE PCIR_BAR(0) /* * Offsets from the AGP Capability pointer. */ #define AGP_CAPID 0x0 #define AGP_STATUS 0x4 #define AGP_COMMAND 0x8 #define AGP_STATUS_AGP3 0x0008 #define AGP_STATUS_RQ_MASK 0xff000000 #define AGP_COMMAND_RQ_MASK 0xff000000 #define AGP_STATUS_ARQSZ_MASK 0xe000 #define AGP_COMMAND_ARQSZ_MASK 0xe000 #define AGP_STATUS_CAL_MASK 0x1c00 #define AGP_COMMAND_CAL_MASK 0x1c00 #define AGP_STATUS_ISOCH 0x10000 #define AGP_STATUS_SBA 0x0200 #define AGP_STATUS_ITA_COH 0x0100 #define AGP_STATUS_GART64 0x0080 #define AGP_STATUS_HTRANS 0x0040 #define AGP_STATUS_64BIT 0x0020 #define AGP_STATUS_FW 0x0010 #define AGP_COMMAND_RQ_MASK 0xff000000 #define AGP_COMMAND_ARQSZ_MASK 0xe000 #define AGP_COMMAND_CAL_MASK 0x1c00 #define AGP_COMMAND_SBA 0x0200 #define AGP_COMMAND_AGP 0x0100 #define AGP_COMMAND_GART64 0x0080 #define AGP_COMMAND_64BIT 0x0020 #define AGP_COMMAND_FW 0x0010 /* * Config offsets for Intel AGP chipsets. */ #define AGP_INTEL_NBXCFG 0x50 #define AGP_INTEL_ERRSTS 0x91 #define AGP_INTEL_AGPCTRL 0xb0 #define AGP_INTEL_APSIZE 0xb4 #define AGP_INTEL_ATTBASE 0xb8 /* * Config offsets for Intel i8xx/E7xxx AGP chipsets. */ #define AGP_INTEL_MCHCFG 0x50 #define AGP_INTEL_I820_RDCR 0x51 #define AGP_INTEL_I845_AGPM 0x51 #define AGP_INTEL_I8XX_ERRSTS 0xc8 /* * Config offsets for VIA AGP 2.x chipsets. */ #define AGP_VIA_GARTCTRL 0x80 #define AGP_VIA_APSIZE 0x84 #define AGP_VIA_ATTBASE 0x88 /* * Config offsets for VIA AGP 3.0 chipsets. */ #define AGP3_VIA_GARTCTRL 0x90 #define AGP3_VIA_APSIZE 0x94 #define AGP3_VIA_ATTBASE 0x98 #define AGP_VIA_AGPSEL 0xfd /* * Config offsets for SiS AGP chipsets. */ #define AGP_SIS_ATTBASE 0x90 #define AGP_SIS_WINCTRL 0x94 #define AGP_SIS_TLBCTRL 0x97 #define AGP_SIS_TLBFLUSH 0x98 /* * Config offsets for Ali AGP chipsets. */ #define AGP_ALI_AGPCTRL 0xb8 #define AGP_ALI_ATTBASE 0xbc #define AGP_ALI_TLBCTRL 0xc0 /* * Config offsets for the AMD 751 chipset. */ #define AGP_AMD751_APBASE 0x10 #define AGP_AMD751_REGISTERS 0x14 #define AGP_AMD751_APCTRL 0xac #define AGP_AMD751_MODECTRL 0xb0 #define AGP_AMD751_MODECTRL_SYNEN 0x80 #define AGP_AMD751_MODECTRL2 0xb2 #define AGP_AMD751_MODECTRL2_G1LM 0x01 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 #define AGP_AMD751_MODECTRL2_NGSE 0x08 /* * Memory mapped register offsets for AMD 751 chipset. */ #define AGP_AMD751_CAPS 0x00 #define AGP_AMD751_CAPS_EHI 0x0800 #define AGP_AMD751_CAPS_P2P 0x0400 #define AGP_AMD751_CAPS_MPC 0x0200 #define AGP_AMD751_CAPS_VBE 0x0100 #define AGP_AMD751_CAPS_REV 0x00ff #define AGP_AMD751_STATUS 0x02 #define AGP_AMD751_STATUS_P2PS 0x0800 #define AGP_AMD751_STATUS_GCS 0x0400 #define AGP_AMD751_STATUS_MPS 0x0200 #define AGP_AMD751_STATUS_VBES 0x0100 #define AGP_AMD751_STATUS_P2PE 0x0008 #define AGP_AMD751_STATUS_GCE 0x0004 #define AGP_AMD751_STATUS_VBEE 0x0001 #define AGP_AMD751_ATTBASE 0x04 #define AGP_AMD751_TLBCTRL 0x0c /* * Config registers for i810 device 0 */ #define AGP_I810_SMRAM 0x70 #define AGP_I810_SMRAM_GMS 0xc0 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 #define AGP_I810_MISCC 0x72 #define AGP_I810_MISCC_WINSIZE 0x0001 #define AGP_I810_MISCC_WINSIZE_64 0x0000 #define AGP_I810_MISCC_WINSIZE_32 0x0001 #define AGP_I810_MISCC_PLCK 0x0008 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 #define AGP_I810_MISCC_WPTC 0x0030 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 #define AGP_I810_MISCC_WPTC_62 0x0010 #define AGP_I810_MISCC_WPTC_50 0x0020 #define AGP_I810_MISCC_WPTC_37 0x0030 #define AGP_I810_MISCC_RPTC 0x00c0 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 #define AGP_I810_MISCC_RPTC_62 0x0040 #define AGP_I810_MISCC_RPTC_50 0x0080 #define AGP_I810_MISCC_RPTC_37 0x00c0 /* * Config registers for i810 device 1 */ #define AGP_I810_GMADR 0x10 #define AGP_I810_MMADR 0x14 +#define I810_PTE_VALID 0x00000001 + /* + * Cache control + * + * Pre-Sandybridge bits + */ +#define I810_PTE_MAIN_UNCACHED 0x00000000 +#define I810_PTE_LOCAL 0x00000002 /* Non-snooped main phys memory */ +#define I830_PTE_SYSTEM_CACHED 0x00000006 /* Snooped main phys memory */ + +/* + * Sandybridge + * LLC - Last Level Cache + * MMC - Mid Level Cache + */ +#define GEN6_PTE_RESERVED 0x00000000 +#define GEN6_PTE_UNCACHED 0x00000002 /* Do not cache */ +#define GEN6_PTE_LLC 0x00000004 /* Cache in LLC */ +#define GEN6_PTE_LLC_MLC 0x00000006 /* Cache in LLC and MLC */ +#define GEN6_PTE_GFDT 0x00000008 /* Graphics Data Type */ + +/* * Memory mapped register offsets for i810 chipset. */ #define AGP_I810_PGTBL_CTL 0x2020 +#define AGP_I810_PGTBL_ENABLED 0x00000001 /** * This field determines the actual size of the global GTT on the 965 * and G33 */ #define AGP_I810_PGTBL_SIZE_MASK 0x0000000e #define AGP_I810_PGTBL_SIZE_512KB (0 << 1) #define AGP_I810_PGTBL_SIZE_256KB (1 << 1) -#define AGP_I810_PGTBL_SIZE_128KB (2 << 1) +#define AGP_I810_PGTBL_SIZE_128KB (2 << 1) +#define AGP_I810_PGTBL_SIZE_1MB (3 << 1) +#define AGP_I810_PGTBL_SIZE_2MB (4 << 1) +#define AGP_I810_PGTBL_SIZE_1_5MB (5 << 1) +#define AGP_G33_GCC1_SIZE_MASK (3 << 8) +#define AGP_G33_GCC1_SIZE_1M (1 << 8) +#define AGP_G33_GCC1_SIZE_2M (2 << 8) +#define AGP_G4x_GCC1_SIZE_MASK (0xf << 8) +#define AGP_G4x_GCC1_SIZE_1M (0x1 << 8) +#define AGP_G4x_GCC1_SIZE_2M (0x3 << 8) +#define AGP_G4x_GCC1_SIZE_VT_EN (0x8 << 8) +#define AGP_G4x_GCC1_SIZE_VT_1M \ + (AGP_G4x_GCC1_SIZE_1M | AGP_G4x_GCC1_SIZE_VT_EN) +#define AGP_G4x_GCC1_SIZE_VT_1_5M ((0x2 << 8) | AGP_G4x_GCC1_SIZE_VT_EN) +#define AGP_G4x_GCC1_SIZE_VT_2M \ + (AGP_G4x_GCC1_SIZE_2M | AGP_G4x_GCC1_SIZE_VT_EN) + #define AGP_I810_DRT 0x3000 #define AGP_I810_DRT_UNPOPULATED 0x00 #define AGP_I810_DRT_POPULATED 0x01 #define AGP_I810_GTT 0x10000 /* * Config registers for i830MG device 0 */ #define AGP_I830_GCC1 0x52 #define AGP_I830_GCC1_DEV2 0x08 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 #define AGP_I830_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */ #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 #define AGP_I830_GCC1_GMASIZE 0x01 #define AGP_I830_GCC1_GMASIZE_64 0x01 #define AGP_I830_GCC1_GMASIZE_128 0x00 +#define AGP_I830_HIC 0x70 /* * Config registers for 852GM/855GM/865G device 0 */ #define AGP_I855_GCC1 0x52 #define AGP_I855_GCC1_DEV2 0x08 #define AGP_I855_GCC1_DEV2_ENABLED 0x00 #define AGP_I855_GCC1_DEV2_DISABLED 0x08 #define AGP_I855_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */ #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 /* * 852GM/855GM variant identification */ #define AGP_I85X_CAPID 0x44 #define AGP_I85X_VARIANT_MASK 0x7 #define AGP_I85X_VARIANT_SHIFT 5 #define AGP_I855_GME 0x0 #define AGP_I855_GM 0x4 #define AGP_I852_GME 0x2 #define AGP_I852_GM 0x5 /* * 915G registers */ #define AGP_I915_GMADR 0x18 #define AGP_I915_MMADR 0x10 #define AGP_I915_GTTADR 0x1C #define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 #define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 #define AGP_I915_DEVEN 0x54 +#define AGP_SB_DEVEN_D2EN 0x10 /* SB+ has IGD enabled bit */ +#define AGP_SB_DEVEN_D2EN_ENABLED 0x10 /* in different place */ +#define AGP_SB_DEVEN_D2EN_DISABLED 0x00 #define AGP_I915_DEVEN_D2F0 0x08 #define AGP_I915_DEVEN_D2F0_ENABLED 0x08 #define AGP_I915_DEVEN_D2F0_DISABLED 0x00 #define AGP_I915_MSAC 0x62 #define AGP_I915_MSAC_GMASIZE 0x02 #define AGP_I915_MSAC_GMASIZE_128 0x02 #define AGP_I915_MSAC_GMASIZE_256 0x00 +#define AGP_I915_IFPADDR 0x60 /* * G965 registers */ #define AGP_I965_GTTMMADR 0x10 #define AGP_I965_MSAC 0x62 #define AGP_I965_MSAC_GMASIZE_128 0x00 #define AGP_I965_MSAC_GMASIZE_256 0x02 #define AGP_I965_MSAC_GMASIZE_512 0x06 #define AGP_I965_PGTBL_SIZE_1MB (3 << 1) #define AGP_I965_PGTBL_SIZE_2MB (4 << 1) #define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1) +#define AGP_I965_PGTBL_CTL2 0x20c4 +#define AGP_I965_IFPADDR 0x70 /* * G33 registers */ #define AGP_G33_MGGC_GGMS_MASK (3 << 8) #define AGP_G33_MGGC_GGMS_SIZE_1M (1 << 8) #define AGP_G33_MGGC_GGMS_SIZE_2M (2 << 8) #define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 #define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 /* * G4X registers */ +#define AGP_G4X_GMADR 0x20 +#define AGP_G4X_MMADR 0x10 +#define AGP_G4X_GTTADR 0x18 #define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0 #define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0 #define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0 #define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0 + +/* + * SandyBridge/IvyBridge registers + */ +#define AGP_SNB_GCC1 0x50 +#define AGP_SNB_GMCH_GMS_STOLEN_MASK 0xF8 +#define AGP_SNB_GMCH_GMS_STOLEN_32M (1 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_64M (2 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_96M (3 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_128M (4 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_160M (5 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_192M (6 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_224M (7 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_256M (8 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_288M (9 << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_320M (0xa << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_352M (0xb << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_384M (0xc << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_416M (0xd << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_448M (0xe << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_480M (0xf << 3) +#define AGP_SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) +#define AGP_SNB_GTT_SIZE_0M (0 << 8) +#define AGP_SNB_GTT_SIZE_1M (1 << 8) +#define AGP_SNB_GTT_SIZE_2M (2 << 8) +#define AGP_SNB_GTT_SIZE_MASK (3 << 8) + +#define AGP_SNB_GFX_MODE 0x02520 /* * NVIDIA nForce/nForce2 registers */ #define AGP_NVIDIA_0_APBASE 0x10 #define AGP_NVIDIA_0_APSIZE 0x80 #define AGP_NVIDIA_1_WBC 0xf0 #define AGP_NVIDIA_2_GARTCTRL 0xd0 #define AGP_NVIDIA_2_APBASE 0xd8 #define AGP_NVIDIA_2_APLIMIT 0xdc #define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) #define AGP_NVIDIA_3_APBASE 0x50 #define AGP_NVIDIA_3_APLIMIT 0x54 /* * AMD64 GART registers */ #define AGP_AMD64_APCTRL 0x90 #define AGP_AMD64_APBASE 0x94 #define AGP_AMD64_ATTBASE 0x98 #define AGP_AMD64_CACHECTRL 0x9c #define AGP_AMD64_APCTRL_GARTEN 0x00000001 #define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e #define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010 #define AGP_AMD64_APCTRL_DISGARTIO 0x00000020 #define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040 #define AGP_AMD64_APBASE_MASK 0x00007fff #define AGP_AMD64_ATTBASE_MASK 0xfffffff0 #define AGP_AMD64_CACHECTRL_INVGART 0x00000001 #define AGP_AMD64_CACHECTRL_PTEERR 0x00000002 /* * NVIDIA nForce3 registers */ #define AGP_AMD64_NVIDIA_0_APBASE 0x10 #define AGP_AMD64_NVIDIA_1_APBASE1 0x50 #define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54 #define AGP_AMD64_NVIDIA_1_APSIZE 0xa8 #define AGP_AMD64_NVIDIA_1_APBASE2 0xd8 #define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc /* * ULi M1689 registers */ #define AGP_AMD64_ULI_APBASE 0x10 #define AGP_AMD64_ULI_HTT_FEATURE 0x50 #define AGP_AMD64_ULI_ENU_SCR 0x54 /* * ATI IGP registers */ #define ATI_GART_MMADDR 0x14 #define ATI_RS100_APSIZE 0xac #define ATI_RS100_IG_AGPMODE 0xb0 #define ATI_RS300_APSIZE 0xf8 #define ATI_RS300_IG_AGPMODE 0xfc #define ATI_GART_FEATURE_ID 0x00 #define ATI_GART_BASE 0x04 #define ATI_GART_CACHE_CNTRL 0x0c #endif /* !_PCI_AGPREG_H_ */ Index: head/sys/dev/agp/agpvar.h =================================================================== --- head/sys/dev/agp/agpvar.h (revision 235781) +++ head/sys/dev/agp/agpvar.h (revision 235782) @@ -1,125 +1,131 @@ /*- * Copyright (c) 2000 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _PCI_AGPVAR_H_ #define _PCI_AGPVAR_H_ /* * The AGP chipset can be acquired by user or kernel code. If the * chipset has already been acquired, it cannot be acquired by another * user until the previous user has released it. */ enum agp_acquire_state { AGP_ACQUIRE_FREE, AGP_ACQUIRE_USER, AGP_ACQUIRE_KERNEL }; /* * This structure is used to query the state of the AGP system. */ struct agp_info { u_int32_t ai_mode; vm_offset_t ai_aperture_base; vm_size_t ai_aperture_size; vm_size_t ai_memory_allowed; vm_size_t ai_memory_used; u_int32_t ai_devid; }; struct agp_memory_info { vm_size_t ami_size; /* size in bytes */ vm_offset_t ami_physical; /* bogus hack for i810 */ vm_offset_t ami_offset; /* page offset if bound */ int ami_is_bound; /* non-zero if bound */ }; /* * Find the AGP device and return it. */ device_t agp_find_device(void); /* * Return the current owner of the AGP chipset. */ enum agp_acquire_state agp_state(device_t dev); /* * Query the state of the AGP system. */ void agp_get_info(device_t dev, struct agp_info *info); /* * Acquire the AGP chipset for use by the kernel. Returns EBUSY if the * AGP chipset is already acquired by another user. */ int agp_acquire(device_t dev); /* * Release the AGP chipset. */ int agp_release(device_t dev); /* * Enable the agp hardware with the relavent mode. The mode bits are * defined in */ int agp_enable(device_t dev, u_int32_t mode); /* * Allocate physical memory suitable for mapping into the AGP * aperture. The value returned is an opaque handle which can be * passed to agp_bind(), agp_unbind() or agp_deallocate(). */ void *agp_alloc_memory(device_t dev, int type, vm_size_t bytes); /* * Free memory which was allocated with agp_allocate(). */ void agp_free_memory(device_t dev, void *handle); /* * Bind memory allocated with agp_allocate() at a given offset within * the AGP aperture. Returns EINVAL if the memory is already bound or * the offset is not at an AGP page boundary. */ int agp_bind_memory(device_t dev, void *handle, vm_offset_t offset); /* * Unbind memory from the AGP aperture. Returns EINVAL if the memory * is not bound. */ int agp_unbind_memory(device_t dev, void *handle); /* * Retrieve information about a memory block allocated with * agp_alloc_memory(). */ void agp_memory_info(device_t dev, void *handle, struct agp_memory_info *mi); +#define AGP_NORMAL_MEMORY 0 + +#define AGP_USER_TYPES (1 << 16) +#define AGP_USER_MEMORY (AGP_USER_TYPES) +#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1) + #endif /* !_PCI_AGPVAR_H_ */ Index: head/sys/modules/agp/Makefile =================================================================== --- head/sys/modules/agp/Makefile (revision 235781) +++ head/sys/modules/agp/Makefile (revision 235782) @@ -1,36 +1,48 @@ # $FreeBSD$ .PATH: ${.CURDIR}/../../dev/agp KMOD= agp SRCS= agp.c agp_if.c .if ${MACHINE_CPUARCH} == "i386" SRCS+= agp_i810.c agp_intel.c agp_via.c agp_sis.c agp_ali.c agp_amd.c \ agp_nvidia.c agp_ati.c .endif .if ${MACHINE} == "i386" SRCS+= agp_amd64.c .endif .if ${MACHINE_CPUARCH} == "amd64" SRCS+= agp_amd64.c agp_i810.c agp_via.c .endif .if ${MACHINE_CPUARCH} == "powerpc" SRCS+= agp_apple.c .endif SRCS+= device_if.h bus_if.h agp_if.h pci_if.h SRCS+= opt_agp.h opt_bus.h MFILES= kern/device_if.m kern/bus_if.m dev/agp/agp_if.m dev/pci/pci_if.m WERROR= EXPORT_SYMS= agp_find_device \ agp_state \ agp_acquire \ agp_release \ agp_enable \ agp_alloc_memory \ agp_free_memory \ agp_bind_memory \ agp_unbind_memory \ agp_memory_info + +.if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" +EXPORT_SYMS+= intel_gtt_clear_range \ + intel_gtt_insert_pages \ + intel_gtt_get \ + intel_gtt_chipset_flush \ + intel_gtt_unmap_memory \ + intel_gtt_map_memory \ + intel_gtt_insert_sg_entries \ + intel_gtt_get_bridge_device +.endif + .include Index: head/sys/sys/agpio.h =================================================================== --- head/sys/sys/agpio.h (revision 235781) +++ head/sys/sys/agpio.h (revision 235782) @@ -1,149 +1,150 @@ /*- * Copyright (c) 2000 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SYS_AGPIO_H_ #define _SYS_AGPIO_H_ /* * The AGP gatt uses 4k pages irrespective of the host page size. */ #define AGP_PAGE_SIZE 4096 #define AGP_PAGE_SHIFT 12 /* * Macros to manipulate AGP mode words. * * SBA = Sideband Address Port * FW = Fast Writes */ #define AGP_MODE_GET_RQ(x) (((x) & 0xff000000U) >> 24) #define AGP_MODE_GET_ARQSZ(x) (((x) & 0x0000e000U) >> 13) #define AGP_MODE_GET_CAL(x) (((x) & 0x00001c00U) >> 10) #define AGP_MODE_GET_SBA(x) (((x) & 0x00000200U) >> 9) #define AGP_MODE_GET_AGP(x) (((x) & 0x00000100U) >> 8) #define AGP_MODE_GET_GART_64(x) (((x) & 0x00000080U) >> 7) #define AGP_MODE_GET_OVER_4G(x) (((x) & 0x00000020U) >> 5) #define AGP_MODE_GET_FW(x) (((x) & 0x00000010U) >> 4) #define AGP_MODE_GET_MODE_3(x) (((x) & 0x00000008U) >> 3) #define AGP_MODE_GET_RATE(x) ((x) & 0x00000007U) #define AGP_MODE_SET_RQ(x,v) (((x) & ~0xff000000U) | ((v) << 24)) #define AGP_MODE_SET_ARQSZ(x,v) (((x) & ~0x0000e000U) | ((v) << 13)) #define AGP_MODE_SET_CAL(x,v) (((x) & ~0x00001c00U) | ((v) << 10)) #define AGP_MODE_SET_SBA(x,v) (((x) & ~0x00000200U) | ((v) << 9)) #define AGP_MODE_SET_AGP(x,v) (((x) & ~0x00000100U) | ((v) << 8)) #define AGP_MODE_SET_GART_64(x,v) (((x) & ~0x00000080U) | ((v) << 7)) #define AGP_MODE_SET_OVER_4G(x,v) (((x) & ~0x00000020U) | ((v) << 5)) #define AGP_MODE_SET_FW(x,v) (((x) & ~0x00000010U) | ((v) << 4)) #define AGP_MODE_SET_MODE_3(x,v) (((x) & ~0x00000008U) | ((v) << 3)) #define AGP_MODE_SET_RATE(x,v) (((x) & ~0x00000007U) | (v)) #define AGP_MODE_V2_RATE_1x 0x00000001 #define AGP_MODE_V2_RATE_2x 0x00000002 #define AGP_MODE_V2_RATE_4x 0x00000004 #define AGP_MODE_V3_RATE_4x 0x00000001 #define AGP_MODE_V3_RATE_8x 0x00000002 #define AGP_MODE_V3_RATE_RSVD 0x00000004 /* XXX: Compat */ #define AGP_MODE_GET_4G(x) AGP_MODE_GET_OVER_4G(x) #define AGP_MODE_SET_4G(x) AGP_MODE_SET_OVER_4G(x) #define AGP_MODE_RATE_1x AGP_MODE_V2_RATE_1x #define AGP_MODE_RATE_2x AGP_MODE_V2_RATE_2x #define AGP_MODE_RATE_4x AGP_MODE_V2_RATE_4x #define AGPIOC_BASE 'A' #define AGPIOC_INFO _IOR (AGPIOC_BASE, 0, agp_info) #define AGPIOC_ACQUIRE _IO (AGPIOC_BASE, 1) #define AGPIOC_RELEASE _IO (AGPIOC_BASE, 2) #define AGPIOC_SETUP _IOW (AGPIOC_BASE, 3, agp_setup) #if 0 #define AGPIOC_RESERVE _IOW (AGPIOC_BASE, 4, agp_region) #define AGPIOC_PROTECT _IOW (AGPIOC_BASE, 5, agp_region) #endif #define AGPIOC_ALLOCATE _IOWR(AGPIOC_BASE, 6, agp_allocate) #define AGPIOC_DEALLOCATE _IOW (AGPIOC_BASE, 7, int) #define AGPIOC_BIND _IOW (AGPIOC_BASE, 8, agp_bind) #define AGPIOC_UNBIND _IOW (AGPIOC_BASE, 9, agp_unbind) +#define AGPIOC_CHIPSET_FLUSH _IO (AGPIOC_BASE, 10) typedef struct _agp_version { u_int16_t major; u_int16_t minor; } agp_version; typedef struct _agp_info { agp_version version; /* version of the driver */ u_int32_t bridge_id; /* bridge vendor/device */ u_int32_t agp_mode; /* mode info of bridge */ off_t aper_base; /* base of aperture */ size_t aper_size; /* size of aperture */ size_t pg_total; /* max pages (swap + system) */ size_t pg_system; /* max pages (system) */ size_t pg_used; /* current pages used */ } agp_info; typedef struct _agp_setup { u_int32_t agp_mode; /* mode info of bridge */ } agp_setup; #if 0 /* * The "prot" down below needs still a "sleep" flag somehow ... */ typedef struct _agp_segment { off_t pg_start; /* starting page to populate */ size_t pg_count; /* number of pages */ int prot; /* prot flags for mmap */ } agp_segment; typedef struct _agp_region { pid_t pid; /* pid of process */ size_t seg_count; /* number of segments */ struct _agp_segment *seg_list; } agp_region; #endif typedef struct _agp_allocate { int key; /* tag of allocation */ size_t pg_count; /* number of pages */ u_int32_t type; /* 0 == normal, other devspec */ u_int32_t physical; /* device specific (some devices * need a phys address of the * actual page behind the gatt * table) */ } agp_allocate; typedef struct _agp_bind { int key; /* tag of allocation */ off_t pg_start; /* starting page to populate */ } agp_bind; typedef struct _agp_unbind { int key; /* tag of allocation */ u_int32_t priority; /* priority for paging out */ } agp_unbind; #endif /* !_SYS_AGPIO_H_ */