Index: projects/armv6/sys/arm/conf/PANDABOARD =================================================================== --- projects/armv6/sys/arm/conf/PANDABOARD (nonexistent) +++ projects/armv6/sys/arm/conf/PANDABOARD (revision 230362) @@ -0,0 +1,130 @@ +# PANDABOARD -- Custom configuration for the PandaBoard ARM development +# platform, check out www.pandaboard.org +# +# For more information on this file, please read the handbook section on +# Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD$ + +ident PANDABOARD + + + +# This probably wants to move somewhere else. Maybe we can create a basic +# OMAP4340 config, then make a PANDABOARD config that includes the basic one, +# adds the start addresses and custom devices plus pulls in this hints file. + +hints "PANDABOARD.hints" + +include "../omap/omap4/pandaboard/std.pandaboard" + +#To statically compile in device wiring instead of /boot/device.hints +makeoptions MODULES_OVERRIDE="" +makeoptions WITHOUT_MODULES="ahc" + +makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols +options HZ=100 + +options SCHED_4BSD #4BSD scheduler +options INET #InterNETworking +#options INET6 #IPv6 communications protocols +options FFS #Berkeley Fast Filesystem +options SOFTUPDATES #Enable FFS soft updates support +options UFS_ACL #Support for access control lists +options UFS_DIRHASH #Improve performance on big directories +options NFSCLIENT #Network Filesystem Client +device snp +#options NFSCL +#options NFSSERVER #Network Filesystem Server +options NFS_ROOT #NFS usable as /, requires NFSCLIENT +options BREAK_TO_DEBUGGER +options BOOTP_NFSROOT +options BOOTP_COMPAT +options BOOTP +options BOOTP_NFSV3 +options BOOTP_WIRED_TO=ue0 +options MSDOSFS #MSDOS Filesystem +#options CD9660 #ISO 9660 Filesystem +#options PROCFS #Process filesystem (requires PSEUDOFS) +options PSEUDOFS #Pseudo-filesystem framework +options COMPAT_43 #Compatible with BSD 4.3 [KEEP THIS!] +options SCSI_DELAY=5000 #Delay (in ms) before probing SCSI +options KTRACE #ktrace(1) support +options SYSVSHM #SYSV-style shared memory +options SYSVMSG #SYSV-style message queues +options SYSVSEM #SYSV-style semaphores +options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions +options KBD_INSTALL_CDEV # install a CDEV entry in /dev + +options PREEMPTION + +# MMC/SD/SDIO Card slot support +device mmc # mmc/sd bus +device mmcsd # mmc/sd flash cards + +# I2C support +#device iicbus +#device iic +#device omap3_i2c + +device loop +device ether +device mii +device smc +device smcphy +device uart +device uart_ns8250 + +device gpio + +device pty + +# Debugging for use in -current +#options VERBOSE_SYSINIT #Enable verbose sysinit messages +options KDB +options DDB #Enable the kernel debugger +#options INVARIANTS #Enable calls of extra sanity checking +#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS +#options WITNESS #Enable checks to detect deadlocks and cycles +#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed +#options DIAGNOSTIC + +device md + +# The following enables MFS as root, this seems similar to an initramfs or initrd +# as used in Linux. +# options MD_ROOT +# options MD_ROOT_SIZE=7560 + +device random # Entropy device + +# USB support +device usb +options USB_DEBUG +#options USB_REQ_DEBUG +#options USB_VERBOSE +device ohci +device ehci +device umass +device scbus # SCSI bus (required for SCSI) +device da # Direct Access (disks) + + +# USB Ethernet support, requires miibus +device miibus +device axe # ASIX Electronics USB Ethernet +device smsc # SMSC LAN95xx USB Ethernet + + Index: projects/armv6/sys/arm/conf/PANDABOARD.hints =================================================================== --- projects/armv6/sys/arm/conf/PANDABOARD.hints (nonexistent) +++ projects/armv6/sys/arm/conf/PANDABOARD.hints (revision 230362) @@ -0,0 +1,61 @@ +# $FreeBSD$ + +# USB ECHI + +# +# TI OMAP Power Management and System Companion Device sitting on the I2C bus +# hint.tps65950.0.at="iicbus0" +# hint.tps65950.0.addr=0xd0 + + +# +# Defines the GPIO pin used to detect the Write Protect stat of the MMC/SD card. +#hint.omap_mmc.0.wp_gpio="23" + + +# +# If 'phy_reset" is set, then the accompaning PHY is reset using one of the +# GPIO pins. If the reset GPIO pin is not -1 then the pin will be toggled when +# the USB driver is loaded. +hint.ehci.0.phy_reset="0" + +# +# Sets the PHY mode for the individual ports, the following values are allowed +# - EHCI_HCD_OMAP3_MODE_UNKNOWN 0 +# - EHCI_HCD_OMAP3_MODE_PHY 1 +# - EHCI_HCD_OMAP3_MODE_TLL 2 +hint.ehci.0.phy_mode_0="1" +hint.ehci.0.phy_mode_1="0" +hint.ehci.0.phy_mode_2="0" + +# +# If specified the value indicates a pin that is toggled as a heart-beat. The +# heart beat pusle is triggered every 500ms using the system tick timer. +hint.omap_clk.0.heartbeat_gpio="150" + + +# +# Padconf (pinmux) settings - typically this would be set by the boot-loader +# but can be overridden here. These hints are applied to the H/W when the +# SCM module is initialised. +# +# The format is: +# hint.omap_scm.0.padconf.= +# +# Where the options can be one of the following: +# output, input, input_pullup, input_pulldown +# + +# Setup the pin settings for the HS USB Host (PHY mode) +hint.omap44xx.0.padconf.ag19="usbb1_ulpiphy_stp:output" +hint.omap44xx.0.padconf.ae18="usbb1_ulpiphy_clk:input_pulldown" +hint.omap44xx.0.padconf.af19="usbb1_ulpiphy_dir:input_pulldown" +hint.omap44xx.0.padconf.ae19="usbb1_ulpiphy_nxt:input_pulldown" +hint.omap44xx.0.padconf.af18="usbb1_ulpiphy_dat0:input_pulldown" +hint.omap44xx.0.padconf.ag18="usbb1_ulpiphy_dat1:input_pulldown" +hint.omap44xx.0.padconf.ae17="usbb1_ulpiphy_dat2:input_pulldown" +hint.omap44xx.0.padconf.af17="usbb1_ulpiphy_dat3:input_pulldown" +hint.omap44xx.0.padconf.ah17="usbb1_ulpiphy_dat4:input_pulldown" +hint.omap44xx.0.padconf.ae16="usbb1_ulpiphy_dat5:input_pulldown" +hint.omap44xx.0.padconf.af16="usbb1_ulpiphy_dat6:input_pulldown" +hint.omap44xx.0.padconf.ag16="usbb1_ulpiphy_dat7:input_pulldown" Index: projects/armv6/sys/arm/omap/omap.c =================================================================== --- projects/armv6/sys/arm/omap/omap.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap.c (revision 230362) @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2010 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Ben Gray. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +static int omap_probe(device_t); +static void omap_identify(driver_t *, device_t); +static int omap_attach(device_t); + +extern const struct pmap_devmap omap_devmap[]; + +/* Proto types for all the bus_space structure functions */ +bs_protos(generic); +bs_protos(generic_armv7); + +struct bus_space omap_bs_tag = { + /* cookie */ + .bs_cookie = (void *) 0, + + /* mapping/unmapping */ + .bs_map = generic_bs_map, + .bs_unmap = generic_bs_unmap, + .bs_subregion = generic_bs_subregion, + + /* allocation/deallocation */ + .bs_alloc = generic_bs_alloc, + .bs_free = generic_bs_free, + + /* barrier */ + .bs_barrier = generic_bs_barrier, + + /* read (single) */ + .bs_r_1 = generic_bs_r_1, + .bs_r_2 = generic_armv7_bs_r_2, + .bs_r_4 = generic_bs_r_4, + .bs_r_8 = NULL, + + /* read multiple */ + .bs_rm_1 = generic_bs_rm_1, + .bs_rm_2 = generic_armv7_bs_rm_2, + .bs_rm_4 = generic_bs_rm_4, + .bs_rm_8 = NULL, + + /* read region */ + .bs_rr_1 = generic_bs_rr_1, + .bs_rr_2 = generic_armv7_bs_rr_2, + .bs_rr_4 = generic_bs_rr_4, + .bs_rr_8 = NULL, + + /* write (single) */ + .bs_w_1 = generic_bs_w_1, + .bs_w_2 = generic_armv7_bs_w_2, + .bs_w_4 = generic_bs_w_4, + .bs_w_8 = NULL, + + /* write multiple */ + .bs_wm_1 = generic_bs_wm_1, + .bs_wm_2 = generic_armv7_bs_wm_2, + .bs_wm_4 = generic_bs_wm_4, + .bs_wm_8 = NULL, + + /* write region */ + .bs_wr_1 = generic_bs_wr_1, + .bs_wr_2 = generic_armv7_bs_wr_2, + .bs_wr_4 = generic_bs_wr_4, + .bs_wr_8 = NULL, + + /* set multiple */ + /* XXX not implemented */ + + /* set region */ + .bs_sr_1 = NULL, + .bs_sr_2 = generic_armv7_bs_sr_2, + .bs_sr_4 = generic_bs_sr_4, + .bs_sr_8 = NULL, + + /* copy */ + .bs_c_1 = NULL, + .bs_c_2 = generic_armv7_bs_c_2, + .bs_c_4 = NULL, + .bs_c_8 = NULL, +}; + +static void +omap_identify(driver_t *driver, device_t parent) +{ + BUS_ADD_CHILD(parent, 0, "omap", 0); +} + +/** + * omap_probe - driver probe function + * @dev: the root device + * + * Simply sets the name of this base driver + */ +static int +omap_probe(device_t dev) +{ + + device_set_desc(dev, "TI OMAP"); + return (0); +} + +/** + * omap_attach + */ +static int +omap_attach(device_t dev) +{ + struct omap_softc *sc = device_get_softc(dev); + const struct pmap_devmap *pdevmap; + + sc->sc_iotag = &omap_bs_tag; + sc->sc_dev = dev; + + + /* Set all interrupts as the resource */ + sc->sc_irq_rman.rm_type = RMAN_ARRAY; + sc->sc_irq_rman.rm_descr = "OMAP IRQs"; + if (rman_init(&sc->sc_irq_rman) != 0 || + rman_manage_region(&sc->sc_irq_rman, 0, NIRQ) != 0) { + panic("%s: failed to set up IRQ rman", __func__); + } + + /* Setup the memory map based on initial device map in *_machdep.c */ + sc->sc_mem_rman.rm_type = RMAN_ARRAY; + sc->sc_mem_rman.rm_descr = "OMAP Memory"; + + if (rman_init(&sc->sc_mem_rman) != 0) + panic("%s: failed to set up memory rman", __func__); + + for (pdevmap = omap_devmap; pdevmap->pd_va != 0; pdevmap++) { + if (rman_manage_region(&sc->sc_mem_rman, pdevmap->pd_pa, + pdevmap->pd_pa + pdevmap->pd_size - 1) != 0) { + panic("%s: failed to set up memory regions", __func__); + } + } + + /* The device list will be created by the 'cpu' device when it is identified */ + bus_generic_probe(dev); + bus_generic_attach(dev); + enable_interrupts(I32_bit | F32_bit); + return (0); +} + +/** + * omap_devmap_phys2virt + * + * This function will be called when bus_alloc_resource(...) if the memory + * region requested is in the range of the managed values set by + * rman_manage_region(...) above. + * + * For SYS_RES_MEMORY resource types the omap_attach() calls rman_manage_region + * with the list of pyshical mappings defined in the omap_devmap region map. + * However because we are working with physical addresses, we need to convert + * the physical to virtual within this function and return the virtual address + * in the bus tag field. + * + */ +static u_long +omap_devmap_phys2virt(u_long pa) +{ + const struct pmap_devmap *pdevmap; + + for (pdevmap = omap_devmap; pdevmap->pd_va != 0; pdevmap++) { + if ((pa >= pdevmap->pd_pa) && (pa < (pdevmap->pd_pa + pdevmap->pd_size))) { + return (pdevmap->pd_va + (pa - pdevmap->pd_pa)); + } + } + + panic("%s: failed to find addr mapping for 0x%08lx", __func__, pa); + return (0); +} + +/** + * omap_alloc_resource + * + * This function will be called when bus_alloc_resource(...) if the memory + * region requested is in the range of the managed values set by + * rman_manage_region(...) above. + * + * For SYS_RES_MEMORY resource types the omap_attach() calls rman_manage_region + * with the list of pyshical mappings defined in the omap_devmap region map. + * However because we are working with physical addresses, we need to convert + * the physical to virtual within this function and return the virtual address + * in the bus tag field. + * + */ +static struct resource * +omap_alloc_resource(device_t dev, device_t child, int type, int *rid, + u_long start, u_long end, u_long count, u_int flags) +{ + struct omap_softc *sc = device_get_softc(dev); + struct resource_list_entry *rle; + struct omap_ivar *ivar = device_get_ivars(child); + struct resource_list *rl = &ivar->resources; + + /* If we aren't the parent pass it onto the actual parent */ + if (device_get_parent(child) != dev) { + return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, + type, rid, start, end, count, flags)); + } + + /* Find the resource in the list */ + rle = resource_list_find(rl, type, *rid); + if (rle == NULL) + return (NULL); + if (rle->res) + panic("Resource rid %d type %d already in use", *rid, type); + + if (start == 0UL && end == ~0UL) { + start = rle->start; + count = ulmax(count, rle->count); + end = ulmax(rle->end, start + count - 1); + } + + switch (type) + { + case SYS_RES_IRQ: + rle->res = rman_reserve_resource(&sc->sc_irq_rman, + start, end, count, flags, child); + break; + case SYS_RES_MEMORY: + rle->res = rman_reserve_resource(&sc->sc_mem_rman, + start, end, count, flags, child); + if (rle->res != NULL) { + rman_set_bustag(rle->res, &omap_bs_tag); + rman_set_bushandle(rle->res, omap_devmap_phys2virt(start)); + } + break; + } + + if (rle->res) { + rle->start = rman_get_start(rle->res); + rle->end = rman_get_end(rle->res); + rle->count = count; + rman_set_rid(rle->res, *rid); + } + return (rle->res); +} + +/** + * omap_get_resource_list + * + */ +static struct resource_list * +omap_get_resource_list(device_t dev, device_t child) +{ + struct omap_ivar *ivar; + + ivar = device_get_ivars(child); + return (&(ivar->resources)); +} + +/** + * omap_release_resource + * + */ +static int +omap_release_resource(device_t dev, device_t child, int type, int rid, + struct resource *r) +{ + struct resource_list *rl; + struct resource_list_entry *rle; + + rl = omap_get_resource_list(dev, child); + if (rl == NULL) + return (EINVAL); + + rle = resource_list_find(rl, type, rid); + if (rle == NULL) + return (EINVAL); + + rman_release_resource(r); + rle->res = NULL; + return (0); +} + +/** + * omap_activate_resource + * + * + * + */ +static int +omap_activate_resource(device_t dev, device_t child, int type, int rid, + struct resource *r) +{ + +#if 0 + struct omap3_softc *sc = device_get_softc(dev); + const struct hwvtrans *vtrans; + uint32_t start = rman_get_start(r); + uint32_t size = rman_get_size(r); + + if (type == SYS_RES_MEMORY) { + vtrans = omap3_gethwvtrans(start, size); + if (vtrans == NULL) { /* NB: should not happen */ + device_printf(child, "%s: no mapping for 0x%lx:0x%lx\n", + __func__, start, size); + return (ENOENT); + } + rman_set_bustag(r, sc->sc_iot); + rman_set_bushandle(r, vtrans->vbase + (start - vtrans->hwbase)); + } +#endif + return (rman_activate_resource(r)); +} + + +/** + * omap_deactivate_resource + * + */ +static int +omap_deactivate_resource(device_t bus, device_t child, int type, int rid, + struct resource *r) +{ + /* NB: no private resources, just deactive */ + return (rman_deactivate_resource(r)); +} + +static device_t +omap_add_child(device_t bus, u_int order, const char *name, int unit) +{ + device_t child; + struct omap_ivar *ivar; + + ivar = malloc(sizeof(struct omap_ivar), M_DEVBUF, M_NOWAIT|M_ZERO); + if (!ivar) + return (0); + resource_list_init(&ivar->resources); + + child = device_add_child_ordered(bus, order, name, unit); + if (child == NULL) { + device_printf(bus, "failed to add child: %s%d\n", name, unit); + return (0); + } + + /* should we free this in nexus_child_detached? */ + device_set_ivars(child, ivar); + + return (child); +} + + + +/** + * omap_print_child + * + */ +static int +omap_print_child(device_t dev, device_t child) +{ + struct omap_ivar *ivars; + struct resource_list *rl; + int retval = 0; + + ivars = device_get_ivars(child); + rl = &ivars->resources; + + retval += bus_print_child_header(dev, child); + + retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); + retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); + retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); + if (device_get_flags(dev)) + retval += printf(" flags %#x", device_get_flags(dev)); + + retval += bus_print_child_footer(dev, child); + + return (retval); +} + +/** + * omap_setup_intr - initialises and unmasks the IRQ. + * + * RETURNS: + * 0 on success + */ +int +omap_setup_intr(device_t dev, device_t child, + struct resource *res, int flags, driver_filter_t *filt, + driver_intr_t *intr, void *arg, void **cookiep) +{ + unsigned int i; + + BUS_SETUP_INTR(device_get_parent(dev), child, res, flags, filt, intr, + arg, cookiep); + + /* Enable all the interrupts in the range ... will probably be only one */ + for (i = rman_get_start(res); (i < NIRQ) && (i <= rman_get_end(res)); i++) { + arm_unmask_irq(i); + } + + return (0); +} + +/** + * omap_teardown_intr + * + * RETURNS: + * 0 on success + */ +int +omap_teardown_intr(device_t dev, device_t child, struct resource *res, + void *cookie) +{ + unsigned int i; + + /* Mask (disable) all the interrupts in the range ... will probably be only one */ + for (i = rman_get_start(res); (i < NIRQ) && (i <= rman_get_end(res)); i++) { + arm_mask_irq(i); + } + + return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); +} + + + +static device_method_t omap_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, omap_probe), + DEVMETHOD(device_attach, omap_attach), + DEVMETHOD(device_identify, omap_identify), + + /* Bus interface */ + DEVMETHOD(bus_alloc_resource, omap_alloc_resource), + DEVMETHOD(bus_activate_resource, omap_activate_resource), + DEVMETHOD(bus_deactivate_resource, omap_deactivate_resource), + DEVMETHOD(bus_get_resource_list, omap_get_resource_list), + DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), + DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), + DEVMETHOD(bus_release_resource, omap_release_resource), + + DEVMETHOD(bus_setup_intr, omap_setup_intr), + DEVMETHOD(bus_teardown_intr, omap_teardown_intr), + + DEVMETHOD(bus_add_child, omap_add_child), + DEVMETHOD(bus_print_child, omap_print_child), + + {0, 0}, +}; + +static driver_t omap_driver = { + "omap", + omap_methods, + sizeof(struct omap_softc), +}; +static devclass_t omap_devclass; + +DRIVER_MODULE(omap, nexus, omap_driver, omap_devclass, 0, 0); Index: projects/armv6/sys/arm/omap/omap3/omap35xx_reg.h =================================================================== --- projects/armv6/sys/arm/omap/omap3/omap35xx_reg.h (nonexistent) +++ projects/armv6/sys/arm/omap/omap3/omap35xx_reg.h (revision 230362) @@ -0,0 +1,778 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Texas Instruments - OMAP3xxx series processors + * + * Reference: + * OMAP35x Applications Processor + * Technical Reference Manual + * (omap35xx_techref.pdf) + * + * + * Note: + * The devices are mapped into address above 0xD000_0000 as the kernel space + * memory is at 0xC000_0000 and above. The first 256MB after this is reserved + * for the size of the kernel, everything above that is reserved for SoC + * devices. + * + */ +#ifndef _OMAP35XX_REG_H_ +#define _OMAP35XX_REG_H_ + +#ifndef _LOCORE +#include /* for uint32_t */ +#endif + + + + +#define OMAP35XX_SDRAM0_START 0x80000000UL +#define OMAP35XX_SDRAM1_START 0xA0000000UL +#define OMAP35XX_SDRAM_BANKS 2 +#define OMAP35XX_SDRAM_BANK_SIZE 0x20000000UL + + +/* Physical/Virtual address for SDRAM controller */ + +#define OMAP35XX_SMS_VBASE 0x6C000000UL +#define OMAP35XX_SMS_HWBASE 0x6C000000UL +#define OMAP35XX_SMS_SIZE 0x01000000UL + +#define OMAP35XX_SDRC_VBASE 0x6D000000UL +#define OMAP35XX_SDRC_HWBASE 0x6D000000UL +#define OMAP35XX_SDRC_SIZE 0x01000000UL + + + +/* Physical/Virtual address for I/O space */ + +#define OMAP35XX_L3_VBASE 0xD0000000UL +#define OMAP35XX_L3_HWBASE 0x68000000UL +#define OMAP35XX_L3_SIZE 0x01000000UL + +#define OMAP35XX_L4_CORE_VBASE 0xE8000000UL +#define OMAP35XX_L4_CORE_HWBASE 0x48000000UL +#define OMAP35XX_L4_CORE_SIZE 0x01000000UL + +#define OMAP35XX_L4_WAKEUP_VBASE 0xE8300000UL +#define OMAP35XX_L4_WAKEUP_HWBASE 0x48300000UL +#define OMAP35XX_L4_WAKEUP_SIZE 0x00040000UL + +#define OMAP35XX_L4_PERIPH_VBASE 0xE9000000UL +#define OMAP35XX_L4_PERIPH_HWBASE 0x49000000UL +#define OMAP35XX_L4_PERIPH_SIZE 0x00100000UL + + +/* + * L4-CORE Physical/Virtual addresss offsets + */ +#define OMAP35XX_SCM_OFFSET 0x00002000UL +#define OMAP35XX_CM_OFFSET 0x00004000UL +#define OMAP35XX_SDMA_OFFSET 0x00056000UL +#define OMAP35XX_I2C3_OFFSET 0x00060000UL +#define OMAP35XX_USB_TLL_OFFSET 0x00062000UL +#define OMAP35XX_USB_UHH_OFFSET 0x00064000UL +#define OMAP35XX_USB_EHCI_OFFSET 0x00064800UL + + +#define OMAP35XX_UART1_OFFSET 0x0006A000UL +#define OMAP35XX_UART2_OFFSET 0x0006C000UL +#define OMAP35XX_I2C1_OFFSET 0x00070000UL +#define OMAP35XX_I2C2_OFFSET 0x00072000UL +#define OMAP35XX_MCBSP1_OFFSET 0x00074000UL +#define OMAP35XX_GPTIMER10_OFFSET 0x00086000UL +#define OMAP35XX_GPTIMER11_OFFSET 0x00088000UL +#define OMAP35XX_MCBSP5_OFFSET 0x00096000UL +#define OMAP35XX_MMU1_OFFSET 0x000BD400UL +#define OMAP35XX_INTCPS_OFFSET 0x00200000UL + + +/* + * L4-WAKEUP Physical/Virtual addresss offsets + */ +#define OMAP35XX_PRM_OFFSET 0x00006000UL +#define OMAP35XX_GPIO1_OFFSET 0x00010000UL +#define OMAP35XX_GPTIMER1_OFFSET 0x00018000UL + + + +/* + * L4-PERIPH Physical/Virtual addresss offsets + */ +#define OMAP35XX_UART3_OFFSET 0x00020000UL +#define OMAP35XX_MCBSP2_OFFSET 0x00022000UL +#define OMAP35XX_MCBSP3_OFFSET 0x00024000UL +#define OMAP35XX_MCBSP4_OFFSET 0x00026000UL +#define OMAP35XX_SIDETONE_MCBSP2_OFFSET 0x00028000UL +#define OMAP35XX_SIDETONE_MCBSP3_OFFSET 0x0002A000UL +#define OMAP35XX_GPTIMER2_OFFSET 0x00032000UL +#define OMAP35XX_GPTIMER3_OFFSET 0x00034000UL +#define OMAP35XX_GPTIMER4_OFFSET 0x00036000UL +#define OMAP35XX_GPTIMER5_OFFSET 0x00038000UL +#define OMAP35XX_GPTIMER6_OFFSET 0x0003A000UL +#define OMAP35XX_GPTIMER7_OFFSET 0x0003C000UL +#define OMAP35XX_GPTIMER8_OFFSET 0x0003E000UL +#define OMAP35XX_GPTIMER9_OFFSET 0x00040000UL +#define OMAP35XX_GPIO2_OFFSET 0x00050000UL +#define OMAP35XX_GPIO3_OFFSET 0x00052000UL +#define OMAP35XX_GPIO4_OFFSET 0x00054000UL +#define OMAP35XX_GPIO5_OFFSET 0x00056000UL +#define OMAP35XX_GPIO6_OFFSET 0x00058000UL + + + + + + +/* + * System Control Module + */ +#define OMAP35XX_SCM_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_SCM_OFFSET) +#define OMAP35XX_SCM_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_SCM_OFFSET) +#define OMAP35XX_SCM_SIZE 0x00001000UL + +#define OMAP35XX_SCM_REVISION 0x00000000UL +#define OMAP35XX_SCM_SYSCONFIG 0x00000010UL +#define OMAP35XX_SCM_PADCONFS_BASE 0x00000030UL +#define OMAP35XX_SCM_DEVCONF0 0x00000274UL +#define OMAP35XX_SCM_MEM_DFTRW0 0x00000278UL + + + + +/* + * + */ +#define OMAP35XX_CM_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_CM_OFFSET) +#define OMAP35XX_CM_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_CM_OFFSET) +#define OMAP35XX_CM_SIZE 0x00001500UL + +#define OMAP35XX_CM_CORE_OFFSET 0x00000A00UL +#define OMAP35XX_CM_CORE_SIZE 0x00000100UL +#define OMAP35XX_CM_FCLKEN1_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0000UL) +#define OMAP35XX_CM_FCLKEN3_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0008UL) +#define OMAP35XX_CM_ICLKEN1_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0010UL) +#define OMAP35XX_CM_ICLKEN2_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0014UL) +#define OMAP35XX_CM_ICLKEN3_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0018UL) +#define OMAP35XX_CM_IDLEST1_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0020UL) +#define OMAP35XX_CM_IDLEST2_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0024UL) +#define OMAP35XX_CM_IDLEST3_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0028UL) +#define OMAP35XX_CM_AUTOIDLE1_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0030UL) +#define OMAP35XX_CM_AUTOIDLE2_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0034UL) +#define OMAP35XX_CM_AUTOIDLE3_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0038UL) +#define OMAP35XX_CM_CLKSEL_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0040UL) +#define OMAP35XX_CM_CLKSTCTRL_CORE (OMAP35XX_CM_CORE_OFFSET + 0x0048UL) +#define OMAP35XX_CM_CLKSTST_CORE (OMAP35XX_CM_CORE_OFFSET + 0x004CUL) + +#define OMAP35XX_CM_WKUP_OFFSET 0x00000C00UL +#define OMAP35XX_CM_WKUP_SIZE 0x00000100UL +#define OMAP35XX_CM_FCLKEN_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0000UL) +#define OMAP35XX_CM_ICLKEN_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0010UL) +#define OMAP35XX_CM_IDLEST_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0020UL) +#define OMAP35XX_CM_AUTOIDLE_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0030UL) +#define OMAP35XX_CM_CLKSEL_WKUP (OMAP35XX_CM_WKUP_OFFSET + 0x0040UL) + +#define OMAP35XX_CM_PLL_OFFSET 0x00000D00UL +#define OMAP35XX_CM_PLL_SIZE 0x00000100UL +#define OMAP35XX_CM_CLKEN_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0000UL) +#define OMAP35XX_CM_CLKEN2_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0004UL) +#define OMAP35XX_CM_IDLEST_CKGEN (OMAP35XX_CM_PLL_OFFSET + 0x0020UL) +#define OMAP35XX_CM_IDLEST2_CKGEN (OMAP35XX_CM_PLL_OFFSET + 0x0024UL) +#define OMAP35XX_CM_AUTOIDLE_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0030UL) +#define OMAP35XX_CM_AUTOIDLE2_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0034UL) +#define OMAP35XX_CM_CLKSEL1_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0040UL) +#define OMAP35XX_CM_CLKSEL2_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0044UL) +#define OMAP35XX_CM_CLKSEL3_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0048UL) +#define OMAP35XX_CM_CLKSEL4_PLL (OMAP35XX_CM_PLL_OFFSET + 0x004CUL) +#define OMAP35XX_CM_CLKSEL5_PLL (OMAP35XX_CM_PLL_OFFSET + 0x0050UL) +#define OMAP35XX_CM_CLKOUT_CTRL (OMAP35XX_CM_PLL_OFFSET + 0x0070UL) + +#define OMAP35XX_CM_PER_OFFSET 0x00001000UL +#define OMAP35XX_CM_PER_SIZE 0x00000100UL +#define OMAP35XX_CM_FCLKEN_PER (OMAP35XX_CM_PER_OFFSET + 0x0000UL) +#define OMAP35XX_CM_ICLKEN_PER (OMAP35XX_CM_PER_OFFSET + 0x0010UL) +#define OMAP35XX_CM_IDLEST_PER (OMAP35XX_CM_PER_OFFSET + 0x0020UL) +#define OMAP35XX_CM_AUTOIDLE_PER (OMAP35XX_CM_PER_OFFSET + 0x0030UL) +#define OMAP35XX_CM_CLKSEL_PER (OMAP35XX_CM_PER_OFFSET + 0x0040UL) +#define OMAP35XX_CM_SLEEPDEP_PER (OMAP35XX_CM_PER_OFFSET + 0x0044UL) +#define OMAP35XX_CM_CLKSTCTRL_PER (OMAP35XX_CM_PER_OFFSET + 0x0048UL) +#define OMAP35XX_CM_CLKSTST_PER (OMAP35XX_CM_PER_OFFSET + 0x004CUL) + +#define OMAP35XX_CM_USBHOST_OFFSET 0x00001400UL +#define OMAP35XX_CM_USBHOST_SIZE 0x00000100UL +#define OMAP35XX_CM_FCLKEN_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0000UL) +#define OMAP35XX_CM_ICLKEN_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0010UL) +#define OMAP35XX_CM_IDLEST_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0020UL) +#define OMAP35XX_CM_AUTOIDLE_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0030UL) +#define OMAP35XX_CM_SLEEPDEP_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0044UL) +#define OMAP35XX_CM_CLKSTCTRL_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x0048UL) +#define OMAP35XX_CM_CLKSTST_USBHOST (OMAP35XX_CM_USBHOST_OFFSET + 0x004CUL) + + + + +/* + * + */ +#define OMAP35XX_PRM_HWBASE (OMAP35XX_L4_WAKEUP_HWBASE + OMAP35XX_PRM_OFFSET) +#define OMAP35XX_PRM_VBASE (OMAP35XX_L4_WAKEUP_VBASE + OMAP35XX_PRM_OFFSET) +#define OMAP35XX_PRM_SIZE 0x00001600UL + +#define OMAP35XX_PRM_CLKCTRL_OFFSET 0x00000D00UL +#define OMAP35XX_PRM_CLKCTRL_SIZE 0x00000100UL +#define OMAP35XX_PRM_CLKSEL (OMAP35XX_PRM_CLKCTRL_OFFSET + 0x0040UL) +#define OMAP35XX_PRM_CLKOUT_CTRL (OMAP35XX_PRM_CLKCTRL_OFFSET + 0x0070UL) + +#define OMAP35XX_PRM_GLOBAL_OFFSET 0x00001200UL +#define OMAP35XX_PRM_GLOBAL_SIZE 0x00000100UL +#define OMAP35XX_PRM_CLKSRC_CTRL (OMAP35XX_PRM_GLOBAL_OFFSET + 0x0070UL) + + + + + +/* + * Uarts + */ +#define OMAP35XX_UART1_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_UART1_OFFSET) +#define OMAP35XX_UART1_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_UART1_OFFSET) +#define OMAP35XX_UART1_SIZE 0x00001000UL + +#define OMAP35XX_UART2_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_UART2_OFFSET) +#define OMAP35XX_UART2_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_UART2_OFFSET) +#define OMAP35XX_UART2_SIZE 0x00001000UL + +#define OMAP35XX_UART3_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_UART3_OFFSET) +#define OMAP35XX_UART3_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_UART3_OFFSET) +#define OMAP35XX_UART3_SIZE 0x00001000UL + + + + +/* + * I2C Modules + */ +#define OMAP35XX_I2C1_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_I2C1_OFFSET) +#define OMAP35XX_I2C1_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_I2C1_OFFSET) +#define OMAP35XX_I2C1_SIZE 0x00000080UL + +#define OMAP35XX_I2C2_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_I2C2_OFFSET) +#define OMAP35XX_I2C2_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_I2C2_OFFSET) +#define OMAP35XX_I2C2_SIZE 0x00000080UL + +#define OMAP35XX_I2C3_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_I2C3_OFFSET) +#define OMAP35XX_I2C3_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_I2C3_OFFSET) +#define OMAP35XX_I2C3_SIZE 0x00000080UL + +#define OMAP35XX_I2C_IE 0x04 +#define OMAP35XX_I2C_STAT 0x08 +#define OMAP35XX_I2C_WE 0x0C +#define OMAP35XX_I2C_SYSS 0x10 +#define OMAP35XX_I2C_BUF 0x14 +#define OMAP35XX_I2C_CNT 0x18 +#define OMAP35XX_I2C_DATA 0x1C +#define OMAP35XX_I2C_SYSC 0x20 +#define OMAP35XX_I2C_CON 0x24 +#define OMAP35XX_I2C_OA0 0x28 +#define OMAP35XX_I2C_SA 0x2C +#define OMAP35XX_I2C_PSC 0x30 +#define OMAP35XX_I2C_SCLL 0x34 +#define OMAP35XX_I2C_SCLH 0x38 +#define OMAP35XX_I2C_SYSTEST 0x3C +#define OMAP35XX_I2C_BUFSTAT 0x40 +#define OMAP35XX_I2C_OA1 0x44 +#define OMAP35XX_I2C_OA2 0x48 +#define OMAP35XX_I2C_OA3 0x4C +#define OMAP35XX_I2C_ACTOA 0x50 +#define OMAP35XX_I2C_SBLOCK 0x54 + + + +/* + * McBSP Modules + */ +#define OMAP35XX_MCBSP1_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_MCBSP1_OFFSET) +#define OMAP35XX_MCBSP1_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_MCBSP1_OFFSET) +#define OMAP35XX_MCBSP1_SIZE 0x00001000UL + +#define OMAP35XX_MCBSP2_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_MCBSP2_OFFSET) +#define OMAP35XX_MCBSP2_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_MCBSP2_OFFSET) +#define OMAP35XX_MCBSP2_SIZE 0x00001000UL + +#define OMAP35XX_MCBSP3_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_MCBSP3_OFFSET) +#define OMAP35XX_MCBSP3_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_MCBSP3_OFFSET) +#define OMAP35XX_MCBSP3_SIZE 0x00001000UL + +#define OMAP35XX_MCBSP4_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_MCBSP4_OFFSET) +#define OMAP35XX_MCBSP4_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_MCBSP4_OFFSET) +#define OMAP35XX_MCBSP4_SIZE 0x00001000UL + +#define OMAP35XX_MCBSP5_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_MCBSP5_OFFSET) +#define OMAP35XX_MCBSP5_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_MCBSP5_OFFSET) +#define OMAP35XX_MCBSP5_SIZE 0x00001000UL + +#define OMAP35XX_MCBSP_DRR 0x0000 +#define OMAP35XX_MCBSP_DXR 0x0008 +#define OMAP35XX_MCBSP_SPCR2 0x0010 +#define OMAP35XX_MCBSP_SPCR1 0x0014 +#define OMAP35XX_MCBSP_RCR2 0x0018 +#define OMAP35XX_MCBSP_RCR1 0x001C +#define OMAP35XX_MCBSP_XCR2 0x0020 +#define OMAP35XX_MCBSP_XCR1 0x0024 +#define OMAP35XX_MCBSP_SRGR2 0x0028 +#define OMAP35XX_MCBSP_SRGR1 0x002C +#define OMAP35XX_MCBSP_MCR2 0x0030 +#define OMAP35XX_MCBSP_MCR1 0x0034 +#define OMAP35XX_MCBSP_RCERA 0x0038 +#define OMAP35XX_MCBSP_RCERB 0x003C +#define OMAP35XX_MCBSP_XCERA 0x0040 +#define OMAP35XX_MCBSP_XCERB 0x0044 +#define OMAP35XX_MCBSP_PCR 0x0048 +#define OMAP35XX_MCBSP_RCERC 0x004C +#define OMAP35XX_MCBSP_RCERD 0x0050 +#define OMAP35XX_MCBSP_XCERC 0x0054 +#define OMAP35XX_MCBSP_XCERD 0x0058 +#define OMAP35XX_MCBSP_RCERE 0x005C +#define OMAP35XX_MCBSP_RCERF 0x0060 +#define OMAP35XX_MCBSP_XCERE 0x0064 +#define OMAP35XX_MCBSP_XCERF 0x0068 +#define OMAP35XX_MCBSP_RCERG 0x006C +#define OMAP35XX_MCBSP_RCERH 0x0070 +#define OMAP35XX_MCBSP_XCERG 0x0074 +#define OMAP35XX_MCBSP_XCERH 0x0078 +#define OMAP35XX_MCBSP_RINTCLR 0x0080 +#define OMAP35XX_MCBSP_XINTCLR 0x0084 +#define OMAP35XX_MCBSP_ROVFLCLR 0x0088 +#define OMAP35XX_MCBSP_SYSCONFIG 0x008C +#define OMAP35XX_MCBSP_THRSH2 0x0090 +#define OMAP35XX_MCBSP_THRSH1 0x0094 +#define OMAP35XX_MCBSP_IRQSTATUS 0x00A0 +#define OMAP35XX_MCBSP_IRQENABLE 0x00A4 +#define OMAP35XX_MCBSP_WAKEUPEN 0x00A8 +#define OMAP35XX_MCBSP_XCCR 0x00AC +#define OMAP35XX_MCBSP_RCCR 0x00B0 +#define OMAP35XX_MCBSP_XBUFFSTAT 0x00B4 +#define OMAP35XX_MCBSP_RBUFFSTAT 0x00B8 +#define OMAP35XX_MCBSP_SSELCR 0x00BC +#define OMAP35XX_MCBSP_STATUS 0x00C0 + + + +/* + * USB TTL Module + */ +#define OMAP35XX_USBTLL_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_USBTLL_OFFSET) +#define OMAP35XX_USBTLL_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_USBTLL_OFFSET) +#define OMAP35XX_USBTLL_SIZE 0x00001000UL + +#define OMAP35XX_USBTLL_REVISION 0x0000 +#define OMAP35XX_USBTLL_SYSCONFIG 0x0010 +#define OMAP35XX_USBTLL_SYSSTATUS 0x0014 +#define OMAP35XX_USBTLL_IRQSTATUS 0x0018 +#define OMAP35XX_USBTLL_IRQENABLE 0x001C +#define OMAP35XX_USBTLL_TLL_SHARED_CONF 0x0030 +#define OMAP35XX_USBTLL_TLL_CHANNEL_CONF(i) (0x0040 + (0x04 * (i))) +#define OMAP35XX_USBTLL_ULPI_VENDOR_ID_LO(i) (0x0800 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_VENDOR_ID_HI(i) (0x0801 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_PRODUCT_ID_LO(i) (0x0802 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_PRODUCT_ID_HI(i) (0x0803 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_FUNCTION_CTRL(i) (0x0804 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_FUNCTION_CTRL_SET(i) (0x0805 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_FUNCTION_CTRL_CLR(i) (0x0806 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_INTERFACE_CTRL(i) (0x0807 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_INTERFACE_CTRL_SET(i) (0x0808 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_INTERFACE_CTRL_CLR(i) (0x0809 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_OTG_CTRL(i) (0x080A + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_OTG_CTRL_SET(i) (0x080B + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_OTG_CTRL_CLR(i) (0x080C + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_RISE(i) (0x080D + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_RISE_SET(i) (0x080E + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_RISE_CLR(i) (0x080F + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_FALL(i) (0x0810 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_FALL_SET(i) (0x0811 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_EN_FALL_CLR(i) (0x0812 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_STATUS(i) (0x0813 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_LATCH(i) (0x0814 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_DEBUG(i) (0x0815 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_SCRATCH_REGISTER(i) (0x0816 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_SCRATCH_REGISTER_SET(i) (0x0817 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_SCRATCH_REGISTER_CLR(i) (0x0818 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_EXTENDED_SET_ACCESS(i) (0x082F + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_EN(i) (0x0830 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_EN_SET(i) (0x0831 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_EN_CLR(i) (0x0832 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_STATUS(i) (0x0833 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_UTMI_VCONTROL_LATCH(i) (0x0834 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_UTMI_VSTATUS(i) (0x0835 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_UTMI_VSTATUS_SET(i) (0x0836 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_UTMI_VSTATUS_CLR(i) (0x0837 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_USB_INT_LATCH_NOCLR(i) (0x0838 + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_EN(i) (0x083B + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_EN_SET(i) (0x083C + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_EN_CLR(i) (0x083D + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_STATUS(i) (0x083E + (0x100 * (i))) +#define OMAP35XX_USBTLL_ULPI_VENDOR_INT_LATCH(i) (0x083F + (0x100 * (i))) + + +/* + * USB Host Module + */ +#define OMAP35XX_USB_TLL_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_USB_TLL_OFFSET) +#define OMAP35XX_USB_TLL_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_USB_TLL_OFFSET) +#define OMAP35XX_USB_TLL_SIZE 0x00001000UL + +#define OMAP35XX_USB_EHCI_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_USB_EHCI_OFFSET) +#define OMAP35XX_USB_EHCI_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_USB_EHCI_OFFSET) +#define OMAP35XX_USB_EHCI_SIZE 0x00000400UL + +#define OMAP35XX_USB_UHH_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_USB_UHH_OFFSET) +#define OMAP35XX_USB_UHH_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_USB_UHH_OFFSET) +#define OMAP35XX_USB_UHH_SIZE 0x00000400UL + + + + + +/* + * SDRAM Controler (SDRC) + * PA 0x6D00_0000 + */ + +#define OMAP35XX_SDRC_SYSCONFIG (OMAP35XX_SDRC_VBASE + 0x10) +#define OMAP35XX_SDRC_SYSSTATUS (OMAP35XX_SDRC_VBASE + 0x14) +#define OMAP35XX_SDRC_CS_CFG (OMAP35XX_SDRC_VBASE + 0x40) +#define OMAP35XX_SDRC_SHARING (OMAP35XX_SDRC_VBASE + 0x44) +#define OMAP35XX_SDRC_ERR_ADDR (OMAP35XX_SDRC_VBASE + 0x48) +#define OMAP35XX_SDRC_ERR_TYPE (OMAP35XX_SDRC_VBASE + 0x4C) +#define OMAP35XX_SDRC_DLLA_CTRL (OMAP35XX_SDRC_VBASE + 0x60) +#define OMAP35XX_SDRC_DLLA_STATUS (OMAP35XX_SDRC_VBASE + 0x64) +#define OMAP35XX_SDRC_POWER_REG (OMAP35XX_SDRC_VBASE + 0x70) +#define OMAP35XX_SDRC_MCFG(p) (OMAP35XX_SDRC_VBASE + 0x80 + (0x30 * (p))) +#define OMAP35XX_SDRC_MR(p) (OMAP35XX_SDRC_VBASE + 0x84 + (0x30 * (p))) +#define OMAP35XX_SDRC_EMR2(p) (OMAP35XX_SDRC_VBASE + 0x8C + (0x30 * (p))) +#define OMAP35XX_SDRC_ACTIM_CTRLA(p) (OMAP35XX_SDRC_VBASE + 0x9C + (0x28 * (p))) +#define OMAP35XX_SDRC_ACTIM_CTRLB(p) (OMAP35XX_SDRC_VBASE + 0xA0 + (0x28 * (p))) +#define OMAP35XX_SDRC_RFR_CTRL(p) (OMAP35XX_SDRC_VBASE + 0xA4 + (0x30 * (p))) +#define OMAP35XX_SDRC_MANUAL(p) (OMAP35XX_SDRC_VBASE + 0xA8 + (0x30 * (p))) + + +/* + * SDMA Offset + * PA 0x4805 6000 + */ + +#define OMAP35XX_SDMA_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_SDMA_OFFSET) +#define OMAP35XX_SDMA_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_SDMA_OFFSET) +#define OMAP35XX_SDMA_SIZE 0x00001000UL + + + +/* + * Interrupt Controller Unit. + * PA 0x4820_0000 + */ + +#define OMAP35XX_INTCPS_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_INTCPS_OFFSET) +#define OMAP35XX_INTCPS_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_INTCPS_OFFSET) +#define OMAP35XX_INTCPS_SIZE 0x00001000UL + +#define OMAP35XX_INTCPS_SYSCONFIG (OMAP35XX_INTCPS_VBASE + 0x10) +#define OMAP35XX_INTCPS_SYSSTATUS (OMAP35XX_INTCPS_VBASE + 0x14) +#define OMAP35XX_INTCPS_SIR_IRQ (OMAP35XX_INTCPS_VBASE + 0x40) +#define OMAP35XX_INTCPS_SIR_FIQ (OMAP35XX_INTCPS_VBASE + 0x44) +#define OMAP35XX_INTCPS_CONTROL (OMAP35XX_INTCPS_VBASE + 0x48) +#define OMAP35XX_INTCPS_PROTECTION (OMAP35XX_INTCPS_VBASE + 0x4C) +#define OMAP35XX_INTCPS_IDLE (OMAP35XX_INTCPS_VBASE + 0x50) +#define OMAP35XX_INTCPS_IRQ_PRIORITY (OMAP35XX_INTCPS_VBASE + 0x60) +#define OMAP35XX_INTCPS_FIQ_PRIORITY (OMAP35XX_INTCPS_VBASE + 0x64) +#define OMAP35XX_INTCPS_THRESHOLD (OMAP35XX_INTCPS_VBASE + 0x68) +#define OMAP35XX_INTCPS_ITR(n) (OMAP35XX_INTCPS_VBASE + 0x80 + (0x20 * (n))) +#define OMAP35XX_INTCPS_MIR(n) (OMAP35XX_INTCPS_VBASE + 0x84 + (0x20 * (n))) +#define OMAP35XX_INTCPS_MIR_CLEAR(n) (OMAP35XX_INTCPS_VBASE + 0x88 + (0x20 * (n))) +#define OMAP35XX_INTCPS_MIR_SET(n) (OMAP35XX_INTCPS_VBASE + 0x8C + (0x20 * (n))) +#define OMAP35XX_INTCPS_ISR_SET(n) (OMAP35XX_INTCPS_VBASE + 0x90 + (0x20 * (n))) +#define OMAP35XX_INTCPS_ISR_CLEAR(n) (OMAP35XX_INTCPS_VBASE + 0x94 + (0x20 * (n))) +#define OMAP35XX_INTCPS_PENDING_IRQ(n) (OMAP35XX_INTCPS_VBASE + 0x98 + (0x20 * (n))) +#define OMAP35XX_INTCPS_PENDING_FIQ(n) (OMAP35XX_INTCPS_VBASE + 0x9C + (0x20 * (n))) +#define OMAP35XX_INTCPS_ILR(m) (OMAP35XX_INTCPS_VBASE + 0x100 + (0x4 * (m))) + + +#define OMAP35XX_IRQ_EMUINT 0 /* MPU emulation(2) */ +#define OMAP35XX_IRQ_COMMTX 1 /* MPU emulation(2) */ +#define OMAP35XX_IRQ_COMMRX 2 /* MPU emulation(2) */ +#define OMAP35XX_IRQ_BENCH 3 /* MPU emulation(2) */ +#define OMAP35XX_IRQ_MCBSP2_ST 4 /* Sidetone MCBSP2 overflow */ +#define OMAP35XX_IRQ_MCBSP3_ST 5 /* Sidetone MCBSP3 overflow */ +#define OMAP35XX_IRQ_SSM_ABORT 6 /* MPU subsystem secure state-machine abort (2) */ +#define OMAP35XX_IRQ_SYS_NIRQ 7 /* External source (active low) */ +#define OMAP35XX_IRQ_RESERVED8 8 /* RESERVED */ +#define OMAP35XX_IRQ_SMX_DBG 9 /* SMX error for debug */ +#define OMAP35XX_IRQ_SMX_APP 10 /* SMX error for application */ +#define OMAP35XX_IRQ_PRCM_MPU 11 /* PRCM module IRQ */ +#define OMAP35XX_IRQ_SDMA0 12 /* System DMA request 0(3) */ +#define OMAP35XX_IRQ_SDMA1 13 /* System DMA request 1(3) */ +#define OMAP35XX_IRQ_SDMA2 14 /* System DMA request 2 */ +#define OMAP35XX_IRQ_SDMA3 15 /* System DMA request 3 */ +#define OMAP35XX_IRQ_MCBSP1 16 /* McBSP module 1 IRQ (3) */ +#define OMAP35XX_IRQ_MCBSP2 17 /* McBSP module 2 IRQ (3) */ +#define OMAP35XX_IRQ_SR1 18 /* SmartReflex™ 1 */ +#define OMAP35XX_IRQ_SR2 19 /* SmartReflex™ 2 */ +#define OMAP35XX_IRQ_GPMC 20 /* General-purpose memory controller module */ +#define OMAP35XX_IRQ_SGX 21 /* 2D/3D graphics module */ +#define OMAP35XX_IRQ_MCBSP3 22 /* McBSP module 3(3) */ +#define OMAP35XX_IRQ_MCBSP4 23 /* McBSP module 4(3) */ +#define OMAP35XX_IRQ_CAM0 24 /* Camera interface request 0 */ +#define OMAP35XX_IRQ_DSS 25 /* Display subsystem module(3) */ +#define OMAP35XX_IRQ_MAIL_U0 26 /* Mailbox user 0 request */ +#define OMAP35XX_IRQ_MCBSP5_IRQ1 27 /* McBSP module 5 (3) */ +#define OMAP35XX_IRQ_IVA2_MMU 28 /* IVA2 MMU */ +#define OMAP35XX_IRQ_GPIO1_MPU 29 /* GPIO module 1(3) */ +#define OMAP35XX_IRQ_GPIO2_MPU 30 /* GPIO module 2(3) */ +#define OMAP35XX_IRQ_GPIO3_MPU 31 /* GPIO module 3(3) */ +#define OMAP35XX_IRQ_GPIO4_MPU 32 /* GPIO module 4(3) */ +#define OMAP35XX_IRQ_GPIO5_MPU 33 /* GPIO module 5(3) */ +#define OMAP35XX_IRQ_GPIO6_MPU 34 /* GPIO module 6(3) */ +#define OMAP35XX_IRQ_USIM 35 /* USIM interrupt (HS devices only) (4) */ +#define OMAP35XX_IRQ_WDT3 36 /* Watchdog timer module 3 overflow */ +#define OMAP35XX_IRQ_GPT1 37 /* General-purpose timer module 1 */ +#define OMAP35XX_IRQ_GPT2 38 /* General-purpose timer module 2 */ +#define OMAP35XX_IRQ_GPT3 39 /* General-purpose timer module 3 */ +#define OMAP35XX_IRQ_GPT4 40 /* General-purpose timer module 4 */ +#define OMAP35XX_IRQ_GPT5 41 /* General-purpose timer module 5(3) */ +#define OMAP35XX_IRQ_GPT6 42 /* General-purpose timer module 6(3) */ +#define OMAP35XX_IRQ_GPT7 43 /* General-purpose timer module 7(3) */ +#define OMAP35XX_IRQ_GPT8 44 /* General-purpose timer module 8(3) */ +#define OMAP35XX_IRQ_GPT9 45 /* General-purpose timer module 9 */ +#define OMAP35XX_IRQ_GPT10 46 /* General-purpose timer module 10 */ +#define OMAP35XX_IRQ_GPT11 47 /* General-purpose timer module 11 */ +#define OMAP35XX_IRQ_SPI4 48 /* McSPI module 4 */ +#define OMAP35XX_IRQ_SHA1MD5_2 49 /* SHA-1/MD5 crypto-accelerator 2 (HS devices only)(4) */ +#define OMAP35XX_IRQ_FPKA_IRQREADY_N 50 /* PKA crypto-accelerator (HS devices only) (4) */ +#define OMAP35XX_IRQ_SHA2MD5 51 /* SHA-2/MD5 crypto-accelerator 1 (HS devices only) (4) */ +#define OMAP35XX_IRQ_RNG 52 /* RNG module (HS devices only) (4) */ +#define OMAP35XX_IRQ_MG 53 /* MG function (3) */ +#define OMAP35XX_IRQ_MCBSP4_TX 54 /* McBSP module 4 transmit(3) */ +#define OMAP35XX_IRQ_MCBSP4_RX 55 /* McBSP module 4 receive(3) */ +#define OMAP35XX_IRQ_I2C1 56 /* I2C module 1 */ +#define OMAP35XX_IRQ_I2C2 57 /* I2C module 2 */ +#define OMAP35XX_IRQ_HDQ 58 /* HDQ / One-wire */ +#define OMAP35XX_IRQ_MCBSP1_TX 59 /* McBSP module 1 transmit(3) */ +#define OMAP35XX_IRQ_MCBSP1_RX 60 /* McBSP module 1 receive(3) */ +#define OMAP35XX_IRQ_I2C3 61 /* I2C module 3 */ +#define OMAP35XX_IRQ_McBSP2_TX 62 /* McBSP module 2 transmit(3) */ +#define OMAP35XX_IRQ_McBSP2_RX 63 /* McBSP module 2 receive(3) */ +#define OMAP35XX_IRQ_FPKA_IRQRERROR_N 64 /* PKA crypto-accelerator (HS devices only) (4) */ +#define OMAP35XX_IRQ_SPI1 65 /* McSPI module 1 */ +#define OMAP35XX_IRQ_SPI2 66 /* McSPI module 2 */ +#define OMAP35XX_IRQ_RESERVED67 67 /* RESERVED */ +#define OMAP35XX_IRQ_RESERVED68 68 /* RESERVED */ +#define OMAP35XX_IRQ_RESERVED69 69 /* RESERVED */ +#define OMAP35XX_IRQ_RESERVED70 70 /* RESERVED */ +#define OMAP35XX_IRQ_RESERVED71 71 /* RESERVED */ +#define OMAP35XX_IRQ_UART1 72 /* UART module 1 */ +#define OMAP35XX_IRQ_UART2 73 /* UART module 2 */ +#define OMAP35XX_IRQ_UART3 74 /* UART module 3 (also infrared)(3) */ +#define OMAP35XX_IRQ_PBIAS 75 /* Merged interrupt for PBIASlite1 and 2 */ +#define OMAP35XX_IRQ_OHCI 76 /* OHCI controller HSUSB MP Host Interrupt */ +#define OMAP35XX_IRQ_EHCI 77 /* EHCI controller HSUSB MP Host Interrupt */ +#define OMAP35XX_IRQ_TLL 78 /* HSUSB MP TLL Interrupt */ +#define OMAP35XX_IRQ_PARTHASH 79 /* SHA2/MD5 crypto-accelerator 1 (HS devices only) (4) */ +#define OMAP35XX_IRQ_RESERVED80 80 /* Reserved */ +#define OMAP35XX_IRQ_MCBSP5_TX 81 /* McBSP module 5 transmit(3) */ +#define OMAP35XX_IRQ_MCBSP5_RX 82 /* McBSP module 5 receive(3) */ +#define OMAP35XX_IRQ_MMC1 83 /* MMC/SD module 1 */ +#define OMAP35XX_IRQ_MS 84 /* MS-PRO™ module */ +#define OMAP35XX_IRQ_RESERVED85 85 /* Reserved */ +#define OMAP35XX_IRQ_MMC2 86 /* MMC/SD module 2 */ +#define OMAP35XX_IRQ_MPU_ICR 87 /* MPU ICR */ +#define OMAP35XX_IRQ_RESERVED 88 /* RESERVED */ +#define OMAP35XX_IRQ_MCBSP3_TX 89 /* McBSP module 3 transmit(3) */ +#define OMAP35XX_IRQ_MCBSP3_RX 90 /* McBSP module 3 receive(3) */ +#define OMAP35XX_IRQ_SPI3 91 /* McSPI module 3 */ +#define OMAP35XX_IRQ_HSUSB_MC_NINT 92 /* High-Speed USB OTG controller */ +#define OMAP35XX_IRQ_HSUSB_DMA_NINT 93 /* High-Speed USB OTG DMA controller */ +#define OMAP35XX_IRQ_MMC3 94 /* MMC/SD module 3 */ +#define OMAP35XX_IRQ_GPT12 95 /* General-purpose timer module 12 */ + + + + +/* + * General Purpose Timers + */ +#define OMAP35XX_GPTIMER1_VBASE (OMAP35XX_L4_WAKEUP_VBASE + OMAP35XX_GPTIMER1_OFFSET) +#define OMAP35XX_GPTIMER1_HWBASE (OMAP35XX_L4_WAKEUP_HWBASE + OMAP35XX_GPTIMER1_OFFSET) +#define OMAP35XX_GPTIMER2_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER2_OFFSET) +#define OMAP35XX_GPTIMER2_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER2_OFFSET) +#define OMAP35XX_GPTIMER3_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER3_OFFSET) +#define OMAP35XX_GPTIMER3_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER3_OFFSET) +#define OMAP35XX_GPTIMER4_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER4_OFFSET) +#define OMAP35XX_GPTIMER4_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER4_OFFSET) +#define OMAP35XX_GPTIMER5_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER5_OFFSET) +#define OMAP35XX_GPTIMER5_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER5_OFFSET) +#define OMAP35XX_GPTIMER6_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER6_OFFSET) +#define OMAP35XX_GPTIMER6_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER6_OFFSET) +#define OMAP35XX_GPTIMER7_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER7_OFFSET) +#define OMAP35XX_GPTIMER7_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER7_OFFSET) +#define OMAP35XX_GPTIMER8_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER8_OFFSET) +#define OMAP35XX_GPTIMER8_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER8_OFFSET) +#define OMAP35XX_GPTIMER9_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPTIMER9_OFFSET) +#define OMAP35XX_GPTIMER9_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPTIMER9_OFFSET) +#define OMAP35XX_GPTIMER10_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_GPTIMER10_OFFSET) +#define OMAP35XX_GPTIMER10_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_GPTIMER10_OFFSET) +#define OMAP35XX_GPTIMER11_VBASE (OMAP35XX_L4_CORE_VBASE + OMAP35XX_GPTIMER11_OFFSET) +#define OMAP35XX_GPTIMER11_HWBASE (OMAP35XX_L4_CORE_HWBASE + OMAP35XX_GPTIMER11_OFFSET) +#define OMAP35XX_GPTIMER12_VBASE 0x48304000UL /* GPTIMER12 */ +#define OMAP35XX_GPTIMER_SIZE 0x00001000UL + + + +/* Timer register offsets */ +#define OMAP35XX_GPTIMER_TIOCP_CFG 0x010 +#define OMAP35XX_GPTIMER_TISTAT 0x014 +#define OMAP35XX_GPTIMER_TISR 0x018 +#define OMAP35XX_GPTIMER_TIER 0x01C +#define OMAP35XX_GPTIMER_TWER 0x020 +#define OMAP35XX_GPTIMER_TCLR 0x024 +#define OMAP35XX_GPTIMER_TCRR 0x028 +#define OMAP35XX_GPTIMER_TLDR 0x02C +#define OMAP35XX_GPTIMER_TTGR 0x030 +#define OMAP35XX_GPTIMER_TWPS 0x034 +#define OMAP35XX_GPTIMER_TMAR 0x038 +#define OMAP35XX_GPTIMER_TCAR1 0x03C +#define OMAP35XX_GPTIMER_TSICR 0x040 +#define OMAP35XX_GPTIMER_TCAR2 0x044 +#define OMAP35XX_GPTIMER_TPIR 0x048 +#define OMAP35XX_GPTIMER_TNIR 0x04C +#define OMAP35XX_GPTIMER_TCVR 0x050 +#define OMAP35XX_GPTIMER_TOCR 0x054 +#define OMAP35XX_GPTIMER_TOWR 0x058 + +/* Bit values */ +#define MAT_IT_FLAG 0x01 +#define OVF_IT_FLAG 0x02 +#define TCAR_IT_FLAG 0x04 + + + +/* + * GPIO - General Purpose IO + */ + +/* Base addresses for the GPIO modules */ +#define OMAP35XX_GPIO1_HWBASE (OMAP35XX_L4_WAKEUP_HWBASE + OMAP35XX_GPIO1_OFFSET) +#define OMAP35XX_GPIO1_VBASE (OMAP35XX_L4_WAKEUP_VBASE + OMAP35XX_GPIO1_OFFSET) +#define OMAP35XX_GPIO1_SIZE 0x00001000UL +#define OMAP35XX_GPIO2_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO2_OFFSET) +#define OMAP35XX_GPIO2_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO2_OFFSET) +#define OMAP35XX_GPIO2_SIZE 0x00001000UL +#define OMAP35XX_GPIO3_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO3_OFFSET) +#define OMAP35XX_GPIO3_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO3_OFFSET) +#define OMAP35XX_GPIO3_SIZE 0x00001000UL +#define OMAP35XX_GPIO4_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO4_OFFSET) +#define OMAP35XX_GPIO4_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO4_OFFSET) +#define OMAP35XX_GPIO4_SIZE 0x00001000UL +#define OMAP35XX_GPIO5_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO5_OFFSET) +#define OMAP35XX_GPIO5_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO5_OFFSET) +#define OMAP35XX_GPIO5_SIZE 0x00001000UL +#define OMAP35XX_GPIO6_HWBASE (OMAP35XX_L4_PERIPH_HWBASE + OMAP35XX_GPIO6_OFFSET) +#define OMAP35XX_GPIO6_VBASE (OMAP35XX_L4_PERIPH_VBASE + OMAP35XX_GPIO6_OFFSET) +#define OMAP35XX_GPIO6_SIZE 0x00001000UL + + + +/* Register offsets within the banks above */ +#define OMAP35XX_GPIO_SYSCONFIG 0x010 +#define OMAP35XX_GPIO_SYSSTATUS 0x014 +#define OMAP35XX_GPIO_IRQSTATUS1 0x018 +#define OMAP35XX_GPIO_IRQENABLE1 0x01C +#define OMAP35XX_GPIO_WAKEUPENABLE 0x020 +#define OMAP35XX_GPIO_IRQSTATUS2 0x028 +#define OMAP35XX_GPIO_IRQENABLE2 0x02C +#define OMAP35XX_GPIO_CTRL 0x030 +#define OMAP35XX_GPIO_OE 0x034 +#define OMAP35XX_GPIO_DATAIN 0x038 +#define OMAP35XX_GPIO_DATAOUT 0x03C +#define OMAP35XX_GPIO_LEVELDETECT0 0x040 +#define OMAP35XX_GPIO_LEVELDETECT1 0x044 +#define OMAP35XX_GPIO_RISINGDETECT 0x048 +#define OMAP35XX_GPIO_FALLINGDETECT 0x04C +#define OMAP35XX_GPIO_DEBOUNCENABLE 0x050 +#define OMAP35XX_GPIO_DEBOUNCINGTIME 0x054 +#define OMAP35XX_GPIO_CLEARIRQENABLE1 0x060 +#define OMAP35XX_GPIO_SETIRQENABLE1 0x064 +#define OMAP35XX_GPIO_CLEARIRQENABLE2 0x070 +#define OMAP35XX_GPIO_SETIRQENABLE2 0x074 +#define OMAP35XX_GPIO_CLEARWKUENA 0x080 +#define OMAP35XX_GPIO_SETWKUENA 0x084 +#define OMAP35XX_GPIO_CLEARDATAOUT 0x090 +#define OMAP35XX_GPIO_SETDATAOUT 0x094 + + +/* + * MMC/SD/SDIO + */ + +/* Base addresses for the MMC/SD/SDIO modules */ +#define OMAP35XX_MMCHS1_HWBASE (OMAP35XX_L4_CORE_HWBASE + 0x0009C000) +#define OMAP35XX_MMCHS1_VBASE (OMAP35XX_L4_CORE_VBASE + 0x0009C000) +#define OMAP35XX_MMCHS2_HWBASE (OMAP35XX_L4_CORE_HWBASE + 0x000B4000) +#define OMAP35XX_MMCHS2_VBASE (OMAP35XX_L4_CORE_VBASE + 0x000B4000) +#define OMAP35XX_MMCHS3_HWBASE (OMAP35XX_L4_CORE_HWBASE + 0x000AD000) +#define OMAP35XX_MMCHS3_VBASE (OMAP35XX_L4_CORE_VBASE + 0x000AD000) +#define OMAP35XX_MMCHS_SIZE 0x00000200UL + +/* Register offsets within each of the MMC/SD/SDIO controllers */ +#define OMAP35XX_MMCHS_SYSCONFIG 0x010 +#define OMAP35XX_MMCHS_SYSSTATUS 0x014 +#define OMAP35XX_MMCHS_CSRE 0x024 +#define OMAP35XX_MMCHS_SYSTEST 0x028 +#define OMAP35XX_MMCHS_CON 0x02C +#define OMAP35XX_MMCHS_PWCNT 0x030 +#define OMAP35XX_MMCHS_BLK 0x104 +#define OMAP35XX_MMCHS_ARG 0x108 +#define OMAP35XX_MMCHS_CMD 0x10C +#define OMAP35XX_MMCHS_RSP10 0x110 +#define OMAP35XX_MMCHS_RSP32 0x114 +#define OMAP35XX_MMCHS_RSP54 0x118 +#define OMAP35XX_MMCHS_RSP76 0x11C +#define OMAP35XX_MMCHS_DATA 0x120 +#define OMAP35XX_MMCHS_PSTATE 0x124 +#define OMAP35XX_MMCHS_HCTL 0x128 +#define OMAP35XX_MMCHS_SYSCTL 0x12C +#define OMAP35XX_MMCHS_STAT 0x130 +#define OMAP35XX_MMCHS_IE 0x134 +#define OMAP35XX_MMCHS_ISE 0x138 +#define OMAP35XX_MMCHS_AC12 0x13C +#define OMAP35XX_MMCHS_CAPA 0x140 +#define OMAP35XX_MMCHS_CUR_CAPA 0x148 +#define OMAP35XX_MMCHS_REV 0x1FC + + + +#endif /* _OMAP35XX_REG_H_ */ Index: projects/armv6/sys/arm/omap/omap4/files.omap44xx =================================================================== --- projects/armv6/sys/arm/omap/omap4/files.omap44xx (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/files.omap44xx (revision 230362) @@ -0,0 +1,31 @@ +#$FreeBSD$ + +kern/kern_clocksource.c standard + +arm/arm/bus_space_generic.c standard +arm/arm/bus_space_asm_generic.S standard +arm/arm/cpufunc_asm_armv5.S standard +arm/arm/cpufunc_asm_arm10.S standard +arm/arm/cpufunc_asm_arm11.S standard +arm/arm/cpufunc_asm_armv7.S standard +arm/arm/cpufunc_asm_pj4b.S standard +arm/arm/irq_dispatch.S standard + +arm/omap/omap_machdep.c standard +arm/omap/omap.c standard +arm/omap/omap_cpuid.c standard +arm/omap/omap_prcm.c standard +arm/omap/omap_scm.c standard +arm/omap/omap_if.m standard +arm/omap/omap_space_asm.S standard + +arm/omap/omap4/omap4_if.m standard +arm/omap/omap4/omap44xx.c standard +arm/omap/omap4/omap4_intr.c standard +arm/omap/omap4/omap4_prcm_clks.c standard +arm/omap/omap4/omap4_scm_padconf.c standard +arm/omap/omap4/omap4_timer.c standard + +arm/omap/omap4/uart_cpu_omap4.c optional uart + +dev/uart/uart_dev_ns8250.c optional uart Index: projects/armv6/sys/arm/omap/omap4/omap44xx.c =================================================================== --- projects/armv6/sys/arm/omap/omap4/omap44xx.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/omap44xx.c (revision 230362) @@ -0,0 +1,438 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include + +#define _ARM32_BUS_DMA_PRIVATE +#include + +#include +#include +#include +#include + +#include "omap_if.h" +#include "omap4_if.h" + +/* + * Standard priority levels for the system - 0 has the highest priority and 63 + * is the lowest. + * + * Currently these are all set to the same standard value. + */ +static const struct omap4_intr_conf omap44xx_irq_prio[] = +{ + { OMAP44XX_IRQ_L2CACHE, 0, 0x1}, /* L2 cache controller interrupt */ + { OMAP44XX_IRQ_CTI_0, 0, 0x1}, /* Cross-trigger module 0 (CTI0) interrupt */ + { OMAP44XX_IRQ_CTI_1, 0, 0x1}, /* Cross-trigger module 1 (CTI1) interrupt */ + { OMAP44XX_IRQ_ELM, 0, 0x1}, /* Error location process completion */ + { OMAP44XX_IRQ_SYS_NIRQ, 0, 0x1}, /* External source (active low) */ + { OMAP44XX_IRQ_L3_DBG, 0, 0x1}, /* L3 interconnect debug error */ + { OMAP44XX_IRQ_L3_APP, 0, 0x1}, /* L3 interconnect application error */ + { OMAP44XX_IRQ_PRCM_MPU, 0, 0x1}, /* PRCM module IRQ */ + { OMAP44XX_IRQ_SDMA0, 0, 0x1}, /* System DMA request 0(3) */ + { OMAP44XX_IRQ_SDMA1, 0, 0x1}, /* System DMA request 1(3) */ + { OMAP44XX_IRQ_SDMA2, 0, 0x1}, /* System DMA request 2 */ + { OMAP44XX_IRQ_SDMA3, 0, 0x1}, /* System DMA request 3 */ + { OMAP44XX_IRQ_MCBSP4, 0, 0x1}, /* McBSP module 4 IRQ */ + { OMAP44XX_IRQ_MCBSP1, 0, 0x1}, /* McBSP module 1 IRQ */ + { OMAP44XX_IRQ_SR1, 0, 0x1}, /* SmartReflex™ 1 */ + { OMAP44XX_IRQ_SR2, 0, 0x1}, /* SmartReflex™ 2 */ + { OMAP44XX_IRQ_GPMC, 0, 0x1}, /* General-purpose memory controller module */ + { OMAP44XX_IRQ_SGX, 0, 0x1}, /* 2D/3D graphics module */ + { OMAP44XX_IRQ_MCBSP2, 0, 0x1}, /* McBSP module 2 */ + { OMAP44XX_IRQ_MCBSP3, 0, 0x1}, /* McBSP module 3 */ + { OMAP44XX_IRQ_ISS5, 0, 0x1}, /* Imaging subsystem interrupt 5 */ + { OMAP44XX_IRQ_DSS, 0, 0x1}, /* Display subsystem module(3) */ + { OMAP44XX_IRQ_MAIL_U0, 0, 0x1}, /* Mailbox user 0 request */ + { OMAP44XX_IRQ_C2C_SSCM, 0, 0x1}, /* C2C status interrupt */ + { OMAP44XX_IRQ_DSP_MMU, 0, 0x1}, /* DSP MMU */ + { OMAP44XX_IRQ_GPIO1_MPU, 0, 0x1}, /* GPIO module 1(3) */ + { OMAP44XX_IRQ_GPIO2_MPU, 0, 0x1}, /* GPIO module 2(3) */ + { OMAP44XX_IRQ_GPIO3_MPU, 0, 0x1}, /* GPIO module 3(3) */ + { OMAP44XX_IRQ_GPIO4_MPU, 0, 0x1}, /* GPIO module 4(3) */ + { OMAP44XX_IRQ_GPIO5_MPU, 0, 0x1}, /* GPIO module 5(3) */ + { OMAP44XX_IRQ_GPIO6_MPU, 0, 0x1}, /* GPIO module 6(3) */ + { OMAP44XX_IRQ_WDT3, 0, 0x1}, /* Watchdog timer module 3 overflow */ + { OMAP44XX_IRQ_GPT1, 0, 0x1}, /* General-purpose timer module 1 */ + { OMAP44XX_IRQ_GPT2, 0, 0x1}, /* General-purpose timer module 2 */ + { OMAP44XX_IRQ_GPT3, 0, 0x1}, /* General-purpose timer module 3 */ + { OMAP44XX_IRQ_GPT4, 0, 0x1}, /* General-purpose timer module 4 */ + { OMAP44XX_IRQ_GPT5, 0, 0x1}, /* General-purpose timer module 5(3) */ + { OMAP44XX_IRQ_GPT6, 0, 0x1}, /* General-purpose timer module 6(3) */ + { OMAP44XX_IRQ_GPT7, 0, 0x1}, /* General-purpose timer module 7(3) */ + { OMAP44XX_IRQ_GPT8, 0, 0x1}, /* General-purpose timer module 8(3) */ + { OMAP44XX_IRQ_GPT9, 0, 0x1}, /* General-purpose timer module 9 */ + { OMAP44XX_IRQ_GPT10, 0, 0x1}, /* General-purpose timer module 10 */ + { OMAP44XX_IRQ_GPT11, 0, 0x1}, /* General-purpose timer module 11 */ + { OMAP44XX_IRQ_MCSPI4, 0, 0x1}, /* McSPI module 4 */ + { OMAP44XX_IRQ_DSS_DSI1, 0, 0x1}, /* Display Subsystem DSI1 interrupt */ + { OMAP44XX_IRQ_I2C1, 0, 0x1}, /* I2C module 1 */ + { OMAP44XX_IRQ_I2C2, 0, 0x1}, /* I2C module 2 */ + { OMAP44XX_IRQ_HDQ, 0, 0x1}, /* HDQ / One-wire */ + { OMAP44XX_IRQ_MMC5, 0, 0x1}, /* MMC5 interrupt */ + { OMAP44XX_IRQ_I2C3, 0, 0x1}, /* I2C module 3 */ + { OMAP44XX_IRQ_I2C4, 0, 0x1}, /* I2C module 4 */ + { OMAP44XX_IRQ_MCSPI1, 0, 0x1}, /* McSPI module 1 */ + { OMAP44XX_IRQ_MCSPI2, 0, 0x1}, /* McSPI module 2 */ + { OMAP44XX_IRQ_HSI_P1, 0, 0x1}, /* HSI Port 1 interrupt */ + { OMAP44XX_IRQ_HSI_P2, 0, 0x1}, /* HSI Port 2 interrupt */ + { OMAP44XX_IRQ_FDIF_3, 0, 0x1}, /* Face detect interrupt 3 */ + { OMAP44XX_IRQ_UART4, 0, 0x1}, /* UART module 4 interrupt */ + { OMAP44XX_IRQ_HSI_DMA, 0, 0x1}, /* HSI DMA engine MPU request */ + { OMAP44XX_IRQ_UART1, 0, 0x1}, /* UART module 1 */ + { OMAP44XX_IRQ_UART2, 0, 0x1}, /* UART module 2 */ + { OMAP44XX_IRQ_UART3, 0, 0x1}, /* UART module 3 (also infrared)(3) */ + { OMAP44XX_IRQ_PBIAS, 0, 0x1}, /* Merged interrupt for PBIASlite1 and 2 */ + { OMAP44XX_IRQ_OHCI, 0, 0x1}, /* OHCI controller HSUSB MP Host Interrupt */ + { OMAP44XX_IRQ_EHCI, 0, 0x1}, /* EHCI controller HSUSB MP Host Interrupt */ + { OMAP44XX_IRQ_TLL, 0, 0x1}, /* HSUSB MP TLL Interrupt */ + { OMAP44XX_IRQ_WDT2, 0, 0x1}, /* WDTIMER2 interrupt */ + { OMAP44XX_IRQ_MMC1, 0, 0x1}, /* MMC/SD module 1 */ + { OMAP44XX_IRQ_DSS_DSI2, 0, 0x1}, /* Display subsystem DSI2 interrupt */ + { OMAP44XX_IRQ_MMC2, 0, 0x1}, /* MMC/SD module 2 */ + { OMAP44XX_IRQ_MPU_ICR, 0, 0x1}, /* MPU ICR */ + { OMAP44XX_IRQ_C2C_GPI, 0, 0x1}, /* C2C GPI interrupt */ + { OMAP44XX_IRQ_FSUSB, 0, 0x1}, /* FS-USB - host controller Interrupt */ + { OMAP44XX_IRQ_FSUSB_SMI, 0, 0x1}, /* FS-USB - host controller SMI Interrupt */ + { OMAP44XX_IRQ_MCSPI3, 0, 0x1}, /* McSPI module 3 */ + { OMAP44XX_IRQ_HSUSB_OTG, 0, 0x1}, /* High-Speed USB OTG controller */ + { OMAP44XX_IRQ_HSUSB_OTG_DMA, 0, 0x1}, /* High-Speed USB OTG DMA controller */ + { OMAP44XX_IRQ_MMC3, 0, 0x1}, /* MMC/SD module 3 */ + { OMAP44XX_IRQ_MMC4, 0, 0x1}, /* MMC4 interrupt */ + { OMAP44XX_IRQ_SLIMBUS1, 0, 0x1}, /* SLIMBUS1 interrupt */ + { OMAP44XX_IRQ_SLIMBUS2, 0, 0x1}, /* SLIMBUS2 interrupt */ + { OMAP44XX_IRQ_ABE, 0, 0x1}, /* Audio back-end interrupt */ + { OMAP44XX_IRQ_CORTEXM3_MMU, 0, 0x1}, /* Cortex-M3 MMU interrupt */ + { OMAP44XX_IRQ_DSS_HDMI, 0, 0x1}, /* Display subsystem HDMI interrupt */ + { OMAP44XX_IRQ_SR_IVA, 0, 0x1}, /* SmartReflex IVA interrupt */ + { OMAP44XX_IRQ_IVAHD1, 0, 0x1}, /* Sync interrupt from iCONT2 (vDMA) */ + { OMAP44XX_IRQ_IVAHD2, 0, 0x1}, /* Sync interrupt from iCONT1 */ + { OMAP44XX_IRQ_IVAHD_MAILBOX0, 0, 0x1}, /* IVAHD mailbox interrupt */ + { OMAP44XX_IRQ_MCASP1, 0, 0x1}, /* McASP1 transmit interrupt */ + { OMAP44XX_IRQ_EMIF1, 0, 0x1}, /* EMIF1 interrupt */ + { OMAP44XX_IRQ_EMIF2, 0, 0x1}, /* EMIF2 interrupt */ + { OMAP44XX_IRQ_MCPDM, 0, 0x1}, /* MCPDM interrupt */ + { OMAP44XX_IRQ_DMM, 0, 0x1}, /* DMM interrupt */ + { OMAP44XX_IRQ_DMIC, 0, 0x1}, /* DMIC interrupt */ + { OMAP44XX_IRQ_SYS_NIRQ2, 0, 0x1}, /* External source 2 (active low) */ + { OMAP44XX_IRQ_KBD, 0, 0x1}, /* Keyboard controller interrupt */ + { -1, 0, 0 }, +}; + +/** + * omap_sdram_size - called from machdep to get the total memory size + * + * Since this function is called very early in the boot, there is none of the + * bus handling code setup. However the boot device map will be setup, so + * we can directly access registers already mapped. + * + * This is a bit ugly, but since we need this information early on and the + * only way to get it (appart from hardcoding it or via kernel args) is to read + * from the EMIF_SRAM registers. + * + * RETURNS: + * The size of memory in bytes. + */ +unsigned int +omap_sdram_size(void) +{ + uint32_t sdram_cfg; + uint32_t ibank, ebank, pagesize; + + /* Read the two SDRAM config register */ + sdram_cfg = *(volatile uint32_t*)(OMAP44XX_L3_EMIF1_VBASE + 0x0008); + + /* Read the REG_EBANK, REG_IBANK and REG_PAGESIZE - together these tell + * us the maximum size of memory we can access. + */ + ibank = (sdram_cfg >> 4) & 0x7; + ebank = (sdram_cfg >> 3) & 0x1; + pagesize = (sdram_cfg >> 0) & 0x7; + + if (bootverbose) + printf("omap_sdram_size: ibank=%u, ebank=%u, pagesize=%u\n", + ibank, ebank, pagesize); + + /* Using the above read values we determine the memory size, this was + * gleened from tables 15-106 and 15-107 in the omap44xx tech ref manual. + */ + return (1UL << (25 + ibank + ebank + pagesize)); +} + +/* + * Writes val to SCM register at offset off + */ +static void +omap4xx_scm_writes(device_t dev, bus_size_t off, uint16_t val) +{ + struct omap4_softc *sc = device_get_softc(dev); + + bus_write_2(sc->sc_scm_mem, off, val); +} + +/* + * Reads SCM register at offset off + */ +static uint16_t +omap4xx_scm_reads(device_t dev, bus_size_t off) +{ + struct omap4_softc *sc = device_get_softc(dev); + + return bus_read_2(sc->sc_scm_mem, off); +} + +static void +omap4xx_gic_dist_write(device_t dev, bus_size_t off, uint32_t val) +{ + struct omap4_softc *sc = device_get_softc(dev); + + bus_space_write_4(sc->sc_iotag, sc->sc_gic_dist_ioh, + off, val); +} + +static uint32_t +omap4xx_gic_dist_read(device_t dev, bus_size_t off) +{ + struct omap4_softc *sc = device_get_softc(dev); + + return bus_space_read_4(sc->sc_iotag, sc->sc_gic_dist_ioh, off); +} + +static void +omap4xx_gic_cpu_write(device_t dev, bus_size_t off, uint32_t val) +{ + struct omap4_softc *sc = device_get_softc(dev); + + bus_space_write_4(sc->sc_iotag, sc->sc_gic_cpu_ioh, + off, val); +} + +static uint32_t +omap4xx_gic_cpu_read(device_t dev, bus_size_t off) +{ + struct omap4_softc *sc = device_get_softc(dev); + + return bus_space_read_4(sc->sc_iotag, sc->sc_gic_cpu_ioh, off); +} + +static inline uint32_t +omap4xx_gbl_timer_read(device_t dev, bus_size_t off) +{ + struct omap4_softc *sc = device_get_softc(dev); + + return (bus_space_read_4(sc->sc_iotag, sc->sc_gbl_timer_ioh, off)); +} + +static inline void +omap4xx_gbl_timer_write(device_t dev, bus_size_t off, uint32_t val) +{ + struct omap4_softc *sc = device_get_softc(dev); + + bus_space_write_4(sc->sc_iotag, sc->sc_gbl_timer_ioh, off, val); +} + +static inline uint32_t +omap4xx_prv_timer_read(device_t dev, bus_size_t off) +{ + struct omap4_softc *sc = device_get_softc(dev); + + return (bus_space_read_4(sc->sc_iotag, sc->sc_prv_timer_ioh, off)); +} + +static inline void +omap4xx_prv_timer_write(device_t dev, bus_size_t off, uint32_t val) +{ + struct omap4_softc *sc = device_get_softc(dev); + + bus_space_write_4(sc->sc_iotag, sc->sc_prv_timer_ioh, off, val); +} + +/** + * omap44xx_identify - adds the SoC child components + * @dev: this device, the one we are adding to + * + * Adds a child to the omap3 base device. + * + */ +static void +omap44xx_identify(driver_t *drv, device_t parent) +{ + int omap44xx_irqs[] = { 27, 29, -1 }; + struct omap_mem_range omap44xx_mem[] = { { OMAP44XX_MPU_SUBSYS_HWBASE, + OMAP44XX_MPU_SUBSYS_SIZE }, + { 0, 0 } }; + int i; + + device_t self = BUS_ADD_CHILD(parent, 0, "omap44xx", 0); + + for (i = 0; omap44xx_irqs[i] != -1; i++) + bus_set_resource(self, SYS_RES_IRQ, i, omap44xx_irqs[i], 1); + + /* Assign the memory region to the resource list */ + for (i = 0; omap44xx_mem[i].base != 0; i++) { + bus_set_resource(self, SYS_RES_MEMORY, i, + omap44xx_mem[i].base, omap44xx_mem[i].size); + } +} + +/** + * omap44xx_probe - called when the device is probed + * @dev: the new device + * + * All we do in this routine is set the description of this device + * + */ +static int +omap44xx_probe(device_t dev) +{ + device_set_desc(dev, "TI OMAP44XX"); + return (0); +} + +/** + * omap44xx_attach - called when the device is attached + * @dev: the new device + * + * All we do in this routine is set the description of this device + * + */ +static int +omap44xx_attach(device_t dev) +{ + struct omap_softc *omapsc = device_get_softc(device_get_parent(dev)); + struct omap4_softc *sc = device_get_softc(dev); + + sc->sc_iotag = omapsc->sc_iotag; + sc->sc_dev = dev; + + + /* Map in the Generic Interrupt Controller (GIC) register set */ + if (bus_space_map(sc->sc_iotag, OMAP44XX_GIC_CPU_HWBASE, + OMAP44XX_GIC_CPU_SIZE, 0, &sc->sc_gic_cpu_ioh)) { + panic("%s: Cannot map registers", device_get_name(dev)); + } + + /* Also map in the CPU GIC register set */ + if (bus_space_map(sc->sc_iotag, OMAP44XX_GIC_DIST_HWBASE, + OMAP44XX_GIC_DIST_SIZE, 0, &sc->sc_gic_dist_ioh)) { + panic("%s: Cannot map registers", device_get_name(dev)); + } + + /* And the private and global timer register set */ + if (bus_space_map(sc->sc_iotag, OMAP44XX_PRV_TIMER_HWBASE, + OMAP44XX_PRV_TIMER_SIZE, 0, &sc->sc_prv_timer_ioh)) { + panic("%s: Cannot map registers", device_get_name(dev)); + } + if (bus_space_map(sc->sc_iotag, OMAP44XX_GBL_TIMER_HWBASE, + OMAP44XX_GBL_TIMER_SIZE, 0, &sc->sc_gbl_timer_ioh)) { + panic("%s: Cannot map registers", device_get_name(dev)); + } + + /* Map in the PL310 (L2 cache controller) as well */ + if (bus_space_map(sc->sc_iotag, OMAP44XX_PL310_HWBASE, + OMAP44XX_PL310_SIZE, 0, &sc->sc_pl310_ioh)) { + panic("%s: Cannot map registers", device_get_name(dev)); + } + + + /* Init SCM access resource */ + sc->sc_scm_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, + &sc->sc_scm_rid, + OMAP44XX_SCM_PADCONF_HWBASE, + OMAP44XX_SCM_PADCONF_HWBASE + OMAP44XX_SCM_PADCONF_SIZE, + OMAP44XX_SCM_PADCONF_SIZE, RF_ACTIVE); + + if (sc->sc_scm_mem == NULL) + printf("failed to allocate SCM memory resource"); + + /* TODO: Revisit - Install an interrupt post filter */ + arm_post_filter = omap4_post_filter_intr; + + /* Setup the ARM GIC interrupt controller */ + omap4_setup_intr_controller(dev, omap44xx_irq_prio); + /* Should be called after omap4_setup_intr_controller */ + omap4_setup_gic_cpu(0xF0); + + /* Setup basic timer stuff before cpu_initclocks is called */ + omap4_init_timer(dev); + + omap_scm_padconf_init_from_hints(dev); + + bus_generic_probe(dev); + bus_generic_attach(dev); + + return (0); +} + + + +static device_method_t omap44xx_methods[] = { + DEVMETHOD(device_probe, omap44xx_probe), + DEVMETHOD(device_attach, omap44xx_attach), + DEVMETHOD(device_identify, omap44xx_identify), + + /* SCM access methods */ + DEVMETHOD(omap_scm_reads, omap4xx_scm_reads), + DEVMETHOD(omap_scm_writes, omap4xx_scm_writes), + + /* OMAP4-specific accessors methods */ + + /* Interrupt controller */ + DEVMETHOD(omap4_gic_dist_read, omap4xx_gic_dist_read), + DEVMETHOD(omap4_gic_dist_write, omap4xx_gic_dist_write), + DEVMETHOD(omap4_gic_cpu_read, omap4xx_gic_cpu_read), + DEVMETHOD(omap4_gic_cpu_write, omap4xx_gic_cpu_write), + + /* Timers */ + DEVMETHOD(omap4_gbl_timer_read, omap4xx_gbl_timer_read), + DEVMETHOD(omap4_gbl_timer_write, omap4xx_gbl_timer_write), + DEVMETHOD(omap4_prv_timer_read, omap4xx_prv_timer_read), + DEVMETHOD(omap4_prv_timer_write, omap4xx_prv_timer_write), + + {0, 0}, +}; + +static driver_t omap44xx_driver = { + "omap44xx", + omap44xx_methods, + sizeof(struct omap4_softc), +}; + +static devclass_t omap44xx_devclass; + +DRIVER_MODULE(omap44xx, omap, omap44xx_driver, omap44xx_devclass, 0, 0); Index: projects/armv6/sys/arm/omap/omap4/omap44xx_reg.h =================================================================== --- projects/armv6/sys/arm/omap/omap4/omap44xx_reg.h (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/omap44xx_reg.h (revision 230362) @@ -0,0 +1,584 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Texas Instruments - OMAP44xx series processors + * + * Reference: + * OMAP44xx Applications Processor + * Technical Reference Manual + * (omap44xx_techref.pdf) + * + * + * Note: + * The devices are mapped into address above 0xD000_0000 as the kernel space + * memory is at 0xC000_0000 and above. The first 256MB after this is reserved + * for the size of the kernel, everything above that is reserved for SoC + * devices. + * + */ +#ifndef _OMAP44XX_REG_H_ +#define _OMAP44XX_REG_H_ + +#ifndef _LOCORE +#include /* for uint32_t */ +#endif + + + + + +/* Physical/Virtual address for SDRAM controller */ + +#define OMAP44XX_SMS_VBASE 0x6C000000UL +#define OMAP44XX_SMS_HWBASE 0x6C000000UL +#define OMAP44XX_SMS_SIZE 0x01000000UL + +#define OMAP44XX_SDRC_VBASE 0x6D000000UL +#define OMAP44XX_SDRC_HWBASE 0x6D000000UL +#define OMAP44XX_SDRC_SIZE 0x01000000UL + + + +/* Physical/Virtual address for I/O space */ + +#define OMAP44XX_L3_EMU_VBASE 0xD4000000UL +#define OMAP44XX_L3_EMU_HWBASE 0x54000000UL +#define OMAP44XX_L3_EMU_SIZE 0x00200000UL + +#define OMAP44XX_L3_EMIF1_VBASE 0xEC000000UL +#define OMAP44XX_L3_EMIF1_HWBASE 0x4C000000UL +#define OMAP44XX_L3_EMIF1_SIZE 0x01000000UL + +#define OMAP44XX_L3_EMIF2_VBASE 0xED000000UL +#define OMAP44XX_L3_EMIF2_HWBASE 0x4D000000UL +#define OMAP44XX_L3_EMIF2_SIZE 0x01000000UL + + +#define OMAP44XX_L4_CORE_VBASE 0xEA000000UL +#define OMAP44XX_L4_CORE_HWBASE 0x4A000000UL +#define OMAP44XX_L4_CORE_SIZE 0x01000000UL + +#define OMAP44XX_L4_WAKEUP_VBASE 0xEA300000UL +#define OMAP44XX_L4_WAKEUP_HWBASE 0x4A300000UL +#define OMAP44XX_L4_WAKEUP_SIZE 0x00040000UL + +#define OMAP44XX_L4_PERIPH_VBASE 0xE8000000UL +#define OMAP44XX_L4_PERIPH_HWBASE 0x48000000UL +#define OMAP44XX_L4_PERIPH_SIZE 0x01000000UL + +#define OMAP44XX_L4_ABE_VBASE 0xE9000000UL +#define OMAP44XX_L4_ABE_HWBASE 0x49000000UL +#define OMAP44XX_L4_ABE_SIZE 0x00100000UL + + +/* Physical/Virtual address for MPU Subsystem space */ + +#define OMAP44XX_MPU_SUBSYS_VBASE (OMAP44XX_L4_PERIPH_VBASE + 0x00240000UL) +#define OMAP44XX_MPU_SUBSYS_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + 0x00240000UL) +#define OMAP44XX_MPU_SUBSYS_SIZE 0x00004000UL + +/* + * MPU Subsystem addresss offsets + */ +#define OMAP44XX_SCU_OFFSET 0x00000000UL +#define OMAP44XX_GIC_CPU_OFFSET 0x00000100UL +#define OMAP44XX_GBL_TIMER_OFFSET 0x00000200UL +#define OMAP44XX_PRV_TIMER_OFFSET 0x00000600UL +#define OMAP44XX_GIC_DIST_OFFSET 0x00001000UL +#define OMAP44XX_PL310_OFFSET 0x00002000UL +#define OMAP44XX_CORTEXA9_SOCKET_PRCM_OFFSET 0x00003000UL +#define OMAP44XX_CORTEXA9_PRM_OFFSET 0x00003200UL +#define OMAP44XX_CORTEXA9_CPU0_OFFSET 0x00003400UL +#define OMAP44XX_CORTEXA9_CPU1_OFFSET 0x00003800UL + +#define OMAP44XX_SCU_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_SCU_OFFSET) +#define OMAP44XX_SCU_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_SCU_OFFSET) +#define OMAP44XX_SCU_SIZE 0x00000080UL +#define OMAP44XX_GIC_CPU_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GIC_CPU_OFFSET) +#define OMAP44XX_GIC_CPU_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GIC_CPU_OFFSET) +#define OMAP44XX_GIC_CPU_SIZE 0x00000100UL +#define OMAP44XX_GBL_TIMER_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GBL_TIMER_OFFSET) +#define OMAP44XX_GBL_TIMER_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GBL_TIMER_OFFSET) +#define OMAP44XX_GBL_TIMER_SIZE 0x00000100UL +#define OMAP44XX_PRV_TIMER_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_PRV_TIMER_OFFSET) +#define OMAP44XX_PRV_TIMER_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_PRV_TIMER_OFFSET) +#define OMAP44XX_PRV_TIMER_SIZE 0x00000100UL +#define OMAP44XX_GIC_DIST_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GIC_DIST_OFFSET) +#define OMAP44XX_GIC_DIST_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GIC_DIST_OFFSET) +#define OMAP44XX_GIC_DIST_SIZE 0x00000100UL +#define OMAP44XX_PL310_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_PL310_OFFSET) +#define OMAP44XX_PL310_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_PL310_OFFSET) +#define OMAP44XX_PL310_SIZE 0x00001000UL + + + + +/* + * L4-CORE Physical/Virtual addresss offsets + */ +#define OMAP44XX_SCM_OFFSET 0x00002000UL +#define OMAP44XX_CM_OFFSET 0x00004000UL +#define OMAP44XX_SDMA_OFFSET 0x00056000UL +#define OMAP44XX_USB_TLL_OFFSET 0x00062000UL +#define OMAP44XX_USB_UHH_OFFSET 0x00064000UL +#define OMAP44XX_USB_OHCI_OFFSET 0x00064800UL +#define OMAP44XX_USB_EHCI_OFFSET 0x00064C00UL +#define OMAP44XX_MCBSP1_OFFSET 0x00074000UL +#define OMAP44XX_MCBSP5_OFFSET 0x00096000UL +#define OMAP44XX_SCM_PADCONF_OFFSET 0x00100000UL + +/* + * L4-WAKEUP Physical/Virtual addresss offsets + */ +#define OMAP44XX_PRM_OFFSET 0x00006000UL +#define OMAP44XX_SCRM_OFFSET 0x0000A000UL +#define OMAP44XX_GPIO1_OFFSET 0x00010000UL +#define OMAP44XX_GPTIMER1_OFFSET 0x00018000UL + + + +/* + * L4-PERIPH Physical/Virtual addresss offsets + */ +#define OMAP44XX_UART3_OFFSET 0x00020000UL +#define OMAP44XX_GPTIMER2_OFFSET 0x00032000UL +#define OMAP44XX_GPTIMER3_OFFSET 0x00034000UL +#define OMAP44XX_GPTIMER4_OFFSET 0x00036000UL +#define OMAP44XX_GPTIMER9_OFFSET 0x0003E000UL +#define OMAP44XX_GPIO2_OFFSET 0x00055000UL +#define OMAP44XX_GPIO3_OFFSET 0x00057000UL +#define OMAP44XX_GPIO4_OFFSET 0x00059000UL +#define OMAP44XX_GPIO5_OFFSET 0x0005B000UL +#define OMAP44XX_GPIO6_OFFSET 0x0005D000UL +#define OMAP44XX_I2C3_OFFSET 0x00060000UL +#define OMAP44XX_UART1_OFFSET 0x0006A000UL +#define OMAP44XX_UART2_OFFSET 0x0006C000UL +#define OMAP44XX_UART4_OFFSET 0x0006E000UL +#define OMAP44XX_I2C1_OFFSET 0x00070000UL +#define OMAP44XX_I2C2_OFFSET 0x00072000UL +#define OMAP44XX_SLIMBUS2_OFFSET 0x00076000UL +#define OMAP44XX_ELM_OFFSET 0x00078000UL +#define OMAP44XX_GPTIMER10_OFFSET 0x00086000UL +#define OMAP44XX_GPTIMER11_OFFSET 0x00088000UL +#define OMAP44XX_MCBSP4_OFFSET 0x00096000UL +#define OMAP44XX_MCSPI1_OFFSET 0x00098000UL +#define OMAP44XX_MCSPI2_OFFSET 0x0009A000UL +#define OMAP44XX_MMCHS1_OFFSET 0x0009C000UL +#define OMAP44XX_MMCSD3_OFFSET 0x000AD000UL +#define OMAP44XX_MMCHS2_OFFSET 0x000B4000UL +#define OMAP44XX_MMCSD4_OFFSET 0x000D1000UL +#define OMAP44XX_MMCSD5_OFFSET 0x000D5000UL +#define OMAP44XX_I2C4_OFFSET 0x00350000UL + +/* The following are registers defined as part of the ARM MPCORE system, + * they are not SoC components rather registers that control the MPCORE core. + */ +// #define OMAP44XX_SCU_OFFSET 0x48240000 /* Snoop control unit */ +// #define OMAP44XX_GIC_PROC_OFFSET 0x48240100 /* Interrupt controller unit */ +// #define OMAP44XX_MPU_TIMER_OFFSET 0x48240600 +// #define OMAP44XX_GIC_INTR_OFFSET 0x48241000 +// #define OMAP44XX_PL310_OFFSET 0x48242000 /* L2 Cache controller */ + + +/* + * L4-ABE Physical/Virtual addresss offsets + */ +#define OMAP44XX_GPTIMER5_OFFSET 0x00038000UL +#define OMAP44XX_GPTIMER6_OFFSET 0x0003A000UL +#define OMAP44XX_GPTIMER7_OFFSET 0x0003C000UL +#define OMAP44XX_GPTIMER8_OFFSET 0x0003E000UL + + + + + +/* + * System Control Module + */ +#define OMAP44XX_SCM_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SCM_OFFSET) +#define OMAP44XX_SCM_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SCM_OFFSET) +#define OMAP44XX_SCM_SIZE 0x00001000UL + + + +/* + * + */ +#define OMAP44XX_CM_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_CM_OFFSET) +#define OMAP44XX_CM_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_CM_OFFSET) +#define OMAP44XX_CM_SIZE 0x00001500UL + + +/* + * + */ +#define OMAP44XX_PRM_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_PRM_OFFSET) +#define OMAP44XX_PRM_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_PRM_OFFSET) +#define OMAP44XX_PRM_SIZE 0x00001600UL + +/* + * + */ +#define OMAP44XX_SCRM_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_SCRM_OFFSET) +#define OMAP44XX_SCRM_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_SCRM_OFFSET) +#define OMAP44XX_SCRM_SIZE 0x00000800UL + + + +/* + * Uarts + */ +#define OMAP44XX_UART1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_UART1_OFFSET) +#define OMAP44XX_UART1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_UART1_OFFSET) +#define OMAP44XX_UART1_SIZE 0x00001000UL +#define OMAP44XX_UART2_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_UART2_OFFSET) +#define OMAP44XX_UART2_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_UART2_OFFSET) +#define OMAP44XX_UART2_SIZE 0x00001000UL +#define OMAP44XX_UART3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_UART3_OFFSET) +#define OMAP44XX_UART3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_UART3_OFFSET) +#define OMAP44XX_UART3_SIZE 0x00001000UL +#define OMAP44XX_UART4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_UART4_OFFSET) +#define OMAP44XX_UART4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_UART4_OFFSET) +#define OMAP44XX_UART4_SIZE 0x00001000UL + + + + +/* + * I2C Modules + */ +#define OMAP44XX_I2C1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C1_OFFSET) +#define OMAP44XX_I2C1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C1_OFFSET) +#define OMAP44XX_I2C1_SIZE 0x00000080UL +#define OMAP44XX_I2C2_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C2_OFFSET) +#define OMAP44XX_I2C2_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C2_OFFSET) +#define OMAP44XX_I2C2_SIZE 0x00000080UL +#define OMAP44XX_I2C3_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C3_OFFSET) +#define OMAP44XX_I2C3_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C3_OFFSET) +#define OMAP44XX_I2C3_SIZE 0x00000080UL + + + +/* + * McBSP Modules + */ +#define OMAP44XX_MCBSP1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_MCBSP1_OFFSET) +#define OMAP44XX_MCBSP1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_MCBSP1_OFFSET) +#define OMAP44XX_MCBSP1_SIZE 0x00001000UL +#define OMAP44XX_MCBSP2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP2_OFFSET) +#define OMAP44XX_MCBSP2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP2_OFFSET) +#define OMAP44XX_MCBSP2_SIZE 0x00001000UL +#define OMAP44XX_MCBSP3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP3_OFFSET) +#define OMAP44XX_MCBSP3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP3_OFFSET) +#define OMAP44XX_MCBSP3_SIZE 0x00001000UL +#define OMAP44XX_MCBSP4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP4_OFFSET) +#define OMAP44XX_MCBSP4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP4_OFFSET) +#define OMAP44XX_MCBSP4_SIZE 0x00001000UL +#define OMAP44XX_MCBSP5_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_MCBSP5_OFFSET) +#define OMAP44XX_MCBSP5_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_MCBSP5_OFFSET) +#define OMAP44XX_MCBSP5_SIZE 0x00001000UL + + + +/* + * USB TTL Module + */ +#define OMAP44XX_USB_TLL_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_TLL_OFFSET) +#define OMAP44XX_USB_TLL_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_TLL_OFFSET) +#define OMAP44XX_USB_TLL_SIZE 0x00001000UL + +/* + * USB Host Module + */ +#define OMAP44XX_USB_UHH_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_UHH_OFFSET) +#define OMAP44XX_USB_UHH_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_UHH_OFFSET) +#define OMAP44XX_USB_UHH_SIZE 0x00000700UL + +/* + * USB OHCI Module + */ +#define OMAP44XX_USB_OHCI_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_OHCI_OFFSET) +#define OMAP44XX_USB_OHCI_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_OHCI_OFFSET) +#define OMAP44XX_USB_OHCI_SIZE 0x00000400UL + +/* + * USB EHCI Module + */ +#define OMAP44XX_USB_EHCI_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_EHCI_OFFSET) +#define OMAP44XX_USB_EHCI_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_EHCI_OFFSET) +#define OMAP44XX_USB_EHCI_SIZE 0x0000400UL + + + + + +/* + * SDMA Offset + * PA 0x4805 6000 + */ + +#define OMAP44XX_SDMA_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SDMA_OFFSET) +#define OMAP44XX_SDMA_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SDMA_OFFSET) +#define OMAP44XX_SDMA_SIZE 0x00001000UL + + + +/* + * Interrupt Controller Unit. + * + * Refer to the omap4_intr.c file for interrupt controller (GIC) + * implementation. + * + * Note: + * - 16 Interprocessor interrupts (IPI): ID[15:0] + * - 2 private Timer/Watchdog interrupts: ID[30:29] + * - 2 legacy nFIQ & nIRQ: one per CPU, bypasses the interrupt distributor + * logic and directly drives interrupt requests into CPU if used in + * legacy mode (else treated like other interrupts lines with ID28 + * and ID31 respectively) + * - 128 hardware interrupts: ID[159:32] (rising-edge or high-level sensitive). + */ +#define OMAP44XX_HARDIRQ(x) (32 + (x)) + +#define OMAP44XX_IRQ_L2CACHE OMAP44XX_HARDIRQ(0) /* L2 cache controller interrupt */ +#define OMAP44XX_IRQ_CTI_0 OMAP44XX_HARDIRQ(1) /* Cross-trigger module 0 (CTI0) interrupt */ +#define OMAP44XX_IRQ_CTI_1 OMAP44XX_HARDIRQ(2) /* Cross-trigger module 1 (CTI1) interrupt */ +#define OMAP44XX_IRQ_RESERVED3 OMAP44XX_HARDIRQ(3) /* RESERVED */ +#define OMAP44XX_IRQ_ELM OMAP44XX_HARDIRQ(4) /* Error location process completion */ +#define OMAP44XX_IRQ_RESERVED5 OMAP44XX_HARDIRQ(5) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED6 OMAP44XX_HARDIRQ(6) /* RESERVED */ +#define OMAP44XX_IRQ_SYS_NIRQ OMAP44XX_HARDIRQ(7) /* External source (active low) */ +#define OMAP44XX_IRQ_RESERVED8 OMAP44XX_HARDIRQ(8) /* RESERVED */ +#define OMAP44XX_IRQ_L3_DBG OMAP44XX_HARDIRQ(9) /* L3 interconnect debug error */ +#define OMAP44XX_IRQ_L3_APP OMAP44XX_HARDIRQ(10) /* L3 interconnect application error */ +#define OMAP44XX_IRQ_PRCM_MPU OMAP44XX_HARDIRQ(11) /* PRCM module IRQ */ +#define OMAP44XX_IRQ_SDMA0 OMAP44XX_HARDIRQ(12) /* System DMA request 0(3) */ +#define OMAP44XX_IRQ_SDMA1 OMAP44XX_HARDIRQ(13) /* System DMA request 1(3) */ +#define OMAP44XX_IRQ_SDMA2 OMAP44XX_HARDIRQ(14) /* System DMA request 2 */ +#define OMAP44XX_IRQ_SDMA3 OMAP44XX_HARDIRQ(15) /* System DMA request 3 */ +#define OMAP44XX_IRQ_MCBSP4 OMAP44XX_HARDIRQ(16) /* McBSP module 4 IRQ */ +#define OMAP44XX_IRQ_MCBSP1 OMAP44XX_HARDIRQ(17) /* McBSP module 1 IRQ */ +#define OMAP44XX_IRQ_SR1 OMAP44XX_HARDIRQ(18) /* SmartReflex™ 1 */ +#define OMAP44XX_IRQ_SR2 OMAP44XX_HARDIRQ(19) /* SmartReflex™ 2 */ +#define OMAP44XX_IRQ_GPMC OMAP44XX_HARDIRQ(20) /* General-purpose memory controller module */ +#define OMAP44XX_IRQ_SGX OMAP44XX_HARDIRQ(21) /* 2D/3D graphics module */ +#define OMAP44XX_IRQ_MCBSP2 OMAP44XX_HARDIRQ(22) /* McBSP module 2 */ +#define OMAP44XX_IRQ_MCBSP3 OMAP44XX_HARDIRQ(23) /* McBSP module 3 */ +#define OMAP44XX_IRQ_ISS5 OMAP44XX_HARDIRQ(24) /* Imaging subsystem interrupt 5 */ +#define OMAP44XX_IRQ_DSS OMAP44XX_HARDIRQ(25) /* Display subsystem module(3) */ +#define OMAP44XX_IRQ_MAIL_U0 OMAP44XX_HARDIRQ(26) /* Mailbox user 0 request */ +#define OMAP44XX_IRQ_C2C_SSCM OMAP44XX_HARDIRQ(27) /* C2C status interrupt */ +#define OMAP44XX_IRQ_DSP_MMU OMAP44XX_HARDIRQ(28) /* DSP MMU */ +#define OMAP44XX_IRQ_GPIO1_MPU OMAP44XX_HARDIRQ(29) /* GPIO module 1(3) */ +#define OMAP44XX_IRQ_GPIO2_MPU OMAP44XX_HARDIRQ(30) /* GPIO module 2(3) */ +#define OMAP44XX_IRQ_GPIO3_MPU OMAP44XX_HARDIRQ(31) /* GPIO module 3(3) */ +#define OMAP44XX_IRQ_GPIO4_MPU OMAP44XX_HARDIRQ(32) /* GPIO module 4(3) */ +#define OMAP44XX_IRQ_GPIO5_MPU OMAP44XX_HARDIRQ(33) /* GPIO module 5(3) */ +#define OMAP44XX_IRQ_GPIO6_MPU OMAP44XX_HARDIRQ(34) /* GPIO module 6(3) */ +#define OMAP44XX_IRQ_RESERVED35 OMAP44XX_HARDIRQ(35) /* RESERVED */ +#define OMAP44XX_IRQ_WDT3 OMAP44XX_HARDIRQ(36) /* Watchdog timer module 3 overflow */ +#define OMAP44XX_IRQ_GPT1 OMAP44XX_HARDIRQ(37) /* General-purpose timer module 1 */ +#define OMAP44XX_IRQ_GPT2 OMAP44XX_HARDIRQ(38) /* General-purpose timer module 2 */ +#define OMAP44XX_IRQ_GPT3 OMAP44XX_HARDIRQ(39) /* General-purpose timer module 3 */ +#define OMAP44XX_IRQ_GPT4 OMAP44XX_HARDIRQ(40) /* General-purpose timer module 4 */ +#define OMAP44XX_IRQ_GPT5 OMAP44XX_HARDIRQ(41) /* General-purpose timer module 5 */ +#define OMAP44XX_IRQ_GPT6 OMAP44XX_HARDIRQ(42) /* General-purpose timer module 6 */ +#define OMAP44XX_IRQ_GPT7 OMAP44XX_HARDIRQ(43) /* General-purpose timer module 7 */ +#define OMAP44XX_IRQ_GPT8 OMAP44XX_HARDIRQ(44) /* General-purpose timer module 8 */ +#define OMAP44XX_IRQ_GPT9 OMAP44XX_HARDIRQ(45) /* General-purpose timer module 9 */ +#define OMAP44XX_IRQ_GPT10 OMAP44XX_HARDIRQ(46) /* General-purpose timer module 10 */ +#define OMAP44XX_IRQ_GPT11 OMAP44XX_HARDIRQ(47) /* General-purpose timer module 11 */ +#define OMAP44XX_IRQ_MCSPI4 OMAP44XX_HARDIRQ(48) /* McSPI module 4 */ +#define OMAP44XX_IRQ_RESERVED49 OMAP44XX_HARDIRQ(49) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED50 OMAP44XX_HARDIRQ(50) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED51 OMAP44XX_HARDIRQ(51) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED52 OMAP44XX_HARDIRQ(52) /* RESERVED */ +#define OMAP44XX_IRQ_DSS_DSI1 OMAP44XX_HARDIRQ(53) /* Display Subsystem DSI1 interrupt */ +#define OMAP44XX_IRQ_RESERVED54 OMAP44XX_HARDIRQ(54) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED55 OMAP44XX_HARDIRQ(55) /* RESERVED */ +#define OMAP44XX_IRQ_I2C1 OMAP44XX_HARDIRQ(56) /* I2C module 1 */ +#define OMAP44XX_IRQ_I2C2 OMAP44XX_HARDIRQ(57) /* I2C module 2 */ +#define OMAP44XX_IRQ_HDQ OMAP44XX_HARDIRQ(58) /* HDQ / One-wire */ +#define OMAP44XX_IRQ_MMC5 OMAP44XX_HARDIRQ(59) /* MMC5 interrupt */ +#define OMAP44XX_IRQ_RESERVED60 OMAP44XX_HARDIRQ(60) /* RESERVED */ +#define OMAP44XX_IRQ_I2C3 OMAP44XX_HARDIRQ(61) /* I2C module 3 */ +#define OMAP44XX_IRQ_I2C4 OMAP44XX_HARDIRQ(62) /* I2C module 4 */ +#define OMAP44XX_IRQ_RESERVED63 OMAP44XX_HARDIRQ(63) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED64 OMAP44XX_HARDIRQ(64) /* RESERVED */ +#define OMAP44XX_IRQ_MCSPI1 OMAP44XX_HARDIRQ(65) /* McSPI module 1 */ +#define OMAP44XX_IRQ_MCSPI2 OMAP44XX_HARDIRQ(66) /* McSPI module 2 */ +#define OMAP44XX_IRQ_HSI_P1 OMAP44XX_HARDIRQ(67) /* HSI Port 1 interrupt */ +#define OMAP44XX_IRQ_HSI_P2 OMAP44XX_HARDIRQ(68) /* HSI Port 2 interrupt */ +#define OMAP44XX_IRQ_FDIF_3 OMAP44XX_HARDIRQ(69) /* Face detect interrupt 3 */ +#define OMAP44XX_IRQ_UART4 OMAP44XX_HARDIRQ(70) /* UART module 4 interrupt */ +#define OMAP44XX_IRQ_HSI_DMA OMAP44XX_HARDIRQ(71) /* HSI DMA engine MPU request */ +#define OMAP44XX_IRQ_UART1 OMAP44XX_HARDIRQ(72) /* UART module 1 */ +#define OMAP44XX_IRQ_UART2 OMAP44XX_HARDIRQ(73) /* UART module 2 */ +#define OMAP44XX_IRQ_UART3 OMAP44XX_HARDIRQ(74) /* UART module 3 (also infrared)(3) */ +#define OMAP44XX_IRQ_PBIAS OMAP44XX_HARDIRQ(75) /* Merged interrupt for PBIASlite1 and 2 */ +#define OMAP44XX_IRQ_OHCI OMAP44XX_HARDIRQ(76) /* OHCI controller HSUSB MP Host Interrupt */ +#define OMAP44XX_IRQ_EHCI OMAP44XX_HARDIRQ(77) /* EHCI controller HSUSB MP Host Interrupt */ +#define OMAP44XX_IRQ_TLL OMAP44XX_HARDIRQ(78) /* HSUSB MP TLL Interrupt */ +#define OMAP44XX_IRQ_RESERVED79 OMAP44XX_HARDIRQ(79) /* RESERVED */ +#define OMAP44XX_IRQ_WDT2 OMAP44XX_HARDIRQ(80) /* WDTIMER2 interrupt */ +#define OMAP44XX_IRQ_RESERVED81 OMAP44XX_HARDIRQ(81) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED82 OMAP44XX_HARDIRQ(82) /* RESERVED */ +#define OMAP44XX_IRQ_MMC1 OMAP44XX_HARDIRQ(83) /* MMC/SD module 1 */ +#define OMAP44XX_IRQ_DSS_DSI2 OMAP44XX_HARDIRQ(84) /* Display subsystem DSI2 interrupt */ +#define OMAP44XX_IRQ_RESERVED85 OMAP44XX_HARDIRQ(85) /* Reserved */ +#define OMAP44XX_IRQ_MMC2 OMAP44XX_HARDIRQ(86) /* MMC/SD module 2 */ +#define OMAP44XX_IRQ_MPU_ICR OMAP44XX_HARDIRQ(87) /* MPU ICR */ +#define OMAP44XX_IRQ_C2C_GPI OMAP44XX_HARDIRQ(88) /* C2C GPI interrupt */ +#define OMAP44XX_IRQ_FSUSB OMAP44XX_HARDIRQ(89) /* FS-USB - host controller Interrupt */ +#define OMAP44XX_IRQ_FSUSB_SMI OMAP44XX_HARDIRQ(90) /* FS-USB - host controller SMI Interrupt */ +#define OMAP44XX_IRQ_MCSPI3 OMAP44XX_HARDIRQ(91) /* McSPI module 3 */ +#define OMAP44XX_IRQ_HSUSB_OTG OMAP44XX_HARDIRQ(92) /* High-Speed USB OTG controller */ +#define OMAP44XX_IRQ_HSUSB_OTG_DMA OMAP44XX_HARDIRQ(93) /* High-Speed USB OTG DMA controller */ +#define OMAP44XX_IRQ_MMC3 OMAP44XX_HARDIRQ(94) /* MMC/SD module 3 */ +#define OMAP44XX_IRQ_RESERVED95 OMAP44XX_HARDIRQ(95) /* RESERVED */ +#define OMAP44XX_IRQ_MMC4 OMAP44XX_HARDIRQ(96) /* MMC4 interrupt */ +#define OMAP44XX_IRQ_SLIMBUS1 OMAP44XX_HARDIRQ(97) /* SLIMBUS1 interrupt */ +#define OMAP44XX_IRQ_SLIMBUS2 OMAP44XX_HARDIRQ(98) /* SLIMBUS2 interrupt */ +#define OMAP44XX_IRQ_ABE OMAP44XX_HARDIRQ(99) /* Audio back-end interrupt */ +#define OMAP44XX_IRQ_CORTEXM3_MMU OMAP44XX_HARDIRQ(100) /* Cortex-M3 MMU interrupt */ +#define OMAP44XX_IRQ_DSS_HDMI OMAP44XX_HARDIRQ(101) /* Display subsystem HDMI interrupt */ +#define OMAP44XX_IRQ_SR_IVA OMAP44XX_HARDIRQ(102) /* SmartReflex IVA interrupt */ +#define OMAP44XX_IRQ_IVAHD1 OMAP44XX_HARDIRQ(103) /* Sync interrupt from iCONT2 (vDMA) */ +#define OMAP44XX_IRQ_IVAHD2 OMAP44XX_HARDIRQ(104) /* Sync interrupt from iCONT1 */ +#define OMAP44XX_IRQ_RESERVED105 OMAP44XX_HARDIRQ(105) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED106 OMAP44XX_HARDIRQ(106) /* RESERVED */ +#define OMAP44XX_IRQ_IVAHD_MAILBOX0 OMAP44XX_HARDIRQ(107) /* IVAHD mailbox interrupt */ +#define OMAP44XX_IRQ_RESERVED108 OMAP44XX_HARDIRQ(108) /* RESERVED */ +#define OMAP44XX_IRQ_MCASP1 OMAP44XX_HARDIRQ(109) /* McASP1 transmit interrupt */ +#define OMAP44XX_IRQ_EMIF1 OMAP44XX_HARDIRQ(110) /* EMIF1 interrupt */ +#define OMAP44XX_IRQ_EMIF2 OMAP44XX_HARDIRQ(111) /* EMIF2 interrupt */ +#define OMAP44XX_IRQ_MCPDM OMAP44XX_HARDIRQ(112) /* MCPDM interrupt */ +#define OMAP44XX_IRQ_DMM OMAP44XX_HARDIRQ(113) /* DMM interrupt */ +#define OMAP44XX_IRQ_DMIC OMAP44XX_HARDIRQ(114) /* DMIC interrupt */ +#define OMAP44XX_IRQ_RESERVED115 OMAP44XX_HARDIRQ(115) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED116 OMAP44XX_HARDIRQ(116) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED117 OMAP44XX_HARDIRQ(117) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED118 OMAP44XX_HARDIRQ(118) /* RESERVED */ +#define OMAP44XX_IRQ_SYS_NIRQ2 OMAP44XX_HARDIRQ(119) /* External source 2 (active low) */ +#define OMAP44XX_IRQ_KBD OMAP44XX_HARDIRQ(120) /* Keyboard controller interrupt */ +#define OMAP44XX_IRQ_RESERVED121 OMAP44XX_HARDIRQ(121) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED122 OMAP44XX_HARDIRQ(122) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED123 OMAP44XX_HARDIRQ(123) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED124 OMAP44XX_HARDIRQ(124) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED125 OMAP44XX_HARDIRQ(125) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED126 OMAP44XX_HARDIRQ(126) /* RESERVED */ +#define OMAP44XX_IRQ_RESERVED127 OMAP44XX_HARDIRQ(127) /* RESERVED */ + + + +/* + * General Purpose Timers + */ +#define OMAP44XX_GPTIMER1_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_GPTIMER1_OFFSET) +#define OMAP44XX_GPTIMER1_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_GPTIMER1_OFFSET) +#define OMAP44XX_GPTIMER2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER2_OFFSET) +#define OMAP44XX_GPTIMER2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER2_OFFSET) +#define OMAP44XX_GPTIMER3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER3_OFFSET) +#define OMAP44XX_GPTIMER3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER3_OFFSET) +#define OMAP44XX_GPTIMER4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER4_OFFSET) +#define OMAP44XX_GPTIMER4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER4_OFFSET) +#define OMAP44XX_GPTIMER5_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER5_OFFSET) +#define OMAP44XX_GPTIMER5_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER5_OFFSET) +#define OMAP44XX_GPTIMER6_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER6_OFFSET) +#define OMAP44XX_GPTIMER6_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER6_OFFSET) +#define OMAP44XX_GPTIMER7_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER7_OFFSET) +#define OMAP44XX_GPTIMER7_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER7_OFFSET) +#define OMAP44XX_GPTIMER8_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER8_OFFSET) +#define OMAP44XX_GPTIMER8_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER8_OFFSET) +#define OMAP44XX_GPTIMER9_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER9_OFFSET) +#define OMAP44XX_GPTIMER9_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER9_OFFSET) +#define OMAP44XX_GPTIMER10_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER10_OFFSET) +#define OMAP44XX_GPTIMER10_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER10_OFFSET) +#define OMAP44XX_GPTIMER11_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER11_OFFSET) +#define OMAP44XX_GPTIMER11_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER11_OFFSET) +#define OMAP44XX_GPTIMER_SIZE 0x00001000UL + + + +/* + * GPIO - General Purpose IO + */ + +/* Base addresses for the GPIO modules */ +#define OMAP44XX_GPIO1_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_GPIO1_OFFSET) +#define OMAP44XX_GPIO1_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_GPIO1_OFFSET) +#define OMAP44XX_GPIO1_SIZE 0x00001000UL +#define OMAP44XX_GPIO2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO2_OFFSET) +#define OMAP44XX_GPIO2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO2_OFFSET) +#define OMAP44XX_GPIO2_SIZE 0x00001000UL +#define OMAP44XX_GPIO3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO3_OFFSET) +#define OMAP44XX_GPIO3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO3_OFFSET) +#define OMAP44XX_GPIO3_SIZE 0x00001000UL +#define OMAP44XX_GPIO4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO4_OFFSET) +#define OMAP44XX_GPIO4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO4_OFFSET) +#define OMAP44XX_GPIO4_SIZE 0x00001000UL +#define OMAP44XX_GPIO5_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO5_OFFSET) +#define OMAP44XX_GPIO5_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO5_OFFSET) +#define OMAP44XX_GPIO5_SIZE 0x00001000UL +#define OMAP44XX_GPIO6_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO6_OFFSET) +#define OMAP44XX_GPIO6_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO6_OFFSET) +#define OMAP44XX_GPIO6_SIZE 0x00001000UL + + +/* + * MMC/SD/SDIO + */ + +/* Base addresses for the MMC/SD/SDIO modules */ +#define OMAP44XX_MMCHS1_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCHS1_OFFSET) +#define OMAP44XX_MMCHS1_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCHS1_OFFSET) +#define OMAP44XX_MMCHS2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCHS2_OFFSET) +#define OMAP44XX_MMCHS2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCHS2_OFFSET) +#define OMAP44XX_MMCHS3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD3_OFFSET) +#define OMAP44XX_MMCHS3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD3_OFFSET) +#define OMAP44XX_MMCHS4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD4_OFFSET) +#define OMAP44XX_MMCHS4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD4_OFFSET) +#define OMAP44XX_MMCHS5_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD5_OFFSET) +#define OMAP44XX_MMCHS5_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD5_OFFSET) +#define OMAP44XX_MMCHS_SIZE 0x00001000UL + + + +/* + * SCM - System Control Module + */ + +/* Base addresses for the SC modules */ +#define OMAP44XX_SCM_PADCONF_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SCM_PADCONF_OFFSET) +#define OMAP44XX_SCM_PADCONF_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SCM_PADCONF_OFFSET) +#define OMAP44XX_SCM_PADCONF_SIZE 0x00001000UL + + + + +#endif /* _OMAP44XX_REG_H_ */ Index: projects/armv6/sys/arm/omap/omap4/omap4_if.m =================================================================== --- projects/armv6/sys/arm/omap/omap4/omap4_if.m (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/omap4_if.m (revision 230362) @@ -0,0 +1,105 @@ +#- +# Copyright (c) 2012 Oleksandr Tymoshenko +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# $FreeBSD$ +# + +#include + +#include +#include + +INTERFACE omap4; + +# +# Read Generic Interrupt Controller register +# +METHOD uint32_t gic_dist_read { + device_t dev; + bus_size_t off; +}; + +# +# Write GIC register +# +METHOD void gic_dist_write { + device_t dev; + bus_size_t off; + uint32_t val; +}; + + +# +# Read GIC CPU register +# +METHOD uint32_t gic_cpu_read { + device_t dev; + bus_size_t off; +}; + +# +# Write GIC CPU register +# +METHOD void gic_cpu_write { + device_t dev; + bus_size_t off; + uint32_t val; +}; + + +# +# Read global timer register +# +METHOD uint32_t gbl_timer_read { + device_t dev; + bus_size_t off; +}; + +# +# Write global timer register +# +METHOD void gbl_timer_write { + device_t dev; + bus_size_t off; + uint32_t val; +}; + +# +# Read private timer register +# +METHOD uint32_t prv_timer_read { + device_t dev; + bus_size_t off; +}; + +# +# Write private timer register +# +METHOD void prv_timer_write { + device_t dev; + bus_size_t off; + uint32_t val; +}; + Index: projects/armv6/sys/arm/omap/omap4/omap4_intr.c =================================================================== --- projects/armv6/sys/arm/omap/omap4/omap4_intr.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/omap4_intr.c (revision 230362) @@ -0,0 +1,321 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "omap4_if.h" + +/* + * There are a number of ways that interrupt handling is implemented in + * the various ARM platforms, the PXA has the neatest way, it creates another + * device driver that handles everything. However IMO this is rather heavy- + * weight for playing with IRQs which should be quite fast ... so I've + * gone for something similar to the IXP425, which just directly plays with + * registers. This assumes that the interrupt control registers are already + * mapped in virtual memory at a fixed virtual address ... simplies. + * + * The OMAP4xxx processors use the ARM Generic Interrupt Controller (GIC), so + * this file/driver isn't really specific to the OMAP4 series of processors it + * is potentially much broader. However I haven't used any other devices with + * a GIC ... I guess if other platforms would like to use this driver it could + * be made more generic (as the name implies ;-) + * + * + */ + +/* GIC Distributor register map */ +#define ARM_GIC_ICDDCR 0x0000 +#define ARM_GIC_ICDICTR 0x0004 +#define ARM_GIC_ICDIIDR 0x0008 +#define ARM_GIC_ICDISR 0x0080 +#define ARM_GIC_ICDISER(n) (0x0100 + ((n) * 4)) +#define ARM_GIC_ICDICER(n) (0x0180 + ((n) * 4)) +#define ARM_GIC_ICDISPR(n) (0x0200 + ((n) * 4)) +#define ARM_GIC_ICDICPR(n) (0x0280 + ((n) * 4)) +#define ARM_GIC_ICDABR(n) (0x0300 + ((n) * 4)) +#define ARM_GIC_ICDIPR(n) (0x0400 + ((n) * 4)) +#define ARM_GIC_ICDIPTR(n) (0x0800 + ((n) * 4)) +#define ARM_GIC_ICDICFR(n) (0x0C00 + ((n) * 4)) +#define ARM_GIC_ICDSGIR 0x0F00 + +/* GIC CPU/Processor register map */ +#define ARM_GIC_ICCICR 0x0000 +#define ARM_GIC_ICCPMR 0x0004 +#define ARM_GIC_ICCBPR 0x0008 +#define ARM_GIC_ICCIAR 0x000C +#define ARM_GIC_ICCEOIR 0x0010 +#define ARM_GIC_ICCRPR 0x0014 +#define ARM_GIC_ICCHPIR 0x0018 +#define ARM_GIC_ICCABPR 0x001C +#define ARM_GIC_ICCIIDR 0x00FC + +static device_t omap4_dev; + +/** + * omap4_mask_all_intr - masks all interrupts + * + * Called during initialisation to ensure all interrupts are masked before + * globally enabling interrupts. Should only be used at startup time. + * + * RETURNS: + * nothing + */ +void +omap4_mask_all_intr(void) +{ + unsigned int i = 0; + + OMAP4_GIC_DIST_WRITE(omap4_dev, ARM_GIC_ICDICER(i), 0xFFFFFFFF); +} + +/** + * omap4_setup_gic_distributor - configures and enables the distributor part + * of the generic interrupt controller (GIC). + * + * Enables and configures the distributor part of the GIC by programming the + * interrupt priorities and target CPU's. It also ensures the enable bit is + * set at the end of the process. + * + * RETURNS: + * nothing + */ +int +omap4_setup_intr_controller(device_t dev, + const struct omap4_intr_conf *irqs) +{ + u_int oldirqstate; + uint32_t reg_off, bit_off; + uint32_t icdicpr, icdiptr, icdictr; + uint32_t nirqs, i; + + omap4_dev = dev; + + /* Disable interrupts while configuring the controller */ + oldirqstate = disable_interrupts(I32_bit); + + /* Disable interrupt distribution while we are doing the work */ + OMAP4_GIC_DIST_WRITE(omap4_dev, ARM_GIC_ICDDCR, 0x00); + + /* Get the number of interrupts */ + icdictr = OMAP4_GIC_DIST_READ(omap4_dev, ARM_GIC_ICDICTR); + nirqs = 32 * ((icdictr & 0x1f) + 1); + + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32; i < nirqs; i += 32) { + OMAP4_GIC_DIST_WRITE(omap4_dev, + ARM_GIC_ICDICFR(i >> 5), 0x00000000); + } + + /* Disable all interrupts. */ + for (i = 32; i < nirqs; i += 32) { + OMAP4_GIC_DIST_WRITE(omap4_dev, + ARM_GIC_ICDICER(i >> 5), 0xffffffff); + } + + /* Program the interrupt priorites and target CPU(s) */ + for (; irqs->num != -1; irqs++) { + reg_off = (irqs->num >> 2); + bit_off = (irqs->num & 0x3) << 3; + + /* Read the register, mask out the priority bits and then or in */ + icdicpr = OMAP4_GIC_DIST_READ(omap4_dev, + ARM_GIC_ICDICPR(reg_off)); + + icdicpr &= ~(0xFFUL << bit_off); + icdicpr |= ((irqs->priority & 0xFF) << bit_off); + + OMAP4_GIC_DIST_WRITE(omap4_dev, + ARM_GIC_ICDICPR(reg_off), icdicpr); + + /* Read the register, mask out the target cpu bits and then or in */ + icdiptr = OMAP4_GIC_DIST_READ(omap4_dev, + ARM_GIC_ICDIPTR(reg_off)); + + icdiptr &= ~(0xFFUL << bit_off); + icdiptr |= ((irqs->target_cpu & 0xFF) << bit_off); + + OMAP4_GIC_DIST_WRITE(omap4_dev, + ARM_GIC_ICDIPTR(reg_off), icdiptr); + } + + /* Enable interrupt distribution */ + OMAP4_GIC_DIST_WRITE(omap4_dev, ARM_GIC_ICDDCR, 0x01); + + /* Re-enable interrupts */ + restore_interrupts(oldirqstate); + + return (0); +} + +/** + * omap4_setup_gic_cpu - configures and enables the per-CPU part of the generic + * interrupt controller (GIC). + * + * Enables and configures the per-CPU part of the GIC by enabling interrupt + * routing and setting the default interrupt priority filter. + * + * RETURNS: + * nothing + */ +int +omap4_setup_gic_cpu(unsigned int prio_mask) +{ + uint32_t dcr; + uint32_t ictr; + uint32_t iidr; + + if (omap4_dev == NULL) + panic("omap4 devices is not set before calling omap4_setup_gic_cpu"); + + dcr = OMAP4_GIC_CPU_READ(omap4_dev, ARM_GIC_ICCICR); + ictr = OMAP4_GIC_CPU_READ(omap4_dev, ARM_GIC_ICCPMR); + iidr = OMAP4_GIC_CPU_READ(omap4_dev, ARM_GIC_ICCBPR); + + /* Disable interrupt to this CPU while we are doing the work */ + OMAP4_GIC_DIST_WRITE(omap4_dev, ARM_GIC_ICCICR, 0x00); + + /* Enable interrupt to this CPU */ + OMAP4_GIC_DIST_WRITE(omap4_dev, ARM_GIC_ICCICR, 0x01); + + return (0); +} + +/** + * omap3_post_filter_intr - called after the IRQ has been filtered + * @arg: the IRQ number + * + * Called after the interrupt handler has done it's stuff, can be used to + * clean up interrupts that haven't been handled properly. + * + * + * RETURNS: + * nothing + */ +void +omap4_post_filter_intr(void *arg) +{ + /* uintptr_t irq = (uintptr_t) arg; */ + + /* data synchronization barrier */ + cpu_drain_writebuf(); +} + +/** + * arm_mask_irq - masks an IRQ (disables it) + * @nb: the number of the IRQ to mask (disable) + * + * Disables the interrupt at the HW level. + * + * + * RETURNS: + * nothing + */ +void +arm_mask_irq(uintptr_t nb) +{ + /* Write the bit corresponding to the IRQ into the "Clear-Enable Register" */ + OMAP4_GIC_DIST_WRITE(omap4_dev, ARM_GIC_ICDICER(nb >> 5), + (1UL << (nb & 0x1F))); +} + +/** + * arm_unmask_irq - unmasks an IRQ (enables it) + * @nb: the number of the IRQ to unmask (enable) + * + * Enables the interrupt at the HW level. + * + * + * RETURNS: + * nothing + */ +void +arm_unmask_irq(uintptr_t nb) +{ + /* Write the bit corresponding to the IRQ into the "Set-Enable Register" */ + OMAP4_GIC_DIST_WRITE(omap4_dev, ARM_GIC_ICDISER(nb >> 5), + (1UL << (nb & 0x1F))); +} + +/** + * arm_get_next_irq - gets the next tripped interrupt + * @last_irq: the number of the last IRQ processed + * + * This function gets called when an interrupt is tripped, it is initially + * passed -1 in the last_irq argument and is suppose to return the IRQ number. + * The following is psuedo-code for how this is implemented in the core: + * + * irq_handler() + * { + * i = -1; + * while((i = arm_get_next_irq(i)) != -1) + * process_irq(i); + * } + * + * + * RETURNS: + * Returns the IRQ number or -1 if a spurious interrupt was detected + */ +int +arm_get_next_irq(int last_irq) +{ + uint32_t active_irq; + + /* clean-up the last IRQ */ + if (last_irq != -1) { + + /* write the last IRQ number to the end of interrupt register */ + OMAP4_GIC_CPU_WRITE(omap4_dev, ARM_GIC_ICCEOIR, last_irq); + } + + /* Get the next active interrupt */ + active_irq = OMAP4_GIC_CPU_READ(omap4_dev, ARM_GIC_ICCIAR); + active_irq &= 0x3FF; + + /* Check for spurious interrupt */ + if (active_irq == 0x3FF) { + if (last_irq == -1) + printf("Spurious interrupt detected [0x%08x]\n", active_irq); + return -1; + } + + /* Return the new IRQ */ + return active_irq; +} Index: projects/armv6/sys/arm/omap/omap4/omap4_prcm_clks.c =================================================================== --- projects/armv6/sys/arm/omap/omap4/omap4_prcm_clks.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/omap4_prcm_clks.c (revision 230362) @@ -0,0 +1,1476 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "omap_if.h" + +/* + * This file defines the clock configuration for the OMAP4xxx series of + * devices. + * + * How This is Suppose to Work + * =========================== + * - There is a top level omap_prcm module that defines all OMAP SoC drivers + * should use to enable/disable the system clocks regardless of the version + * of OMAP device they are running on. This top level PRCM module is just + * a thin shim to chip specific functions that perform the donkey work of + * configuring the clock - this file is the 'donkey' for OMAP44xx devices. + * + * - The key bit in this file is the omap_clk_devmap array, it's + * used by the omap_prcm driver to determine what clocks are valid and which + * functions to call to manipulate them. + * + * - In essence you just need to define some callbacks for each of the + * clocks and then you're done. + * + * - The other thing that is worth noting is that when the omap_prcm device + * is registered you typically pass in some memory ranges which are the + * SYS_MEMORY resources. These resources are in turn allocated using + * bus_allocate_resources(...) and the resource handles are passed to all + * individual clock callback handlers. + * + * + * + * OMAP4 devices are different from the previous OMAP3 devices in that there + * is no longer a separate functional and interface clock for each module, + * instead there is typically an interface clock that spans many modules. + * + */ + +#define FREQ_96MHZ 96000000 +#define FREQ_64MHZ 64000000 +#define FREQ_48MHZ 48000000 +#define FREQ_32KHZ 32000 + +/** + * We need three memory regions to cover all the clock configuration registers. + * + * PRM Instance - 0x4A30 6000 : 0x4A30 8000 + * CM1 Instance - 0x4A00 4000 : 0x4A00 5000 + * CM2 Instance - 0x4A00 8000 : 0x4A00 A000 + * + */ +#define PRM_INSTANCE_MEM_REGION 0 +#define CM1_INSTANCE_MEM_REGION 1 +#define CM2_INSTANCE_MEM_REGION 2 + +/** + * Address offsets from the PRM memory region to the top level clock control + * registers. + */ +#define CKGEN_PRM_OFFSET 0x00000100UL +#define MPU_PRM_OFFSET 0x00000300UL +#define DSP_PRM_OFFSET 0x00000400UL +#define ABE_PRM_OFFSET 0x00000500UL +#define ALWAYS_ON_PRM_OFFSET 0x00000600UL +#define CORE_PRM_OFFSET 0x00000700UL +#define IVAHD_PRM_OFFSET 0x00000F00UL +#define CAM_PRM_OFFSET 0x00001000UL +#define DSS_PRM_OFFSET 0x00001100UL +#define SGX_PRM_OFFSET 0x00001200UL +#define L3INIT_PRM_OFFSET 0x00001300UL +#define L4PER_PRM_OFFSET 0x00001400UL +#define WKUP_PRM_OFFSET 0x00001700UL +#define WKUP_CM_OFFSET 0x00001800UL +#define EMU_PRM_OFFSET 0x00001900UL +#define EMU_CM_OFFSET 0x00001A00UL +#define DEVICE_PRM_OFFSET 0x00001B00UL +#define INSTR_PRM_OFFSET 0x00001F00UL + + +#define CM_ABE_DSS_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0000UL) +#define CM_L4_WKUP_CLKSELL_OFFSET (CKGEN_PRM_OFFSET + 0x0008UL) +#define CM_ABE_PLL_REF_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x000CUL) +#define CM_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0010UL) + + +/** + * Address offsets from the CM1 memory region to the top level clock control + * registers. + */ +#define CKGEN_CM1_OFFSET 0x00000100UL +#define MPU_CM1_OFFSET 0x00000300UL +#define DSP_CM1_OFFSET 0x00000400UL +#define ABE_CM1_OFFSET 0x00000500UL +#define RESTORE_CM1_OFFSET 0x00000E00UL +#define INSTR_CM1_OFFSET 0x00000F00UL + +#define CM_CLKSEL_DPLL_MPU (CKGEN_CM1_OFFSET + 0x006CUL) + + +/** + * Address offsets from the CM2 memory region to the top level clock control + * registers. + */ +#define INTRCONN_SOCKET_CM2_OFFSET 0x00000000UL +#define CKGEN_CM2_OFFSET 0x00000100UL +#define ALWAYS_ON_CM2_OFFSET 0x00000600UL +#define CORE_CM2_OFFSET 0x00000700UL +#define IVAHD_CM2_OFFSET 0x00000F00UL +#define CAM_CM2_OFFSET 0x00001000UL +#define DSS_CM2_OFFSET 0x00001100UL +#define SGX_CM2_OFFSET 0x00001200UL +#define L3INIT_CM2_OFFSET 0x00001300UL +#define L4PER_CM2_OFFSET 0x00001400UL +#define RESTORE_CM2_OFFSET 0x00001E00UL +#define INSTR_CM2_OFFSET 0x00001F00UL + + + +#define CLKCTRL_MODULEMODE_MASK 0x00000003UL +#define CLKCTRL_MODULEMODE_DISABLE 0x00000000UL +#define CLKCTRL_MODULEMODE_AUTO 0x00000001UL +#define CLKCTRL_MODULEMODE_ENABLE 0x00000001UL + +#define CLKCTRL_IDLEST_MASK 0x00030000UL +#define CLKCTRL_IDLEST_ENABLED 0x00000000UL +#define CLKCTRL_IDLEST_WAKING 0x00010000UL +#define CLKCTRL_IDLEST_IDLE 0x00020000UL +#define CLKCTRL_IDLEST_DISABLED 0x00030000UL + +struct omap4_prcm_softc { + struct resource *sc_mem_res[4]; +}; + +static int omap4_clk_generic_activate(device_t dev, struct omap_clock_dev *clkdev); +static int omap4_clk_generic_deactivate(device_t dev, struct omap_clock_dev *clkdev); +static int omap4_clk_generic_accessible(device_t dev, struct omap_clock_dev *clkdev); +static int omap4_clk_generic_set_source(device_t dev, struct omap_clock_dev *clkdev, clk_src_t clksrc); +static int omap4_clk_generic_get_source_freq(device_t dev, struct omap_clock_dev *clkdev, unsigned int *freq); + +static int omap4_clk_gptimer_set_source(device_t dev, struct omap_clock_dev *clkdev, clk_src_t clksrc); +static int omap4_clk_gptimer_get_source_freq(device_t dev, struct omap_clock_dev *clkdev, unsigned int *freq); + +static int omap4_clk_hsmmc_set_source(device_t dev, struct omap_clock_dev *clkdev, clk_src_t clksrc); +static int omap4_clk_hsmmc_get_source_freq(device_t dev, struct omap_clock_dev *clkdev, unsigned int *freq); + +static int omap4_clk_hsusbhost_set_source(device_t dev, struct omap_clock_dev *clkdev, clk_src_t clksrc); +static int omap4_clk_hsusbhost_activate(device_t dev, struct omap_clock_dev *clkdev); +static int omap4_clk_hsusbhost_deactivate(device_t dev, struct omap_clock_dev *clkdev); +static int omap4_clk_hsusbhost_accessible(device_t dev, struct omap_clock_dev *clkdev); + +static int omap4_clk_get_sysclk_freq(device_t dev, struct omap_clock_dev *clkdev, unsigned int *freq); +static int omap4_clk_get_arm_fclk_freq(device_t dev, struct omap_clock_dev *clkdev, unsigned int *freq); + +/** + * omap_clk_devmap - Array of clock devices available on OMAP4xxx devices + * + * This map only defines which clocks are valid and the callback functions + * for clock activate, deactivate, etc. It is used by the top level omap_prcm + * driver. + * + * The actual details of the clocks (config registers, bit fields, sources, + * etc) are in the private g_omap3_clk_details array below. + * + */ + +#define OMAP4_GENERIC_CLOCK_DEV(i) \ + { .id = (i), \ + .clk_activate = omap4_clk_generic_activate, \ + .clk_deactivate = omap4_clk_generic_deactivate, \ + .clk_set_source = omap4_clk_generic_set_source, \ + .clk_accessible = omap4_clk_generic_accessible, \ + .clk_get_source_freq = omap4_clk_generic_get_source_freq \ + } + +#define OMAP4_GPTIMER_CLOCK_DEV(i) \ + { .id = (i), \ + .clk_activate = omap4_clk_generic_activate, \ + .clk_deactivate = omap4_clk_generic_deactivate, \ + .clk_set_source = omap4_clk_gptimer_set_source, \ + .clk_accessible = omap4_clk_generic_accessible, \ + .clk_get_source_freq = omap4_clk_gptimer_get_source_freq \ + } + +#define OMAP4_HSMMC_CLOCK_DEV(i) \ + { .id = (i), \ + .clk_activate = omap4_clk_generic_activate, \ + .clk_deactivate = omap4_clk_generic_deactivate, \ + .clk_set_source = omap4_clk_hsmmc_set_source, \ + .clk_accessible = omap4_clk_generic_accessible, \ + .clk_get_source_freq = omap4_clk_hsmmc_get_source_freq \ + } + +#define OMAP4_HSUSBHOST_CLOCK_DEV(i) \ + { .id = (i), \ + .clk_activate = omap4_clk_hsusbhost_activate, \ + .clk_deactivate = omap4_clk_hsusbhost_deactivate, \ + .clk_set_source = omap4_clk_hsusbhost_set_source, \ + .clk_accessible = omap4_clk_hsusbhost_accessible, \ + .clk_get_source_freq = NULL \ + } + + +struct omap_clock_dev omap_clk_devmap[] = { + + /* System clocks */ + { .id = SYS_CLK, + .clk_activate = NULL, + .clk_deactivate = NULL, + .clk_set_source = NULL, + .clk_accessible = NULL, + .clk_get_source_freq = omap4_clk_get_sysclk_freq, + }, + /* MPU (ARM) core clocks */ + { .id = MPU_CLK, + .clk_activate = NULL, + .clk_deactivate = NULL, + .clk_set_source = NULL, + .clk_accessible = NULL, + .clk_get_source_freq = omap4_clk_get_arm_fclk_freq, + }, + + + /* UART device clocks */ + OMAP4_GENERIC_CLOCK_DEV(UART1_CLK), + OMAP4_GENERIC_CLOCK_DEV(UART2_CLK), + OMAP4_GENERIC_CLOCK_DEV(UART3_CLK), + OMAP4_GENERIC_CLOCK_DEV(UART4_CLK), + + /* Timer device source clocks */ + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER1_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER2_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER3_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER4_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER5_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER6_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER7_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER8_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER9_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER10_CLK), + OMAP4_GPTIMER_CLOCK_DEV(GPTIMER11_CLK), + + /* MMC device clocks (MMC1 and MMC2 can have different input clocks) */ + OMAP4_HSMMC_CLOCK_DEV(MMC1_CLK), + OMAP4_HSMMC_CLOCK_DEV(MMC2_CLK), + OMAP4_GENERIC_CLOCK_DEV(MMC3_CLK), + OMAP4_GENERIC_CLOCK_DEV(MMC4_CLK), + OMAP4_GENERIC_CLOCK_DEV(MMC5_CLK), + + /* USB HS (high speed TLL, EHCI and OHCI) */ + OMAP4_HSUSBHOST_CLOCK_DEV(USBTLL_CLK), + OMAP4_HSUSBHOST_CLOCK_DEV(USBHSHOST_CLK), + OMAP4_HSUSBHOST_CLOCK_DEV(USBFSHOST_CLK), + OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_PHY_CLK), + OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_PHY_CLK), + OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_UTMI_CLK), + OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_UTMI_CLK), + OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_HSIC_CLK), + OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_HSIC_CLK), + + /* GPIO */ + OMAP4_GENERIC_CLOCK_DEV(GPIO1_CLK), + OMAP4_GENERIC_CLOCK_DEV(GPIO2_CLK), + OMAP4_GENERIC_CLOCK_DEV(GPIO3_CLK), + OMAP4_GENERIC_CLOCK_DEV(GPIO4_CLK), + OMAP4_GENERIC_CLOCK_DEV(GPIO5_CLK), + OMAP4_GENERIC_CLOCK_DEV(GPIO6_CLK), + + /* sDMA */ + OMAP4_GENERIC_CLOCK_DEV(SDMA_CLK), + + { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } +}; + + + + + + +/** + * g_omap4_clk_details - Stores details for all the different clocks supported + * + * Whenever an operation on a clock is being performed (activated, deactivated, + * etc) this array is looked up to find the correct register and bit(s) we + * should be modifying. + * + */ + +struct omap4_clk_details { + clk_ident_t id; + + uint32_t mem_region; + uint32_t clksel_reg; + + int32_t src_freq; + + uint32_t enable_mode; +}; + +#define OMAP4_GENERIC_CLOCK_DETAILS(i, f, m, r, e) \ + { .id = (i), \ + .mem_region = (m), \ + .clksel_reg = (r), \ + .src_freq = (f), \ + .enable_mode = (e), \ + } + +static struct omap4_clk_details g_omap4_clk_details[] = { + + /* UART */ + OMAP4_GENERIC_CLOCK_DETAILS(UART1_CLK, FREQ_48MHZ, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x0140), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(UART2_CLK, FREQ_48MHZ, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x0148), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(UART3_CLK, FREQ_48MHZ, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x0140), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(UART4_CLK, FREQ_48MHZ, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x0148), CLKCTRL_MODULEMODE_ENABLE), + + /* General purpose timers */ + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER1_CLK, -1, PRM_INSTANCE_MEM_REGION, + (WKUP_CM_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER2_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x038), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER3_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER4_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x048), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER5_CLK, -1, CM1_INSTANCE_MEM_REGION, + (ABE_CM1_OFFSET + 0x068), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER6_CLK, -1, CM1_INSTANCE_MEM_REGION, + (ABE_CM1_OFFSET + 0x070), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER7_CLK, -1, CM1_INSTANCE_MEM_REGION, + (ABE_CM1_OFFSET + 0x078), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER8_CLK, -1, CM1_INSTANCE_MEM_REGION, + (ABE_CM1_OFFSET + 0x080), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER9_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x050), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER10_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x028), CLKCTRL_MODULEMODE_ENABLE), + OMAP4_GENERIC_CLOCK_DETAILS(GPTIMER11_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x030), CLKCTRL_MODULEMODE_ENABLE), + + /* HSMMC (MMC1 and MMC2 can have different input clocks) */ + OMAP4_GENERIC_CLOCK_DETAILS(MMC1_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L3INIT_CM2_OFFSET + 0x028), /*CLKCTRL_MODULEMODE_ENABLE*/2), + OMAP4_GENERIC_CLOCK_DETAILS(MMC2_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L3INIT_CM2_OFFSET + 0x030), /*CLKCTRL_MODULEMODE_ENABLE*/2), + OMAP4_GENERIC_CLOCK_DETAILS(MMC3_CLK, FREQ_48MHZ, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x120), /*CLKCTRL_MODULEMODE_ENABLE*/2), + OMAP4_GENERIC_CLOCK_DETAILS(MMC4_CLK, FREQ_48MHZ, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x128), /*CLKCTRL_MODULEMODE_ENABLE*/2), + OMAP4_GENERIC_CLOCK_DETAILS(MMC5_CLK, FREQ_48MHZ, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x160), /*CLKCTRL_MODULEMODE_ENABLE*/1), + + /* GPIO modules */ + OMAP4_GENERIC_CLOCK_DETAILS(GPIO1_CLK, -1, PRM_INSTANCE_MEM_REGION, + (WKUP_CM_OFFSET + 0x038), CLKCTRL_MODULEMODE_AUTO), + OMAP4_GENERIC_CLOCK_DETAILS(GPIO2_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x060), CLKCTRL_MODULEMODE_AUTO), + OMAP4_GENERIC_CLOCK_DETAILS(GPIO3_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x068), CLKCTRL_MODULEMODE_AUTO), + OMAP4_GENERIC_CLOCK_DETAILS(GPIO4_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x070), CLKCTRL_MODULEMODE_AUTO), + OMAP4_GENERIC_CLOCK_DETAILS(GPIO5_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x078), CLKCTRL_MODULEMODE_AUTO), + OMAP4_GENERIC_CLOCK_DETAILS(GPIO6_CLK, -1, CM2_INSTANCE_MEM_REGION, + (L4PER_CM2_OFFSET + 0x080), CLKCTRL_MODULEMODE_AUTO), + + /* sDMA block */ + OMAP4_GENERIC_CLOCK_DETAILS(SDMA_CLK, -1, CM2_INSTANCE_MEM_REGION, + (CORE_CM2_OFFSET + 0x320), CLKCTRL_MODULEMODE_AUTO), + + { INVALID_CLK_IDENT, 0, 0, 0, 0 }, +}; + + + + + + +/** + * MAX_MODULE_ENABLE_WAIT - the number of loops to wait for the module to come + * alive. + * + */ +#define MAX_MODULE_ENABLE_WAIT 1000 + + +/** + * ARRAY_SIZE - Macro to return the number of elements in a static const array. + * + */ +#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) + + +/** + * omap4_clk_details - writes a 32-bit value to one of the timer registers + * @timer: Timer device context + * @off: The offset of a register from the timer register address range + * @val: The value to write into the register + * + * + * RETURNS: + * nothing + */ +static struct omap4_clk_details* +omap4_clk_details(clk_ident_t id) +{ + struct omap4_clk_details *walker; + + for (walker = g_omap4_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { + if (id == walker->id) + return (walker); + } + + return NULL; +} + + + + +/** + * omap4_clk_generic_activate - checks if a module is accessible + * @module: identifier for the module to check, see omap3_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1 + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a positive error code on failure. + */ +static int +omap4_clk_generic_activate(device_t dev, struct omap_clock_dev *clkdev) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); + struct resource* clk_mem_res = sc->sc_mem_res[clk_details->mem_region]; + uint32_t clksel; + unsigned int i; + + if (clk_details == NULL) + return (ENXIO); + if (clk_mem_res == NULL) + return (EINVAL); + + + + /* All the 'generic' clocks have a CLKCTRL register which is more or less + * generic - the have at least two fielda called MODULEMODE and IDLEST. + */ + clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); + clksel &= ~CLKCTRL_MODULEMODE_MASK; + clksel |= clk_details->enable_mode; + bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); + + + /* Now poll on the IDLEST register to tell us if the module has come up. + * TODO: We need to take into account the parent clocks. + */ + + /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ + for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { + clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); + if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) + break; + } + + /* Check the enabled state */ + if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { + printf("Error: failed to enable module with clock %d\n", clkdev->id); + printf("Error: 0x%08x => 0x%08x\n", clk_details->clksel_reg, clksel); + return (ETIMEDOUT); + } + + return (0); +} + + + +/** + * omap4_clk_generic_deactivate - checks if a module is accessible + * @module: identifier for the module to check, see omap3_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1 + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a positive error code on failure. + */ +static int +omap4_clk_generic_deactivate(device_t dev, struct omap_clock_dev *clkdev) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); + struct resource* clk_mem_res = sc->sc_mem_res[clk_details->mem_region]; + uint32_t clksel; + + if (clk_details == NULL) + return (ENXIO); + if (clk_mem_res == NULL) + return (EINVAL); + + + /* All the 'generic' clocks have a CLKCTRL register which is more or less + * generic - the have at least two fielda called MODULEMODE and IDLEST. + */ + clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); + clksel &= ~CLKCTRL_MODULEMODE_MASK; + clksel |= CLKCTRL_MODULEMODE_DISABLE; + bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); + + return (0); +} + + +/** + * omap4_clk_generic_set_source - checks if a module is accessible + * @module: identifier for the module to check, see omap3_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1 + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a positive error code on failure. + */ +static int +omap4_clk_generic_set_source(device_t dev, struct omap_clock_dev *clkdev, + clk_src_t clksrc) +{ + + + return (0); +} + +/** + * omap4_clk_generic_accessible - checks if a module is accessible + * @module: identifier for the module to check, see omap3_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1 + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a negative error code on failure. + */ +static int +omap4_clk_generic_accessible(device_t dev, struct omap_clock_dev *clkdev) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); + struct resource* clk_mem_res = sc->sc_mem_res[clk_details->mem_region]; + uint32_t clksel; + + if (clk_details == NULL) + return (ENXIO); + if (clk_mem_res == NULL) + return (EINVAL); + + clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); + + /* Check the enabled state */ + if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) + return (0); + + return (1); +} + + +/** + * omap4_clk_generic_get_source_freq - checks if a module is accessible + * @module: identifier for the module to check, see omap3_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1 + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a negative error code on failure. + */ +static int +omap4_clk_generic_get_source_freq(device_t dev, struct omap_clock_dev *clkdev, + unsigned int *freq + ) +{ + struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); +#if 0 + uint32_t clksel; + unsigned int src_freq; +#endif + + if (clk_details == NULL) + return (ENXIO); + + /* Simply return the stored frequency */ + if (freq) + *freq = (unsigned int)clk_details->src_freq; + + return (0); +} + + +/** + * omap4_clk_gptimer_set_source - checks if a module is accessible + * @module: identifier for the module to check, see omap3_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1 + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a negative error code on failure. + */ +static int +omap4_clk_gptimer_set_source(device_t dev, struct omap_clock_dev *clkdev, + clk_src_t clksrc) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); + struct resource* clk_mem_res = sc->sc_mem_res[clk_details->mem_region]; +#if 0 + uint32_t clksel; + unsigned int src_freq; +#endif + + if (clk_details == NULL) + return (ENXIO); + if (clk_mem_res == NULL) + return (EINVAL); + + /* TODO: Implement */ + + return (0); +} + +/** + * omap4_clk_gptimer_get_source_freq - checks if a module is accessible + * @module: identifier for the module to check, see omap3_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1 + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a negative error code on failure. + */ +static int +omap4_clk_gptimer_get_source_freq(device_t dev, struct omap_clock_dev *clkdev, + unsigned int *freq + ) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); + struct resource* clk_mem_res = sc->sc_mem_res[clk_details->mem_region]; + uint32_t clksel; + unsigned int src_freq; + + if (clk_details == NULL) + return (ENXIO); + if (clk_mem_res == NULL) + return (EINVAL); + + /* Need to read the CLKSEL field to determine the clock source */ + clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); + if (clksel & (0x1UL << 24)) + src_freq = FREQ_32KHZ; + else + omap4_clk_get_sysclk_freq(dev, NULL, &src_freq); + + /* Return the frequency */ + if (freq) + *freq = src_freq; + + return (0); +} + + + +/** + * omap4_clk_hsmmc_set_source - sets the source clock (freq) + * @clkdev: pointer to the clockdev structure (id field will contain clock id) + * + * The MMC 1 and 2 clocks can be source from either a 64MHz or 96MHz clock. + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a negative error code on failure. + */ +static int +omap4_clk_hsmmc_set_source(device_t dev, struct omap_clock_dev *clkdev, + clk_src_t clksrc) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); + struct resource* clk_mem_res = sc->sc_mem_res[clk_details->mem_region]; + uint32_t clksel; + + if (clk_details == NULL) + return (ENXIO); + if (clk_mem_res == NULL) + return (EINVAL); + + /* For MMC modules 3, 4 & 5 you can't change the freq, it's always 48MHz */ + if ((clkdev->id == MMC3_CLK) || (clkdev->id == MMC4_CLK) || + (clkdev->id == MMC5_CLK)) { + if (clksrc != F48MHZ_CLK) + return (EINVAL); + return 0; + } + + + clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); + + /* Bit 24 is set if 96MHz clock or cleared for 64MHz clock */ + if (clksrc == F64MHZ_CLK) + clksel &= ~(0x1UL << 24); + else if (clksrc == F96MHZ_CLK) + clksel |= (0x1UL << 24); + else + return (EINVAL); + + bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); + + return (0); +} + +/** + * omap4_clk_hsmmc_get_source_freq - checks if a module is accessible + * @clkdev: pointer to the clockdev structure (id field will contain clock id) + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a negative error code on failure. + */ +static int +omap4_clk_hsmmc_get_source_freq(device_t dev, struct omap_clock_dev *clkdev, + unsigned int *freq + ) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); + struct resource* clk_mem_res = sc->sc_mem_res[clk_details->mem_region]; + uint32_t clksel; + unsigned int src_freq; + + if (clk_details == NULL) + return (ENXIO); + if (clk_mem_res == NULL) + return (EINVAL); + + switch (clkdev->id) { + case MMC1_CLK: + case MMC2_CLK: + /* Need to read the CLKSEL field to determine the clock source */ + clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); + if (clksel & (0x1UL << 24)) + src_freq = FREQ_96MHZ; + else + src_freq = FREQ_64MHZ; + break; + case MMC3_CLK: + case MMC4_CLK: + case MMC5_CLK: + src_freq = FREQ_48MHZ; + break; + default: + return (EINVAL); + } + + /* Return the frequency */ + if (freq) + *freq = src_freq; + + return (0); +} + + + +/** + * omap4_clk_get_sysclk_freq - gets the sysclk frequency + * @sc: pointer to the clk module/device context + * + * Read the clocking information from the power-control/boot-strap registers, + * and stored in two global variables. + * + * RETURNS: + * nothing, values are saved in global variables + */ +static int +omap4_clk_get_sysclk_freq(device_t dev, struct omap_clock_dev *clkdev, + unsigned int *freq) +{ + uint32_t clksel; + uint32_t sysclk; + struct omap4_prcm_softc *sc = device_get_softc(dev); + + /* Read the input clock freq from the configuration register (CM_SYS_CLKSEL) */ + clksel = bus_read_4(sc->sc_mem_res[PRM_INSTANCE_MEM_REGION], CM_SYS_CLKSEL_OFFSET); + switch (clksel & 0x7) { + case 0x1: + /* 12Mhz */ + sysclk = 12000000; + break; + case 0x3: + /* 16.8Mhz */ + sysclk = 16800000; + break; + case 0x4: + /* 19.2Mhz */ + sysclk = 19200000; + break; + case 0x5: + /* 26Mhz */ + sysclk = 26000000; + break; + case 0x7: + /* 38.4Mhz */ + sysclk = 38400000; + break; + default: + panic("%s: Invalid clock freq", __func__); + } + + /* Return the value */ + if (freq) + *freq = sysclk; + + return (0); +} + + +/** + * omap4_clk_get_arm_fclk_freq - gets the MPU clock frequency + * @clkdev: ignored + * @freq: pointer which upon return will contain the freq in hz + * @mem_res: array of allocated memory resources + * + * Reads the frequency setting information registers and returns the value + * in the freq variable. + * + * RETURNS: + * returns 0 on success, a positive error code on failure. + */ +static int +omap4_clk_get_arm_fclk_freq(device_t dev, struct omap_clock_dev *clkdev, + unsigned int *freq) +{ + uint32_t clksel; + uint32_t pll_mult, pll_div; + uint32_t mpuclk, sysclk; + struct omap4_prcm_softc *sc = device_get_softc(dev); + + /* Read the clksel register which contains the DPLL multiple and divide + * values. These are applied to the sysclk. + */ + clksel = bus_read_4(sc->sc_mem_res[CM1_INSTANCE_MEM_REGION], CM_CLKSEL_DPLL_MPU); + + pll_mult = ((clksel >> 8) & 0x7ff); + pll_div = (clksel & 0x7f) + 1; + + + /* Get the system clock freq */ + omap4_clk_get_sysclk_freq(dev, NULL, &sysclk); + + + /* Calculate the MPU freq */ + mpuclk = (sysclk * pll_mult) / pll_div; + + /* Return the value */ + if (freq) + *freq = mpuclk; + + return (0); +} + + + +/** + * omap4_clk_hsusbhost_activate - activates the USB clocks for the given module + * @clkdev: pointer to the clock device structure. + * @mem_res: array of memory resouces allocated by the top level PRCM driver. + * + * The USB clocking setup seems to be a bit more tricky than the other modules, + * to start with the clocking diagram for the HS host module shows 13 different + * clocks. So to try and make it easier to follow the clocking activation + * and deactivation is handled in it's own set of callbacks. + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a positive error code on failure. + */ + +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m7; +}; +/* USB parameters */ +struct dpll_param usb_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC + {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, +#else + {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, +#endif +}; +static int +omap4_clk_hsusbhost_activate(device_t dev, struct omap_clock_dev *clkdev) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct resource* clk_mem_res; + uint32_t clksel_reg_off; + uint32_t clksel; + unsigned int i; +#if 0 + struct dpll_param *dpll_param; + + + + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = 0x104; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel &= ~CLKCTRL_MODULEMODE_MASK; + clksel = 1; + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = 0x180; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel &= ~0x7; + clksel |= 4; + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + clksel_reg_off = 0x184; + while (bus_read_4(clk_mem_res, clksel_reg_off) & 1) { + printf("GOT %x\n", bus_read_4(clk_mem_res, clksel_reg_off)); + } + + clksel_reg_off = 0x188; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel &= ~0x7; + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + + i = *(unsigned int *)(OMAP44XX_L4_CORE_VBASE + 0x306110); + printf("got %d\n", i); + dpll_param = &usb_dpll_param[i - 1]; + clksel_reg_off = 0x18c; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel = (dpll_param->m << 8) | (dpll_param->n); + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + clksel_reg_off = 0x190; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel = 0x100 | (dpll_param->m2) | (1 << 8); + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = 0x1b4; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel |= (1 << 8); + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + clksel_reg_off = 0x180; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel &= ~0x7; + clksel |= 7; + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + printf("YEAH YEAH\n"); + clksel_reg_off = 0x184; + while (!(bus_read_4(clk_mem_res, clksel_reg_off) & 1)) { + printf("pouic pouic %x\n", bus_read_4(clk_mem_res, clksel_reg_off) & 1); + } + + clksel_reg_off = 0x1b4; + clksel = 0x100; + bus_write_4(clk_mem_res, clksel_reg_off, clksel); +#if 0 + bus_write_4(clk_mem_res, L3INIT_CM2_OFFSET + 0x38, 1); + bus_write_4(clk_mem_res, L3INIT_CM2_OFFSET + 0x40, 2); + bus_write_4(clk_mem_res, L3INIT_CM2_OFFSET + 0x58, 2); + bus_write_4(clk_mem_res, L3INIT_CM2_OFFSET + 0x60, 1); + bus_write_4(clk_mem_res, L3INIT_CM2_OFFSET + 0x68, 1); + bus_write_4(clk_mem_res, L3INIT_CM2_OFFSET + 0xd0, 2); + bus_write_4(clk_mem_res, L3INIT_CM2_OFFSET + 0xe0, 0x301); +#endif +#endif + + switch (clkdev->id) { + case USBTLL_CLK: + /* For the USBTLL module we need to enable the following clocks: + * - INIT_L4_ICLK (will be enabled by bootloader) + * - TLL_CH0_FCLK + * - TLL_CH1_FCLK + */ + + /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; + + /* Enable the module and also enable the optional func clocks for + * channels 0 & 1 (is this needed ?) + */ + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel &= ~CLKCTRL_MODULEMODE_MASK; + clksel |= CLKCTRL_MODULEMODE_ENABLE; + + clksel |= (0x1 << 8); /* USB-HOST optional clock: USB_CH0_CLK */ + clksel |= (0x1 << 9); /* USB-HOST optional clock: USB_CH1_CLK */ + break; + + case USBHSHOST_CLK: + case USBP1_PHY_CLK: + case USBP2_PHY_CLK: + case USBP1_UTMI_CLK: + case USBP2_UTMI_CLK: + case USBP1_HSIC_CLK: + case USBP2_HSIC_CLK: + /* For the USB HS HOST module we need to enable the following clocks: + * - INIT_L4_ICLK (will be enabled by bootloader) + * - INIT_L3_ICLK (will be enabled by bootloader) + * - INIT_48MC_FCLK + * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) + * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) + * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) + * - HSIC_P1_60 (HSIC only, create a new clock for that ?) + * - HSIC_P1_480 (HSIC only, create a new clock for that ?) + * - HSIC_P2_60 (HSIC only, create a new clock for that ?) + * - HSIC_P2_480 (HSIC only, create a new clock for that ?) + */ + + /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + /* Enable the module and also enable the optional func clocks */ + if (clkdev->id == USBHSHOST_CLK) { + clksel &= ~CLKCTRL_MODULEMODE_MASK; + clksel |= /*CLKCTRL_MODULEMODE_ENABLE*/2; + + clksel |= (0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ + } + + else if (clkdev->id == USBP1_UTMI_CLK) + clksel |= (0x1 << 8); /* UTMI_P1_CLK */ + else if (clkdev->id == USBP2_UTMI_CLK) + clksel |= (0x1 << 9); /* UTMI_P2_CLK */ + + else if (clkdev->id == USBP1_HSIC_CLK) + clksel |= (0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ + else if (clkdev->id == USBP2_HSIC_CLK) + clksel |= (0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ + + break; + + default: + return (EINVAL); + } + + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + + + /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ + for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) + break; + } + + /* Check the enabled state */ + if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { + printf("Error: HERE failed to enable module with clock %d\n", clkdev->id); + printf("Error: 0x%08x => 0x%08x\n", clksel_reg_off, clksel); + return (ETIMEDOUT); + } + + + return (0); +} + + + +/** + * omap4_clk_generic_deactivate - checks if a module is accessible + * @clkdev: pointer to the clock device structure. + * @mem_res: array of memory resouces allocated by the top level PRCM driver. + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 on success or a positive error code on failure. + */ +static int +omap4_clk_hsusbhost_deactivate(device_t dev, struct omap_clock_dev *clkdev) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct resource* clk_mem_res; + uint32_t clksel_reg_off; + uint32_t clksel; + + switch (clkdev->id) { + case USBTLL_CLK: + /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; + + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + clksel &= ~CLKCTRL_MODULEMODE_MASK; + clksel |= CLKCTRL_MODULEMODE_DISABLE; + break; + + case USBHSHOST_CLK: + case USBP1_PHY_CLK: + case USBP2_PHY_CLK: + case USBP1_UTMI_CLK: + case USBP2_UTMI_CLK: + case USBP1_HSIC_CLK: + case USBP2_HSIC_CLK: + /* For the USB HS HOST module we need to enable the following clocks: + * - INIT_L4_ICLK (will be enabled by bootloader) + * - INIT_L3_ICLK (will be enabled by bootloader) + * - INIT_48MC_FCLK + * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) + * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) + * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) + * - HSIC_P1_60 (HSIC only, create a new clock for that ?) + * - HSIC_P1_480 (HSIC only, create a new clock for that ?) + * - HSIC_P2_60 (HSIC only, create a new clock for that ?) + * - HSIC_P2_480 (HSIC only, create a new clock for that ?) + */ + + /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + + /* Enable the module and also enable the optional func clocks */ + if (clkdev->id == USBHSHOST_CLK) { + clksel &= ~CLKCTRL_MODULEMODE_MASK; + clksel |= CLKCTRL_MODULEMODE_DISABLE; + + clksel &= ~(0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ + } + + else if (clkdev->id == USBP1_UTMI_CLK) + clksel &= ~(0x1 << 8); /* UTMI_P1_CLK */ + else if (clkdev->id == USBP2_UTMI_CLK) + clksel &= ~(0x1 << 9); /* UTMI_P2_CLK */ + + else if (clkdev->id == USBP1_HSIC_CLK) + clksel &= ~(0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ + else if (clkdev->id == USBP2_HSIC_CLK) + clksel &= ~(0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ + + break; + + default: + return (EINVAL); + } + + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + + return (0); +} + + +/** + * omap4_clk_hsusbhost_accessible - checks if a module is accessible + * @clkdev: pointer to the clock device structure. + * @mem_res: array of memory resouces allocated by the top level PRCM driver. + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 if module is not enable, 1 if module is enabled or a negative + * error code on failure. + */ +static int +omap4_clk_hsusbhost_accessible(device_t dev, struct omap_clock_dev *clkdev) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct resource* clk_mem_res; + uint32_t clksel_reg_off; + uint32_t clksel; + + if (clkdev->id == USBTLL_CLK) { + /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; + } + else if (clkdev->id == USBHSHOST_CLK) { + /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; + } + else { + return (-EINVAL); + } + + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + + /* Check the enabled state */ + if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) + return (0); + + return (1); +} + +/** + * omap4_clk_hsusbhost_set_source - sets the source clocks + * @clkdev: pointer to the clock device structure. + * @clksrc: the clock source ID for the given clock. + * @mem_res: array of memory resouces allocated by the top level PRCM driver. + * + * + * + * LOCKING: + * Inherits the locks from the omap_prcm driver, no internal locking. + * + * RETURNS: + * Returns 0 if sucessful otherwise a negative error code on failure. + */ +static int +omap4_clk_hsusbhost_set_source(device_t dev, struct omap_clock_dev *clkdev, + clk_src_t clksrc) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + struct resource* clk_mem_res; + uint32_t clksel_reg_off; + uint32_t clksel; + unsigned int bit; + + if (clkdev->id == USBP1_PHY_CLK) + bit = 24; + else if (clkdev->id != USBP2_PHY_CLK) + bit = 25; + else + return (-EINVAL); + + /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ + clk_mem_res = sc->sc_mem_res[CM2_INSTANCE_MEM_REGION]; + clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; + clksel = bus_read_4(clk_mem_res, clksel_reg_off); + + /* Set the clock source to either external or internal */ + if (clksrc == EXT_CLK) + clksel |= (0x1 << bit); + else + clksel &= ~(0x1 << bit); + + bus_write_4(clk_mem_res, clksel_reg_off, clksel); + + return (0); +} + +#define PRM_RSTCTRL 0x1b00 +#define PRM_RSTCTRL_RESET 0x2 + +static void +omap4_prcm_reset(device_t dev) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + bus_write_4(sc->sc_mem_res[0], PRM_RSTCTRL, + bus_read_4(sc->sc_mem_res[0], PRM_RSTCTRL) | PRM_RSTCTRL_RESET); + bus_read_4(sc->sc_mem_res[0], PRM_RSTCTRL); +} + +static void +omap4_prcm_identify(driver_t *driver, device_t parent) +{ + + BUS_ADD_CHILD(parent, 0, "omap4_prcm", 0); +} + +/** + * omap4_prcm_probe - probe function for the driver + * @dev: prcm device handle + * + * Simply sets the name of the driver module. + * + * LOCKING: + * None + * + * RETURNS: + * Always returns 0 + */ +static int +omap4_prcm_probe(device_t dev) +{ + device_set_desc(dev, "TI OMAP Power, Reset and Clock Management"); + bus_set_resource(dev, SYS_RES_MEMORY, 0, 0x4A306000, 0x2000); + bus_set_resource(dev, SYS_RES_MEMORY, 1, 0x4A004000, 0x1000); + bus_set_resource(dev, SYS_RES_MEMORY, 2, 0x4A008000, 0x2000); + return (0); +} + +/** + * omap_prcm_attach - attach function for the driver + * @dev: prcm device handle + * + * Allocates and sets up the driver context, this simply entails creating a + * bus mappings for the PRCM register set. + * + * LOCKING: + * None + * + * RETURNS: + * Always returns 0 + */ +static int +omap4_prcm_attach(device_t dev) +{ + struct omap4_prcm_softc *sc = device_get_softc(dev); + int rid; + + rid = 0; + /* Attempt to get the memory resource(s) */ + sc->sc_mem_res[PRM_INSTANCE_MEM_REGION] = + bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, + 0x4A306000, + 0x4A306000 + 0x2000, + 0x2000, RF_ACTIVE); + + if (sc->sc_mem_res[PRM_INSTANCE_MEM_REGION] == NULL) { + device_printf(dev, "failed to allocate resource for PRM region\n"); + return (ENXIO); + } + + rid = 1; + sc->sc_mem_res[CM1_INSTANCE_MEM_REGION] = + bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, + 0x4A004000, + 0x4A004000 + 0x1000, + 0x1000, RF_ACTIVE); + + if (sc->sc_mem_res[CM1_INSTANCE_MEM_REGION] == NULL) { + device_printf(dev, "failed to allocate resource for CM1 region\n"); + return (ENXIO); + } + + rid = 2; + sc->sc_mem_res[CM2_INSTANCE_MEM_REGION] = + bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, + 0x4A008000, + 0x4A008000 + 0x8000, + 0x8000, RF_ACTIVE); + + if (sc->sc_mem_res[CM2_INSTANCE_MEM_REGION] == NULL) { + device_printf(dev, "failed to allocate resource for CM2 region\n"); + return (ENXIO); + } + + /* Initialize top-level OMAP PRCM API */ + omap_prcm_init(dev); + + return (0); +} + +static device_method_t omap4_prcm_methods[] = { + DEVMETHOD(device_identify, omap4_prcm_identify), + DEVMETHOD(device_probe, omap4_prcm_probe), + DEVMETHOD(device_attach, omap4_prcm_attach), + + DEVMETHOD(omap_prcm_reset, omap4_prcm_reset), + {0, 0}, +}; + +static driver_t omap4_prcm_driver = { + "omap4_prcm", + omap4_prcm_methods, + sizeof(struct omap4_prcm_softc), +}; + +static devclass_t omap4_prcm_devclass; + +DRIVER_MODULE(omap4_prcm, omap, omap4_prcm_driver, omap4_prcm_devclass, 0, 0); +MODULE_VERSION(omap4_prcm, 1); Index: projects/armv6/sys/arm/omap/omap4/omap4_scm_padconf.c =================================================================== --- projects/armv6/sys/arm/omap/omap4/omap4_scm_padconf.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/omap4_scm_padconf.c (revision 230362) @@ -0,0 +1,295 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +/* + * This file defines the pin mux configuration for the OMAP4xxx series of + * devices. + * + * How This is Suppose to Work + * =========================== + * - There is a top level omap_scm module (System Control Module) that is + * the interface for all omap drivers, which can use it to change the mux + * settings for individual pins. (That said, typically the pin mux settings + * are set to defaults by the 'hints' and then not altered by the driver). + * + * - For this to work the top level driver needs all the pin info, and hence + * this is where this file comes in. Here we define all the pin information + * that is supplied to the top level driver. + * + */ + +#define _OMAP_PINDEF(r, b, gp, gm, m0, m1, m2, m3, m4, m5, m6, m7) \ + { .reg_off = r, \ + .gpio_pin = gp, \ + .gpio_mode = gm, \ + .ballname = b, \ + .muxmodes[0] = m0, \ + .muxmodes[1] = m1, \ + .muxmodes[2] = m2, \ + .muxmodes[3] = m3, \ + .muxmodes[4] = m4, \ + .muxmodes[5] = m5, \ + .muxmodes[6] = m6, \ + .muxmodes[7] = m7, \ + } + +/* + * Table 18-10, p. 3470 + */ +const struct omap_scm_padconf omap_padconf_devmap[] = { + _OMAP_PINDEF(0x0040, "c12", 0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0042, "d12", 0, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0044, "c13", 0, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0046, "d13", 0, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0048, "c15", 0, 0, "gpmc_ad4", "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x004a, "d15", 0, 0, "gpmc_ad5", "sdmmc2_dat5", "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x004c, "a16", 0, 0, "gpmc_ad6", "sdmmc2_dat6", "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x004e, "b16", 0, 0, "gpmc_ad7", "sdmmc2_dat7", "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0050, "c16", 32, 3, "gpmc_ad8", "kpd_row0", "c2c_data15", "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL), + _OMAP_PINDEF(0x0052, "d16", 33, 3, "gpmc_ad9", "kpd_row1", "c2c_data14", "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL), + _OMAP_PINDEF(0x0054, "c17", 34, 3, "gpmc_ad10", "kpd_row2", "c2c_data13", "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL), + _OMAP_PINDEF(0x0056, "d17", 35, 3, "gpmc_ad11", "kpd_row3", "c2c_data12", "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL), + _OMAP_PINDEF(0x0058, "c18", 36, 3, "gpmc_ad12", "kpd_col0", "c2c_data11", "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL), + _OMAP_PINDEF(0x005a, "d18", 37, 3, "gpmc_ad13", "kpd_col1", "c2c_data10", "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL), + _OMAP_PINDEF(0x005c, "c19", 38, 3, "gpmc_ad14", "kpd_col2", "c2c_data9", "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL), + _OMAP_PINDEF(0x005e, "d19", 39, 3, "gpmc_ad15", "kpd_col3", "c2c_data8", "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL), + _OMAP_PINDEF(0x0060, "b17", 40, 3, "gpmc_a16", "kpd_row4", "c2c_datain0", "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0062, "a18", 41, 3, "gpmc_a17", "kpd_row5", "c2c_datain1", "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0064, "b18", 42, 3, "gpmc_a18", "kpd_row6", "c2c_datain2", "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0066, "a19", 43, 3, "gpmc_a19", "kpd_row7", "c2c_datain3", "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0068, "b19", 44, 3, "gpmc_a20", "kpd_col4", "c2c_datain4", "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x006a, "b20", 45, 3, "gpmc_a21", "kpd_col5", "c2c_datain5", "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x006c, "a21", 46, 3, "gpmc_a22", "kpd_col6", "c2c_datain6", "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x006e, "b21", 47, 3, "gpmc_a23", "kpd_col7", "c2c_datain7", "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0070, "c20", 48, 3, "gpmc_a24", "kpd_col8", "c2c_clkout0", "gpio_48", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0072, "d20", 49, 3, "gpmc_a25", NULL, "c2c_clkout1", "gpio_49", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0074, "b25", 50, 3, "gpmc_ncs0", NULL, NULL, "gpio_50", "sys_ndmareq0", NULL, NULL, NULL), + _OMAP_PINDEF(0x0076, "c21", 51, 3, "gpmc_ncs1", NULL, "c2c_dataout6", "gpio_51", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0078, "d21", 52, 3, "gpmc_ncs2", "kpd_row8", "c2c_dataout7", "gpio_52", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x007a, "c22", 53, 3, "gpmc_ncs3", "gpmc_dir", "c2c_dataout4", "gpio_53", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x007c, "c25", 54, 3, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", "sys_ndmareq1", NULL, NULL, NULL), + _OMAP_PINDEF(0x007e, "b22", 55, 3, "gpmc_clk", NULL, NULL, "gpio_55", "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL), + _OMAP_PINDEF(0x0080, "d25", 56, 3, "gpmc_nadv_ale", "dsi1_te1", NULL, "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL), + _OMAP_PINDEF(0x0082, "b11", 0, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0084, "b12", 0, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0086, "c23", 59, 3, "gpmc_nbe0_cle", "dsi2_te0", NULL, "gpio_59", NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0088, "d22", 60, 3, "gpmc_nbe1", NULL, "c2c_dataout5", "gpio_60", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x008a, "b26", 61, 3, "gpmc_wait0", "dsi2_te1", NULL, "gpio_61", NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x008c, "b23", 62, 3, "gpmc_wait1", NULL, "c2c_dataout2", "gpio_62", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x008e, "d23", 100, 3, "gpmc_wait2", "usbc1_icusb_txen", "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0090, "a24", 101, 3, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0092, "b24", 102, 3, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0094, "c24", 103, 3, "gpmc_ncs6", "dsi2_te0", "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0096, "d24", 104, 3, "gpmc_ncs7", "dsi2_te1", "c2c_dataout1", "gpio_104", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0098, "b9", 63, 3, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x009a, "b10", 64, 3, "hdmi_cec", NULL, NULL, "gpio_64", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x009c, "a8", 65, 3, "hdmi_ddc_scl", NULL, NULL, "gpio_65", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x009e, "b8", 66, 3, "hdmi_ddc_sda", NULL, NULL, "gpio_66", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00a0, "r26", 0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00a2, "r25", 0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00a4, "t26", 0, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00a6, "t25", 0, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00a8, "u26", 0, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00aa, "u25", 0, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00ac, "v26", 0, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00ae, "v25", 0, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00b0, "w26", 0, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00b2, "w25", 0, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00b4, "m26", 0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00b6, "m25", 0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00b8, "n26", 0, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00ba, "n25", 0, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00bc, "t27", 81, 3, "cam_shutter", NULL, NULL, "gpio_81", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00be, "u27", 82, 3, "cam_strobe", NULL, NULL, "gpio_82", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00c0, "v27", 83, 3, "cam_globalreset", NULL, NULL, "gpio_83", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00c2, "ae18", 84, 3, "usbb1_ulpitll_clk", "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", NULL, "hw_dbg20", "safe_mode"), + _OMAP_PINDEF(0x00c4, "ag19", 85, 3, "usbb1_ulpitll_stp", "hsi1_cadata", "mcbsp4_clkr", "gpio_85", "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", "safe_mode"), + _OMAP_PINDEF(0x00c6, "af19", 86, 3, "usbb1_ulpitll_dir", "hsi1_caflag", "mcbsp4_fsr", "gpio_86", "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), + _OMAP_PINDEF(0x00c8, "ae19", 87, 3, "usbb1_ulpitll_nxt", "hsi1_acready", "mcbsp4_fsx", "gpio_87", "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", "safe_mode"), + _OMAP_PINDEF(0x00ca, "af18", 88, 3, "usbb1_ulpitll_dat0", "hsi1_acwake", "mcbsp4_clkx", "gpio_88", "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24", "safe_mode"), + _OMAP_PINDEF(0x00cc, "ag18", 89, 3, "usbb1_ulpitll_dat1", "hsi1_acdata", "mcbsp4_dx", "gpio_89", "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25", "safe_mode"), + _OMAP_PINDEF(0x00ce, "ae17", 90, 3, "usbb1_ulpitll_dat2", "hsi1_acflag", "mcbsp4_dr", "gpio_90", "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26", "safe_mode"), + _OMAP_PINDEF(0x00d0, "af17", 91, 3, "usbb1_ulpitll_dat3", "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"), + _OMAP_PINDEF(0x00d2, "ah17", 92, 3, "usbb1_ulpitll_dat4", "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), + _OMAP_PINDEF(0x00d4, "ae16", 93, 3, "usbb1_ulpitll_dat5", "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), + _OMAP_PINDEF(0x00d6, "af16", 94, 3, "usbb1_ulpitll_dat6", "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", "safe_mode"), + _OMAP_PINDEF(0x00d8, "ag16", 95, 3, "usbb1_ulpitll_dat7", "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", "safe_mode"), + _OMAP_PINDEF(0x00da, "af14", 96, 3, "usbb1_hsic_data", NULL, NULL, "gpio_96", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00dc, "ae14", 97, 3, "usbb1_hsic_strobe", NULL, NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00de, "h2", 98, 3, "usbc1_icusb_dp", NULL, NULL, "gpio_98", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00e0, "h3", 99, 3, "usbc1_icusb_dm", NULL, NULL, "gpio_99", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00e2, "d2", 100, 3, "sdmmc1_clk", NULL, "dpm_emu19", "gpio_100", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00e4, "e3", 101, 3, "sdmmc1_cmd", NULL, "uart1_rx", "gpio_101", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00e6, "e4", 102, 3, "sdmmc1_dat0", NULL, "dpm_emu18", "gpio_102", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00e8, "e2", 103, 3, "sdmmc1_dat1", NULL, "dpm_emu17", "gpio_103", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00ea, "e1", 104, 3, "sdmmc1_dat2", NULL, "dpm_emu16", "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00ec, "f4", 105, 3, "sdmmc1_dat3", NULL, "dpm_emu15", "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00ee, "f3", 106, 3, "sdmmc1_dat4", NULL, NULL, "gpio_106", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00f0, "f1", 107, 3, "sdmmc1_dat5", NULL, NULL, "gpio_107", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00f2, "g4", 108, 3, "sdmmc1_dat6", NULL, NULL, "gpio_108", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00f4, "g3", 109, 3, "sdmmc1_dat7", NULL, NULL, "gpio_109", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00f6, "ad27", 110, 3, "abe_mcbsp2_clkx", "mcspi2_clk", "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00f8, "ad26", 111, 3, "abe_mcbsp2_dr", "mcspi2_somi", "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00fa, "ad25", 112, 3, "abe_mcbsp2_dx", "mcspi2_simo", "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00fc, "ac28", 113, 3, "abe_mcbsp2_fsx", "mcspi2_cs0", "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x00fe, "ac26", 114, 3, "abe_mcbsp1_clkx", "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0100, "ac25", 115, 3, "abe_mcbsp1_dr", "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0102, "ab25", 116, 3, "abe_mcbsp1_dx", "sdmmc3_dat2", "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0104, "ac27", 117, 3, "abe_mcbsp1_fsx", "sdmmc3_dat3", "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0106, "ag25", 0, 0, "abe_pdm_ul_data", "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0108, "af25", 0, 0, "abe_pdm_dl_data", "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x010a, "ae25", 0, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x010c, "af26", 0, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x010e, "ah26", 118, 3, "abe_clks", NULL, NULL, "gpio_118", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0110, "ae24", 119, 3, "abe_dmic_clk1", NULL, NULL, "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL, "safe_mode"), + _OMAP_PINDEF(0x0112, "af24", 120, 3, "abe_dmic_din1", NULL, NULL, "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL, "safe_mode"), + _OMAP_PINDEF(0x0114, "ag24", 121, 3, "abe_dmic_din2", "slimbus2_clock", "abe_mcasp_axr", "gpio_121", NULL, "dmtimer11_pwm_evt", NULL, "safe_mode"), + _OMAP_PINDEF(0x0116, "ah24", 122, 3, "abe_dmic_din3", "slimbus2_data", "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt", NULL, "safe_mode"), + _OMAP_PINDEF(0x0118, "ab26", 123, 3, "uart2_cts", "sdmmc3_clk", NULL, "gpio_123", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x011a, "ab27", 124, 3, "uart2_rts", "sdmmc3_cmd", NULL, "gpio_124", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x011c, "aa25", 125, 3, "uart2_rx", "sdmmc3_dat0", NULL, "gpio_125", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x011e, "aa26", 126, 3, "uart2_tx", "sdmmc3_dat1", NULL, "gpio_126", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0120, "aa27", 127, 3, "hdq_sio", "i2c3_sccb", "i2c2_sccb", "gpio_127", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0122, "ae28", 0, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0124, "ae26", 0, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0126, "c26", 128, 3, "i2c2_scl", "uart1_rx", NULL, "gpio_128", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0128, "d26", 129, 3, "i2c2_sda", "uart1_tx", NULL, "gpio_129", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x012a, "w27", 130, 3, "i2c3_scl", NULL, NULL, "gpio_130", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x012c, "y27", 131, 3, "i2c3_sda", NULL, NULL, "gpio_131", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x012e, "ag21", 132, 3, "i2c4_scl", NULL, NULL, "gpio_132", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0130, "ah22", 133, 3, "i2c4_sda", NULL, NULL, "gpio_133", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0132, "af22", 134, 3, "mcspi1_clk", NULL, NULL, "gpio_134", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0134, "ae22", 135, 3, "mcspi1_somi", NULL, NULL, "gpio_135", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0136, "ag22", 136, 3, "mcspi1_simo", NULL, NULL, "gpio_136", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0138, "ae23", 137, 3, "mcspi1_cs0", NULL, NULL, "gpio_137", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x013a, "af23", 138, 3, "mcspi1_cs1", "uart1_rx", NULL, "gpio_138", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x013c, "ag23", 139, 3, "mcspi1_cs2", "uart1_cts", "slimbus2_clock", "gpio_139", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x013e, "ah23", 140, 3, "mcspi1_cs3", "uart1_rts", "slimbus2_data", "gpio_140", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0140, "f27", 141, 3, "uart3_cts_rctx", "uart1_tx", NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0142, "f28", 142, 3, "uart3_rts_sd", NULL, NULL, "gpio_142", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0144, "g27", 143, 3, "uart3_rx_irrx", "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0146, "g28", 144, 3, "uart3_tx_irtx", "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0148, "ae5", 145, 3, "sdmmc5_clk", "mcspi2_clk", "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk", NULL, "safe_mode"), + _OMAP_PINDEF(0x014a, "af5", 146, 3, "sdmmc5_cmd", "mcspi2_simo", "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd", NULL, "safe_mode"), + _OMAP_PINDEF(0x014c, "ae4", 147, 3, "sdmmc5_dat0", "mcspi2_somi", "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0", NULL, "safe_mode"), + _OMAP_PINDEF(0x014e, "af4", 148, 3, "sdmmc5_dat1", NULL, "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1", NULL, "safe_mode"), + _OMAP_PINDEF(0x0150, "ag3", 149, 3, "sdmmc5_dat2", "mcspi2_cs1", NULL, "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"), + _OMAP_PINDEF(0x0152, "af3", 150, 3, "sdmmc5_dat3", "mcspi2_cs0", NULL, "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"), + _OMAP_PINDEF(0x0154, "ae21", 151, 3, "mcspi4_clk", "sdmmc4_clk", "kpd_col6", "gpio_151", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0156, "af20", 152, 3, "mcspi4_simo", "sdmmc4_cmd", "kpd_col7", "gpio_152", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0158, "af21", 153, 3, "mcspi4_somi", "sdmmc4_dat0", "kpd_row6", "gpio_153", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x015a, "ae20", 154, 3, "mcspi4_cs0", "sdmmc4_dat3", "kpd_row7", "gpio_154", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x015c, "ag20", 155, 3, "uart4_rx", "sdmmc4_dat2", "kpd_row8", "gpio_155", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x015e, "ah19", 156, 3, "uart4_tx", "sdmmc4_dat1", "kpd_col8", "gpio_156", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0160, "ag12", 157, 3, "usbb2_ulpitll_clk", "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", "hsi2_cawake", NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0162, "af12", 158, 3, "usbb2_ulpitll_stp", "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"), + _OMAP_PINDEF(0x0164, "ae12", 159, 3, "usbb2_ulpitll_dir", "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"), + _OMAP_PINDEF(0x0166, "ag13", 160, 3, "usbb2_ulpitll_nxt", "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", "hsi2_acready", "dispc2_data21", NULL, "safe_mode"), + _OMAP_PINDEF(0x0168, "ae11", 161, 3, "usbb2_ulpitll_dat0", "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen", "safe_mode"), + _OMAP_PINDEF(0x016a, "af11", 162, 3, "usbb2_ulpitll_dat1", "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat", "safe_mode"), + _OMAP_PINDEF(0x016c, "ag11", 163, 3, "usbb2_ulpitll_dat2", "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0", "safe_mode"), + _OMAP_PINDEF(0x016e, "ah11", 164, 3, "usbb2_ulpitll_dat3", "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", "hsi2_caready", "dispc2_data15", "rfbi_data15", "safe_mode"), + _OMAP_PINDEF(0x0170, "ae10", 165, 3, "usbb2_ulpitll_dat4", "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", "mcspi3_somi", "dispc2_data14", "rfbi_data14", "safe_mode"), + _OMAP_PINDEF(0x0172, "af10", 166, 3, "usbb2_ulpitll_dat5", "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", "mcspi3_cs0", "dispc2_data13", "rfbi_data13", "safe_mode"), + _OMAP_PINDEF(0x0174, "ag10", 167, 3, "usbb2_ulpitll_dat6", "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", "mcspi3_simo", "dispc2_data12", "rfbi_data12", "safe_mode"), + _OMAP_PINDEF(0x0176, "ae9", 168, 3, "usbb2_ulpitll_dat7", "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", "mcspi3_clk", "dispc2_data11", "rfbi_data11", "safe_mode"), + _OMAP_PINDEF(0x0178, "af13", 169, 3, "usbb2_hsic_data", NULL, NULL, "gpio_169", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x017a, "ae13", 170, 3, "usbb2_hsic_strobe", NULL, NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x017c, "g26", 171, 3, "kpd_col3", "kpd_col0", NULL, "gpio_171", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x017e, "g25", 172, 3, "kpd_col4", "kpd_col1", NULL, "gpio_172", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0180, "h26", 173, 3, "kpd_col5", "kpd_col2", NULL, "gpio_173", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0182, "h25", 174, 3, "kpd_col0", "kpd_col3", NULL, "gpio_174", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0184, "j27", 0, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0186, "h27", 1, 3, "kpd_col2", "kpd_col5", NULL, "gpio_1", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0188, "j26", 175, 3, "kpd_row3", "kpd_row0", NULL, "gpio_175", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x018a, "j25", 176, 3, "kpd_row4", "kpd_row1", NULL, "gpio_176", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x018c, "k26", 177, 3, "kpd_row5", "kpd_row2", NULL, "gpio_177", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x018e, "k25", 178, 3, "kpd_row0", "kpd_row3", NULL, "gpio_178", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0190, "l27", 2, 3, "kpd_row1", "kpd_row4", NULL, "gpio_2", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0192, "k27", 3, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0194, "c3", 0, 0, "usba0_otg_ce", NULL, NULL, NULL, NULL, NULL, NULL, NULL), + _OMAP_PINDEF(0x0196, "b5", 0, 0, "usba0_otg_dp", "uart3_rx_irrx", "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x0198, "b4", 0, 0, "usba0_otg_dm", "uart3_tx_irtx", "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x019a, "aa28", 181, 3, "fref_clk1_out", NULL, NULL, "gpio_181", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x019c, "y28", 182, 3, "fref_clk2_out", NULL, NULL, "gpio_182", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x019e, "ae6", 0, 0, "sys_nirq1", NULL, NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x01a0, "af6", 183, 3, "sys_nirq2", NULL, NULL, "gpio_183", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x01a2, "f26", 184, 3, "sys_boot0", NULL, NULL, "gpio_184", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x01a4, "e27", 185, 3, "sys_boot1", NULL, NULL, "gpio_185", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x01a6, "e26", 186, 3, "sys_boot2", NULL, NULL, "gpio_186", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x01a8, "e25", 187, 3, "sys_boot3", NULL, NULL, "gpio_187", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x01aa, "d28", 188, 3, "sys_boot4", NULL, NULL, "gpio_188", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x01ac, "d27", 189, 3, "sys_boot5", NULL, NULL, "gpio_189", NULL, NULL, NULL, "safe_mode"), + _OMAP_PINDEF(0x01ae, "m2", 11, 3, "dpm_emu0", NULL, NULL, "gpio_11", NULL, NULL, "hw_dbg0", "safe_mode"), + _OMAP_PINDEF(0x01b0, "n2", 12, 3, "dpm_emu1", NULL, NULL, "gpio_12", NULL, NULL, "hw_dbg1", "safe_mode"), + _OMAP_PINDEF(0x01b2, "p2", 13, 3, "dpm_emu2", "usba0_ulpiphy_clk", NULL, "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "safe_mode"), + _OMAP_PINDEF(0x01b4, "v1", 14, 3, "dpm_emu3", "usba0_ulpiphy_stp", NULL, "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3", "safe_mode"), + _OMAP_PINDEF(0x01b6, "v2", 15, 3, "dpm_emu4", "usba0_ulpiphy_dir", NULL, "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4", "safe_mode"), + _OMAP_PINDEF(0x01b8, "w1", 16, 3, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, "gpio_16", "rfbi_te_vsync0", "dispc2_data16", "hw_dbg5", "safe_mode"), + _OMAP_PINDEF(0x01ba, "w2", 17, 3, "dpm_emu6", "usba0_ulpiphy_dat0", "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", "dispc2_data17", "hw_dbg6", "safe_mode"), + _OMAP_PINDEF(0x01bc, "w3", 18, 3, "dpm_emu7", "usba0_ulpiphy_dat1", "uart3_rx_irrx", "gpio_18", "rfbi_cs0", "dispc2_hsync", "hw_dbg7", "safe_mode"), + _OMAP_PINDEF(0x01be, "w4", 19, 3, "dpm_emu8", "usba0_ulpiphy_dat2", "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", "hw_dbg8", "safe_mode"), + _OMAP_PINDEF(0x01c0, "y2", 20, 3, "dpm_emu9", "usba0_ulpiphy_dat3", "uart3_cts_rctx", "gpio_20", "rfbi_we", "dispc2_vsync", "hw_dbg9", "safe_mode"), + _OMAP_PINDEF(0x01c2, "y3", 21, 3, "dpm_emu10", "usba0_ulpiphy_dat4", NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", "safe_mode"), + _OMAP_PINDEF(0x01c4, "y4", 22, 3, "dpm_emu11", "usba0_ulpiphy_dat5", NULL, "gpio_22", "rfbi_data8", "dispc2_data8", "hw_dbg11", "safe_mode"), + _OMAP_PINDEF(0x01c6, "aa1", 23, 3, "dpm_emu12", "usba0_ulpiphy_dat6", NULL, "gpio_23", "rfbi_data7", "dispc2_data7", "hw_dbg12", "safe_mode"), + _OMAP_PINDEF(0x01c8, "aa2", 24, 3, "dpm_emu13", "usba0_ulpiphy_dat7", NULL, "gpio_24", "rfbi_data6", "dispc2_data6", "hw_dbg13", "safe_mode"), + _OMAP_PINDEF(0x01ca, "aa3", 25, 3, "dpm_emu14", "sys_drm_msecure", "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", "hw_dbg14", "safe_mode"), + _OMAP_PINDEF(0x01cc, "aa4", 26, 3, "dpm_emu15", "sys_secure_indicator", NULL, "gpio_26", "rfbi_data4", "dispc2_data4", "hw_dbg15", "safe_mode"), + _OMAP_PINDEF(0x01ce, "ab2", 27, 3, "dpm_emu16", "dmtimer8_pwm_evt", "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", "hw_dbg16", "safe_mode"), + _OMAP_PINDEF(0x01d0, "ab3", 28, 3, "dpm_emu17", "dmtimer9_pwm_evt", "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", "hw_dbg17", "safe_mode"), + _OMAP_PINDEF(0x01d2, "ab4", 190, 3, "dpm_emu18", "dmtimer10_pwm_evt", "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", "hw_dbg18", "safe_mode"), + _OMAP_PINDEF(0x01d4, "ac4", 191, 3, "dpm_emu19", "dmtimer11_pwm_evt", "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", "hw_dbg19", "safe_mode"), + { .ballname = NULL }, +}; Index: projects/armv6/sys/arm/omap/omap4/omap4_timer.c =================================================================== --- projects/armv6/sys/arm/omap/omap4/omap4_timer.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/omap4_timer.c (revision 230362) @@ -0,0 +1,417 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "omap4_if.h" + +/** + * After writing the GPTIMER driver I began thinking that these are probably + * not the best timers to use for the tick timer and time count stuff, rather + * perhaps it's a better idea to use the timers built into the A9 core. + * + * My reasoning is that the GPTIMER driver really should (and currently does) + * take a mutex to protect access to the timer structure when reading the time + * counter, and this may not be a good idea within system callback functions + * like timecounter. However that said the locks are currently SPIN_MTX + * types so I think this *shouldn't* be a problem. + * + * Regardless I think it is probably better to just use the A9 Core global + * timer and be done with it. + * + * + * Current System Timer Design + * =========================== + * + * Tick Timer => uses => Core 0 Private timer + * Timecount => uses => ARM Global timer + * + */ + + + +/* Private (per-CPU) timer register map */ +#define PRV_TIMER_LOAD 0x0000 +#define PRV_TIMER_COUNT 0x0004 +#define PRV_TIMER_CTRL 0x0008 +#define PRV_TIMER_INTR 0x000C + +#define PRV_TIMER_IRQ_NUM 29 + +#define PRV_TIMER_CTR_PRESCALER_SHIFT 8 +#define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2) +#define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1) +#define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0) + +#define PRV_TIMER_INTR_EVENT (1UL << 0) + +/* Global timer register map */ +#define GBL_TIMER_COUNT_LOW 0x0000 +#define GBL_TIMER_COUNT_HIGH 0x0004 +#define GBL_TIMER_CTRL 0x0008 +#define GBL_TIMER_INTR 0x000C + +#define GBL_TIMER_IRQ_NUM 27 + +#define GBL_TIMER_CTR_PRESCALER_SHIFT 8 +#define GBL_TIMER_CTRL_AUTO_INC (1UL << 3) +#define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2) +#define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1) +#define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0) + +#define GBL_TIMER_INTR_EVENT (1UL << 0) + +static device_t omap4_dev; + +/** + * omap4_timer_get_timecount - returns the count in GPTIMER11, the system counter + * @tc: pointer to the timecounter structure used to register the callback + * + * + * + * RETURNS: + * the value in the counter + */ +static unsigned +omap4_timer_get_timecount(struct timecounter *tc) +{ + /* We only read the lower 32-bits, the timecount stuff only uses 32-bits + * so (for now?) ignore the upper 32-bits. + */ + return (OMAP4_GBL_TIMER_READ(omap4_dev, GBL_TIMER_COUNT_LOW)); +} + +static struct timecounter omap4_timecounter = { + .tc_get_timecount = omap4_timer_get_timecount, /* get_timecount */ + .tc_poll_pps = NULL, /* no poll_pps */ + .tc_counter_mask = ~0u, /* counter_mask */ + .tc_frequency = 0, /* frequency */ + .tc_name = "OMAP4 Timer", /* name */ + .tc_quality = 1000, /* quality */ +}; + +static struct eventtimer omap4_eventtimer; + +/** + * omap4_clk_intr - + * + * Interrupt handler for the private interrupt. + * + * RETURNS: + * nothing + */ +static int +omap4_clk_intr(void *arg) +{ + struct trapframe *frame = arg; + + OMAP4_PRV_TIMER_WRITE(omap4_dev, + PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT); + + hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); + return (FILTER_HANDLED); +} + +static int +omap4_timer_start(struct eventtimer *et, + struct bintime *first, struct bintime *period) +{ + + return (0); +} + +static int +omap4_timer_stop(struct eventtimer *et) +{ + + return (0); +} + +/* + * omap4_init_timer - + * setup interrupt and device instance that manages access to registers + */ + +void +omap4_init_timer(device_t dev) +{ + struct resource *irq; + int rid = 0; + void *ihl; + + omap4_dev = dev; + + /* Register an interrupt handler for general purpose timer 10 */ + irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, + PRV_TIMER_IRQ_NUM, PRV_TIMER_IRQ_NUM, 1, RF_ACTIVE); + if (!irq) + panic("Unable to setup the clock irq handler.\n"); + else + bus_setup_intr(dev, irq, INTR_TYPE_CLK, + omap4_clk_intr, NULL, NULL, &ihl); + +} + +/** + * cpu_initclocks - function called by the system in init the tick clock/timer + * + * This is where both the timercount and system ticks timer are started. + * + * RETURNS: + * nothing + */ +void +cpu_initclocks(void) +{ + u_int oldirqstate; + unsigned int mpuclk_freq; + unsigned int periphclk_freq; + unsigned int prescaler; + uint64_t load64; + + /* First ensure we have what we need */ + if (omap4_dev == NULL) + panic("omap4xx device is not set before enabling global timer\n"); + + + oldirqstate = disable_interrupts(I32_bit); + + /* Ensure the timer is disabled before we start playing with it */ + OMAP4_PRV_TIMER_WRITE(omap4_dev, PRV_TIMER_CTRL, 0x00000000); + + + /* Next get the "PERIPHCLK" freq - which I take to be the "LOCAL_INTCNT_FCLK" + * refered to in the OMAP44xx datasheet. The "LOCAL_INTCNT_FCLK" is half + * the ARM_FCLK. + */ + if (omap_prcm_clk_get_source_freq(MPU_CLK, &mpuclk_freq) != 0) + panic("Failed to get the SYSCLK frequency\n"); + + periphclk_freq = mpuclk_freq / 2; + + /* The timer counts down from a 'load' value to zero, when it reaches zero + * it loads the 'load' value back in and starts counting down again. + * + * So we need to calculate the load value, the larger the load the value + * the better the accuracy. + */ + for (prescaler = 1; prescaler < 255; prescaler++) { + load64 = ((uint64_t)periphclk_freq / (uint64_t)hz) / (uint64_t)prescaler; + if (load64 <= 0xFFFFFFFFULL) { + break; + } + } + + if (prescaler == 255) + panic("Couldn't fit timer tick in private counter\n"); + + /* Set the load value */ + OMAP4_PRV_TIMER_WRITE(omap4_dev, PRV_TIMER_LOAD, (uint32_t)load64); + OMAP4_PRV_TIMER_WRITE(omap4_dev, PRV_TIMER_COUNT, (uint32_t)load64); + + /* Setup and enable the timer */ + OMAP4_PRV_TIMER_WRITE(omap4_dev, PRV_TIMER_CTRL, + ((prescaler - 1) << PRV_TIMER_CTR_PRESCALER_SHIFT) | + PRV_TIMER_CTRL_IRQ_ENABLE | + PRV_TIMER_CTRL_AUTO_RELOAD | + PRV_TIMER_CTRL_TIMER_ENABLE); + + + /* Setup and enable the global timer to use as the timecounter */ + OMAP4_GBL_TIMER_WRITE(omap4_dev, GBL_TIMER_CTRL, + (0x00 << GBL_TIMER_CTR_PRESCALER_SHIFT) | + GBL_TIMER_CTRL_TIMER_ENABLE); + + + /* Save the system clock speed */ + omap4_timecounter.tc_frequency = periphclk_freq; + + /* Setup the time counter */ + tc_init(&omap4_timecounter); + + omap4_eventtimer.et_name = "OMAP4 Event Timer"; + omap4_eventtimer.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; + omap4_eventtimer.et_quality = 1000; + + omap4_eventtimer.et_frequency = 1000; /* XXX */ + omap4_eventtimer.et_min_period.sec = 0; + omap4_eventtimer.et_min_period.frac = + ((0x00000002LLU << 32) / omap4_eventtimer.et_frequency) << 32; + omap4_eventtimer.et_max_period.sec = 0xfffffff0U / omap4_eventtimer.et_frequency; + omap4_eventtimer.et_max_period.frac = + ((0xfffffffeLLU << 32) / omap4_eventtimer.et_frequency) << 32; + omap4_eventtimer.et_start = omap4_timer_start; + omap4_eventtimer.et_stop = omap4_timer_stop; + omap4_eventtimer.et_priv = NULL; + et_register(&omap4_eventtimer); + + restore_interrupts(oldirqstate); + + cpu_initclocks_bsp(); + +#if 0 + unsigned int sysclk_freq; + + /* Number of microseconds between interrupts */ + tick = 1000000 / hz; + + /* Next setup one of the timers to be the system tick timer */ + if (omap_timer_activate(TICKTIMER_GPTIMER, OMAP_TIMER_SYSTICK_FLAG, tick, + NULL, NULL)) { + panic("Error: failed to activate system tick timer\n"); + } else if (omap_timer_start(TICKTIMER_GPTIMER)) { + panic("Error: failed to start system tick timer\n"); + } + + + /* Enable the ARM Coretex-A9 core global timer, this is used for calculating + * delay times in the DELAY() function ... and as the system timecount + * value ?? + */ + + + + /* Setup another timer to be the timecounter */ + if (omap_timer_activate(TIMECOUNT_GPTIMER, OMAP_TIMER_PERIODIC_FLAG, 0, + NULL, NULL)) { + printf("Error: failed to activate system tick timer\n"); + } else if (omap_timer_start(TIMECOUNT_GPTIMER)) { + printf("Error: failed to start system tick timer\n"); + } + + /* Get the SYS_CLK frequency, this is the freq of the timer tick */ + if (omap_prcm_clk_get_source_freq(SYS_CLK, &sysclk_freq) != 0) + panic("Failed to get the SYSCLK frequency\n"); + + /* Save the system clock speed */ + omap4_timecounter.tc_frequency = sysclk_freq; + + /* Setup the time counter */ + tc_init(&omap4_timecounter); + +#endif + +} + +/** + * DELAY - Delay for at least N microseconds. + * @n: number of microseconds to delay by + * + * This function is called all over the kernel and is suppose to provide a + * consistent delay. It is a busy loop and blocks polling a timer when called. + * + * RETURNS: + * nothing + */ +void +DELAY(int n) +{ + int32_t counts_per_usec; + int32_t counts; + uint32_t first, last; + + if (n <= 0) + return; + + /* Check the timers are setup, if not just use a for loop for the meantime */ + if (omap4_timecounter.tc_frequency == 0) { + + /* If the CPU clock speed is defined we use that via the 'cycle count' + * register, this should give us a pretty accurate delay value. If not + * defined we use a basic for loop with a very simply calculation. + */ +#if defined(CPU_CLOCKSPEED) + counts_per_usec = (CPU_CLOCKSPEED / 1000000); + counts = counts_per_usec * 1000; + + __asm __volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (first)); + while (counts > 0) { + __asm __volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (last)); + counts -= (int32_t)(last - first); + first = last; + } +#else + uint32_t val; + for (; n > 0; n--) + for (val = 200; val > 0; val--) + cpufunc_nullop(); /* + * Prevent gcc from + * optimizing out the + * loop + */ + +#endif + return; + } + + /* Get the number of times to count */ + counts_per_usec = ((omap4_timecounter.tc_frequency / 1000000) + 1); + + /* + * Clamp the timeout at a maximum value (about 32 seconds with + * a 66MHz clock). *Nobody* should be delay()ing for anywhere + * near that length of time and if they are, they should be hung + * out to dry. + */ + if (n >= (0x80000000U / counts_per_usec)) + counts = (0x80000000U / counts_per_usec) - 1; + else + counts = n * counts_per_usec; + + first = OMAP4_GBL_TIMER_READ(omap4_dev, GBL_TIMER_COUNT_LOW); + + while (counts > 0) { + last = OMAP4_GBL_TIMER_READ(omap4_dev, GBL_TIMER_COUNT_LOW); + counts -= (int32_t)(last - first); + first = last; + } +} Index: projects/armv6/sys/arm/omap/omap4/omap4var.h =================================================================== --- projects/armv6/sys/arm/omap/omap4/omap4var.h (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/omap4var.h (revision 230362) @@ -0,0 +1,89 @@ +/*- + * Copyright (c) 2010 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _OMAP4VAR_H_ +#define _OMAP4VAR_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +void omap4_mask_all_intr(void); +void omap4_post_filter_intr(void *arg); + +struct omap4_softc { + device_t sc_dev; + bus_space_tag_t sc_iotag; + + /* Handles for the two generic interrupt controller (GIC) register mappings */ + bus_space_handle_t sc_gic_cpu_ioh; + bus_space_handle_t sc_gic_dist_ioh; + + /* Handle for the PL310 L2 cache controller */ + bus_space_handle_t sc_pl310_ioh; + + /* Handle for the global and provate timer register set in the Cortex core */ + bus_space_handle_t sc_prv_timer_ioh; + bus_space_handle_t sc_gbl_timer_ioh; + + /* SCM access */ + struct resource *sc_scm_mem; + int sc_scm_rid; +}; + +struct omap4_intr_conf { + int num; + unsigned int priority; + unsigned int target_cpu; +}; + +int omap4_setup_intr_controller(device_t dev, + const struct omap4_intr_conf *irqs); +int omap4_setup_gic_cpu(unsigned int prio_mask); + +void omap4_init_timer(device_t dev); + +int omap4_setup_l2cache_controller(struct omap4_softc *sc); +void omap4_smc_call(uint32_t fn, uint32_t arg); + +#endif /* _OMAP4VAR_H_ */ Index: projects/armv6/sys/arm/omap/omap4/pandaboard/files.pandaboard =================================================================== --- projects/armv6/sys/arm/omap/omap4/pandaboard/files.pandaboard (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/pandaboard/files.pandaboard (revision 230362) @@ -0,0 +1,3 @@ +# $FreeBSD$ + +arm/omap/omap4/pandaboard/pandaboard.c standard Index: projects/armv6/sys/arm/omap/omap4/pandaboard/pandaboard.c =================================================================== --- projects/armv6/sys/arm/omap/omap4/pandaboard/pandaboard.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/pandaboard/pandaboard.c (revision 230362) @@ -0,0 +1,194 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +/* Registers in the SCRM that control the AUX clocks */ +#define SCRM_ALTCLKSRC (OMAP44XX_SCRM_VBASE + 0x110) +#define SCRM_AUXCLK0 (OMAP44XX_SCRM_VBASE + 0x0310) +#define SCRM_AUXCLK1 (OMAP44XX_SCRM_VBASE + 0x0314) +#define SCRM_AUXCLK2 (OMAP44XX_SCRM_VBASE + 0x0318) +#define SCRM_AUXCLK3 (OMAP44XX_SCRM_VBASE + 0x031C) + +/* Some of the GPIO register set */ +#define GPIO1_OE (OMAP44XX_GPIO1_VBASE + 0x0134) +#define GPIO1_CLEARDATAOUT (OMAP44XX_GPIO1_VBASE + 0x0190) +#define GPIO1_SETDATAOUT (OMAP44XX_GPIO1_VBASE + 0x0194) +#define GPIO2_OE (OMAP44XX_GPIO2_VBASE + 0x0134) +#define GPIO2_CLEARDATAOUT (OMAP44XX_GPIO2_VBASE + 0x0190) +#define GPIO2_SETDATAOUT (OMAP44XX_GPIO2_VBASE + 0x0194) + +/* Some of the PADCONF register set */ +#define CONTROL_WKUP_PAD0_FREF_CLK3_OUT (OMAP44XX_SCM_PADCONF_VBASE + 0x058) +#define CONTROL_CORE_PAD1_KPD_COL2 (OMAP44XX_SCM_PADCONF_VBASE + 0x186) +#define CONTROL_CORE_PAD0_GPMC_WAIT1 (OMAP44XX_SCM_PADCONF_VBASE + 0x08C) + +#define REG_WRITE32(r, x) *((volatile uint32_t*)(r)) = (uint32_t)(x) +#define REG_READ32(r) *((volatile uint32_t*)(r)) + +#define REG_WRITE16(r, x) *((volatile uint16_t*)(r)) = (uint16_t)(x) +#define REG_READ16(r) *((volatile uint16_t*)(r)) + +/** + * usb_hub_init - initialises and resets the external USB hub + * + * The USB hub needs to be held in reset while the power is being applied + * and the reference clock is enabled at 19.2MHz. The following is the + * layout of the USB hub taken from the Pandaboard reference manual. + * + * + * .-------------. .--------------. .----------------. + * | OMAP4430 | | USB3320C | | LAN9514 | + * | | | | | USB Hub / Eth | + * | CLK | <------ | CLKOUT | | | + * | STP | ------> | STP | | | + * | DIR | <------ | DIR | | | + * | NXT | <------ | NXT | | | + * | DAT0 | <-----> | DAT0 | | | + * | DAT1 | <-----> | DAT1 DP | <-----> | DP | + * | DAT2 | <-----> | DAT2 DM | <-----> | DM | + * | DAT3 | <-----> | DAT3 | | | + * | DAT4 | <-----> | DAT4 | | | + * | DAT5 | <-----> | DAT5 | +----> | N_RESET | + * | DAT6 | <-----> | DAT6 | | | | + * | DAT7 | <-----> | DAT7 | | | | + * | | | | | +-> | VDD33IO | + * | AUX_CLK3 | ------> | REFCLK | | +-> | VDD33A | + * | | | | | | | | + * | GPIO_62 | --+---> | RESET | | | | | + * | | | | | | | | | + * | | | '--------------' | | '----------------' + * | | | .--------------. | | + * | | '---->| VOLT CONVERT |--' | + * | | '--------------' | + * | | | + * | | .--------------. | + * | GPIO_1 | ------> | TPS73633 |-----' + * | | '--------------' + * '-------------' + * + * + * RETURNS: + * nothing. + */ +static void +usb_hub_init(void) +{ + + + /* Need to set FREF_CLK3_OUT to 19.2 MHz and pump it out on pin GPIO_WK31. + * We know the SYS_CLK is 38.4Mhz and therefore to get the needed 19.2Mhz, + * just use a 2x divider and ensure the SYS_CLK is used as the source. + */ + //int pouet = REG_READ32(SCRM_AUXCLK3); + REG_WRITE32(SCRM_AUXCLK3, (1 << 16) | /* Divider of 2 */ + (0 << 1) | /* Use the SYS_CLK as the source */ + (1 << 8)); /* Enable the clock */ + +#if 0 + REG_WRITE32(SCRM_ALTCLKSRC, (1 << 1) | ( 3 << 2)); +#endif + /* Enable the clock out to the pin (GPIO_WK31). + * muxmode=fref_clk3_out, pullup/down=disabled, input buffer=disabled, + * wakeup=disabled. + */ + REG_WRITE16(CONTROL_WKUP_PAD0_FREF_CLK3_OUT, 0x0000); + + + /* Disable the power to the USB hub, drive GPIO1 low */ + REG_WRITE32(GPIO1_OE, REG_READ32(GPIO1_OE) & ~(1UL << 1)); + REG_WRITE32(GPIO1_CLEARDATAOUT, (1UL << 1)); + REG_WRITE16(CONTROL_CORE_PAD1_KPD_COL2, 0x0003); + + + /* Reset the USB PHY and Hub using GPIO_62 */ + REG_WRITE32(GPIO2_OE, REG_READ32(GPIO2_OE) & ~(1UL << 30)); + REG_WRITE32(GPIO2_CLEARDATAOUT, (1UL << 30)); + REG_WRITE16(CONTROL_CORE_PAD0_GPMC_WAIT1, 0x0003); + DELAY(10); + REG_WRITE32(GPIO2_SETDATAOUT, (1UL << 30)); + + + /* Enable power to the hub (GPIO_1) */ + REG_WRITE32(GPIO1_SETDATAOUT, (1UL << 1)); + +} + +/** + * board_init - initialises the pandaboard + * @dummy: ignored + * + * This function is called before any of the driver are initialised, which is + * annoying because it means we can't use the SCM, PRCM and GPIO modules which + * would really be useful. + * + * So we don't have: + * - any drivers + * - no interrupts + * + * What we do have: + * - virt/phys mappings from the devmap (see omap44xx.c) + * - + * + * + * So we are hamstrung without the useful drivers and we have to go back to + * direct register manupulation. Luckly we don't have to do to much, basically + * just setup the usb hub/ethernet. + * + */ +static void +board_init(void *dummy) +{ + /* Initialise the USB phy and hub */ + usb_hub_init(); + + /* + * XXX Board identification e.g. read out from FPGA or similar should + * go here + */ +} + +SYSINIT(board_init, SI_SUB_CPU, SI_ORDER_THIRD, board_init, NULL); Index: projects/armv6/sys/arm/omap/omap4/pandaboard/std.pandaboard =================================================================== --- projects/armv6/sys/arm/omap/omap4/pandaboard/std.pandaboard (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/pandaboard/std.pandaboard (revision 230362) @@ -0,0 +1,4 @@ +# $FreeBSD$ + +include "../omap/omap4/std.omap44xx" +files "../omap/omap4/pandaboard/files.pandaboard" Index: projects/armv6/sys/arm/omap/omap4/std.omap44xx =================================================================== --- projects/armv6/sys/arm/omap/omap4/std.omap44xx (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/std.omap44xx (revision 230362) @@ -0,0 +1,21 @@ +# Omap4430 generic configuration +#$FreeBSD$ +files "../omap/omap4/files.omap44xx" +include "../omap/std.omap" +makeoption ARM_LITTLE_ENDIAN + +# Physical memory starts at 0x80000000. We assume images are loaded at +# 0x80200000, e.g. from u-boot with 'fatload mmc 0 0x80200000 kernel.bin' +# +# +options PHYSADDR=0x80000000 +options KERNPHYSADDR=0x80200000 +makeoptions KERNPHYSADDR=0x80200000 +options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm +makeoptions KERNVIRTADDR=0xc0200000 + +options STARTUP_PAGETABLE_ADDR=0x80000000 + +options SOC_OMAP4 + +options ARM_L2_PIPT Index: projects/armv6/sys/arm/omap/omap4/uart_cpu_omap4.c =================================================================== --- projects/armv6/sys/arm/omap/omap4/uart_cpu_omap4.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap4/uart_cpu_omap4.c (revision 230362) @@ -0,0 +1,90 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +bus_space_tag_t uart_bus_space_io; +bus_space_tag_t uart_bus_space_mem; + + +#define OMAP44XX_UART_FREQ 48000000 /* 48Mhz clock for all uarts (techref 17.3.1.1) */ + + +/* --------------------------------------------------------------- */ +/* uart_cpu_eqres + * + * Checks if the two UART base addresses are equal, if they are + * 1 is returned, otherwise 0 is returned. + */ +int uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) +{ + return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); +} + +/* --------------------------------------------------------------- */ +/* uart_cpu_getdev + * + * + * + */ +int uart_cpu_getdev(int devtype, struct uart_devinfo *di) +{ + di->ops = uart_getops(&uart_ns8250_class); + di->bas.chan = 0; + di->bas.regshft = 2; + di->bas.rclk = OMAP44XX_UART_FREQ; + di->bas.bst = &omap_bs_tag; + + if (bus_space_map(di->bas.bst, OMAP44XX_UART3_HWBASE, OMAP44XX_UART3_SIZE, + 0, &di->bas.bsh) != 0) { + return (ENXIO); + } + + di->baudrate = 115200; + di->databits = 8; + di->stopbits = 1; + di->parity = UART_PARITY_NONE; + uart_bus_space_mem = NULL; + uart_bus_space_io = &omap_bs_tag; + + return (0); +} Index: projects/armv6/sys/arm/omap/omap_cpuid.c =================================================================== --- projects/armv6/sys/arm/omap/omap_cpuid.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap_cpuid.c (revision 230362) @@ -0,0 +1,234 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define OMAP4_STD_FUSE_DIE_ID_0 0x2200 +#define OMAP4_ID_CODE 0x2204 +#define OMAP4_STD_FUSE_DIE_ID_1 0x2208 +#define OMAP4_STD_FUSE_DIE_ID_2 0x220C +#define OMAP4_STD_FUSE_DIE_ID_3 0x2210 +#define OMAP4_STD_FUSE_PROD_ID_0 0x2214 +#define OMAP4_STD_FUSE_PROD_ID_1 0x2218 + +#define OMAP3_ID_CODE 0xA204 + +#define REG_READ32(r) *((volatile uint32_t*)(r)) + +static uint32_t chip_revision = 0xffffffff; + +/** + * omap_revision - Returns the revision number of the device + * + * Simply returns an identifier for the revision of the chip we are running + * on. + * + * RETURNS + * A 32-bit identifier for the current chip + */ +uint32_t +omap_revision(void) +{ + return chip_revision; +} + +/** + * omap4_get_revision - determines omap4 revision + * + * Reads the registers to determine the revision of the chip we are currently + * running on. Stores the information in global variables. + * + * + */ +static void +omap4_get_revision(void) +{ + uint32_t id_code; + uint32_t revision; + uint32_t hawkeye; + + /* The chip revsion is read from the device identification registers and + * the JTAG (?) tap registers, which are located in address 0x4A00_2200 to + * 0x4A00_2218. This is part of the L4_CORE memory range and should have + * been mapped in by the machdep.c code. + * + * STD_FUSE_DIE_ID_0 0x4A00 2200 + * ID_CODE 0x4A00 2204 (this is the only one we need) + * STD_FUSE_DIE_ID_1 0x4A00 2208 + * STD_FUSE_DIE_ID_2 0x4A00 220C + * STD_FUSE_DIE_ID_3 0x4A00 2210 + * STD_FUSE_PROD_ID_0 0x4A00 2214 + * STD_FUSE_PROD_ID_1 0x4A00 2218 + */ + id_code = REG_READ32(OMAP44XX_L4_CORE_VBASE + OMAP4_ID_CODE); + + hawkeye = ((id_code >> 12) & 0xffff); + revision = ((id_code >> 28) & 0xf); + + /* Apparently according to the linux code there were some ES2.0 samples that + * have the wrong id code and report themselves as ES1.0 silicon. So used + * the ARM cpuid to get the correct revision. + */ + if (revision == 0) { + id_code = cpufunc_id(); + revision = (id_code & 0xf) - 1; + } + + switch (hawkeye) { + case 0xB852: + if (revision == 0) + chip_revision = OMAP4430_REV_ES1_0; + else + chip_revision = OMAP4430_REV_ES2_0; + break; + case 0xB95C: + if (revision == 3) + chip_revision = OMAP4430_REV_ES2_1; + else if (revision == 4) + chip_revision = OMAP4430_REV_ES2_2; + else + chip_revision = OMAP4430_REV_ES2_3; + break; + default: + /* Default to the latest revision if we can't determine type */ + chip_revision = OMAP4430_REV_ES2_3; + break; + } + + printf("OMAP%04x ES%u.%u\n", OMAP_REV_DEVICE(chip_revision), + OMAP_REV_MAJOR(chip_revision), OMAP_REV_MINOR(chip_revision)); +} + +/** + * omap3_get_revision - determines omap3 revision + * + * Reads the registers to determine the revision of the chip we are currently + * running on. Stores the information in global variables. + * + * WARNING: This function currently only really works for OMAP3530 devices. + * + * + * + */ +static void +omap3_get_revision(void) +{ + uint32_t id_code; + uint32_t revision; + uint32_t hawkeye; + + /* The chip revsion is read from the device identification registers and + * the JTAG (?) tap registers, which are located in address 0x4A00_2200 to + * 0x4A00_2218. This is part of the L4_CORE memory range and should have + * been mapped in by the machdep.c code. + * + * CONTROL_IDCODE 0x4830 A204 (this is the only one we need) + * + * + */ + id_code = REG_READ32(OMAP35XX_L4_WAKEUP_VBASE + OMAP3_ID_CODE); + + hawkeye = ((id_code >> 12) & 0xffff); + revision = ((id_code >> 28) & 0xf); + + switch (hawkeye) { + case 0xB6D6: + chip_revision = OMAP3350_REV_ES1_0; + break; + case 0xB7AE: + if (revision == 1) + chip_revision = OMAP3530_REV_ES2_0; + else if (revision == 2) + chip_revision = OMAP3530_REV_ES2_1; + else if (revision == 3) + chip_revision = OMAP3530_REV_ES3_0; + else if (revision == 4) + chip_revision = OMAP3530_REV_ES3_1; + else if (revision == 7) + chip_revision = OMAP3530_REV_ES3_1_2; + break; + default: + /* Default to the latest revision if we can't determine type */ + chip_revision = OMAP3530_REV_ES3_1_2; + break; + } + + printf("OMAP%04x ES%u.%u\n", OMAP_REV_DEVICE(chip_revision), + OMAP_REV_MAJOR(chip_revision), OMAP_REV_MINOR(chip_revision)); +} + +/** + * omap_cpu_ident - attempts to identify the chip we are running on + * @dummy: ignored + * + * This function is called before any of the driver are initialised, however + * the basic virt to phys maps have been setup in machdep.c so we can still + * access the required registers, we just have to use direct register reads + * and writes rather than going through the bus stuff. + * + * + */ +static void +omap_cpu_ident(void *dummy) +{ + switch(omap_chip()) { + case CHIP_OMAP_3: + omap3_get_revision(); + break; + case CHIP_OMAP_4: + omap4_get_revision(); + break; + default: + panic("Unknown OMAP chip type, fixme!\n"); + } +} + +SYSINIT(omap_cpu_ident, SI_SUB_CPU, SI_ORDER_SECOND, omap_cpu_ident, NULL); Index: projects/armv6/sys/arm/omap/omap_cpuid.h =================================================================== --- projects/armv6/sys/arm/omap/omap_cpuid.h (nonexistent) +++ projects/armv6/sys/arm/omap/omap_cpuid.h (revision 230362) @@ -0,0 +1,71 @@ +/*- + * Copyright (c) 2011 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _OMAP_CPUID_H_ +#define _OMAP_CPUID_H_ + +#define OMAP_MAKEREV(d, a, b, c) \ + (uint32_t)(((d) << 16) | (((a) & 0xf) << 8) | (((b) & 0xf) << 4) | ((c) & 0xf)) + +#define OMAP_REV_DEVICE(x) (((x) >> 16) & 0xffff) +#define OMAP_REV_MAJOR(x) (((x) >> 8) & 0xf) +#define OMAP_REV_MINOR(x) (((x) >> 4) & 0xf) +#define OMAP_REV_MINOR_MINOR(x) (((x) >> 0) & 0xf) + +#define OMAP3530_DEV 0x3530 +#define OMAP4430_DEV 0x4430 + +#define OMAP3350_REV_ES1_0 OMAP_MAKEREV(OMAP3530_DEV, 1, 0, 0) +#define OMAP3530_REV_ES2_0 OMAP_MAKEREV(OMAP3530_DEV, 2, 0, 0) +#define OMAP3530_REV_ES2_1 OMAP_MAKEREV(OMAP3530_DEV, 2, 1, 0) +#define OMAP3530_REV_ES3_0 OMAP_MAKEREV(OMAP3530_DEV, 3, 0, 0) +#define OMAP3530_REV_ES3_1 OMAP_MAKEREV(OMAP3530_DEV, 3, 1, 0) +#define OMAP3530_REV_ES3_1_2 OMAP_MAKEREV(OMAP3530_DEV, 3, 1, 2) + +#define OMAP4430_REV_ES1_0 OMAP_MAKEREV(OMAP4430_DEV, 1, 0, 0) +#define OMAP4430_REV_ES2_0 OMAP_MAKEREV(OMAP4430_DEV, 2, 0, 0) +#define OMAP4430_REV_ES2_1 OMAP_MAKEREV(OMAP4430_DEV, 2, 1, 0) +#define OMAP4430_REV_ES2_2 OMAP_MAKEREV(OMAP4430_DEV, 2, 2, 0) +#define OMAP4430_REV_ES2_3 OMAP_MAKEREV(OMAP4430_DEV, 2, 3, 0) + +#define CHIP_OMAP_3 0 +#define CHIP_OMAP_4 1 + +static __inline int omap_chip(void) +{ +#if defined(SOC_OMAP4) + return CHIP_OMAP_4; +#elif defined(SOC_OMAP3) + return CHIP_OMAP_3; +#else +# error OMAP chip type not defined, ensure SOC_OMAPxxxx is defined +#endif +} + +uint32_t omap_revision(void); + +#endif /* _OMAP_CPUID_H_ */ Index: projects/armv6/sys/arm/omap/omap_if.m =================================================================== --- projects/armv6/sys/arm/omap/omap_if.m (nonexistent) +++ projects/armv6/sys/arm/omap/omap_if.m (revision 230362) @@ -0,0 +1,58 @@ +#- +# Copyright (c) 2012 Oleksandr Tymoshenko +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# $FreeBSD$ +# + +#include + +#include +#include + +INTERFACE omap; + +# +# read SCM register +# +METHOD uint16_t scm_reads { + device_t dev; + bus_size_t off; +}; + +# +# write SCM register +# +METHOD void scm_writes { + device_t dev; + bus_size_t off; + uint16_t val; +}; + +# +# Request reset from PRCM module +# +METHOD void prcm_reset { + device_t dev; +}; Index: projects/armv6/sys/arm/omap/omap_machdep.c =================================================================== --- projects/armv6/sys/arm/omap/omap_machdep.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap_machdep.c (revision 230362) @@ -0,0 +1,547 @@ +/*- + * Copyright (c) 2009 Guillaume Ballet + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#define _ARM32_BUS_DMA_PRIVATE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define DEBUG_INITARM +#define VERBOSE_INIT_ARM + +#include +#include + +#if defined(SOC_OMAP4) +#include +const struct pmap_devmap omap_devmap[] = { + /* + * Add the main memory areas, + */ +/* + { + .pd_va = OMAP44XX_L3_EMU_VBASE, + .pd_pa = OMAP44XX_L3_EMU_HWBASE, + .pd_size = OMAP44XX_L3_EMU_SIZE, + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, + .pd_cache = PTE_DEVICE + }, +*/ + + /* SDRAM EMIF register set, mapped as read-only for now */ + { + .pd_va = OMAP44XX_L3_EMIF1_VBASE, + .pd_pa = OMAP44XX_L3_EMIF1_HWBASE, + .pd_size = OMAP44XX_L3_EMIF1_SIZE, + .pd_prot = VM_PROT_READ, + .pd_cache = PTE_NOCACHE + }, + { + .pd_va = OMAP44XX_L3_EMIF2_VBASE, + .pd_pa = OMAP44XX_L3_EMIF2_HWBASE, + .pd_size = OMAP44XX_L3_EMIF2_SIZE, + .pd_prot = VM_PROT_READ, + .pd_cache = PTE_NOCACHE + }, + + /* General memory areas */ + { + .pd_va = OMAP44XX_L4_CORE_VBASE, + .pd_pa = OMAP44XX_L4_CORE_HWBASE, + .pd_size = OMAP44XX_L4_CORE_SIZE, + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, + .pd_cache = PTE_NOCACHE + }, + { + .pd_va = OMAP44XX_L4_PERIPH_VBASE, + .pd_pa = OMAP44XX_L4_PERIPH_HWBASE, + .pd_size = OMAP44XX_L4_PERIPH_SIZE, + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, + .pd_cache = PTE_NOCACHE + }, + { + .pd_va = OMAP44XX_L4_ABE_VBASE, + .pd_pa = OMAP44XX_L4_ABE_HWBASE, + .pd_size = OMAP44XX_L4_ABE_SIZE, + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, + .pd_cache = PTE_NOCACHE + }, + { 0, 0, 0, 0, 0 } /* Array terminator */ +}; + +#elif defined(SOC_OMAP3) +#include +const struct pmap_devmap omap_devmap[] = { + /* + * For the moment, map devices with PA==VA. + */ + { + /* 16MB of L4, covering all L4 core registers */ + .pd_va = OMAP35XX_L4_CORE_VBASE, + .pd_pa = OMAP35XX_L4_CORE_HWBASE, + .pd_size = OMAP35XX_L4_CORE_SIZE, + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, + .pd_cache = PTE_NOCACHE + }, + { + /* 1MB of L4, covering the periph registers */ + .pd_va = OMAP35XX_L4_PERIPH_VBASE, + .pd_pa = OMAP35XX_L4_PERIPH_HWBASE, + .pd_size = OMAP35XX_L4_PERIPH_SIZE, + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, + .pd_cache = PTE_NOCACHE + }, + { + /* 64Kb of L3, covering the SDRAM controller registers */ + .pd_va = OMAP35XX_SDRC_VBASE, + .pd_pa = OMAP35XX_SDRC_HWBASE, + .pd_size = OMAP35XX_SDRC_SIZE, + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, + .pd_cache = PTE_NOCACHE + }, +#if 0 + { + /* 64Kb of L3, covering the SDRAM controller registers */ + .pd_va = OMAP35XX_L3_VBASE, + .pd_pa = OMAP35XX_L3_HWBASE, + .pd_size = OMAP35XX_L3_SIZE, + .pd_prot = VM_PROT_READ|VM_PROT_WRITE, + .pd_cache = PTE_NOCACHE + }, +#endif + { 0, 0, 0, 0, 0 } /* Array terminator */ +}; + +#else +#error OMAP chip type not defined + +#endif + +#ifdef VERBOSE_INIT_ARM +#define DPRINTF(x) +#else +#define DPRINTF(x) +#endif + +/* Physical page ranges */ +vm_paddr_t phys_avail[4]; +vm_paddr_t dump_avail[4]; + +struct pv_addr systempage; + +#define FIQ_STACK_SIZE 1 +#define IRQ_STACK_SIZE 1 +#define ABT_STACK_SIZE 1 +#define UND_STACK_SIZE 1 + +extern int _start[]; +extern int _end[]; + +extern void early_putchar(unsigned char); +extern void early_putstr(unsigned char *); +extern void early_printf(const char *fmt, ...); +extern void early_print_init(uint32_t hw_addr, uint32_t virt_addr); + +extern u_int data_abort_handler_address; +extern u_int prefetch_abort_handler_address; +extern u_int undefined_handler_address; + +static struct pv_addr fiqstack; /* Stack page descriptors for all modes */ +static struct pv_addr msgbuf; +static struct pv_addr irqstack; +static struct pv_addr undstack; +static struct pv_addr abtstack; +static struct pv_addr kernelstack; +static struct pv_addr kernel_l1pt; /* Level-1 page table entry */ + +#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ +#define KERNEL_PT_KERN 1 +#define KERNEL_PT_KERN_NUM 22 +#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */ +#define KERNEL_PT_AFKERNEL_NUM 5 + +/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ +#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) + +static struct pv_addr kernel_page_tables[NUM_KERNEL_PTS]; /* Level-2 page table entries for the kernel */ +static struct trapframe proc0_tf; + +#define PHYS2VIRT(x) ((x - KERNPHYSADDR) + KERNVIRTADDR) +#define VIRT2PHYS(x) ((x - KERNVIRTADDR) + KERNPHYSADDR) + +/* Macro stolen from the Xscale part, used to simplify TLB allocation */ +#define valloc_pages(var, np) do { \ + alloc_pages((var).pv_pa, (np)); \ + (var).pv_va = PHYS2VIRT((var).pv_pa); \ + DPRINTF(("va=%p pa=%p\n", (void*)(var).pv_va, \ + (void*)(var).pv_pa)); \ +} while(0) + +#define alloc_pages(var, np) do { \ + (var) = freemempos; \ + freemempos += (np * PAGE_SIZE); \ + memset((char *)(var), 0, ((np) * PAGE_SIZE)); \ +} while(0) + +#define round_L_page(x) (((x) + L2_L_OFFSET) & L2_L_FRAME) + +#define VERBOSE_INIT_ARM + +static void * +initarm_boilerplate(void *arg1, void *arg2) +{ + vm_offset_t freemempos; + vm_offset_t freemem_pt; + vm_offset_t lastaddr; + vm_offset_t offset; + uint32_t i, j; + uint32_t sdram_size; + uint32_t l1pagetable; + size_t textsize; + size_t totalsize; + + /* + * Sets the CPU functions based on the CPU ID, this code is all + * in the cpufunc.c file. The function sets the cpufunc structure + * to match the machine and also initialises the pmap/pte code. + */ + set_cpufuncs(); + + /* + * fake_preload_metadata() creates a fake boot descriptor table and + * returns the last address in the kernel. + */ + lastaddr = fake_preload_metadata(); + + /* + * Initialize the MI portions of a struct per cpu structure. + */ + pcpu_init(pcpup, 0, sizeof(struct pcpu)); + PCPU_SET(curthread, &thread0); + init_param1(); + + /* + * Initialize freemempos. Pages are allocated from the end of the RAM's + * first 64MB, as it is what is covered by the default TLB in locore.S. + */ + freemempos = VIRT2PHYS(round_L_page(lastaddr)); + + /* Reserve L1 table pages now, as freemempos is 64K-aligned */ + valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); + + /* + * Reserve the paging system pages, page #0 is reserved as a L2 table for + * the exception vector. Now allocate L2 page tables; they are linked to L1 below + */ + for (i = 0; i < NUM_KERNEL_PTS; ++i) { + j = (i % (PAGE_SIZE / L2_TABLE_SIZE_REAL)); + + if (j == 0) + valloc_pages(kernel_page_tables[i], L2_TABLE_SIZE / PAGE_SIZE); + else { + kernel_page_tables[i].pv_pa = kernel_page_tables[i - j].pv_pa + + (j * L2_TABLE_SIZE_REAL); + kernel_page_tables[i].pv_va = kernel_page_tables[i - j].pv_va + + (j * L2_TABLE_SIZE_REAL); + } + } + + /* base of allocated pt's */ + freemem_pt = freemempos; + + /* + * Allocate a page for the system page mapped to V0x00000000. This page + * will just contain the system vectors and can be shared by all processes. + * This is where the interrupt vector is stored. + */ + valloc_pages(systempage, 1); + systempage.pv_va = ARM_VECTORS_HIGH; + + /* Allocate dynamic per-cpu area. */ + /* TODO: valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); */ + /* TODO: dpcpu_init((void *)dpcpu.pv_va, 0); */ + + + /* Allocate stacks for all modes */ + valloc_pages(fiqstack, FIQ_STACK_SIZE); + valloc_pages(irqstack, IRQ_STACK_SIZE); + valloc_pages(abtstack, ABT_STACK_SIZE); + valloc_pages(undstack, UND_STACK_SIZE); + valloc_pages(kernelstack, KSTACK_PAGES + 1); + valloc_pages(msgbuf, round_page(msgbufsize) / PAGE_SIZE); + + /* Build the TLBs */ + + /* + * Now construct the L1 page table. First map the L2 + * page tables into the L1 so we can replace L1 mappings + * later on if necessary + */ + l1pagetable = kernel_l1pt.pv_va; + + /* L2 table for the exception vector */ + pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x100000 - 1), + &kernel_page_tables[0]); + + /* Insert a reference to the kernel L2 page tables into the L1 page. */ + for (i=1; ipcb_flags = 0; + thread0.td_frame = &proc0_tf; + pcpup->pc_curpcb = thread0.td_pcb; + +#ifdef VERBOSE_INIT_ARM + printf("\nThread-0 stack=0x%08x pcb=0x%08x\n", (unsigned int)thread0.td_kstack, (unsigned int)thread0.td_pcb); +#endif + + /* Exception vector */ + arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); + +#ifdef VERBOSE_INIT_ARM + printf("Exception vector at (0x%08x)\n", ((unsigned int *)systempage.pv_va)[0]); +#endif + + /* First unbacked address of KVM */ + pmap_curmaxkvaddr = KERNVIRTADDR + 0x100000 * NUM_KERNEL_PTS; +#ifdef VERBOSE_INIT_ARM + printf("pmap_curmaxkvaddr = 0x%08x\n", pmap_curmaxkvaddr); +#endif + + /* Get the size of the SDRAM, this is typically defined in the SoC specific + * files (i.e. omap44xx.c) + */ + sdram_size = omap_sdram_size(); +#ifdef VERBOSE_INIT_ARM + printf("\nSDRAM size 0x%08X, %dMB\n", sdram_size, (sdram_size / 1024 / 1024)); +#endif + + /* Physical ranges of available memory. */ + phys_avail[0] = freemempos; + phys_avail[1] = PHYSADDR + sdram_size; + phys_avail[2] = 0; + phys_avail[3] = 0; + + dump_avail[0] = PHYSADDR; + dump_avail[1] = PHYSADDR + sdram_size; + dump_avail[2] = 0; + dump_avail[3] = 0; + + physmem = sdram_size / PAGE_SIZE; + + pmap_bootstrap((freemempos&0x00ffffff)|0xc0000000, /* start address */ + 0xe8000000, /* end address, min adress for device stuff */ + &kernel_l1pt); + + init_param2(physmem); + + /* Locking system */ + mutex_init(); + + msgbufp = (void*)msgbuf.pv_va; + msgbufinit(msgbufp, msgbufsize); + + /* Kernel debugger */ + kdb_init(); + vector_page_setprot(VM_PROT_READ); + + /* initarm returns the address of the kernel stack */ + return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - + sizeof(struct pcb))); +} + +void * +initarm(void *arg1, void *arg2) +{ + return initarm_boilerplate(arg1, arg2); +} + +struct arm32_dma_range * +bus_dma_get_range(void) +{ + /* TODO: Need implementation ? */ + return (NULL); +} + +int +bus_dma_get_range_nb(void) +{ + /* TODO: Need implementation ? */ + return (0); +} + +/** + * cpu_reset + * + * Called by the system to reset the CPU - obvious really + * + */ +void +cpu_reset() +{ + omap_prcm_reset(); + printf("Reset failed!\n"); + while (1); +} Index: projects/armv6/sys/arm/omap/omap_prcm.c =================================================================== --- projects/armv6/sys/arm/omap/omap_prcm.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap_prcm.c (revision 230362) @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2010 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Ben Gray. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * Power, Reset and Clock Managment Module + * + * This is a very simple driver wrapper around the PRCM set of registers in + * the OMAP3 chip. It allows you to turn on and off things like the functional + * and interface clocks to the various on-chip modules. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "omap_if.h" + +static device_t prcm_dev; +static struct mtx prcm_mtx; + +/** + * Structure that stores the driver context. + * + * This structure is allocated during driver attach, it is not designed to be + * deallocated and a pointer to it is stored globally (g_omap3_prcm_softc). + */ +struct omap_prcm_softc { + device_t sc_dev; + + /* + * The memory resource(s) for the PRCM register set, when the device is + * created the caller can assign up to 4 memory regions. + */ + struct resource* sc_mem_res[4]; +}; + + +/** + * omap_clk_devmap - Array of clock devices, should be defined one per SoC + * + * This array is typically defined in one of the targeted omap??_prcm_clk.c + * files and is specific to the given SoC platform. Each entry in the array + * corresponds to an individual clock device. + */ +extern struct omap_clock_dev omap_clk_devmap[]; + + + +/** + * Macros for driver mutex locking + */ +#define OMAP_PRCM_LOCK mtx_lock(&prcm_mtx) +#define OMAP_PRCM_UNLOCK mtx_unlock(&prcm_mtx) +#define OMAP_PRCM_LOCK_DESTROY mtx_destroy(&prcm_mtx) +#define OMAP_PRCM_ASSERT_LOCKED mtx_assert(&prcm_mtx, MA_OWNED) +#define OMAP_PRCM_ASSERT_UNLOCKED mtx_assert(&prcm_mtx, MA_NOTOWNED) + +void +omap_prcm_init(device_t dev) +{ + prcm_dev = dev; + + mtx_init(&prcm_mtx, device_get_nameunit(dev), "omap_prcm", MTX_DEF); +} + +/** + * omap_prcm_clk_dev - returns a pointer to the clock device with given id + * @clk: the ID of the clock device to get + * + * Simply iterates through the clk_devmap global array and returns a pointer + * to the clock device if found. + * + * LOCKING: + * None + * + * RETURNS: + * The pointer to the clock device on success, on failure NULL is returned. + */ +static struct omap_clock_dev * +omap_prcm_clk_dev(clk_ident_t clk) +{ + struct omap_clock_dev *clk_dev; + + /* Find the clock within the devmap - it's a bit inefficent having a for + * loop for this, but this function should only called when a driver is + * being activated so IMHO not a big issue. + */ + clk_dev = &(omap_clk_devmap[0]); + while (clk_dev->id != INVALID_CLK_IDENT) { + if (clk_dev->id == clk) { + return (clk_dev); + } + clk_dev++; + } + + /* Sanity check we managed to find the clock */ + device_printf(prcm_dev, "Error: Failed to find clock device (%d)\n", clk); + return (NULL); +} + +/** + * omap_prcm_clk_valid - enables a clock for a particular module + * @clk: identifier for the module to enable, see omap_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1_ICLK or OMAP3_MODULE_GPTIMER10_FCLK. + * + * This function can enable either a functional or interface clock. + * + * The real work done to enable the clock is really done in the callback + * function associated with the clock, this function is simply a wrapper + * around that. + * + * LOCKING: + * Internally locks the driver context. + * + * RETURNS: + * Returns 0 on success or positive error code on failure. + */ +int +omap_prcm_clk_valid(clk_ident_t clk) +{ + int ret = 0; + + /* Sanity check */ + if (prcm_dev == NULL) { + device_printf(prcm_dev, "Error: PRCM module not setup (%s)\n", __func__); + return (EINVAL); + } + + OMAP_PRCM_LOCK; + + if (omap_prcm_clk_dev(clk) == NULL) + ret = EINVAL; + + OMAP_PRCM_UNLOCK; + + return (ret); +} + + +/** + * omap_prcm_clk_enable - enables a clock for a particular module + * @clk: identifier for the module to enable, see omap_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1_ICLK or OMAP3_MODULE_GPTIMER10_FCLK. + * + * This function can enable either a functional or interface clock. + * + * The real work done to enable the clock is really done in the callback + * function associated with the clock, this function is simply a wrapper + * around that. + * + * LOCKING: + * Internally locks the driver context. + * + * RETURNS: + * Returns 0 on success or positive error code on failure. + */ +int +omap_prcm_clk_enable(clk_ident_t clk) +{ + struct omap_clock_dev *clk_dev; + int ret; + + /* Sanity check */ + if (prcm_dev == NULL) { + device_printf(prcm_dev, "Error: PRCM module not setup (%s)\n", __func__); + return (EINVAL); + } + + OMAP_PRCM_LOCK; + + /* Find the clock within the devmap - it's a bit inefficent having a for + * loop for this, but this function should only called when a driver is + * being activated so IMHO not a big issue. + */ + clk_dev = omap_prcm_clk_dev(clk); + + /* Sanity check we managed to find the clock */ + if (clk_dev == NULL) { + OMAP_PRCM_UNLOCK; + return (EINVAL); + } + + /* Activate the clock */ + if (clk_dev->clk_activate) + ret = clk_dev->clk_activate(prcm_dev, clk_dev); + else + ret = EINVAL; + + + OMAP_PRCM_UNLOCK; + + return (ret); +} + + +/** + * omap_prcm_clk_disable - disables a clock for a particular module + * @clk: identifier for the module to enable, see omap_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1_ICLK or OMAP3_MODULE_GPTIMER10_FCLK. + * + * This function can enable either a functional or interface clock. + * + * The real work done to enable the clock is really done in the callback + * function associated with the clock, this function is simply a wrapper + * around that. + * + * LOCKING: + * Internally locks the driver context. + * + * RETURNS: + * Returns 0 on success or positive error code on failure. + */ +int +omap_prcm_clk_disable(clk_ident_t clk) +{ + struct omap_clock_dev *clk_dev; + int ret; + + /* Sanity check */ + if (prcm_dev == NULL) { + device_printf(prcm_dev, "Error: PRCM module not setup (%s)\n", __func__); + return (EINVAL); + } + + OMAP_PRCM_LOCK; + + /* Find the clock within the devmap - it's a bit inefficent having a for + * loop for this, but this function should only called when a driver is + * being activated so IMHO not a big issue. + */ + clk_dev = omap_prcm_clk_dev(clk); + + /* Sanity check we managed to find the clock */ + if (clk_dev == NULL) { + OMAP_PRCM_UNLOCK; + return (EINVAL); + } + + /* Activate the clock */ + if (clk_dev->clk_deactivate) + ret = clk_dev->clk_deactivate(prcm_dev, clk_dev); + else + ret = EINVAL; + + + OMAP_PRCM_UNLOCK; + + return (ret); +} + +/** + * omap_prcm_clk_set_source - sets the source + * @clk: identifier for the module to enable, see omap_prcm.h for a list + * of possible modules. + * Example: OMAP3_MODULE_MMC1_ICLK or OMAP3_MODULE_GPTIMER10_FCLK. + * + * This function can enable either a functional or interface clock. + * + * The real work done to enable the clock is really done in the callback + * function associated with the clock, this function is simply a wrapper + * around that. + * + * LOCKING: + * Internally locks the driver context. + * + * RETURNS: + * Returns 0 on success or positive error code on failure. + */ +int +omap_prcm_clk_set_source(clk_ident_t clk, clk_src_t clksrc) +{ + struct omap_clock_dev *clk_dev; + int ret; + + /* Sanity check */ + if (prcm_dev == NULL) { + device_printf(prcm_dev, "Error: PRCM module not setup (%s)\n", __func__); + return (EINVAL); + } + + OMAP_PRCM_LOCK; + + /* Find the clock within the devmap - it's a bit inefficent having a for + * loop for this, but this function should only called when a driver is + * being activated so IMHO not a big issue. + */ + clk_dev = omap_prcm_clk_dev(clk); + + /* Sanity check we managed to find the clock */ + if (clk_dev == NULL) { + OMAP_PRCM_UNLOCK; + return (EINVAL); + } + + /* Activate the clock */ + if (clk_dev->clk_set_source) + ret = clk_dev->clk_set_source(prcm_dev, clk_dev, clksrc); + else + ret = EINVAL; + + + OMAP_PRCM_UNLOCK; + + return (ret); +} + + +/** + * omap_prcm_clk_get_source_freq - gets the source clock frequency + * @clk: identifier for the module to enable, see omap_prcm.h for a list + * of possible modules. + * @freq: pointer to an integer that upon return will contain the src freq + * + * This function returns the frequency of the source clock. + * + * The real work done to enable the clock is really done in the callback + * function associated with the clock, this function is simply a wrapper + * around that. + * + * LOCKING: + * Internally locks the driver context. + * + * RETURNS: + * Returns 0 on success or positive error code on failure. + */ +int +omap_prcm_clk_get_source_freq(clk_ident_t clk, unsigned int *freq) +{ + struct omap_clock_dev *clk_dev; + int ret; + + /* Sanity check */ + if (prcm_dev == NULL) { + device_printf(prcm_dev, "Error: PRCM module not setup (%s)\n", __func__); + return (EINVAL); + } + + OMAP_PRCM_LOCK; + + /* Find the clock within the devmap - it's a bit inefficent having a for + * loop for this, but this function should only called when a driver is + * being activated so IMHO not a big issue. + */ + clk_dev = omap_prcm_clk_dev(clk); + + /* Sanity check we managed to find the clock */ + if (clk_dev == NULL) { + OMAP_PRCM_UNLOCK; + return (EINVAL); + } + + /* Get the source frequency of the clock */ + if (clk_dev->clk_get_source_freq) + ret = clk_dev->clk_get_source_freq(prcm_dev, clk_dev, freq); + else + ret = EINVAL; + + OMAP_PRCM_UNLOCK; + + return (ret); +} + +void +omap_prcm_reset() +{ + if (prcm_dev == NULL) { + device_printf(prcm_dev, "Error: PRCM module not setup (%s)\n", __func__); + return; + } + + OMAP_PRCM_RESET(prcm_dev); +} Index: projects/armv6/sys/arm/omap/omap_prcm.h =================================================================== --- projects/armv6/sys/arm/omap/omap_prcm.h (nonexistent) +++ projects/armv6/sys/arm/omap/omap_prcm.h (revision 230362) @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2010 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Ben Gray. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + * Texas Instruments - OMAP3xxx series processors + * + * Reference: + * OMAP35x Applications Processor + * Technical Reference Manual + * (omap35xx_techref.pdf) + */ +#ifndef _OMAP_PRCM_H_ +#define _OMAP_PRCM_H_ + +typedef enum { + + /* System clocks, typically you can only call omap_prcm_clk_get_source_freq() + * on these clocks as they are enabled by default. + */ + SYS_CLK = 1, + + /* The MPU (ARM) core clock */ + MPU_CLK = 20, + + /* MMC modules */ + MMC1_CLK = 100, + MMC2_CLK, + MMC3_CLK, + MMC4_CLK, + MMC5_CLK, + + /* I2C modules */ + I2C1_CLK = 200, + I2C2_CLK, + I2C3_CLK, + I2C4_CLK, + + /* USB module(s) */ + USBTLL_CLK = 300, + USBHSHOST_CLK, + USBFSHOST_CLK, + USBP1_PHY_CLK, + USBP2_PHY_CLK, + USBP1_UTMI_CLK, + USBP2_UTMI_CLK, + USBP1_HSIC_CLK, + USBP2_HSIC_CLK, + + /* UART modules */ + UART1_CLK = 400, + UART2_CLK, + UART3_CLK, + UART4_CLK, + + /* General purpose timer modules */ + GPTIMER1_CLK = 500, + GPTIMER2_CLK, + GPTIMER3_CLK, + GPTIMER4_CLK, + GPTIMER5_CLK, + GPTIMER6_CLK, + GPTIMER7_CLK, + GPTIMER8_CLK, + GPTIMER9_CLK, + GPTIMER10_CLK, + GPTIMER11_CLK, + GPTIMER12_CLK, + + /* McBSP module(s) */ + MCBSP1_CLK = 600, + MCBSP2_CLK, + MCBSP3_CLK, + MCBSP4_CLK, + MCBSP5_CLK, + + /* General purpose I/O modules */ + GPIO1_CLK = 700, + GPIO2_CLK, + GPIO3_CLK, + GPIO4_CLK, + GPIO5_CLK, + GPIO6_CLK, + + /* sDMA module */ + SDMA_CLK = 800, + + INVALID_CLK_IDENT + +} clk_ident_t; + +/* + * + */ +typedef enum { + SYSCLK_CLK, /* System clock */ + EXT_CLK, + + F32KHZ_CLK, /* 32KHz clock */ + F48MHZ_CLK, /* 48MHz clock */ + F64MHZ_CLK, /* 64MHz clock */ + F96MHZ_CLK, /* 96MHz clock */ + +} clk_src_t; + +struct omap_clock_dev { + /* The profile of the timer */ + clk_ident_t id; + + /* A bunch of callbacks associated with the clock device */ + int (*clk_activate)(device_t dev, struct omap_clock_dev *clkdev); + int (*clk_deactivate)(device_t dev, struct omap_clock_dev *clkdev); + int (*clk_set_source)(device_t dev, struct omap_clock_dev *clkdev, + clk_src_t clksrc); + int (*clk_accessible)(device_t dev, struct omap_clock_dev *clkdev); + int (*clk_get_source_freq)(device_t dev, struct omap_clock_dev *clkdev, + unsigned int *freq); + +}; + +/* Setup PRCM device to be used in API calls */ +void omap_prcm_init(device_t dev); +int omap_prcm_clk_valid(clk_ident_t clk); +int omap_prcm_clk_enable(clk_ident_t clk); +int omap_prcm_clk_disable(clk_ident_t clk); +int omap_prcm_clk_accessible(clk_ident_t clk); +int omap_prcm_clk_disable_autoidle(clk_ident_t clk); +int omap_prcm_clk_set_source(clk_ident_t clk, clk_src_t clksrc); +int omap_prcm_clk_get_source_freq(clk_ident_t clk, unsigned int *freq); +void omap_prcm_reset(void); + +#endif /* _OMAP_PRCM_H_ */ Index: projects/armv6/sys/arm/omap/omap_scm.c =================================================================== --- projects/armv6/sys/arm/omap/omap_scm.c (nonexistent) +++ projects/armv6/sys/arm/omap/omap_scm.c (revision 230362) @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2010 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Ben Gray. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * SCM - System Control Module + * + * Hopefully in the end this module will contain a bunch of utility functions + * for configuring and querying the general system control registers, but for + * now it only does pin(pad) multiplexing. + * + * This is different from the GPIO module in that it is used to configure the + * pins between modules not just GPIO input/output. + * + * This file contains the generic top level driver, however it relies on chip + * specific settings and therefore expects an array of omap_scm_padconf structs + * call omap_padconf_devmap to be located somewhere in the kernel. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "omap_scm.h" +#include "omap_if.h" + +/** + * omap_padconf_devmap - Array of pins, should be defined one per SoC + * + * This array is typically defined in one of the targeted omap??_scm_pinumx.c + * files and is specific to the given SoC platform. Each entry in the array + * corresponds to an individual pin. + */ +extern const struct omap_scm_padconf omap_padconf_devmap[]; + +/** + * Macros for driver mutex locking + */ +#define OMAP_SCM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) +#define OMAP_SCM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) +#define OMAP_SCM_LOCK_INIT(_sc) \ + mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ + "omap_scm", MTX_DEF) +#define OMAP_SCM_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) +#define OMAP_SCM_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) +#define OMAP_SCM_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) + +/** + * omap_scm_padconf_from_name - searches the list of pads and returns entry + * with matching ball name. + * @ballname: the name of the ball + * + * RETURNS: + * A pointer to the matching padconf or NULL if the ball wasn't found. + */ +static const struct omap_scm_padconf* +omap_scm_padconf_from_name(const char *ballname) +{ + const struct omap_scm_padconf *padconf; + + padconf = omap_padconf_devmap; + while (padconf->ballname != NULL) { + if (strcmp(ballname, padconf->ballname) == 0) + return(padconf); + padconf++; + } + + return (NULL); +} + +/** + * omap_scm_padconf_set_internal - sets the muxmode and state for a pad/pin + * @padconf: pointer to the pad structure + * @muxmode: the name of the mode to use for the pin, i.e. "uart1_rx" + * @state: the state to put the pad/pin in, i.e. PADCONF_PIN_??? + * + * + * LOCKING: + * Internally locks it's own context. + * + * RETURNS: + * 0 on success. + * EINVAL if pin requested is outside valid range or already in use. + */ +static int +omap_scm_padconf_set_internal(device_t dev, + const struct omap_scm_padconf *padconf, + const char *muxmode, unsigned int state) +{ + unsigned int mode; + uint16_t reg_val; + + /* populate the new value for the PADCONF register */ + reg_val = (uint16_t)(state & CONTROL_PADCONF_SATE_MASK); + + /* find the new mode requested */ + for (mode = 0; mode < 8; mode++) { + if ((padconf->muxmodes[mode] != NULL) && + (strcmp(padconf->muxmodes[mode], muxmode) == 0)) { + break; + } + } + + /* couldn't find the mux mode */ + if (mode >= 8) + return (EINVAL); + + /* set the mux mode */ + reg_val |= (uint16_t)(mode & CONTROL_PADCONF_MUXMODE_MASK); + + printf("setting internal %x for %s\n", reg_val, muxmode); + /* write the register value (16-bit writes) */ + OMAP_SCM_WRITES(dev, padconf->reg_off, reg_val); + + return (0); +} + +/** + * omap_scm_padconf_set - sets the muxmode and state for a pad/pin + * @padname: the name of the pad, i.e. "c12" + * @muxmode: the name of the mode to use for the pin, i.e. "uart1_rx" + * @state: the state to put the pad/pin in, i.e. PADCONF_PIN_??? + * + * + * LOCKING: + * Internally locks it's own context. + * + * RETURNS: + * 0 on success. + * EINVAL if pin requested is outside valid range or already in use. + */ +int +omap_scm_padconf_set(device_t dev, const char *padname, + const char *muxmode, unsigned int state) +{ + const struct omap_scm_padconf *padconf; + + /* find the pin in the devmap */ + padconf = omap_scm_padconf_from_name(padname); + if (padconf == NULL) + return (EINVAL); + + return (omap_scm_padconf_set_internal(dev, padconf, muxmode, state)); +} + +/** + * omap_scm_padconf_get - gets the muxmode and state for a pad/pin + * @padname: the name of the pad, i.e. "c12" + * @muxmode: upon return will contain the name of the muxmode of the pin + * @state: upon return will contain the state of the the pad/pin + * + * + * LOCKING: + * Internally locks it's own context. + * + * RETURNS: + * 0 on success. + * EINVAL if pin requested is outside valid range or already in use. + */ +int +omap_scm_padconf_get(device_t dev, const char *padname, const char **muxmode, + unsigned int *state) +{ + const struct omap_scm_padconf *padconf; + uint16_t reg_val; + + /* find the pin in the devmap */ + padconf = omap_scm_padconf_from_name(padname); + if (padconf == NULL) + return (EINVAL); + + /* read the register value (16-bit reads) */ + reg_val = OMAP_SCM_READS(dev, padconf->reg_off); + + /* save the state */ + if (state) + *state = (reg_val & CONTROL_PADCONF_SATE_MASK); + + /* save the mode */ + if (muxmode) + *muxmode = padconf->muxmodes[(reg_val & CONTROL_PADCONF_MUXMODE_MASK)]; + + return (0); +} + +/** + * omap_scm_padconf_set_gpiomode - converts a pad to GPIO mode. + * @gpio: the GPIO pin number (0-195) + * @state: the state to put the pad/pin in, i.e. PADCONF_PIN_??? + * + * + * + * LOCKING: + * Internally locks it's own context. + * + * RETURNS: + * 0 on success. + * EINVAL if pin requested is outside valid range or already in use. + */ +int +omap_scm_padconf_set_gpiomode(device_t dev, uint32_t gpio, unsigned int state) +{ + const struct omap_scm_padconf *padconf; + uint16_t reg_val; + + /* find the gpio pin in the padconf array */ + padconf = omap_padconf_devmap; + while (padconf->ballname != NULL) { + if (padconf->gpio_pin == gpio) + break; + padconf++; + } + if (padconf->ballname == NULL) + return (EINVAL); + + /* populate the new value for the PADCONF register */ + reg_val = (uint16_t)(state & CONTROL_PADCONF_SATE_MASK); + + /* set the mux mode */ + reg_val |= (uint16_t)(padconf->gpio_mode & CONTROL_PADCONF_MUXMODE_MASK); + + /* write the register value (16-bit writes) */ + OMAP_SCM_WRITES(dev, padconf->reg_off, reg_val); + + return (0); +} + +/** + * omap_scm_padconf_get_gpiomode - gets the current GPIO mode of the pin + * @gpio: the GPIO pin number (0-195) + * @state: upon return will contain the state + * + * + * + * LOCKING: + * Internally locks it's own context. + * + * RETURNS: + * 0 on success. + * EINVAL if pin requested is outside valid range or not configured as GPIO. + */ +int +omap_scm_padconf_get_gpiomode(device_t dev, uint32_t gpio, unsigned int *state) +{ + const struct omap_scm_padconf *padconf; + uint16_t reg_val; + + /* find the gpio pin in the padconf array */ + padconf = omap_padconf_devmap; + while (padconf->ballname != NULL) { + if (padconf->gpio_pin == gpio) + break; + padconf++; + } + if (padconf->ballname == NULL) + return (EINVAL); + + /* read the current register settings */ + reg_val = OMAP_SCM_READS(dev, padconf->reg_off); + + /* check to make sure the pins is configured as GPIO in the first state */ + if ((reg_val & CONTROL_PADCONF_MUXMODE_MASK) != padconf->gpio_mode) + return (EINVAL); + + /* read and store the reset of the state, i.e. pull-up, pull-down, etc */ + if (state) + *state = (reg_val & CONTROL_PADCONF_SATE_MASK); + + return (0); +} + +/** + * omap_scm_padconf_init_from_hints - processes the hints for padconf + * @sc: the driver soft context + * + * + * + * LOCKING: + * Internally locks it's own context. + * + * RETURNS: + * 0 on success. + * EINVAL if pin requested is outside valid range or already in use. + */ +int +omap_scm_padconf_init_from_hints(device_t dev) +{ + const struct omap_scm_padconf *padconf; + int err; + char resname[64]; + const char *resval; + char muxname[64]; + char padstate[64]; + + /* Hint names should be of the form "padconf." */ + strcpy(resname, "padconf."); + + + /* This is very inefficent ... basically we look up every possible pad name + * in the hints. Unfortunatly there doesn't seem to be any way to iterate + * over all the hints for a given device, so instead we have to manually + * probe for the existance of every possible pad. + */ + padconf = omap_padconf_devmap; + while (padconf->ballname != NULL) { + + strncpy(&resname[8], padconf->ballname, 50); + + err = resource_string_value(device_get_name(dev), + device_get_unit(dev), resname, &resval); + if ((err == 0) && (resval != NULL)) { + + /* Found a matching pad/ball name in the hints section, the hint + * should be of the following format: + * : + * i.e. + * usbb1_ulpiphy_stp:output + */ + + /* Read the mux name */ + if (sscanf(resval, "%64[^:]:%64s", muxname, padstate) != 2) { + device_printf(dev, "err: padconf hint for pin \"%s\"" + "is incorrectly formated, ignoring hint.\n", + padconf->ballname); + } + + /* Convert the padstate to a flag and write the values */ + else { + if (strcmp(padstate, "output") == 0) + err = omap_scm_padconf_set_internal(dev, + padconf, muxname, PADCONF_PIN_OUTPUT); + else if (strcmp(padstate, "input") == 0) + err = omap_scm_padconf_set_internal(dev, + padconf, muxname, PADCONF_PIN_INPUT); + else if (strcmp(padstate, "input_pullup") == 0) + err = omap_scm_padconf_set_internal(dev, + padconf, muxname, + PADCONF_PIN_INPUT_PULLUP); + else if (strcmp(padstate, "input_pulldown") == 0) + err = omap_scm_padconf_set_internal(dev, + padconf, muxname, + PADCONF_PIN_INPUT_PULLDOWN); + else + device_printf(dev, "err: padconf hint for pin \"%s\"" + "has incorrectly formated state, ignoring hint.\n", + padconf->ballname); + } + } + + padconf++; + } + + return (0); +} Index: projects/armv6/sys/arm/omap/omap_scm.h =================================================================== --- projects/armv6/sys/arm/omap/omap_scm.h (nonexistent) +++ projects/armv6/sys/arm/omap/omap_scm.h (revision 230362) @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2010 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Ben Gray. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/** + * Functions to configure the PIN multiplexing on the chip. + * + * This is different from the GPIO module in that it is used to configure the + * pins between modules not just GPIO input output. + * + */ +#ifndef _OMAP_SCM_H_ +#define _OMAP_SCM_H_ + +#define CONTROL_PADCONF_WAKEUP_EVENT (1UL << 15) +#define CONTROL_PADCONF_WAKEUP_ENABLE (1UL << 14) +#define CONTROL_PADCONF_OFF_PULL_UP (1UL << 13) +#define CONTROL_PADCONF_OFF_PULL_ENABLE (1UL << 12) +#define CONTROL_PADCONF_OFF_OUT_HIGH (1UL << 11) +#define CONTROL_PADCONF_OFF_OUT_ENABLE (1UL << 10) +#define CONTROL_PADCONF_OFF_ENABLE (1UL << 9) +#define CONTROL_PADCONF_INPUT_ENABLE (1UL << 8) +#define CONTROL_PADCONF_PULL_UP (1UL << 4) +#define CONTROL_PADCONF_PULL_ENABLE (1UL << 3) +#define CONTROL_PADCONF_MUXMODE_MASK (0x7) + +#define CONTROL_PADCONF_SATE_MASK ( CONTROL_PADCONF_WAKEUP_EVENT \ + | CONTROL_PADCONF_WAKEUP_ENABLE \ + | CONTROL_PADCONF_OFF_PULL_UP \ + | CONTROL_PADCONF_OFF_PULL_ENABLE \ + | CONTROL_PADCONF_OFF_OUT_HIGH \ + | CONTROL_PADCONF_OFF_OUT_ENABLE \ + | CONTROL_PADCONF_OFF_ENABLE \ + | CONTROL_PADCONF_INPUT_ENABLE \ + | CONTROL_PADCONF_PULL_UP \ + | CONTROL_PADCONF_PULL_ENABLE ) + +/* Active pin states */ +#define PADCONF_PIN_OUTPUT 0 +#define PADCONF_PIN_INPUT CONTROL_PADCONF_INPUT_ENABLE +#define PADCONF_PIN_INPUT_PULLUP ( CONTROL_PADCONF_INPUT_ENABLE \ + | CONTROL_PADCONF_PULL_ENABLE \ + | CONTROL_PADCONF_PULL_UP) +#define PADCONF_PIN_INPUT_PULLDOWN ( CONTROL_PADCONF_INPUT_ENABLE \ + | CONTROL_PADCONF_PULL_ENABLE ) + +/* Off mode states */ +#define PADCONF_PIN_OFF_NONE 0 +#define PADCONF_PIN_OFF_OUTPUT_HIGH ( CONTROL_PADCONF_OFF_ENABLE \ + | CONTROL_PADCONF_OFF_OUT_ENABLE \ + | CONTROL_PADCONF_OFF_OUT_HIGH) +#define PADCONF_PIN_OFF_OUTPUT_LOW ( CONTROL_PADCONF_OFF_ENABLE \ + | CONTROL_PADCONF_OFF_OUT_ENABLE) +#define PADCONF_PIN_OFF_INPUT_PULLUP ( CONTROL_PADCONF_OFF_ENABLE \ + | CONTROL_PADCONF_OFF_PULL_ENABLE \ + | CONTROL_PADCONF_OFF_PULL_UP) +#define PADCONF_PIN_OFF_INPUT_PULLDOWN ( CONTROL_PADCONF_OFF_ENABLE \ + | CONTROL_PADCONF_OFF_PULL_ENABLE) +#define PADCONF_PIN_OFF_WAKEUPENABLE CONTROL_PADCONF_WAKEUP_ENABLE + +struct omap_scm_padconf { + uint16_t reg_off; + uint16_t gpio_pin; + uint16_t gpio_mode; + const char *ballname; + const char *muxmodes[8]; +}; + +int omap_scm_padconf_set(device_t dev, const char *padname, + const char *muxmode, unsigned int state); +int omap_scm_padconf_get(device_t dev, const char *padname, + const char **muxmode, unsigned int *state); +int omap_scm_padconf_set_gpiomode(device_t dev, uint32_t gpio, + unsigned int state); +int omap_scm_padconf_get_gpiomode(device_t dev, uint32_t gpio, + unsigned int *state); +int omap_scm_padconf_init_from_hints(device_t dev); + +#endif /* _OMAP_SCM_H_ */ Index: projects/armv6/sys/arm/omap/omap_space_asm.S =================================================================== --- projects/armv6/sys/arm/omap/omap_space_asm.S (nonexistent) +++ projects/armv6/sys/arm/omap/omap_space_asm.S (revision 230362) @@ -0,0 +1,183 @@ +/* $NetBSD: bus_space_asm_generic.S,v 1.3 2003/03/27 19:46:14 mycroft Exp $ */ + +/*- + * Copyright (c) 1997 Causality Limited. + * Copyright (c) 1997 Mark Brinicombe. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Mark Brinicombe + * for the NetBSD Project. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include +#include +__FBSDID("$FreeBSD$"); + +/* + * Generic bus_space functions. + */ + +/* + * read single + */ + +ENTRY(generic_armv7_bs_r_2) + ldrh r0, [r1, r2] + RET + +/* + * write single + */ + +ENTRY(generic_armv7_bs_w_2) + strh r3, [r1, r2] + RET + +/* + * read multiple + */ + +ENTRY(generic_armv7_bs_rm_2) + add r0, r1, r2 + mov r1, r3 + ldr r2, [sp, #0] + teq r2, #0 + RETeq + +1: ldrh r3, [r0] + strh r3, [r1], #2 + subs r2, r2, #1 + bne 1b + + RET + +/* + * write multiple + */ + +ENTRY(generic_armv7_bs_wm_2) + add r0, r1, r2 + mov r1, r3 + ldr r2, [sp, #0] + teq r2, #0 + RETeq + +1: ldrh r3, [r1], #2 + strh r3, [r0] + subs r2, r2, #1 + bne 1b + + RET + +/* + * read region + */ + +ENTRY(generic_armv7_bs_rr_2) + add r0, r1, r2 + mov r1, r3 + ldr r2, [sp, #0] + teq r2, #0 + RETeq + +1: ldrh r3, [r0], #2 + strh r3, [r1], #2 + subs r2, r2, #1 + bne 1b + + RET + +/* + * write region. + */ + +ENTRY(generic_armv7_bs_wr_2) + add r0, r1, r2 + mov r1, r3 + ldr r2, [sp, #0] + teq r2, #0 + RETeq + +1: ldrh r3, [r1], #2 + strh r3, [r0], #2 + subs r2, r2, #1 + bne 1b + + RET + +/* + * set region + */ + +ENTRY(generic_armv7_bs_sr_2) + add r0, r1, r2 + mov r1, r3 + ldr r2, [sp, #0] + teq r2, #0 + RETeq + +1: strh r1, [r0], #2 + subs r2, r2, #1 + bne 1b + + RET + +/* + * copy region + */ + +ENTRY(generic_armv7_bs_c_2) + add r0, r1, r2 + ldr r2, [sp, #0] + add r1, r2, r3 + ldr r2, [sp, #4] + teq r2, #0 + RETeq + + cmp r0, r1 + blt 2f + +1: ldrh r3, [r0], #2 + strh r3, [r1], #2 + subs r2, r2, #1 + bne 1b + + RET + +2: add r0, r0, r2, lsl #1 + add r1, r1, r2, lsl #1 + sub r0, r0, #2 + sub r1, r1, #2 + +3: ldrh r3, [r0], #-2 + strh r3, [r1], #-2 + subs r2, r2, #1 + bne 3b + + RET Index: projects/armv6/sys/arm/omap/omapvar.h =================================================================== --- projects/armv6/sys/arm/omap/omapvar.h (nonexistent) +++ projects/armv6/sys/arm/omap/omapvar.h (revision 230362) @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2010 + * Ben Gray . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Ben Gray. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _OMAPVAR_H_ +#define _OMAPVAR_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + + +/* + * Random collection of functions and definitions ... needs cleanup + * + * + * + */ + + +extern struct bus_space omap_bs_tag; + +unsigned int +omap_sdram_size(void); + +void +omap_mask_all_intr(void); + +void +omap_post_filter_intr(void *arg); + +int +omap_setup_intr(device_t dev, device_t child, + struct resource *res, int flags, driver_filter_t *filt, + driver_intr_t *intr, void *arg, void **cookiep); + +int +omap_teardown_intr(device_t dev, device_t child, struct resource *res, + void *cookie); + + + +/** + * OMAP Device IDs + * + * These values are typically read out of the ID_CODE register, located at + * physical address 0x4A00 2204 on most OMAP devices + */ +#define OMAP_CPUID_OMAP3530 0x0C00 +#define OMAP_CPUID_OMAP3525 0x4C00 +#define OMAP_CPUID_OMAP3515 0x1C00 +#define OMAP_CPUID_OMAP3503 0x5C00 + +#define OMAP_CPUID_OMAP4430_ES1_2 0xB852 +#define OMAP_CPUID_OMAP4430 0xB95C + + + + +/** + * struct omap_softc + * + * + * + */ +extern uint32_t omap3_chip_id; + +static inline int +omap_cpu_is(uint32_t cpu) +{ + return ((omap3_chip_id & 0xffff) == cpu); +} + + +/** + * struct omap_softc + * + * + * + */ +struct omap_softc { + device_t sc_dev; + bus_space_tag_t sc_iotag; + bus_space_handle_t sc_ioh; + + struct rman sc_irq_rman; + struct rman sc_mem_rman; + bus_dma_tag_t sc_dmat; +}; + + +struct omap_mem_range { + bus_addr_t base; + bus_size_t size; +}; + +/** + * struct omap_cpu_dev + * + * Structure used to define all the SoC devices, it allows for two memory + * address ranges and 4 IRQ's per device. + * + */ +struct omap_cpu_dev { + const char *name; + int unit; + + struct omap_mem_range mem[16]; + int irqs[16]; +}; + + + +struct omap_ivar { + struct resource_list resources; +}; + + + + + +#endif /* _OMAP3VAR_H_ */ Index: projects/armv6/sys/arm/omap/std.omap =================================================================== --- projects/armv6/sys/arm/omap/std.omap (nonexistent) +++ projects/armv6/sys/arm/omap/std.omap (revision 230362) @@ -0,0 +1,6 @@ +# $FreeBSD$ + +# This should be armv7-a but current gcc doesn't support it +# makeoptions CONF_CFLAGS=-march=armv6 + +cpu CPU_CORTEXA Index: projects/armv6/sys/conf/options.arm =================================================================== --- projects/armv6/sys/conf/options.arm (revision 230361) +++ projects/armv6/sys/conf/options.arm (revision 230362) @@ -1,50 +1,52 @@ #$FreeBSD$ ARM9_CACHE_WRITE_THROUGH opt_global.h ARM_CACHE_LOCK_ENABLE opt_global.h ARMFPE opt_global.h ARM_KERN_DIRECTMAP opt_vm.h ARM_L2_PIPT opt_global.h ARM_USE_SMALL_ALLOC opt_global.h AT91C_MASTER_CLOCK opt_global.h AT91C_MAIN_CLOCK opt_at91.h COUNTS_PER_SEC opt_timer.h CPU_ARM9 opt_global.h CPU_ARM9E opt_global.h CPU_ARM11 opt_global.h CPU_CORTEXA opt_global.h CPU_FA526 opt_global.h CPU_FA626TE opt_global.h CPU_MV_PJ4B opt_global.h CPU_SA1100 opt_global.h CPU_SA1110 opt_global.h CPU_XSCALE_80219 opt_global.h CPU_XSCALE_80321 opt_global.h CPU_XSCALE_81342 opt_global.h CPU_XSCALE_IXP425 opt_global.h CPU_XSCALE_IXP435 opt_global.h CPU_XSCALE_PXA2X0 opt_global.h FLASHADDR opt_global.h IXP4XX_FLASH_SIZE opt_global.h KERNPHYSADDR opt_global.h KERNVIRTADDR opt_global.h LOADERRAMADDR opt_global.h PHYSADDR opt_global.h SKYEYE_WORKAROUNDS opt_global.h SOC_MV_ARMADAXP opt_global.h SOC_MV_DISCOVERY opt_global.h SOC_MV_DOVE opt_global.h SOC_MV_FREY opt_global.h SOC_MV_KIRKWOOD opt_global.h SOC_MV_LOKIPLUS opt_global.h SOC_MV_ORION opt_global.h +SOC_OMAP3 opt_global.h +SOC_OMAP4 opt_global.h STARTUP_PAGETABLE_ADDR opt_global.h XSCALE_CACHE_READ_WRITE_ALLOCATE opt_global.h XSACLE_DISABLE_CCNT opt_timer.h VERBOSE_INIT_ARM opt_global.h VM_MAXUSER_ADDRESS opt_global.h AT91_ATE_USE_RMII opt_at91.h AT91_BWCT opt_at91.h AT91_TSC opt_at91.h AT91_KWIKBYTE opt_at91.h AT91_MCI_HAS_4WIRE opt_at91.h AT91_MCI_SLOT_B opt_at91.h