Index: stable/7/sys/cddl/contrib/opensolaris =================================================================== --- stable/7/sys/cddl/contrib/opensolaris (revision 225594) +++ stable/7/sys/cddl/contrib/opensolaris (revision 225595) Property changes on: stable/7/sys/cddl/contrib/opensolaris ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/cddl/contrib/opensolaris:r225440 Index: stable/7/sys/contrib/dev/acpica =================================================================== --- stable/7/sys/contrib/dev/acpica (revision 225594) +++ stable/7/sys/contrib/dev/acpica (revision 225595) Property changes on: stable/7/sys/contrib/dev/acpica ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/contrib/dev/acpica:r225440 Index: stable/7/sys/contrib/pf =================================================================== --- stable/7/sys/contrib/pf (revision 225594) +++ stable/7/sys/contrib/pf (revision 225595) Property changes on: stable/7/sys/contrib/pf ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/contrib/pf:r225440 Index: stable/7/sys/dev/vge/if_vge.c =================================================================== --- stable/7/sys/dev/vge/if_vge.c (revision 225594) +++ stable/7/sys/dev/vge/if_vge.c (revision 225595) @@ -1,2898 +1,2902 @@ /*- * Copyright (c) 2004 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. * * Written by Bill Paul * Senior Networking Software Engineer * Wind River Systems */ /* * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that * combines a tri-speed ethernet MAC and PHY, with the following * features: * * o Jumbo frame support up to 16K * o Transmit and receive flow control * o IPv4 checksum offload * o VLAN tag insertion and stripping * o TCP large send * o 64-bit multicast hash table filter * o 64 entry CAM filter * o 16K RX FIFO and 48K TX FIFO memory * o Interrupt moderation * * The VT6122 supports up to four transmit DMA queues. The descriptors * in the transmit ring can address up to 7 data fragments; frames which * span more than 7 data buffers must be coalesced, but in general the * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments * long. The receive descriptors address only a single buffer. * * There are two peculiar design issues with the VT6122. One is that * receive data buffers must be aligned on a 32-bit boundary. This is * not a problem where the VT6122 is used as a LOM device in x86-based * systems, but on architectures that generate unaligned access traps, we * have to do some copying. * * The other issue has to do with the way 64-bit addresses are handled. * The DMA descriptors only allow you to specify 48 bits of addressing * information. The remaining 16 bits are specified using one of the * I/O registers. If you only have a 32-bit system, then this isn't * an issue, but if you have a 64-bit system and more than 4GB of * memory, you must have to make sure your network data buffers reside * in the same 48-bit 'segment.' * * Special thanks to Ryan Fu at VIA Networking for providing documentation * and sample NICs for testing. */ #ifdef HAVE_KERNEL_OPTION_HEADERS #include "opt_device_polling.h" #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include MODULE_DEPEND(vge, pci, 1, 1, 1); MODULE_DEPEND(vge, ether, 1, 1, 1); MODULE_DEPEND(vge, miibus, 1, 1, 1); /* "device miibus" required. See GENERIC if you get errors here. */ #include "miibus_if.h" #include #include #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) /* Tunables */ static int msi_disable = 0; TUNABLE_INT("hw.vge.msi_disable", &msi_disable); /* * The SQE error counter of MIB seems to report bogus value. * Vendor's workaround does not seem to work on PCIe based * controllers. Disable it until we find better workaround. */ #undef VGE_ENABLE_SQEERR /* * Various supported device vendors/types and their names. */ static struct vge_type vge_devs[] = { { VIA_VENDORID, VIA_DEVICEID_61XX, "VIA Networking Velocity Gigabit Ethernet" }, { 0, 0, NULL } }; static int vge_attach(device_t); static int vge_detach(device_t); static int vge_probe(device_t); static int vge_resume(device_t); static int vge_shutdown(device_t); static int vge_suspend(device_t); static void vge_cam_clear(struct vge_softc *); static int vge_cam_set(struct vge_softc *, uint8_t *); static void vge_clrwol(struct vge_softc *); static void vge_discard_rxbuf(struct vge_softc *, int); static int vge_dma_alloc(struct vge_softc *); static void vge_dma_free(struct vge_softc *); static void vge_dmamap_cb(void *, bus_dma_segment_t *, int, int); #ifdef VGE_EEPROM static void vge_eeprom_getword(struct vge_softc *, int, uint16_t *); #endif static int vge_encap(struct vge_softc *, struct mbuf **); #ifndef __NO_STRICT_ALIGNMENT static __inline void vge_fixup_rx(struct mbuf *); #endif static void vge_freebufs(struct vge_softc *); static void vge_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int vge_ifmedia_upd(struct ifnet *); static void vge_init(void *); static void vge_init_locked(struct vge_softc *); static void vge_intr(void *); static void vge_intr_holdoff(struct vge_softc *); static int vge_ioctl(struct ifnet *, u_long, caddr_t); static void vge_link_statchg(void *); static int vge_miibus_readreg(device_t, int, int); static void vge_miibus_statchg(device_t); static int vge_miibus_writereg(device_t, int, int, int); static void vge_miipoll_start(struct vge_softc *); static void vge_miipoll_stop(struct vge_softc *); static int vge_newbuf(struct vge_softc *, int); static void vge_read_eeprom(struct vge_softc *, caddr_t, int, int, int); static void vge_reset(struct vge_softc *); static int vge_rx_list_init(struct vge_softc *); static int vge_rxeof(struct vge_softc *, int); static void vge_rxfilter(struct vge_softc *); static void vge_setvlan(struct vge_softc *); static void vge_setwol(struct vge_softc *); static void vge_start(struct ifnet *); static void vge_start_locked(struct ifnet *); static void vge_stats_clear(struct vge_softc *); static void vge_stats_update(struct vge_softc *); static void vge_stop(struct vge_softc *); static void vge_sysctl_node(struct vge_softc *); static int vge_tx_list_init(struct vge_softc *); static void vge_txeof(struct vge_softc *); static void vge_watchdog(void *); static device_method_t vge_methods[] = { /* Device interface */ DEVMETHOD(device_probe, vge_probe), DEVMETHOD(device_attach, vge_attach), DEVMETHOD(device_detach, vge_detach), DEVMETHOD(device_suspend, vge_suspend), DEVMETHOD(device_resume, vge_resume), DEVMETHOD(device_shutdown, vge_shutdown), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* MII interface */ DEVMETHOD(miibus_readreg, vge_miibus_readreg), DEVMETHOD(miibus_writereg, vge_miibus_writereg), DEVMETHOD(miibus_statchg, vge_miibus_statchg), { 0, 0 } }; static driver_t vge_driver = { "vge", vge_methods, sizeof(struct vge_softc) }; static devclass_t vge_devclass; DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); #ifdef VGE_EEPROM /* * Read a word of data stored in the EEPROM at address 'addr.' */ static void vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) { int i; uint16_t word = 0; /* * Enter EEPROM embedded programming mode. In order to * access the EEPROM at all, we first have to set the * EELOAD bit in the CHIPCFG2 register. */ CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); /* Select the address of the word we want to read */ CSR_WRITE_1(sc, VGE_EEADDR, addr); /* Issue read command */ CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); /* Wait for the done bit to be set. */ for (i = 0; i < VGE_TIMEOUT; i++) { if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "EEPROM read timed out\n"); *dest = 0; return; } /* Read the result */ word = CSR_READ_2(sc, VGE_EERDDAT); /* Turn off EEPROM access mode. */ CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); *dest = word; } #endif /* * Read a sequence of words from the EEPROM. */ static void vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) { int i; #ifdef VGE_EEPROM uint16_t word = 0, *ptr; for (i = 0; i < cnt; i++) { vge_eeprom_getword(sc, off + i, &word); ptr = (uint16_t *)(dest + (i * 2)); if (swap) *ptr = ntohs(word); else *ptr = word; } #else for (i = 0; i < ETHER_ADDR_LEN; i++) dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); #endif } static void vge_miipoll_stop(struct vge_softc *sc) { int i; CSR_WRITE_1(sc, VGE_MIICMD, 0); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); } static void vge_miipoll_start(struct vge_softc *sc) { int i; /* First, make sure we're idle. */ CSR_WRITE_1(sc, VGE_MIICMD, 0); CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); return; } /* Now enable auto poll mode. */ CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); /* And make sure it started. */ for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "failed to start MII autopoll\n"); } static int vge_miibus_readreg(device_t dev, int phy, int reg) { struct vge_softc *sc; int i; uint16_t rval = 0; sc = device_get_softc(dev); vge_miipoll_stop(sc); /* Specify the register we want to read. */ CSR_WRITE_1(sc, VGE_MIIADDR, reg); /* Issue read command. */ CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); /* Wait for the read command bit to self-clear. */ for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) break; } if (i == VGE_TIMEOUT) device_printf(sc->vge_dev, "MII read timed out\n"); else rval = CSR_READ_2(sc, VGE_MIIDATA); vge_miipoll_start(sc); return (rval); } static int vge_miibus_writereg(device_t dev, int phy, int reg, int data) { struct vge_softc *sc; int i, rval = 0; sc = device_get_softc(dev); vge_miipoll_stop(sc); /* Specify the register we want to write. */ CSR_WRITE_1(sc, VGE_MIIADDR, reg); /* Specify the data we want to write. */ CSR_WRITE_2(sc, VGE_MIIDATA, data); /* Issue write command. */ CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); /* Wait for the write command bit to self-clear. */ for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "MII write timed out\n"); rval = EIO; } vge_miipoll_start(sc); return (rval); } static void vge_cam_clear(struct vge_softc *sc) { int i; /* * Turn off all the mask bits. This tells the chip * that none of the entries in the CAM filter are valid. * desired entries will be enabled as we fill the filter in. */ CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); for (i = 0; i < 8; i++) CSR_WRITE_1(sc, VGE_CAM0 + i, 0); /* Clear the VLAN filter too. */ CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); for (i = 0; i < 8; i++) CSR_WRITE_1(sc, VGE_CAM0 + i, 0); CSR_WRITE_1(sc, VGE_CAMADDR, 0); CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); sc->vge_camidx = 0; } static int vge_cam_set(struct vge_softc *sc, uint8_t *addr) { int i, error = 0; if (sc->vge_camidx == VGE_CAM_MAXADDRS) return (ENOSPC); /* Select the CAM data page. */ CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); /* Set the filter entry we want to update and enable writing. */ CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); /* Write the address to the CAM registers */ for (i = 0; i < ETHER_ADDR_LEN; i++) CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); /* Issue a write command. */ CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); /* Wake for it to clear. */ for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(1); if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "setting CAM filter failed\n"); error = EIO; goto fail; } /* Select the CAM mask page. */ CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); /* Set the mask bit that enables this filter. */ CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 1<<(sc->vge_camidx & 7)); sc->vge_camidx++; fail: /* Turn off access to CAM. */ CSR_WRITE_1(sc, VGE_CAMADDR, 0); CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); return (error); } static void vge_setvlan(struct vge_softc *sc) { struct ifnet *ifp; uint8_t cfg; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; cfg = CSR_READ_1(sc, VGE_RXCFG); if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) cfg |= VGE_VTAG_OPT2; else cfg &= ~VGE_VTAG_OPT2; CSR_WRITE_1(sc, VGE_RXCFG, cfg); } /* * Program the multicast filter. We use the 64-entry CAM filter * for perfect filtering. If there's more than 64 multicast addresses, * we use the hash filter instead. */ static void vge_rxfilter(struct vge_softc *sc) { struct ifnet *ifp; struct ifmultiaddr *ifma; uint32_t h, hashes[2]; uint8_t rxcfg; int error = 0; VGE_LOCK_ASSERT(sc); /* First, zot all the multicast entries. */ hashes[0] = 0; hashes[1] = 0; rxcfg = CSR_READ_1(sc, VGE_RXCTL); rxcfg &= ~(VGE_RXCTL_RX_MCAST | VGE_RXCTL_RX_BCAST | VGE_RXCTL_RX_PROMISC); /* * Always allow VLAN oversized frames and frames for * this host. */ rxcfg |= VGE_RXCTL_RX_GIANT | VGE_RXCTL_RX_UCAST; ifp = sc->vge_ifp; if ((ifp->if_flags & IFF_BROADCAST) != 0) rxcfg |= VGE_RXCTL_RX_BCAST; if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { if ((ifp->if_flags & IFF_PROMISC) != 0) rxcfg |= VGE_RXCTL_RX_PROMISC; if ((ifp->if_flags & IFF_ALLMULTI) != 0) { hashes[0] = 0xFFFFFFFF; hashes[1] = 0xFFFFFFFF; } goto done; } vge_cam_clear(sc); /* Now program new ones */ IF_ADDR_LOCK(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; error = vge_cam_set(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); if (error) break; } /* If there were too many addresses, use the hash filter. */ if (error) { vge_cam_clear(sc); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; if (h < 32) hashes[0] |= (1 << h); else hashes[1] |= (1 << (h - 32)); } } IF_ADDR_UNLOCK(ifp); done: if (hashes[0] != 0 || hashes[1] != 0) rxcfg |= VGE_RXCTL_RX_MCAST; CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); CSR_WRITE_1(sc, VGE_RXCTL, rxcfg); } static void vge_reset(struct vge_softc *sc) { int i; CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(5); if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) break; } if (i == VGE_TIMEOUT) { device_printf(sc->vge_dev, "soft reset timed out\n"); CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); DELAY(2000); } DELAY(5000); } /* * Probe for a VIA gigabit chip. Check the PCI vendor and device * IDs against our list and return a device name if we find a match. */ static int vge_probe(device_t dev) { struct vge_type *t; struct vge_softc *sc; t = vge_devs; sc = device_get_softc(dev); while (t->vge_name != NULL) { if ((pci_get_vendor(dev) == t->vge_vid) && (pci_get_device(dev) == t->vge_did)) { device_set_desc(dev, t->vge_name); return (BUS_PROBE_DEFAULT); } t++; } return (ENXIO); } /* * Map a single buffer address. */ struct vge_dmamap_arg { bus_addr_t vge_busaddr; }; static void vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { struct vge_dmamap_arg *ctx; if (error != 0) return; KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); ctx = (struct vge_dmamap_arg *)arg; ctx->vge_busaddr = segs[0].ds_addr; } static int vge_dma_alloc(struct vge_softc *sc) { struct vge_dmamap_arg ctx; struct vge_txdesc *txd; struct vge_rxdesc *rxd; bus_addr_t lowaddr, tx_ring_end, rx_ring_end; int error, i; /* * It seems old PCI controllers do not support DAC. DAC * configuration can be enabled by accessing VGE_CHIPCFG3 * register but honor EEPROM configuration instead of * blindly overriding DAC configuration. PCIe based * controllers are supposed to support 64bit DMA so enable * 64bit DMA on these controllers. */ if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) lowaddr = BUS_SPACE_MAXADDR; else lowaddr = BUS_SPACE_MAXADDR_32BIT; again: /* Create parent ring tag. */ error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 1, 0, /* algnmnt, boundary */ lowaddr, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_ring_tag); if (error != 0) { device_printf(sc->vge_dev, "could not create parent DMA tag.\n"); goto fail; } /* Create tag for Tx ring. */ error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ VGE_TX_LIST_SZ, /* maxsize */ 1, /* nsegments */ VGE_TX_LIST_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_tx_ring_tag); if (error != 0) { device_printf(sc->vge_dev, "could not allocate Tx ring DMA tag.\n"); goto fail; } /* Create tag for Rx ring. */ error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ VGE_RX_LIST_SZ, /* maxsize */ 1, /* nsegments */ VGE_RX_LIST_SZ, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_rx_ring_tag); if (error != 0) { device_printf(sc->vge_dev, "could not allocate Rx ring DMA tag.\n"); goto fail; } /* Allocate DMA'able memory and load the DMA map for Tx ring. */ error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, (void **)&sc->vge_rdata.vge_tx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->vge_cdata.vge_tx_ring_map); if (error != 0) { device_printf(sc->vge_dev, "could not allocate DMA'able memory for Tx ring.\n"); goto fail; } ctx.vge_busaddr = 0; error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); if (error != 0 || ctx.vge_busaddr == 0) { device_printf(sc->vge_dev, "could not load DMA'able memory for Tx ring.\n"); goto fail; } sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; /* Allocate DMA'able memory and load the DMA map for Rx ring. */ error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, (void **)&sc->vge_rdata.vge_rx_ring, BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->vge_cdata.vge_rx_ring_map); if (error != 0) { device_printf(sc->vge_dev, "could not allocate DMA'able memory for Rx ring.\n"); goto fail; } ctx.vge_busaddr = 0; error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); if (error != 0 || ctx.vge_busaddr == 0) { device_printf(sc->vge_dev, "could not load DMA'able memory for Rx ring.\n"); goto fail; } sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; /* Tx/Rx descriptor queue should reside within 4GB boundary. */ tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; if ((VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || (VGE_ADDR_HI(rx_ring_end) != VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { device_printf(sc->vge_dev, "4GB boundary crossed, " "switching to 32bit DMA address mode.\n"); vge_dma_free(sc); /* Limit DMA address space to 32bit and try again. */ lowaddr = BUS_SPACE_MAXADDR_32BIT; goto again; } if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) lowaddr = VGE_BUF_DMA_MAXADDR; else lowaddr = BUS_SPACE_MAXADDR_32BIT; /* Create parent buffer tag. */ error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 1, 0, /* algnmnt, boundary */ lowaddr, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_buffer_tag); if (error != 0) { device_printf(sc->vge_dev, "could not create parent buffer DMA tag.\n"); goto fail; } /* Create tag for Tx buffers. */ error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 1, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ VGE_MAXTXSEGS, /* nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_tx_tag); if (error != 0) { device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); goto fail; } /* Create tag for Rx buffers. */ error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, /* maxsize */ 1, /* nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->vge_cdata.vge_rx_tag); if (error != 0) { device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); goto fail; } /* Create DMA maps for Tx buffers. */ for (i = 0; i < VGE_TX_DESC_CNT; i++) { txd = &sc->vge_cdata.vge_txdesc[i]; txd->tx_m = NULL; txd->tx_dmamap = NULL; error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, &txd->tx_dmamap); if (error != 0) { device_printf(sc->vge_dev, "could not create Tx dmamap.\n"); goto fail; } } /* Create DMA maps for Rx buffers. */ if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, &sc->vge_cdata.vge_rx_sparemap)) != 0) { device_printf(sc->vge_dev, "could not create spare Rx dmamap.\n"); goto fail; } for (i = 0; i < VGE_RX_DESC_CNT; i++) { rxd = &sc->vge_cdata.vge_rxdesc[i]; rxd->rx_m = NULL; rxd->rx_dmamap = NULL; error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, &rxd->rx_dmamap); if (error != 0) { device_printf(sc->vge_dev, "could not create Rx dmamap.\n"); goto fail; } } fail: return (error); } static void vge_dma_free(struct vge_softc *sc) { struct vge_txdesc *txd; struct vge_rxdesc *rxd; int i; /* Tx ring. */ if (sc->vge_cdata.vge_tx_ring_tag != NULL) { if (sc->vge_cdata.vge_tx_ring_map) bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map); if (sc->vge_cdata.vge_tx_ring_map && sc->vge_rdata.vge_tx_ring) bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, sc->vge_rdata.vge_tx_ring, sc->vge_cdata.vge_tx_ring_map); sc->vge_rdata.vge_tx_ring = NULL; sc->vge_cdata.vge_tx_ring_map = NULL; bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); sc->vge_cdata.vge_tx_ring_tag = NULL; } /* Rx ring. */ if (sc->vge_cdata.vge_rx_ring_tag != NULL) { if (sc->vge_cdata.vge_rx_ring_map) bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map); if (sc->vge_cdata.vge_rx_ring_map && sc->vge_rdata.vge_rx_ring) bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, sc->vge_rdata.vge_rx_ring, sc->vge_cdata.vge_rx_ring_map); sc->vge_rdata.vge_rx_ring = NULL; sc->vge_cdata.vge_rx_ring_map = NULL; bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); sc->vge_cdata.vge_rx_ring_tag = NULL; } /* Tx buffers. */ if (sc->vge_cdata.vge_tx_tag != NULL) { for (i = 0; i < VGE_TX_DESC_CNT; i++) { txd = &sc->vge_cdata.vge_txdesc[i]; if (txd->tx_dmamap != NULL) { bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); txd->tx_dmamap = NULL; } } bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); sc->vge_cdata.vge_tx_tag = NULL; } /* Rx buffers. */ if (sc->vge_cdata.vge_rx_tag != NULL) { for (i = 0; i < VGE_RX_DESC_CNT; i++) { rxd = &sc->vge_cdata.vge_rxdesc[i]; if (rxd->rx_dmamap != NULL) { bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); rxd->rx_dmamap = NULL; } } if (sc->vge_cdata.vge_rx_sparemap != NULL) { bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, sc->vge_cdata.vge_rx_sparemap); sc->vge_cdata.vge_rx_sparemap = NULL; } bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); sc->vge_cdata.vge_rx_tag = NULL; } if (sc->vge_cdata.vge_buffer_tag != NULL) { bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); sc->vge_cdata.vge_buffer_tag = NULL; } if (sc->vge_cdata.vge_ring_tag != NULL) { bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); sc->vge_cdata.vge_ring_tag = NULL; } } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int vge_attach(device_t dev) { u_char eaddr[ETHER_ADDR_LEN]; struct vge_softc *sc; struct ifnet *ifp; int error = 0, cap, i, msic, rid; sc = device_get_softc(dev); sc->vge_dev = dev; mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); /* * Map control/status registers. */ pci_enable_busmaster(dev); rid = PCIR_BAR(1); sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->vge_res == NULL) { device_printf(dev, "couldn't map ports/memory\n"); error = ENXIO; goto fail; } if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { sc->vge_flags |= VGE_FLAG_PCIE; sc->vge_expcap = cap; } else sc->vge_flags |= VGE_FLAG_JUMBO; if (pci_find_extcap(dev, PCIY_PMG, &cap) == 0) { sc->vge_flags |= VGE_FLAG_PMCAP; sc->vge_pmcap = cap; } rid = 0; msic = pci_msi_count(dev); if (msi_disable == 0 && msic > 0) { msic = 1; if (pci_alloc_msi(dev, &msic) == 0) { if (msic == 1) { sc->vge_flags |= VGE_FLAG_MSI; device_printf(dev, "Using %d MSI message\n", msic); rid = 1; } else pci_release_msi(dev); } } /* Allocate interrupt */ sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE); if (sc->vge_irq == NULL) { device_printf(dev, "couldn't map interrupt\n"); error = ENXIO; goto fail; } /* Reset the adapter. */ vge_reset(sc); /* Reload EEPROM. */ CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); for (i = 0; i < VGE_TIMEOUT; i++) { DELAY(5); if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) break; } if (i == VGE_TIMEOUT) device_printf(dev, "EEPROM reload timed out\n"); /* * Clear PACPI as EEPROM reload will set the bit. Otherwise * MAC will receive magic packet which in turn confuses * controller. */ CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); /* * Get station address from the EEPROM. */ vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); /* * Save configured PHY address. * It seems the PHY address of PCIe controllers just * reflects media jump strapping status so we assume the * internal PHY address of PCIe controller is at 1. */ if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) sc->vge_phyaddr = 1; else sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & VGE_MIICFG_PHYADDR; /* Clear WOL and take hardware from powerdown. */ vge_clrwol(sc); vge_sysctl_node(sc); error = vge_dma_alloc(sc); if (error) goto fail; ifp = sc->vge_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "can not if_alloc()\n"); error = ENOSPC; goto fail; } /* Do MII setup */ error = mii_attach(dev, &sc->vge_miibus, ifp, vge_ifmedia_upd, vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY, 0); if (error != 0) { device_printf(dev, "attaching PHYs failed\n"); goto fail; } ifp->if_softc = sc; if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = vge_ioctl; ifp->if_capabilities = IFCAP_VLAN_MTU; ifp->if_start = vge_start; ifp->if_hwassist = VGE_CSUM_FEATURES; ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTAGGING; if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) ifp->if_capabilities |= IFCAP_WOL; ifp->if_capenable = ifp->if_capabilities; #ifdef DEVICE_POLLING ifp->if_capabilities |= IFCAP_POLLING; #endif ifp->if_init = vge_init; IFQ_SET_MAXLEN(&ifp->if_snd, VGE_TX_DESC_CNT - 1); ifp->if_snd.ifq_drv_maxlen = VGE_TX_DESC_CNT - 1; IFQ_SET_READY(&ifp->if_snd); /* * Call MI attach routine. */ ether_ifattach(ifp, eaddr); /* Tell the upper layer(s) we support long frames. */ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); /* Hook interrupt last to avoid having to lock softc */ error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, NULL, vge_intr, sc, &sc->vge_intrhand); if (error) { device_printf(dev, "couldn't set up irq\n"); ether_ifdetach(ifp); goto fail; } fail: if (error) vge_detach(dev); return (error); } /* * Shutdown hardware and free up resources. This can be called any * time after the mutex has been initialized. It is called in both * the error case in attach and the normal detach case so it needs * to be careful about only freeing resources that have actually been * allocated. */ static int vge_detach(device_t dev) { struct vge_softc *sc; struct ifnet *ifp; sc = device_get_softc(dev); KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); ifp = sc->vge_ifp; #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) ether_poll_deregister(ifp); #endif /* These should only be active if attach succeeded */ if (device_is_attached(dev)) { ether_ifdetach(ifp); VGE_LOCK(sc); vge_stop(sc); VGE_UNLOCK(sc); callout_drain(&sc->vge_watchdog); } if (sc->vge_miibus) device_delete_child(dev, sc->vge_miibus); bus_generic_detach(dev); if (sc->vge_intrhand) bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); if (sc->vge_irq) bus_release_resource(dev, SYS_RES_IRQ, sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq); if (sc->vge_flags & VGE_FLAG_MSI) pci_release_msi(dev); if (sc->vge_res) bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(1), sc->vge_res); if (ifp) if_free(ifp); vge_dma_free(sc); mtx_destroy(&sc->vge_mtx); return (0); } static void vge_discard_rxbuf(struct vge_softc *sc, int prod) { struct vge_rxdesc *rxd; int i; rxd = &sc->vge_cdata.vge_rxdesc[prod]; rxd->rx_desc->vge_sts = 0; rxd->rx_desc->vge_ctl = 0; /* * Note: the manual fails to document the fact that for * proper opration, the driver needs to replentish the RX * DMA ring 4 descriptors at a time (rather than one at a * time, like most chips). We can allocate the new buffers * but we should not set the OWN bits until we're ready * to hand back 4 of them in one shot. */ if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { for (i = VGE_RXCHUNK; i > 0; i--) { rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); rxd = rxd->rxd_prev; } sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; } } static int vge_newbuf(struct vge_softc *sc, int prod) { struct vge_rxdesc *rxd; struct mbuf *m; bus_dma_segment_t segs[1]; bus_dmamap_t map; int i, nsegs; m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); /* * This is part of an evil trick to deal with strict-alignment * architectures. The VIA chip requires RX buffers to be aligned * on 32-bit boundaries, but that will hose strict-alignment * architectures. To get around this, we leave some empty space * at the start of each buffer and for non-strict-alignment hosts, * we copy the buffer back two bytes to achieve word alignment. * This is slightly more efficient than allocating a new buffer, * copying the contents, and discarding the old buffer. */ m->m_len = m->m_pkthdr.len = MCLBYTES; m_adj(m, VGE_RX_BUF_ALIGN); if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { m_freem(m); return (ENOBUFS); } KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); rxd = &sc->vge_cdata.vge_rxdesc[prod]; if (rxd->rx_m != NULL) { bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); } map = rxd->rx_dmamap; rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; sc->vge_cdata.vge_rx_sparemap = map; bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); rxd->rx_m = m; rxd->rx_desc->vge_sts = 0; rxd->rx_desc->vge_ctl = 0; rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); /* * Note: the manual fails to document the fact that for * proper operation, the driver needs to replenish the RX * DMA ring 4 descriptors at a time (rather than one at a * time, like most chips). We can allocate the new buffers * but we should not set the OWN bits until we're ready * to hand back 4 of them in one shot. */ if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { for (i = VGE_RXCHUNK; i > 0; i--) { rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); rxd = rxd->rxd_prev; } sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; } return (0); } static int vge_tx_list_init(struct vge_softc *sc) { struct vge_ring_data *rd; struct vge_txdesc *txd; int i; VGE_LOCK_ASSERT(sc); sc->vge_cdata.vge_tx_prodidx = 0; sc->vge_cdata.vge_tx_considx = 0; sc->vge_cdata.vge_tx_cnt = 0; rd = &sc->vge_rdata; bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); for (i = 0; i < VGE_TX_DESC_CNT; i++) { txd = &sc->vge_cdata.vge_txdesc[i]; txd->tx_m = NULL; txd->tx_desc = &rd->vge_tx_ring[i]; } bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); return (0); } static int vge_rx_list_init(struct vge_softc *sc) { struct vge_ring_data *rd; struct vge_rxdesc *rxd; int i; VGE_LOCK_ASSERT(sc); sc->vge_cdata.vge_rx_prodidx = 0; sc->vge_cdata.vge_head = NULL; sc->vge_cdata.vge_tail = NULL; sc->vge_cdata.vge_rx_commit = 0; rd = &sc->vge_rdata; bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); for (i = 0; i < VGE_RX_DESC_CNT; i++) { rxd = &sc->vge_cdata.vge_rxdesc[i]; rxd->rx_m = NULL; rxd->rx_desc = &rd->vge_rx_ring[i]; if (i == 0) rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; else rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; if (vge_newbuf(sc, i) != 0) return (ENOBUFS); } bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); sc->vge_cdata.vge_rx_commit = 0; return (0); } static void vge_freebufs(struct vge_softc *sc) { struct vge_txdesc *txd; struct vge_rxdesc *rxd; struct ifnet *ifp; int i; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; /* * Free RX and TX mbufs still in the queues. */ for (i = 0; i < VGE_RX_DESC_CNT; i++) { rxd = &sc->vge_cdata.vge_rxdesc[i]; if (rxd->rx_m != NULL) { bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); m_freem(rxd->rx_m); rxd->rx_m = NULL; } } for (i = 0; i < VGE_TX_DESC_CNT; i++) { txd = &sc->vge_cdata.vge_txdesc[i]; if (txd->tx_m != NULL) { bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); m_freem(txd->tx_m); txd->tx_m = NULL; ifp->if_oerrors++; } } } #ifndef __NO_STRICT_ALIGNMENT static __inline void vge_fixup_rx(struct mbuf *m) { int i; uint16_t *src, *dst; src = mtod(m, uint16_t *); dst = src - 1; for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) *dst++ = *src++; m->m_data -= ETHER_ALIGN; } #endif /* * RX handler. We support the reception of jumbo frames that have * been fragmented across multiple 2K mbuf cluster buffers. */ static int vge_rxeof(struct vge_softc *sc, int count) { struct mbuf *m; struct ifnet *ifp; int prod, prog, total_len; struct vge_rxdesc *rxd; struct vge_rx_desc *cur_rx; uint32_t rxstat, rxctl; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); prod = sc->vge_cdata.vge_rx_prodidx; for (prog = 0; count > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; VGE_RX_DESC_INC(prod)) { cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; rxstat = le32toh(cur_rx->vge_sts); if ((rxstat & VGE_RDSTS_OWN) != 0) break; count--; prog++; rxctl = le32toh(cur_rx->vge_ctl); total_len = VGE_RXBYTES(rxstat); rxd = &sc->vge_cdata.vge_rxdesc[prod]; m = rxd->rx_m; /* * If the 'start of frame' bit is set, this indicates * either the first fragment in a multi-fragment receive, * or an intermediate fragment. Either way, we want to * accumulate the buffers. */ if ((rxstat & VGE_RXPKT_SOF) != 0) { if (vge_newbuf(sc, prod) != 0) { ifp->if_iqdrops++; VGE_CHAIN_RESET(sc); vge_discard_rxbuf(sc, prod); continue; } m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; if (sc->vge_cdata.vge_head == NULL) { sc->vge_cdata.vge_head = m; sc->vge_cdata.vge_tail = m; } else { m->m_flags &= ~M_PKTHDR; sc->vge_cdata.vge_tail->m_next = m; sc->vge_cdata.vge_tail = m; } continue; } /* * Bad/error frames will have the RXOK bit cleared. * However, there's one error case we want to allow: * if a VLAN tagged frame arrives and the chip can't * match it against the CAM filter, it considers this * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. * We don't want to drop the frame though: our VLAN * filtering is done in software. * We also want to receive bad-checksummed frames and * and frames with bad-length. */ if ((rxstat & VGE_RDSTS_RXOK) == 0 && (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | VGE_RDSTS_CSUMERR)) == 0) { ifp->if_ierrors++; /* * If this is part of a multi-fragment packet, * discard all the pieces. */ VGE_CHAIN_RESET(sc); vge_discard_rxbuf(sc, prod); continue; } if (vge_newbuf(sc, prod) != 0) { ifp->if_iqdrops++; VGE_CHAIN_RESET(sc); vge_discard_rxbuf(sc, prod); continue; } /* Chain received mbufs. */ if (sc->vge_cdata.vge_head != NULL) { m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); /* * Special case: if there's 4 bytes or less * in this buffer, the mbuf can be discarded: * the last 4 bytes is the CRC, which we don't * care about anyway. */ if (m->m_len <= ETHER_CRC_LEN) { sc->vge_cdata.vge_tail->m_len -= (ETHER_CRC_LEN - m->m_len); m_freem(m); } else { m->m_len -= ETHER_CRC_LEN; m->m_flags &= ~M_PKTHDR; sc->vge_cdata.vge_tail->m_next = m; } m = sc->vge_cdata.vge_head; m->m_flags |= M_PKTHDR; m->m_pkthdr.len = total_len - ETHER_CRC_LEN; } else { m->m_flags |= M_PKTHDR; m->m_pkthdr.len = m->m_len = (total_len - ETHER_CRC_LEN); } #ifndef __NO_STRICT_ALIGNMENT vge_fixup_rx(m); #endif m->m_pkthdr.rcvif = ifp; /* Do RX checksumming if enabled */ if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && (rxctl & VGE_RDCTL_FRAG) == 0) { /* Check IP header checksum */ if ((rxctl & VGE_RDCTL_IPPKT) != 0) m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) m->m_pkthdr.csum_flags |= CSUM_IP_VALID; /* Check TCP/UDP checksum */ if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && rxctl & VGE_RDCTL_PROTOCSUMOK) { m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; m->m_pkthdr.csum_data = 0xffff; } } if ((rxstat & VGE_RDSTS_VTAG) != 0) { /* * The 32-bit rxctl register is stored in little-endian. * However, the 16-bit vlan tag is stored in big-endian, * so we have to byte swap it. */ m->m_pkthdr.ether_vtag = bswap16(rxctl & VGE_RDCTL_VLANID); m->m_flags |= M_VLANTAG; } VGE_UNLOCK(sc); (*ifp->if_input)(ifp, m); VGE_LOCK(sc); sc->vge_cdata.vge_head = NULL; sc->vge_cdata.vge_tail = NULL; } if (prog > 0) { sc->vge_cdata.vge_rx_prodidx = prod; bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, sc->vge_cdata.vge_rx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* Update residue counter. */ if (sc->vge_cdata.vge_rx_commit != 0) { CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, sc->vge_cdata.vge_rx_commit); sc->vge_cdata.vge_rx_commit = 0; } } return (prog); } static void vge_txeof(struct vge_softc *sc) { struct ifnet *ifp; struct vge_tx_desc *cur_tx; struct vge_txdesc *txd; uint32_t txstat; int cons, prod; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; if (sc->vge_cdata.vge_tx_cnt == 0) return; bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); /* * Go through our tx list and free mbufs for those * frames that have been transmitted. */ cons = sc->vge_cdata.vge_tx_considx; prod = sc->vge_cdata.vge_tx_prodidx; for (; cons != prod; VGE_TX_DESC_INC(cons)) { cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; txstat = le32toh(cur_tx->vge_sts); if ((txstat & VGE_TDSTS_OWN) != 0) break; sc->vge_cdata.vge_tx_cnt--; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; txd = &sc->vge_cdata.vge_txdesc[cons]; bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", __func__)); m_freem(txd->tx_m); txd->tx_m = NULL; txd->tx_desc->vge_frag[0].vge_addrhi = 0; } bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); sc->vge_cdata.vge_tx_considx = cons; if (sc->vge_cdata.vge_tx_cnt == 0) sc->vge_timer = 0; } static void vge_link_statchg(void *xsc) { struct vge_softc *sc; struct ifnet *ifp; struct mii_data *mii; sc = xsc; ifp = sc->vge_ifp; VGE_LOCK_ASSERT(sc); mii = device_get_softc(sc->vge_miibus); mii_pollstat(mii); if ((sc->vge_flags & VGE_FLAG_LINK) != 0) { if (!(mii->mii_media_status & IFM_ACTIVE)) { sc->vge_flags &= ~VGE_FLAG_LINK; if_link_state_change(sc->vge_ifp, LINK_STATE_DOWN); } } else { if (mii->mii_media_status & IFM_ACTIVE && IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { sc->vge_flags |= VGE_FLAG_LINK; if_link_state_change(sc->vge_ifp, LINK_STATE_UP); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) vge_start_locked(ifp); } } } #ifdef DEVICE_POLLING static void vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) { struct vge_softc *sc = ifp->if_softc; VGE_LOCK(sc); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) goto done; vge_rxeof(sc, count); vge_txeof(sc); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) vge_start_locked(ifp); if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ uint32_t status; status = CSR_READ_4(sc, VGE_ISR); if (status == 0xFFFFFFFF) goto done; if (status) CSR_WRITE_4(sc, VGE_ISR, status); /* * XXX check behaviour on receiver stalls. */ if (status & VGE_ISR_TXDMA_STALL || status & VGE_ISR_RXDMA_STALL) { ifp->if_drv_flags &= ~IFF_DRV_RUNNING; vge_init_locked(sc); } if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { vge_rxeof(sc, count); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); } } done: VGE_UNLOCK(sc); } #endif /* DEVICE_POLLING */ static void vge_intr(void *arg) { struct vge_softc *sc; struct ifnet *ifp; uint32_t status; sc = arg; VGE_LOCK(sc); ifp = sc->vge_ifp; if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0 || (ifp->if_flags & IFF_UP) == 0) { VGE_UNLOCK(sc); return; } #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) { + status = CSR_READ_4(sc, VGE_ISR); + CSR_WRITE_4(sc, VGE_ISR, status); + if (status != 0xFFFFFFFF && (status & VGE_ISR_LINKSTS) != 0) + vge_link_statchg(sc); VGE_UNLOCK(sc); return; } #endif /* Disable interrupts */ CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); status = CSR_READ_4(sc, VGE_ISR); CSR_WRITE_4(sc, VGE_ISR, status | VGE_ISR_HOLDOFF_RELOAD); /* If the card has gone away the read returns 0xffff. */ if (status == 0xFFFFFFFF || (status & VGE_INTRS) == 0) goto done; if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) vge_rxeof(sc, VGE_RX_DESC_CNT); if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { vge_rxeof(sc, VGE_RX_DESC_CNT); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); } if (status & (VGE_ISR_TXOK0|VGE_ISR_TXOK_HIPRIO)) vge_txeof(sc); if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { ifp->if_drv_flags &= ~IFF_DRV_RUNNING; vge_init_locked(sc); } if (status & VGE_ISR_LINKSTS) vge_link_statchg(sc); } done: if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { /* Re-enable interrupts */ CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) vge_start_locked(ifp); } VGE_UNLOCK(sc); } static int vge_encap(struct vge_softc *sc, struct mbuf **m_head) { struct vge_txdesc *txd; struct vge_tx_frag *frag; struct mbuf *m; bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; int error, i, nsegs, padlen; uint32_t cflags; VGE_LOCK_ASSERT(sc); M_ASSERTPKTHDR((*m_head)); /* Argh. This chip does not autopad short frames. */ if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { m = *m_head; padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; if (M_WRITABLE(m) == 0) { /* Get a writable copy. */ m = m_dup(*m_head, M_DONTWAIT); m_freem(*m_head); if (m == NULL) { *m_head = NULL; return (ENOBUFS); } *m_head = m; } if (M_TRAILINGSPACE(m) < padlen) { m = m_defrag(m, M_DONTWAIT); if (m == NULL) { m_freem(*m_head); *m_head = NULL; return (ENOBUFS); } } /* * Manually pad short frames, and zero the pad space * to avoid leaking data. */ bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); m->m_pkthdr.len += padlen; m->m_len = m->m_pkthdr.len; *m_head = m; } txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); if (error == EFBIG) { m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); if (m == NULL) { m_freem(*m_head); *m_head = NULL; return (ENOMEM); } *m_head = m; error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); if (error != 0) { m_freem(*m_head); *m_head = NULL; return (error); } } else if (error != 0) return (error); bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); m = *m_head; cflags = 0; /* Configure checksum offload. */ if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) cflags |= VGE_TDCTL_IPCSUM; if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) cflags |= VGE_TDCTL_TCPCSUM; if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) cflags |= VGE_TDCTL_UDPCSUM; /* Configure VLAN. */ if ((m->m_flags & M_VLANTAG) != 0) cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); /* * XXX * Velocity family seems to support TSO but no information * for MSS configuration is available. Also the number of * fragments supported by a descriptor is too small to hold * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build * longer chain of buffers but no additional information is * available. * * When telling the chip how many segments there are, we * must use nsegs + 1 instead of just nsegs. Darned if I * know why. This also means we can't use the last fragment * field of Tx descriptor. */ txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | VGE_TD_LS_NORM); for (i = 0; i < nsegs; i++) { frag = &txd->tx_desc->vge_frag[i]; frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | (VGE_BUFLEN(txsegs[i].ds_len) << 16)); } sc->vge_cdata.vge_tx_cnt++; VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); /* * Finally request interrupt and give the first descriptor * ownership to hardware. */ txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); txd->tx_m = m; return (0); } /* * Main transmit routine. */ static void vge_start(struct ifnet *ifp) { struct vge_softc *sc; sc = ifp->if_softc; VGE_LOCK(sc); vge_start_locked(ifp); VGE_UNLOCK(sc); } static void vge_start_locked(struct ifnet *ifp) { struct vge_softc *sc; struct vge_txdesc *txd; struct mbuf *m_head; int enq, idx; sc = ifp->if_softc; VGE_LOCK_ASSERT(sc); if ((sc->vge_flags & VGE_FLAG_LINK) == 0 || (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) return; idx = sc->vge_cdata.vge_tx_prodidx; VGE_TX_DESC_DEC(idx); for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); if (m_head == NULL) break; /* * Pack the data into the transmit ring. If we * don't have room, set the OACTIVE flag and wait * for the NIC to drain the ring. */ if (vge_encap(sc, &m_head)) { if (m_head == NULL) break; IFQ_DRV_PREPEND(&ifp->if_snd, m_head); ifp->if_drv_flags |= IFF_DRV_OACTIVE; break; } txd = &sc->vge_cdata.vge_txdesc[idx]; txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); VGE_TX_DESC_INC(idx); enq++; /* * If there's a BPF listener, bounce a copy of this frame * to him. */ ETHER_BPF_MTAP(ifp, m_head); } if (enq > 0) { bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, sc->vge_cdata.vge_tx_ring_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* Issue a transmit command. */ CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); /* * Set a timeout in case the chip goes out to lunch. */ sc->vge_timer = 5; } } static void vge_init(void *xsc) { struct vge_softc *sc = xsc; VGE_LOCK(sc); vge_init_locked(sc); VGE_UNLOCK(sc); } static void vge_init_locked(struct vge_softc *sc) { struct ifnet *ifp = sc->vge_ifp; struct mii_data *mii; int error, i; VGE_LOCK_ASSERT(sc); mii = device_get_softc(sc->vge_miibus); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) return; /* * Cancel pending I/O and free all RX/TX buffers. */ vge_stop(sc); vge_reset(sc); /* * Initialize the RX and TX descriptors and mbufs. */ error = vge_rx_list_init(sc); if (error != 0) { device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); return; } vge_tx_list_init(sc); /* Clear MAC statistics. */ vge_stats_clear(sc); /* Set our station address */ for (i = 0; i < ETHER_ADDR_LEN; i++) CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); /* * Set receive FIFO threshold. Also allow transmission and * reception of VLAN tagged frames. */ CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); /* Set DMA burst length */ CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); /* Set collision backoff algorithm */ CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); /* Disable LPSEL field in priority resolution */ CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); /* * Load the addresses of the DMA queues into the chip. * Note that we only use one transmit queue. */ CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); /* Configure interrupt moderation. */ vge_intr_holdoff(sc); /* Enable and wake up the RX descriptor queue */ CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); /* Enable the TX descriptor queue */ CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); /* Init the cam filter. */ vge_cam_clear(sc); /* Set up receiver filter. */ vge_rxfilter(sc); vge_setvlan(sc); /* Enable flow control */ CSR_WRITE_1(sc, VGE_CRS2, 0x8B); /* Enable jumbo frame reception (if desired) */ /* Start the MAC. */ CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); #ifdef DEVICE_POLLING /* - * Disable interrupts if we are polling. + * Disable interrupts except link state change if we are polling. */ if (ifp->if_capenable & IFCAP_POLLING) { - CSR_WRITE_4(sc, VGE_IMR, 0); - CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); + CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING); } else /* otherwise ... */ #endif { /* * Enable interrupts. */ CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); - CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); - CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); } + CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); + CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); sc->vge_flags &= ~VGE_FLAG_LINK; mii_mediachg(mii); ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); } /* * Set media options. */ static int vge_ifmedia_upd(struct ifnet *ifp) { struct vge_softc *sc; struct mii_data *mii; int error; sc = ifp->if_softc; VGE_LOCK(sc); mii = device_get_softc(sc->vge_miibus); error = mii_mediachg(mii); VGE_UNLOCK(sc); return (error); } /* * Report current media status. */ static void vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct vge_softc *sc; struct mii_data *mii; sc = ifp->if_softc; mii = device_get_softc(sc->vge_miibus); VGE_LOCK(sc); if ((ifp->if_flags & IFF_UP) == 0) { VGE_UNLOCK(sc); return; } mii_pollstat(mii); VGE_UNLOCK(sc); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; } static void vge_miibus_statchg(device_t dev) { struct vge_softc *sc; struct mii_data *mii; struct ifmedia_entry *ife; sc = device_get_softc(dev); mii = device_get_softc(sc->vge_miibus); ife = mii->mii_media.ifm_cur; /* * If the user manually selects a media mode, we need to turn * on the forced MAC mode bit in the DIAGCTL register. If the * user happens to choose a full duplex mode, we also need to * set the 'force full duplex' bit. This applies only to * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC * mode is disabled, and in 1000baseT mode, full duplex is * always implied, so we turn on the forced mode bit but leave * the FDX bit cleared. */ switch (IFM_SUBTYPE(ife->ifm_media)) { case IFM_AUTO: CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); break; case IFM_1000_T: CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); break; case IFM_100_TX: case IFM_10_T: CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); } else { CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); } break; default: device_printf(dev, "unknown media type: %x\n", IFM_SUBTYPE(ife->ifm_media)); break; } } static int vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { struct vge_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *) data; struct mii_data *mii; int error = 0, mask; switch (command) { case SIOCSIFMTU: VGE_LOCK(sc); if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > VGE_JUMBO_MTU) error = EINVAL; else if (ifp->if_mtu != ifr->ifr_mtu) { if (ifr->ifr_mtu > ETHERMTU && (sc->vge_flags & VGE_FLAG_JUMBO) == 0) error = EINVAL; else ifp->if_mtu = ifr->ifr_mtu; } VGE_UNLOCK(sc); break; case SIOCSIFFLAGS: VGE_LOCK(sc); if ((ifp->if_flags & IFF_UP) != 0) { if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && ((ifp->if_flags ^ sc->vge_if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) vge_rxfilter(sc); else vge_init_locked(sc); } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) vge_stop(sc); sc->vge_if_flags = ifp->if_flags; VGE_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: VGE_LOCK(sc); if (ifp->if_drv_flags & IFF_DRV_RUNNING) vge_rxfilter(sc); VGE_UNLOCK(sc); break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: mii = device_get_softc(sc->vge_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); break; case SIOCSIFCAP: mask = ifr->ifr_reqcap ^ ifp->if_capenable; #ifdef DEVICE_POLLING if (mask & IFCAP_POLLING) { if (ifr->ifr_reqcap & IFCAP_POLLING) { error = ether_poll_register(vge_poll, ifp); if (error) return (error); VGE_LOCK(sc); /* Disable interrupts */ - CSR_WRITE_4(sc, VGE_IMR, 0); - CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); + CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING); + CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); + CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); ifp->if_capenable |= IFCAP_POLLING; VGE_UNLOCK(sc); } else { error = ether_poll_deregister(ifp); /* Enable interrupts. */ VGE_LOCK(sc); CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); ifp->if_capenable &= ~IFCAP_POLLING; VGE_UNLOCK(sc); } } #endif /* DEVICE_POLLING */ VGE_LOCK(sc); if ((mask & IFCAP_TXCSUM) != 0 && (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { ifp->if_capenable ^= IFCAP_TXCSUM; if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) ifp->if_hwassist |= VGE_CSUM_FEATURES; else ifp->if_hwassist &= ~VGE_CSUM_FEATURES; } if ((mask & IFCAP_RXCSUM) != 0 && (ifp->if_capabilities & IFCAP_RXCSUM) != 0) ifp->if_capenable ^= IFCAP_RXCSUM; if ((mask & IFCAP_WOL_UCAST) != 0 && (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) ifp->if_capenable ^= IFCAP_WOL_UCAST; if ((mask & IFCAP_WOL_MCAST) != 0 && (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) ifp->if_capenable ^= IFCAP_WOL_MCAST; if ((mask & IFCAP_WOL_MAGIC) != 0 && (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) ifp->if_capenable ^= IFCAP_WOL_MAGIC; if ((mask & IFCAP_VLAN_HWCSUM) != 0 && (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; vge_setvlan(sc); } VGE_UNLOCK(sc); VLAN_CAPABILITIES(ifp); break; default: error = ether_ioctl(ifp, command, data); break; } return (error); } static void vge_watchdog(void *arg) { struct vge_softc *sc; struct ifnet *ifp; sc = arg; VGE_LOCK_ASSERT(sc); vge_stats_update(sc); callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); if (sc->vge_timer == 0 || --sc->vge_timer > 0) return; ifp = sc->vge_ifp; if_printf(ifp, "watchdog timeout\n"); ifp->if_oerrors++; vge_txeof(sc); vge_rxeof(sc, VGE_RX_DESC_CNT); ifp->if_drv_flags &= ~IFF_DRV_RUNNING; vge_init_locked(sc); } /* * Stop the adapter and free any mbufs allocated to the * RX and TX lists. */ static void vge_stop(struct vge_softc *sc) { struct ifnet *ifp; VGE_LOCK_ASSERT(sc); ifp = sc->vge_ifp; sc->vge_timer = 0; callout_stop(&sc->vge_watchdog); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); vge_stats_update(sc); VGE_CHAIN_RESET(sc); vge_txeof(sc); vge_freebufs(sc); } /* * Device suspend routine. Stop the interface and save some PCI * settings in case the BIOS doesn't restore them properly on * resume. */ static int vge_suspend(device_t dev) { struct vge_softc *sc; sc = device_get_softc(dev); VGE_LOCK(sc); vge_stop(sc); vge_setwol(sc); sc->vge_flags |= VGE_FLAG_SUSPENDED; VGE_UNLOCK(sc); return (0); } /* * Device resume routine. Restore some PCI settings in case the BIOS * doesn't, re-enable busmastering, and restart the interface if * appropriate. */ static int vge_resume(device_t dev) { struct vge_softc *sc; struct ifnet *ifp; uint16_t pmstat; sc = device_get_softc(dev); VGE_LOCK(sc); if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) { /* Disable PME and clear PME status. */ pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS, 2); if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { pmstat &= ~PCIM_PSTAT_PMEENABLE; pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS, pmstat, 2); } } vge_clrwol(sc); /* Restart MII auto-polling. */ vge_miipoll_start(sc); ifp = sc->vge_ifp; /* Reinitialize interface if necessary. */ if ((ifp->if_flags & IFF_UP) != 0) { ifp->if_drv_flags &= ~IFF_DRV_RUNNING; vge_init_locked(sc); } sc->vge_flags &= ~VGE_FLAG_SUSPENDED; VGE_UNLOCK(sc); return (0); } /* * Stop all chip I/O so that the kernel's probe routines don't * get confused by errant DMAs when rebooting. */ static int vge_shutdown(device_t dev) { return (vge_suspend(dev)); } #define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) static void vge_sysctl_node(struct vge_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid_list *child, *parent; struct sysctl_oid *tree; struct vge_hw_stats *stats; stats = &sc->vge_stats; ctx = device_get_sysctl_ctx(sc->vge_dev); child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev)); SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_holdoff", CTLFLAG_RW, &sc->vge_int_holdoff, 0, "interrupt holdoff"); SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rx_coal_pkt", CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, "rx coalescing packet"); SYSCTL_ADD_INT(ctx, child, OID_AUTO, "tx_coal_pkt", CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, "tx coalescing packet"); /* Pull in device tunables. */ sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT; resource_int_value(device_get_name(sc->vge_dev), device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff); sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT; resource_int_value(device_get_name(sc->vge_dev), device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt); sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT; resource_int_value(device_get_name(sc->vge_dev), device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt); tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, NULL, "VGE statistics"); parent = SYSCTL_CHILDREN(tree); /* Rx statistics. */ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, NULL, "RX MAC statistics"); child = SYSCTL_CHILDREN(tree); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames", &stats->rx_frames, "frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", &stats->rx_good_frames, "Good frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", &stats->rx_fifo_oflows, "FIFO overflows"); VGE_SYSCTL_STAT_ADD32(ctx, child, "runts", &stats->rx_runts, "Too short frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs", &stats->rx_runts_errs, "Too short frames with errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", &stats->rx_pkts_64, "64 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", &stats->rx_pkts_65_127, "65 to 127 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", &stats->rx_pkts_128_255, "128 to 255 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", &stats->rx_pkts_256_511, "256 to 511 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", &stats->rx_pkts_1519_max, "1519 to max frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs", &stats->rx_pkts_1519_max_errs, "1519 to max frames with error"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", &stats->rx_jumbos, "Jumbo frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", &stats->rx_crcerrs, "CRC errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", &stats->rx_pause_frames, "CRC errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", &stats->rx_alignerrs, "Alignment errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs", &stats->rx_nobufs, "Frames with no buffer event"); VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", &stats->rx_symerrs, "Frames with symbol errors"); VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", &stats->rx_lenerrs, "Frames with length mismatched"); /* Tx statistics. */ tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, NULL, "TX MAC statistics"); child = SYSCTL_CHILDREN(tree); VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", &stats->tx_good_frames, "Good frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", &stats->tx_pkts_64, "64 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", &stats->tx_pkts_65_127, "65 to 127 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", &stats->tx_pkts_128_255, "128 to 255 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", &stats->tx_pkts_256_511, "256 to 511 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", &stats->tx_jumbos, "Jumbo frames"); VGE_SYSCTL_STAT_ADD32(ctx, child, "colls", &stats->tx_colls, "Collisions"); VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", &stats->tx_latecolls, "Late collisions"); VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", &stats->tx_pause, "Pause frames"); #ifdef VGE_ENABLE_SQEERR VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs", &stats->tx_sqeerrs, "SQE errors"); #endif /* Clear MAC statistics. */ vge_stats_clear(sc); } #undef VGE_SYSCTL_STAT_ADD32 static void vge_stats_clear(struct vge_softc *sc) { int i; CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE); CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR); for (i = VGE_TIMEOUT; i > 0; i--) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0) break; } if (i == 0) device_printf(sc->vge_dev, "MIB clear timed out!\n"); CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) & ~VGE_MIBCSR_FREEZE); } static void vge_stats_update(struct vge_softc *sc) { struct vge_hw_stats *stats; struct ifnet *ifp; uint32_t mib[VGE_MIB_CNT], val; int i; VGE_LOCK_ASSERT(sc); stats = &sc->vge_stats; ifp = sc->vge_ifp; CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH); for (i = VGE_TIMEOUT; i > 0; i--) { DELAY(1); if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0) break; } if (i == 0) { device_printf(sc->vge_dev, "MIB counter dump timed out!\n"); vge_stats_clear(sc); return; } bzero(mib, sizeof(mib)); reset_idx: /* Set MIB read index to 0. */ CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI); for (i = 0; i < VGE_MIB_CNT; i++) { val = CSR_READ_4(sc, VGE_MIBDATA); if (i != VGE_MIB_DATA_IDX(val)) { /* Reading interrupted. */ goto reset_idx; } mib[i] = val & VGE_MIB_DATA_MASK; } /* Rx stats. */ stats->rx_frames += mib[VGE_MIB_RX_FRAMES]; stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES]; stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS]; stats->rx_runts += mib[VGE_MIB_RX_RUNTS]; stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS]; stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64]; stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127]; stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255]; stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511]; stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023]; stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518]; stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX]; stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS]; stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS]; stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS]; stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE]; stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS]; stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS]; stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS]; stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS]; /* Tx stats. */ stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES]; stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64]; stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127]; stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255]; stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511]; stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023]; stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518]; stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS]; stats->tx_colls += mib[VGE_MIB_TX_COLLS]; stats->tx_pause += mib[VGE_MIB_TX_PAUSE]; #ifdef VGE_ENABLE_SQEERR stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS]; #endif stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS]; /* Update counters in ifnet. */ ifp->if_opackets += mib[VGE_MIB_TX_GOOD_FRAMES]; ifp->if_collisions += mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]; ifp->if_oerrors += mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]; ifp->if_ipackets += mib[VGE_MIB_RX_GOOD_FRAMES]; ifp->if_ierrors += mib[VGE_MIB_RX_FIFO_OVERRUNS] + mib[VGE_MIB_RX_RUNTS] + mib[VGE_MIB_RX_RUNTS_ERRS] + mib[VGE_MIB_RX_CRCERRS] + mib[VGE_MIB_RX_ALIGNERRS] + mib[VGE_MIB_RX_NOBUFS] + mib[VGE_MIB_RX_SYMERRS] + mib[VGE_MIB_RX_LENERRS]; } static void vge_intr_holdoff(struct vge_softc *sc) { uint8_t intctl; VGE_LOCK_ASSERT(sc); /* * Set Tx interrupt supression threshold. * It's possible to use single-shot timer in VGE_CRS1 register * in Tx path such that driver can remove most of Tx completion * interrupts. However this requires additional access to * VGE_CRS1 register to reload the timer in addintion to * activating Tx kick command. Another downside is we don't know * what single-shot timer value should be used in advance so * reclaiming transmitted mbufs could be delayed a lot which in * turn slows down Tx operation. */ CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_TXSUPPTHR); CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt); /* Set Rx interrupt suppresion threshold. */ CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt); intctl = CSR_READ_1(sc, VGE_INTCTL1); intctl &= ~VGE_INTCTL_SC_RELOAD; intctl |= VGE_INTCTL_HC_RELOAD; if (sc->vge_tx_coal_pkt <= 0) intctl |= VGE_INTCTL_TXINTSUP_DISABLE; else intctl &= ~VGE_INTCTL_TXINTSUP_DISABLE; if (sc->vge_rx_coal_pkt <= 0) intctl |= VGE_INTCTL_RXINTSUP_DISABLE; else intctl &= ~VGE_INTCTL_RXINTSUP_DISABLE; CSR_WRITE_1(sc, VGE_INTCTL1, intctl); CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF); if (sc->vge_int_holdoff > 0) { /* Set interrupt holdoff timer. */ CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); CSR_WRITE_1(sc, VGE_INTHOLDOFF, VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff)); /* Enable holdoff timer. */ CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); } } static void vge_setlinkspeed(struct vge_softc *sc) { struct mii_data *mii; int aneg, i; VGE_LOCK_ASSERT(sc); mii = device_get_softc(sc->vge_miibus); mii_pollstat(mii); aneg = 0; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch IFM_SUBTYPE(mii->mii_media_active) { case IFM_10_T: case IFM_100_TX: return; case IFM_1000_T: aneg++; default: break; } } vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0); vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); DELAY(1000); if (aneg != 0) { /* Poll link state until vge(4) get a 10/100 link. */ for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { mii_pollstat(mii); if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: return; default: break; } } VGE_UNLOCK(sc); pause("vgelnk", hz); VGE_LOCK(sc); } if (i == MII_ANEGTICKS_GIGE) device_printf(sc->vge_dev, "establishing link failed, " "WOL may not work!"); } /* * No link, force MAC to have 100Mbps, full-duplex link. * This is the last resort and may/may not work. */ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; } static void vge_setwol(struct vge_softc *sc) { struct ifnet *ifp; uint16_t pmstat; uint8_t val; VGE_LOCK_ASSERT(sc); if ((sc->vge_flags & VGE_FLAG_PMCAP) == 0) { /* No PME capability, PHY power down. */ vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, BMCR_PDOWN); vge_miipoll_stop(sc); return; } ifp = sc->vge_ifp; /* Clear WOL on pattern match. */ CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); /* Disable WOL on magic/unicast packet. */ CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | VGE_WOLCFG_PMEOVR); if ((ifp->if_capenable & IFCAP_WOL) != 0) { vge_setlinkspeed(sc); val = 0; if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) val |= VGE_WOLCR1_UCAST; if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) val |= VGE_WOLCR1_MAGIC; CSR_WRITE_1(sc, VGE_WOLCR1S, val); val = 0; if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) val |= VGE_WOLCFG_SAM | VGE_WOLCFG_SAB; CSR_WRITE_1(sc, VGE_WOLCFGS, val | VGE_WOLCFG_PMEOVR); /* Disable MII auto-polling. */ vge_miipoll_stop(sc); } CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE | VGE_DIAGCTL_FDXFORCE); CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); /* Clear WOL status on pattern match. */ CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); val = CSR_READ_1(sc, VGE_PWRSTAT); val |= VGE_STICKHW_SWPTAG; CSR_WRITE_1(sc, VGE_PWRSTAT, val); /* Put hardware into sleep. */ val = CSR_READ_1(sc, VGE_PWRSTAT); val |= VGE_STICKHW_DS0 | VGE_STICKHW_DS1; CSR_WRITE_1(sc, VGE_PWRSTAT, val); /* Request PME if WOL is requested. */ pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS, 2); pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); if ((ifp->if_capenable & IFCAP_WOL) != 0) pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS, pmstat, 2); } static void vge_clrwol(struct vge_softc *sc) { uint8_t val; val = CSR_READ_1(sc, VGE_PWRSTAT); val &= ~VGE_STICKHW_SWPTAG; CSR_WRITE_1(sc, VGE_PWRSTAT, val); /* Disable WOL and clear power state indicator. */ val = CSR_READ_1(sc, VGE_PWRSTAT); val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1); CSR_WRITE_1(sc, VGE_PWRSTAT, val); CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); /* Clear WOL on pattern match. */ CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); /* Disable WOL on magic/unicast packet. */ CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | VGE_WOLCFG_PMEOVR); /* Clear WOL status on pattern match. */ CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); } Index: stable/7/sys/dev/vge/if_vgereg.h =================================================================== --- stable/7/sys/dev/vge/if_vgereg.h (revision 225594) +++ stable/7/sys/dev/vge/if_vgereg.h (revision 225595) @@ -1,778 +1,780 @@ /*- * Copyright (c) 2004 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* * Register definitions for the VIA VT6122 gigabit ethernet controller. * Definitions for the built-in copper PHY can be found in vgphy.h. * * The VT612x controllers have 256 bytes of register space. The * manual seems to imply that the registers should all be accessed * using 32-bit I/O cycles, but some of them are less than 32 bits * wide. Go figure. */ #ifndef _IF_VGEREG_H_ #define _IF_VGEREG_H_ #define VIA_VENDORID 0x1106 #define VIA_DEVICEID_61XX 0x3119 #define VGE_PAR0 0x00 /* physical address register */ #define VGE_PAR1 0x02 #define VGE_PAR2 0x04 #define VGE_RXCTL 0x06 /* RX control register */ #define VGE_TXCTL 0x07 /* TX control register */ #define VGE_CRS0 0x08 /* Global cmd register 0 (w to set) */ #define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */ #define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */ #define VGE_CRS3 0x0B /* Global cmd register 3 (w to set) */ #define VGE_CRC0 0x0C /* Global cmd register 0 (w to clr) */ #define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */ #define VGE_CRC2 0x0E /* Global cmd register 2 (w to clr) */ #define VGE_CRC3 0x0F /* Global cmd register 3 (w to clr) */ #define VGE_MAR0 0x10 /* Mcast hash/CAM register 0 */ #define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */ #define VGE_CAM0 0x10 #define VGE_CAM1 0x11 #define VGE_CAM2 0x12 #define VGE_CAM3 0x13 #define VGE_CAM4 0x14 #define VGE_CAM5 0x15 #define VGE_CAM6 0x16 #define VGE_CAM7 0x17 #define VGE_TXDESC_HIADDR 0x18 /* Hi part of 64bit txdesc base addr */ #define VGE_DATABUF_HIADDR 0x1D /* Hi part of 64bit data buffer addr */ #define VGE_INTCTL0 0x20 /* interrupt control register */ #define VGE_RXSUPPTHR 0x20 #define VGE_TXSUPPTHR 0x20 #define VGE_INTHOLDOFF 0x20 #define VGE_INTCTL1 0x21 /* interrupt control register */ #define VGE_TXHOSTERR 0x22 /* TX host error status */ #define VGE_RXHOSTERR 0x23 /* RX host error status */ #define VGE_ISR 0x24 /* Interrupt status register */ #define VGE_IMR 0x28 /* Interrupt mask register */ #define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */ #define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */ #define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */ #define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */ #define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */ #define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */ #define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */ #define VGE_TXQTIMER 0x3E /* TX queue timer pend register */ #define VGE_RXQTIMER 0x3F /* RX queue timer pend register */ #define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */ #define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */ #define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */ #define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */ #define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */ #define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */ #define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */ #define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */ #define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */ #define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */ #define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */ #define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */ #define VGE_FIFOTEST0 0x60 /* FIFO test register */ #define VGE_FIFOTEST1 0x64 /* FIFO test register */ #define VGE_CAMADDR 0x68 /* CAM address register */ #define VGE_CAMCTL 0x69 /* CAM control register */ #define VGE_GFTEST 0x6A #define VGE_FTSCMD 0x6B #define VGE_MIICFG 0x6C /* MII port config register */ #define VGE_MIISTS 0x6D /* MII port status register */ #define VGE_PHYSTS0 0x6E /* PHY status register */ #define VGE_PHYSTS1 0x6F /* PHY status register */ #define VGE_MIICMD 0x70 /* MII command register */ #define VGE_MIIADDR 0x71 /* MII address register */ #define VGE_MIIDATA 0x72 /* MII data register */ #define VGE_SSTIMER 0x74 /* single-shot timer */ #define VGE_PTIMER 0x76 /* periodic timer */ #define VGE_CHIPCFG0 0x78 /* chip config A */ #define VGE_CHIPCFG1 0x79 /* chip config B */ #define VGE_CHIPCFG2 0x7A /* chip config C */ #define VGE_CHIPCFG3 0x7B /* chip config D */ #define VGE_DMACFG0 0x7C /* DMA config 0 */ #define VGE_DMACFG1 0x7D /* DMA config 1 */ #define VGE_RXCFG 0x7E /* MAC RX config */ #define VGE_TXCFG 0x7F /* MAC TX config */ #define VGE_PWRMGMT 0x82 /* power management shadow register */ #define VGE_PWRSTAT 0x83 /* power state shadow register */ #define VGE_MIBCSR 0x84 /* MIB control/status register */ #define VGE_SWEEDATA 0x85 /* EEPROM software loaded data */ #define VGE_MIBDATA 0x88 /* MIB data register */ #define VGE_EEWRDAT 0x8C /* EEPROM embedded write */ #define VGE_EECSUM 0x92 /* EEPROM checksum */ #define VGE_EECSR 0x93 /* EEPROM control/status */ #define VGE_EERDDAT 0x94 /* EEPROM embedded read */ #define VGE_EEADDR 0x96 /* EEPROM address */ #define VGE_EECMD 0x97 /* EEPROM embedded command */ #define VGE_CHIPSTRAP 0x99 /* Chip jumper strapping status */ #define VGE_MEDIASTRAP 0x9B /* Media jumper strapping */ #define VGE_DIAGSTS 0x9C /* Chip diagnostic status */ #define VGE_DBGCTL 0x9E /* Chip debug control */ #define VGE_DIAGCTL 0x9F /* Chip diagnostic control */ #define VGE_WOLCR0S 0xA0 /* WOL0 event set */ #define VGE_WOLCR1S 0xA1 /* WOL1 event set */ #define VGE_PWRCFGS 0xA2 /* Power management config set */ #define VGE_WOLCFGS 0xA3 /* WOL config set */ #define VGE_WOLCR0C 0xA4 /* WOL0 event clear */ #define VGE_WOLCR1C 0xA5 /* WOL1 event clear */ #define VGE_PWRCFGC 0xA6 /* Power management config clear */ #define VGE_WOLCFGC 0xA7 /* WOL config clear */ #define VGE_WOLSR0S 0xA8 /* WOL status set */ #define VGE_WOLSR1S 0xA9 /* WOL status set */ #define VGE_WOLSR0C 0xAC /* WOL status clear */ #define VGE_WOLSR1C 0xAD /* WOL status clear */ #define VGE_WAKEPAT_CRC0 0xB0 #define VGE_WAKEPAT_CRC1 0xB2 #define VGE_WAKEPAT_CRC2 0xB4 #define VGE_WAKEPAT_CRC3 0xB6 #define VGE_WAKEPAT_CRC4 0xB8 #define VGE_WAKEPAT_CRC5 0xBA #define VGE_WAKEPAT_CRC6 0xBC #define VGE_WAKEPAT_CRC7 0xBE #define VGE_WAKEPAT_MSK0_0 0xC0 #define VGE_WAKEPAT_MSK0_1 0xC4 #define VGE_WAKEPAT_MSK0_2 0xC8 #define VGE_WAKEPAT_MSK0_3 0xCC #define VGE_WAKEPAT_MSK1_0 0xD0 #define VGE_WAKEPAT_MSK1_1 0xD4 #define VGE_WAKEPAT_MSK1_2 0xD8 #define VGE_WAKEPAT_MSK1_3 0xDC #define VGE_WAKEPAT_MSK2_0 0xE0 #define VGE_WAKEPAT_MSK2_1 0xE4 #define VGE_WAKEPAT_MSK2_2 0xE8 #define VGE_WAKEPAT_MSK2_3 0xEC #define VGE_WAKEPAT_MSK3_0 0xF0 #define VGE_WAKEPAT_MSK3_1 0xF4 #define VGE_WAKEPAT_MSK3_2 0xF8 #define VGE_WAKEPAT_MSK3_3 0xFC /* Receive control register */ #define VGE_RXCTL_RX_BADFRAMES 0x01 /* accept CRC error frames */ #define VGE_RXCTL_RX_RUNT 0x02 /* accept runts */ #define VGE_RXCTL_RX_MCAST 0x04 /* accept multicasts */ #define VGE_RXCTL_RX_BCAST 0x08 /* accept broadcasts */ #define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */ #define VGE_RXCTL_RX_GIANT 0x20 /* accept VLAN tagged frames */ #define VGE_RXCTL_RX_UCAST 0x40 /* use perfect filtering */ #define VGE_RXCTL_RX_SYMERR 0x80 /* accept symbol err packet */ /* Transmit control register */ #define VGE_TXCTL_LOOPCTL 0x03 /* loopback control */ #define VGE_TXCTL_COLLCTL 0x0C /* collision retry control */ #define VGE_TXLOOPCTL_OFF 0x00 #define VGE_TXLOOPCTL_MAC_INTERNAL 0x01 #define VGE_TXLOOPCTL_EXTERNAL 0x02 #define VGE_TXCOLLS_NORMAL 0x00 /* one set of 16 retries */ #define VGE_TXCOLLS_32 0x04 /* two sets of 16 retries */ #define VGE_TXCOLLS_48 0x08 /* three sets of 16 retries */ #define VGE_TXCOLLS_INFINITE 0x0C /* retry forever */ /* Global command register 0 */ #define VGE_CR0_START 0x01 /* start NIC */ #define VGE_CR0_STOP 0x02 /* stop NIC */ #define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */ #define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */ /* Global command register 1 */ #define VGE_CR1_NOUCAST 0x01 /* disable unicast reception */ #define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */ #define VGE_CR1_TIMER0_ENABLE 0x20 /* enable single shot timer */ #define VGE_CR1_TIMER1_ENABLE 0x40 /* enable periodic timer */ #define VGE_CR1_SOFTRESET 0x80 /* software reset */ /* Global command register 2 */ #define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */ #define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */ #define VGE_CR2_HDX_FLOWCTL_ENABLE 0x10 /* half duplex flow control */ #define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */ #define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */ #define VGE_CR2_XON_ENABLE 0x80 /* 802.3x XON/XOFF flow control */ /* Global command register 3 */ #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */ #define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */ #define VGE_CR3_INT_HOLDOFF 0x04 /* enable int hold off timer */ #define VGE_CR3_DIAG 0x10 /* diagnostic enabled */ #define VGE_CR3_PHYRST 0x20 /* assert PHYRSTZ */ #define VGE_CR3_STOP_FORCE 0x40 /* force NIC to stopped state */ /* Interrupt control register */ #define VGE_INTCTL_SC_RELOAD 0x01 /* reload hold timer */ #define VGE_INTCTL_HC_RELOAD 0x02 /* enable hold timer reload */ #define VGE_INTCTL_STATUS 0x04 /* interrupt pending status */ #define VGE_INTCTL_MASK 0x18 /* multilayer int mask */ #define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */ #define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */ #define VGE_INTCTL_SOFTINT 0x80 /* request soft interrupt */ #define VGE_INTMASK_LAYER0 0x00 #define VGE_INTMASK_LAYER1 0x08 #define VGE_INTMASK_ALL 0x10 #define VGE_INTMASK_ALL2 0x18 /* Transmit host error status register */ #define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */ #define VGE_TXHOSTERR_TDFETCH_BUSERR 0x02 /* bus error on desc fetch */ #define VGE_TXHOSTERR_TDWBACK_BUSERR 0x04 /* bus error on desc writeback */ #define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */ /* Receive host error status register */ #define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */ #define VGE_RXHOSTERR_RDFETCH_BUSERR 0x02 /* bus error on desc fetch */ #define VGE_RXHOSTERR_RDWBACK_BUSERR 0x04 /* bus error on desc writeback */ #define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */ /* Interrupt status register */ #define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ #define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ #define VGE_ISR_RXOK 0x00000004 /* normal RX done */ #define VGE_ISR_TXOK 0x00000008 /* combo results for next 4 bits */ #define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */ #define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */ #define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */ #define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */ #define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ #define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */ #define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */ #define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */ #define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ #define VGE_ISR_LINKSTS 0x00008000 /* link status change */ #define VGE_ISR_TIMER0 0x00010000 /* one shot timer expired */ #define VGE_ISR_TIMER1 0x00020000 /* periodic timer expired */ #define VGE_ISR_PWR 0x00040000 /* wake up power event */ #define VGE_ISR_PHYINT 0x00080000 /* PHY interrupt */ #define VGE_ISR_STOPPED 0x00100000 /* software shutdown complete */ #define VGE_ISR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ #define VGE_ISR_SOFTINT 0x00400000 /* software interrupt */ #define VGE_ISR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ #define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */ #define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ #define VGE_ISR_ISRC0 0x10000000 /* interrupt source indication */ #define VGE_ISR_ISRC1 0x20000000 /* interrupt source indication */ #define VGE_ISR_ISRC2 0x40000000 /* interrupt source indication */ #define VGE_ISR_ISRC3 0x80000000 /* interrupt source indication */ #define VGE_INTRS (VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED| \ VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \ VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \ VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL) +#define VGE_INTRS_POLLING (VGE_ISR_PHYINT|VGE_ISR_LINKSTS) + /* Interrupt mask register */ #define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ #define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ #define VGE_IMR_RXOK 0x00000004 /* normal RX done */ #define VGE_IMR_TXOK 0x00000008 /* combo results for next 4 bits */ #define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */ #define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */ #define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */ #define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */ #define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ #define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */ #define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */ #define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */ #define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ #define VGE_IMR_LINKSTS 0x00008000 /* link status change */ #define VGE_IMR_TIMER0 0x00010000 /* one shot timer expired */ #define VGE_IMR_TIMER1 0x00020000 /* periodic timer expired */ #define VGE_IMR_PWR 0x00040000 /* wake up power event */ #define VGE_IMR_PHYINT 0x00080000 /* PHY interrupt */ #define VGE_IMR_STOPPED 0x00100000 /* software shutdown complete */ #define VGE_IMR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ #define VGE_IMR_SOFTINT 0x00400000 /* software interrupt */ #define VGE_IMR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ #define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */ #define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ #define VGE_IMR_ISRC0 0x10000000 /* interrupt source indication */ #define VGE_IMR_ISRC1 0x20000000 /* interrupt source indication */ #define VGE_IMR_ISRC2 0x40000000 /* interrupt source indication */ #define VGE_IMR_ISRC3 0x80000000 /* interrupt source indication */ /* TX descriptor queue control/status register */ #define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */ #define VGE_TXQCSR_ACT0 0x0002 /* queue 0 active indicator */ #define VGE_TXQCSR_WAK0 0x0004 /* Wake up (poll) queue 0 */ #define VGE_TXQCSR_DEAD0 0x0008 /* queue 0 dead indicator */ #define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */ #define VGE_TXQCSR_ACT1 0x0020 /* queue 1 active indicator */ #define VGE_TXQCSR_WAK1 0x0040 /* Wake up (poll) queue 1 */ #define VGE_TXQCSR_DEAD1 0x0080 /* queue 1 dead indicator */ #define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */ #define VGE_TXQCSR_ACT2 0x0200 /* queue 2 active indicator */ #define VGE_TXQCSR_WAK2 0x0400 /* Wake up (poll) queue 2 */ #define VGE_TXQCSR_DEAD2 0x0800 /* queue 2 dead indicator */ #define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */ #define VGE_TXQCSR_ACT3 0x2000 /* queue 3 active indicator */ #define VGE_TXQCSR_WAK3 0x4000 /* Wake up (poll) queue 3 */ #define VGE_TXQCSR_DEAD3 0x8000 /* queue 3 dead indicator */ /* RX descriptor queue control/status register */ #define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */ #define VGE_RXQCSR_ACT 0x0002 /* queue active indicator */ #define VGE_RXQCSR_WAK 0x0004 /* Wake up (poll) queue */ #define VGE_RXQCSR_DEAD 0x0008 /* queue dead indicator */ /* RX/TX queue empty interrupt delay timer register */ #define VGE_QTIMER_PENDCNT 0x3F #define VGE_QTIMER_RESOLUTION 0xC0 #define VGE_QTIMER_RES_1US 0x00 #define VGE_QTIMER_RES_4US 0x40 #define VGE_QTIMER_RES_16US 0x80 #define VGE_QTIMER_RES_64US 0xC0 /* CAM address register */ #define VGE_CAMADDR_ADDR 0x3F /* CAM address to program */ #define VGE_CAMADDR_AVSEL 0x40 /* 0 = address cam, 1 = VLAN cam */ #define VGE_CAMADDR_ENABLE 0x80 /* enable CAM read/write */ #define VGE_CAM_MAXADDRS 64 /* * CAM command register * Note that the page select bits in this register affect three * different things: * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the * page select bits control whether the MAR0/MAR1 registers affect * the multicast hash filter or the CAM table) * - The behavior of the interrupt holdoff timer register at offset * 0x20 (the page select bits allow you to set the interrupt * holdoff timer, the TX interrupt supression count or the * RX interrupt supression count) * - The behavior the WOL pattern programming registers at offset * 0xC0 (controls which pattern is set) */ #define VGE_CAMCTL_WRITE 0x04 /* CAM write command */ #define VGE_CAMCTL_READ 0x08 /* CAM read command */ #define VGE_CAMCTL_INTPKT_SIZ 0x10 /* select interesting pkt CAM size */ #define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */ #define VGE_CAMCTL_PAGESEL 0xC0 /* page select */ #define VGE_PAGESEL_MAR 0x00 #define VGE_PAGESEL_CAMMASK 0x40 #define VGE_PAGESEL_CAMDATA 0x80 #define VGE_PAGESEL_INTHLDOFF 0x00 #define VGE_PAGESEL_TXSUPPTHR 0x40 #define VGE_PAGESEL_RXSUPPTHR 0x80 #define VGE_PAGESEL_WOLPAT0 0x00 #define VGE_PAGESEL_WOLPAT1 0x40 /* MII port config register */ #define VGE_MIICFG_PHYADDR 0x1F /* PHY address (internal PHY is 1) */ #define VGE_MIICFG_MDCSPEED 0x20 /* MDC accelerate x 4 */ #define VGE_MIICFG_POLLINT 0xC0 /* polling interval */ #define VGE_MIIPOLLINT_1024 0x00 #define VGE_MIIPOLLINT_512 0x40 #define VGE_MIIPOLLINT_128 0x80 #define VGE_MIIPOLLINT_64 0xC0 /* MII port status register */ #define VGE_MIISTS_IIDL 0x80 /* not at sofrware/timer poll cycle */ /* PHY status register */ #define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */ #define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */ #define VGE_PHYSTS_SPEED10 0x04 /* PHY in 10Mbps mode */ #define VGE_PHYSTS_SPEED1000 0x08 /* PHY in giga mode */ #define VGE_PHYSTS_FDX 0x10 /* PHY in full duplex mode */ #define VGE_PHYSTS_LINK 0x40 /* link status */ #define VGE_PHYSTS_RESETSTS 0x80 /* reset status */ /* MII management command register */ #define VGE_MIICMD_MDC 0x01 /* clock pin */ #define VGE_MIICMD_MDI 0x02 /* data in pin */ #define VGE_MIICMD_MDO 0x04 /* data out pin */ #define VGE_MIICMD_MOUT 0x08 /* data out pin enable */ #define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */ #define VGE_MIICMD_WCMD 0x20 /* embedded mode write */ #define VGE_MIICMD_RCMD 0x40 /* embadded mode read */ #define VGE_MIICMD_MAUTO 0x80 /* enable autopolling */ /* MII address register */ #define VGE_MIIADDR_SWMPL 0x80 /* initiate priority resolution */ /* Chip config register A */ #define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */ #define VGE_CHIPCFG0_ABSHDN 0x02 /* abnormal shutdown function */ #define VGE_CHIPCFG0_GPIO1PD 0x04 /* GPIO pin enable */ #define VGE_CHIPCFG0_SKIPTAG 0x08 /* omit 802.1p tag from CRC calc */ #define VGE_CHIPCFG0_PHLED 0x30 /* phy LED select */ /* Chip config register B */ /* Note: some of these bits are not documented in the manual! */ #define VGE_CHIPCFG1_BAKOPT 0x01 #define VGE_CHIPCFG1_MBA 0x02 #define VGE_CHIPCFG1_CAP 0x04 #define VGE_CHIPCFG1_CRANDOM 0x08 #define VGE_CHIPCFG1_OFSET 0x10 #define VGE_CHIPCFG1_SLOTTIME 0x20 /* slot time 512/500 in giga mode */ #define VGE_CHIPCFG1_MIIOPT 0x40 #define VGE_CHIPCFG1_GTCKOPT 0x80 /* Chip config register C */ #define VGE_CHIPCFG2_EELOAD 0x80 /* enable EEPROM programming */ /* Chip config register D */ #define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */ #define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */ /* DMA config register 0 */ #define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */ #define VGE_DMABURST_8 0x00 #define VGE_DMABURST_16 0x01 #define VGE_DMABURST_32 0x02 #define VGE_DMABURST_64 0x03 #define VGE_DMABURST_128 0x04 #define VGE_DMABURST_256 0x05 #define VGE_DMABURST_STRFWD 0x07 /* DMA config register 1 */ #define VGE_DMACFG1_LATENB 0x01 /* Latency timer enable */ #define VGE_DMACFG1_MWWAIT 0x02 /* insert wait on master write */ #define VGE_DMACFG1_MRWAIT 0x04 /* insert wait on master read */ #define VGE_DMACFG1_MRM 0x08 /* use memory read multiple */ #define VGE_DMACFG1_PERR_DIS 0x10 /* disable parity error checking */ #define VGE_DMACFG1_XMRL 0x20 /* disable memory read line support */ /* RX MAC config register */ #define VGE_RXCFG_VLANFILT 0x01 /* filter VLAN ID mismatches */ #define VGE_RXCFG_VTAGOPT 0x06 /* VLAN tag handling */ #define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */ #define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */ #define VGE_RXCFG_ARB_PRIO 0x80 /* arbitration priority */ #define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion RX: rx all, no tag extraction */ #define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion RX: rx only tagged pkts, no extraction */ #define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion, RX: rx all, extract tags */ #define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion, RX: rx only tagged pkts, with extraction */ #define VGE_RXFIFOTHR_128BYTES 0x00 #define VGE_RXFIFOTHR_512BYTES 0x10 #define VGE_RXFIFOTHR_1024BYTES 0x20 #define VGE_RXFIFOTHR_STRNFWD 0x30 /* TX MAC config register */ #define VGE_TXCFG_SNAPOPT 0x01 /* 1 == insert VLAN tag at 13th byte 0 == insert VLANM tag after SNAP header (21st byte) */ #define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */ #define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */ #define VGE_TXCFG_ARB_PRIO 0x80 /* arbitration priority */ #define VGE_TXBLOCK_64PKTS 0x00 #define VGE_TXBLOCK_32PKTS 0x04 #define VGE_TXBLOCK_128PKTS 0x08 #define VGE_TXBLOCK_8PKTS 0x0C /* MIB control/status register */ #define VGE_MIBCSR_CLR 0x01 #define VGE_MIBCSR_RINI 0x02 #define VGE_MIBCSR_FLUSH 0x04 #define VGE_MIBCSR_FREEZE 0x08 #define VGE_MIBCSR_HI_80 0x00 #define VGE_MIBCSR_HI_C0 0x10 #define VGE_MIBCSR_BISTGO 0x40 #define VGE_MIBCSR_BISTOK 0x80 /* MIB data index. */ #define VGE_MIB_RX_FRAMES 0 #define VGE_MIB_RX_GOOD_FRAMES 1 #define VGE_MIB_TX_GOOD_FRAMES 2 #define VGE_MIB_RX_FIFO_OVERRUNS 3 #define VGE_MIB_RX_RUNTS 4 #define VGE_MIB_RX_RUNTS_ERRS 5 #define VGE_MIB_RX_PKTS_64 6 #define VGE_MIB_TX_PKTS_64 7 #define VGE_MIB_RX_PKTS_65_127 8 #define VGE_MIB_TX_PKTS_65_127 9 #define VGE_MIB_RX_PKTS_128_255 10 #define VGE_MIB_TX_PKTS_128_255 11 #define VGE_MIB_RX_PKTS_256_511 12 #define VGE_MIB_TX_PKTS_256_511 13 #define VGE_MIB_RX_PKTS_512_1023 14 #define VGE_MIB_TX_PKTS_512_1023 15 #define VGE_MIB_RX_PKTS_1024_1518 16 #define VGE_MIB_TX_PKTS_1024_1518 17 #define VGE_MIB_TX_COLLS 18 #define VGE_MIB_RX_CRCERRS 19 #define VGE_MIB_RX_JUMBOS 20 #define VGE_MIB_TX_JUMBOS 21 #define VGE_MIB_RX_PAUSE 22 #define VGE_MIB_TX_PAUSE 23 #define VGE_MIB_RX_ALIGNERRS 24 #define VGE_MIB_RX_PKTS_1519_MAX 25 #define VGE_MIB_RX_PKTS_1519_MAX_ERRS 26 #define VGE_MIB_TX_SQEERRS 27 #define VGE_MIB_RX_NOBUFS 28 #define VGE_MIB_RX_SYMERRS 29 #define VGE_MIB_RX_LENERRS 30 #define VGE_MIB_TX_LATECOLLS 31 #define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1) #define VGE_MIB_DATA_MASK 0x00FFFFFF #define VGE_MIB_DATA_IDX(x) ((x) >> 24) /* Sticky bit shadow register */ #define VGE_STICKHW_DS0 0x01 #define VGE_STICKHW_DS1 0x02 #define VGE_STICKHW_WOL_ENB 0x04 #define VGE_STICKHW_WOL_STS 0x08 #define VGE_STICKHW_SWPTAG 0x10 /* WOL pattern control */ #define VGE_WOLCR0_PATTERN0 0x01 #define VGE_WOLCR0_PATTERN1 0x02 #define VGE_WOLCR0_PATTERN2 0x04 #define VGE_WOLCR0_PATTERN3 0x08 #define VGE_WOLCR0_PATTERN4 0x10 #define VGE_WOLCR0_PATTERN5 0x20 #define VGE_WOLCR0_PATTERN6 0x40 #define VGE_WOLCR0_PATTERN7 0x80 #define VGE_WOLCR0_PATTERN_ALL 0xFF /* WOL event control */ #define VGE_WOLCR1_UCAST 0x01 #define VGE_WOLCR1_MAGIC 0x02 #define VGE_WOLCR1_LINKON 0x04 #define VGE_WOLCR1_LINKOFF 0x08 /* Poweer management config */ #define VGE_PWRCFG_LEGACY_WOLEN 0x01 #define VGE_PWRCFG_WOL_PULSE 0x20 #define VGE_PWRCFG_WOL_BUTTON 0x00 /* WOL config register */ #define VGE_WOLCFG_PHYINT_ENB 0x01 #define VGE_WOLCFG_SAB 0x10 #define VGE_WOLCFG_SAM 0x20 #define VGE_WOLCFG_PMEOVR 0x80 /* EEPROM control/status register */ #define VGE_EECSR_EDO 0x01 /* data out pin */ #define VGE_EECSR_EDI 0x02 /* data in pin */ #define VGE_EECSR_ECK 0x04 /* clock pin */ #define VGE_EECSR_ECS 0x08 /* chip select pin */ #define VGE_EECSR_DPM 0x10 /* direct program mode enable */ #define VGE_EECSR_RELOAD 0x20 /* trigger reload from EEPROM */ #define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */ /* EEPROM embedded command register */ #define VGE_EECMD_ERD 0x01 /* EEPROM read command */ #define VGE_EECMD_EWR 0x02 /* EEPROM write command */ #define VGE_EECMD_EWEN 0x04 /* EEPROM write enable */ #define VGE_EECMD_EWDIS 0x08 /* EEPROM write disable */ #define VGE_EECMD_EDONE 0x80 /* read/write done */ /* Chip operation and diagnostic control register */ #define VGE_DIAGCTL_PHYINT_ENB 0x01 /* Enable PHY interrupts */ #define VGE_DIAGCTL_TIMER0_RES 0x02 /* timer0 uSec resolution */ #define VGE_DIAGCTL_TIMER1_RES 0x04 /* timer1 uSec resolution */ #define VGE_DIAGCTL_LPSEL_DIS 0x08 /* disable LPSEL field */ #define VGE_DIAGCTL_MACFORCE 0x10 /* MAC side force mode */ #define VGE_DIAGCTL_FCRSVD 0x20 /* reserved for future fiber use */ #define VGE_DIAGCTL_FDXFORCE 0x40 /* force full duplex mode */ #define VGE_DIAGCTL_GMII 0x80 /* force GMII mode, otherwise MII */ /* Location of station address in EEPROM */ #define VGE_EE_EADDR 0 /* DMA descriptor structures */ /* * Each TX DMA descriptor has a control and status word, and 7 * fragment address/length words. If a transmitted packet spans * more than 7 fragments, it has to be coalesced. */ #define VGE_TX_FRAGS 7 struct vge_tx_frag { uint32_t vge_addrlo; uint32_t vge_addrhi; }; /* * The high bit in the buflen field of fragment #0 has special meaning. * Normally, the chip requires the driver to issue a TX poll command * for every packet that gets put in the TX DMA queue. Sometimes though, * the driver might want to queue up several packets at once and just * issue one transmit command to have all of them processed. In order * to obtain this behavior, the special 'queue' bit must be set. */ #define VGE_TXDESC_Q 0x80000000 struct vge_tx_desc { uint32_t vge_sts; uint32_t vge_ctl; struct vge_tx_frag vge_frag[VGE_TX_FRAGS]; }; #define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */ #define VGE_TDSTS_COLL 0x00000010 /* collision seen */ #define VGE_TDSTS_OWINCOLL 0x00000020 /* out of window collision */ #define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */ #define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */ #define VGE_TDSTS_HBEATFAIL 0x00000100 /* heartbeat detect failed */ #define VGE_TDSTS_CARRLOSS 0x00000200 /* carrier sense lost */ #define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */ #define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */ #define VGE_TDSTS_GMII 0x00002000 /* GMII transmission */ #define VGE_TDSTS_FDX 0x00004000 /* full duplex transmit */ #define VGE_TDSTS_TXERR 0x00008000 /* error occurred */ #define VGE_TDSTS_SEGSIZE 0x3FFF0000 /* TCP large send size */ #define VGE_TDSTS_OWN 0x80000000 /* own bit */ #define VGE_TDCTL_VLANID 0x00000FFF /* VLAN ID */ #define VGE_TDCTL_CFI 0x00001000 /* VLAN CFI bit */ #define VGE_TDCTL_PRIO 0x0000E000 /* VLAN prio bits */ #define VGE_TDCTL_NOCRC 0x00010000 /* disable CRC generation */ #define VGE_TDCTL_JUMBO 0x00020000 /* jumbo frame */ #define VGE_TDCTL_TCPCSUM 0x00040000 /* do TCP hw checksum */ #define VGE_TDCTL_UDPCSUM 0x00080000 /* do UDP hw checksum */ #define VGE_TDCTL_IPCSUM 0x00100000 /* do IP hw checksum */ #define VGE_TDCTL_VTAG 0x00200000 /* insert VLAN tag */ #define VGE_TDCTL_PRIO_INT 0x00400000 /* priority int request */ #define VGE_TDCTL_TIC 0x00800000 /* transfer int request */ #define VGE_TDCTL_TCPLSCTL 0x03000000 /* TCP large send ctl */ #define VGE_TDCTL_FRAGCNT 0xF0000000 /* number of frags used */ #define VGE_TD_LS_MOF 0x00000000 /* middle of large send */ #define VGE_TD_LS_SOF 0x01000000 /* start of large send */ #define VGE_TD_LS_EOF 0x02000000 /* end of large send */ #define VGE_TD_LS_NORM 0x03000000 /* normal frame */ /* Receive DMA descriptors have a single fragment pointer. */ struct vge_rx_desc { uint32_t vge_sts; uint32_t vge_ctl; uint32_t vge_addrlo; uint32_t vge_addrhi; }; /* * Like the TX descriptor, the high bit in the buflen field in the * RX descriptor has special meaning. This bit controls whether or * not interrupts are generated for this descriptor. */ #define VGE_RXDESC_I 0x80000000 #define VGE_RDSTS_VIDM 0x00000001 /* VLAN tag filter miss */ #define VGE_RDSTS_CRCERR 0x00000002 /* bad CRC error */ #define VGE_RDSTS_FAERR 0x00000004 /* frame alignment error */ #define VGE_RDSTS_CSUMERR 0x00000008 /* bad TCP/IP checksum */ #define VGE_RDSTS_RLERR 0x00000010 /* RX length error */ #define VGE_RDSTS_SYMERR 0x00000020 /* PCS symbol error */ #define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */ #define VGE_RDSTS_DETAG 0x00000080 /* VLAN tag extracted */ #define VGE_RDSTS_BOUNDARY 0x00000300 /* frame boundary bits */ #define VGE_RDSTS_VTAG 0x00000400 /* VLAN tag indicator */ #define VGE_RDSTS_UCAST 0x00000800 /* unicast frame */ #define VGE_RDSTS_BCAST 0x00001000 /* broadcast frame */ #define VGE_RDSTS_MCAST 0x00002000 /* multicast frame */ #define VGE_RDSTS_PFT 0x00004000 /* perfect filter hit */ #define VGE_RDSTS_RXOK 0x00008000 /* frame is good. */ #define VGE_RDSTS_BUFSIZ 0x3FFF0000 /* received frame len */ #define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */ #define VGE_RDSTS_OWN 0x80000000 /* own bit. */ #define VGE_RXPKT_ONEFRAG 0x00000000 /* only one fragment */ #define VGE_RXPKT_EOF 0x00000100 /* last frag in frame */ #define VGE_RXPKT_SOF 0x00000200 /* first frag in frame */ #define VGE_RXPKT_MOF 0x00000300 /* intermediate frag */ #define VGE_RDCTL_VLANID 0x0000FFFF /* VLAN ID info */ #define VGE_RDCTL_UDPPKT 0x00010000 /* UDP packet received */ #define VGE_RDCTL_TCPPKT 0x00020000 /* TCP packet received */ #define VGE_RDCTL_IPPKT 0x00040000 /* IP packet received */ #define VGE_RDCTL_UDPZERO 0x00080000 /* pkt with UDP CSUM of 0 */ #define VGE_RDCTL_FRAG 0x00100000 /* received IP frag */ #define VGE_RDCTL_PROTOCSUMOK 0x00200000 /* TCP/UDP checksum ok */ #define VGE_RDCTL_IPCSUMOK 0x00400000 /* IP checksum ok */ #define VGE_RDCTL_FILTIDX 0x3C000000 /* interesting filter idx */ #endif /* _IF_VGEREG_H_ */ Index: stable/7/sys =================================================================== --- stable/7/sys (revision 225594) +++ stable/7/sys (revision 225595) Property changes on: stable/7/sys ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys:r225440