Index: stable/8/sys/amd64/include/xen =================================================================== --- stable/8/sys/amd64/include/xen (revision 222793) +++ stable/8/sys/amd64/include/xen (revision 222794) Property changes on: stable/8/sys/amd64/include/xen ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/amd64/include/xen:r222509-222510,222513,222551-222552,222701,222703 Index: stable/8/sys/cddl/contrib/opensolaris =================================================================== --- stable/8/sys/cddl/contrib/opensolaris (revision 222793) +++ stable/8/sys/cddl/contrib/opensolaris (revision 222794) Property changes on: stable/8/sys/cddl/contrib/opensolaris ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/cddl/contrib/opensolaris:r222509-222510,222513,222551-222552,222701,222703 Index: stable/8/sys/conf/files =================================================================== --- stable/8/sys/conf/files (revision 222793) +++ stable/8/sys/conf/files (revision 222794) @@ -1,3003 +1,3005 @@ # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # acpi_quirks.h optional acpi \ dependency "$S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \ compile-with "${AWK} -f $S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \ no-obj no-implicit-rule before-depend \ clean "acpi_quirks.h" aicasm optional ahc | ahd \ dependency "$S/dev/aic7xxx/aicasm/*.[chyl]" \ compile-with "CC='${CC}' ${MAKE} -f $S/dev/aic7xxx/aicasm/Makefile MAKESRCPATH=$S/dev/aic7xxx/aicasm" \ no-obj no-implicit-rule \ clean "aicasm* y.tab.h" aic7xxx_seq.h optional ahc \ compile-with "./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic7xxx_seq.h -r aic7xxx_reg.h -p aic7xxx_reg_print.c -i $S/dev/aic7xxx/aic7xxx_osm.h $S/dev/aic7xxx/aic7xxx.seq" \ no-obj no-implicit-rule before-depend local \ clean "aic7xxx_seq.h" \ dependency "$S/dev/aic7xxx/aic7xxx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm" aic7xxx_reg.h optional ahc \ compile-with "./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic7xxx_seq.h -r aic7xxx_reg.h -p aic7xxx_reg_print.c -i $S/dev/aic7xxx/aic7xxx_osm.h $S/dev/aic7xxx/aic7xxx.seq" \ no-obj no-implicit-rule before-depend local \ clean "aic7xxx_reg.h" \ dependency "$S/dev/aic7xxx/aic7xxx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm" aic7xxx_reg_print.c optional ahc \ compile-with "./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic7xxx_seq.h -r aic7xxx_reg.h -p aic7xxx_reg_print.c -i $S/dev/aic7xxx/aic7xxx_osm.h $S/dev/aic7xxx/aic7xxx.seq" \ no-obj no-implicit-rule local \ clean "aic7xxx_reg_print.c" \ dependency "$S/dev/aic7xxx/aic7xxx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm" aic7xxx_reg_print.o optional ahc ahc_reg_pretty_print \ compile-with "${NORMAL_C}" \ no-implicit-rule local aic79xx_seq.h optional ahd pci \ compile-with "./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic79xx_seq.h -r aic79xx_reg.h -p aic79xx_reg_print.c -i $S/dev/aic7xxx/aic79xx_osm.h $S/dev/aic7xxx/aic79xx.seq" \ no-obj no-implicit-rule before-depend local \ clean "aic79xx_seq.h" \ dependency "$S/dev/aic7xxx/aic79xx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm" aic79xx_reg.h optional ahd pci \ compile-with "./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic79xx_seq.h -r aic79xx_reg.h -p aic79xx_reg_print.c -i $S/dev/aic7xxx/aic79xx_osm.h $S/dev/aic7xxx/aic79xx.seq" \ no-obj no-implicit-rule before-depend local \ clean "aic79xx_reg.h" \ dependency "$S/dev/aic7xxx/aic79xx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm" aic79xx_reg_print.c optional ahd pci \ compile-with "./aicasm ${INCLUDES} -I$S/cam/scsi -I$S/dev/aic7xxx -o aic79xx_seq.h -r aic79xx_reg.h -p aic79xx_reg_print.c -i $S/dev/aic7xxx/aic79xx_osm.h $S/dev/aic7xxx/aic79xx.seq" \ no-obj no-implicit-rule local \ clean "aic79xx_reg_print.c" \ dependency "$S/dev/aic7xxx/aic79xx.{reg,seq} $S/cam/scsi/scsi_message.h aicasm" aic79xx_reg_print.o optional ahd pci ahd_reg_pretty_print \ compile-with "${NORMAL_C}" \ no-implicit-rule local emu10k1-alsa%diked.h optional snd_emu10k1 | snd_emu10kx \ dependency "$S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/emu10k1-alsa.h" \ compile-with "CC='${CC}' AWK=${AWK} sh $S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/emu10k1-alsa.h emu10k1-alsa%diked.h" \ no-obj no-implicit-rule before-depend \ clean "emu10k1-alsa%diked.h" p16v-alsa%diked.h optional snd_emu10kx pci \ dependency "$S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/p16v-alsa.h" \ compile-with "CC='${CC}' AWK=${AWK} sh $S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/p16v-alsa.h p16v-alsa%diked.h" \ no-obj no-implicit-rule before-depend \ clean "p16v-alsa%diked.h" p17v-alsa%diked.h optional snd_emu10kx pci \ dependency "$S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/p17v-alsa.h" \ compile-with "CC='${CC}' AWK=${AWK} sh $S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/p17v-alsa.h p17v-alsa%diked.h" \ no-obj no-implicit-rule before-depend \ clean "p17v-alsa%diked.h" feeder_eq_gen.h optional sound \ dependency "$S/tools/sound/feeder_eq_mkfilter.awk" \ compile-with "${AWK} -f $S/tools/sound/feeder_eq_mkfilter.awk -- ${FEEDER_EQ_PRESETS} > feeder_eq_gen.h" \ no-obj no-implicit-rule before-depend \ clean "feeder_eq_gen.h" feeder_rate_gen.h optional sound \ dependency "$S/tools/sound/feeder_rate_mkfilter.awk" \ compile-with "${AWK} -f $S/tools/sound/feeder_rate_mkfilter.awk -- ${FEEDER_RATE_PRESETS} > feeder_rate_gen.h" \ no-obj no-implicit-rule before-depend \ clean "feeder_rate_gen.h" snd_fxdiv_gen.h optional sound \ dependency "$S/tools/sound/snd_fxdiv_gen.awk" \ compile-with "${AWK} -f $S/tools/sound/snd_fxdiv_gen.awk -- > snd_fxdiv_gen.h" \ no-obj no-implicit-rule before-depend \ clean "snd_fxdiv_gen.h" miidevs.h optional miibus | mii \ dependency "$S/tools/miidevs2h.awk $S/dev/mii/miidevs" \ compile-with "${AWK} -f $S/tools/miidevs2h.awk $S/dev/mii/miidevs" \ no-obj no-implicit-rule before-depend \ clean "miidevs.h" pccarddevs.h standard \ dependency "$S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \ compile-with "${AWK} -f $S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \ no-obj no-implicit-rule before-depend \ clean "pccarddevs.h" teken_state.h optional sc \ dependency "$S/dev/syscons/teken/gensequences $S/dev/syscons/teken/sequences" \ compile-with "${AWK} -f $S/dev/syscons/teken/gensequences $S/dev/syscons/teken/sequences > teken_state.h" \ no-obj no-implicit-rule before-depend \ clean "teken_state.h" usbdevs.h optional usb \ dependency "$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \ compile-with "${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -h" \ no-obj no-implicit-rule before-depend \ clean "usbdevs.h" usbdevs_data.h optional usb \ dependency "$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \ compile-with "${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -d" \ no-obj no-implicit-rule before-depend \ clean "usbdevs_data.h" cam/cam.c optional scbus cam/cam_periph.c optional scbus cam/cam_queue.c optional scbus cam/cam_sim.c optional scbus cam/cam_xpt.c optional scbus cam/ata/ata_all.c optional scbus cam/ata/ata_xpt.c optional scbus cam/ata/ata_pmp.c optional scbus cam/scsi/scsi_xpt.c optional scbus cam/scsi/scsi_all.c optional scbus cam/scsi/scsi_cd.c optional cd cam/scsi/scsi_ch.c optional ch cam/ata/ata_da.c optional ada | da cam/scsi/scsi_da.c optional da cam/scsi/scsi_low.c optional ct | ncv | nsp | stg cam/scsi/scsi_low_pisa.c optional ct | ncv | nsp | stg cam/scsi/scsi_pass.c optional pass cam/scsi/scsi_pt.c optional pt cam/scsi/scsi_sa.c optional sa cam/scsi/scsi_ses.c optional ses cam/scsi/scsi_sg.c optional sg cam/scsi/scsi_targ_bh.c optional targbh cam/scsi/scsi_target.c optional targ contrib/altq/altq/altq_cbq.c optional altq \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/altq/altq/altq_cdnr.c optional altq contrib/altq/altq/altq_hfsc.c optional altq \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/altq/altq/altq_priq.c optional altq \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/altq/altq/altq_red.c optional altq \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/altq/altq/altq_rio.c optional altq \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/altq/altq/altq_rmclass.c optional altq contrib/altq/altq/altq_subr.c optional altq \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/dev/acpica/debugger/dbcmds.c optional acpi acpi_debug contrib/dev/acpica/debugger/dbdisply.c optional acpi acpi_debug contrib/dev/acpica/debugger/dbexec.c optional acpi acpi_debug contrib/dev/acpica/debugger/dbfileio.c optional acpi acpi_debug contrib/dev/acpica/debugger/dbhistry.c optional acpi acpi_debug contrib/dev/acpica/debugger/dbinput.c optional acpi acpi_debug contrib/dev/acpica/debugger/dbstats.c optional acpi acpi_debug contrib/dev/acpica/debugger/dbutils.c optional acpi acpi_debug contrib/dev/acpica/debugger/dbxface.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmbuffer.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmnames.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmopcode.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmobject.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmresrc.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmresrcl.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmresrcs.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmutils.c optional acpi acpi_debug contrib/dev/acpica/disassembler/dmwalk.c optional acpi acpi_debug contrib/dev/acpica/dispatcher/dsfield.c optional acpi contrib/dev/acpica/dispatcher/dsinit.c optional acpi contrib/dev/acpica/dispatcher/dsmethod.c optional acpi contrib/dev/acpica/dispatcher/dsmthdat.c optional acpi contrib/dev/acpica/dispatcher/dsobject.c optional acpi contrib/dev/acpica/dispatcher/dsopcode.c optional acpi contrib/dev/acpica/dispatcher/dsutils.c optional acpi contrib/dev/acpica/dispatcher/dswexec.c optional acpi contrib/dev/acpica/dispatcher/dswload.c optional acpi contrib/dev/acpica/dispatcher/dswscope.c optional acpi contrib/dev/acpica/dispatcher/dswstate.c optional acpi contrib/dev/acpica/events/evevent.c optional acpi contrib/dev/acpica/events/evgpe.c optional acpi contrib/dev/acpica/events/evgpeblk.c optional acpi contrib/dev/acpica/events/evgpeinit.c optional acpi contrib/dev/acpica/events/evgpeutil.c optional acpi contrib/dev/acpica/events/evmisc.c optional acpi contrib/dev/acpica/events/evregion.c optional acpi contrib/dev/acpica/events/evrgnini.c optional acpi contrib/dev/acpica/events/evsci.c optional acpi contrib/dev/acpica/events/evxface.c optional acpi contrib/dev/acpica/events/evxfevnt.c optional acpi contrib/dev/acpica/events/evxfregn.c optional acpi contrib/dev/acpica/executer/exconfig.c optional acpi contrib/dev/acpica/executer/exconvrt.c optional acpi contrib/dev/acpica/executer/excreate.c optional acpi contrib/dev/acpica/executer/exdebug.c optional acpi contrib/dev/acpica/executer/exdump.c optional acpi contrib/dev/acpica/executer/exfield.c optional acpi contrib/dev/acpica/executer/exfldio.c optional acpi contrib/dev/acpica/executer/exmisc.c optional acpi contrib/dev/acpica/executer/exmutex.c optional acpi contrib/dev/acpica/executer/exnames.c optional acpi contrib/dev/acpica/executer/exoparg1.c optional acpi contrib/dev/acpica/executer/exoparg2.c optional acpi contrib/dev/acpica/executer/exoparg3.c optional acpi contrib/dev/acpica/executer/exoparg6.c optional acpi contrib/dev/acpica/executer/exprep.c optional acpi contrib/dev/acpica/executer/exregion.c optional acpi contrib/dev/acpica/executer/exresnte.c optional acpi contrib/dev/acpica/executer/exresolv.c optional acpi contrib/dev/acpica/executer/exresop.c optional acpi contrib/dev/acpica/executer/exstore.c optional acpi contrib/dev/acpica/executer/exstoren.c optional acpi contrib/dev/acpica/executer/exstorob.c optional acpi contrib/dev/acpica/executer/exsystem.c optional acpi contrib/dev/acpica/executer/exutils.c optional acpi contrib/dev/acpica/hardware/hwacpi.c optional acpi contrib/dev/acpica/hardware/hwgpe.c optional acpi contrib/dev/acpica/hardware/hwpci.c optional acpi contrib/dev/acpica/hardware/hwregs.c optional acpi contrib/dev/acpica/hardware/hwsleep.c optional acpi contrib/dev/acpica/hardware/hwtimer.c optional acpi contrib/dev/acpica/hardware/hwvalid.c optional acpi contrib/dev/acpica/hardware/hwxface.c optional acpi contrib/dev/acpica/namespace/nsaccess.c optional acpi contrib/dev/acpica/namespace/nsalloc.c optional acpi contrib/dev/acpica/namespace/nsdump.c optional acpi contrib/dev/acpica/namespace/nseval.c optional acpi contrib/dev/acpica/namespace/nsinit.c optional acpi contrib/dev/acpica/namespace/nsload.c optional acpi contrib/dev/acpica/namespace/nsnames.c optional acpi contrib/dev/acpica/namespace/nsobject.c optional acpi contrib/dev/acpica/namespace/nsparse.c optional acpi contrib/dev/acpica/namespace/nspredef.c optional acpi contrib/dev/acpica/namespace/nsrepair.c optional acpi contrib/dev/acpica/namespace/nsrepair2.c optional acpi contrib/dev/acpica/namespace/nssearch.c optional acpi contrib/dev/acpica/namespace/nsutils.c optional acpi contrib/dev/acpica/namespace/nswalk.c optional acpi contrib/dev/acpica/namespace/nsxfeval.c optional acpi contrib/dev/acpica/namespace/nsxfname.c optional acpi contrib/dev/acpica/namespace/nsxfobj.c optional acpi contrib/dev/acpica/parser/psargs.c optional acpi contrib/dev/acpica/parser/psloop.c optional acpi contrib/dev/acpica/parser/psopcode.c optional acpi contrib/dev/acpica/parser/psparse.c optional acpi contrib/dev/acpica/parser/psscope.c optional acpi contrib/dev/acpica/parser/pstree.c optional acpi contrib/dev/acpica/parser/psutils.c optional acpi contrib/dev/acpica/parser/pswalk.c optional acpi contrib/dev/acpica/parser/psxface.c optional acpi contrib/dev/acpica/resources/rsaddr.c optional acpi contrib/dev/acpica/resources/rscalc.c optional acpi contrib/dev/acpica/resources/rscreate.c optional acpi contrib/dev/acpica/resources/rsdump.c optional acpi contrib/dev/acpica/resources/rsinfo.c optional acpi contrib/dev/acpica/resources/rsio.c optional acpi contrib/dev/acpica/resources/rsirq.c optional acpi contrib/dev/acpica/resources/rslist.c optional acpi contrib/dev/acpica/resources/rsmemory.c optional acpi contrib/dev/acpica/resources/rsmisc.c optional acpi contrib/dev/acpica/resources/rsutils.c optional acpi contrib/dev/acpica/resources/rsxface.c optional acpi contrib/dev/acpica/tables/tbfadt.c optional acpi contrib/dev/acpica/tables/tbfind.c optional acpi contrib/dev/acpica/tables/tbinstal.c optional acpi contrib/dev/acpica/tables/tbutils.c optional acpi contrib/dev/acpica/tables/tbxface.c optional acpi contrib/dev/acpica/tables/tbxfroot.c optional acpi contrib/dev/acpica/utilities/utalloc.c optional acpi contrib/dev/acpica/utilities/utcache.c optional acpi contrib/dev/acpica/utilities/utcopy.c optional acpi contrib/dev/acpica/utilities/utdebug.c optional acpi contrib/dev/acpica/utilities/utdelete.c optional acpi contrib/dev/acpica/utilities/uteval.c optional acpi contrib/dev/acpica/utilities/utglobal.c optional acpi contrib/dev/acpica/utilities/utids.c optional acpi contrib/dev/acpica/utilities/utinit.c optional acpi contrib/dev/acpica/utilities/utlock.c optional acpi contrib/dev/acpica/utilities/utmath.c optional acpi contrib/dev/acpica/utilities/utmisc.c optional acpi contrib/dev/acpica/utilities/utmutex.c optional acpi contrib/dev/acpica/utilities/utobject.c optional acpi contrib/dev/acpica/utilities/utosi.c optional acpi contrib/dev/acpica/utilities/utresrc.c optional acpi contrib/dev/acpica/utilities/utstate.c optional acpi contrib/dev/acpica/utilities/utxface.c optional acpi contrib/dev/acpica/utilities/utxferror.c optional acpi contrib/ipfilter/netinet/fil.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_auth.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_fil_freebsd.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_frag.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_log.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_nat.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_proxy.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_state.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_lookup.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-error -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_pool.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_htable.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_sync.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/mlfk_ipl.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ngatm/netnatm/api/cc_conn.c optional ngatm_ccatm \ compile-with "${NORMAL_C_NOWERROR} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_data.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_dump.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_port.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_sig.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_user.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/unisap.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/misc/straddr.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/misc/unimsg_common.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/traffic.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/uni_ie.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/uni_msg.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/saal/saal_sscfu.c optional ngatm_sscfu \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/saal/saal_sscop.c optional ngatm_sscop \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_call.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_coord.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_party.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_print.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_reset.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_uni.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_unimsgcpy.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_verify.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/pf/net/if_pflog.c optional pflog pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/if_pfsync.c optional pfsync pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/pf.c optional pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/pf_if.c optional pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/pf_ioctl.c optional pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/pf_norm.c optional pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/pf_osfp.c optional pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/pf_ruleset.c optional pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/pf_subr.c optional pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/net/pf_table.c optional pf inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" contrib/pf/netinet/in4_cksum.c optional pf inet crypto/blowfish/bf_ecb.c optional ipsec crypto/blowfish/bf_skey.c optional crypto | ipsec crypto/camellia/camellia.c optional crypto | ipsec crypto/camellia/camellia-api.c optional crypto | ipsec crypto/des/des_ecb.c optional crypto | ipsec | netsmb crypto/des/des_setkey.c optional crypto | ipsec | netsmb crypto/rc4/rc4.c optional netgraph_mppc_encryption | kgssapi crypto/rijndael/rijndael-alg-fst.c optional crypto | geom_bde | \ ipsec | random | wlan_ccmp crypto/rijndael/rijndael-api-fst.c optional geom_bde | random crypto/rijndael/rijndael-api.c optional crypto | ipsec | wlan_ccmp crypto/sha1.c optional carp | crypto | ipsec | \ netgraph_mppc_encryption | sctp crypto/sha2/sha2.c optional crypto | geom_bde | ipsec | random | \ sctp ddb/db_access.c optional ddb ddb/db_break.c optional ddb ddb/db_capture.c optional ddb ddb/db_command.c optional ddb ddb/db_examine.c optional ddb ddb/db_expr.c optional ddb ddb/db_input.c optional ddb ddb/db_lex.c optional ddb ddb/db_main.c optional ddb ddb/db_output.c optional ddb ddb/db_print.c optional ddb ddb/db_ps.c optional ddb ddb/db_run.c optional ddb ddb/db_script.c optional ddb ddb/db_sym.c optional ddb ddb/db_thread.c optional ddb ddb/db_textdump.c optional ddb ddb/db_variables.c optional ddb ddb/db_watch.c optional ddb ddb/db_write_cmd.c optional ddb #dev/dpt/dpt_control.c optional dpt dev/aac/aac.c optional aac dev/aac/aac_cam.c optional aacp aac dev/aac/aac_debug.c optional aac dev/aac/aac_disk.c optional aac dev/aac/aac_linux.c optional aac compat_linux dev/aac/aac_pci.c optional aac pci dev/acpi_support/acpi_wmi.c optional acpi_wmi acpi dev/acpi_support/acpi_aiboost.c optional acpi_aiboost acpi dev/acpi_support/acpi_asus.c optional acpi_asus acpi dev/acpi_support/acpi_fujitsu.c optional acpi_fujitsu acpi dev/acpi_support/acpi_hp.c optional acpi_hp acpi dev/acpi_support/acpi_ibm.c optional acpi_ibm acpi dev/acpi_support/acpi_panasonic.c optional acpi_panasonic acpi dev/acpi_support/acpi_sony.c optional acpi_sony acpi dev/acpi_support/acpi_toshiba.c optional acpi_toshiba acpi dev/acpi_support/atk0110.c optional aibs acpi dev/acpica/Osd/OsdDebug.c optional acpi dev/acpica/Osd/OsdHardware.c optional acpi dev/acpica/Osd/OsdInterrupt.c optional acpi dev/acpica/Osd/OsdMemory.c optional acpi dev/acpica/Osd/OsdSchedule.c optional acpi dev/acpica/Osd/OsdStream.c optional acpi dev/acpica/Osd/OsdSynch.c optional acpi dev/acpica/Osd/OsdTable.c optional acpi dev/acpica/acpi.c optional acpi dev/acpica/acpi_acad.c optional acpi dev/acpica/acpi_battery.c optional acpi dev/acpica/acpi_button.c optional acpi dev/acpica/acpi_cmbat.c optional acpi dev/acpica/acpi_cpu.c optional acpi dev/acpica/acpi_ec.c optional acpi dev/acpica/acpi_hpet.c optional acpi dev/acpica/acpi_isab.c optional acpi isa dev/acpica/acpi_lid.c optional acpi dev/acpica/acpi_package.c optional acpi dev/acpica/acpi_pci.c optional acpi pci dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pcib_acpi.c optional acpi pci dev/acpica/acpi_pcib_pci.c optional acpi pci dev/acpica/acpi_perf.c optional acpi dev/acpica/acpi_powerres.c optional acpi dev/acpica/acpi_quirk.c optional acpi dev/acpica/acpi_resource.c optional acpi dev/acpica/acpi_smbat.c optional acpi dev/acpica/acpi_thermal.c optional acpi dev/acpica/acpi_throttle.c optional acpi dev/acpica/acpi_timer.c optional acpi dev/acpica/acpi_video.c optional acpi_video acpi dev/acpica/acpi_dock.c optional acpi_dock acpi dev/adlink/adlink.c optional adlink dev/advansys/adv_eisa.c optional adv eisa dev/advansys/adv_pci.c optional adv pci dev/advansys/advansys.c optional adv dev/advansys/advlib.c optional adv dev/advansys/advmcode.c optional adv dev/advansys/adw_pci.c optional adw pci dev/advansys/adwcam.c optional adw dev/advansys/adwlib.c optional adw dev/advansys/adwmcode.c optional adw dev/ae/if_ae.c optional ae pci dev/age/if_age.c optional age pci inet dev/agp/agp.c optional agp pci dev/agp/agp_if.m optional agp pci dev/aha/aha.c optional aha dev/aha/aha_isa.c optional aha isa dev/aha/aha_mca.c optional aha mca dev/ahb/ahb.c optional ahb eisa dev/ahci/ahci.c optional ahci pci dev/aic/aic.c optional aic dev/aic/aic_pccard.c optional aic pccard dev/aic7xxx/ahc_eisa.c optional ahc eisa dev/aic7xxx/ahc_isa.c optional ahc isa dev/aic7xxx/ahc_pci.c optional ahc pci dev/aic7xxx/ahd_pci.c optional ahd pci dev/aic7xxx/aic7770.c optional ahc dev/aic7xxx/aic79xx.c optional ahd pci dev/aic7xxx/aic79xx_osm.c optional ahd pci dev/aic7xxx/aic79xx_pci.c optional ahd pci dev/aic7xxx/aic7xxx.c optional ahc dev/aic7xxx/aic7xxx_93cx6.c optional ahc dev/aic7xxx/aic7xxx_osm.c optional ahc dev/aic7xxx/aic7xxx_pci.c optional ahc pci dev/alc/if_alc.c optional alc pci inet dev/ale/if_ale.c optional ale pci inet dev/amd/amd.c optional amd dev/amr/amr.c optional amr dev/amr/amr_cam.c optional amrp amr dev/amr/amr_disk.c optional amr dev/amr/amr_linux.c optional amr compat_linux dev/amr/amr_pci.c optional amr pci dev/an/if_an.c optional an dev/an/if_an_isa.c optional an isa dev/an/if_an_pccard.c optional an pccard dev/an/if_an_pci.c optional an pci dev/asr/asr.c optional asr pci # dev/ata/ata_if.m optional ata | atacore dev/ata/ata-all.c optional ata | atacore dev/ata/ata-dma.c optional ata | atacore dev/ata/ata-lowlevel.c optional ata | atacore dev/ata/ata-queue.c optional ata | atacore dev/ata/ata-sata.c optional ata | atacore dev/ata/ata-card.c optional ata pccard | atapccard dev/ata/ata-cbus.c optional ata pc98 | atapc98 dev/ata/ata-isa.c optional ata isa | ataisa dev/ata/ata-pci.c optional ata pci | atapci dev/ata/chipsets/ata-ahci.c optional ata pci | ataahci | ataacerlabs | \ ataati | ataintel | atajmicron | \ atavia | atanvidia dev/ata/chipsets/ata-acard.c optional ata pci | ataacard dev/ata/chipsets/ata-acerlabs.c optional ata pci | ataacerlabs dev/ata/chipsets/ata-adaptec.c optional ata pci | ataadaptec dev/ata/chipsets/ata-amd.c optional ata pci | ataamd dev/ata/chipsets/ata-ati.c optional ata pci | ataati dev/ata/chipsets/ata-cenatek.c optional ata pci | atacenatek dev/ata/chipsets/ata-cypress.c optional ata pci | atacypress dev/ata/chipsets/ata-cyrix.c optional ata pci | atacyrix dev/ata/chipsets/ata-highpoint.c optional ata pci | atahighpoint dev/ata/chipsets/ata-intel.c optional ata pci | ataintel dev/ata/chipsets/ata-ite.c optional ata pci | ataite dev/ata/chipsets/ata-jmicron.c optional ata pci | atajmicron dev/ata/chipsets/ata-marvell.c optional ata pci | atamarvell | ataadaptec dev/ata/chipsets/ata-micron.c optional ata pci | atamicron dev/ata/chipsets/ata-national.c optional ata pci | atanational dev/ata/chipsets/ata-netcell.c optional ata pci | atanetcell dev/ata/chipsets/ata-nvidia.c optional ata pci | atanvidia dev/ata/chipsets/ata-promise.c optional ata pci | atapromise dev/ata/chipsets/ata-serverworks.c optional ata pci | ataserverworks dev/ata/chipsets/ata-siliconimage.c optional ata pci | atasiliconimage | ataati dev/ata/chipsets/ata-sis.c optional ata pci | atasis dev/ata/chipsets/ata-via.c optional ata pci | atavia dev/ata/ata-disk.c optional atadisk dev/ata/ata-raid.c optional ataraid dev/ata/atapi-cd.c optional atapicd dev/ata/atapi-fd.c optional atapifd dev/ata/atapi-tape.c optional atapist dev/ata/atapi-cam.c optional atapicam # dev/ath/if_ath.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_pci.c optional ath pci \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ah_osdep.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/ath_hal/ah.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v1.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v3.c optional ath_hal | ath_ar5211 | ath_ar5212 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v14.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v4k.c \ optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_regdomain.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" # ar5210 dev/ath/ath_hal/ar5210/ar5210_attach.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_beacon.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_interrupts.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_keycache.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_misc.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_phy.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_power.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_recv.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_reset.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_xmit.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5211 dev/ath/ath_hal/ar5211/ar5211_attach.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_beacon.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_interrupts.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_keycache.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_misc.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_phy.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_power.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_recv.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_reset.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_xmit.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5212 dev/ath/ath_hal/ar5212/ar5212_ani.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_attach.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_beacon.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_eeprom.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_gpio.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_interrupts.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_keycache.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_misc.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_phy.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_power.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_recv.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_reset.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_rfgain.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_xmit.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5416 (depends on ar5212) dev/ath/ath_hal/ar5416/ar5416_ani.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_attach.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_beacon.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_iq.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_eeprom.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_gpio.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_interrupts.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_keycache.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_misc.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_phy.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_power.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_recv.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_reset.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_xmit.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9160 (depends on ar5416) dev/ath/ath_hal/ar5416/ar9160_attach.c optional ath_hal | ath_ar9160 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9280 (depends on ar5416) dev/ath/ath_hal/ar5416/ar9280_attach.c optional ath_hal | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9285 (depends on ar5416 and ar9280) dev/ath/ath_hal/ar5416/ar9285_attach.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar9285_reset.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # rf backends dev/ath/ath_hal/ar5212/ar2316.c optional ath_rf2316 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2317.c optional ath_rf2317 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2413.c optional ath_hal | ath_rf2413 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2425.c optional ath_hal | ath_rf2425 | ath_rf2417 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5111.c optional ath_hal | ath_rf5111 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5112.c optional ath_hal | ath_rf5112 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5413.c optional ath_hal | ath_rf5413 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar2133.c optional ath_hal | ath_ar5416 | ath_ar9160 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar9280.c optional ath_hal | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar9285.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ath rate control algorithms dev/ath/ath_rate/amrr/amrr.c optional ath_rate_amrr \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_rate/onoe/onoe.c optional ath_rate_onoe \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_rate/sample/sample.c optional ath_rate_sample \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/bce/if_bce.c optional bce dev/bfe/if_bfe.c optional bfe dev/bge/if_bge.c optional bge dev/bktr/bktr_audio.c optional bktr pci dev/bktr/bktr_card.c optional bktr pci dev/bktr/bktr_core.c optional bktr pci dev/bktr/bktr_i2c.c optional bktr pci smbus dev/bktr/bktr_os.c optional bktr pci dev/bktr/bktr_tuner.c optional bktr pci dev/bktr/msp34xx.c optional bktr pci dev/buslogic/bt.c optional bt dev/buslogic/bt_eisa.c optional bt eisa dev/buslogic/bt_isa.c optional bt isa dev/buslogic/bt_mca.c optional bt mca dev/buslogic/bt_pci.c optional bt pci dev/bwi/bwimac.c optional bwi dev/bwi/bwiphy.c optional bwi dev/bwi/bwirf.c optional bwi dev/bwi/if_bwi.c optional bwi dev/bwi/if_bwi_pci.c optional bwi pci dev/bwn/if_bwn.c optional bwn siba_bwn dev/cardbus/cardbus.c optional cardbus dev/cardbus/cardbus_cis.c optional cardbus dev/cardbus/cardbus_device.c optional cardbus dev/cas/if_cas.c optional cas dev/cfi/cfi_core.c optional cfi dev/cfi/cfi_dev.c optional cfi dev/cfi/cfi_disk.c optional cfid dev/ciss/ciss.c optional ciss dev/cm/smc90cx6.c optional cm dev/cmx/cmx.c optional cmx dev/cmx/cmx_pccard.c optional cmx pccard dev/cpufreq/ichss.c optional cpufreq dev/cs/if_cs.c optional cs dev/cs/if_cs_isa.c optional cs isa dev/cs/if_cs_pccard.c optional cs pccard dev/cxgb/cxgb_main.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_offload.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_sge.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_mc5.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_vsc7323.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_vsc8211.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_ael1002.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_aq100x.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_mv88e1xxx.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_xgmac.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_t3_hw.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_tn1010.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/sys/uipc_mvec.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_t3fw.c optional cxgb cxgb_t3fw \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgbe/t4_main.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_sge.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" +dev/cxgbe/t4_l2t.c optional cxgbe pci \ + compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/common/t4_hw.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cy/cy.c optional cy dev/cy/cy_isa.c optional cy isa dev/cy/cy_pci.c optional cy pci dev/dc/if_dc.c optional dc pci dev/dc/dcphy.c optional dc pci dev/dc/pnphy.c optional dc pci dev/dcons/dcons.c optional dcons dev/dcons/dcons_crom.c optional dcons_crom dev/dcons/dcons_os.c optional dcons dev/de/if_de.c optional de pci dev/digi/CX.c optional digi_CX dev/digi/CX_PCI.c optional digi_CX_PCI dev/digi/EPCX.c optional digi_EPCX dev/digi/EPCX_PCI.c optional digi_EPCX_PCI dev/digi/Xe.c optional digi_Xe dev/digi/Xem.c optional digi_Xem dev/digi/Xr.c optional digi_Xr dev/digi/digi.c optional digi dev/digi/digi_isa.c optional digi isa dev/digi/digi_pci.c optional digi pci dev/dpt/dpt_eisa.c optional dpt eisa dev/dpt/dpt_pci.c optional dpt pci dev/dpt/dpt_scsi.c optional dpt dev/drm/ati_pcigart.c optional drm dev/drm/drm_agpsupport.c optional drm dev/drm/drm_auth.c optional drm dev/drm/drm_bufs.c optional drm dev/drm/drm_context.c optional drm dev/drm/drm_dma.c optional drm dev/drm/drm_drawable.c optional drm dev/drm/drm_drv.c optional drm dev/drm/drm_fops.c optional drm dev/drm/drm_ioctl.c optional drm dev/drm/drm_irq.c optional drm dev/drm/drm_lock.c optional drm dev/drm/drm_memory.c optional drm dev/drm/drm_pci.c optional drm dev/drm/drm_scatter.c optional drm dev/drm/drm_sysctl.c optional drm dev/drm/drm_vm.c optional drm dev/drm/i915_dma.c optional i915drm dev/drm/i915_drv.c optional i915drm dev/drm/i915_irq.c optional i915drm dev/drm/i915_mem.c optional i915drm dev/drm/i915_suspend.c optional i915drm dev/drm/mach64_dma.c optional mach64drm dev/drm/mach64_drv.c optional mach64drm dev/drm/mach64_irq.c optional mach64drm dev/drm/mach64_state.c optional mach64drm dev/drm/mga_dma.c optional mgadrm dev/drm/mga_drv.c optional mgadrm dev/drm/mga_irq.c optional mgadrm dev/drm/mga_state.c optional mgadrm \ compile-with "${NORMAL_C} -finline-limit=13500" dev/drm/mga_warp.c optional mgadrm dev/drm/r128_cce.c optional r128drm dev/drm/r128_drv.c optional r128drm dev/drm/r128_irq.c optional r128drm dev/drm/r128_state.c optional r128drm \ compile-with "${NORMAL_C} -finline-limit=13500" dev/drm/r300_cmdbuf.c optional radeondrm dev/drm/r600_blit.c optional radeondrm dev/drm/r600_cp.c optional radeondrm dev/drm/radeon_cp.c optional radeondrm dev/drm/radeon_cs.c optional radeondrm dev/drm/radeon_drv.c optional radeondrm dev/drm/radeon_irq.c optional radeondrm dev/drm/radeon_mem.c optional radeondrm dev/drm/radeon_state.c optional radeondrm dev/drm/savage_bci.c optional savagedrm dev/drm/savage_drv.c optional savagedrm dev/drm/savage_state.c optional savagedrm dev/drm/sis_drv.c optional sisdrm dev/drm/sis_ds.c optional sisdrm dev/drm/sis_mm.c optional sisdrm dev/drm/tdfx_drv.c optional tdfxdrm dev/ed/if_ed.c optional ed dev/ed/if_ed_novell.c optional ed dev/ed/if_ed_rtl80x9.c optional ed dev/ed/if_ed_pccard.c optional ed pccard dev/ed/if_ed_pci.c optional ed pci dev/eisa/eisa_if.m standard dev/eisa/eisaconf.c optional eisa dev/e1000/if_em.c optional em inet \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/if_lem.c optional em inet \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/if_igb.c optional igb inet \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_80003es2lan.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82540.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82541.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82542.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82543.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82571.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82575.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_ich8lan.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_api.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_mac.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_manage.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_nvm.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_phy.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_vf.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_mbx.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_osdep.c optional em | igb \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/et/if_et.c optional et dev/en/if_en_pci.c optional en pci dev/en/midway.c optional en dev/ep/if_ep.c optional ep dev/ep/if_ep_eisa.c optional ep eisa dev/ep/if_ep_isa.c optional ep isa dev/ep/if_ep_mca.c optional ep mca dev/ep/if_ep_pccard.c optional ep pccard dev/esp/ncr53c9x.c optional esp dev/ex/if_ex.c optional ex dev/ex/if_ex_isa.c optional ex isa dev/ex/if_ex_pccard.c optional ex pccard dev/exca/exca.c optional cbb dev/fatm/if_fatm.c optional fatm pci dev/fb/splash.c optional splash dev/fe/if_fe.c optional fe dev/fe/if_fe_pccard.c optional fe pccard dev/firewire/firewire.c optional firewire dev/firewire/fwcrom.c optional firewire dev/firewire/fwdev.c optional firewire dev/firewire/fwdma.c optional firewire dev/firewire/fwmem.c optional firewire dev/firewire/fwohci.c optional firewire dev/firewire/fwohci_pci.c optional firewire pci dev/firewire/if_fwe.c optional fwe dev/firewire/if_fwip.c optional fwip dev/firewire/sbp.c optional sbp dev/firewire/sbp_targ.c optional sbp_targ dev/flash/at45d.c optional at45d dev/fxp/if_fxp.c optional fxp inet dev/gem/if_gem.c optional gem dev/gem/if_gem_pci.c optional gem pci dev/gem/if_gem_sbus.c optional gem sbus dev/hatm/if_hatm.c optional hatm pci dev/hatm/if_hatm_intr.c optional hatm pci dev/hatm/if_hatm_ioctl.c optional hatm pci dev/hatm/if_hatm_rx.c optional hatm pci dev/hatm/if_hatm_tx.c optional hatm pci dev/hifn/hifn7751.c optional hifn dev/hme/if_hme.c optional hme dev/hme/if_hme_pci.c optional hme pci dev/hme/if_hme_sbus.c optional hme sbus dev/hptiop/hptiop.c optional hptiop scbus dev/hwpmc/hwpmc_logging.c optional hwpmc dev/hwpmc/hwpmc_mod.c optional hwpmc dev/ichsmb/ichsmb.c optional ichsmb dev/ichsmb/ichsmb_pci.c optional ichsmb pci dev/ida/ida.c optional ida dev/ida/ida_disk.c optional ida dev/ida/ida_eisa.c optional ida eisa dev/ida/ida_pci.c optional ida pci dev/ie/if_ie.c optional ie isa nowerror dev/ie/if_ie_isa.c optional ie isa dev/ieee488/ibfoo.c optional pcii | tnt4882 dev/ieee488/pcii.c optional pcii dev/ieee488/tnt4882.c optional tnt4882 dev/ieee488/upd7210.c optional pcii | tnt4882 dev/iicbus/ad7418.c optional ad7418 dev/iicbus/ds133x.c optional ds133x dev/iicbus/ds1672.c optional ds1672 dev/iicbus/icee.c optional icee dev/iicbus/if_ic.c optional ic dev/iicbus/iic.c optional iic dev/iicbus/iicbb.c optional iicbb dev/iicbus/iicbb_if.m optional iicbb dev/iicbus/iicbus.c optional iicbus dev/iicbus/iicbus_if.m optional iicbus dev/iicbus/iiconf.c optional iicbus dev/iicbus/iicsmb.c optional iicsmb \ dependency "iicbus_if.h" dev/iir/iir.c optional iir dev/iir/iir_ctrl.c optional iir dev/iir/iir_pci.c optional iir pci dev/ips/ips.c optional ips dev/ips/ips_commands.c optional ips dev/ips/ips_disk.c optional ips dev/ips/ips_ioctl.c optional ips dev/ips/ips_pci.c optional ips pci dev/ipw/if_ipw.c optional ipw ipwbssfw.c optional ipwbssfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_bss.fw:ipw_bss:130 -lintel_ipw -mipw_bss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwbssfw.c" ipw_bss.fwo optional ipwbssfw | ipwfw \ dependency "ipw_bss.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} ipw_bss.fw" \ no-implicit-rule \ clean "ipw_bss.fwo" ipw_bss.fw optional ipwbssfw | ipwfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/ipw/ipw2100-1.3.fw.uu" \ no-obj no-implicit-rule \ clean "ipw_bss.fw" ipwibssfw.c optional ipwibssfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_ibss.fw:ipw_ibss:130 -lintel_ipw -mipw_ibss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwibssfw.c" ipw_ibss.fwo optional ipwibssfw | ipwfw \ dependency "ipw_ibss.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} ipw_ibss.fw" \ no-implicit-rule \ clean "ipw_ibss.fwo" ipw_ibss.fw optional ipwibssfw | ipwfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/ipw/ipw2100-1.3-i.fw.uu" \ no-obj no-implicit-rule \ clean "ipw_ibss.fw" ipwmonitorfw.c optional ipwmonitorfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_monitor.fw:ipw_monitor:130 -lintel_ipw -mipw_monitor -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwmonitorfw.c" ipw_monitor.fwo optional ipwmonitorfw | ipwfw \ dependency "ipw_monitor.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} ipw_monitor.fw" \ no-implicit-rule \ clean "ipw_monitor.fwo" ipw_monitor.fw optional ipwmonitorfw | ipwfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/ipw/ipw2100-1.3-p.fw.uu" \ no-obj no-implicit-rule \ clean "ipw_monitor.fw" dev/iscsi/initiator/iscsi.c optional iscsi_initiator scbus dev/iscsi/initiator/iscsi_subr.c optional iscsi_initiator scbus dev/iscsi/initiator/isc_cam.c optional iscsi_initiator scbus dev/iscsi/initiator/isc_soc.c optional iscsi_initiator scbus dev/iscsi/initiator/isc_sm.c optional iscsi_initiator scbus dev/iscsi/initiator/isc_subr.c optional iscsi_initiator scbus dev/isp/isp.c optional isp dev/isp/isp_freebsd.c optional isp dev/isp/isp_library.c optional isp dev/isp/isp_pci.c optional isp pci dev/isp/isp_sbus.c optional isp sbus dev/isp/isp_target.c optional isp dev/ispfw/ispfw.c optional ispfw dev/iwi/if_iwi.c optional iwi iwibssfw.c optional iwibssfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_bss.fw:iwi_bss:300 -lintel_iwi -miwi_bss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwibssfw.c" iwi_bss.fwo optional iwibssfw | iwifw \ dependency "iwi_bss.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwi_bss.fw" \ no-implicit-rule \ clean "iwi_bss.fwo" iwi_bss.fw optional iwibssfw | iwifw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwi/ipw2200-bss.fw.uu" \ no-obj no-implicit-rule \ clean "iwi_bss.fw" iwiibssfw.c optional iwiibssfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_ibss.fw:iwi_ibss:300 -lintel_iwi -miwi_ibss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwiibssfw.c" iwi_ibss.fwo optional iwiibssfw | iwifw \ dependency "iwi_ibss.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwi_ibss.fw" \ no-implicit-rule \ clean "iwi_ibss.fwo" iwi_ibss.fw optional iwiibssfw | iwifw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwi/ipw2200-ibss.fw.uu" \ no-obj no-implicit-rule \ clean "iwi_ibss.fw" iwimonitorfw.c optional iwimonitorfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_monitor.fw:iwi_monitor:300 -lintel_iwi -miwi_monitor -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwimonitorfw.c" iwi_monitor.fwo optional iwimonitorfw | iwifw \ dependency "iwi_monitor.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwi_monitor.fw" \ no-implicit-rule \ clean "iwi_monitor.fwo" iwi_monitor.fw optional iwimonitorfw | iwifw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwi/ipw2200-sniffer.fw.uu" \ no-obj no-implicit-rule \ clean "iwi_monitor.fw" dev/iwn/if_iwn.c optional iwn iwn1000fw.c optional iwn1000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn1000.fw:iwn1000fw -miwn1000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn1000fw.c" iwn1000fw.fwo optional iwn1000fw | iwnfw \ dependency "iwn1000.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwn1000.fw" \ no-implicit-rule \ clean "iwn1000fw.fwo" iwn1000.fw optional iwn1000fw | iwnfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwn/iwlwifi-1000-128.50.3.1.fw.uu" \ no-obj no-implicit-rule \ clean "iwn1000.fw" iwn4965fw.c optional iwn4965fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn4965.fw:iwn4965fw -miwn4965fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn4965fw.c" iwn4965fw.fwo optional iwn4965fw | iwnfw \ dependency "iwn4965.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwn4965.fw" \ no-implicit-rule \ clean "iwn4965fw.fwo" iwn4965.fw optional iwn4965fw | iwnfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwn/iwlwifi-4965-228.61.2.24.fw.uu" \ no-obj no-implicit-rule \ clean "iwn4965.fw" iwn5000fw.c optional iwn5000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn5000.fw:iwn5000fw -miwn5000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn5000fw.c" iwn5000fw.fwo optional iwn5000fw | iwnfw \ dependency "iwn5000.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwn5000.fw" \ no-implicit-rule \ clean "iwn5000fw.fwo" iwn5000.fw optional iwn5000fw | iwnfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwn/iwlwifi-5000-8.24.2.12.fw.uu" \ no-obj no-implicit-rule \ clean "iwn5000.fw" iwn5150fw.c optional iwn5150fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn5150.fw:iwn5150fw -miwn5150fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn5150fw.c" iwn5150fw.fwo optional iwn5150fw | iwnfw \ dependency "iwn5150.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwn5150.fw" \ no-implicit-rule \ clean "iwn5150fw.fwo" iwn5150.fw optional iwn5150fw | iwnfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwn/iwlwifi-5150-8.24.2.2.fw.uu" \ no-obj no-implicit-rule \ clean "iwn5150.fw" iwn6000fw.c optional iwn6000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000.fw:iwn6000fw -miwn6000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000fw.c" iwn6000fw.fwo optional iwn6000fw | iwnfw \ dependency "iwn6000.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwn6000.fw" \ no-implicit-rule \ clean "iwn6000fw.fwo" iwn6000.fw optional iwn6000fw | iwnfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwn/iwlwifi-6000-9.221.4.1.fw.uu" \ no-obj no-implicit-rule \ clean "iwn6000.fw" iwn6050fw.c optional iwn6050fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6050.fw:iwn6050fw -miwn6050fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6050fw.c" iwn6050fw.fwo optional iwn6050fw | iwnfw \ dependency "iwn6050.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} iwn6050.fw" \ no-implicit-rule \ clean "iwn6050fw.fwo" iwn6050.fw optional iwn6050fw | iwnfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/iwn/iwlwifi-6050-9.201.4.1.fw.uu" \ no-obj no-implicit-rule \ clean "iwn6050.fw" dev/ixgb/if_ixgb.c optional ixgb dev/ixgb/ixgb_ee.c optional ixgb dev/ixgb/ixgb_hw.c optional ixgb dev/ixgbe/ixgbe.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixv.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_phy.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_api.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_common.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_mbx.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_vf.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_82598.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_82599.c optional ixgbe inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/jme/if_jme.c optional jme pci inet dev/joy/joy.c optional joy dev/joy/joy_isa.c optional joy isa dev/joy/joy_pccard.c optional joy pccard dev/kbdmux/kbdmux.c optional kbdmux dev/ksyms/ksyms.c optional ksyms dev/le/am7990.c optional le dev/le/am79900.c optional le dev/le/if_le_pci.c optional le pci dev/le/lance.c optional le dev/led/led.c standard dev/lge/if_lge.c optional lge dev/lmc/if_lmc.c optional lmc dev/malo/if_malo.c optional malo dev/malo/if_malohal.c optional malo dev/malo/if_malo_pci.c optional malo pci dev/mc146818/mc146818.c optional mc146818 dev/mca/mca_bus.c optional mca dev/mcd/mcd.c optional mcd isa nowerror dev/mcd/mcd_isa.c optional mcd isa nowerror dev/md/md.c optional md dev/mem/memdev.c optional mem dev/mem/memutil.c optional mem dev/mfi/mfi.c optional mfi dev/mfi/mfi_debug.c optional mfi dev/mfi/mfi_pci.c optional mfi pci dev/mfi/mfi_disk.c optional mfi dev/mfi/mfi_linux.c optional mfi compat_linux dev/mfi/mfi_cam.c optional mfip scbus dev/mii/acphy.c optional miibus | acphy dev/mii/amphy.c optional miibus | amphy dev/mii/atphy.c optional miibus | atphy dev/mii/axphy.c optional miibus | axphy dev/mii/bmtphy.c optional miibus | bmtphy dev/mii/brgphy.c optional miibus | brgphy dev/mii/ciphy.c optional miibus | ciphy dev/mii/e1000phy.c optional miibus | e1000phy # XXX only xl cards? dev/mii/exphy.c optional miibus | exphy dev/mii/gentbi.c optional miibus | gentbi dev/mii/icsphy.c optional miibus | icsphy # XXX only fxp cards? dev/mii/inphy.c optional miibus | inphy dev/mii/ip1000phy.c optional miibus | ip1000phy dev/mii/jmphy.c optional miibus | jmphy dev/mii/lxtphy.c optional miibus | lxtphy dev/mii/mii.c optional miibus | mii dev/mii/mii_physubr.c optional miibus | mii dev/mii/miibus_if.m optional miibus | mii dev/mii/mlphy.c optional miibus | mlphy dev/mii/nsgphy.c optional miibus | nsgphy dev/mii/nsphy.c optional miibus | nsphy dev/mii/nsphyter.c optional miibus | nsphyter dev/mii/pnaphy.c optional miibus | pnaphy dev/mii/qsphy.c optional miibus | qsphy dev/mii/rdcphy.c optional miibus | rdcphy dev/mii/rgephy.c optional miibus | rgephy dev/mii/rlphy.c optional miibus | rlphy dev/mii/rlswitch.c optional rlswitch # XXX rue only? dev/mii/ruephy.c optional miibus | ruephy dev/mii/smcphy.c optional miibus | smcphy dev/mii/tdkphy.c optional miibus | tdkphy dev/mii/tlphy.c optional miibus | tlphy dev/mii/truephy.c optional miibus | truephy dev/mii/ukphy.c optional miibus | mii dev/mii/ukphy_subr.c optional miibus | mii dev/mii/xmphy.c optional miibus | xmphy dev/mk48txx/mk48txx.c optional mk48txx dev/mlx/mlx.c optional mlx dev/mlx/mlx_disk.c optional mlx dev/mlx/mlx_pci.c optional mlx pci dev/mly/mly.c optional mly dev/mmc/mmc.c optional mmc dev/mmc/mmcbr_if.m standard dev/mmc/mmcbus_if.m standard dev/mmc/mmcsd.c optional mmcsd dev/mn/if_mn.c optional mn pci dev/mps/mps.c optional mps dev/mps/mps_pci.c optional mps pci dev/mps/mps_sas.c optional mps dev/mps/mps_table.c optional mps dev/mps/mps_user.c optional mps dev/mpt/mpt.c optional mpt dev/mpt/mpt_cam.c optional mpt dev/mpt/mpt_debug.c optional mpt dev/mpt/mpt_pci.c optional mpt pci dev/mpt/mpt_raid.c optional mpt dev/mpt/mpt_user.c optional mpt dev/msk/if_msk.c optional msk inet dev/mvs/mvs.c optional mvs dev/mvs/mvs_if.m optional mvs dev/mvs/mvs_pci.c optional mvs pci dev/mwl/if_mwl.c optional mwl dev/mwl/if_mwl_pci.c optional mwl pci dev/mwl/mwlhal.c optional mwl mwlfw.c optional mwlfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk mw88W8363.fw:mw88W8363fw mwlboot.fw:mwlboot -mmwl -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "mwlfw.c" mw88W8363.fwo optional mwlfw \ dependency "mw88W8363.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} mw88W8363.fw" \ no-implicit-rule \ clean "mw88W8363.fwo" mw88W8363.fw optional mwlfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/mwl/mw88W8363.fw.uu" \ no-obj no-implicit-rule \ clean "mw88W8363.fw" mwlboot.fwo optional mwlfw \ dependency "mwlboot.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} mwlboot.fw" \ no-implicit-rule \ clean "mwlboot.fwo" mwlboot.fw optional mwlfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/mwl/mwlboot.fw.uu" \ no-obj no-implicit-rule \ clean "mwlboot.fw" dev/mxge/if_mxge.c optional mxge pci dev/mxge/mxge_lro.c optional mxge pci dev/mxge/mxge_eth_z8e.c optional mxge pci dev/mxge/mxge_ethp_z8e.c optional mxge pci dev/mxge/mxge_rss_eth_z8e.c optional mxge pci dev/mxge/mxge_rss_ethp_z8e.c optional mxge pci dev/my/if_my.c optional my dev/ncv/ncr53c500.c optional ncv dev/ncv/ncr53c500_pccard.c optional ncv pccard dev/nge/if_nge.c optional nge dev/nxge/if_nxge.c optional nxge dev/nxge/xgehal/xgehal-device.c optional nxge dev/nxge/xgehal/xgehal-mm.c optional nxge dev/nxge/xgehal/xge-queue.c optional nxge dev/nxge/xgehal/xgehal-driver.c optional nxge dev/nxge/xgehal/xgehal-ring.c optional nxge dev/nxge/xgehal/xgehal-channel.c optional nxge dev/nxge/xgehal/xgehal-fifo.c optional nxge dev/nxge/xgehal/xgehal-stats.c optional nxge dev/nxge/xgehal/xgehal-config.c optional nxge dev/nxge/xgehal/xgehal-mgmt.c optional nxge dev/nmdm/nmdm.c optional nmdm dev/nsp/nsp.c optional nsp dev/nsp/nsp_pccard.c optional nsp pccard dev/null/null.c standard dev/patm/if_patm.c optional patm pci dev/patm/if_patm_attach.c optional patm pci dev/patm/if_patm_intr.c optional patm pci dev/patm/if_patm_ioctl.c optional patm pci dev/patm/if_patm_rtables.c optional patm pci dev/patm/if_patm_rx.c optional patm pci dev/patm/if_patm_tx.c optional patm pci dev/pbio/pbio.c optional pbio isa dev/pccard/card_if.m standard dev/pccard/pccard.c optional pccard dev/pccard/pccard_cis.c optional pccard dev/pccard/pccard_cis_quirks.c optional pccard dev/pccard/pccard_device.c optional pccard dev/pccard/power_if.m standard dev/pccbb/pccbb.c optional cbb dev/pccbb/pccbb_isa.c optional cbb isa dev/pccbb/pccbb_pci.c optional cbb pci dev/pcf/pcf.c optional pcf dev/pci/eisa_pci.c optional pci eisa dev/pci/fixup_pci.c optional pci dev/pci/hostb_pci.c optional pci dev/pci/ignore_pci.c optional pci dev/pci/isa_pci.c optional pci isa dev/pci/pci.c optional pci dev/pci/pci_if.m standard dev/pci/pci_pci.c optional pci dev/pci/pci_user.c optional pci dev/pci/pcib_if.m standard dev/pci/vga_pci.c optional pci dev/pcn/if_pcn.c optional pcn pci dev/pdq/if_fea.c optional fea eisa dev/pdq/if_fpa.c optional fpa pci dev/pdq/pdq.c optional nowerror fea eisa | fpa pci dev/pdq/pdq_ifsubr.c optional nowerror fea eisa | fpa pci dev/ppbus/if_plip.c optional plip dev/ppbus/immio.c optional vpo dev/ppbus/lpbb.c optional lpbb dev/ppbus/lpt.c optional lpt dev/ppbus/pcfclock.c optional pcfclock dev/ppbus/ppb_1284.c optional ppbus dev/ppbus/ppb_base.c optional ppbus dev/ppbus/ppb_msq.c optional ppbus dev/ppbus/ppbconf.c optional ppbus dev/ppbus/ppbus_if.m optional ppbus dev/ppbus/ppi.c optional ppi dev/ppbus/pps.c optional pps dev/ppbus/vpo.c optional vpo dev/ppbus/vpoio.c optional vpo dev/ppc/ppc.c optional ppc dev/ppc/ppc_acpi.c optional ppc acpi dev/ppc/ppc_isa.c optional ppc isa dev/ppc/ppc_pci.c optional ppc pci dev/ppc/ppc_puc.c optional ppc puc dev/pst/pst-iop.c optional pst dev/pst/pst-pci.c optional pst pci dev/pst/pst-raid.c optional pst dev/puc/puc.c optional puc dev/puc/puc_cfg.c optional puc dev/puc/puc_pccard.c optional puc pccard dev/puc/puc_pci.c optional puc pci dev/puc/pucdata.c optional puc pci dev/quicc/quicc_core.c optional quicc dev/ral/rt2560.c optional ral dev/ral/rt2661.c optional ral dev/ral/if_ral_pci.c optional ral pci rt2561fw.c optional rt2561fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2561.fw:rt2561fw -mrt2561 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2561fw.c" rt2561fw.fwo optional rt2561fw | ralfw \ dependency "rt2561.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} rt2561.fw" \ no-implicit-rule \ clean "rt2561fw.fwo" rt2561.fw optional rt2561fw | ralfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/ral/rt2561.fw.uu" \ no-obj no-implicit-rule \ clean "rt2561.fw" rt2561sfw.c optional rt2561sfw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2561s.fw:rt2561sfw -mrt2561s -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2561sfw.c" rt2561sfw.fwo optional rt2561sfw | ralfw \ dependency "rt2561s.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} rt2561s.fw" \ no-implicit-rule \ clean "rt2561sfw.fwo" rt2561s.fw optional rt2561sfw | ralfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/ral/rt2561s.fw.uu" \ no-obj no-implicit-rule \ clean "rt2561s.fw" rt2661fw.c optional rt2661fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2661.fw:rt2661fw -mrt2661 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2661fw.c" rt2661fw.fwo optional rt2661fw | ralfw \ dependency "rt2661.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} rt2661.fw" \ no-implicit-rule \ clean "rt2661fw.fwo" rt2661.fw optional rt2661fw | ralfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/ral/rt2661.fw.uu" \ no-obj no-implicit-rule \ clean "rt2661.fw" rt2860fw.c optional rt2860fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2860.fw:rt2860fw -mrt2860 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2860fw.c" rt2860fw.fwo optional rt2860fw | ralfw \ dependency "rt2860.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} rt2860.fw" \ no-implicit-rule \ clean "rt2860fw.fwo" rt2860.fw optional rt2860fw | ralfw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/ral/rt2860.fw.uu" \ no-obj no-implicit-rule \ clean "rt2860.fw" dev/random/harvest.c standard dev/random/hash.c optional random dev/random/probe.c optional random dev/random/randomdev.c optional random dev/random/randomdev_soft.c optional random dev/random/yarrow.c optional random dev/rc/rc.c optional rc dev/re/if_re.c optional re dev/rndtest/rndtest.c optional rndtest dev/rp/rp.c optional rp dev/rp/rp_isa.c optional rp isa dev/rp/rp_pci.c optional rp pci dev/safe/safe.c optional safe dev/scc/scc_if.m optional scc dev/scc/scc_bfe_ebus.c optional scc ebus dev/scc/scc_bfe_quicc.c optional scc quicc dev/scc/scc_bfe_sbus.c optional scc fhc | scc sbus dev/scc/scc_core.c optional scc dev/scc/scc_dev_quicc.c optional scc quicc dev/scc/scc_dev_sab82532.c optional scc dev/scc/scc_dev_z8530.c optional scc dev/scd/scd.c optional scd isa dev/scd/scd_isa.c optional scd isa dev/sdhci/sdhci.c optional sdhci pci dev/sf/if_sf.c optional sf pci dev/sge/if_sge.c optional sge pci dev/si/si.c optional si dev/si/si2_z280.c optional si dev/si/si3_t225.c optional si dev/si/si_eisa.c optional si eisa dev/si/si_isa.c optional si isa dev/si/si_pci.c optional si pci dev/siba/siba_bwn.c optional siba_bwn pci dev/siba/siba_core.c optional siba_bwn pci dev/siis/siis.c optional siis pci dev/sis/if_sis.c optional sis pci dev/sk/if_sk.c optional sk pci inet dev/smbus/smb.c optional smb dev/smbus/smbconf.c optional smbus dev/smbus/smbus.c optional smbus dev/smbus/smbus_if.m optional smbus dev/smc/if_smc.c optional smc dev/sn/if_sn.c optional sn dev/sn/if_sn_isa.c optional sn isa dev/sn/if_sn_pccard.c optional sn pccard dev/snp/snp.c optional snp dev/sound/clone.c optional sound dev/sound/unit.c optional sound dev/sound/isa/ad1816.c optional snd_ad1816 isa dev/sound/isa/ess.c optional snd_ess isa dev/sound/isa/gusc.c optional snd_gusc isa dev/sound/isa/mss.c optional snd_mss isa dev/sound/isa/sb16.c optional snd_sb16 isa dev/sound/isa/sb8.c optional snd_sb8 isa dev/sound/isa/sbc.c optional snd_sbc isa dev/sound/isa/sndbuf_dma.c optional sound isa dev/sound/pci/als4000.c optional snd_als4000 pci dev/sound/pci/atiixp.c optional snd_atiixp pci dev/sound/pci/cmi.c optional snd_cmi pci dev/sound/pci/cs4281.c optional snd_cs4281 pci dev/sound/pci/csa.c optional snd_csa pci \ warning "kernel contains GPL contaminated csaimg.h header" dev/sound/pci/csapcm.c optional snd_csa pci dev/sound/pci/ds1.c optional snd_ds1 pci dev/sound/pci/emu10k1.c optional snd_emu10k1 pci \ dependency "emu10k1-alsa%diked.h" \ warning "kernel contains GPL contaminated emu10k1 headers" dev/sound/pci/emu10kx.c optional snd_emu10kx pci \ dependency "emu10k1-alsa%diked.h" \ dependency "p16v-alsa%diked.h" \ dependency "p17v-alsa%diked.h" \ warning "kernel contains GPL contaminated emu10kx headers" dev/sound/pci/emu10kx-pcm.c optional snd_emu10kx pci \ dependency "emu10k1-alsa%diked.h" \ dependency "p16v-alsa%diked.h" \ dependency "p17v-alsa%diked.h" \ warning "kernel contains GPL contaminated emu10kx headers" dev/sound/pci/emu10kx-midi.c optional snd_emu10kx pci \ dependency "emu10k1-alsa%diked.h" \ warning "kernel contains GPL contaminated emu10kx headers" dev/sound/pci/envy24.c optional snd_envy24 pci dev/sound/pci/envy24ht.c optional snd_envy24ht pci dev/sound/pci/es137x.c optional snd_es137x pci dev/sound/pci/fm801.c optional snd_fm801 pci dev/sound/pci/ich.c optional snd_ich pci dev/sound/pci/maestro.c optional snd_maestro pci dev/sound/pci/maestro3.c optional snd_maestro3 pci \ warning "kernel contains GPL contaminated maestro3 headers" dev/sound/pci/neomagic.c optional snd_neomagic pci dev/sound/pci/solo.c optional snd_solo pci dev/sound/pci/spicds.c optional snd_spicds pci dev/sound/pci/t4dwave.c optional snd_t4dwave pci dev/sound/pci/via8233.c optional snd_via8233 pci dev/sound/pci/via82c686.c optional snd_via82c686 pci dev/sound/pci/vibes.c optional snd_vibes pci dev/sound/pci/hda/hdac.c optional snd_hda pci dev/sound/pcm/ac97.c optional sound dev/sound/pcm/ac97_if.m optional sound dev/sound/pcm/ac97_patch.c optional sound dev/sound/pcm/buffer.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/channel.c optional sound dev/sound/pcm/channel_if.m optional sound dev/sound/pcm/dsp.c optional sound dev/sound/pcm/feeder.c optional sound dev/sound/pcm/feeder_chain.c optional sound dev/sound/pcm/feeder_eq.c optional sound \ dependency "feeder_eq_gen.h" \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_if.m optional sound dev/sound/pcm/feeder_format.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_matrix.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_mixer.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_rate.c optional sound \ dependency "feeder_rate_gen.h" \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_volume.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/mixer.c optional sound dev/sound/pcm/mixer_if.m optional sound dev/sound/pcm/sndstat.c optional sound dev/sound/pcm/sound.c optional sound dev/sound/pcm/vchan.c optional sound dev/sound/usb/uaudio.c optional snd_uaudio usb dev/sound/usb/uaudio_pcm.c optional snd_uaudio usb dev/sound/midi/midi.c optional sound dev/sound/midi/mpu401.c optional sound dev/sound/midi/mpu_if.m optional sound dev/sound/midi/mpufoi_if.m optional sound dev/sound/midi/sequencer.c optional sound dev/sound/midi/synth_if.m optional sound dev/spibus/spibus.c optional spibus \ dependency "spibus_if.h" dev/spibus/spibus_if.m optional spibus dev/ste/if_ste.c optional ste pci dev/stg/tmc18c30.c optional stg dev/stg/tmc18c30_isa.c optional stg isa dev/stg/tmc18c30_pccard.c optional stg pccard dev/stg/tmc18c30_pci.c optional stg pci dev/stg/tmc18c30_subr.c optional stg dev/stge/if_stge.c optional stge dev/streams/streams.c optional streams dev/sym/sym_hipd.c optional sym \ dependency "$S/dev/sym/sym_{conf,defs}.h" dev/syscons/blank/blank_saver.c optional blank_saver dev/syscons/daemon/daemon_saver.c optional daemon_saver dev/syscons/dragon/dragon_saver.c optional dragon_saver dev/syscons/fade/fade_saver.c optional fade_saver dev/syscons/fire/fire_saver.c optional fire_saver dev/syscons/green/green_saver.c optional green_saver dev/syscons/logo/logo.c optional logo_saver dev/syscons/logo/logo_saver.c optional logo_saver dev/syscons/rain/rain_saver.c optional rain_saver dev/syscons/schistory.c optional sc dev/syscons/scmouse.c optional sc dev/syscons/scterm.c optional sc dev/syscons/scvidctl.c optional sc dev/syscons/snake/snake_saver.c optional snake_saver dev/syscons/star/star_saver.c optional star_saver dev/syscons/syscons.c optional sc dev/syscons/sysmouse.c optional sc dev/syscons/warp/warp_saver.c optional warp_saver dev/tdfx/tdfx_linux.c optional tdfx_linux tdfx compat_linux dev/tdfx/tdfx_pci.c optional tdfx pci dev/ti/if_ti.c optional ti pci dev/tl/if_tl.c optional tl pci dev/trm/trm.c optional trm dev/twa/tw_cl_init.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_intr.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_io.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_misc.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_osl_cam.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_osl_freebsd.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twe/twe.c optional twe dev/twe/twe_freebsd.c optional twe dev/tx/if_tx.c optional tx dev/txp/if_txp.c optional txp inet dev/uart/uart_bus_acpi.c optional uart acpi #dev/uart/uart_bus_cbus.c optional uart cbus dev/uart/uart_bus_ebus.c optional uart ebus dev/uart/uart_bus_isa.c optional uart isa dev/uart/uart_bus_pccard.c optional uart pccard dev/uart/uart_bus_pci.c optional uart pci dev/uart/uart_bus_puc.c optional uart puc dev/uart/uart_bus_scc.c optional uart scc dev/uart/uart_core.c optional uart dev/uart/uart_dbg.c optional uart gdb dev/uart/uart_dev_ns8250.c optional uart uart_ns8250 dev/uart/uart_dev_quicc.c optional uart quicc dev/uart/uart_dev_sab82532.c optional uart uart_sab82532 dev/uart/uart_dev_sab82532.c optional uart scc dev/uart/uart_dev_z8530.c optional uart uart_z8530 dev/uart/uart_dev_z8530.c optional uart scc dev/uart/uart_if.m optional uart dev/uart/uart_subr.c optional uart dev/uart/uart_tty.c optional uart dev/ubsec/ubsec.c optional ubsec # # USB controller drivers # dev/usb/controller/at91dci.c optional at91dci dev/usb/controller/at91dci_atmelarm.c optional at91dci at91rm9200 dev/usb/controller/musb_otg.c optional musb dev/usb/controller/musb_otg_atmelarm.c optional musb at91rm9200 dev/usb/controller/ehci.c optional ehci dev/usb/controller/ehci_pci.c optional ehci pci dev/usb/controller/ohci.c optional ohci dev/usb/controller/ohci_atmelarm.c optional ohci at91rm9200 dev/usb/controller/ohci_pci.c optional ohci pci dev/usb/controller/uhci.c optional uhci dev/usb/controller/uhci_pci.c optional uhci pci dev/usb/controller/xhci.c optional xhci dev/usb/controller/xhci_pci.c optional xhci pci dev/usb/controller/uss820dci.c optional uss820dci dev/usb/controller/uss820dci_atmelarm.c optional uss820dci at91rm9200 dev/usb/controller/usb_controller.c optional usb # # USB storage drivers # dev/usb/storage/umass.c optional umass dev/usb/storage/urio.c optional urio dev/usb/storage/ustorage_fs.c optional usfs # # USB core # dev/usb/usb_busdma.c optional usb dev/usb/usb_compat_linux.c optional usb dev/usb/usb_core.c optional usb dev/usb/usb_debug.c optional usb dev/usb/usb_dev.c optional usb dev/usb/usb_device.c optional usb dev/usb/usb_dynamic.c optional usb dev/usb/usb_error.c optional usb dev/usb/usb_generic.c optional usb dev/usb/usb_handle_request.c optional usb dev/usb/usb_hid.c optional usb dev/usb/usb_hub.c optional usb dev/usb/usb_if.m optional usb dev/usb/usb_lookup.c optional usb dev/usb/usb_mbuf.c optional usb dev/usb/usb_msctest.c optional usb dev/usb/usb_parse.c optional usb dev/usb/usb_pf.c optional usb dev/usb/usb_process.c optional usb dev/usb/usb_request.c optional usb dev/usb/usb_transfer.c optional usb dev/usb/usb_util.c optional usb # # USB network drivers # dev/usb/net/if_aue.c optional aue dev/usb/net/if_axe.c optional axe dev/usb/net/if_cdce.c optional cdce dev/usb/net/if_cue.c optional cue dev/usb/net/if_ipheth.c optional ipheth dev/usb/net/if_kue.c optional kue dev/usb/net/if_rue.c optional rue dev/usb/net/if_udav.c optional udav dev/usb/net/usb_ethernet.c optional aue | axe | cdce | cue | kue | rue | \ udav dev/usb/net/uhso.c optional uhso # # USB WLAN drivers # dev/usb/wlan/if_rum.c optional rum dev/usb/wlan/if_run.c optional run dev/usb/wlan/if_uath.c optional uath dev/usb/wlan/if_upgt.c optional upgt dev/usb/wlan/if_ural.c optional ural dev/usb/wlan/if_urtw.c optional urtw dev/usb/wlan/if_zyd.c optional zyd # # USB serial and parallel port drivers # dev/usb/serial/u3g.c optional u3g dev/usb/serial/uark.c optional uark dev/usb/serial/ubsa.c optional ubsa dev/usb/serial/ubser.c optional ubser dev/usb/serial/uchcom.c optional uchcom dev/usb/serial/ucycom.c optional ucycom dev/usb/serial/ufoma.c optional ufoma dev/usb/serial/uftdi.c optional uftdi dev/usb/serial/ugensa.c optional ugensa dev/usb/serial/uipaq.c optional uipaq dev/usb/serial/ulpt.c optional ulpt dev/usb/serial/umcs.c optional umcs dev/usb/serial/umct.c optional umct dev/usb/serial/umodem.c optional umodem dev/usb/serial/umoscom.c optional umoscom dev/usb/serial/uplcom.c optional uplcom dev/usb/serial/uslcom.c optional uslcom dev/usb/serial/uvisor.c optional uvisor dev/usb/serial/uvscom.c optional uvscom dev/usb/serial/usb_serial.c optional ucom | u3g | uark | ubsa | ubser | \ uchcom | ucycom | ufoma | uftdi | \ ugensa | uipaq | umcs | umct | \ umodem | umoscom | uplcom | uslcom | \ uvisor | uvscom # # USB misc drivers # dev/usb/misc/ufm.c optional ufm dev/usb/misc/udbp.c optional udbp # # USB input drivers # dev/usb/input/atp.c optional atp dev/usb/input/uep.c optional uep dev/usb/input/uhid.c optional uhid dev/usb/input/ukbd.c optional ukbd dev/usb/input/ums.c optional ums # # USB quirks # dev/usb/quirk/usb_quirk.c optional usb # # USB templates # dev/usb/template/usb_template.c optional usb_template dev/usb/template/usb_template_cdce.c optional usb_template dev/usb/template/usb_template_msc.c optional usb_template dev/usb/template/usb_template_mtp.c optional usb_template # # USB END # dev/utopia/idtphy.c optional utopia dev/utopia/suni.c optional utopia dev/utopia/utopia.c optional utopia dev/vge/if_vge.c optional vge dev/vkbd/vkbd.c optional vkbd dev/vr/if_vr.c optional vr pci dev/vte/if_vte.c optional vte pci dev/vx/if_vx.c optional vx dev/vx/if_vx_eisa.c optional vx eisa dev/vx/if_vx_pci.c optional vx pci dev/watchdog/watchdog.c standard dev/wb/if_wb.c optional wb pci dev/wds/wd7000.c optional wds isa dev/wi/if_wi.c optional wi dev/wi/if_wi_pccard.c optional wi pccard dev/wi/if_wi_pci.c optional wi pci dev/wl/if_wl.c optional wl isa wpifw.c optional wpifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk wpi.fw:wpifw:2144 -mwpi -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "wpifw.c" wpifw.fwo optional wpifw \ dependency "wpi.fw" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} wpi.fw" \ no-implicit-rule \ clean "wpifw.fwo" wpi.fw optional wpifw \ dependency ".PHONY" \ compile-with "uudecode -o ${.TARGET} $S/contrib/dev/wpi/iwlwifi-3945-2.14.4.fw.uu" \ no-obj no-implicit-rule \ clean "wpi.fw" dev/xe/if_xe.c optional xe dev/xe/if_xe_pccard.c optional xe pccard dev/xl/if_xl.c optional xl pci fs/coda/coda_fbsd.c optional vcoda fs/coda/coda_psdev.c optional vcoda fs/coda/coda_subr.c optional vcoda fs/coda/coda_venus.c optional vcoda fs/coda/coda_vfsops.c optional vcoda fs/coda/coda_vnops.c optional vcoda fs/deadfs/dead_vnops.c standard fs/devfs/devfs_devs.c standard fs/devfs/devfs_rule.c standard fs/devfs/devfs_vfsops.c standard fs/devfs/devfs_vnops.c standard fs/fdescfs/fdesc_vfsops.c optional fdescfs fs/fdescfs/fdesc_vnops.c optional fdescfs fs/fifofs/fifo_vnops.c standard fs/hpfs/hpfs_alsubr.c optional hpfs fs/hpfs/hpfs_lookup.c optional hpfs fs/hpfs/hpfs_subr.c optional hpfs fs/hpfs/hpfs_vfsops.c optional hpfs fs/hpfs/hpfs_vnops.c optional hpfs fs/msdosfs/msdosfs_conv.c optional msdosfs fs/msdosfs/msdosfs_denode.c optional msdosfs fs/msdosfs/msdosfs_fat.c optional msdosfs fs/msdosfs/msdosfs_fileno.c optional msdosfs fs/msdosfs/msdosfs_iconv.c optional msdosfs_iconv fs/msdosfs/msdosfs_lookup.c optional msdosfs fs/msdosfs/msdosfs_vfsops.c optional msdosfs fs/msdosfs/msdosfs_vnops.c optional msdosfs fs/nfs/nfs_commonkrpc.c optional nfscl | nfsd fs/nfs/nfs_commonsubs.c optional nfscl | nfsd fs/nfs/nfs_commonport.c optional nfscl | nfsd fs/nfs/nfs_commonacl.c optional nfscl | nfsd fs/nfsclient/nfs_clcomsubs.c optional nfscl fs/nfsclient/nfs_clsubs.c optional nfscl fs/nfsclient/nfs_clstate.c optional nfscl fs/nfsclient/nfs_clkrpc.c optional nfscl fs/nfsclient/nfs_clrpcops.c optional nfscl fs/nfsclient/nfs_clvnops.c optional nfscl fs/nfsclient/nfs_clnode.c optional nfscl fs/nfsclient/nfs_clvfsops.c optional nfscl fs/nfsclient/nfs_clport.c optional nfscl fs/nfsclient/nfs_clbio.c optional nfscl fs/nfsclient/nfs_clnfsiod.c optional nfscl fs/nfsserver/nfs_nfsdsocket.c optional nfsd inet fs/nfsserver/nfs_nfsdsubs.c optional nfsd inet fs/nfsserver/nfs_nfsdstate.c optional nfsd inet fs/nfsserver/nfs_nfsdkrpc.c optional nfsd inet fs/nfsserver/nfs_nfsdserv.c optional nfsd inet fs/nfsserver/nfs_nfsdport.c optional nfsd inet fs/nfsserver/nfs_nfsdcache.c optional nfsd inet fs/ntfs/ntfs_compr.c optional ntfs fs/ntfs/ntfs_iconv.c optional ntfs_iconv fs/ntfs/ntfs_ihash.c optional ntfs fs/ntfs/ntfs_subr.c optional ntfs fs/ntfs/ntfs_vfsops.c optional ntfs fs/ntfs/ntfs_vnops.c optional ntfs fs/nullfs/null_subr.c optional nullfs fs/nullfs/null_vfsops.c optional nullfs fs/nullfs/null_vnops.c optional nullfs fs/nwfs/nwfs_io.c optional nwfs fs/nwfs/nwfs_ioctl.c optional nwfs fs/nwfs/nwfs_node.c optional nwfs fs/nwfs/nwfs_subr.c optional nwfs fs/nwfs/nwfs_vfsops.c optional nwfs fs/nwfs/nwfs_vnops.c optional nwfs fs/portalfs/portal_vfsops.c optional portalfs fs/portalfs/portal_vnops.c optional portalfs fs/procfs/procfs.c optional procfs fs/procfs/procfs_ctl.c optional procfs fs/procfs/procfs_dbregs.c optional procfs fs/procfs/procfs_fpregs.c optional procfs fs/procfs/procfs_ioctl.c optional procfs fs/procfs/procfs_map.c optional procfs fs/procfs/procfs_mem.c optional procfs fs/procfs/procfs_note.c optional procfs fs/procfs/procfs_osrel.c optional procfs fs/procfs/procfs_regs.c optional procfs fs/procfs/procfs_rlimit.c optional procfs fs/procfs/procfs_status.c optional procfs fs/procfs/procfs_type.c optional procfs fs/pseudofs/pseudofs.c optional pseudofs fs/pseudofs/pseudofs_fileno.c optional pseudofs fs/pseudofs/pseudofs_vncache.c optional pseudofs fs/pseudofs/pseudofs_vnops.c optional pseudofs fs/smbfs/smbfs_io.c optional smbfs fs/smbfs/smbfs_node.c optional smbfs fs/smbfs/smbfs_smb.c optional smbfs fs/smbfs/smbfs_subr.c optional smbfs fs/smbfs/smbfs_vfsops.c optional smbfs fs/smbfs/smbfs_vnops.c optional smbfs fs/udf/osta.c optional udf fs/udf/udf_iconv.c optional udf_iconv fs/udf/udf_vfsops.c optional udf fs/udf/udf_vnops.c optional udf fs/unionfs/union_subr.c optional unionfs fs/unionfs/union_vfsops.c optional unionfs fs/unionfs/union_vnops.c optional unionfs fs/tmpfs/tmpfs_vnops.c optional tmpfs fs/tmpfs/tmpfs_fifoops.c optional tmpfs fs/tmpfs/tmpfs_vfsops.c optional tmpfs fs/tmpfs/tmpfs_subr.c optional tmpfs gdb/gdb_cons.c optional gdb gdb/gdb_main.c optional gdb gdb/gdb_packet.c optional gdb geom/bde/g_bde.c optional geom_bde geom/bde/g_bde_crypt.c optional geom_bde geom/bde/g_bde_lock.c optional geom_bde geom/bde/g_bde_work.c optional geom_bde geom/cache/g_cache.c optional geom_cache geom/concat/g_concat.c optional geom_concat geom/eli/g_eli.c optional geom_eli geom/eli/g_eli_crypto.c optional geom_eli geom/eli/g_eli_ctl.c optional geom_eli geom/eli/g_eli_integrity.c optional geom_eli geom/eli/g_eli_key.c optional geom_eli geom/eli/g_eli_privacy.c optional geom_eli geom/eli/pkcs5v2.c optional geom_eli geom/gate/g_gate.c optional geom_gate geom/geom_aes.c optional geom_aes geom/geom_bsd.c optional geom_bsd geom/geom_bsd_enc.c optional geom_bsd geom/geom_ccd.c optional ccd | geom_ccd geom/geom_ctl.c standard geom/geom_dev.c standard geom/geom_disk.c standard geom/geom_dump.c standard geom/geom_event.c standard geom/geom_fox.c optional geom_fox geom/geom_io.c standard geom/geom_kern.c standard geom/geom_mbr.c optional geom_mbr geom/geom_mbr_enc.c optional geom_mbr geom/geom_pc98.c optional geom_pc98 geom/geom_pc98_enc.c optional geom_pc98 geom/geom_redboot.c optional geom_redboot geom/geom_slice.c standard geom/geom_subr.c standard geom/geom_sunlabel.c optional geom_sunlabel geom/geom_sunlabel_enc.c optional geom_sunlabel geom/geom_vfs.c standard geom/geom_vol_ffs.c optional geom_vol geom/journal/g_journal.c optional geom_journal geom/journal/g_journal_ufs.c optional geom_journal geom/label/g_label.c optional geom_label geom/label/g_label_ext2fs.c optional geom_label geom/label/g_label_iso9660.c optional geom_label geom/label/g_label_msdosfs.c optional geom_label geom/label/g_label_ntfs.c optional geom_label geom/label/g_label_reiserfs.c optional geom_label geom/label/g_label_ufs.c optional geom_label geom/label/g_label_gpt.c optional geom_label geom/linux_lvm/g_linux_lvm.c optional geom_linux_lvm geom/mirror/g_mirror.c optional geom_mirror geom/mirror/g_mirror_ctl.c optional geom_mirror geom/multipath/g_multipath.c optional geom_multipath geom/nop/g_nop.c optional geom_nop geom/part/g_part.c standard geom/part/g_part_if.m standard geom/part/g_part_apm.c optional geom_part_apm geom/part/g_part_bsd.c optional geom_part_bsd geom/part/g_part_ebr.c optional geom_part_ebr geom/part/g_part_gpt.c optional geom_part_gpt geom/part/g_part_mbr.c optional geom_part_mbr geom/part/g_part_pc98.c optional geom_part_pc98 geom/part/g_part_vtoc8.c optional geom_part_vtoc8 geom/raid3/g_raid3.c optional geom_raid3 geom/raid3/g_raid3_ctl.c optional geom_raid3 geom/shsec/g_shsec.c optional geom_shsec geom/stripe/g_stripe.c optional geom_stripe geom/uzip/g_uzip.c optional geom_uzip geom/virstor/binstream.c optional geom_virstor geom/virstor/g_virstor.c optional geom_virstor geom/virstor/g_virstor_md.c optional geom_virstor geom/zero/g_zero.c optional geom_zero gnu/fs/ext2fs/ext2_alloc.c optional ext2fs \ warning "kernel contains GPL contaminated ext2fs filesystem" gnu/fs/ext2fs/ext2_balloc.c optional ext2fs gnu/fs/ext2fs/ext2_bmap.c optional ext2fs gnu/fs/ext2fs/ext2_inode.c optional ext2fs gnu/fs/ext2fs/ext2_inode_cnv.c optional ext2fs gnu/fs/ext2fs/ext2_linux_balloc.c optional ext2fs gnu/fs/ext2fs/ext2_linux_ialloc.c optional ext2fs gnu/fs/ext2fs/ext2_lookup.c optional ext2fs gnu/fs/ext2fs/ext2_subr.c optional ext2fs gnu/fs/ext2fs/ext2_vfsops.c optional ext2fs gnu/fs/ext2fs/ext2_vnops.c optional ext2fs gnu/fs/reiserfs/reiserfs_hashes.c optional reiserfs \ warning "kernel contains GPL contaminated ReiserFS filesystem" gnu/fs/reiserfs/reiserfs_inode.c optional reiserfs gnu/fs/reiserfs/reiserfs_item_ops.c optional reiserfs gnu/fs/reiserfs/reiserfs_namei.c optional reiserfs gnu/fs/reiserfs/reiserfs_prints.c optional reiserfs gnu/fs/reiserfs/reiserfs_stree.c optional reiserfs gnu/fs/reiserfs/reiserfs_vfsops.c optional reiserfs gnu/fs/reiserfs/reiserfs_vnops.c optional reiserfs # isa/isa_if.m standard isa/isa_common.c optional isa isa/isahint.c optional isa isa/orm.c optional isa isa/pnp.c optional isa isapnp isa/pnpparse.c optional isa isapnp fs/cd9660/cd9660_bmap.c optional cd9660 fs/cd9660/cd9660_lookup.c optional cd9660 fs/cd9660/cd9660_node.c optional cd9660 fs/cd9660/cd9660_rrip.c optional cd9660 fs/cd9660/cd9660_util.c optional cd9660 fs/cd9660/cd9660_vfsops.c optional cd9660 fs/cd9660/cd9660_vnops.c optional cd9660 fs/cd9660/cd9660_iconv.c optional cd9660_iconv kern/bus_if.m standard kern/clock_if.m standard kern/cpufreq_if.m standard kern/device_if.m standard kern/imgact_elf.c standard kern/imgact_shell.c standard kern/inflate.c optional gzip kern/init_main.c standard kern/init_sysent.c standard kern/ksched.c optional _kposix_priority_scheduling kern/kern_acct.c standard kern/kern_alq.c optional alq kern/kern_clock.c standard kern/kern_condvar.c standard kern/kern_conf.c standard kern/kern_cons.c standard kern/kern_cpu.c standard kern/kern_cpuset.c standard kern/kern_context.c standard kern/kern_descrip.c standard kern/kern_dtrace.c optional kdtrace_hooks kern/kern_environment.c standard kern/kern_event.c standard kern/kern_exec.c standard kern/kern_exit.c standard kern/kern_fail.c standard kern/kern_fork.c standard kern/kern_hhook.c standard kern/kern_idle.c standard kern/kern_intr.c standard kern/kern_jail.c standard kern/kern_khelp.c standard kern/kern_kthread.c standard kern/kern_ktr.c optional ktr kern/kern_ktrace.c standard kern/kern_linker.c standard kern/kern_lock.c standard kern/kern_lockf.c standard kern/kern_lockstat.c optional kdtrace_hooks kern/kern_malloc.c standard kern/kern_mbuf.c standard kern/kern_mib.c standard kern/kern_module.c standard kern/kern_mtxpool.c standard kern/kern_mutex.c standard kern/kern_ntptime.c standard kern/kern_osd.c standard kern/kern_physio.c standard kern/kern_pmc.c standard kern/kern_poll.c optional device_polling kern/kern_priv.c standard kern/kern_proc.c standard kern/kern_prot.c standard kern/kern_resource.c standard kern/kern_rmlock.c standard kern/kern_rwlock.c standard kern/kern_sdt.c optional kdtrace_hooks kern/kern_sema.c standard kern/kern_shutdown.c standard kern/kern_sig.c standard kern/kern_subr.c standard kern/kern_switch.c standard kern/kern_sx.c standard kern/kern_synch.c standard kern/kern_syscalls.c standard kern/kern_sysctl.c standard kern/kern_tc.c standard kern/kern_thr.c standard kern/kern_thread.c standard kern/kern_time.c standard kern/kern_timeout.c standard kern/kern_umtx.c standard kern/kern_uuid.c standard kern/kern_xxx.c standard kern/link_elf.c standard kern/linker_if.m standard kern/md4c.c optional netsmb kern/md5c.c standard kern/p1003_1b.c standard kern/posix4_mib.c standard kern/sched_4bsd.c optional sched_4bsd kern/sched_ule.c optional sched_ule kern/serdev_if.m standard kern/stack_protector.c standard \ compile-with "${NORMAL_C:N-fstack-protector*}" kern/subr_acl_nfs4.c standard kern/subr_acl_posix1e.c standard kern/subr_autoconf.c standard kern/subr_blist.c standard kern/subr_bus.c standard kern/subr_bufring.c standard kern/subr_clock.c standard kern/subr_devstat.c standard kern/subr_disk.c standard kern/subr_eventhandler.c standard kern/subr_fattime.c standard kern/subr_firmware.c optional firmware kern/subr_hints.c standard kern/subr_kdb.c standard kern/subr_kobj.c standard kern/subr_lock.c standard kern/subr_log.c standard kern/subr_mbpool.c optional libmbpool kern/subr_mchain.c optional libmchain kern/subr_module.c standard kern/subr_msgbuf.c standard kern/subr_param.c standard kern/subr_pcpu.c standard kern/subr_power.c standard kern/subr_prf.c standard kern/subr_prof.c standard kern/subr_rman.c standard kern/subr_rtc.c standard kern/subr_sbuf.c standard kern/subr_scanf.c standard kern/subr_sglist.c standard kern/subr_sleepqueue.c standard kern/subr_smp.c standard kern/subr_stack.c optional ddb | stack | ktr kern/subr_taskqueue.c standard kern/subr_trap.c standard kern/subr_turnstile.c standard kern/subr_unit.c standard kern/subr_witness.c optional witness kern/sys_generic.c standard kern/sys_pipe.c standard kern/sys_process.c standard kern/sys_socket.c standard kern/syscalls.c standard kern/sysv_ipc.c standard kern/sysv_msg.c optional sysvmsg kern/sysv_sem.c optional sysvsem kern/sysv_shm.c optional sysvshm kern/tty.c standard kern/tty_compat.c optional compat_43tty kern/tty_info.c standard kern/tty_inq.c standard kern/tty_outq.c standard kern/tty_pts.c standard kern/tty_pty.c optional pty kern/tty_tty.c standard kern/tty_ttydisc.c standard kern/uipc_accf.c optional inet kern/uipc_cow.c optional zero_copy_sockets kern/uipc_debug.c optional ddb kern/uipc_domain.c standard kern/uipc_mbuf.c standard kern/uipc_mbuf2.c standard kern/uipc_mqueue.c optional p1003_1b_mqueue kern/uipc_sem.c optional p1003_1b_semaphores kern/uipc_shm.c standard kern/uipc_sockbuf.c standard kern/uipc_socket.c standard kern/uipc_syscalls.c standard kern/uipc_usrreq.c standard kern/vfs_acl.c standard kern/vfs_aio.c optional vfs_aio kern/vfs_bio.c standard kern/vfs_cache.c standard kern/vfs_cluster.c standard kern/vfs_default.c standard kern/vfs_export.c standard kern/vfs_extattr.c standard kern/vfs_hash.c standard kern/vfs_init.c standard kern/vfs_lookup.c standard kern/vfs_mount.c standard kern/vfs_subr.c standard kern/vfs_syscalls.c standard kern/vfs_vnops.c standard # # Kernel GSS-API # gssd.h optional kgssapi \ dependency "$S/kgssapi/gssd.x" \ compile-with "rpcgen -hM $S/kgssapi/gssd.x | grep -v pthread.h > gssd.h" \ no-obj no-implicit-rule before-depend local \ clean "gssd.h" gssd_xdr.c optional kgssapi \ dependency "$S/kgssapi/gssd.x gssd.h" \ compile-with "rpcgen -c $S/kgssapi/gssd.x -o gssd_xdr.c" \ no-implicit-rule before-depend local \ clean "gssd_xdr.c" gssd_clnt.c optional kgssapi \ dependency "$S/kgssapi/gssd.x gssd.h" \ compile-with "rpcgen -lM $S/kgssapi/gssd.x | grep -v string.h > gssd_clnt.c" \ no-implicit-rule before-depend local \ clean "gssd_clnt.c" kgssapi/gss_accept_sec_context.c optional kgssapi kgssapi/gss_add_oid_set_member.c optional kgssapi kgssapi/gss_acquire_cred.c optional kgssapi kgssapi/gss_canonicalize_name.c optional kgssapi kgssapi/gss_create_empty_oid_set.c optional kgssapi kgssapi/gss_delete_sec_context.c optional kgssapi kgssapi/gss_display_status.c optional kgssapi kgssapi/gss_export_name.c optional kgssapi kgssapi/gss_get_mic.c optional kgssapi kgssapi/gss_init_sec_context.c optional kgssapi kgssapi/gss_impl.c optional kgssapi kgssapi/gss_import_name.c optional kgssapi kgssapi/gss_names.c optional kgssapi kgssapi/gss_pname_to_uid.c optional kgssapi kgssapi/gss_release_buffer.c optional kgssapi kgssapi/gss_release_cred.c optional kgssapi kgssapi/gss_release_name.c optional kgssapi kgssapi/gss_release_oid_set.c optional kgssapi kgssapi/gss_set_cred_option.c optional kgssapi kgssapi/gss_test_oid_set_member.c optional kgssapi kgssapi/gss_unwrap.c optional kgssapi kgssapi/gss_verify_mic.c optional kgssapi kgssapi/gss_wrap.c optional kgssapi kgssapi/gss_wrap_size_limit.c optional kgssapi kgssapi/gssd_prot.c optional kgssapi kgssapi/krb5/krb5_mech.c optional kgssapi kgssapi/krb5/kcrypto.c optional kgssapi kgssapi/krb5/kcrypto_aes.c optional kgssapi kgssapi/krb5/kcrypto_arcfour.c optional kgssapi kgssapi/krb5/kcrypto_des.c optional kgssapi kgssapi/krb5/kcrypto_des3.c optional kgssapi kgssapi/kgss_if.m optional kgssapi kgssapi/gsstest.c optional kgssapi_debug # These files in libkern/ are those needed by all architectures. Some # of the files in libkern/ are only needed on some architectures, e.g., # libkern/divdi3.c is needed by i386 but not alpha. Also, some of these # routines may be optimized for a particular platform. In either case, # the file should be moved to conf/files. from here. # libkern/arc4random.c standard libkern/bcd.c standard libkern/bsearch.c standard libkern/crc32.c standard libkern/fnmatch.c standard libkern/gets.c standard libkern/iconv.c optional libiconv libkern/iconv_converter_if.m optional libiconv libkern/iconv_xlat.c optional libiconv libkern/iconv_xlat16.c optional libiconv libkern/index.c standard libkern/inet_aton.c standard libkern/inet_ntoa.c standard libkern/inet_ntop.c standard libkern/inet_pton.c standard libkern/mcount.c optional profiling-routine libkern/memcmp.c standard libkern/qsort.c standard libkern/qsort_r.c standard libkern/random.c standard libkern/rindex.c standard libkern/scanc.c standard libkern/skpc.c standard libkern/strcasecmp.c standard libkern/strcat.c standard libkern/strcmp.c standard libkern/strcpy.c standard libkern/strcspn.c standard libkern/strdup.c standard libkern/strlcat.c standard libkern/strlcpy.c standard libkern/strlen.c standard libkern/strncmp.c standard libkern/strncpy.c standard libkern/strsep.c standard libkern/strspn.c standard libkern/strstr.c standard libkern/strtol.c standard libkern/strtoq.c standard libkern/strtoul.c standard libkern/strtouq.c standard libkern/strvalid.c standard net/bpf.c standard net/bpf_buffer.c optional bpf net/bpf_jitter.c optional bpf_jitter net/bpf_filter.c optional bpf | netgraph_bpf net/bpf_zerocopy.c optional bpf net/bridgestp.c optional bridge | if_bridge net/flowtable.c optional flowtable inet net/ieee8023ad_lacp.c optional lagg net/if.c standard net/if_arcsubr.c optional arcnet net/if_atmsubr.c optional atm net/if_bridge.c optional bridge inet | if_bridge inet net/if_clone.c standard net/if_dead.c standard net/if_debug.c optional ddb net/if_disc.c optional disc net/if_edsc.c optional edsc net/if_ef.c optional ef net/if_enc.c optional enc ipsec inet | enc ipsec inet6 net/if_epair.c optional epair net/if_ethersubr.c optional ether \ compile-with "${NORMAL_C} -I$S/contrib/pf" net/if_faith.c optional faith net/if_fddisubr.c optional fddi net/if_fwsubr.c optional fwip net/if_gif.c optional gif | netgraph_gif net/if_gre.c optional gre inet net/if_iso88025subr.c optional token net/if_lagg.c optional lagg net/if_loop.c optional loop net/if_llatbl.c standard net/if_media.c standard net/if_mib.c standard net/if_spppfr.c optional sppp | netgraph_sppp net/if_spppsubr.c optional sppp | netgraph_sppp net/if_stf.c optional stf inet inet6 net/if_tun.c optional tun net/if_tap.c optional tap net/if_vlan.c optional vlan net/mppcc.c optional netgraph_mppc_compression net/mppcd.c optional netgraph_mppc_compression net/netisr.c standard net/pfil.c optional ether | inet net/radix.c standard net/radix_mpath.c standard net/raw_cb.c standard net/raw_usrreq.c standard net/route.c standard net/rtsock.c standard net/slcompress.c optional netgraph_vjc | sppp | \ netgraph_sppp net/vnet.c optional vimage net/zlib.c optional crypto | geom_uzip | ipsec | \ mxge | netgraph_deflate | \ ddb_ctf net80211/ieee80211.c optional wlan net80211/ieee80211_acl.c optional wlan wlan_acl net80211/ieee80211_action.c optional wlan net80211/ieee80211_ageq.c optional wlan net80211/ieee80211_adhoc.c optional wlan net80211/ieee80211_ageq.c optional wlan net80211/ieee80211_amrr.c optional wlan | wlan_amrr net80211/ieee80211_crypto.c optional wlan net80211/ieee80211_crypto_ccmp.c optional wlan wlan_ccmp net80211/ieee80211_crypto_none.c optional wlan net80211/ieee80211_crypto_tkip.c optional wlan wlan_tkip net80211/ieee80211_crypto_wep.c optional wlan wlan_wep net80211/ieee80211_ddb.c optional wlan ddb net80211/ieee80211_dfs.c optional wlan net80211/ieee80211_freebsd.c optional wlan net80211/ieee80211_hostap.c optional wlan net80211/ieee80211_ht.c optional wlan net80211/ieee80211_hwmp.c optional wlan ieee80211_support_mesh net80211/ieee80211_input.c optional wlan net80211/ieee80211_ioctl.c optional wlan net80211/ieee80211_mesh.c optional wlan ieee80211_support_mesh net80211/ieee80211_monitor.c optional wlan net80211/ieee80211_node.c optional wlan net80211/ieee80211_output.c optional wlan net80211/ieee80211_phy.c optional wlan net80211/ieee80211_power.c optional wlan net80211/ieee80211_proto.c optional wlan net80211/ieee80211_radiotap.c optional wlan net80211/ieee80211_ratectl.c optional wlan net80211/ieee80211_ratectl_none.c optional wlan net80211/ieee80211_regdomain.c optional wlan net80211/ieee80211_rssadapt.c optional wlan wlan_rssadapt net80211/ieee80211_scan.c optional wlan net80211/ieee80211_scan_sta.c optional wlan net80211/ieee80211_sta.c optional wlan net80211/ieee80211_superg.c optional wlan ieee80211_support_superg net80211/ieee80211_tdma.c optional wlan ieee80211_support_tdma net80211/ieee80211_wds.c optional wlan net80211/ieee80211_xauth.c optional wlan wlan_xauth netatalk/aarp.c optional netatalk netatalk/at_control.c optional netatalk netatalk/at_proto.c optional netatalk netatalk/at_rmx.c optional netatalk netatalk/ddp_input.c optional netatalk netatalk/ddp_output.c optional netatalk netatalk/ddp_pcb.c optional netatalk netatalk/ddp_usrreq.c optional netatalk netgraph/atm/ccatm/ng_ccatm.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/ng_atm.c optional ngatm_atm netgraph/atm/ngatmbase.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/sscfu/ng_sscfu.c optional ngatm_sscfu \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/sscop/ng_sscop.c optional ngatm_sscop \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/uni/ng_uni.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/bluetooth/common/ng_bluetooth.c optional netgraph_bluetooth netgraph/bluetooth/drivers/bt3c/ng_bt3c_pccard.c optional netgraph_bluetooth_bt3c netgraph/bluetooth/drivers/h4/ng_h4.c optional netgraph_bluetooth_h4 netgraph/bluetooth/drivers/ubt/ng_ubt.c optional netgraph_bluetooth_ubt usb netgraph/bluetooth/drivers/ubtbcmfw/ubtbcmfw.c optional netgraph_bluetooth_ubtbcmfw usb netgraph/bluetooth/hci/ng_hci_cmds.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_evnt.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_main.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_misc.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_ulpi.c optional netgraph_bluetooth_hci netgraph/bluetooth/l2cap/ng_l2cap_cmds.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_evnt.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_llpi.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_main.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_misc.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_ulpi.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/socket/ng_btsocket.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_hci_raw.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_l2cap.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_l2cap_raw.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_rfcomm.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_sco.c optional netgraph_bluetooth_socket netgraph/netflow/netflow.c optional netgraph_netflow netgraph/netflow/ng_netflow.c optional netgraph_netflow netgraph/ng_UI.c optional netgraph_UI netgraph/ng_async.c optional netgraph_async netgraph/ng_atmllc.c optional netgraph_atmllc netgraph/ng_base.c optional netgraph netgraph/ng_bpf.c optional netgraph_bpf netgraph/ng_bridge.c optional netgraph_bridge netgraph/ng_car.c optional netgraph_car netgraph/ng_cisco.c optional netgraph_cisco netgraph/ng_deflate.c optional netgraph_deflate netgraph/ng_device.c optional netgraph_device netgraph/ng_echo.c optional netgraph_echo netgraph/ng_eiface.c optional netgraph_eiface netgraph/ng_ether.c optional netgraph_ether netgraph/ng_ether_echo.c optional netgraph_ether_echo netgraph/ng_fec.c optional netgraph_fec netgraph/ng_frame_relay.c optional netgraph_frame_relay netgraph/ng_gif.c optional netgraph_gif netgraph/ng_gif_demux.c optional netgraph_gif_demux netgraph/ng_hole.c optional netgraph_hole netgraph/ng_iface.c optional netgraph_iface netgraph/ng_ip_input.c optional netgraph_ip_input netgraph/ng_ipfw.c optional netgraph_ipfw inet ipfirewall netgraph/ng_ksocket.c optional netgraph_ksocket netgraph/ng_l2tp.c optional netgraph_l2tp netgraph/ng_lmi.c optional netgraph_lmi netgraph/ng_mppc.c optional netgraph_mppc_compression | \ netgraph_mppc_encryption netgraph/ng_nat.c optional netgraph_nat inet libalias netgraph/ng_one2many.c optional netgraph_one2many netgraph/ng_parse.c optional netgraph netgraph/ng_patch.c optional netgraph_patch netgraph/ng_pipe.c optional netgraph_pipe netgraph/ng_ppp.c optional netgraph_ppp netgraph/ng_pppoe.c optional netgraph_pppoe netgraph/ng_pptpgre.c optional netgraph_pptpgre netgraph/ng_pred1.c optional netgraph_pred1 netgraph/ng_rfc1490.c optional netgraph_rfc1490 netgraph/ng_socket.c optional netgraph_socket netgraph/ng_split.c optional netgraph_split netgraph/ng_sppp.c optional netgraph_sppp netgraph/ng_tag.c optional netgraph_tag netgraph/ng_tcpmss.c optional netgraph_tcpmss netgraph/ng_tee.c optional netgraph_tee netgraph/ng_tty.c optional netgraph_tty netgraph/ng_vjc.c optional netgraph_vjc netinet/accf_data.c optional accept_filter_data inet netinet/accf_dns.c optional accept_filter_dns inet netinet/accf_http.c optional accept_filter_http inet netinet/if_atm.c optional atm netinet/if_ether.c optional inet ether netinet/igmp.c optional inet netinet/in.c optional inet netinet/in_debug.c optional inet ddb netinet/ip_carp.c optional inet carp | inet6 carp netinet/in_gif.c optional gif inet | netgraph_gif inet netinet/ip_gre.c optional gre inet netinet/ip_id.c optional inet netinet/in_mcast.c optional inet netinet/in_pcb.c optional inet | inet6 netinet/in_proto.c optional inet \ compile-with "${NORMAL_C} -I$S/contrib/pf" netinet/in_rmx.c optional inet netinet/ip_divert.c optional inet ipdivert ipfirewall netinet/ipfw/dn_heap.c optional inet dummynet netinet/ipfw/dn_sched_fifo.c optional inet dummynet netinet/ipfw/dn_sched_prio.c optional inet dummynet netinet/ipfw/dn_sched_qfq.c optional inet dummynet netinet/ipfw/dn_sched_rr.c optional inet dummynet netinet/ipfw/dn_sched_wf2q.c optional inet dummynet netinet/ipfw/ip_dummynet.c optional inet dummynet netinet/ipfw/ip_dn_io.c optional inet dummynet netinet/ipfw/ip_dn_glue.c optional inet dummynet netinet/ip_ecn.c optional inet | inet6 netinet/ip_encap.c optional inet | inet6 netinet/ip_fastfwd.c optional inet netinet/ipfw/ip_fw2.c optional inet ipfirewall \ compile-with "${NORMAL_C} -I$S/contrib/pf" netinet/ipfw/ip_fw_dynamic.c optional inet ipfirewall netinet/ipfw/ip_fw_log.c optional inet ipfirewall netinet/ipfw/ip_fw_pfil.c optional inet ipfirewall netinet/ipfw/ip_fw_sockopt.c optional inet ipfirewall netinet/ipfw/ip_fw_table.c optional inet ipfirewall netinet/ipfw/ip_fw_nat.c optional inet ipfirewall_nat netinet/ip_icmp.c optional inet netinet/ip_input.c optional inet netinet/ip_ipsec.c optional inet ipsec netinet/ip_mroute.c optional mrouting inet | mrouting inet6 netinet/ip_options.c optional inet netinet/ip_output.c optional inet netinet/raw_ip.c optional inet netinet/cc/cc.c optional inet netinet/cc/cc_newreno.c optional inet netinet/sctp_asconf.c optional inet sctp netinet/sctp_auth.c optional inet sctp netinet/sctp_bsd_addr.c optional inet sctp netinet/sctp_cc_functions.c optional inet sctp netinet/sctp_crc32.c optional inet sctp netinet/sctp_indata.c optional inet sctp netinet/sctp_input.c optional inet sctp netinet/sctp_output.c optional inet sctp netinet/sctp_pcb.c optional inet sctp netinet/sctp_peeloff.c optional inet sctp netinet/sctp_sysctl.c optional inet sctp netinet/sctp_timer.c optional inet sctp netinet/sctp_usrreq.c optional inet sctp netinet/sctputil.c optional inet sctp netinet/tcp_debug.c optional tcpdebug netinet/tcp_hostcache.c optional inet netinet/tcp_input.c optional inet netinet/tcp_lro.c optional inet netinet/tcp_output.c optional inet netinet/tcp_offload.c optional inet netinet/tcp_reass.c optional inet netinet/tcp_sack.c optional inet netinet/tcp_subr.c optional inet netinet/tcp_syncache.c optional inet netinet/tcp_timer.c optional inet netinet/tcp_timewait.c optional inet netinet/tcp_usrreq.c optional inet netinet/udp_usrreq.c optional inet netinet/libalias/alias.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_db.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_mod.c optional libalias | netgraph_nat netinet/libalias/alias_proxy.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_util.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_sctp.c optional libalias inet | netgraph_nat inet netinet6/dest6.c optional inet6 netinet6/frag6.c optional inet6 netinet6/icmp6.c optional inet6 netinet6/in6.c optional inet6 netinet6/in6_cksum.c optional inet6 netinet6/in6_gif.c optional gif inet6 | netgraph_gif inet6 netinet6/in6_ifattach.c optional inet6 netinet6/in6_mcast.c optional inet6 netinet6/in6_pcb.c optional inet6 netinet6/in6_proto.c optional inet6 netinet6/in6_rmx.c optional inet6 netinet6/in6_src.c optional inet6 netinet6/ip6_forward.c optional inet6 netinet6/ip6_id.c optional inet6 netinet6/ip6_input.c optional inet6 netinet6/ip6_mroute.c optional mrouting inet6 netinet6/ip6_output.c optional inet6 netinet6/ip6_ipsec.c optional inet6 ipsec netinet6/mld6.c optional inet6 netinet6/nd6.c optional inet6 netinet6/nd6_nbr.c optional inet6 netinet6/nd6_rtr.c optional inet6 netinet6/raw_ip6.c optional inet6 netinet6/route6.c optional inet6 netinet6/scope6.c optional inet6 netinet6/sctp6_usrreq.c optional inet6 sctp netinet6/udp6_usrreq.c optional inet6 netipsec/ipsec.c optional ipsec inet | ipsec inet6 netipsec/ipsec_input.c optional ipsec inet | ipsec inet6 netipsec/ipsec_mbuf.c optional ipsec inet | ipsec inet6 netipsec/ipsec_output.c optional ipsec inet | ipsec inet6 netipsec/key.c optional ipsec inet | ipsec inet6 netipsec/key_debug.c optional ipsec inet | ipsec inet6 netipsec/keysock.c optional ipsec inet | ipsec inet6 netipsec/xform_ah.c optional ipsec inet | ipsec inet6 netipsec/xform_esp.c optional ipsec inet | ipsec inet6 netipsec/xform_ipcomp.c optional ipsec inet | ipsec inet6 netipsec/xform_ipip.c optional ipsec inet | ipsec inet6 netipsec/xform_tcp.c optional ipsec inet tcp_signature | \ ipsec inet6 tcp_signature netipx/ipx.c optional ipx netipx/ipx_cksum.c optional ipx netipx/ipx_input.c optional ipx netipx/ipx_outputfl.c optional ipx netipx/ipx_pcb.c optional ipx netipx/ipx_proto.c optional ipx netipx/ipx_usrreq.c optional ipx netipx/spx_debug.c optional ipx netipx/spx_reass.c optional ipx netipx/spx_usrreq.c optional ipx netnatm/natm.c optional natm netnatm/natm_pcb.c optional natm netnatm/natm_proto.c optional natm netncp/ncp_conn.c optional ncp netncp/ncp_crypt.c optional ncp netncp/ncp_login.c optional ncp netncp/ncp_mod.c optional ncp netncp/ncp_ncp.c optional ncp netncp/ncp_nls.c optional ncp netncp/ncp_rq.c optional ncp netncp/ncp_sock.c optional ncp netncp/ncp_subr.c optional ncp netsmb/smb_conn.c optional netsmb netsmb/smb_crypt.c optional netsmb netsmb/smb_dev.c optional netsmb netsmb/smb_iod.c optional netsmb netsmb/smb_rq.c optional netsmb netsmb/smb_smb.c optional netsmb netsmb/smb_subr.c optional netsmb netsmb/smb_trantcp.c optional netsmb netsmb/smb_usr.c optional netsmb nfs/bootp_subr.c optional bootp nfsclient | bootp nfscl nfs/krpc_subr.c optional bootp nfsclient | bootp nfscl nfs/nfs_common.c optional nfsclient | nfsserver nfs/nfs_diskless.c optional nfsclient nfs_root | nfscl nfs_root nfs/nfs_lock.c optional nfsclient | nfscl | nfslockd | nfsd nfsclient/nfs_bio.c optional nfsclient nfsclient/nfs_node.c optional nfsclient nfsclient/nfs_krpc.c optional nfsclient nfsclient/nfs_subs.c optional nfsclient nfsclient/nfs_nfsiod.c optional nfsclient nfsclient/nfs_vfsops.c optional nfsclient nfsclient/nfs_vnops.c optional nfsclient nfsserver/nfs_fha.c optional nfsserver nfsserver/nfs_serv.c optional nfsserver nfsserver/nfs_srvkrpc.c optional nfsserver nfsserver/nfs_srvsubs.c optional nfsserver nfs/nfs_nfssvc.c optional nfsserver | nfscl | nfsd nlm/nlm_advlock.c optional nfslockd | nfsd nlm/nlm_prot_clnt.c optional nfslockd | nfsd nlm/nlm_prot_impl.c optional nfslockd | nfsd nlm/nlm_prot_server.c optional nfslockd | nfsd nlm/nlm_prot_svc.c optional nfslockd | nfsd nlm/nlm_prot_xdr.c optional nfslockd | nfsd nlm/sm_inter_xdr.c optional nfslockd | nfsd # crypto support opencrypto/cast.c optional crypto | ipsec opencrypto/criov.c optional crypto opencrypto/crypto.c optional crypto opencrypto/cryptodev.c optional cryptodev opencrypto/cryptodev_if.m optional crypto opencrypto/cryptosoft.c optional crypto opencrypto/deflate.c optional crypto opencrypto/rmd160.c optional crypto | ipsec opencrypto/skipjack.c optional crypto opencrypto/xform.c optional crypto pci/alpm.c optional alpm pci pci/amdpm.c optional amdpm pci | nfpm pci pci/amdsmb.c optional amdsmb pci pci/if_rl.c optional rl pci pci/intpm.c optional intpm pci pci/ncr.c optional ncr pci pci/nfsmb.c optional nfsmb pci pci/viapm.c optional viapm pci rpc/auth_none.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/auth_unix.c optional krpc | nfslockd | nfsclient | nfscl | nfsd rpc/authunix_prot.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/clnt_dg.c optional krpc | nfslockd | nfsclient | nfscl | nfsd rpc/clnt_rc.c optional krpc | nfslockd | nfsclient | nfscl | nfsd rpc/clnt_vc.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/getnetconfig.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/replay.c optional krpc | nfslockd | nfsserver | nfscl | nfsd rpc/rpc_callmsg.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/rpc_generic.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/rpc_prot.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/rpcb_clnt.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/rpcb_prot.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd rpc/svc.c optional krpc | nfslockd | nfsserver | nfscl | nfsd rpc/svc_auth.c optional krpc | nfslockd | nfsserver | nfscl | nfsd rpc/svc_auth_unix.c optional krpc | nfslockd | nfsserver | nfscl | nfsd rpc/svc_dg.c optional krpc | nfslockd | nfsserver | nfscl | nfsd rpc/svc_generic.c optional krpc | nfslockd | nfsserver | nfscl | nfsd rpc/svc_vc.c optional krpc | nfslockd | nfsserver | nfscl | nfsd rpc/rpcsec_gss/rpcsec_gss.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_conf.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_misc.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_prot.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/svc_rpcsec_gss.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi security/audit/audit.c optional audit security/audit/audit_arg.c optional audit security/audit/audit_bsm.c optional audit security/audit/audit_bsm_domain.c optional audit security/audit/audit_bsm_errno.c optional audit security/audit/audit_bsm_fcntl.c optional audit security/audit/audit_bsm_klib.c optional audit security/audit/audit_bsm_socket_type.c optional audit security/audit/audit_bsm_token.c optional audit security/audit/audit_pipe.c optional audit security/audit/audit_syscalls.c standard security/audit/audit_trigger.c optional audit security/audit/audit_worker.c optional audit security/mac/mac_atalk.c optional mac netatalk security/mac/mac_audit.c optional mac audit security/mac/mac_cred.c optional mac security/mac/mac_framework.c optional mac security/mac/mac_inet.c optional mac inet security/mac/mac_inet6.c optional mac inet6 security/mac/mac_label.c optional mac security/mac/mac_net.c optional mac security/mac/mac_pipe.c optional mac security/mac/mac_posix_sem.c optional mac security/mac/mac_posix_shm.c optional mac security/mac/mac_priv.c optional mac security/mac/mac_process.c optional mac security/mac/mac_socket.c optional mac security/mac/mac_syscalls.c standard security/mac/mac_system.c optional mac security/mac/mac_sysv_msg.c optional mac security/mac/mac_sysv_sem.c optional mac security/mac/mac_sysv_shm.c optional mac security/mac/mac_vfs.c optional mac security/mac_biba/mac_biba.c optional mac_biba security/mac_bsdextended/mac_bsdextended.c optional mac_bsdextended security/mac_bsdextended/ugidfw_system.c optional mac_bsdextended security/mac_bsdextended/ugidfw_vnode.c optional mac_bsdextended security/mac_ifoff/mac_ifoff.c optional mac_ifoff security/mac_lomac/mac_lomac.c optional mac_lomac security/mac_mls/mac_mls.c optional mac_mls security/mac_none/mac_none.c optional mac_none security/mac_partition/mac_partition.c optional mac_partition security/mac_portacl/mac_portacl.c optional mac_portacl security/mac_seeotheruids/mac_seeotheruids.c optional mac_seeotheruids security/mac_stub/mac_stub.c optional mac_stub security/mac_test/mac_test.c optional mac_test ufs/ffs/ffs_alloc.c optional ffs ufs/ffs/ffs_balloc.c optional ffs ufs/ffs/ffs_inode.c optional ffs ufs/ffs/ffs_snapshot.c optional ffs ufs/ffs/ffs_softdep.c optional ffs ufs/ffs/ffs_subr.c optional ffs ufs/ffs/ffs_tables.c optional ffs ufs/ffs/ffs_vfsops.c optional ffs ufs/ffs/ffs_vnops.c optional ffs ufs/ffs/ffs_rawread.c optional directio ufs/ufs/ufs_acl.c optional ffs ufs/ufs/ufs_bmap.c optional ffs ufs/ufs/ufs_dirhash.c optional ffs ufs/ufs/ufs_extattr.c optional ffs ufs/ufs/ufs_gjournal.c optional ffs ufs/ufs/ufs_inode.c optional ffs ufs/ufs/ufs_lookup.c optional ffs ufs/ufs/ufs_quota.c optional ffs ufs/ufs/ufs_vfsops.c optional ffs ufs/ufs/ufs_vnops.c optional ffs vm/default_pager.c standard vm/device_pager.c standard vm/phys_pager.c standard vm/redzone.c optional DEBUG_REDZONE vm/sg_pager.c standard vm/swap_pager.c standard vm/uma_core.c standard vm/uma_dbg.c standard vm/vm_contig.c standard vm/memguard.c optional DEBUG_MEMGUARD vm/vm_fault.c standard vm/vm_glue.c standard vm/vm_init.c standard vm/vm_kern.c standard vm/vm_map.c standard vm/vm_meter.c standard vm/vm_mmap.c standard vm/vm_object.c standard vm/vm_page.c standard vm/vm_pageout.c standard vm/vm_pager.c standard vm/vm_phys.c standard vm/vm_reserv.c standard vm/vm_unix.c standard vm/vm_zeroidle.c standard vm/vnode_pager.c standard xdr/xdr.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd xdr/xdr_array.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd xdr/xdr_mbuf.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd xdr/xdr_mem.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd xdr/xdr_reference.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd xdr/xdr_sizeof.c optional krpc | nfslockd | nfsclient | nfsserver | nfscl | nfsd # gnu/fs/xfs/xfs_alloc.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" \ warning "kernel contains GPL contaminated xfs filesystem" gnu/fs/xfs/xfs_alloc_btree.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_bit.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_bmap.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_bmap_btree.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_btree.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_buf_item.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_da_btree.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir2.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir2_block.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir2_data.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir2_leaf.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir2_node.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir2_sf.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir2_trace.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dir_leaf.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_error.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_extfree_item.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_fsops.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_ialloc.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_ialloc_btree.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_inode.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_inode_item.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_iocore.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_itable.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dfrag.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_log.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_log_recover.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_mount.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_rename.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_trans.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_trans_ail.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_trans_buf.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_trans_extfree.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_trans_inode.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_trans_item.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_utils.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_vfsops.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_vnodeops.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_rw.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_attr_leaf.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_attr.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_dmops.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_qmops.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_iget.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_freebsd_iget.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_mountops.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_vnops.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_frw.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_buf.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_globals.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_dmistubs.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_super.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_stats.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_vfs.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_vnode.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_sysctl.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_fs_subr.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/xfs_ioctl.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/support/debug.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/support/ktrace.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/support/mrlock.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/support/uuid.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/FreeBSD/support/kmem.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_iomap.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" gnu/fs/xfs/xfs_behavior.c optional xfs \ compile-with "${NORMAL_C} -I$S/gnu/fs/xfs/FreeBSD -I$S/gnu/fs/xfs/FreeBSD/support -I$S/gnu/fs/xfs" xen/gnttab.c optional xen | xenhvm xen/features.c optional xen | xenhvm xen/evtchn/evtchn.c optional xen xen/evtchn/evtchn_dev.c optional xen | xenhvm xen/xenbus/xenbus_if.m optional xen | xenhvm xen/xenbus/xenbus.c optional xen | xenhvm xen/xenbus/xenbusb_if.m optional xen | xenhvm xen/xenbus/xenbusb.c optional xen | xenhvm xen/xenbus/xenbusb_front.c optional xen | xenhvm xen/xenbus/xenbusb_back.c optional xen | xenhvm xen/xenstore/xenstore.c optional xen | xenhvm xen/xenstore/xenstore_dev.c optional xen | xenhvm dev/xen/balloon/balloon.c optional xen | xenhvm dev/xen/blkfront/blkfront.c optional xen | xenhvm dev/xen/blkback/blkback.c optional xen | xenhvm dev/xen/console/console.c optional xen dev/xen/console/xencons_ring.c optional xen dev/xen/control/control.c optional xen | xenhvm dev/xen/netfront/netfront.c optional xen | xenhvm dev/xen/xenpci/xenpci.c optional xenpci dev/xen/xenpci/evtchn.c optional xenpci Index: stable/8/sys/contrib/dev/acpica =================================================================== --- stable/8/sys/contrib/dev/acpica (revision 222793) +++ stable/8/sys/contrib/dev/acpica (revision 222794) Property changes on: stable/8/sys/contrib/dev/acpica ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/contrib/dev/acpica:r222509-222510,222513,222551-222552,222701,222703 Index: stable/8/sys/contrib/pf =================================================================== --- stable/8/sys/contrib/pf (revision 222793) +++ stable/8/sys/contrib/pf (revision 222794) Property changes on: stable/8/sys/contrib/pf ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/contrib/pf:r222509-222510,222513,222551-222552,222701,222703 Index: stable/8/sys/dev/cxgbe/adapter.h =================================================================== --- stable/8/sys/dev/cxgbe/adapter.h (revision 222793) +++ stable/8/sys/dev/cxgbe/adapter.h (revision 222794) @@ -1,612 +1,627 @@ /*- * Copyright (c) 2011 Chelsio Communications, Inc. * All rights reserved. * Written by: Navdeep Parhar * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __T4_ADAPTER_H__ #define __T4_ADAPTER_H__ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "offload.h" #include "common/t4fw_interface.h" #define T4_FWNAME "t4fw" MALLOC_DECLARE(M_CXGBE); #define CXGBE_UNIMPLEMENTED(s) \ panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) #if defined(__i386__) || defined(__amd64__) static __inline void prefetch(void *x) { __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); } #else #define prefetch(x) #endif +#ifndef SYSCTL_ADD_UQUAD +#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD +#define sysctl_handle_64 sysctl_handle_quad +#define CTLTYPE_U64 CTLTYPE_QUAD +#endif + +#if __FreeBSD_version >= 802507 +#define T4_DEVLOG 1 +#endif + #ifdef __amd64__ /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ static __inline uint64_t t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, bus_size_t offset) { KASSERT(tag == AMD64_BUS_SPACE_MEM, ("%s: can only handle mem space", __func__)); return (*(volatile uint64_t *)(handle + offset)); } static __inline void t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, uint64_t value) { KASSERT(tag == AMD64_BUS_SPACE_MEM, ("%s: can only handle mem space", __func__)); *(volatile uint64_t *)(bsh + offset) = value; } #else static __inline uint64_t t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, bus_size_t offset) { return (uint64_t)bus_space_read_4(tag, handle, offset) + ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); } static __inline void t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, uint64_t value) { bus_space_write_4(tag, bsh, offset, value); bus_space_write_4(tag, bsh, offset + 4, value >> 32); } #endif struct adapter; typedef struct adapter adapter_t; enum { FW_IQ_QSIZE = 256, FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ + INTR_IQ_QSIZE = 64, + INTR_IQ_ESIZE = 64, /* Handles some CPLs too, do not reduce */ + CTRL_EQ_QSIZE = 128, CTRL_EQ_ESIZE = 64, RX_IQ_QSIZE = 1024, RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ RX_FL_ESIZE = 64, /* 8 64bit addresses */ #if MJUMPAGESIZE != MCLBYTES FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ #else FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ #endif TX_EQ_QSIZE = 1024, TX_EQ_ESIZE = 64, TX_SGL_SEGS = 36, TX_WR_FLITS = SGE_MAX_WR_LEN / 8 }; enum { /* adapter intr_type */ INTR_INTX = (1 << 0), INTR_MSI = (1 << 1), INTR_MSIX = (1 << 2) }; enum { /* adapter flags */ FULL_INIT_DONE = (1 << 0), FW_OK = (1 << 1), - INTR_FWD = (1 << 2), + INTR_SHARED = (1 << 2), /* one set of intrq's for all ports */ CXGBE_BUSY = (1 << 9), /* port flags */ DOOMED = (1 << 0), VI_ENABLED = (1 << 1), }; #define IS_DOOMED(pi) (pi->flags & DOOMED) #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0) #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY) #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0) #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0) struct port_info { device_t dev; struct adapter *adapter; struct ifnet *ifp; struct ifmedia media; struct mtx pi_lock; char lockname[16]; unsigned long flags; int if_flags; uint16_t viid; int16_t xact_addr_filt;/* index of exact MAC address filter */ uint16_t rss_size; /* size of VI's RSS table slice */ uint8_t lport; /* associated offload logical port */ int8_t mdio_addr; uint8_t port_type; uint8_t mod_type; uint8_t port_id; uint8_t tx_chan; /* These need to be int as they are used in sysctl */ int ntxq; /* # of tx queues */ int first_txq; /* index of first tx queue */ int nrxq; /* # of rx queues */ int first_rxq; /* index of first rx queue */ int tmr_idx; int pktc_idx; int qsize_rxq; int qsize_txq; struct link_config link_cfg; struct port_stats stats; struct taskqueue *tq; struct callout tick; struct sysctl_ctx_list ctx; /* lives from ifconfig up to down */ struct sysctl_oid *oid_rxq; struct sysctl_oid *oid_txq; uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ }; struct fl_sdesc { struct mbuf *m; bus_dmamap_t map; caddr_t cl; uint8_t tag_idx; /* the sc->fl_tag this map comes from */ #ifdef INVARIANTS __be64 ba_tag; #endif }; struct tx_desc { __be64 flit[8]; }; struct tx_map { struct mbuf *m; bus_dmamap_t map; }; struct tx_sdesc { uint8_t desc_used; /* # of hardware descriptors used by the WR */ uint8_t credits; /* NIC txq: # of frames sent out in the WR */ }; typedef void (iq_intr_handler_t)(void *); enum { /* iq flags */ IQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ IQ_STARTED = (1 << 2), /* started */ /* iq state */ IQS_DISABLED = 0, IQS_BUSY = 1, IQS_IDLE = 2, }; /* * Ingress Queue: T4 is producer, driver is consumer. */ struct sge_iq { bus_dma_tag_t desc_tag; bus_dmamap_t desc_map; bus_addr_t ba; /* bus address of descriptor ring */ char lockname[16]; uint32_t flags; uint16_t abs_id; /* absolute SGE id for the iq */ int8_t intr_pktc_idx; /* packet count threshold index */ int8_t pad0; iq_intr_handler_t *handler; __be64 *desc; /* KVA of descriptor ring */ volatile uint32_t state; struct adapter *adapter; const __be64 *cdesc; /* current descriptor */ uint8_t gen; /* generation bit */ uint8_t intr_params; /* interrupt holdoff parameters */ uint8_t intr_next; /* holdoff for next interrupt */ uint8_t esize; /* size (bytes) of each entry in the queue */ uint16_t qsize; /* size (# of entries) of the queue */ uint16_t cidx; /* consumer index */ uint16_t cntxt_id; /* SGE context id for the iq */ }; enum { /* eq flags */ EQ_ALLOCATED = (1 << 1), /* firmware resources allocated */ EQ_STARTED = (1 << 2), /* started */ EQ_CRFLUSHED = (1 << 3), /* expecting an update from SGE */ }; /* * Egress Queue: driver is producer, T4 is consumer. * * Note: A free list is an egress queue (driver produces the buffers and T4 * consumes them) but it's special enough to have its own struct (see sge_fl). */ struct sge_eq { bus_dma_tag_t desc_tag; bus_dmamap_t desc_map; char lockname[16]; unsigned int flags; struct mtx eq_lock; struct tx_desc *desc; /* KVA of descriptor ring */ bus_addr_t ba; /* bus address of descriptor ring */ struct sge_qstat *spg; /* status page, for convenience */ uint16_t cap; /* max # of desc, for convenience */ uint16_t avail; /* available descriptors, for convenience */ uint16_t qsize; /* size (# of entries) of the queue */ uint16_t cidx; /* consumer idx (desc idx) */ uint16_t pidx; /* producer idx (desc idx) */ uint16_t pending; /* # of descriptors used since last doorbell */ uint16_t iqid; /* iq that gets egr_update for the eq */ uint32_t cntxt_id; /* SGE context id for the eq */ }; struct sge_fl { bus_dma_tag_t desc_tag; bus_dmamap_t desc_map; bus_dma_tag_t tag[FL_BUF_SIZES]; uint8_t tag_idx; struct mtx fl_lock; char lockname[16]; __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ bus_addr_t ba; /* bus address of descriptor ring */ struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ uint32_t cap; /* max # of buffers, for convenience */ uint16_t qsize; /* size (# of entries) of the queue */ uint16_t cntxt_id; /* SGE context id for the freelist */ uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ uint32_t needed; /* # of buffers needed to fill up fl. */ uint32_t pending; /* # of bufs allocated since last doorbell */ unsigned int dmamap_failed; }; /* txq: SGE egress queue + what's needed for Ethernet NIC */ struct sge_txq { struct sge_eq eq; /* MUST be first */ struct ifnet *ifp; /* the interface this txq belongs to */ bus_dma_tag_t tx_tag; /* tag for transmit buffers */ struct buf_ring *br; /* tx buffer ring */ struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ struct mbuf *m; /* held up due to temporary resource shortage */ struct task resume_tx; /* DMA maps used for tx */ struct tx_map *maps; uint32_t map_total; /* # of DMA maps */ uint32_t map_pidx; /* next map to be used */ uint32_t map_cidx; /* reclaimed up to this index */ uint32_t map_avail; /* # of available maps */ /* stats for common events first */ uint64_t txcsum; /* # of times hardware assisted with checksum */ uint64_t tso_wrs; /* # of IPv4 TSO work requests */ uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ uint64_t imm_wrs; /* # of work requests with immediate data */ uint64_t sgl_wrs; /* # of work requests with direct SGL */ uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ uint64_t txpkts_wrs; /* # of coalesced tx work requests */ uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ /* stats for not-that-common events */ uint32_t no_dmamap; /* no DMA map to load the mbuf */ uint32_t no_desc; /* out of hardware descriptors */ uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for txq */ } __aligned(CACHE_LINE_SIZE); enum { RXQ_LRO_ENABLED = (1 << 0) }; /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ struct sge_rxq { struct sge_iq iq; /* MUST be first */ struct sge_fl fl; struct ifnet *ifp; /* the interface this rxq belongs to */ unsigned int flags; #ifdef INET struct lro_ctrl lro; /* LRO state */ #endif /* stats for common events first */ uint64_t rxcsum; /* # of times hardware assisted with checksum */ uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ /* stats for not-that-common events */ } __aligned(CACHE_LINE_SIZE); /* ctrlq: SGE egress queue + stats for control queue */ struct sge_ctrlq { struct sge_eq eq; /* MUST be first */ /* stats for common events first */ - uint64_t total_wrs; /* # of work requests sent down this queue */ /* stats for not-that-common events */ uint32_t no_desc; /* out of hardware descriptors */ - uint32_t too_long; /* WR longer than hardware max */ } __aligned(CACHE_LINE_SIZE); struct sge { uint16_t timer_val[SGE_NTIMERS]; uint8_t counter_val[SGE_NCOUNTERS]; + int fl_starve_threshold; int nrxq; /* total rx queues (all ports and the rest) */ int ntxq; /* total tx queues (all ports and the rest) */ int niq; /* total ingress queues */ int neq; /* total egress queues */ struct sge_iq fwq; /* Firmware event queue */ struct sge_ctrlq *ctrlq;/* Control queues */ - struct sge_iq *fiq; /* Forwarded interrupt queues (INTR_FWD) */ + struct sge_iq *intrq; /* Interrupt queues */ struct sge_txq *txq; /* NIC tx queues */ struct sge_rxq *rxq; /* NIC rx queues */ uint16_t iq_start; int eq_start; struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ }; struct adapter { device_t dev; struct cdev *cdev; /* PCIe register resources */ int regs_rid; struct resource *regs_res; int msix_rid; struct resource *msix_res; bus_space_handle_t bh; bus_space_tag_t bt; bus_size_t mmio_len; unsigned int pf; unsigned int mbox; /* Interrupt information */ int intr_type; int intr_count; struct irq { struct resource *res; int rid; void *tag; } *irq; bus_dma_tag_t dmat; /* Parent DMA tag */ struct sge sge; struct port_info *port[MAX_NPORTS]; uint8_t chan_map[NCHAN]; + struct l2t_data *l2t; /* L2 table */ struct tid_info tids; int registered_device_map; int open_device_map; int flags; char fw_version[32]; struct adapter_params params; struct t4_virt_res vres; struct sysctl_ctx_list ctx; /* from first_port_up to last_port_down */ + struct sysctl_oid *oid_fwq; struct sysctl_oid *oid_ctrlq; + struct sysctl_oid *oid_intrq; struct mtx sc_lock; char lockname[16]; }; #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) #define for_each_txq(pi, iter, txq) \ txq = &pi->adapter->sge.txq[pi->first_txq]; \ for (iter = 0; iter < pi->ntxq; ++iter, ++txq) #define for_each_rxq(pi, iter, rxq) \ rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \ for (iter = 0; iter < pi->nrxq; ++iter, ++rxq) -#define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1) +/* One for errors, one for firmware events */ +#define T4_EXTRA_INTR 2 +#define NINTRQ(sc) ((sc)->intr_count > T4_EXTRA_INTR ? \ + (sc)->intr_count - T4_EXTRA_INTR : 1) static inline uint32_t t4_read_reg(struct adapter *sc, uint32_t reg) { return bus_space_read_4(sc->bt, sc->bh, reg); } static inline void t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) { bus_space_write_4(sc->bt, sc->bh, reg, val); } static inline uint64_t t4_read_reg64(struct adapter *sc, uint32_t reg) { return t4_bus_space_read_8(sc->bt, sc->bh, reg); } static inline void t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) { t4_bus_space_write_8(sc->bt, sc->bh, reg, val); } static inline void t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) { *val = pci_read_config(sc->dev, reg, 1); } static inline void t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) { pci_write_config(sc->dev, reg, val, 1); } static inline void t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) { *val = pci_read_config(sc->dev, reg, 2); } static inline void t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) { pci_write_config(sc->dev, reg, val, 2); } static inline void t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) { *val = pci_read_config(sc->dev, reg, 4); } static inline void t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) { pci_write_config(sc->dev, reg, val, 4); } static inline struct port_info * adap2pinfo(struct adapter *sc, int idx) { return (sc->port[idx]); } static inline void t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) { bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); } static inline bool is_10G_port(const struct port_info *pi) { return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); } /* t4_main.c */ void cxgbe_txq_start(void *, int); int t4_os_find_pci_capability(struct adapter *, int); int t4_os_pci_save_state(struct adapter *); int t4_os_pci_restore_state(struct adapter *); void t4_os_portmod_changed(const struct adapter *, int); void t4_os_link_changed(struct adapter *, int, int); /* t4_sge.c */ void t4_sge_modload(void); void t4_sge_init(struct adapter *); int t4_create_dma_tag(struct adapter *); int t4_destroy_dma_tag(struct adapter *); int t4_setup_adapter_queues(struct adapter *); int t4_teardown_adapter_queues(struct adapter *); int t4_setup_eth_queues(struct port_info *); int t4_teardown_eth_queues(struct port_info *); void t4_intr_all(void *); -void t4_intr_fwd(void *); +void t4_intr(void *); void t4_intr_err(void *); void t4_intr_evt(void *); -void t4_intr_data(void *); -void t4_evt_rx(void *); -void t4_eth_rx(void *); int t4_mgmt_tx(struct adapter *, struct mbuf *); int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); void t4_update_fl_bufsize(struct ifnet *); #endif Index: stable/8/sys/dev/cxgbe/common/common.h =================================================================== --- stable/8/sys/dev/cxgbe/common/common.h (revision 222793) +++ stable/8/sys/dev/cxgbe/common/common.h (revision 222794) @@ -1,517 +1,517 @@ /*- * Copyright (c) 2011 Chelsio Communications, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __CHELSIO_COMMON_H #define __CHELSIO_COMMON_H #include "t4_hw.h" enum { MAX_NPORTS = 4, /* max # of ports */ SERNUM_LEN = 24, /* Serial # length */ EC_LEN = 16, /* E/C length */ ID_LEN = 16, /* ID length */ }; enum { MEM_EDC0, MEM_EDC1, MEM_MC }; enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; enum { PAUSE_RX = 1 << 0, PAUSE_TX = 1 << 1, PAUSE_AUTONEG = 1 << 2 }; #define FW_VERSION_MAJOR 1 #define FW_VERSION_MINOR 3 -#define FW_VERSION_MICRO 8 +#define FW_VERSION_MICRO 10 struct port_stats { u64 tx_octets; /* total # of octets in good frames */ u64 tx_frames; /* all good frames */ u64 tx_bcast_frames; /* all broadcast frames */ u64 tx_mcast_frames; /* all multicast frames */ u64 tx_ucast_frames; /* all unicast frames */ u64 tx_error_frames; /* all error frames */ u64 tx_frames_64; /* # of Tx frames in a particular range */ u64 tx_frames_65_127; u64 tx_frames_128_255; u64 tx_frames_256_511; u64 tx_frames_512_1023; u64 tx_frames_1024_1518; u64 tx_frames_1519_max; u64 tx_drop; /* # of dropped Tx frames */ u64 tx_pause; /* # of transmitted pause frames */ u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ u64 rx_octets; /* total # of octets in good frames */ u64 rx_frames; /* all good frames */ u64 rx_bcast_frames; /* all broadcast frames */ u64 rx_mcast_frames; /* all multicast frames */ u64 rx_ucast_frames; /* all unicast frames */ u64 rx_too_long; /* # of frames exceeding MTU */ u64 rx_jabber; /* # of jabber frames */ u64 rx_fcs_err; /* # of received frames with bad FCS */ u64 rx_len_err; /* # of received frames with length error */ u64 rx_symbol_err; /* symbol errors */ u64 rx_runt; /* # of short frames */ u64 rx_frames_64; /* # of Rx frames in a particular range */ u64 rx_frames_65_127; u64 rx_frames_128_255; u64 rx_frames_256_511; u64 rx_frames_512_1023; u64 rx_frames_1024_1518; u64 rx_frames_1519_max; u64 rx_pause; /* # of received pause frames */ u64 rx_ppp0; /* # of received PPP prio 0 frames */ u64 rx_ppp1; /* # of received PPP prio 1 frames */ u64 rx_ppp2; /* # of received PPP prio 2 frames */ u64 rx_ppp3; /* # of received PPP prio 3 frames */ u64 rx_ppp4; /* # of received PPP prio 4 frames */ u64 rx_ppp5; /* # of received PPP prio 5 frames */ u64 rx_ppp6; /* # of received PPP prio 6 frames */ u64 rx_ppp7; /* # of received PPP prio 7 frames */ u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ u64 rx_trunc0; /* buffer-group 0 truncated packets */ u64 rx_trunc1; /* buffer-group 1 truncated packets */ u64 rx_trunc2; /* buffer-group 2 truncated packets */ u64 rx_trunc3; /* buffer-group 3 truncated packets */ }; struct lb_port_stats { u64 octets; u64 frames; u64 bcast_frames; u64 mcast_frames; u64 ucast_frames; u64 error_frames; u64 frames_64; u64 frames_65_127; u64 frames_128_255; u64 frames_256_511; u64 frames_512_1023; u64 frames_1024_1518; u64 frames_1519_max; u64 drop; u64 ovflow0; u64 ovflow1; u64 ovflow2; u64 ovflow3; u64 trunc0; u64 trunc1; u64 trunc2; u64 trunc3; }; struct tp_tcp_stats { u32 tcpOutRsts; u64 tcpInSegs; u64 tcpOutSegs; u64 tcpRetransSegs; }; struct tp_usm_stats { u32 frames; u32 drops; u64 octets; }; struct tp_fcoe_stats { u32 framesDDP; u32 framesDrop; u64 octetsDDP; }; struct tp_err_stats { u32 macInErrs[4]; u32 hdrInErrs[4]; u32 tcpInErrs[4]; u32 tnlCongDrops[4]; u32 ofldChanDrops[4]; u32 tnlTxDrops[4]; u32 ofldVlanDrops[4]; u32 tcp6InErrs[4]; u32 ofldNoNeigh; u32 ofldCongDefer; }; struct tp_proxy_stats { u32 proxy[4]; }; struct tp_cpl_stats { u32 req[4]; u32 rsp[4]; u32 tx_err[4]; }; struct tp_rdma_stats { u32 rqe_dfr_mod; u32 rqe_dfr_pkt; }; struct tp_params { unsigned int ntxchan; /* # of Tx channels */ unsigned int tre; /* log2 of core clocks per TP tick */ unsigned int dack_re; /* DACK timer resolution */ unsigned int la_mask; /* what events are recorded by TP LA */ unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ }; struct vpd_params { unsigned int cclk; u8 ec[EC_LEN + 1]; u8 sn[SERNUM_LEN + 1]; u8 id[ID_LEN + 1]; }; struct pci_params { unsigned int vpd_cap_addr; unsigned char speed; unsigned char width; }; /* * Firmware device log. */ struct devlog_params { u32 memtype; /* which memory (EDC0, EDC1, MC) */ u32 start; /* start of log in firmware memory */ u32 size; /* size of log */ }; struct adapter_params { struct tp_params tp; struct vpd_params vpd; struct pci_params pci; struct devlog_params devlog; unsigned int sf_size; /* serial flash size in bytes */ unsigned int sf_nsec; /* # of flash sectors */ unsigned int fw_vers; unsigned int tp_vers; u8 api_vers[7]; unsigned short mtus[NMTUS]; unsigned short a_wnd[NCCTRL_WIN]; unsigned short b_wnd[NCCTRL_WIN]; unsigned int mc_size; /* MC memory size */ unsigned int nfilters; /* size of filter region */ unsigned int cim_la_size; unsigned int nports; /* # of ethernet ports */ unsigned int portvec; unsigned int rev; /* chip revision */ unsigned int offload; unsigned int ofldq_wr_cred; }; enum { /* chip revisions */ T4_REV_A = 0, }; struct trace_params { u32 data[TRACE_LEN / 4]; u32 mask[TRACE_LEN / 4]; unsigned short snap_len; unsigned short min_len; unsigned char skip_ofst; unsigned char skip_len; unsigned char invert; unsigned char port; }; struct link_config { unsigned short supported; /* link capabilities */ unsigned short advertising; /* advertised capabilities */ unsigned short requested_speed; /* speed user has requested */ unsigned short speed; /* actual link speed */ unsigned char requested_fc; /* flow control user has requested */ unsigned char fc; /* actual link flow control */ unsigned char autoneg; /* autonegotiating? */ unsigned char link_ok; /* link up? */ }; #include "adapter.h" #ifndef PCI_VENDOR_ID_CHELSIO # define PCI_VENDOR_ID_CHELSIO 0x1425 #endif #define for_each_port(adapter, iter) \ for (iter = 0; iter < (adapter)->params.nports; ++iter) static inline int is_offload(const struct adapter *adap) { return adap->params.offload; } static inline unsigned int core_ticks_per_usec(const struct adapter *adap) { return adap->params.vpd.cclk / 1000; } static inline unsigned int us_to_core_ticks(const struct adapter *adap, unsigned int us) { return (us * adap->params.vpd.cclk) / 1000; } static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, unsigned int ticks) { return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); } void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, int polarity, int attempts, int delay, u32 *valp); static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, int polarity, int attempts, int delay) { return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, delay, NULL); } int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl, bool sleep_ok); static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl) { return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); } static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, int size, void *rpl) { return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); } void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, unsigned int data_reg, u32 *vals, unsigned int nregs, unsigned int start_idx); void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, unsigned int data_reg, const u32 *vals, unsigned int nregs, unsigned int start_idx); struct fw_filter_wr; void t4_intr_enable(struct adapter *adapter); void t4_intr_disable(struct adapter *adapter); void t4_intr_clear(struct adapter *adapter); int t4_slow_intr_handler(struct adapter *adapter); int t4_hash_mac_addr(const u8 *addr); int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, struct link_config *lc); int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); int t4_seeprom_wp(struct adapter *adapter, int enable); int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented); int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); int t4_get_fw_version(struct adapter *adapter, u32 *vers); int t4_get_tp_version(struct adapter *adapter, u32 *vers); int t4_check_fw_version(struct adapter *adapter); int t4_init_hw(struct adapter *adapter, u32 fw_params); int t4_prep_adapter(struct adapter *adapter); int t4_port_init(struct port_info *p, int mbox, int pf, int vf); int t4_reinit_adapter(struct adapter *adap); void t4_fatal_err(struct adapter *adapter); int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, int filter_index, int enable); void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, int filter_index, int *enabled); int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, int start, int n, const u16 *rspq, unsigned int nrspq); int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, unsigned int flags); int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, unsigned int flags, unsigned int defq); int t4_read_rss(struct adapter *adapter, u16 *entries); void t4_read_rss_key(struct adapter *adapter, u32 *key); void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp); void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val); void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, u32 *vfl, u32 *vfh); void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, u32 vfl, u32 vfh); u32 t4_read_rss_pf_map(struct adapter *adapter); void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap); u32 t4_read_rss_pf_mask(struct adapter *adapter); void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask); int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, unsigned int *valp); int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, const unsigned int *valp); int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, unsigned int *valp); int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity); int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, __be32 *data); void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); void t4_clr_port_stats(struct adapter *adap, int idx); void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, unsigned int *ipg); void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, unsigned int mask, unsigned int val); void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st); void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, struct tp_tcp_stats *v6); void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, struct tp_fcoe_stats *st); void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, const unsigned short *alpha, const unsigned short *beta); void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, unsigned int start, unsigned int n); void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map); void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, u64 mask0, u64 mask1, unsigned int crc, bool enable); int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, enum dev_master master, enum dev_state *state); int t4_fw_bye(struct adapter *adap, unsigned int mbox); int t4_early_init(struct adapter *adap, unsigned int mbox); int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, u32 *val); int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, const u32 *val); int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, unsigned int rxqi, unsigned int rxq, unsigned int tc, unsigned int vi, unsigned int cmask, unsigned int pmask, unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, unsigned int *rss_size); int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int viid); int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, int mtu, int promisc, int all_multi, int bcast, int vlanex, bool sleep_ok); int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, bool free, unsigned int naddr, const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok); int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int idx, const u8 *addr, bool persist, bool add_smt); int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, bool ucast, u64 vec, bool sleep_ok); int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, bool rx_en, bool tx_en); int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, unsigned int nblinks); int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, unsigned int mmd, unsigned int reg, unsigned int *valp); int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, unsigned int mmd, unsigned int reg, unsigned int val); int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, unsigned int pf, unsigned int vf, unsigned int iqid, unsigned int fl0id, unsigned int fl1id); int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int iqtype, unsigned int iqid, unsigned int fl0id, unsigned int fl1id); int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid); int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid); int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int eqid); int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, enum ctxt_type ctype, u32 *data); int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, u32 *data); int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); #endif /* __CHELSIO_COMMON_H */ Index: stable/8/sys/dev/cxgbe/common/jhash.h =================================================================== --- stable/8/sys/dev/cxgbe/common/jhash.h (nonexistent) +++ stable/8/sys/dev/cxgbe/common/jhash.h (revision 222794) @@ -0,0 +1,140 @@ +#ifndef _JHASH_H +#define _JHASH_H + +/* jhash.h: Jenkins hash support. + * + * Copyright (C) 1996 Bob Jenkins (bob_jenkins@burtleburtle.net) + * + * http://burtleburtle.net/bob/hash/ + * + * These are the credits from Bob's sources: + * + * lookup2.c, by Bob Jenkins, December 1996, Public Domain. + * hash(), hash2(), hash3, and mix() are externally useful functions. + * Routines to test the hash are included if SELF_TEST is defined. + * You can use this free for any purpose. It has no warranty. + * + * $FreeBSD$ + */ + +/* NOTE: Arguments are modified. */ +#define __jhash_mix(a, b, c) \ +{ \ + a -= b; a -= c; a ^= (c>>13); \ + b -= c; b -= a; b ^= (a<<8); \ + c -= a; c -= b; c ^= (b>>13); \ + a -= b; a -= c; a ^= (c>>12); \ + b -= c; b -= a; b ^= (a<<16); \ + c -= a; c -= b; c ^= (b>>5); \ + a -= b; a -= c; a ^= (c>>3); \ + b -= c; b -= a; b ^= (a<<10); \ + c -= a; c -= b; c ^= (b>>15); \ +} + +/* The golden ration: an arbitrary value */ +#define JHASH_GOLDEN_RATIO 0x9e3779b9 + +/* The most generic version, hashes an arbitrary sequence + * of bytes. No alignment or length assumptions are made about + * the input key. + */ +static inline u32 jhash(const void *key, u32 length, u32 initval) +{ + u32 a, b, c, len; + const u8 *k = key; + + len = length; + a = b = JHASH_GOLDEN_RATIO; + c = initval; + + while (len >= 12) { + a += (k[0] +((u32)k[1]<<8) +((u32)k[2]<<16) +((u32)k[3]<<24)); + b += (k[4] +((u32)k[5]<<8) +((u32)k[6]<<16) +((u32)k[7]<<24)); + c += (k[8] +((u32)k[9]<<8) +((u32)k[10]<<16)+((u32)k[11]<<24)); + + __jhash_mix(a,b,c); + + k += 12; + len -= 12; + } + + c += length; + switch (len) { + case 11: c += ((u32)k[10]<<24); + case 10: c += ((u32)k[9]<<16); + case 9 : c += ((u32)k[8]<<8); + case 8 : b += ((u32)k[7]<<24); + case 7 : b += ((u32)k[6]<<16); + case 6 : b += ((u32)k[5]<<8); + case 5 : b += k[4]; + case 4 : a += ((u32)k[3]<<24); + case 3 : a += ((u32)k[2]<<16); + case 2 : a += ((u32)k[1]<<8); + case 1 : a += k[0]; + }; + + __jhash_mix(a,b,c); + + return c; +} + +/* A special optimized version that handles 1 or more of u32s. + * The length parameter here is the number of u32s in the key. + */ +static inline u32 jhash2(u32 *k, u32 length, u32 initval) +{ + u32 a, b, c, len; + + a = b = JHASH_GOLDEN_RATIO; + c = initval; + len = length; + + while (len >= 3) { + a += k[0]; + b += k[1]; + c += k[2]; + __jhash_mix(a, b, c); + k += 3; len -= 3; + } + + c += length * 4; + + switch (len) { + case 2 : b += k[1]; + case 1 : a += k[0]; + }; + + __jhash_mix(a,b,c); + + return c; +} + + +/* A special ultra-optimized versions that knows they are hashing exactly + * 3, 2 or 1 word(s). + * + * NOTE: In partilar the "c += length; __jhash_mix(a,b,c);" normally + * done at the end is not done here. + */ +static inline u32 jhash_3words(u32 a, u32 b, u32 c, u32 initval) +{ + a += JHASH_GOLDEN_RATIO; + b += JHASH_GOLDEN_RATIO; + c += initval; + + __jhash_mix(a, b, c); + + return c; +} + +static inline u32 jhash_2words(u32 a, u32 b, u32 initval) +{ + return jhash_3words(a, b, 0, initval); +} + +static inline u32 jhash_1word(u32 a, u32 initval) +{ + return jhash_3words(a, 0, 0, initval); +} + +#endif /* _JHASH_H */ Property changes on: stable/8/sys/dev/cxgbe/common/jhash.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/8/sys/dev/cxgbe/common/t4fw_interface.h =================================================================== --- stable/8/sys/dev/cxgbe/common/t4fw_interface.h (revision 222793) +++ stable/8/sys/dev/cxgbe/common/t4fw_interface.h (revision 222794) @@ -1,5396 +1,5625 @@ /*- * Copyright (c) 2011 Chelsio Communications, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef _T4FW_INTERFACE_H_ #define _T4FW_INTERFACE_H_ /****************************************************************************** * R E T U R N V A L U E S ********************************/ enum fw_retval { FW_SUCCESS = 0, /* completed sucessfully */ FW_EPERM = 1, /* operation not permitted */ FW_EIO = 5, /* input/output error; hw bad */ FW_ENOEXEC = 8, /* Exec format error; inv microcode */ FW_EAGAIN = 11, /* try again */ FW_ENOMEM = 12, /* out of memory */ FW_EFAULT = 14, /* bad address; fw bad */ FW_EBUSY = 16, /* resource busy */ + FW_EEXIST = 17, /* File exists */ FW_EINVAL = 22, /* invalid argument */ FW_ENOSYS = 38, /* functionality not implemented */ FW_EPROTO = 71, /* protocol error */ FW_ETIMEDOUT = 110, /* timeout */ FW_EINPROGRESS = 115, /* fw internal */ FW_SCSI_ABORT_REQUESTED = 128, /* */ FW_SCSI_ABORT_TIMEDOUT = 129, /* */ FW_SCSI_ABORTED = 130, /* */ FW_SCSI_CLOSE_REQUESTED = 131, /* */ FW_ERR_LINK_DOWN = 132, /* */ FW_RDEV_NOT_READY = 133, /* */ FW_ERR_RDEV_LOST = 134, /* */ FW_ERR_RDEV_LOGO = 135, /* */ FW_FCOE_NO_XCHG = 136, /* */ FW_SCSI_RSP_ERR = 137, /* */ FW_ERR_RDEV_IMPL_LOGO = 138, /* */ + FW_SCSI_UNDER_FLOW_ERR = 139, /* */ + FW_SCSI_OVER_FLOW_ERR = 140, /* */ }; /****************************************************************************** * W O R K R E Q U E S T s ********************************/ enum fw_wr_opcodes { FW_FILTER_WR = 0x02, FW_ULPTX_WR = 0x04, FW_TP_WR = 0x05, FW_ETH_TX_PKT_WR = 0x08, FW_ETH_TX_PKTS_WR = 0x09, FW_EQ_FLUSH_WR = 0x1b, FW_FLOWC_WR = 0x0a, FW_OFLD_TX_DATA_WR = 0x0b, FW_CMD_WR = 0x10, FW_ETH_TX_PKT_VM_WR = 0x11, FW_RI_RES_WR = 0x0c, FW_RI_RDMA_WRITE_WR = 0x14, FW_RI_SEND_WR = 0x15, FW_RI_RDMA_READ_WR = 0x16, FW_RI_RECV_WR = 0x17, FW_RI_BIND_MW_WR = 0x18, FW_RI_FR_NSMR_WR = 0x19, FW_RI_INV_LSTAG_WR = 0x1a, FW_RI_WR = 0x0d, - FW_LASTC2E_WR = 0x4a + FW_ISCSI_NODE_WR = 0x4a, + FW_LASTC2E_WR = 0x4b }; /* * Generic work request header flit0 */ struct fw_wr_hdr { __be32 hi; __be32 lo; }; /* work request opcode (hi) */ #define S_FW_WR_OP 24 #define M_FW_WR_OP 0xff #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ #define S_FW_WR_ATOMIC 23 #define M_FW_WR_ATOMIC 0x1 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) #define G_FW_WR_ATOMIC(x) \ (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) /* flush flag (hi) - firmware flushes flushable work request buffered * in the flow context. */ #define S_FW_WR_FLUSH 22 #define M_FW_WR_FLUSH 0x1 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) #define G_FW_WR_FLUSH(x) \ (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) /* completion flag (hi) - firmware generates a cpl_fw6_ack */ #define S_FW_WR_COMPL 21 #define M_FW_WR_COMPL 0x1 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) #define G_FW_WR_COMPL(x) \ (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) /* work request immediate data lengh (hi) */ #define S_FW_WR_IMMDLEN 0 #define M_FW_WR_IMMDLEN 0xff #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) #define G_FW_WR_IMMDLEN(x) \ (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) /* egress queue status update to associated ingress queue entry (lo) */ #define S_FW_WR_EQUIQ 31 #define M_FW_WR_EQUIQ 0x1 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) /* egress queue status update to egress queue status entry (lo) */ #define S_FW_WR_EQUEQ 30 #define M_FW_WR_EQUEQ 0x1 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) /* flow context identifier (lo) */ #define S_FW_WR_FLOWID 8 #define M_FW_WR_FLOWID 0xfffff #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) /* length in units of 16-bytes (lo) */ #define S_FW_WR_LEN16 0 #define M_FW_WR_LEN16 0xff #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) /* valid filter configurations for compressed tuple * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, * OV - Outer VLAN/VNIC_ID, */ #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B #define HW_TPL_FR_MT_M_OV_P_FC 0x387 #define HW_TPL_FR_MT_E_PR_T 0x370 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 #define HW_TPL_FR_MT_E_T_P_FC 0X353 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B #define HW_TPL_FR_MT_T_OV_P_FC 0X317 #define HW_TPL_FR_M_E_PR_FC 0X2E1 #define HW_TPL_FR_M_E_T_FC 0X2D1 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 #define HW_TPL_FR_M_T_IV_FC 0X299 #define HW_TPL_FR_M_T_OV_FC 0X295 #define HW_TPL_FR_E_PR_T_P 0X272 #define HW_TPL_FR_E_PR_T_FC 0X271 #define HW_TPL_FR_E_IV_FC 0X249 #define HW_TPL_FR_E_OV_FC 0X245 #define HW_TPL_FR_PR_T_IV_FC 0X239 #define HW_TPL_FR_PR_T_OV_FC 0X235 #define HW_TPL_FR_IV_OV_FC 0X20D #define HW_TPL_MT_M_E_PR 0X1E0 #define HW_TPL_MT_M_E_T 0X1D0 #define HW_TPL_MT_E_PR_T_FC 0X171 #define HW_TPL_MT_E_IV 0X148 #define HW_TPL_MT_E_OV 0X144 #define HW_TPL_MT_PR_T_IV 0X138 #define HW_TPL_MT_PR_T_OV 0X134 #define HW_TPL_M_E_PR_P 0X0E2 #define HW_TPL_M_E_T_P 0X0D2 #define HW_TPL_E_PR_T_P_FC 0X073 #define HW_TPL_E_IV_P 0X04A #define HW_TPL_E_OV_P 0X046 #define HW_TPL_PR_T_IV_P 0X03A #define HW_TPL_PR_T_OV_P 0X036 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ enum fw_filter_wr_cookie { FW_FILTER_WR_SUCCESS, FW_FILTER_WR_FLT_ADDED, FW_FILTER_WR_FLT_DELETED, FW_FILTER_WR_SMT_TBL_FULL, FW_FILTER_WR_EINVAL, }; struct fw_filter_wr { __be32 op_pkd; __be32 len16_pkd; __be64 r3; __be32 tid_to_iq; __be32 del_filter_to_l2tix; __be16 ethtype; __be16 ethtypem; __u8 frag_to_ovlan_vldm; __u8 smac_sel; __be16 rx_chan_rx_rpl_iq; __be32 maci_to_matchtypem; __u8 ptcl; __u8 ptclm; __u8 ttyp; __u8 ttypm; __be16 ivlan; __be16 ivlanm; __be16 ovlan; __be16 ovlanm; __u8 lip[16]; __u8 lipm[16]; __u8 fip[16]; __u8 fipm[16]; __be16 lp; __be16 lpm; __be16 fp; __be16 fpm; __be16 r7; __u8 sma[6]; }; #define S_FW_FILTER_WR_TID 12 #define M_FW_FILTER_WR_TID 0xfffff #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) #define G_FW_FILTER_WR_TID(x) \ (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) #define S_FW_FILTER_WR_RQTYPE 11 #define M_FW_FILTER_WR_RQTYPE 0x1 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) #define G_FW_FILTER_WR_RQTYPE(x) \ (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) #define S_FW_FILTER_WR_NOREPLY 10 #define M_FW_FILTER_WR_NOREPLY 0x1 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) #define G_FW_FILTER_WR_NOREPLY(x) \ (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) #define S_FW_FILTER_WR_IQ 0 #define M_FW_FILTER_WR_IQ 0x3ff #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) #define G_FW_FILTER_WR_IQ(x) \ (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) #define S_FW_FILTER_WR_DEL_FILTER 31 #define M_FW_FILTER_WR_DEL_FILTER 0x1 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) #define G_FW_FILTER_WR_DEL_FILTER(x) \ (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) #define S_FW_FILTER_WR_RPTTID 25 #define M_FW_FILTER_WR_RPTTID 0x1 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) #define G_FW_FILTER_WR_RPTTID(x) \ (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) #define S_FW_FILTER_WR_DROP 24 #define M_FW_FILTER_WR_DROP 0x1 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) #define G_FW_FILTER_WR_DROP(x) \ (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) #define S_FW_FILTER_WR_DIRSTEER 23 #define M_FW_FILTER_WR_DIRSTEER 0x1 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) #define G_FW_FILTER_WR_DIRSTEER(x) \ (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) #define S_FW_FILTER_WR_MASKHASH 22 #define M_FW_FILTER_WR_MASKHASH 0x1 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) #define G_FW_FILTER_WR_MASKHASH(x) \ (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) #define S_FW_FILTER_WR_DIRSTEERHASH 21 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) #define S_FW_FILTER_WR_LPBK 20 #define M_FW_FILTER_WR_LPBK 0x1 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) #define G_FW_FILTER_WR_LPBK(x) \ (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) #define S_FW_FILTER_WR_DMAC 19 #define M_FW_FILTER_WR_DMAC 0x1 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) #define G_FW_FILTER_WR_DMAC(x) \ (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) #define S_FW_FILTER_WR_SMAC 18 #define M_FW_FILTER_WR_SMAC 0x1 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) #define G_FW_FILTER_WR_SMAC(x) \ (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) #define S_FW_FILTER_WR_INSVLAN 17 #define M_FW_FILTER_WR_INSVLAN 0x1 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) #define G_FW_FILTER_WR_INSVLAN(x) \ (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) #define S_FW_FILTER_WR_RMVLAN 16 #define M_FW_FILTER_WR_RMVLAN 0x1 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) #define G_FW_FILTER_WR_RMVLAN(x) \ (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) #define S_FW_FILTER_WR_HITCNTS 15 #define M_FW_FILTER_WR_HITCNTS 0x1 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) #define G_FW_FILTER_WR_HITCNTS(x) \ (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) #define S_FW_FILTER_WR_TXCHAN 13 #define M_FW_FILTER_WR_TXCHAN 0x3 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) #define G_FW_FILTER_WR_TXCHAN(x) \ (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) #define S_FW_FILTER_WR_PRIO 12 #define M_FW_FILTER_WR_PRIO 0x1 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) #define G_FW_FILTER_WR_PRIO(x) \ (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) #define S_FW_FILTER_WR_L2TIX 0 #define M_FW_FILTER_WR_L2TIX 0xfff #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) #define G_FW_FILTER_WR_L2TIX(x) \ (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) #define S_FW_FILTER_WR_FRAG 7 #define M_FW_FILTER_WR_FRAG 0x1 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) #define G_FW_FILTER_WR_FRAG(x) \ (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) #define S_FW_FILTER_WR_FRAGM 6 #define M_FW_FILTER_WR_FRAGM 0x1 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) #define G_FW_FILTER_WR_FRAGM(x) \ (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) #define S_FW_FILTER_WR_IVLAN_VLD 5 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) #define G_FW_FILTER_WR_IVLAN_VLD(x) \ (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) #define S_FW_FILTER_WR_OVLAN_VLD 4 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) #define G_FW_FILTER_WR_OVLAN_VLD(x) \ (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) #define S_FW_FILTER_WR_IVLAN_VLDM 3 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) #define S_FW_FILTER_WR_OVLAN_VLDM 2 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) #define S_FW_FILTER_WR_RX_CHAN 15 #define M_FW_FILTER_WR_RX_CHAN 0x1 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) #define G_FW_FILTER_WR_RX_CHAN(x) \ (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) #define S_FW_FILTER_WR_RX_RPL_IQ 0 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) #define S_FW_FILTER_WR_MACI 23 #define M_FW_FILTER_WR_MACI 0x1ff #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) #define G_FW_FILTER_WR_MACI(x) \ (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) #define S_FW_FILTER_WR_MACIM 14 #define M_FW_FILTER_WR_MACIM 0x1ff #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) #define G_FW_FILTER_WR_MACIM(x) \ (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) #define S_FW_FILTER_WR_FCOE 13 #define M_FW_FILTER_WR_FCOE 0x1 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) #define G_FW_FILTER_WR_FCOE(x) \ (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) #define S_FW_FILTER_WR_FCOEM 12 #define M_FW_FILTER_WR_FCOEM 0x1 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) #define G_FW_FILTER_WR_FCOEM(x) \ (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) #define S_FW_FILTER_WR_PORT 9 #define M_FW_FILTER_WR_PORT 0x7 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) #define G_FW_FILTER_WR_PORT(x) \ (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) #define S_FW_FILTER_WR_PORTM 6 #define M_FW_FILTER_WR_PORTM 0x7 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) #define G_FW_FILTER_WR_PORTM(x) \ (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) #define S_FW_FILTER_WR_MATCHTYPE 3 #define M_FW_FILTER_WR_MATCHTYPE 0x7 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) #define G_FW_FILTER_WR_MATCHTYPE(x) \ (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) #define S_FW_FILTER_WR_MATCHTYPEM 0 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) #define G_FW_FILTER_WR_MATCHTYPEM(x) \ (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) struct fw_ulptx_wr { __be32 op_to_compl; __be32 flowid_len16; __u64 cookie; }; struct fw_tp_wr { __be32 op_to_immdlen; __be32 flowid_len16; __u64 cookie; }; struct fw_eth_tx_pkt_wr { __be32 op_immdlen; __be32 equiq_to_len16; __be64 r3; }; struct fw_eth_tx_pkts_wr { __be32 op_immdlen; __be32 equiq_to_len16; __be32 r3; __be16 plen; __u8 npkt; - __u8 r4; + __u8 type; }; struct fw_eq_flush_wr { __u8 opcode; __u8 r1[3]; __be32 equiq_to_len16; __be64 r3; }; enum fw_flowc_mnem { FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ FW_FLOWC_MNEM_CH, FW_FLOWC_MNEM_PORT, FW_FLOWC_MNEM_IQID, FW_FLOWC_MNEM_SNDNXT, FW_FLOWC_MNEM_RCVNXT, FW_FLOWC_MNEM_SNDBUF, FW_FLOWC_MNEM_MSS, FW_FLOWC_MEM_TXDATAPLEN_MAX, }; struct fw_flowc_mnemval { __u8 mnemonic; __u8 r4[3]; __be32 val; }; struct fw_flowc_wr { __be32 op_to_nparams; __be32 flowid_len16; #ifndef C99_NOT_SUPPORTED struct fw_flowc_mnemval mnemval[0]; #endif }; #define S_FW_FLOWC_WR_NPARAMS 0 #define M_FW_FLOWC_WR_NPARAMS 0xff #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) #define G_FW_FLOWC_WR_NPARAMS(x) \ (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) struct fw_ofld_tx_data_wr { __be32 op_to_immdlen; __be32 flowid_len16; __be32 plen; __be32 tunnel_to_proxy; }; #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) #define S_FW_OFLD_TX_DATA_WR_SAVE 18 #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) #define S_FW_OFLD_TX_DATA_WR_FLUSH 17 #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) #define S_FW_OFLD_TX_DATA_WR_URGENT 16 #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) #define S_FW_OFLD_TX_DATA_WR_MORE 15 #define M_FW_OFLD_TX_DATA_WR_MORE 0x1 #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) #define G_FW_OFLD_TX_DATA_WR_MORE(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) #define S_FW_OFLD_TX_DATA_WR_SHOVE 14 #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) #define S_FW_OFLD_TX_DATA_WR_PROXY 5 #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) struct fw_cmd_wr { __be32 op_dma; __be32 len16_pkd; __be64 cookie_daddr; }; #define S_FW_CMD_WR_DMA 17 #define M_FW_CMD_WR_DMA 0x1 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) struct fw_eth_tx_pkt_vm_wr { __be32 op_immdlen; __be32 equiq_to_len16; __be32 r3[2]; __u8 ethmacdst[6]; __u8 ethmacsrc[6]; __be16 ethtype; __be16 vlantci; }; /****************************************************************************** * R I W O R K R E Q U E S T s **************************************/ enum fw_ri_wr_opcode { FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ FW_RI_READ_REQ = 0x1, FW_RI_READ_RESP = 0x2, FW_RI_SEND = 0x3, FW_RI_SEND_WITH_INV = 0x4, FW_RI_SEND_WITH_SE = 0x5, FW_RI_SEND_WITH_SE_INV = 0x6, FW_RI_TERMINATE = 0x7, FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ FW_RI_BIND_MW = 0x9, FW_RI_FAST_REGISTER = 0xa, FW_RI_LOCAL_INV = 0xb, FW_RI_QP_MODIFY = 0xc, FW_RI_BYPASS = 0xd, FW_RI_RECEIVE = 0xe, FW_RI_SGE_EC_CR_RETURN = 0xf }; enum fw_ri_wr_flags { FW_RI_COMPLETION_FLAG = 0x01, FW_RI_NOTIFICATION_FLAG = 0x02, FW_RI_SOLICITED_EVENT_FLAG = 0x04, FW_RI_READ_FENCE_FLAG = 0x08, FW_RI_LOCAL_FENCE_FLAG = 0x10, FW_RI_RDMA_READ_INVALIDATE = 0x20 }; enum fw_ri_mpa_attrs { FW_RI_MPA_RX_MARKER_ENABLE = 0x01, FW_RI_MPA_TX_MARKER_ENABLE = 0x02, FW_RI_MPA_CRC_ENABLE = 0x04, FW_RI_MPA_IETF_ENABLE = 0x08 }; enum fw_ri_qp_caps { FW_RI_QP_RDMA_READ_ENABLE = 0x01, FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, FW_RI_QP_BIND_ENABLE = 0x04, FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, FW_RI_QP_STAG0_ENABLE = 0x10, FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, }; enum fw_ri_addr_type { FW_RI_ZERO_BASED_TO = 0x00, FW_RI_VA_BASED_TO = 0x01 }; enum fw_ri_mem_perms { FW_RI_MEM_ACCESS_REM_WRITE = 0x01, FW_RI_MEM_ACCESS_REM_READ = 0x02, FW_RI_MEM_ACCESS_REM = 0x03, FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, FW_RI_MEM_ACCESS_LOCAL = 0x0C }; enum fw_ri_stag_type { FW_RI_STAG_NSMR = 0x00, FW_RI_STAG_SMR = 0x01, FW_RI_STAG_MW = 0x02, FW_RI_STAG_MW_RELAXED = 0x03 }; enum fw_ri_data_op { FW_RI_DATA_IMMD = 0x81, FW_RI_DATA_DSGL = 0x82, FW_RI_DATA_ISGL = 0x83 }; enum fw_ri_sgl_depth { FW_RI_SGL_DEPTH_MAX_SQ = 16, FW_RI_SGL_DEPTH_MAX_RQ = 4 }; enum fw_ri_cqe_err { FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ }; struct fw_ri_dsge_pair { __be32 len[2]; __be64 addr[2]; }; struct fw_ri_dsgl { __u8 op; __u8 r1; __be16 nsge; __be32 len0; __be64 addr0; #ifndef C99_NOT_SUPPORTED struct fw_ri_dsge_pair sge[0]; #endif }; struct fw_ri_sge { __be32 stag; __be32 len; __be64 to; }; struct fw_ri_isgl { __u8 op; __u8 r1; __be16 nsge; __be32 r2; #ifndef C99_NOT_SUPPORTED struct fw_ri_sge sge[0]; #endif }; struct fw_ri_immd { __u8 op; __u8 r1; __be16 r2; __be32 immdlen; #ifndef C99_NOT_SUPPORTED __u8 data[0]; #endif }; struct fw_ri_tpte { __be32 valid_to_pdid; __be32 locread_to_qpid; __be32 nosnoop_pbladdr; __be32 len_lo; __be32 va_hi; __be32 va_lo_fbo; __be32 dca_mwbcnt_pstag; __be32 len_hi; }; #define S_FW_RI_TPTE_VALID 31 #define M_FW_RI_TPTE_VALID 0x1 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) #define G_FW_RI_TPTE_VALID(x) \ (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) #define S_FW_RI_TPTE_STAGKEY 23 #define M_FW_RI_TPTE_STAGKEY 0xff #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) #define G_FW_RI_TPTE_STAGKEY(x) \ (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) #define S_FW_RI_TPTE_STAGSTATE 22 #define M_FW_RI_TPTE_STAGSTATE 0x1 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) #define G_FW_RI_TPTE_STAGSTATE(x) \ (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) #define S_FW_RI_TPTE_STAGTYPE 20 #define M_FW_RI_TPTE_STAGTYPE 0x3 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) #define G_FW_RI_TPTE_STAGTYPE(x) \ (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) #define S_FW_RI_TPTE_PDID 0 #define M_FW_RI_TPTE_PDID 0xfffff #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) #define G_FW_RI_TPTE_PDID(x) \ (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) #define S_FW_RI_TPTE_PERM 28 #define M_FW_RI_TPTE_PERM 0xf #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) #define G_FW_RI_TPTE_PERM(x) \ (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) #define S_FW_RI_TPTE_REMINVDIS 27 #define M_FW_RI_TPTE_REMINVDIS 0x1 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) #define G_FW_RI_TPTE_REMINVDIS(x) \ (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) #define S_FW_RI_TPTE_ADDRTYPE 26 #define M_FW_RI_TPTE_ADDRTYPE 1 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) #define G_FW_RI_TPTE_ADDRTYPE(x) \ (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) #define S_FW_RI_TPTE_MWBINDEN 25 #define M_FW_RI_TPTE_MWBINDEN 0x1 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) #define G_FW_RI_TPTE_MWBINDEN(x) \ (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) #define S_FW_RI_TPTE_PS 20 #define M_FW_RI_TPTE_PS 0x1f #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) #define G_FW_RI_TPTE_PS(x) \ (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) #define S_FW_RI_TPTE_QPID 0 #define M_FW_RI_TPTE_QPID 0xfffff #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) #define G_FW_RI_TPTE_QPID(x) \ (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) #define S_FW_RI_TPTE_NOSNOOP 31 #define M_FW_RI_TPTE_NOSNOOP 0x1 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) #define G_FW_RI_TPTE_NOSNOOP(x) \ (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) #define S_FW_RI_TPTE_PBLADDR 0 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) #define G_FW_RI_TPTE_PBLADDR(x) \ (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) #define S_FW_RI_TPTE_DCA 24 #define M_FW_RI_TPTE_DCA 0x1f #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) #define G_FW_RI_TPTE_DCA(x) \ (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) enum fw_ri_cqe_rxtx { FW_RI_CQE_RXTX_RX = 0x0, FW_RI_CQE_RXTX_TX = 0x1, }; struct fw_ri_cqe { union fw_ri_rxtx { struct fw_ri_scqe { __be32 qpid_n_stat_rxtx_type; __be32 plen; __be32 reserved; __be32 wrid; } scqe; struct fw_ri_rcqe { __be32 qpid_n_stat_rxtx_type; __be32 plen; __be32 stag; __be32 msn; } rcqe; } u; }; #define S_FW_RI_CQE_QPID 12 #define M_FW_RI_CQE_QPID 0xfffff #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) #define G_FW_RI_CQE_QPID(x) \ (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) #define S_FW_RI_CQE_NOTIFY 10 #define M_FW_RI_CQE_NOTIFY 0x1 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) #define G_FW_RI_CQE_NOTIFY(x) \ (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) #define S_FW_RI_CQE_STATUS 5 #define M_FW_RI_CQE_STATUS 0x1f #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) #define G_FW_RI_CQE_STATUS(x) \ (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) #define S_FW_RI_CQE_RXTX 4 #define M_FW_RI_CQE_RXTX 0x1 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) #define G_FW_RI_CQE_RXTX(x) \ (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) #define S_FW_RI_CQE_TYPE 0 #define M_FW_RI_CQE_TYPE 0xf #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) #define G_FW_RI_CQE_TYPE(x) \ (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) enum fw_ri_res_type { FW_RI_RES_TYPE_SQ, FW_RI_RES_TYPE_RQ, FW_RI_RES_TYPE_CQ, }; enum fw_ri_res_op { FW_RI_RES_OP_WRITE, FW_RI_RES_OP_RESET, }; struct fw_ri_res { union fw_ri_restype { struct fw_ri_res_sqrq { __u8 restype; __u8 op; __be16 r3; __be32 eqid; __be32 r4[2]; __be32 fetchszm_to_iqid; __be32 dcaen_to_eqsize; __be64 eqaddr; } sqrq; struct fw_ri_res_cq { __u8 restype; __u8 op; __be16 r3; __be32 iqid; __be32 r4[2]; __be32 iqandst_to_iqandstindex; __be16 iqdroprss_to_iqesize; __be16 iqsize; __be64 iqaddr; __be32 iqns_iqro; __be32 r6_lo; __be64 r7; } cq; } u; }; struct fw_ri_res_wr { __be32 op_nres; __be32 len16_pkd; __u64 cookie; #ifndef C99_NOT_SUPPORTED struct fw_ri_res res[0]; #endif }; #define S_FW_RI_RES_WR_NRES 0 #define M_FW_RI_RES_WR_NRES 0xff #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) #define G_FW_RI_RES_WR_NRES(x) \ (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) #define S_FW_RI_RES_WR_FETCHSZM 26 #define M_FW_RI_RES_WR_FETCHSZM 0x1 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) #define G_FW_RI_RES_WR_FETCHSZM(x) \ (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) #define S_FW_RI_RES_WR_STATUSPGNS 25 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) #define G_FW_RI_RES_WR_STATUSPGNS(x) \ (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) #define S_FW_RI_RES_WR_STATUSPGRO 24 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) #define G_FW_RI_RES_WR_STATUSPGRO(x) \ (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) #define S_FW_RI_RES_WR_FETCHNS 23 #define M_FW_RI_RES_WR_FETCHNS 0x1 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) #define G_FW_RI_RES_WR_FETCHNS(x) \ (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) #define S_FW_RI_RES_WR_FETCHRO 22 #define M_FW_RI_RES_WR_FETCHRO 0x1 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) #define G_FW_RI_RES_WR_FETCHRO(x) \ (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) #define S_FW_RI_RES_WR_HOSTFCMODE 20 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) #define S_FW_RI_RES_WR_CPRIO 19 #define M_FW_RI_RES_WR_CPRIO 0x1 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) #define G_FW_RI_RES_WR_CPRIO(x) \ (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) #define S_FW_RI_RES_WR_ONCHIP 18 #define M_FW_RI_RES_WR_ONCHIP 0x1 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) #define G_FW_RI_RES_WR_ONCHIP(x) \ (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) #define S_FW_RI_RES_WR_PCIECHN 16 #define M_FW_RI_RES_WR_PCIECHN 0x3 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) #define G_FW_RI_RES_WR_PCIECHN(x) \ (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) #define S_FW_RI_RES_WR_IQID 0 #define M_FW_RI_RES_WR_IQID 0xffff #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) #define G_FW_RI_RES_WR_IQID(x) \ (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) #define S_FW_RI_RES_WR_DCAEN 31 #define M_FW_RI_RES_WR_DCAEN 0x1 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) #define G_FW_RI_RES_WR_DCAEN(x) \ (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) #define S_FW_RI_RES_WR_DCACPU 26 #define M_FW_RI_RES_WR_DCACPU 0x1f #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) #define G_FW_RI_RES_WR_DCACPU(x) \ (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) #define S_FW_RI_RES_WR_FBMIN 23 #define M_FW_RI_RES_WR_FBMIN 0x7 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) #define G_FW_RI_RES_WR_FBMIN(x) \ (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) #define S_FW_RI_RES_WR_FBMAX 20 #define M_FW_RI_RES_WR_FBMAX 0x7 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) #define G_FW_RI_RES_WR_FBMAX(x) \ (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) #define S_FW_RI_RES_WR_CIDXFTHRESH 16 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) #define S_FW_RI_RES_WR_EQSIZE 0 #define M_FW_RI_RES_WR_EQSIZE 0xffff #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) #define G_FW_RI_RES_WR_EQSIZE(x) \ (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) #define S_FW_RI_RES_WR_IQANDST 15 #define M_FW_RI_RES_WR_IQANDST 0x1 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) #define G_FW_RI_RES_WR_IQANDST(x) \ (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) #define S_FW_RI_RES_WR_IQANUS 14 #define M_FW_RI_RES_WR_IQANUS 0x1 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) #define G_FW_RI_RES_WR_IQANUS(x) \ (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) #define S_FW_RI_RES_WR_IQANUD 12 #define M_FW_RI_RES_WR_IQANUD 0x3 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) #define G_FW_RI_RES_WR_IQANUD(x) \ (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) #define S_FW_RI_RES_WR_IQANDSTINDEX 0 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) #define S_FW_RI_RES_WR_IQDROPRSS 15 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) #define G_FW_RI_RES_WR_IQDROPRSS(x) \ (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) #define S_FW_RI_RES_WR_IQGTSMODE 14 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) #define G_FW_RI_RES_WR_IQGTSMODE(x) \ (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) #define S_FW_RI_RES_WR_IQPCIECH 12 #define M_FW_RI_RES_WR_IQPCIECH 0x3 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) #define G_FW_RI_RES_WR_IQPCIECH(x) \ (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) #define S_FW_RI_RES_WR_IQDCAEN 11 #define M_FW_RI_RES_WR_IQDCAEN 0x1 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) #define G_FW_RI_RES_WR_IQDCAEN(x) \ (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) #define S_FW_RI_RES_WR_IQDCACPU 6 #define M_FW_RI_RES_WR_IQDCACPU 0x1f #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) #define G_FW_RI_RES_WR_IQDCACPU(x) \ (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) #define S_FW_RI_RES_WR_IQO 3 #define M_FW_RI_RES_WR_IQO 0x1 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) #define G_FW_RI_RES_WR_IQO(x) \ (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) #define S_FW_RI_RES_WR_IQCPRIO 2 #define M_FW_RI_RES_WR_IQCPRIO 0x1 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) #define G_FW_RI_RES_WR_IQCPRIO(x) \ (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) #define S_FW_RI_RES_WR_IQESIZE 0 #define M_FW_RI_RES_WR_IQESIZE 0x3 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) #define G_FW_RI_RES_WR_IQESIZE(x) \ (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) #define S_FW_RI_RES_WR_IQNS 31 #define M_FW_RI_RES_WR_IQNS 0x1 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) #define G_FW_RI_RES_WR_IQNS(x) \ (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) #define S_FW_RI_RES_WR_IQRO 30 #define M_FW_RI_RES_WR_IQRO 0x1 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) #define G_FW_RI_RES_WR_IQRO(x) \ (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) struct fw_ri_rdma_write_wr { __u8 opcode; __u8 flags; __u16 wrid; __u8 r1[3]; __u8 len16; __be64 r2; __be32 plen; __be32 stag_sink; __be64 to_sink; #ifndef C99_NOT_SUPPORTED union { struct fw_ri_immd immd_src[0]; struct fw_ri_isgl isgl_src[0]; } u; #endif }; struct fw_ri_send_wr { __u8 opcode; __u8 flags; __u16 wrid; __u8 r1[3]; __u8 len16; __be32 sendop_pkd; __be32 stag_inv; __be32 plen; __be32 r3; __be64 r4; #ifndef C99_NOT_SUPPORTED union { struct fw_ri_immd immd_src[0]; struct fw_ri_isgl isgl_src[0]; } u; #endif }; #define S_FW_RI_SEND_WR_SENDOP 0 #define M_FW_RI_SEND_WR_SENDOP 0xf #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) #define G_FW_RI_SEND_WR_SENDOP(x) \ (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) struct fw_ri_rdma_read_wr { __u8 opcode; __u8 flags; __u16 wrid; __u8 r1[3]; __u8 len16; __be64 r2; __be32 stag_sink; __be32 to_sink_hi; __be32 to_sink_lo; __be32 plen; __be32 stag_src; __be32 to_src_hi; __be32 to_src_lo; __be32 r5; }; struct fw_ri_recv_wr { __u8 opcode; __u8 r1; __u16 wrid; __u8 r2[3]; __u8 len16; struct fw_ri_isgl isgl; }; struct fw_ri_bind_mw_wr { __u8 opcode; __u8 flags; __u16 wrid; __u8 r1[3]; __u8 len16; __u8 qpbinde_to_dcacpu; __u8 pgsz_shift; __u8 addr_type; __u8 mem_perms; __be32 stag_mr; __be32 stag_mw; __be32 r3; __be64 len_mw; __be64 va_fbo; __be64 r4; }; #define S_FW_RI_BIND_MW_WR_QPBINDE 6 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) #define S_FW_RI_BIND_MW_WR_NS 5 #define M_FW_RI_BIND_MW_WR_NS 0x1 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) #define G_FW_RI_BIND_MW_WR_NS(x) \ (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) #define S_FW_RI_BIND_MW_WR_DCACPU 0 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) struct fw_ri_fr_nsmr_wr { __u8 opcode; __u8 flags; __u16 wrid; __u8 r1[3]; __u8 len16; __u8 qpbinde_to_dcacpu; __u8 pgsz_shift; __u8 addr_type; __u8 mem_perms; __be32 stag; __be32 len_hi; __be32 len_lo; __be32 va_hi; __be32 va_lo_fbo; }; #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) #define S_FW_RI_FR_NSMR_WR_NS 5 #define M_FW_RI_FR_NSMR_WR_NS 0x1 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) #define G_FW_RI_FR_NSMR_WR_NS(x) \ (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) #define S_FW_RI_FR_NSMR_WR_DCACPU 0 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) struct fw_ri_inv_lstag_wr { __u8 opcode; __u8 flags; __u16 wrid; __u8 r1[3]; __u8 len16; __be32 r2; __be32 stag_inv; }; enum fw_ri_type { FW_RI_TYPE_INIT, FW_RI_TYPE_FINI, FW_RI_TYPE_TERMINATE }; enum fw_ri_init_p2ptype { FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, FW_RI_INIT_P2PTYPE_DISABLED = 0xf, }; struct fw_ri_wr { __be32 op_compl; __be32 flowid_len16; __u64 cookie; union fw_ri { struct fw_ri_init { __u8 type; __u8 mpareqbit_p2ptype; __u8 r4[2]; __u8 mpa_attrs; __u8 qp_caps; __be16 nrqe; __be32 pdid; __be32 qpid; __be32 sq_eqid; __be32 rq_eqid; __be32 scqid; __be32 rcqid; __be32 ord_max; __be32 ird_max; __be32 iss; __be32 irs; __be32 hwrqsize; __be32 hwrqaddr; __be64 r5; union fw_ri_init_p2p { struct fw_ri_rdma_write_wr write; struct fw_ri_rdma_read_wr read; struct fw_ri_send_wr send; } u; } init; struct fw_ri_fini { __u8 type; __u8 r3[7]; __be64 r4; } fini; struct fw_ri_terminate { __u8 type; __u8 r3[3]; __be32 immdlen; __u8 termmsg[40]; } terminate; } u; }; #define S_FW_RI_WR_MPAREQBIT 7 #define M_FW_RI_WR_MPAREQBIT 0x1 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) #define G_FW_RI_WR_MPAREQBIT(x) \ (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) #define S_FW_RI_WR_0BRRBIT 6 #define M_FW_RI_WR_0BRRBIT 0x1 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) #define G_FW_RI_WR_0BRRBIT(x) \ (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) #define S_FW_RI_WR_P2PTYPE 0 #define M_FW_RI_WR_P2PTYPE 0xf #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) #define G_FW_RI_WR_P2PTYPE(x) \ (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) +#ifdef FOISCSI +struct fw_iscsi_node_wr { + __u8 opcode; + __u8 subop; + __u8 node_attr_to_compl; + __u8 len16; + __u8 status; + __u8 r2; + __be16 immd_len; + __be64 cookie; + __be32 node_id; + __be32 ctrl_handle; + __be32 io_handle; + __be32 r3; +}; +#define S_FW_ISCSI_NODE_WR_NODE_ATTR 7 +#define M_FW_ISCSI_NODE_WR_NODE_ATTR 0x1 +#define V_FW_ISCSI_NODE_WR_NODE_ATTR(x) ((x) << S_FW_ISCSI_NODE_WR_NODE_ATTR) +#define G_FW_ISCSI_NODE_WR_NODE_ATTR(x) \ + (((x) >> S_FW_ISCSI_NODE_WR_NODE_ATTR) & M_FW_ISCSI_NODE_WR_NODE_ATTR) +#define F_FW_ISCSI_NODE_WR_NODE_ATTR V_FW_ISCSI_NODE_WR_NODE_ATTR(1U) + +#define S_FW_ISCSI_NODE_WR_SESS_ATTR 6 +#define M_FW_ISCSI_NODE_WR_SESS_ATTR 0x1 +#define V_FW_ISCSI_NODE_WR_SESS_ATTR(x) ((x) << S_FW_ISCSI_NODE_WR_SESS_ATTR) +#define G_FW_ISCSI_NODE_WR_SESS_ATTR(x) \ + (((x) >> S_FW_ISCSI_NODE_WR_SESS_ATTR) & M_FW_ISCSI_NODE_WR_SESS_ATTR) +#define F_FW_ISCSI_NODE_WR_SESS_ATTR V_FW_ISCSI_NODE_WR_SESS_ATTR(1U) + +#define S_FW_ISCSI_NODE_WR_CONN_ATTR 5 +#define M_FW_ISCSI_NODE_WR_CONN_ATTR 0x1 +#define V_FW_ISCSI_NODE_WR_CONN_ATTR(x) ((x) << S_FW_ISCSI_NODE_WR_CONN_ATTR) +#define G_FW_ISCSI_NODE_WR_CONN_ATTR(x) \ + (((x) >> S_FW_ISCSI_NODE_WR_CONN_ATTR) & M_FW_ISCSI_NODE_WR_CONN_ATTR) +#define F_FW_ISCSI_NODE_WR_CONN_ATTR V_FW_ISCSI_NODE_WR_CONN_ATTR(1U) + +#define S_FW_ISCSI_NODE_WR_TGT_ATTR 4 +#define M_FW_ISCSI_NODE_WR_TGT_ATTR 0x1 +#define V_FW_ISCSI_NODE_WR_TGT_ATTR(x) ((x) << S_FW_ISCSI_NODE_WR_TGT_ATTR) +#define G_FW_ISCSI_NODE_WR_TGT_ATTR(x) \ + (((x) >> S_FW_ISCSI_NODE_WR_TGT_ATTR) & M_FW_ISCSI_NODE_WR_TGT_ATTR) +#define F_FW_ISCSI_NODE_WR_TGT_ATTR V_FW_ISCSI_NODE_WR_TGT_ATTR(1U) + +#define S_FW_ISCSI_NODE_WR_NODE_TYPE 3 +#define M_FW_ISCSI_NODE_WR_NODE_TYPE 0x1 +#define V_FW_ISCSI_NODE_WR_NODE_TYPE(x) ((x) << S_FW_ISCSI_NODE_WR_NODE_TYPE) +#define G_FW_ISCSI_NODE_WR_NODE_TYPE(x) \ + (((x) >> S_FW_ISCSI_NODE_WR_NODE_TYPE) & M_FW_ISCSI_NODE_WR_NODE_TYPE) +#define F_FW_ISCSI_NODE_WR_NODE_TYPE V_FW_ISCSI_NODE_WR_NODE_TYPE(1U) + +#define S_FW_ISCSI_NODE_WR_COMPL 0 +#define M_FW_ISCSI_NODE_WR_COMPL 0x1 +#define V_FW_ISCSI_NODE_WR_COMPL(x) ((x) << S_FW_ISCSI_NODE_WR_COMPL) +#define G_FW_ISCSI_NODE_WR_COMPL(x) \ + (((x) >> S_FW_ISCSI_NODE_WR_COMPL) & M_FW_ISCSI_NODE_WR_COMPL) +#define F_FW_ISCSI_NODE_WR_COMPL V_FW_ISCSI_NODE_WR_COMPL(1U) + +#endif + /****************************************************************************** * C O M M A N D s *********************/ /* * The maximum length of time, in miliseconds, that we expect any firmware * command to take to execute and return a reply to the host. The RESET * and INITIALIZE commands can take a fair amount of time to execute but * most execute in far less time than this maximum. This constant is used * by host software to determine how long to wait for a firmware command * reply before declaring the firmware as dead/unreachable ... */ #define FW_CMD_MAX_TIMEOUT 10000 enum fw_cmd_opcodes { FW_LDST_CMD = 0x01, FW_RESET_CMD = 0x03, FW_HELLO_CMD = 0x04, FW_BYE_CMD = 0x05, FW_INITIALIZE_CMD = 0x06, FW_CAPS_CONFIG_CMD = 0x07, FW_PARAMS_CMD = 0x08, FW_PFVF_CMD = 0x09, FW_IQ_CMD = 0x10, FW_EQ_MNGT_CMD = 0x11, FW_EQ_ETH_CMD = 0x12, FW_EQ_CTRL_CMD = 0x13, FW_EQ_OFLD_CMD = 0x21, FW_VI_CMD = 0x14, FW_VI_MAC_CMD = 0x15, FW_VI_RXMODE_CMD = 0x16, FW_VI_ENABLE_CMD = 0x17, FW_VI_STATS_CMD = 0x1a, FW_ACL_MAC_CMD = 0x18, FW_ACL_VLAN_CMD = 0x19, FW_PORT_CMD = 0x1b, FW_PORT_STATS_CMD = 0x1c, FW_PORT_LB_STATS_CMD = 0x1d, FW_PORT_TRACE_CMD = 0x1e, FW_PORT_TRACE_MMAP_CMD = 0x1f, FW_RSS_IND_TBL_CMD = 0x20, FW_RSS_GLB_CONFIG_CMD = 0x22, FW_RSS_VI_CONFIG_CMD = 0x23, FW_SCHED_CMD = 0x24, FW_DEVLOG_CMD = 0x25, + FW_NETIF_CMD = 0x26, FW_LASTC2E_CMD = 0x40, FW_ERROR_CMD = 0x80, FW_DEBUG_CMD = 0x81, }; enum fw_cmd_cap { FW_CMD_CAP_PF = 0x01, FW_CMD_CAP_DMAQ = 0x02, FW_CMD_CAP_PORT = 0x04, FW_CMD_CAP_PORTPROMISC = 0x08, FW_CMD_CAP_PORTSTATS = 0x10, FW_CMD_CAP_VF = 0x80, }; /* * Generic command header flit0 */ struct fw_cmd_hdr { __be32 hi; __be32 lo; }; #define S_FW_CMD_OP 24 #define M_FW_CMD_OP 0xff #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) #define S_FW_CMD_REQUEST 23 #define M_FW_CMD_REQUEST 0x1 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) #define S_FW_CMD_READ 22 #define M_FW_CMD_READ 0x1 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) #define F_FW_CMD_READ V_FW_CMD_READ(1U) #define S_FW_CMD_WRITE 21 #define M_FW_CMD_WRITE 0x1 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) #define S_FW_CMD_EXEC 20 #define M_FW_CMD_EXEC 0x1 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) #define S_FW_CMD_RAMASK 20 #define M_FW_CMD_RAMASK 0xf #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) #define S_FW_CMD_RETVAL 8 #define M_FW_CMD_RETVAL 0xff #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) #define S_FW_CMD_LEN16 0 #define M_FW_CMD_LEN16 0xff #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) /* * address spaces */ enum fw_ldst_addrspc { FW_LDST_ADDRSPC_FIRMWARE = 0x0001, FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, FW_LDST_ADDRSPC_SGE_INGC = 0x0009, FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, FW_LDST_ADDRSPC_TP_PIO = 0x0010, FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, FW_LDST_ADDRSPC_TP_MIB = 0x0012, FW_LDST_ADDRSPC_MDIO = 0x0018, FW_LDST_ADDRSPC_MPS = 0x0020, FW_LDST_ADDRSPC_FUNC = 0x0028, FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, }; /* * MDIO VSC8634 register access control field */ enum fw_ldst_mdio_vsc8634_aid { FW_LDST_MDIO_VS_STANDARD, FW_LDST_MDIO_VS_EXTENDED, FW_LDST_MDIO_VS_GPIO }; enum fw_ldst_mps_fid { FW_LDST_MPS_ATRB, FW_LDST_MPS_RPLC }; enum fw_ldst_func_access_ctl { FW_LDST_FUNC_ACC_CTL_VIID, FW_LDST_FUNC_ACC_CTL_FID }; enum fw_ldst_func_mod_index { FW_LDST_FUNC_MPS }; struct fw_ldst_cmd { __be32 op_to_addrspace; __be32 cycles_to_len16; union fw_ldst { struct fw_ldst_addrval { __be32 addr; __be32 val; } addrval; struct fw_ldst_idctxt { __be32 physid; __be32 msg_pkd; __be32 ctxt_data7; __be32 ctxt_data6; __be32 ctxt_data5; __be32 ctxt_data4; __be32 ctxt_data3; __be32 ctxt_data2; __be32 ctxt_data1; __be32 ctxt_data0; } idctxt; struct fw_ldst_mdio { __be16 paddr_mmd; __be16 raddr; __be16 vctl; __be16 rval; } mdio; struct fw_ldst_mps { __be16 fid_ctl; __be16 rplcpf_pkd; __be32 rplc127_96; __be32 rplc95_64; __be32 rplc63_32; __be32 rplc31_0; __be32 atrb; __be16 vlan[16]; } mps; struct fw_ldst_func { __u8 access_ctl; __u8 mod_index; __be16 ctl_id; __be32 offset; __be64 data0; __be64 data1; } func; struct fw_ldst_pcie { __u8 ctrl_to_fn; __u8 bnum; __u8 r; __u8 ext_r; __u8 select_naccess; __u8 pcie_fn; __be16 nset_pkd; __be32 data[12]; } pcie; struct fw_ldst_i2c { __u8 pid_pkd; __u8 base; __u8 boffset; __u8 data; __be32 r9; } i2c; } u; }; #define S_FW_LDST_CMD_ADDRSPACE 0 #define M_FW_LDST_CMD_ADDRSPACE 0xff #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) #define G_FW_LDST_CMD_ADDRSPACE(x) \ (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) #define S_FW_LDST_CMD_CYCLES 16 #define M_FW_LDST_CMD_CYCLES 0xffff #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) #define G_FW_LDST_CMD_CYCLES(x) \ (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) #define S_FW_LDST_CMD_MSG 31 #define M_FW_LDST_CMD_MSG 0x1 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) #define G_FW_LDST_CMD_MSG(x) \ (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) #define S_FW_LDST_CMD_PADDR 8 #define M_FW_LDST_CMD_PADDR 0x1f #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) #define G_FW_LDST_CMD_PADDR(x) \ (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) #define S_FW_LDST_CMD_MMD 0 #define M_FW_LDST_CMD_MMD 0x1f #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) #define G_FW_LDST_CMD_MMD(x) \ (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) #define S_FW_LDST_CMD_FID 15 #define M_FW_LDST_CMD_FID 0x1 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) #define G_FW_LDST_CMD_FID(x) \ (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) #define S_FW_LDST_CMD_CTL 0 #define M_FW_LDST_CMD_CTL 0x7fff #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) #define G_FW_LDST_CMD_CTL(x) \ (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) #define S_FW_LDST_CMD_RPLCPF 0 #define M_FW_LDST_CMD_RPLCPF 0xff #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) #define G_FW_LDST_CMD_RPLCPF(x) \ (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) #define S_FW_LDST_CMD_CTRL 7 #define M_FW_LDST_CMD_CTRL 0x1 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) #define G_FW_LDST_CMD_CTRL(x) \ (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) #define S_FW_LDST_CMD_LC 4 #define M_FW_LDST_CMD_LC 0x1 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) #define S_FW_LDST_CMD_AI 3 #define M_FW_LDST_CMD_AI 0x1 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) #define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) #define S_FW_LDST_CMD_FN 0 #define M_FW_LDST_CMD_FN 0x7 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) #define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) #define S_FW_LDST_CMD_SELECT 4 #define M_FW_LDST_CMD_SELECT 0xf #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) #define G_FW_LDST_CMD_SELECT(x) \ (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) #define S_FW_LDST_CMD_NACCESS 0 #define M_FW_LDST_CMD_NACCESS 0xf #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) #define G_FW_LDST_CMD_NACCESS(x) \ (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) #define S_FW_LDST_CMD_NSET 14 #define M_FW_LDST_CMD_NSET 0x3 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) #define G_FW_LDST_CMD_NSET(x) \ (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) #define S_FW_LDST_CMD_PID 6 #define M_FW_LDST_CMD_PID 0x3 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) #define G_FW_LDST_CMD_PID(x) \ (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) struct fw_reset_cmd { __be32 op_to_write; __be32 retval_len16; __be32 val; __be32 r3; }; struct fw_hello_cmd { __be32 op_to_write; __be32 retval_len16; __be32 err_to_mbasyncnot; __be32 fwrev; }; #define S_FW_HELLO_CMD_ERR 31 #define M_FW_HELLO_CMD_ERR 0x1 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) #define G_FW_HELLO_CMD_ERR(x) \ (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) #define S_FW_HELLO_CMD_INIT 30 #define M_FW_HELLO_CMD_INIT 0x1 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) #define G_FW_HELLO_CMD_INIT(x) \ (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) #define S_FW_HELLO_CMD_MASTERDIS 29 #define M_FW_HELLO_CMD_MASTERDIS 0x1 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) #define G_FW_HELLO_CMD_MASTERDIS(x) \ (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) #define S_FW_HELLO_CMD_MASTERFORCE 28 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) #define G_FW_HELLO_CMD_MASTERFORCE(x) \ (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) #define S_FW_HELLO_CMD_MBMASTER 24 #define M_FW_HELLO_CMD_MBMASTER 0xf #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) #define G_FW_HELLO_CMD_MBMASTER(x) \ (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) #define S_FW_HELLO_CMD_MBASYNCNOT 20 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) struct fw_bye_cmd { __be32 op_to_write; __be32 retval_len16; __be64 r3; }; struct fw_initialize_cmd { __be32 op_to_write; __be32 retval_len16; __be64 r3; }; enum fw_caps_config_hm { FW_CAPS_CONFIG_HM_PCIE = 0x00000001, FW_CAPS_CONFIG_HM_PL = 0x00000002, FW_CAPS_CONFIG_HM_SGE = 0x00000004, FW_CAPS_CONFIG_HM_CIM = 0x00000008, FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, FW_CAPS_CONFIG_HM_TP = 0x00000020, FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, FW_CAPS_CONFIG_HM_PMRX = 0x00000080, FW_CAPS_CONFIG_HM_PMTX = 0x00000100, FW_CAPS_CONFIG_HM_MC = 0x00000200, FW_CAPS_CONFIG_HM_LE = 0x00000400, FW_CAPS_CONFIG_HM_MPS = 0x00000800, FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, FW_CAPS_CONFIG_HM_MI = 0x00008000, FW_CAPS_CONFIG_HM_I2CM = 0x00010000, FW_CAPS_CONFIG_HM_NCSI = 0x00020000, FW_CAPS_CONFIG_HM_SMB = 0x00040000, FW_CAPS_CONFIG_HM_MA = 0x00080000, FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, FW_CAPS_CONFIG_HM_PMU = 0x00200000, FW_CAPS_CONFIG_HM_UART = 0x00400000, FW_CAPS_CONFIG_HM_SF = 0x00800000, }; /* * The VF Register Map. * * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local * bus module (PL) and CPU Interface Module (CIM) components are mapped via * the Slice to Module Map Table (see below) in the Physical Function Register * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base * and Offset registers in the PF Register Map. The MBDATA base address is * quite constrained as it determines the Mailbox Data addresses for both PFs * and VFs, and therefore must fit in both the VF and PF Register Maps without * overlapping other registers. */ #define FW_T4VF_SGE_BASE_ADDR 0x0000 #define FW_T4VF_MPS_BASE_ADDR 0x0100 #define FW_T4VF_PL_BASE_ADDR 0x0200 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 #define FW_T4VF_CIM_BASE_ADDR 0x0300 #define FW_T4VF_REGMAP_START 0x0000 #define FW_T4VF_REGMAP_SIZE 0x0400 enum fw_caps_config_nbm { FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, }; enum fw_caps_config_link { FW_CAPS_CONFIG_LINK_PPP = 0x00000001, FW_CAPS_CONFIG_LINK_QFC = 0x00000002, FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, }; enum fw_caps_config_switch { FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, }; enum fw_caps_config_nic { FW_CAPS_CONFIG_NIC = 0x00000001, FW_CAPS_CONFIG_NIC_VM = 0x00000002, FW_CAPS_CONFIG_NIC_IDS = 0x00000004, }; enum fw_caps_config_toe { FW_CAPS_CONFIG_TOE = 0x00000001, }; enum fw_caps_config_rdma { FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, }; enum fw_caps_config_iscsi { FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, + FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, + FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, }; enum fw_caps_config_fcoe { FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, }; struct fw_caps_config_cmd { __be32 op_to_write; __be32 retval_len16; __be32 r2; __be32 hwmbitmap; __be16 nbmcaps; __be16 linkcaps; __be16 switchcaps; __be16 r3; __be16 niccaps; __be16 toecaps; __be16 rdmacaps; __be16 r4; __be16 iscsicaps; __be16 fcoecaps; __be32 r5; __be64 r6; }; /* * params command mnemonics */ enum fw_params_mnem { FW_PARAMS_MNEM_DEV = 1, /* device params */ FW_PARAMS_MNEM_PFVF = 2, /* function params */ FW_PARAMS_MNEM_REG = 3, /* limited register access */ FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ FW_PARAMS_MNEM_LAST }; /* * device parameters */ enum fw_params_param_dev { FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs * allocated by the device's * Lookup Engine */ FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, FW_PARAMS_PARAM_DEV_FWREV = 0x0B, FW_PARAMS_PARAM_DEV_TPREV = 0x0C, }; /* * physical and virtual function parameters */ enum fw_params_param_pfvf { FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, FW_PARAMS_PARAM_PFVF_VIID = 0x24, FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C }; /* * dma queue parameters */ enum fw_params_param_dmaq { FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, }; #define S_FW_PARAMS_MNEM 24 #define M_FW_PARAMS_MNEM 0xff #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) #define G_FW_PARAMS_MNEM(x) \ (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) #define S_FW_PARAMS_PARAM_X 16 #define M_FW_PARAMS_PARAM_X 0xff #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) #define G_FW_PARAMS_PARAM_X(x) \ (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) #define S_FW_PARAMS_PARAM_Y 8 #define M_FW_PARAMS_PARAM_Y 0xff #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) #define G_FW_PARAMS_PARAM_Y(x) \ (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) #define S_FW_PARAMS_PARAM_Z 0 #define M_FW_PARAMS_PARAM_Z 0xff #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) #define G_FW_PARAMS_PARAM_Z(x) \ (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) #define S_FW_PARAMS_PARAM_XYZ 0 #define M_FW_PARAMS_PARAM_XYZ 0xffffff #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) #define G_FW_PARAMS_PARAM_XYZ(x) \ (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) #define S_FW_PARAMS_PARAM_YZ 0 #define M_FW_PARAMS_PARAM_YZ 0xffff #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) #define G_FW_PARAMS_PARAM_YZ(x) \ (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) struct fw_params_cmd { __be32 op_to_vfn; __be32 retval_len16; struct fw_params_param { __be32 mnem; __be32 val; } param[7]; }; #define S_FW_PARAMS_CMD_PFN 8 #define M_FW_PARAMS_CMD_PFN 0x7 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) #define G_FW_PARAMS_CMD_PFN(x) \ (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) #define S_FW_PARAMS_CMD_VFN 0 #define M_FW_PARAMS_CMD_VFN 0xff #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) #define G_FW_PARAMS_CMD_VFN(x) \ (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) struct fw_pfvf_cmd { __be32 op_to_vfn; __be32 retval_len16; __be32 niqflint_niq; __be32 type_to_neq; __be32 tc_to_nexactf; __be32 r_caps_to_nethctrl; __be16 nricq; __be16 nriqp; __be32 r4; }; #define S_FW_PFVF_CMD_PFN 8 #define M_FW_PFVF_CMD_PFN 0x7 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) #define G_FW_PFVF_CMD_PFN(x) \ (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) #define S_FW_PFVF_CMD_VFN 0 #define M_FW_PFVF_CMD_VFN 0xff #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) #define G_FW_PFVF_CMD_VFN(x) \ (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) #define S_FW_PFVF_CMD_NIQFLINT 20 #define M_FW_PFVF_CMD_NIQFLINT 0xfff #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) #define G_FW_PFVF_CMD_NIQFLINT(x) \ (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) #define S_FW_PFVF_CMD_NIQ 0 #define M_FW_PFVF_CMD_NIQ 0xfffff #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) #define G_FW_PFVF_CMD_NIQ(x) \ (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) #define S_FW_PFVF_CMD_TYPE 31 #define M_FW_PFVF_CMD_TYPE 0x1 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) #define G_FW_PFVF_CMD_TYPE(x) \ (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) #define S_FW_PFVF_CMD_CMASK 24 #define M_FW_PFVF_CMD_CMASK 0xf #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) #define G_FW_PFVF_CMD_CMASK(x) \ (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) #define S_FW_PFVF_CMD_PMASK 20 #define M_FW_PFVF_CMD_PMASK 0xf #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) #define G_FW_PFVF_CMD_PMASK(x) \ (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) #define S_FW_PFVF_CMD_NEQ 0 #define M_FW_PFVF_CMD_NEQ 0xfffff #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) #define G_FW_PFVF_CMD_NEQ(x) \ (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) #define S_FW_PFVF_CMD_TC 24 #define M_FW_PFVF_CMD_TC 0xff #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) #define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) #define S_FW_PFVF_CMD_NVI 16 #define M_FW_PFVF_CMD_NVI 0xff #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) #define G_FW_PFVF_CMD_NVI(x) \ (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) #define S_FW_PFVF_CMD_NEXACTF 0 #define M_FW_PFVF_CMD_NEXACTF 0xffff #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) #define G_FW_PFVF_CMD_NEXACTF(x) \ (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) #define S_FW_PFVF_CMD_R_CAPS 24 #define M_FW_PFVF_CMD_R_CAPS 0xff #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) #define G_FW_PFVF_CMD_R_CAPS(x) \ (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) #define S_FW_PFVF_CMD_WX_CAPS 16 #define M_FW_PFVF_CMD_WX_CAPS 0xff #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) #define G_FW_PFVF_CMD_WX_CAPS(x) \ (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) #define S_FW_PFVF_CMD_NETHCTRL 0 #define M_FW_PFVF_CMD_NETHCTRL 0xffff #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) #define G_FW_PFVF_CMD_NETHCTRL(x) \ (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) /* * ingress queue type; the first 1K ingress queues can have associated 0, * 1 or 2 free lists and an interrupt, all other ingress queues lack these * capabilities */ enum fw_iq_type { FW_IQ_TYPE_FL_INT_CAP, FW_IQ_TYPE_NO_FL_INT_CAP }; struct fw_iq_cmd { __be32 op_to_vfn; __be32 alloc_to_len16; __be16 physiqid; __be16 iqid; __be16 fl0id; __be16 fl1id; __be32 type_to_iqandstindex; __be16 iqdroprss_to_iqesize; __be16 iqsize; __be64 iqaddr; __be32 iqns_to_fl0congen; __be16 fl0dcaen_to_fl0cidxfthresh; __be16 fl0size; __be64 fl0addr; __be32 fl1cngchmap_to_fl1congen; __be16 fl1dcaen_to_fl1cidxfthresh; __be16 fl1size; __be64 fl1addr; }; #define S_FW_IQ_CMD_PFN 8 #define M_FW_IQ_CMD_PFN 0x7 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) #define S_FW_IQ_CMD_VFN 0 #define M_FW_IQ_CMD_VFN 0xff #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) #define S_FW_IQ_CMD_ALLOC 31 #define M_FW_IQ_CMD_ALLOC 0x1 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) #define G_FW_IQ_CMD_ALLOC(x) \ (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) #define S_FW_IQ_CMD_FREE 30 #define M_FW_IQ_CMD_FREE 0x1 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) #define S_FW_IQ_CMD_MODIFY 29 #define M_FW_IQ_CMD_MODIFY 0x1 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) #define G_FW_IQ_CMD_MODIFY(x) \ (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) #define S_FW_IQ_CMD_IQSTART 28 #define M_FW_IQ_CMD_IQSTART 0x1 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) #define G_FW_IQ_CMD_IQSTART(x) \ (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) #define S_FW_IQ_CMD_IQSTOP 27 #define M_FW_IQ_CMD_IQSTOP 0x1 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) #define G_FW_IQ_CMD_IQSTOP(x) \ (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) #define S_FW_IQ_CMD_TYPE 29 #define M_FW_IQ_CMD_TYPE 0x7 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) #define S_FW_IQ_CMD_IQASYNCH 28 #define M_FW_IQ_CMD_IQASYNCH 0x1 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) #define G_FW_IQ_CMD_IQASYNCH(x) \ (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) #define S_FW_IQ_CMD_VIID 16 #define M_FW_IQ_CMD_VIID 0xfff #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) #define S_FW_IQ_CMD_IQANDST 15 #define M_FW_IQ_CMD_IQANDST 0x1 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) #define G_FW_IQ_CMD_IQANDST(x) \ (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) #define S_FW_IQ_CMD_IQANUS 14 #define M_FW_IQ_CMD_IQANUS 0x1 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) #define G_FW_IQ_CMD_IQANUS(x) \ (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) #define S_FW_IQ_CMD_IQANUD 12 #define M_FW_IQ_CMD_IQANUD 0x3 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) #define G_FW_IQ_CMD_IQANUD(x) \ (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) #define S_FW_IQ_CMD_IQANDSTINDEX 0 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) #define S_FW_IQ_CMD_IQDROPRSS 15 #define M_FW_IQ_CMD_IQDROPRSS 0x1 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) #define G_FW_IQ_CMD_IQDROPRSS(x) \ (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) #define S_FW_IQ_CMD_IQGTSMODE 14 #define M_FW_IQ_CMD_IQGTSMODE 0x1 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) #define G_FW_IQ_CMD_IQGTSMODE(x) \ (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) #define S_FW_IQ_CMD_IQPCIECH 12 #define M_FW_IQ_CMD_IQPCIECH 0x3 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) #define G_FW_IQ_CMD_IQPCIECH(x) \ (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) #define S_FW_IQ_CMD_IQDCAEN 11 #define M_FW_IQ_CMD_IQDCAEN 0x1 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) #define G_FW_IQ_CMD_IQDCAEN(x) \ (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) #define S_FW_IQ_CMD_IQDCACPU 6 #define M_FW_IQ_CMD_IQDCACPU 0x1f #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) #define G_FW_IQ_CMD_IQDCACPU(x) \ (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) #define S_FW_IQ_CMD_IQO 3 #define M_FW_IQ_CMD_IQO 0x1 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) #define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) #define S_FW_IQ_CMD_IQCPRIO 2 #define M_FW_IQ_CMD_IQCPRIO 0x1 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) #define G_FW_IQ_CMD_IQCPRIO(x) \ (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) #define S_FW_IQ_CMD_IQESIZE 0 #define M_FW_IQ_CMD_IQESIZE 0x3 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) #define G_FW_IQ_CMD_IQESIZE(x) \ (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) #define S_FW_IQ_CMD_IQNS 31 #define M_FW_IQ_CMD_IQNS 0x1 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) #define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) #define S_FW_IQ_CMD_IQRO 30 #define M_FW_IQ_CMD_IQRO 0x1 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) #define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) #define S_FW_IQ_CMD_IQFLINTCONGEN 27 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) #define S_FW_IQ_CMD_IQFLINTISCSIC 26 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) #define S_FW_IQ_CMD_FL0CNGCHMAP 20 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) #define S_FW_IQ_CMD_FL0CACHELOCK 15 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) #define S_FW_IQ_CMD_FL0DBP 14 #define M_FW_IQ_CMD_FL0DBP 0x1 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) #define G_FW_IQ_CMD_FL0DBP(x) \ (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) #define S_FW_IQ_CMD_FL0DATANS 13 #define M_FW_IQ_CMD_FL0DATANS 0x1 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) #define G_FW_IQ_CMD_FL0DATANS(x) \ (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) #define S_FW_IQ_CMD_FL0DATARO 12 #define M_FW_IQ_CMD_FL0DATARO 0x1 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) #define G_FW_IQ_CMD_FL0DATARO(x) \ (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) #define S_FW_IQ_CMD_FL0CONGCIF 11 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) #define G_FW_IQ_CMD_FL0CONGCIF(x) \ (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) #define S_FW_IQ_CMD_FL0ONCHIP 10 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) #define G_FW_IQ_CMD_FL0ONCHIP(x) \ (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) #define S_FW_IQ_CMD_FL0STATUSPGNS 9 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) #define S_FW_IQ_CMD_FL0STATUSPGRO 8 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) #define S_FW_IQ_CMD_FL0FETCHNS 7 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) #define G_FW_IQ_CMD_FL0FETCHNS(x) \ (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) #define S_FW_IQ_CMD_FL0FETCHRO 6 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) #define G_FW_IQ_CMD_FL0FETCHRO(x) \ (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) #define S_FW_IQ_CMD_FL0CPRIO 3 #define M_FW_IQ_CMD_FL0CPRIO 0x1 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) #define G_FW_IQ_CMD_FL0CPRIO(x) \ (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) #define S_FW_IQ_CMD_FL0PADEN 2 #define M_FW_IQ_CMD_FL0PADEN 0x1 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) #define G_FW_IQ_CMD_FL0PADEN(x) \ (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) #define S_FW_IQ_CMD_FL0PACKEN 1 #define M_FW_IQ_CMD_FL0PACKEN 0x1 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) #define G_FW_IQ_CMD_FL0PACKEN(x) \ (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) #define S_FW_IQ_CMD_FL0CONGEN 0 #define M_FW_IQ_CMD_FL0CONGEN 0x1 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) #define G_FW_IQ_CMD_FL0CONGEN(x) \ (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) #define S_FW_IQ_CMD_FL0DCAEN 15 #define M_FW_IQ_CMD_FL0DCAEN 0x1 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) #define G_FW_IQ_CMD_FL0DCAEN(x) \ (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) #define S_FW_IQ_CMD_FL0DCACPU 10 #define M_FW_IQ_CMD_FL0DCACPU 0x1f #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) #define G_FW_IQ_CMD_FL0DCACPU(x) \ (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) #define S_FW_IQ_CMD_FL0FBMIN 7 #define M_FW_IQ_CMD_FL0FBMIN 0x7 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) #define G_FW_IQ_CMD_FL0FBMIN(x) \ (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) #define S_FW_IQ_CMD_FL0FBMAX 4 #define M_FW_IQ_CMD_FL0FBMAX 0x7 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) #define G_FW_IQ_CMD_FL0FBMAX(x) \ (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) #define S_FW_IQ_CMD_FL1CNGCHMAP 20 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) #define S_FW_IQ_CMD_FL1CACHELOCK 15 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) #define S_FW_IQ_CMD_FL1DBP 14 #define M_FW_IQ_CMD_FL1DBP 0x1 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) #define G_FW_IQ_CMD_FL1DBP(x) \ (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) #define S_FW_IQ_CMD_FL1DATANS 13 #define M_FW_IQ_CMD_FL1DATANS 0x1 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) #define G_FW_IQ_CMD_FL1DATANS(x) \ (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) #define S_FW_IQ_CMD_FL1DATARO 12 #define M_FW_IQ_CMD_FL1DATARO 0x1 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) #define G_FW_IQ_CMD_FL1DATARO(x) \ (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) #define S_FW_IQ_CMD_FL1CONGCIF 11 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) #define G_FW_IQ_CMD_FL1CONGCIF(x) \ (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) #define S_FW_IQ_CMD_FL1ONCHIP 10 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) #define G_FW_IQ_CMD_FL1ONCHIP(x) \ (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) #define S_FW_IQ_CMD_FL1STATUSPGNS 9 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) #define S_FW_IQ_CMD_FL1STATUSPGRO 8 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) #define S_FW_IQ_CMD_FL1FETCHNS 7 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) #define G_FW_IQ_CMD_FL1FETCHNS(x) \ (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) #define S_FW_IQ_CMD_FL1FETCHRO 6 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) #define G_FW_IQ_CMD_FL1FETCHRO(x) \ (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) #define S_FW_IQ_CMD_FL1CPRIO 3 #define M_FW_IQ_CMD_FL1CPRIO 0x1 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) #define G_FW_IQ_CMD_FL1CPRIO(x) \ (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) #define S_FW_IQ_CMD_FL1PADEN 2 #define M_FW_IQ_CMD_FL1PADEN 0x1 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) #define G_FW_IQ_CMD_FL1PADEN(x) \ (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) #define S_FW_IQ_CMD_FL1PACKEN 1 #define M_FW_IQ_CMD_FL1PACKEN 0x1 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) #define G_FW_IQ_CMD_FL1PACKEN(x) \ (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) #define S_FW_IQ_CMD_FL1CONGEN 0 #define M_FW_IQ_CMD_FL1CONGEN 0x1 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) #define G_FW_IQ_CMD_FL1CONGEN(x) \ (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) #define S_FW_IQ_CMD_FL1DCAEN 15 #define M_FW_IQ_CMD_FL1DCAEN 0x1 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) #define G_FW_IQ_CMD_FL1DCAEN(x) \ (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) #define S_FW_IQ_CMD_FL1DCACPU 10 #define M_FW_IQ_CMD_FL1DCACPU 0x1f #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) #define G_FW_IQ_CMD_FL1DCACPU(x) \ (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) #define S_FW_IQ_CMD_FL1FBMIN 7 #define M_FW_IQ_CMD_FL1FBMIN 0x7 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) #define G_FW_IQ_CMD_FL1FBMIN(x) \ (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) #define S_FW_IQ_CMD_FL1FBMAX 4 #define M_FW_IQ_CMD_FL1FBMAX 0x7 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) #define G_FW_IQ_CMD_FL1FBMAX(x) \ (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) struct fw_eq_mngt_cmd { __be32 op_to_vfn; __be32 alloc_to_len16; __be32 cmpliqid_eqid; __be32 physeqid_pkd; __be32 fetchszm_to_iqid; __be32 dcaen_to_eqsize; __be64 eqaddr; }; #define S_FW_EQ_MNGT_CMD_PFN 8 #define M_FW_EQ_MNGT_CMD_PFN 0x7 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) #define G_FW_EQ_MNGT_CMD_PFN(x) \ (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) #define S_FW_EQ_MNGT_CMD_VFN 0 #define M_FW_EQ_MNGT_CMD_VFN 0xff #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) #define G_FW_EQ_MNGT_CMD_VFN(x) \ (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) #define S_FW_EQ_MNGT_CMD_ALLOC 31 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) #define S_FW_EQ_MNGT_CMD_FREE 30 #define M_FW_EQ_MNGT_CMD_FREE 0x1 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) #define G_FW_EQ_MNGT_CMD_FREE(x) \ (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) #define S_FW_EQ_MNGT_CMD_MODIFY 29 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) #define S_FW_EQ_MNGT_CMD_EQSTART 28 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) #define S_FW_EQ_MNGT_CMD_EQSTOP 27 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) #define S_FW_EQ_MNGT_CMD_EQID 0 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) #define G_FW_EQ_MNGT_CMD_EQID(x) \ (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) #define S_FW_EQ_MNGT_CMD_FETCHNS 23 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) #define S_FW_EQ_MNGT_CMD_FETCHRO 22 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) #define S_FW_EQ_MNGT_CMD_CPRIO 19 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) #define S_FW_EQ_MNGT_CMD_ONCHIP 18 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) #define S_FW_EQ_MNGT_CMD_PCIECHN 16 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) #define S_FW_EQ_MNGT_CMD_IQID 0 #define M_FW_EQ_MNGT_CMD_IQID 0xffff #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) #define G_FW_EQ_MNGT_CMD_IQID(x) \ (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) #define S_FW_EQ_MNGT_CMD_DCAEN 31 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) #define S_FW_EQ_MNGT_CMD_DCACPU 26 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) #define S_FW_EQ_MNGT_CMD_FBMIN 23 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) #define S_FW_EQ_MNGT_CMD_FBMAX 20 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) #define S_FW_EQ_MNGT_CMD_EQSIZE 0 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) struct fw_eq_eth_cmd { __be32 op_to_vfn; __be32 alloc_to_len16; __be32 eqid_pkd; __be32 physeqid_pkd; __be32 fetchszm_to_iqid; __be32 dcaen_to_eqsize; __be64 eqaddr; __be32 viid_pkd; __be32 r8_lo; __be64 r9; }; #define S_FW_EQ_ETH_CMD_PFN 8 #define M_FW_EQ_ETH_CMD_PFN 0x7 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) #define G_FW_EQ_ETH_CMD_PFN(x) \ (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) #define S_FW_EQ_ETH_CMD_VFN 0 #define M_FW_EQ_ETH_CMD_VFN 0xff #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) #define G_FW_EQ_ETH_CMD_VFN(x) \ (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) #define S_FW_EQ_ETH_CMD_ALLOC 31 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) #define G_FW_EQ_ETH_CMD_ALLOC(x) \ (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) #define S_FW_EQ_ETH_CMD_FREE 30 #define M_FW_EQ_ETH_CMD_FREE 0x1 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) #define G_FW_EQ_ETH_CMD_FREE(x) \ (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) #define S_FW_EQ_ETH_CMD_MODIFY 29 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) #define G_FW_EQ_ETH_CMD_MODIFY(x) \ (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) #define S_FW_EQ_ETH_CMD_EQSTART 28 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) #define G_FW_EQ_ETH_CMD_EQSTART(x) \ (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) #define S_FW_EQ_ETH_CMD_EQSTOP 27 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) #define S_FW_EQ_ETH_CMD_EQID 0 #define M_FW_EQ_ETH_CMD_EQID 0xfffff #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) #define G_FW_EQ_ETH_CMD_EQID(x) \ (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) #define S_FW_EQ_ETH_CMD_PHYSEQID 0 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) #define S_FW_EQ_ETH_CMD_FETCHSZM 26 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) #define S_FW_EQ_ETH_CMD_FETCHNS 23 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) #define S_FW_EQ_ETH_CMD_FETCHRO 22 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) #define S_FW_EQ_ETH_CMD_CPRIO 19 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) #define G_FW_EQ_ETH_CMD_CPRIO(x) \ (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) #define S_FW_EQ_ETH_CMD_ONCHIP 18 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) #define S_FW_EQ_ETH_CMD_PCIECHN 16 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) #define S_FW_EQ_ETH_CMD_IQID 0 #define M_FW_EQ_ETH_CMD_IQID 0xffff #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) #define G_FW_EQ_ETH_CMD_IQID(x) \ (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) #define S_FW_EQ_ETH_CMD_DCAEN 31 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) #define G_FW_EQ_ETH_CMD_DCAEN(x) \ (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) #define S_FW_EQ_ETH_CMD_DCACPU 26 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) #define G_FW_EQ_ETH_CMD_DCACPU(x) \ (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) #define S_FW_EQ_ETH_CMD_FBMIN 23 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) #define G_FW_EQ_ETH_CMD_FBMIN(x) \ (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) #define S_FW_EQ_ETH_CMD_FBMAX 20 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) #define G_FW_EQ_ETH_CMD_FBMAX(x) \ (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) #define S_FW_EQ_ETH_CMD_EQSIZE 0 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) #define S_FW_EQ_ETH_CMD_VIID 16 #define M_FW_EQ_ETH_CMD_VIID 0xfff #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) #define G_FW_EQ_ETH_CMD_VIID(x) \ (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) struct fw_eq_ctrl_cmd { __be32 op_to_vfn; __be32 alloc_to_len16; __be32 cmpliqid_eqid; __be32 physeqid_pkd; __be32 fetchszm_to_iqid; __be32 dcaen_to_eqsize; __be64 eqaddr; }; #define S_FW_EQ_CTRL_CMD_PFN 8 #define M_FW_EQ_CTRL_CMD_PFN 0x7 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) #define G_FW_EQ_CTRL_CMD_PFN(x) \ (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) #define S_FW_EQ_CTRL_CMD_VFN 0 #define M_FW_EQ_CTRL_CMD_VFN 0xff #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) #define G_FW_EQ_CTRL_CMD_VFN(x) \ (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) #define S_FW_EQ_CTRL_CMD_ALLOC 31 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) #define S_FW_EQ_CTRL_CMD_FREE 30 #define M_FW_EQ_CTRL_CMD_FREE 0x1 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) #define G_FW_EQ_CTRL_CMD_FREE(x) \ (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) #define S_FW_EQ_CTRL_CMD_MODIFY 29 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) #define S_FW_EQ_CTRL_CMD_EQSTART 28 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) #define S_FW_EQ_CTRL_CMD_EQSTOP 27 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) #define S_FW_EQ_CTRL_CMD_EQID 0 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) #define G_FW_EQ_CTRL_CMD_EQID(x) \ (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) #define S_FW_EQ_CTRL_CMD_FETCHNS 23 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) #define S_FW_EQ_CTRL_CMD_FETCHRO 22 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) #define S_FW_EQ_CTRL_CMD_CPRIO 19 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) #define S_FW_EQ_CTRL_CMD_ONCHIP 18 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) #define S_FW_EQ_CTRL_CMD_PCIECHN 16 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) #define S_FW_EQ_CTRL_CMD_IQID 0 #define M_FW_EQ_CTRL_CMD_IQID 0xffff #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) #define G_FW_EQ_CTRL_CMD_IQID(x) \ (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) #define S_FW_EQ_CTRL_CMD_DCAEN 31 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) #define S_FW_EQ_CTRL_CMD_DCACPU 26 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) #define S_FW_EQ_CTRL_CMD_FBMIN 23 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) #define S_FW_EQ_CTRL_CMD_FBMAX 20 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) #define S_FW_EQ_CTRL_CMD_EQSIZE 0 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) struct fw_eq_ofld_cmd { __be32 op_to_vfn; __be32 alloc_to_len16; __be32 eqid_pkd; __be32 physeqid_pkd; __be32 fetchszm_to_iqid; __be32 dcaen_to_eqsize; __be64 eqaddr; }; #define S_FW_EQ_OFLD_CMD_PFN 8 #define M_FW_EQ_OFLD_CMD_PFN 0x7 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) #define G_FW_EQ_OFLD_CMD_PFN(x) \ (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) #define S_FW_EQ_OFLD_CMD_VFN 0 #define M_FW_EQ_OFLD_CMD_VFN 0xff #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) #define G_FW_EQ_OFLD_CMD_VFN(x) \ (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) #define S_FW_EQ_OFLD_CMD_ALLOC 31 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) #define S_FW_EQ_OFLD_CMD_FREE 30 #define M_FW_EQ_OFLD_CMD_FREE 0x1 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) #define G_FW_EQ_OFLD_CMD_FREE(x) \ (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) #define S_FW_EQ_OFLD_CMD_MODIFY 29 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) #define S_FW_EQ_OFLD_CMD_EQSTART 28 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) #define S_FW_EQ_OFLD_CMD_EQSTOP 27 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) #define S_FW_EQ_OFLD_CMD_EQID 0 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) #define G_FW_EQ_OFLD_CMD_EQID(x) \ (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) #define S_FW_EQ_OFLD_CMD_FETCHNS 23 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) #define S_FW_EQ_OFLD_CMD_FETCHRO 22 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) #define S_FW_EQ_OFLD_CMD_CPRIO 19 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) #define S_FW_EQ_OFLD_CMD_ONCHIP 18 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) #define S_FW_EQ_OFLD_CMD_PCIECHN 16 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) #define S_FW_EQ_OFLD_CMD_IQID 0 #define M_FW_EQ_OFLD_CMD_IQID 0xffff #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) #define G_FW_EQ_OFLD_CMD_IQID(x) \ (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) #define S_FW_EQ_OFLD_CMD_DCAEN 31 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) #define S_FW_EQ_OFLD_CMD_DCACPU 26 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) #define S_FW_EQ_OFLD_CMD_FBMIN 23 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) #define S_FW_EQ_OFLD_CMD_FBMAX 20 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) #define S_FW_EQ_OFLD_CMD_EQSIZE 0 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) /* Macros for VIID parsing: VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ #define S_FW_VIID_PFN 8 #define M_FW_VIID_PFN 0x7 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) #define S_FW_VIID_VIVLD 7 #define M_FW_VIID_VIVLD 0x1 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) #define S_FW_VIID_VIN 0 #define M_FW_VIID_VIN 0x7F #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) enum fw_vi_func { FW_VI_FUNC_ETH, FW_VI_FUNC_OFLD, FW_VI_FUNC_IWARP, FW_VI_FUNC_OPENISCSI, FW_VI_FUNC_OPENFCOE, FW_VI_FUNC_FOISCSI, FW_VI_FUNC_FOFCOE, FW_VI_FUNC_FW, }; struct fw_vi_cmd { __be32 op_to_vfn; __be32 alloc_to_len16; __be16 type_to_viid; __u8 mac[6]; __u8 portid_pkd; __u8 nmac; __u8 nmac0[6]; __be16 rsssize_pkd; __u8 nmac1[6]; __be16 idsiiq_pkd; __u8 nmac2[6]; __be16 idseiq_pkd; __u8 nmac3[6]; __be64 r9; __be64 r10; }; #define S_FW_VI_CMD_PFN 8 #define M_FW_VI_CMD_PFN 0x7 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) #define S_FW_VI_CMD_VFN 0 #define M_FW_VI_CMD_VFN 0xff #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) #define S_FW_VI_CMD_ALLOC 31 #define M_FW_VI_CMD_ALLOC 0x1 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) #define G_FW_VI_CMD_ALLOC(x) \ (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) #define S_FW_VI_CMD_FREE 30 #define M_FW_VI_CMD_FREE 0x1 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) #define S_FW_VI_CMD_TYPE 15 #define M_FW_VI_CMD_TYPE 0x1 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) #define S_FW_VI_CMD_FUNC 12 #define M_FW_VI_CMD_FUNC 0x7 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) #define S_FW_VI_CMD_VIID 0 #define M_FW_VI_CMD_VIID 0xfff #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) #define S_FW_VI_CMD_PORTID 4 #define M_FW_VI_CMD_PORTID 0xf #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) #define G_FW_VI_CMD_PORTID(x) \ (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) #define S_FW_VI_CMD_RSSSIZE 0 #define M_FW_VI_CMD_RSSSIZE 0x7ff #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) #define G_FW_VI_CMD_RSSSIZE(x) \ (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) #define S_FW_VI_CMD_IDSIIQ 0 #define M_FW_VI_CMD_IDSIIQ 0x3ff #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) #define G_FW_VI_CMD_IDSIIQ(x) \ (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) #define S_FW_VI_CMD_IDSEIQ 0 #define M_FW_VI_CMD_IDSEIQ 0x3ff #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) #define G_FW_VI_CMD_IDSEIQ(x) \ (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) /* Special VI_MAC command index ids */ #define FW_VI_MAC_ADD_MAC 0x3FF #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE #define FW_VI_MAC_MAC_BASED_FREE 0x3FD #define FW_CLS_TCAM_NUM_ENTRIES 336 enum fw_vi_mac_smac { FW_VI_MAC_MPS_TCAM_ENTRY, FW_VI_MAC_MPS_TCAM_ONLY, FW_VI_MAC_SMT_ONLY, FW_VI_MAC_SMT_AND_MPSTCAM }; enum fw_vi_mac_result { FW_VI_MAC_R_SUCCESS, FW_VI_MAC_R_F_NONEXISTENT_NOMEM, FW_VI_MAC_R_SMAC_FAIL, FW_VI_MAC_R_F_ACL_CHECK }; struct fw_vi_mac_cmd { __be32 op_to_viid; __be32 freemacs_to_len16; union fw_vi_mac { struct fw_vi_mac_exact { __be16 valid_to_idx; __u8 macaddr[6]; } exact[7]; struct fw_vi_mac_hash { __be64 hashvec; } hash; } u; }; #define S_FW_VI_MAC_CMD_VIID 0 #define M_FW_VI_MAC_CMD_VIID 0xfff #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) #define G_FW_VI_MAC_CMD_VIID(x) \ (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) #define S_FW_VI_MAC_CMD_FREEMACS 31 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) #define G_FW_VI_MAC_CMD_FREEMACS(x) \ (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) #define S_FW_VI_MAC_CMD_HASHVECEN 23 #define M_FW_VI_MAC_CMD_HASHVECEN 0x1 #define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) #define G_FW_VI_MAC_CMD_HASHVECEN(x) \ (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) #define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) #define S_FW_VI_MAC_CMD_HASHUNIEN 22 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) #define S_FW_VI_MAC_CMD_VALID 15 #define M_FW_VI_MAC_CMD_VALID 0x1 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) #define G_FW_VI_MAC_CMD_VALID(x) \ (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) #define S_FW_VI_MAC_CMD_PRIO 12 #define M_FW_VI_MAC_CMD_PRIO 0x7 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) #define G_FW_VI_MAC_CMD_PRIO(x) \ (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) #define S_FW_VI_MAC_CMD_IDX 0 #define M_FW_VI_MAC_CMD_IDX 0x3ff #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) #define G_FW_VI_MAC_CMD_IDX(x) \ (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) /* T4 max MTU supported */ #define T4_MAX_MTU_SUPPORTED 9600 #define FW_RXMODE_MTU_NO_CHG 65535 struct fw_vi_rxmode_cmd { __be32 op_to_viid; __be32 retval_len16; __be32 mtu_to_vlanexen; __be32 r4_lo; }; #define S_FW_VI_RXMODE_CMD_VIID 0 #define M_FW_VI_RXMODE_CMD_VIID 0xfff #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) #define G_FW_VI_RXMODE_CMD_VIID(x) \ (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) #define S_FW_VI_RXMODE_CMD_MTU 16 #define M_FW_VI_RXMODE_CMD_MTU 0xffff #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) #define G_FW_VI_RXMODE_CMD_MTU(x) \ (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) struct fw_vi_enable_cmd { __be32 op_to_viid; __be32 ien_to_len16; __be16 blinkdur; __be16 r3; __be32 r4; }; #define S_FW_VI_ENABLE_CMD_VIID 0 #define M_FW_VI_ENABLE_CMD_VIID 0xfff #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) #define G_FW_VI_ENABLE_CMD_VIID(x) \ (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) #define S_FW_VI_ENABLE_CMD_IEN 31 #define M_FW_VI_ENABLE_CMD_IEN 0x1 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) #define G_FW_VI_ENABLE_CMD_IEN(x) \ (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) #define S_FW_VI_ENABLE_CMD_EEN 30 #define M_FW_VI_ENABLE_CMD_EEN 0x1 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) #define G_FW_VI_ENABLE_CMD_EEN(x) \ (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) #define S_FW_VI_ENABLE_CMD_LED 29 #define M_FW_VI_ENABLE_CMD_LED 0x1 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) #define G_FW_VI_ENABLE_CMD_LED(x) \ (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) /* VI VF stats offset definitions */ #define VI_VF_NUM_STATS 16 enum fw_vi_stats_vf_index { FW_VI_VF_STAT_TX_BCAST_BYTES_IX, FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, FW_VI_VF_STAT_TX_MCAST_BYTES_IX, FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, FW_VI_VF_STAT_TX_UCAST_BYTES_IX, FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, FW_VI_VF_STAT_TX_DROP_FRAMES_IX, FW_VI_VF_STAT_TX_OFLD_BYTES_IX, FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, FW_VI_VF_STAT_RX_BCAST_BYTES_IX, FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, FW_VI_VF_STAT_RX_MCAST_BYTES_IX, FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, FW_VI_VF_STAT_RX_UCAST_BYTES_IX, FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, FW_VI_VF_STAT_RX_ERR_FRAMES_IX }; /* VI PF stats offset definitions */ #define VI_PF_NUM_STATS 17 enum fw_vi_stats_pf_index { FW_VI_PF_STAT_TX_BCAST_BYTES_IX, FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, FW_VI_PF_STAT_TX_MCAST_BYTES_IX, FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, FW_VI_PF_STAT_TX_UCAST_BYTES_IX, FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, FW_VI_PF_STAT_TX_OFLD_BYTES_IX, FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, FW_VI_PF_STAT_RX_BYTES_IX, FW_VI_PF_STAT_RX_FRAMES_IX, FW_VI_PF_STAT_RX_BCAST_BYTES_IX, FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, FW_VI_PF_STAT_RX_MCAST_BYTES_IX, FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, FW_VI_PF_STAT_RX_UCAST_BYTES_IX, FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, FW_VI_PF_STAT_RX_ERR_FRAMES_IX }; struct fw_vi_stats_cmd { __be32 op_to_viid; __be32 retval_len16; union fw_vi_stats { struct fw_vi_stats_ctl { __be16 nstats_ix; __be16 r6; __be32 r7; __be64 stat0; __be64 stat1; __be64 stat2; __be64 stat3; __be64 stat4; __be64 stat5; } ctl; struct fw_vi_stats_pf { __be64 tx_bcast_bytes; __be64 tx_bcast_frames; __be64 tx_mcast_bytes; __be64 tx_mcast_frames; __be64 tx_ucast_bytes; __be64 tx_ucast_frames; __be64 tx_offload_bytes; __be64 tx_offload_frames; __be64 rx_pf_bytes; __be64 rx_pf_frames; __be64 rx_bcast_bytes; __be64 rx_bcast_frames; __be64 rx_mcast_bytes; __be64 rx_mcast_frames; __be64 rx_ucast_bytes; __be64 rx_ucast_frames; __be64 rx_err_frames; } pf; struct fw_vi_stats_vf { __be64 tx_bcast_bytes; __be64 tx_bcast_frames; __be64 tx_mcast_bytes; __be64 tx_mcast_frames; __be64 tx_ucast_bytes; __be64 tx_ucast_frames; __be64 tx_drop_frames; __be64 tx_offload_bytes; __be64 tx_offload_frames; __be64 rx_bcast_bytes; __be64 rx_bcast_frames; __be64 rx_mcast_bytes; __be64 rx_mcast_frames; __be64 rx_ucast_bytes; __be64 rx_ucast_frames; __be64 rx_err_frames; } vf; } u; }; #define S_FW_VI_STATS_CMD_VIID 0 #define M_FW_VI_STATS_CMD_VIID 0xfff #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) #define G_FW_VI_STATS_CMD_VIID(x) \ (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) #define S_FW_VI_STATS_CMD_NSTATS 12 #define M_FW_VI_STATS_CMD_NSTATS 0x7 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) #define G_FW_VI_STATS_CMD_NSTATS(x) \ (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) #define S_FW_VI_STATS_CMD_IX 0 #define M_FW_VI_STATS_CMD_IX 0x1f #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) #define G_FW_VI_STATS_CMD_IX(x) \ (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) struct fw_acl_mac_cmd { __be32 op_to_vfn; __be32 en_to_len16; __u8 nmac; __u8 r3[7]; __be16 r4; __u8 macaddr0[6]; __be16 r5; __u8 macaddr1[6]; __be16 r6; __u8 macaddr2[6]; __be16 r7; __u8 macaddr3[6]; }; #define S_FW_ACL_MAC_CMD_PFN 8 #define M_FW_ACL_MAC_CMD_PFN 0x7 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) #define G_FW_ACL_MAC_CMD_PFN(x) \ (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) #define S_FW_ACL_MAC_CMD_VFN 0 #define M_FW_ACL_MAC_CMD_VFN 0xff #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) #define G_FW_ACL_MAC_CMD_VFN(x) \ (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) #define S_FW_ACL_MAC_CMD_EN 31 #define M_FW_ACL_MAC_CMD_EN 0x1 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) #define G_FW_ACL_MAC_CMD_EN(x) \ (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) struct fw_acl_vlan_cmd { __be32 op_to_vfn; __be32 en_to_len16; __u8 nvlan; __u8 dropnovlan_fm; __u8 r3_lo[6]; __be16 vlanid[16]; }; #define S_FW_ACL_VLAN_CMD_PFN 8 #define M_FW_ACL_VLAN_CMD_PFN 0x7 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) #define G_FW_ACL_VLAN_CMD_PFN(x) \ (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) #define S_FW_ACL_VLAN_CMD_VFN 0 #define M_FW_ACL_VLAN_CMD_VFN 0xff #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) #define G_FW_ACL_VLAN_CMD_VFN(x) \ (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) #define S_FW_ACL_VLAN_CMD_EN 31 #define M_FW_ACL_VLAN_CMD_EN 0x1 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) #define G_FW_ACL_VLAN_CMD_EN(x) \ (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) #define S_FW_ACL_VLAN_CMD_FM 6 #define M_FW_ACL_VLAN_CMD_FM 0x1 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) #define G_FW_ACL_VLAN_CMD_FM(x) \ (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) /* port capabilities bitmap */ enum fw_port_cap { FW_PORT_CAP_SPEED_100M = 0x0001, FW_PORT_CAP_SPEED_1G = 0x0002, FW_PORT_CAP_SPEED_2_5G = 0x0004, FW_PORT_CAP_SPEED_10G = 0x0008, FW_PORT_CAP_SPEED_40G = 0x0010, FW_PORT_CAP_SPEED_100G = 0x0020, FW_PORT_CAP_FC_RX = 0x0040, FW_PORT_CAP_FC_TX = 0x0080, FW_PORT_CAP_ANEG = 0x0100, FW_PORT_CAP_MDIX = 0x0200, FW_PORT_CAP_MDIAUTO = 0x0400, FW_PORT_CAP_FEC = 0x0800, FW_PORT_CAP_TECHKR = 0x1000, FW_PORT_CAP_TECHKX4 = 0x2000, }; +#define S_FW_PORT_AUXLINFO_MDI 3 +#define M_FW_PORT_AUXLINFO_MDI 0x3 +#define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) +#define G_FW_PORT_AUXLINFO_MDI(x) \ + (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) + +#define S_FW_PORT_AUXLINFO_KX4 2 +#define M_FW_PORT_AUXLINFO_KX4 0x1 +#define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) +#define G_FW_PORT_AUXLINFO_KX4(x) \ + (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) +#define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) + +#define S_FW_PORT_AUXLINFO_KR 1 +#define M_FW_PORT_AUXLINFO_KR 0x1 +#define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) +#define G_FW_PORT_AUXLINFO_KR(x) \ + (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) +#define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) + +#define S_FW_PORT_AUXLINFO_FEC 0 +#define M_FW_PORT_AUXLINFO_FEC 0x1 +#define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) +#define G_FW_PORT_AUXLINFO_FEC(x) \ + (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) +#define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) + +#define S_FW_PORT_RCAP_AUX 11 +#define M_FW_PORT_RCAP_AUX 0x7 +#define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) +#define G_FW_PORT_RCAP_AUX(x) \ + (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) + #define S_FW_PORT_CAP_SPEED 0 #define M_FW_PORT_CAP_SPEED 0x3f #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) #define G_FW_PORT_CAP_SPEED(x) \ (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) #define S_FW_PORT_CAP_FC 6 #define M_FW_PORT_CAP_FC 0x3 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) #define G_FW_PORT_CAP_FC(x) \ (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) #define S_FW_PORT_CAP_ANEG 8 #define M_FW_PORT_CAP_ANEG 0x1 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) #define G_FW_PORT_CAP_ANEG(x) \ (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) enum fw_port_mdi { FW_PORT_CAP_MDI_UNCHANGED, FW_PORT_CAP_MDI_AUTO, FW_PORT_CAP_MDI_F_STRAIGHT, FW_PORT_CAP_MDI_F_CROSSOVER }; #define S_FW_PORT_CAP_MDI 9 #define M_FW_PORT_CAP_MDI 3 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) enum fw_port_action { FW_PORT_ACTION_L1_CFG = 0x0001, FW_PORT_ACTION_L2_CFG = 0x0002, FW_PORT_ACTION_GET_PORT_INFO = 0x0003, FW_PORT_ACTION_L2_PPP_CFG = 0x0004, FW_PORT_ACTION_L2_DCB_CFG = 0x0005, FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021, FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023, FW_PORT_ACTION_L1_EXT_LPBK = 0x0026, FW_PORT_ACTION_PHY_RESET = 0x0040, FW_PORT_ACTION_PMA_RESET = 0x0041, FW_PORT_ACTION_PCS_RESET = 0x0042, FW_PORT_ACTION_PHYXS_RESET = 0x0043, FW_PORT_ACTION_DTEXS_REEST = 0x0044, FW_PORT_ACTION_AN_RESET = 0x0045 }; enum fw_port_l2cfg_ctlbf { FW_PORT_L2_CTLBF_OVLAN0 = 0x01, FW_PORT_L2_CTLBF_OVLAN1 = 0x02, FW_PORT_L2_CTLBF_OVLAN2 = 0x04, FW_PORT_L2_CTLBF_OVLAN3 = 0x08, FW_PORT_L2_CTLBF_IVLAN = 0x10, FW_PORT_L2_CTLBF_TXIPG = 0x20, FW_PORT_L2_CTLBF_MTU = 0x40 }; +enum fw_port_dcb_cfg { + FW_PORT_DCB_CFG_PG = 0x01, + FW_PORT_DCB_CFG_PFC = 0x02, + FW_PORT_DCB_CFG_APPL = 0x04 +}; + +enum fw_port_dcb_cfg_rc { + FW_PORT_DCB_CFG_SUCCESS = 0x0, + FW_PORT_DCB_CFG_ERROR = 0x1 +}; + enum fw_port_dcb_type { FW_PORT_DCB_TYPE_PGID = 0x00, FW_PORT_DCB_TYPE_PGRATE = 0x01, FW_PORT_DCB_TYPE_PRIORATE = 0x02, - FW_PORT_DCB_TYPE_PFC = 0x03 + FW_PORT_DCB_TYPE_PFC = 0x03, + FW_PORT_DCB_TYPE_APP_ID = 0x04, }; struct fw_port_cmd { __be32 op_to_portid; __be32 action_to_len16; union fw_port { struct fw_port_l1cfg { __be32 rcap; __be32 r; } l1cfg; struct fw_port_l2cfg { __u8 ctlbf; __u8 ovlan3_to_ivlan0; __be16 ivlantype; __be16 txipg_force_pinfo; __be16 mtu; __be16 ovlan0mask; __be16 ovlan0type; __be16 ovlan1mask; __be16 ovlan1type; __be16 ovlan2mask; __be16 ovlan2type; __be16 ovlan3mask; __be16 ovlan3type; } l2cfg; struct fw_port_info { __be32 lstatus_to_modtype; __be16 pcap; __be16 acap; __be16 mtu; __u8 cbllen; - __u8 r7; + __u8 auxlinfo; __be32 r8; __be64 r9; } info; union fw_port_dcb { struct fw_port_dcb_pgid { __u8 type; __u8 apply_pkd; __u8 r10_lo[2]; __be32 pgid; __be64 r11; } pgid; struct fw_port_dcb_pgrate { __u8 type; __u8 apply_pkd; __u8 r10_lo[6]; __u8 pgrate[8]; } pgrate; struct fw_port_dcb_priorate { __u8 type; __u8 apply_pkd; __u8 r10_lo[6]; __u8 strict_priorate[8]; } priorate; struct fw_port_dcb_pfc { __u8 type; __u8 pfcen; __be16 r10[3]; __be64 r11; } pfc; + struct fw_port_app_priority { + __u8 type; + __u8 r10_lo[3]; + __u8 prio; + __u8 sel; + __be16 protocolid; + __u8 r12[8]; + } app_priority; } dcb; } u; }; #define S_FW_PORT_CMD_READ 22 #define M_FW_PORT_CMD_READ 0x1 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) #define G_FW_PORT_CMD_READ(x) \ (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) #define S_FW_PORT_CMD_PORTID 0 #define M_FW_PORT_CMD_PORTID 0xf #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) #define G_FW_PORT_CMD_PORTID(x) \ (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) #define S_FW_PORT_CMD_ACTION 16 #define M_FW_PORT_CMD_ACTION 0xffff #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) #define G_FW_PORT_CMD_ACTION(x) \ (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) #define S_FW_PORT_CMD_OVLAN3 7 #define M_FW_PORT_CMD_OVLAN3 0x1 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) #define G_FW_PORT_CMD_OVLAN3(x) \ (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) #define S_FW_PORT_CMD_OVLAN2 6 #define M_FW_PORT_CMD_OVLAN2 0x1 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) #define G_FW_PORT_CMD_OVLAN2(x) \ (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) #define S_FW_PORT_CMD_OVLAN1 5 #define M_FW_PORT_CMD_OVLAN1 0x1 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) #define G_FW_PORT_CMD_OVLAN1(x) \ (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) #define S_FW_PORT_CMD_OVLAN0 4 #define M_FW_PORT_CMD_OVLAN0 0x1 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) #define G_FW_PORT_CMD_OVLAN0(x) \ (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) #define S_FW_PORT_CMD_IVLAN0 3 #define M_FW_PORT_CMD_IVLAN0 0x1 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) #define G_FW_PORT_CMD_IVLAN0(x) \ (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) #define S_FW_PORT_CMD_TXIPG 3 #define M_FW_PORT_CMD_TXIPG 0x1fff #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) #define G_FW_PORT_CMD_TXIPG(x) \ (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) #define S_FW_PORT_CMD_FORCE_PINFO 0 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) #define G_FW_PORT_CMD_FORCE_PINFO(x) \ (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) #define S_FW_PORT_CMD_LSTATUS 31 #define M_FW_PORT_CMD_LSTATUS 0x1 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) #define G_FW_PORT_CMD_LSTATUS(x) \ (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) #define S_FW_PORT_CMD_LSPEED 24 #define M_FW_PORT_CMD_LSPEED 0x3f #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) #define G_FW_PORT_CMD_LSPEED(x) \ (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) #define S_FW_PORT_CMD_TXPAUSE 23 #define M_FW_PORT_CMD_TXPAUSE 0x1 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) #define G_FW_PORT_CMD_TXPAUSE(x) \ (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) #define S_FW_PORT_CMD_RXPAUSE 22 #define M_FW_PORT_CMD_RXPAUSE 0x1 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) #define G_FW_PORT_CMD_RXPAUSE(x) \ (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) #define S_FW_PORT_CMD_MDIOCAP 21 #define M_FW_PORT_CMD_MDIOCAP 0x1 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) #define G_FW_PORT_CMD_MDIOCAP(x) \ (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) #define S_FW_PORT_CMD_MDIOADDR 16 #define M_FW_PORT_CMD_MDIOADDR 0x1f #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) #define G_FW_PORT_CMD_MDIOADDR(x) \ (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) #define S_FW_PORT_CMD_LPTXPAUSE 15 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) #define G_FW_PORT_CMD_LPTXPAUSE(x) \ (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) #define S_FW_PORT_CMD_LPRXPAUSE 14 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) #define G_FW_PORT_CMD_LPRXPAUSE(x) \ (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) #define S_FW_PORT_CMD_PTYPE 8 #define M_FW_PORT_CMD_PTYPE 0x1f #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) #define G_FW_PORT_CMD_PTYPE(x) \ (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) #define S_FW_PORT_CMD_LINKDNRC 5 #define M_FW_PORT_CMD_LINKDNRC 0x7 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) #define G_FW_PORT_CMD_LINKDNRC(x) \ (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) #define S_FW_PORT_CMD_MODTYPE 0 #define M_FW_PORT_CMD_MODTYPE 0x1f #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) #define G_FW_PORT_CMD_MODTYPE(x) \ (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) #define S_FW_PORT_CMD_APPLY 7 #define M_FW_PORT_CMD_APPLY 0x1 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) #define G_FW_PORT_CMD_APPLY(x) \ (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) #define S_FW_PORT_CMD_APPLY 7 #define M_FW_PORT_CMD_APPLY 0x1 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) #define G_FW_PORT_CMD_APPLY(x) \ (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) #define S_FW_PORT_CMD_APPLY 7 #define M_FW_PORT_CMD_APPLY 0x1 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) #define G_FW_PORT_CMD_APPLY(x) \ (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) /* * These are configured into the VPD and hence tools that generate * VPD may use this enumeration. * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed */ enum fw_port_type { FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE }; /* These are read from module's EEPROM and determined once the module is inserted. */ enum fw_port_module_type { FW_PORT_MOD_TYPE_NA = 0x0, FW_PORT_MOD_TYPE_LR = 0x1, FW_PORT_MOD_TYPE_SR = 0x2, FW_PORT_MOD_TYPE_ER = 0x3, FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, FW_PORT_MOD_TYPE_LRM = 0x6, FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE }; /* used by FW and tools may use this to generate VPD */ enum fw_port_mod_sub_type { FW_PORT_MOD_SUB_TYPE_NA, FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, /* * The following will never been in the VPD. They are TWINAX cable * lengths decoded from SFP+ module i2c PROMs. These should almost * certainly go somewhere else ... */ FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, }; /* link down reason codes (3b) */ enum fw_port_link_dn_rc { FW_PORT_LINK_DN_RC_NONE, FW_PORT_LINK_DN_RC_REMFLT, FW_PORT_LINK_DN_ANEG_F, FW_PORT_LINK_DN_MS_RES_F, FW_PORT_LINK_DN_UNKNOWN }; /* port stats */ #define FW_NUM_PORT_STATS 50 #define FW_NUM_PORT_TX_STATS 23 #define FW_NUM_PORT_RX_STATS 27 enum fw_port_stats_tx_index { FW_STAT_TX_PORT_BYTES_IX, FW_STAT_TX_PORT_FRAMES_IX, FW_STAT_TX_PORT_BCAST_IX, FW_STAT_TX_PORT_MCAST_IX, FW_STAT_TX_PORT_UCAST_IX, FW_STAT_TX_PORT_ERROR_IX, FW_STAT_TX_PORT_64B_IX, FW_STAT_TX_PORT_65B_127B_IX, FW_STAT_TX_PORT_128B_255B_IX, FW_STAT_TX_PORT_256B_511B_IX, FW_STAT_TX_PORT_512B_1023B_IX, FW_STAT_TX_PORT_1024B_1518B_IX, FW_STAT_TX_PORT_1519B_MAX_IX, FW_STAT_TX_PORT_DROP_IX, FW_STAT_TX_PORT_PAUSE_IX, FW_STAT_TX_PORT_PPP0_IX, FW_STAT_TX_PORT_PPP1_IX, FW_STAT_TX_PORT_PPP2_IX, FW_STAT_TX_PORT_PPP3_IX, FW_STAT_TX_PORT_PPP4_IX, FW_STAT_TX_PORT_PPP5_IX, FW_STAT_TX_PORT_PPP6_IX, FW_STAT_TX_PORT_PPP7_IX }; enum fw_port_stat_rx_index { FW_STAT_RX_PORT_BYTES_IX, FW_STAT_RX_PORT_FRAMES_IX, FW_STAT_RX_PORT_BCAST_IX, FW_STAT_RX_PORT_MCAST_IX, FW_STAT_RX_PORT_UCAST_IX, FW_STAT_RX_PORT_MTU_ERROR_IX, FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, FW_STAT_RX_PORT_CRC_ERROR_IX, FW_STAT_RX_PORT_LEN_ERROR_IX, FW_STAT_RX_PORT_SYM_ERROR_IX, FW_STAT_RX_PORT_64B_IX, FW_STAT_RX_PORT_65B_127B_IX, FW_STAT_RX_PORT_128B_255B_IX, FW_STAT_RX_PORT_256B_511B_IX, FW_STAT_RX_PORT_512B_1023B_IX, FW_STAT_RX_PORT_1024B_1518B_IX, FW_STAT_RX_PORT_1519B_MAX_IX, FW_STAT_RX_PORT_PAUSE_IX, FW_STAT_RX_PORT_PPP0_IX, FW_STAT_RX_PORT_PPP1_IX, FW_STAT_RX_PORT_PPP2_IX, FW_STAT_RX_PORT_PPP3_IX, FW_STAT_RX_PORT_PPP4_IX, FW_STAT_RX_PORT_PPP5_IX, FW_STAT_RX_PORT_PPP6_IX, FW_STAT_RX_PORT_PPP7_IX, FW_STAT_RX_PORT_LESS_64B_IX }; struct fw_port_stats_cmd { __be32 op_to_portid; __be32 retval_len16; union fw_port_stats { struct fw_port_stats_ctl { __u8 nstats_bg_bm; __u8 tx_ix; __be16 r6; __be32 r7; __be64 stat0; __be64 stat1; __be64 stat2; __be64 stat3; __be64 stat4; __be64 stat5; } ctl; struct fw_port_stats_all { __be64 tx_bytes; __be64 tx_frames; __be64 tx_bcast; __be64 tx_mcast; __be64 tx_ucast; __be64 tx_error; __be64 tx_64b; __be64 tx_65b_127b; __be64 tx_128b_255b; __be64 tx_256b_511b; __be64 tx_512b_1023b; __be64 tx_1024b_1518b; __be64 tx_1519b_max; __be64 tx_drop; __be64 tx_pause; __be64 tx_ppp0; __be64 tx_ppp1; __be64 tx_ppp2; __be64 tx_ppp3; __be64 tx_ppp4; __be64 tx_ppp5; __be64 tx_ppp6; __be64 tx_ppp7; __be64 rx_bytes; __be64 rx_frames; __be64 rx_bcast; __be64 rx_mcast; __be64 rx_ucast; __be64 rx_mtu_error; __be64 rx_mtu_crc_error; __be64 rx_crc_error; __be64 rx_len_error; __be64 rx_sym_error; __be64 rx_64b; __be64 rx_65b_127b; __be64 rx_128b_255b; __be64 rx_256b_511b; __be64 rx_512b_1023b; __be64 rx_1024b_1518b; __be64 rx_1519b_max; __be64 rx_pause; __be64 rx_ppp0; __be64 rx_ppp1; __be64 rx_ppp2; __be64 rx_ppp3; __be64 rx_ppp4; __be64 rx_ppp5; __be64 rx_ppp6; __be64 rx_ppp7; __be64 rx_less_64b; __be64 rx_bg_drop; __be64 rx_bg_trunc; } all; } u; }; #define S_FW_PORT_STATS_CMD_NSTATS 4 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) #define G_FW_PORT_STATS_CMD_NSTATS(x) \ (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) #define S_FW_PORT_STATS_CMD_BG_BM 0 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) #define G_FW_PORT_STATS_CMD_BG_BM(x) \ (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) #define S_FW_PORT_STATS_CMD_TX 7 #define M_FW_PORT_STATS_CMD_TX 0x1 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) #define G_FW_PORT_STATS_CMD_TX(x) \ (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) #define S_FW_PORT_STATS_CMD_IX 0 #define M_FW_PORT_STATS_CMD_IX 0x3f #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) #define G_FW_PORT_STATS_CMD_IX(x) \ (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) /* port loopback stats */ #define FW_NUM_LB_STATS 14 enum fw_port_lb_stats_index { FW_STAT_LB_PORT_BYTES_IX, FW_STAT_LB_PORT_FRAMES_IX, FW_STAT_LB_PORT_BCAST_IX, FW_STAT_LB_PORT_MCAST_IX, FW_STAT_LB_PORT_UCAST_IX, FW_STAT_LB_PORT_ERROR_IX, FW_STAT_LB_PORT_64B_IX, FW_STAT_LB_PORT_65B_127B_IX, FW_STAT_LB_PORT_128B_255B_IX, FW_STAT_LB_PORT_256B_511B_IX, FW_STAT_LB_PORT_512B_1023B_IX, FW_STAT_LB_PORT_1024B_1518B_IX, FW_STAT_LB_PORT_1519B_MAX_IX, FW_STAT_LB_PORT_DROP_FRAMES_IX }; struct fw_port_lb_stats_cmd { __be32 op_to_lbport; __be32 retval_len16; union fw_port_lb_stats { struct fw_port_lb_stats_ctl { __u8 nstats_bg_bm; __u8 ix_pkd; __be16 r6; __be32 r7; __be64 stat0; __be64 stat1; __be64 stat2; __be64 stat3; __be64 stat4; __be64 stat5; } ctl; struct fw_port_lb_stats_all { __be64 tx_bytes; __be64 tx_frames; __be64 tx_bcast; __be64 tx_mcast; __be64 tx_ucast; __be64 tx_error; __be64 tx_64b; __be64 tx_65b_127b; __be64 tx_128b_255b; __be64 tx_256b_511b; __be64 tx_512b_1023b; __be64 tx_1024b_1518b; __be64 tx_1519b_max; __be64 rx_lb_drop; __be64 rx_lb_trunc; } all; } u; }; #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) #define S_FW_PORT_LB_STATS_CMD_IX 0 #define M_FW_PORT_LB_STATS_CMD_IX 0xf #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) #define G_FW_PORT_LB_STATS_CMD_IX(x) \ (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) /* Trace related defines */ #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 struct fw_port_trace_cmd { __be32 op_to_portid; __be32 retval_len16; __be16 traceen_to_pciech; __be16 qnum; __be32 r5; }; #define S_FW_PORT_TRACE_CMD_PORTID 0 #define M_FW_PORT_TRACE_CMD_PORTID 0xf #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) #define G_FW_PORT_TRACE_CMD_PORTID(x) \ (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) #define S_FW_PORT_TRACE_CMD_TRACEEN 15 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) #define S_FW_PORT_TRACE_CMD_FLTMODE 14 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) #define S_FW_PORT_TRACE_CMD_DUPLEN 13 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) #define S_FW_PORT_TRACE_CMD_PCIECH 6 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) struct fw_port_trace_mmap_cmd { __be32 op_to_portid; __be32 retval_len16; __be32 fid_to_skipoffset; __be32 minpktsize_capturemax; __u8 map[224]; }; #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ M_FW_PORT_TRACE_MMAP_CMD_PORTID) #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) struct fw_rss_ind_tbl_cmd { __be32 op_to_viid; __be32 retval_len16; __be16 niqid; __be16 startidx; __be32 r3; __be32 iq0_to_iq2; __be32 iq3_to_iq5; __be32 iq6_to_iq8; __be32 iq9_to_iq11; __be32 iq12_to_iq14; __be32 iq15_to_iq17; __be32 iq18_to_iq20; __be32 iq21_to_iq23; __be32 iq24_to_iq26; __be32 iq27_to_iq29; __be32 iq30_iq31; __be32 r15_lo; }; #define S_FW_RSS_IND_TBL_CMD_VIID 0 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) #define S_FW_RSS_IND_TBL_CMD_IQ0 20 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) #define S_FW_RSS_IND_TBL_CMD_IQ1 10 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) #define S_FW_RSS_IND_TBL_CMD_IQ2 0 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) #define S_FW_RSS_IND_TBL_CMD_IQ3 20 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) #define S_FW_RSS_IND_TBL_CMD_IQ4 10 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) #define S_FW_RSS_IND_TBL_CMD_IQ5 0 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) #define S_FW_RSS_IND_TBL_CMD_IQ6 20 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) #define S_FW_RSS_IND_TBL_CMD_IQ7 10 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) #define S_FW_RSS_IND_TBL_CMD_IQ8 0 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) #define S_FW_RSS_IND_TBL_CMD_IQ9 20 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) #define S_FW_RSS_IND_TBL_CMD_IQ10 10 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) #define S_FW_RSS_IND_TBL_CMD_IQ11 0 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) #define S_FW_RSS_IND_TBL_CMD_IQ12 20 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) #define S_FW_RSS_IND_TBL_CMD_IQ13 10 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) #define S_FW_RSS_IND_TBL_CMD_IQ14 0 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) #define S_FW_RSS_IND_TBL_CMD_IQ15 20 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) #define S_FW_RSS_IND_TBL_CMD_IQ16 10 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) #define S_FW_RSS_IND_TBL_CMD_IQ17 0 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) #define S_FW_RSS_IND_TBL_CMD_IQ18 20 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) #define S_FW_RSS_IND_TBL_CMD_IQ19 10 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) #define S_FW_RSS_IND_TBL_CMD_IQ20 0 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) #define S_FW_RSS_IND_TBL_CMD_IQ21 20 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) #define S_FW_RSS_IND_TBL_CMD_IQ22 10 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) #define S_FW_RSS_IND_TBL_CMD_IQ23 0 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) #define S_FW_RSS_IND_TBL_CMD_IQ24 20 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) #define S_FW_RSS_IND_TBL_CMD_IQ25 10 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) #define S_FW_RSS_IND_TBL_CMD_IQ26 0 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) #define S_FW_RSS_IND_TBL_CMD_IQ27 20 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) #define S_FW_RSS_IND_TBL_CMD_IQ28 10 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) #define S_FW_RSS_IND_TBL_CMD_IQ29 0 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) #define S_FW_RSS_IND_TBL_CMD_IQ30 20 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) #define S_FW_RSS_IND_TBL_CMD_IQ31 10 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) struct fw_rss_glb_config_cmd { __be32 op_to_write; __be32 retval_len16; union fw_rss_glb_config { struct fw_rss_glb_config_manual { __be32 mode_pkd; __be32 r3; __be64 r4; __be64 r5; } manual; struct fw_rss_glb_config_basicvirtual { __be32 mode_pkd; __be32 synmapen_to_hashtoeplitz; __be64 r8; __be64 r9; } basicvirtual; } u; }; #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) struct fw_rss_vi_config_cmd { __be32 op_to_viid; __be32 retval_len16; union fw_rss_vi_config { struct fw_rss_vi_config_manual { __be64 r3; __be64 r4; __be64 r5; } manual; struct fw_rss_vi_config_basicvirtual { __be32 r6; __be32 defaultq_to_udpen; __be64 r9; __be64 r10; } basicvirtual; } u; }; #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & \ M_FW_RSS_VI_CONFIG_CMD_UDPEN) #define F_FW_RSS_VI_CONFIG_CMD_UDPEN \ V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) enum fw_sched_sc { FW_SCHED_SC_CONFIG = 0, FW_SCHED_SC_PARAMS = 1, }; enum fw_sched_type { FW_SCHED_TYPE_PKTSCHED = 0, FW_SCHED_TYPE_STREAMSCHED = 1, }; enum fw_sched_params_level { FW_SCHED_PARAMS_LEVEL_CL_RL = 0, FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, FW_SCHED_PARAMS_LEVEL_CH_RL = 2, FW_SCHED_PARAMS_LEVEL_CH_WRR = 3, }; enum fw_sched_params_mode { FW_SCHED_PARAMS_MODE_CLASS = 0, FW_SCHED_PARAMS_MODE_FLOW = 1, }; enum fw_sched_params_unit { FW_SCHED_PARAMS_UNIT_BITRATE = 0, FW_SCHED_PARAMS_UNIT_PKTRATE = 1, }; enum fw_sched_params_rate { FW_SCHED_PARAMS_RATE_REL = 0, FW_SCHED_PARAMS_RATE_ABS = 1, }; struct fw_sched_cmd { __be32 op_to_write; __be32 retval_len16; union fw_sched { struct fw_sched_config { __u8 sc; __u8 type; __u8 minmaxen; __u8 r3[5]; } config; struct fw_sched_params { __u8 sc; __u8 type; __u8 level; __u8 mode; __u8 unit; __u8 rate; __u8 ch; __u8 cl; __be32 min; __be32 max; __be16 weight; __be16 pktsize; __be32 r4; } params; } u; }; /* * length of the formatting string */ #define FW_DEVLOG_FMT_LEN 192 /* * maximum number of the formatting string parameters */ #define FW_DEVLOG_FMT_PARAMS_NUM 8 /* * priority levels */ enum fw_devlog_level { FW_DEVLOG_LEVEL_EMERG = 0x0, FW_DEVLOG_LEVEL_CRIT = 0x1, FW_DEVLOG_LEVEL_ERR = 0x2, FW_DEVLOG_LEVEL_NOTICE = 0x3, FW_DEVLOG_LEVEL_INFO = 0x4, FW_DEVLOG_LEVEL_DEBUG = 0x5, FW_DEVLOG_LEVEL_MAX = 0x5, }; /* * facilities that may send a log message */ enum fw_devlog_facility { FW_DEVLOG_FACILITY_CORE = 0x00, FW_DEVLOG_FACILITY_SCHED = 0x02, FW_DEVLOG_FACILITY_TIMER = 0x04, FW_DEVLOG_FACILITY_RES = 0x06, FW_DEVLOG_FACILITY_HW = 0x08, FW_DEVLOG_FACILITY_FLR = 0x10, FW_DEVLOG_FACILITY_DMAQ = 0x12, FW_DEVLOG_FACILITY_PHY = 0x14, FW_DEVLOG_FACILITY_MAC = 0x16, FW_DEVLOG_FACILITY_PORT = 0x18, FW_DEVLOG_FACILITY_VI = 0x1A, FW_DEVLOG_FACILITY_FILTER = 0x1C, FW_DEVLOG_FACILITY_ACL = 0x1E, FW_DEVLOG_FACILITY_TM = 0x20, FW_DEVLOG_FACILITY_QFC = 0x22, FW_DEVLOG_FACILITY_DCB = 0x24, FW_DEVLOG_FACILITY_ETH = 0x26, FW_DEVLOG_FACILITY_OFLD = 0x28, FW_DEVLOG_FACILITY_RI = 0x2A, FW_DEVLOG_FACILITY_ISCSI = 0x2C, FW_DEVLOG_FACILITY_FCOE = 0x2E, FW_DEVLOG_FACILITY_FOISCSI = 0x30, FW_DEVLOG_FACILITY_FOFCOE = 0x32, FW_DEVLOG_FACILITY_MAX = 0x32, }; /* * log message format */ struct fw_devlog_e { __be64 timestamp; __be32 seqno; __be16 reserved1; __u8 level; __u8 facility; __u8 fmt[FW_DEVLOG_FMT_LEN]; __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; __be32 reserved3[4]; }; struct fw_devlog_cmd { __be32 op_to_write; __be32 retval_len16; __u8 level; __u8 r2[7]; __be32 memtype_devlog_memaddr16_devlog; __be32 memsize_devlog; __be32 r3[2]; }; #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) + +struct fw_netif_cmd { + __be32 op_portid; + __be32 retval_to_len16; + __be32 add_to_ipv4gw; + __be32 vlanid_mtuval; + __be32 gwaddr; + __be32 addr; + __be32 nmask; + __be32 bcaddr; +}; + +#define S_FW_NETIF_CMD_PORTID 0 +#define M_FW_NETIF_CMD_PORTID 0xf +#define V_FW_NETIF_CMD_PORTID(x) ((x) << S_FW_NETIF_CMD_PORTID) +#define G_FW_NETIF_CMD_PORTID(x) \ + (((x) >> S_FW_NETIF_CMD_PORTID) & M_FW_NETIF_CMD_PORTID) + +#define S_FW_NETIF_CMD_RETVAL 24 +#define M_FW_NETIF_CMD_RETVAL 0xff +#define V_FW_NETIF_CMD_RETVAL(x) ((x) << S_FW_NETIF_CMD_RETVAL) +#define G_FW_NETIF_CMD_RETVAL(x) \ + (((x) >> S_FW_NETIF_CMD_RETVAL) & M_FW_NETIF_CMD_RETVAL) + +#define S_FW_NETIF_CMD_IFIDX 16 +#define M_FW_NETIF_CMD_IFIDX 0xff +#define V_FW_NETIF_CMD_IFIDX(x) ((x) << S_FW_NETIF_CMD_IFIDX) +#define G_FW_NETIF_CMD_IFIDX(x) \ + (((x) >> S_FW_NETIF_CMD_IFIDX) & M_FW_NETIF_CMD_IFIDX) + +#define S_FW_NETIF_CMD_LEN16 0 +#define M_FW_NETIF_CMD_LEN16 0xff +#define V_FW_NETIF_CMD_LEN16(x) ((x) << S_FW_NETIF_CMD_LEN16) +#define G_FW_NETIF_CMD_LEN16(x) \ + (((x) >> S_FW_NETIF_CMD_LEN16) & M_FW_NETIF_CMD_LEN16) + +#define S_FW_NETIF_CMD_ADD 31 +#define M_FW_NETIF_CMD_ADD 0x1 +#define V_FW_NETIF_CMD_ADD(x) ((x) << S_FW_NETIF_CMD_ADD) +#define G_FW_NETIF_CMD_ADD(x) \ + (((x) >> S_FW_NETIF_CMD_ADD) & M_FW_NETIF_CMD_ADD) +#define F_FW_NETIF_CMD_ADD V_FW_NETIF_CMD_ADD(1U) + +#define S_FW_NETIF_CMD_LINK 30 +#define M_FW_NETIF_CMD_LINK 0x1 +#define V_FW_NETIF_CMD_LINK(x) ((x) << S_FW_NETIF_CMD_LINK) +#define G_FW_NETIF_CMD_LINK(x) \ + (((x) >> S_FW_NETIF_CMD_LINK) & M_FW_NETIF_CMD_LINK) +#define F_FW_NETIF_CMD_LINK V_FW_NETIF_CMD_LINK(1U) + +#define S_FW_NETIF_CMD_VLAN 29 +#define M_FW_NETIF_CMD_VLAN 0x1 +#define V_FW_NETIF_CMD_VLAN(x) ((x) << S_FW_NETIF_CMD_VLAN) +#define G_FW_NETIF_CMD_VLAN(x) \ + (((x) >> S_FW_NETIF_CMD_VLAN) & M_FW_NETIF_CMD_VLAN) +#define F_FW_NETIF_CMD_VLAN V_FW_NETIF_CMD_VLAN(1U) + +#define S_FW_NETIF_CMD_MTU 28 +#define M_FW_NETIF_CMD_MTU 0x1 +#define V_FW_NETIF_CMD_MTU(x) ((x) << S_FW_NETIF_CMD_MTU) +#define G_FW_NETIF_CMD_MTU(x) \ + (((x) >> S_FW_NETIF_CMD_MTU) & M_FW_NETIF_CMD_MTU) +#define F_FW_NETIF_CMD_MTU V_FW_NETIF_CMD_MTU(1U) + +#define S_FW_NETIF_CMD_DHCP 27 +#define M_FW_NETIF_CMD_DHCP 0x1 +#define V_FW_NETIF_CMD_DHCP(x) ((x) << S_FW_NETIF_CMD_DHCP) +#define G_FW_NETIF_CMD_DHCP(x) \ + (((x) >> S_FW_NETIF_CMD_DHCP) & M_FW_NETIF_CMD_DHCP) +#define F_FW_NETIF_CMD_DHCP V_FW_NETIF_CMD_DHCP(1U) + +#define S_FW_NETIF_CMD_IPV4BCADDR 3 +#define M_FW_NETIF_CMD_IPV4BCADDR 0x1 +#define V_FW_NETIF_CMD_IPV4BCADDR(x) ((x) << S_FW_NETIF_CMD_IPV4BCADDR) +#define G_FW_NETIF_CMD_IPV4BCADDR(x) \ + (((x) >> S_FW_NETIF_CMD_IPV4BCADDR) & M_FW_NETIF_CMD_IPV4BCADDR) +#define F_FW_NETIF_CMD_IPV4BCADDR V_FW_NETIF_CMD_IPV4BCADDR(1U) + +#define S_FW_NETIF_CMD_IPV4NMASK 2 +#define M_FW_NETIF_CMD_IPV4NMASK 0x1 +#define V_FW_NETIF_CMD_IPV4NMASK(x) ((x) << S_FW_NETIF_CMD_IPV4NMASK) +#define G_FW_NETIF_CMD_IPV4NMASK(x) \ + (((x) >> S_FW_NETIF_CMD_IPV4NMASK) & M_FW_NETIF_CMD_IPV4NMASK) +#define F_FW_NETIF_CMD_IPV4NMASK V_FW_NETIF_CMD_IPV4NMASK(1U) + +#define S_FW_NETIF_CMD_IPV4ADDR 1 +#define M_FW_NETIF_CMD_IPV4ADDR 0x1 +#define V_FW_NETIF_CMD_IPV4ADDR(x) ((x) << S_FW_NETIF_CMD_IPV4ADDR) +#define G_FW_NETIF_CMD_IPV4ADDR(x) \ + (((x) >> S_FW_NETIF_CMD_IPV4ADDR) & M_FW_NETIF_CMD_IPV4ADDR) +#define F_FW_NETIF_CMD_IPV4ADDR V_FW_NETIF_CMD_IPV4ADDR(1U) + +#define S_FW_NETIF_CMD_IPV4GW 0 +#define M_FW_NETIF_CMD_IPV4GW 0x1 +#define V_FW_NETIF_CMD_IPV4GW(x) ((x) << S_FW_NETIF_CMD_IPV4GW) +#define G_FW_NETIF_CMD_IPV4GW(x) \ + (((x) >> S_FW_NETIF_CMD_IPV4GW) & M_FW_NETIF_CMD_IPV4GW) +#define F_FW_NETIF_CMD_IPV4GW V_FW_NETIF_CMD_IPV4GW(1U) + +#define S_FW_NETIF_CMD_VLANID 16 +#define M_FW_NETIF_CMD_VLANID 0xfff +#define V_FW_NETIF_CMD_VLANID(x) ((x) << S_FW_NETIF_CMD_VLANID) +#define G_FW_NETIF_CMD_VLANID(x) \ + (((x) >> S_FW_NETIF_CMD_VLANID) & M_FW_NETIF_CMD_VLANID) + +#define S_FW_NETIF_CMD_MTUVAL 0 +#define M_FW_NETIF_CMD_MTUVAL 0xffff +#define V_FW_NETIF_CMD_MTUVAL(x) ((x) << S_FW_NETIF_CMD_MTUVAL) +#define G_FW_NETIF_CMD_MTUVAL(x) \ + (((x) >> S_FW_NETIF_CMD_MTUVAL) & M_FW_NETIF_CMD_MTUVAL) enum fw_error_type { FW_ERROR_TYPE_EXCEPTION = 0x0, FW_ERROR_TYPE_HWMODULE = 0x1, FW_ERROR_TYPE_WR = 0x2, FW_ERROR_TYPE_ACL = 0x3, }; struct fw_error_cmd { __be32 op_to_type; __be32 len16_pkd; union fw_error { struct fw_error_exception { __be32 info[6]; } exception; struct fw_error_hwmodule { __be32 regaddr; __be32 regval; } hwmodule; struct fw_error_wr { __be16 cidx; __be16 pfn_vfn; __be32 eqid; __u8 wrhdr[16]; } wr; struct fw_error_acl { __be16 cidx; __be16 pfn_vfn; __be32 eqid; __be16 mv_pkd; __u8 val[6]; __be64 r4; } acl; } u; }; #define S_FW_ERROR_CMD_FATAL 4 #define M_FW_ERROR_CMD_FATAL 0x1 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) #define G_FW_ERROR_CMD_FATAL(x) \ (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) #define S_FW_ERROR_CMD_TYPE 0 #define M_FW_ERROR_CMD_TYPE 0xf #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) #define G_FW_ERROR_CMD_TYPE(x) \ (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) #define S_FW_ERROR_CMD_PFN 8 #define M_FW_ERROR_CMD_PFN 0x7 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) #define G_FW_ERROR_CMD_PFN(x) \ (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) #define S_FW_ERROR_CMD_VFN 0 #define M_FW_ERROR_CMD_VFN 0xff #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) #define G_FW_ERROR_CMD_VFN(x) \ (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) #define S_FW_ERROR_CMD_PFN 8 #define M_FW_ERROR_CMD_PFN 0x7 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) #define G_FW_ERROR_CMD_PFN(x) \ (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) #define S_FW_ERROR_CMD_VFN 0 #define M_FW_ERROR_CMD_VFN 0xff #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) #define G_FW_ERROR_CMD_VFN(x) \ (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) #define S_FW_ERROR_CMD_MV 15 #define M_FW_ERROR_CMD_MV 0x1 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) #define G_FW_ERROR_CMD_MV(x) \ (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) struct fw_debug_cmd { __be32 op_type; __be32 len16_pkd; union fw_debug { struct fw_debug_assert { __be32 fcid; __be32 line; __be32 x; __be32 y; __u8 filename_0_7[8]; __u8 filename_8_15[8]; __be64 r3; } assert; struct fw_debug_prt { __be16 dprtstridx; __be16 r3[3]; __be32 dprtstrparam0; __be32 dprtstrparam1; __be32 dprtstrparam2; __be32 dprtstrparam3; } prt; } u; }; #define S_FW_DEBUG_CMD_TYPE 0 #define M_FW_DEBUG_CMD_TYPE 0xff #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) #define G_FW_DEBUG_CMD_TYPE(x) \ (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) /****************************************************************************** * B I N A R Y H E A D E R F O R M A T **********************************************/ /* * firmware binary header format */ struct fw_hdr { __u8 ver; __u8 reserved1; __be16 len512; /* bin length in units of 512-bytes */ __be32 fw_ver; /* firmware version */ __be32 tp_microcode_ver; /* tcp processor microcode version */ __u8 intfver_nic; __u8 intfver_vnic; __u8 intfver_ofld; __u8 intfver_ri; __u8 intfver_iscsipdu; __u8 intfver_iscsi; __u8 intfver_fcoe; __u8 reserved2; __be32 reserved3[27]; }; #define S_FW_HDR_FW_VER_MAJOR 24 #define M_FW_HDR_FW_VER_MAJOR 0xff #define V_FW_HDR_FW_VER_MAJOR(x) \ ((x) << S_FW_HDR_FW_VER_MAJOR) #define G_FW_HDR_FW_VER_MAJOR(x) \ (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) #define S_FW_HDR_FW_VER_MINOR 16 #define M_FW_HDR_FW_VER_MINOR 0xff #define V_FW_HDR_FW_VER_MINOR(x) \ ((x) << S_FW_HDR_FW_VER_MINOR) #define G_FW_HDR_FW_VER_MINOR(x) \ (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) #define S_FW_HDR_FW_VER_MICRO 8 #define M_FW_HDR_FW_VER_MICRO 0xff #define V_FW_HDR_FW_VER_MICRO(x) \ ((x) << S_FW_HDR_FW_VER_MICRO) #define G_FW_HDR_FW_VER_MICRO(x) \ (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) #define S_FW_HDR_FW_VER_BUILD 0 #define M_FW_HDR_FW_VER_BUILD 0xff #define V_FW_HDR_FW_VER_BUILD(x) \ ((x) << S_FW_HDR_FW_VER_BUILD) #define G_FW_HDR_FW_VER_BUILD(x) \ (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) #endif /* _T4FW_INTERFACE_H_ */ Index: stable/8/sys/dev/cxgbe/offload.h =================================================================== --- stable/8/sys/dev/cxgbe/offload.h (revision 222793) +++ stable/8/sys/dev/cxgbe/offload.h (revision 222794) @@ -1,88 +1,106 @@ /*- * Copyright (c) 2010 Chelsio Communications, Inc. * All rights reserved. * Written by: Navdeep Parhar * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __T4_OFFLOAD_H__ #define __T4_OFFLOAD_H__ +/* CPL message priority levels */ +enum { + CPL_PRIORITY_DATA = 0, /* data messages */ + CPL_PRIORITY_SETUP = 1, /* connection setup messages */ + CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */ + CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */ + CPL_PRIORITY_ACK = 1, /* RX ACK messages */ + CPL_PRIORITY_CONTROL = 1 /* control messages */ +}; + +#define INIT_TP_WR(w, tid) do { \ + (w)->wr.wr_hi = htonl(V_FW_WR_OP(FW_TP_WR) | \ + V_FW_WR_IMMDLEN(sizeof(*w) - sizeof(w->wr))); \ + (w)->wr.wr_mid = htonl(V_FW_WR_LEN16(DIV_ROUND_UP(sizeof(*w), 16)) | \ + V_FW_WR_FLOWID(tid)); \ + (w)->wr.wr_lo = cpu_to_be64(0); \ +} while (0) + /* * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. */ #define MAX_ATIDS 8192U struct serv_entry { void *data; }; union aopen_entry { void *data; union aopen_entry *next; }; /* * Holds the size, base address, free list start, etc of the TID, server TID, * and active-open TID tables. The tables themselves are allocated dynamically. */ struct tid_info { void **tid_tab; unsigned int ntids; struct serv_entry *stid_tab; unsigned long *stid_bmap; unsigned int nstids; unsigned int stid_base; union aopen_entry *atid_tab; unsigned int natids; struct filter_entry *ftid_tab; unsigned int nftids; unsigned int ftid_base; unsigned int ftids_in_use; union aopen_entry *afree; unsigned int atids_in_use; unsigned int stids_in_use; }; struct t4_range { unsigned int start; unsigned int size; }; struct t4_virt_res { /* virtualized HW resources */ struct t4_range ddp; struct t4_range iscsi; struct t4_range stag; struct t4_range rq; struct t4_range pbl; }; #endif Index: stable/8/sys/dev/cxgbe/osdep.h =================================================================== --- stable/8/sys/dev/cxgbe/osdep.h (revision 222793) +++ stable/8/sys/dev/cxgbe/osdep.h (revision 222794) @@ -1,151 +1,152 @@ /*- * Copyright (c) 2010 Chelsio Communications, Inc. * All rights reserved. * Written by: Navdeep Parhar * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __CXGBE_OSDEP_H_ #define __CXGBE_OSDEP_H_ #include #include #include #include #include #include #include #include #define CH_ERR(adap, fmt, ...) log(LOG_ERR, fmt, ##__VA_ARGS__) #define CH_WARN(adap, fmt, ...) log(LOG_WARNING, fmt, ##__VA_ARGS__) #define CH_ALERT(adap, fmt, ...) log(LOG_ALERT, fmt, ##__VA_ARGS__) #define CH_WARN_RATELIMIT(adap, fmt, ...) log(LOG_WARNING, fmt, ##__VA_ARGS__) typedef int8_t s8; typedef int16_t s16; typedef int32_t s32; typedef int64_t s64; typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; typedef uint8_t __u8; typedef uint16_t __u16; typedef uint32_t __u32; typedef uint64_t __u64; typedef uint8_t __be8; typedef uint16_t __be16; typedef uint32_t __be32; typedef uint64_t __be64; #if BYTE_ORDER == BIG_ENDIAN #define __BIG_ENDIAN_BITFIELD #elif BYTE_ORDER == LITTLE_ENDIAN #define __LITTLE_ENDIAN_BITFIELD #else #error "Must set BYTE_ORDER" #endif typedef boolean_t bool; #define false FALSE #define true TRUE #define mdelay(x) DELAY((x) * 1000) #define udelay(x) DELAY(x) #define __devinit #define simple_strtoul strtoul #define DIV_ROUND_UP(x, y) howmany(x, y) #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define container_of(p, s, f) ((s *)(((uint8_t *)(p)) - offsetof(s, f))) #define swab16(x) bswap16(x) #define swab32(x) bswap32(x) #define swab64(x) bswap64(x) #define le16_to_cpu(x) le16toh(x) #define le32_to_cpu(x) le32toh(x) #define le64_to_cpu(x) le64toh(x) #define cpu_to_le16(x) htole16(x) #define cpu_to_le32(x) htole32(x) #define cpu_to_le64(x) htole64(x) #define be16_to_cpu(x) be16toh(x) #define be32_to_cpu(x) be32toh(x) #define be64_to_cpu(x) be64toh(x) #define cpu_to_be16(x) htobe16(x) #define cpu_to_be32(x) htobe32(x) #define cpu_to_be64(x) htobe64(x) #define SPEED_10 10 #define SPEED_100 100 #define SPEED_1000 1000 #define SPEED_10000 10000 #define DUPLEX_HALF 0 #define DUPLEX_FULL 1 #define AUTONEG_DISABLE 0 #define AUTONEG_ENABLE 1 #define PCI_CAP_ID_VPD PCIY_VPD #define PCI_VPD_ADDR PCIR_VPD_ADDR #define PCI_VPD_ADDR_F 0x8000 #define PCI_VPD_DATA PCIR_VPD_DATA #define PCI_CAP_ID_EXP PCIY_EXPRESS #define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL #define PCI_EXP_DEVCTL_PAYLOAD PCIM_EXP_CTL_MAX_PAYLOAD #define PCI_EXP_DEVCTL_READRQ PCIM_EXP_CTL_MAX_READ_REQUEST #define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL #define PCI_EXP_LNKSTA PCIR_EXPRESS_LINK_STA #define PCI_EXP_LNKSTA_CLS PCIM_LINK_STA_SPEED #define PCI_EXP_LNKSTA_NLW PCIM_LINK_STA_WIDTH static inline int ilog2(long x) { KASSERT(x > 0 && powerof2(x), ("%s: invalid arg %ld", __func__, x)); return (flsl(x) - 1); } static inline char * strstrip(char *s) { char c, *r, *trim_at; while (isspace(*s)) s++; r = trim_at = s; while ((c = *s++) != 0) { if (!isspace(c)) trim_at = s; } *trim_at = 0; return (r); } #endif Index: stable/8/sys/dev/cxgbe/t4_ioctl.h =================================================================== --- stable/8/sys/dev/cxgbe/t4_ioctl.h (revision 222793) +++ stable/8/sys/dev/cxgbe/t4_ioctl.h (revision 222794) @@ -1,193 +1,195 @@ /*- * Copyright (c) 2011 Chelsio Communications, Inc. * All rights reserved. * Written by: Navdeep Parhar * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #ifndef __T4_IOCTL_H__ #define __T4_IOCTL_H__ #include #include /* * Ioctl commands specific to this driver. */ enum { T4_GETREG = 0x40, /* read register */ T4_SETREG, /* write register */ T4_REGDUMP, /* dump of all registers */ T4_GET_FILTER_MODE, /* get global filter mode */ T4_SET_FILTER_MODE, /* set global filter mode */ T4_GET_FILTER, /* get information about a filter */ T4_SET_FILTER, /* program a filter */ T4_DEL_FILTER, /* delete a filter */ }; struct t4_reg { uint32_t addr; uint32_t size; uint64_t val; }; #define T4_REGDUMP_SIZE (160 * 1024) struct t4_regdump { uint32_t version; uint32_t len; /* bytes */ uint32_t *data; }; /* * A hardware filter is some valid combination of these. */ #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ #define T4_FILTER_PORT 0x80 /* Physical ingress port */ #define T4_FILTER_OVLAN 0x100 /* Outer VLAN ID */ #define T4_FILTER_IVLAN 0x200 /* Inner VLAN ID */ #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ /* Filter action */ enum { FILTER_PASS = 0, /* default */ FILTER_DROP, FILTER_SWITCH }; /* 802.1q manipulation on FILTER_SWITCH */ enum { VLAN_NOCHANGE = 0, /* default */ VLAN_REMOVE, VLAN_INSERT, VLAN_REWRITE }; /* MPS match type */ enum { UCAST_EXACT = 0, /* exact unicast match */ UCAST_HASH = 1, /* inexact (hashed) unicast match */ MCAST_EXACT = 2, /* exact multicast match */ MCAST_HASH = 3, /* inexact (hashed) multicast match */ PROMISC = 4, /* no match but port is promiscuous */ HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ BCAST = 6, /* broadcast packet */ }; /* Rx steering */ enum { DST_MODE_QUEUE, /* queue is directly specified by filter */ DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ DST_MODE_RSS, /* queue selected by default RSS hash lookup */ DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified RSS subtable */ }; struct t4_filter_tuple { /* * These are always available. */ uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ uint16_t sport; /* source port */ uint16_t dport; /* destination port */ /* * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP * is used to select the global mode and all filters are limited to the * set of fields allowed by the global mode. */ uint16_t ovlan; /* outer VLAN */ uint16_t ivlan; /* inner VLAN */ uint16_t ethtype; /* Ethernet type */ uint8_t tos; /* TOS/Traffic Type */ uint8_t proto; /* protocol type */ uint32_t fcoe:1; /* FCoE packet */ uint32_t iport:3; /* ingress port */ uint32_t matchtype:3; /* MPS match type */ uint32_t frag:1; /* fragmentation extension header */ uint32_t macidx:9; /* exact match MAC index */ uint32_t ivlan_vld:1; /* inner VLAN valid */ uint32_t ovlan_vld:1; /* outer VLAN valid */ }; struct t4_filter_specification { uint32_t hitcnts:1; /* count filter hits in TCB */ uint32_t prio:1; /* filter has priority over active/server */ uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ uint32_t action:2; /* drop, pass, switch */ uint32_t rpttid:1; /* report TID in RSS hash field */ uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ uint32_t iq:10; /* ingress queue */ uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ /* 1 => TCB contains IQ ID */ /* * Switch proxy/rewrite fields. An ingress packet which matches a * filter with "switch" set will be looped back out as an egress * packet -- potentially with some Ethernet header rewriting. */ uint32_t eport:2; /* egress port to switch packet out */ uint32_t newdmac:1; /* rewrite destination MAC address */ uint32_t newsmac:1; /* rewrite source MAC address */ uint32_t newvlan:2; /* rewrite VLAN Tag */ uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ uint16_t vlan; /* VLAN Tag to insert */ /* * Filter rule value/mask pairs. */ struct t4_filter_tuple val; struct t4_filter_tuple mask; }; struct t4_filter { uint32_t idx; + uint16_t l2tidx; + uint16_t smtidx; uint64_t hits; struct t4_filter_specification fs; }; #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) #endif Index: stable/8/sys/dev/cxgbe/t4_l2t.c =================================================================== --- stable/8/sys/dev/cxgbe/t4_l2t.c (nonexistent) +++ stable/8/sys/dev/cxgbe/t4_l2t.c (revision 222794) @@ -0,0 +1,361 @@ +/*- + * Copyright (c) 2011 Chelsio Communications, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include +__FBSDID("$FreeBSD$"); + +#include "opt_inet.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common/common.h" +#include "common/jhash.h" +#include "common/t4_msg.h" +#include "offload.h" +#include "t4_l2t.h" + +/* identifies sync vs async L2T_WRITE_REQs */ +#define S_SYNC_WR 12 +#define V_SYNC_WR(x) ((x) << S_SYNC_WR) +#define F_SYNC_WR V_SYNC_WR(1) + +enum { + L2T_STATE_VALID, /* entry is up to date */ + L2T_STATE_STALE, /* entry may be used but needs revalidation */ + L2T_STATE_RESOLVING, /* entry needs address resolution */ + L2T_STATE_SYNC_WRITE, /* synchronous write of entry underway */ + + /* when state is one of the below the entry is not hashed */ + L2T_STATE_SWITCHING, /* entry is being used by a switching filter */ + L2T_STATE_UNUSED /* entry not in use */ +}; + +struct l2t_data { + struct rwlock lock; + volatile int nfree; /* number of free entries */ + struct l2t_entry *rover;/* starting point for next allocation */ + struct l2t_entry l2tab[L2T_SIZE]; +}; + +/* + * Module locking notes: There is a RW lock protecting the L2 table as a + * whole plus a spinlock per L2T entry. Entry lookups and allocations happen + * under the protection of the table lock, individual entry changes happen + * while holding that entry's spinlock. The table lock nests outside the + * entry locks. Allocations of new entries take the table lock as writers so + * no other lookups can happen while allocating new entries. Entry updates + * take the table lock as readers so multiple entries can be updated in + * parallel. An L2T entry can be dropped by decrementing its reference count + * and therefore can happen in parallel with entry allocation but no entry + * can change state or increment its ref count during allocation as both of + * these perform lookups. + * + * Note: We do not take refereces to ifnets in this module because both + * the TOE and the sockets already hold references to the interfaces and the + * lifetime of an L2T entry is fully contained in the lifetime of the TOE. + */ +static inline unsigned int +vlan_prio(const struct l2t_entry *e) +{ + return e->vlan >> 13; +} + +static inline void +l2t_hold(struct l2t_data *d, struct l2t_entry *e) +{ + if (atomic_fetchadd_int(&e->refcnt, 1) == 0) /* 0 -> 1 transition */ + atomic_add_int(&d->nfree, -1); +} + +/* + * To avoid having to check address families we do not allow v4 and v6 + * neighbors to be on the same hash chain. We keep v4 entries in the first + * half of available hash buckets and v6 in the second. + */ +enum { + L2T_SZ_HALF = L2T_SIZE / 2, + L2T_HASH_MASK = L2T_SZ_HALF - 1 +}; + +static inline unsigned int +arp_hash(const uint32_t *key, int ifindex) +{ + return jhash_2words(*key, ifindex, 0) & L2T_HASH_MASK; +} + +static inline unsigned int +ipv6_hash(const uint32_t *key, int ifindex) +{ + uint32_t xor = key[0] ^ key[1] ^ key[2] ^ key[3]; + + return L2T_SZ_HALF + (jhash_2words(xor, ifindex, 0) & L2T_HASH_MASK); +} + +static inline unsigned int +addr_hash(const uint32_t *addr, int addr_len, int ifindex) +{ + return addr_len == 4 ? arp_hash(addr, ifindex) : + ipv6_hash(addr, ifindex); +} + +/* + * Checks if an L2T entry is for the given IP/IPv6 address. It does not check + * whether the L2T entry and the address are of the same address family. + * Callers ensure an address is only checked against L2T entries of the same + * family, something made trivial by the separation of IP and IPv6 hash chains + * mentioned above. Returns 0 if there's a match, + */ +static inline int +addreq(const struct l2t_entry *e, const uint32_t *addr) +{ + if (e->v6) + return (e->addr[0] ^ addr[0]) | (e->addr[1] ^ addr[1]) | + (e->addr[2] ^ addr[2]) | (e->addr[3] ^ addr[3]); + return e->addr[0] ^ addr[0]; +} + +/* + * Write an L2T entry. Must be called with the entry locked (XXX: really?). + * The write may be synchronous or asynchronous. + */ +static int +write_l2e(struct adapter *sc, struct l2t_entry *e, int sync) +{ + struct mbuf *m; + struct cpl_l2t_write_req *req; + + if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) + return (ENOMEM); + + req = mtod(m, struct cpl_l2t_write_req *); + m->m_pkthdr.len = m->m_len = sizeof(*req); + + INIT_TP_WR(req, 0); + OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, e->idx | + V_SYNC_WR(sync) | V_TID_QID(sc->sge.fwq.abs_id))); + req->params = htons(V_L2T_W_PORT(e->lport) | V_L2T_W_NOREPLY(!sync)); + req->l2t_idx = htons(e->idx); + req->vlan = htons(e->vlan); + memcpy(req->dst_mac, e->dmac, sizeof(req->dst_mac)); + + t4_mgmt_tx(sc, m); + + if (sync && e->state != L2T_STATE_SWITCHING) + e->state = L2T_STATE_SYNC_WRITE; + + return (0); +} + +/* + * Add a packet to an L2T entry's queue of packets awaiting resolution. + * Must be called with the entry's lock held. + */ +static inline void +arpq_enqueue(struct l2t_entry *e, struct mbuf *m) +{ + mtx_assert(&e->lock, MA_OWNED); + + m->m_next = NULL; + if (e->arpq_head) + e->arpq_tail->m_next = m; + else + e->arpq_head = m; + e->arpq_tail = m; +} + +/* + * Allocate a free L2T entry. Must be called with l2t_data.lock held. + */ +static struct l2t_entry * +alloc_l2e(struct l2t_data *d) +{ + struct l2t_entry *end, *e, **p; + + rw_assert(&d->lock, RA_WLOCKED); + + if (!atomic_load_acq_int(&d->nfree)) + return (NULL); + + /* there's definitely a free entry */ + for (e = d->rover, end = &d->l2tab[L2T_SIZE]; e != end; ++e) + if (atomic_load_acq_int(&e->refcnt) == 0) + goto found; + + for (e = d->l2tab; atomic_load_acq_int(&e->refcnt); ++e) ; +found: + d->rover = e + 1; + atomic_add_int(&d->nfree, -1); + + /* + * The entry we found may be an inactive entry that is + * presently in the hash table. We need to remove it. + */ + if (e->state < L2T_STATE_SWITCHING) { + for (p = &d->l2tab[e->hash].first; *p; p = &(*p)->next) { + if (*p == e) { + *p = e->next; + e->next = NULL; + break; + } + } + } + + e->state = L2T_STATE_UNUSED; + return e; +} + +/* + * Called when an L2T entry has no more users. The entry is left in the hash + * table since it is likely to be reused but we also bump nfree to indicate + * that the entry can be reallocated for a different neighbor. We also drop + * the existing neighbor reference in case the neighbor is going away and is + * waiting on our reference. + * + * Because entries can be reallocated to other neighbors once their ref count + * drops to 0 we need to take the entry's lock to avoid races with a new + * incarnation. + */ +static void +t4_l2e_free(struct l2t_entry *e) +{ + struct llentry *lle = NULL; + struct l2t_data *d; + + mtx_lock(&e->lock); + if (atomic_load_acq_int(&e->refcnt) == 0) { /* hasn't been recycled */ + lle = e->lle; + e->lle = NULL; + /* + * Don't need to worry about the arpq, an L2T entry can't be + * released if any packets are waiting for resolution as we + * need to be able to communicate with the device to close a + * connection. + */ + } + mtx_unlock(&e->lock); + + d = container_of(e, struct l2t_data, l2tab[e->idx]); + atomic_add_int(&d->nfree, 1); + + if (lle) + LLE_FREE(lle); +} + +void +t4_l2t_release(struct l2t_entry *e) +{ + if (atomic_fetchadd_int(&e->refcnt, -1) == 1) + t4_l2e_free(e); +} + +/* + * Allocate an L2T entry for use by a switching rule. Such need to be + * explicitly freed and while busy they are not on any hash chain, so normal + * address resolution updates do not see them. + */ +struct l2t_entry * +t4_l2t_alloc_switching(struct l2t_data *d) +{ + struct l2t_entry *e; + + rw_rlock(&d->lock); + e = alloc_l2e(d); + if (e) { + mtx_lock(&e->lock); /* avoid race with t4_l2t_free */ + e->state = L2T_STATE_SWITCHING; + atomic_store_rel_int(&e->refcnt, 1); + mtx_unlock(&e->lock); + } + rw_runlock(&d->lock); + return e; +} + +/* + * Sets/updates the contents of a switching L2T entry that has been allocated + * with an earlier call to @t4_l2t_alloc_switching. + */ +int +t4_l2t_set_switching(struct adapter *sc, struct l2t_entry *e, uint16_t vlan, + uint8_t port, uint8_t *eth_addr) +{ + e->vlan = vlan; + e->lport = port; + memcpy(e->dmac, eth_addr, ETHER_ADDR_LEN); + return write_l2e(sc, e, 0); +} + +struct l2t_data * +t4_init_l2t(int flags) +{ + int i; + struct l2t_data *d; + + d = malloc(sizeof(*d), M_CXGBE, M_ZERO | flags); + if (!d) + return (NULL); + + d->rover = d->l2tab; + atomic_store_rel_int(&d->nfree, L2T_SIZE); + rw_init(&d->lock, "L2T"); + + for (i = 0; i < L2T_SIZE; i++) { + d->l2tab[i].idx = i; + d->l2tab[i].state = L2T_STATE_UNUSED; + mtx_init(&d->l2tab[i].lock, "L2T_E", NULL, MTX_DEF); + atomic_store_rel_int(&d->l2tab[i].refcnt, 0); + } + + return (d); +} + +int +t4_free_l2t(struct l2t_data *d) +{ + int i; + + for (i = 0; i < L2T_SIZE; i++) + mtx_destroy(&d->l2tab[i].lock); + rw_destroy(&d->lock); + free(d, M_CXGBE); + + return (0); +} Property changes on: stable/8/sys/dev/cxgbe/t4_l2t.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/8/sys/dev/cxgbe/t4_l2t.h =================================================================== --- stable/8/sys/dev/cxgbe/t4_l2t.h (nonexistent) +++ stable/8/sys/dev/cxgbe/t4_l2t.h (revision 222794) @@ -0,0 +1,71 @@ +/*- + * Copyright (c) 2011 Chelsio Communications, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + * + */ + +#ifndef __T4_L2T_H +#define __T4_L2T_H + +enum { L2T_SIZE = 4096 }; /* # of L2T entries */ + +/* + * Each L2T entry plays multiple roles. First of all, it keeps state for the + * corresponding entry of the HW L2 table and maintains a queue of offload + * packets awaiting address resolution. Second, it is a node of a hash table + * chain, where the nodes of the chain are linked together through their next + * pointer. Finally, each node is a bucket of a hash table, pointing to the + * first element in its chain through its first pointer. + */ +struct l2t_entry { + uint16_t state; /* entry state */ + uint16_t idx; /* entry index */ + uint32_t addr[4]; /* next hop IP or IPv6 address */ + struct ifnet *ifp; /* outgoing interface */ + uint16_t smt_idx; /* SMT index */ + uint16_t vlan; /* VLAN TCI (id: 0-11, prio: 13-15) */ + int ifindex; /* interface index */ + struct llentry *lle; /* llentry for next hop */ + struct l2t_entry *first; /* start of hash chain */ + struct l2t_entry *next; /* next l2t_entry on chain */ + struct mbuf *arpq_head; /* list of mbufs awaiting resolution */ + struct mbuf *arpq_tail; + struct mtx lock; + volatile uint32_t refcnt; /* entry reference count */ + uint16_t hash; /* hash bucket the entry is on */ + uint8_t v6; /* whether entry is for IPv6 */ + uint8_t lport; /* associated offload logical port */ + uint8_t dmac[ETHER_ADDR_LEN]; /* next hop's MAC address */ +}; + +struct l2t_data *t4_init_l2t(int); +int t4_free_l2t(struct l2t_data *); +struct l2t_entry *t4_l2t_alloc_switching(struct l2t_data *); +int t4_l2t_set_switching(struct adapter *, struct l2t_entry *, uint16_t, + uint8_t, uint8_t *); +void t4_l2t_release(struct l2t_entry *); + +#endif /* __T4_L2T_H */ Property changes on: stable/8/sys/dev/cxgbe/t4_l2t.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/8/sys/dev/cxgbe/t4_main.c =================================================================== --- stable/8/sys/dev/cxgbe/t4_main.c (revision 222793) +++ stable/8/sys/dev/cxgbe/t4_main.c (revision 222794) @@ -1,3402 +1,3613 @@ /*- * Copyright (c) 2011 Chelsio Communications, Inc. * All rights reserved. * Written by: Navdeep Parhar * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_inet.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "common/t4_hw.h" #include "common/common.h" #include "common/t4_msg.h" #include "common/t4_regs.h" #include "common/t4_regs_values.h" #include "common/t4fw_interface.h" #include "t4_ioctl.h" +#include "t4_l2t.h" /* T4 bus driver interface */ static int t4_probe(device_t); static int t4_attach(device_t); static int t4_detach(device_t); static device_method_t t4_methods[] = { DEVMETHOD(device_probe, t4_probe), DEVMETHOD(device_attach, t4_attach), DEVMETHOD(device_detach, t4_detach), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), { 0, 0 } }; static driver_t t4_driver = { "t4nex", t4_methods, sizeof(struct adapter) }; /* T4 port (cxgbe) interface */ static int cxgbe_probe(device_t); static int cxgbe_attach(device_t); static int cxgbe_detach(device_t); static device_method_t cxgbe_methods[] = { DEVMETHOD(device_probe, cxgbe_probe), DEVMETHOD(device_attach, cxgbe_attach), DEVMETHOD(device_detach, cxgbe_detach), { 0, 0 } }; static driver_t cxgbe_driver = { "cxgbe", cxgbe_methods, sizeof(struct port_info) }; static d_ioctl_t t4_ioctl; static d_open_t t4_open; static d_close_t t4_close; static struct cdevsw t4_cdevsw = { .d_version = D_VERSION, .d_flags = 0, .d_open = t4_open, .d_close = t4_close, .d_ioctl = t4_ioctl, .d_name = "t4nex", }; /* ifnet + media interface */ static void cxgbe_init(void *); static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); static void cxgbe_start(struct ifnet *); static int cxgbe_transmit(struct ifnet *, struct mbuf *); static void cxgbe_qflush(struct ifnet *); static int cxgbe_media_change(struct ifnet *); static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4 Ethernet driver and services"); /* * Tunables. */ SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe driver parameters"); static int force_firmware_install = 0; TUNABLE_INT("hw.cxgbe.force_firmware_install", &force_firmware_install); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, force_firmware_install, CTLFLAG_RDTUN, &force_firmware_install, 0, "install firmware on every attach."); /* * Holdoff timer and packet counter values. */ static unsigned int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200}; static unsigned int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */ /* * Max # of tx and rx queues to use for each 10G and 1G port. */ static unsigned int max_ntxq_10g = 8; TUNABLE_INT("hw.cxgbe.max_ntxq_10G_port", &max_ntxq_10g); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_ntxq_10G_port, CTLFLAG_RDTUN, &max_ntxq_10g, 0, "maximum number of tx queues per 10G port."); static unsigned int max_nrxq_10g = 8; TUNABLE_INT("hw.cxgbe.max_nrxq_10G_port", &max_nrxq_10g); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_nrxq_10G_port, CTLFLAG_RDTUN, &max_nrxq_10g, 0, "maximum number of rxq's (per 10G port)."); static unsigned int max_ntxq_1g = 2; TUNABLE_INT("hw.cxgbe.max_ntxq_1G_port", &max_ntxq_1g); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_ntxq_1G_port, CTLFLAG_RDTUN, &max_ntxq_1g, 0, "maximum number of tx queues per 1G port."); static unsigned int max_nrxq_1g = 2; TUNABLE_INT("hw.cxgbe.max_nrxq_1G_port", &max_nrxq_1g); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, max_nrxq_1G_port, CTLFLAG_RDTUN, &max_nrxq_1g, 0, "maximum number of rxq's (per 1G port)."); /* * Holdoff parameters for 10G and 1G ports. */ static unsigned int tmr_idx_10g = 1; TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &tmr_idx_10g); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_10G, CTLFLAG_RDTUN, &tmr_idx_10g, 0, "default timer index for interrupt holdoff (10G ports)."); static int pktc_idx_10g = 2; TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &pktc_idx_10g); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_10G, CTLFLAG_RDTUN, &pktc_idx_10g, 0, "default pkt counter index for interrupt holdoff (10G ports)."); static unsigned int tmr_idx_1g = 1; TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &tmr_idx_1g); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_1G, CTLFLAG_RDTUN, &tmr_idx_1g, 0, "default timer index for interrupt holdoff (1G ports)."); static int pktc_idx_1g = 2; TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &pktc_idx_1g); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_1G, CTLFLAG_RDTUN, &pktc_idx_1g, 0, "default pkt counter index for interrupt holdoff (1G ports)."); /* * Size (# of entries) of each tx and rx queue. */ static unsigned int qsize_txq = TX_EQ_QSIZE; TUNABLE_INT("hw.cxgbe.qsize_txq", &qsize_txq); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &qsize_txq, 0, "default queue size of NIC tx queues."); static unsigned int qsize_rxq = RX_IQ_QSIZE; TUNABLE_INT("hw.cxgbe.qsize_rxq", &qsize_rxq); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &qsize_rxq, 0, "default queue size of NIC rx queues."); /* * Interrupt types allowed. */ static int intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; TUNABLE_INT("hw.cxgbe.interrupt_types", &intr_types); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &intr_types, 0, "interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively)"); /* - * Force the driver to use interrupt forwarding. + * Force the driver to use the same set of interrupts for all ports. */ -static int intr_fwd = 0; -TUNABLE_INT("hw.cxgbe.interrupt_forwarding", &intr_fwd); -SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupt_forwarding, CTLFLAG_RDTUN, - &intr_fwd, 0, "always use forwarded interrupts"); +static int intr_shared = 0; +TUNABLE_INT("hw.cxgbe.interrupts_shared", &intr_shared); +SYSCTL_UINT(_hw_cxgbe, OID_AUTO, interrupts_shared, CTLFLAG_RDTUN, + &intr_shared, 0, "interrupts shared between all ports"); static unsigned int filter_mode = HW_TPL_FR_MT_PR_IV_P_FC; TUNABLE_INT("hw.cxgbe.filter_mode", &filter_mode); SYSCTL_UINT(_hw_cxgbe, OID_AUTO, filter_mode, CTLFLAG_RDTUN, &filter_mode, 0, "default global filter mode."); struct intrs_and_queues { int intr_type; /* INTx, MSI, or MSI-X */ int nirq; /* Number of vectors */ - int intr_fwd; /* Interrupts forwarded */ + int intr_shared; /* Interrupts shared between all ports */ int ntxq10g; /* # of NIC txq's for each 10G port */ int nrxq10g; /* # of NIC rxq's for each 10G port */ int ntxq1g; /* # of NIC txq's for each 1G port */ int nrxq1g; /* # of NIC rxq's for each 1G port */ }; struct filter_entry { uint32_t valid:1; /* filter allocated and valid */ uint32_t locked:1; /* filter is administratively locked */ uint32_t pending:1; /* filter action is pending firmware reply */ uint32_t smtidx:8; /* Source MAC Table index for smac */ + struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ struct t4_filter_specification fs; }; enum { MEMWIN0_APERTURE = 2048, MEMWIN0_BASE = 0x1b800, MEMWIN1_APERTURE = 32768, MEMWIN1_BASE = 0x28000, MEMWIN2_APERTURE = 65536, MEMWIN2_BASE = 0x30000, }; enum { XGMAC_MTU = (1 << 0), XGMAC_PROMISC = (1 << 1), XGMAC_ALLMULTI = (1 << 2), XGMAC_VLANEX = (1 << 3), XGMAC_UCADDR = (1 << 4), XGMAC_MCADDRS = (1 << 5), XGMAC_ALL = 0xffff }; static int map_bars(struct adapter *); static void setup_memwin(struct adapter *); static int cfg_itype_and_nqueues(struct adapter *, int, int, struct intrs_and_queues *); static int prep_firmware(struct adapter *); +static int get_devlog_params(struct adapter *, struct devlog_params *); static int get_capabilities(struct adapter *, struct fw_caps_config_cmd *); static int get_params(struct adapter *, struct fw_caps_config_cmd *); static void t4_set_desc(struct adapter *); static void build_medialist(struct port_info *); static int update_mac_settings(struct port_info *, int); static int cxgbe_init_locked(struct port_info *); static int cxgbe_init_synchronized(struct port_info *); static int cxgbe_uninit_locked(struct port_info *); static int cxgbe_uninit_synchronized(struct port_info *); static int first_port_up(struct adapter *); static int last_port_down(struct adapter *); static int t4_alloc_irq(struct adapter *, struct irq *, int rid, iq_intr_handler_t *, void *, char *); static int t4_free_irq(struct adapter *, struct irq *); static void reg_block_dump(struct adapter *, uint8_t *, unsigned int, unsigned int); static void t4_get_regs(struct adapter *, struct t4_regdump *, uint8_t *); static void cxgbe_tick(void *); static int t4_sysctls(struct adapter *); static int cxgbe_sysctls(struct port_info *); static int sysctl_int_array(SYSCTL_HANDLER_ARGS); static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); +#ifdef T4_DEVLOG +static int sysctl_devlog(SYSCTL_HANDLER_ARGS); +#endif static inline void txq_start(struct ifnet *, struct sge_txq *); static uint32_t fconf_to_mode(uint32_t); static uint32_t mode_to_fconf(uint32_t); static uint32_t fspec_to_fconf(struct t4_filter_specification *); static int get_filter_mode(struct adapter *, uint32_t *); static int set_filter_mode(struct adapter *, uint32_t); +static inline uint64_t get_filter_hits(struct adapter *, uint32_t); static int get_filter(struct adapter *, struct t4_filter *); static int set_filter(struct adapter *, struct t4_filter *); static int del_filter(struct adapter *, struct t4_filter *); -static void clear_filter(struct adapter *, struct filter_entry *); +static void clear_filter(struct filter_entry *); static int set_filter_wr(struct adapter *, int); static int del_filter_wr(struct adapter *, int); void filter_rpl(struct adapter *, const struct cpl_set_tcb_rpl *); static int t4_mod_event(module_t, int, void *); struct t4_pciids { uint16_t device; uint8_t mpf; char *desc; } t4_pciids[] = { {0xa000, 0, "Chelsio Terminator 4 FPGA"}, {0x4400, 4, "Chelsio T440-dbg"}, {0x4401, 4, "Chelsio T420-CR"}, {0x4402, 4, "Chelsio T422-CR"}, {0x4403, 4, "Chelsio T440-CR"}, {0x4404, 4, "Chelsio T420-BCH"}, {0x4405, 4, "Chelsio T440-BCH"}, {0x4406, 4, "Chelsio T440-CH"}, {0x4407, 4, "Chelsio T420-SO"}, {0x4408, 4, "Chelsio T420-CX"}, {0x4409, 4, "Chelsio T420-BT"}, {0x440a, 4, "Chelsio T404-BT"}, }; static int t4_probe(device_t dev) { int i; uint16_t v = pci_get_vendor(dev); uint16_t d = pci_get_device(dev); if (v != PCI_VENDOR_ID_CHELSIO) return (ENXIO); for (i = 0; i < ARRAY_SIZE(t4_pciids); i++) { if (d == t4_pciids[i].device && pci_get_function(dev) == t4_pciids[i].mpf) { device_set_desc(dev, t4_pciids[i].desc); return (BUS_PROBE_DEFAULT); } } return (ENXIO); } static int t4_attach(device_t dev) { struct adapter *sc; int rc = 0, i, n10g, n1g, rqidx, tqidx; struct fw_caps_config_cmd caps; uint32_t p, v; struct intrs_and_queues iaq; struct sge *s; sc = device_get_softc(dev); sc->dev = dev; sc->pf = pci_get_function(dev); sc->mbox = sc->pf; pci_enable_busmaster(dev); if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { pci_set_max_read_req(dev, 4096); v = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2); v |= PCIM_EXP_CTL_RELAXED_ORD_ENABLE; pci_write_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, v, 2); } snprintf(sc->lockname, sizeof(sc->lockname), "%s", device_get_nameunit(dev)); mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); rc = map_bars(sc); if (rc != 0) goto done; /* error message displayed already */ memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); /* Prepare the adapter for operation */ rc = -t4_prep_adapter(sc); if (rc != 0) { device_printf(dev, "failed to prepare adapter: %d.\n", rc); goto done; } /* Do this really early */ sc->cdev = make_dev(&t4_cdevsw, device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); sc->cdev->si_drv1 = sc; /* Prepare the firmware for operation */ rc = prep_firmware(sc); if (rc != 0) goto done; /* error message displayed already */ + /* Read firmware devlog parameters */ + (void) get_devlog_params(sc, &sc->params.devlog); + /* Get device capabilities and select which ones we'll use */ rc = get_capabilities(sc, &caps); if (rc != 0) { device_printf(dev, "failed to initialize adapter capabilities: %d.\n", rc); goto done; } /* Choose the global RSS mode. */ rc = -t4_config_glbl_rss(sc, sc->mbox, FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN | F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ | F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP); if (rc != 0) { device_printf(dev, "failed to select global RSS mode: %d.\n", rc); goto done; } /* These are total (sum of all ports) limits for a bus driver */ rc = -t4_cfg_pfvf(sc, sc->mbox, sc->pf, 0, 128, /* max # of egress queues */ 64, /* max # of egress Ethernet or control queues */ 64, /* max # of ingress queues with fl/interrupt */ 0, /* max # of ingress queues without interrupt */ 0, /* PCIe traffic class */ 4, /* max # of virtual interfaces */ M_FW_PFVF_CMD_CMASK, M_FW_PFVF_CMD_PMASK, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF); if (rc != 0) { device_printf(dev, "failed to configure pf/vf resources: %d.\n", rc); goto done; } /* Need this before sge_init */ for (i = 0; i < SGE_NTIMERS; i++) sc->sge.timer_val[i] = min(intr_timer[i], 200U); for (i = 0; i < SGE_NCOUNTERS; i++) sc->sge.counter_val[i] = min(intr_pktcount[i], M_THRESHOLD_0); /* Also need the cooked value of cclk before sge_init */ p = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK)); rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &p, &v); if (rc != 0) { device_printf(sc->dev, "failed to obtain core clock value: %d.\n", rc); goto done; } sc->params.vpd.cclk = v; t4_sge_init(sc); t4_set_filter_mode(sc, filter_mode); t4_set_reg_field(sc, A_TP_GLOBAL_CONFIG, V_FIVETUPLELOOKUP(M_FIVETUPLELOOKUP), V_FIVETUPLELOOKUP(M_FIVETUPLELOOKUP)); t4_tp_wr_bits_indirect(sc, A_TP_INGRESS_CONFIG, F_CSUM_HAS_PSEUDO_HDR, F_LOOKUPEVERYPKT); /* get basic stuff going */ rc = -t4_early_init(sc, sc->mbox); if (rc != 0) { device_printf(dev, "early init failed: %d.\n", rc); goto done; } rc = get_params(sc, &caps); if (rc != 0) goto done; /* error message displayed already */ /* These are finalized by FW initialization, load their values now */ v = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); sc->params.tp.tre = G_TIMERRESOLUTION(v); sc->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v); t4_read_mtu_tbl(sc, sc->params.mtus, NULL); /* tweak some settings */ t4_write_reg(sc, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) | V_RXTSHIFTMAXR2(15) | V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) | V_KEEPALIVEMAXR1(4) | V_KEEPALIVEMAXR2(9)); t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); + t4_set_reg_field(sc, A_TP_PARA_REG3, F_TUNNELCNGDROP0 | + F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 | F_TUNNELCNGDROP3, 0); setup_memwin(sc); rc = t4_create_dma_tag(sc); if (rc != 0) goto done; /* error message displayed already */ /* * First pass over all the ports - allocate VIs and initialize some * basic parameters like mac address, port type, etc. We also figure * out whether a port is 10G or 1G and use that information when * calculating how many interrupts to attempt to allocate. */ n10g = n1g = 0; for_each_port(sc, i) { struct port_info *pi; pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); sc->port[i] = pi; /* These must be set before t4_port_init */ pi->adapter = sc; pi->port_id = i; /* Allocate the vi and initialize parameters like mac addr */ rc = -t4_port_init(pi, sc->mbox, sc->pf, 0); if (rc != 0) { device_printf(dev, "unable to initialize port %d: %d\n", i, rc); free(pi, M_CXGBE); - sc->port[i] = NULL; /* indicates init failed */ - continue; + sc->port[i] = NULL; + goto done; } snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", device_get_nameunit(dev), i); mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); if (is_10G_port(pi)) { n10g++; pi->tmr_idx = tmr_idx_10g; pi->pktc_idx = pktc_idx_10g; } else { n1g++; pi->tmr_idx = tmr_idx_1g; pi->pktc_idx = pktc_idx_1g; } pi->xact_addr_filt = -1; pi->qsize_rxq = max(qsize_rxq, 128); while (pi->qsize_rxq & 7) pi->qsize_rxq++; pi->qsize_txq = max(qsize_txq, 128); if (pi->qsize_rxq != qsize_rxq) { device_printf(dev, "using %d instead of %d as the rx queue size.\n", pi->qsize_rxq, qsize_rxq); } if (pi->qsize_txq != qsize_txq) { device_printf(dev, "using %d instead of %d as the tx queue size.\n", pi->qsize_txq, qsize_txq); } pi->dev = device_add_child(dev, "cxgbe", -1); if (pi->dev == NULL) { device_printf(dev, "failed to add device for port %d.\n", i); rc = ENXIO; goto done; } device_set_softc(pi->dev, pi); setbit(&sc->registered_device_map, i); } if (sc->registered_device_map == 0) { device_printf(dev, "no usable ports\n"); rc = ENXIO; goto done; } /* * Interrupt type, # of interrupts, # of rx/tx queues, etc. */ rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq); if (rc != 0) goto done; /* error message displayed already */ sc->intr_type = iaq.intr_type; sc->intr_count = iaq.nirq; s = &sc->sge; s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ - s->neq += NCHAN; /* control queues, 1 per hw channel */ + s->neq += sc->params.nports; /* control queues, 1 per port */ s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ - if (iaq.intr_fwd) { - sc->flags |= INTR_FWD; - s->niq += NFIQ(sc); /* forwarded interrupt queues */ - s->fiq = malloc(NFIQ(sc) * sizeof(struct sge_iq), M_CXGBE, - M_ZERO | M_WAITOK); - } - s->ctrlq = malloc(NCHAN * sizeof(struct sge_ctrlq), M_CXGBE, + if (iaq.intr_shared) + sc->flags |= INTR_SHARED; + s->niq += NINTRQ(sc); /* interrupt queues */ + + s->intrq = malloc(NINTRQ(sc) * sizeof(struct sge_iq), M_CXGBE, M_ZERO | M_WAITOK); + s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_ctrlq), M_CXGBE, + M_ZERO | M_WAITOK); s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, M_ZERO | M_WAITOK); s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, M_ZERO | M_WAITOK); s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, M_ZERO | M_WAITOK); s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, M_ZERO | M_WAITOK); sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, M_ZERO | M_WAITOK); + sc->l2t = t4_init_l2t(M_WAITOK); + t4_sysctls(sc); /* * Second pass over the ports. This time we know the number of rx and * tx queues that each port should get. */ rqidx = tqidx = 0; for_each_port(sc, i) { struct port_info *pi = sc->port[i]; if (pi == NULL) continue; pi->first_rxq = rqidx; pi->nrxq = is_10G_port(pi) ? iaq.nrxq10g : iaq.nrxq1g; pi->first_txq = tqidx; pi->ntxq = is_10G_port(pi) ? iaq.ntxq10g : iaq.ntxq1g; rqidx += pi->nrxq; tqidx += pi->ntxq; } rc = bus_generic_attach(dev); if (rc != 0) { device_printf(dev, "failed to attach all child ports: %d\n", rc); goto done; } #ifdef INVARIANTS device_printf(dev, "%p, %d ports (0x%x), %d intr_type, %d intr_count\n", sc, sc->params.nports, sc->params.portvec, sc->intr_type, sc->intr_count); #endif t4_set_desc(sc); done: if (rc != 0) t4_detach(dev); return (rc); } /* * Idempotent */ static int t4_detach(device_t dev) { struct adapter *sc; struct port_info *pi; int i; sc = device_get_softc(dev); if (sc->cdev) destroy_dev(sc->cdev); bus_generic_detach(dev); for (i = 0; i < MAX_NPORTS; i++) { pi = sc->port[i]; if (pi) { t4_free_vi(pi->adapter, sc->mbox, sc->pf, 0, pi->viid); if (pi->dev) device_delete_child(dev, pi->dev); mtx_destroy(&pi->pi_lock); free(pi, M_CXGBE); } } if (sc->flags & FW_OK) t4_fw_bye(sc, sc->mbox); if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) pci_release_msi(dev); if (sc->regs_res) bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, sc->regs_res); if (sc->msix_res) bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, sc->msix_res); + if (sc->l2t) + t4_free_l2t(sc->l2t); + free(sc->irq, M_CXGBE); free(sc->sge.rxq, M_CXGBE); free(sc->sge.txq, M_CXGBE); free(sc->sge.ctrlq, M_CXGBE); - free(sc->sge.fiq, M_CXGBE); + free(sc->sge.intrq, M_CXGBE); free(sc->sge.iqmap, M_CXGBE); free(sc->sge.eqmap, M_CXGBE); free(sc->tids.ftid_tab, M_CXGBE); t4_destroy_dma_tag(sc); mtx_destroy(&sc->sc_lock); bzero(sc, sizeof(*sc)); return (0); } static int cxgbe_probe(device_t dev) { char buf[128]; struct port_info *pi = device_get_softc(dev); snprintf(buf, sizeof(buf), "Port %d", pi->port_id); device_set_desc_copy(dev, buf); return (BUS_PROBE_DEFAULT); } #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ IFCAP_VLAN_HWTSO) #define T4_CAP_ENABLE (T4_CAP & ~IFCAP_TSO6) static int cxgbe_attach(device_t dev) { struct port_info *pi = device_get_softc(dev); struct ifnet *ifp; /* Allocate an ifnet and set it up */ ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "Cannot allocate ifnet\n"); return (ENOMEM); } pi->ifp = ifp; ifp->if_softc = pi; callout_init(&pi->tick, CALLOUT_MPSAFE); pi->tq = taskqueue_create("cxgbe_taskq", M_NOWAIT, taskqueue_thread_enqueue, &pi->tq); if (pi->tq == NULL) { device_printf(dev, "failed to allocate port task queue\n"); if_free(pi->ifp); return (ENOMEM); } taskqueue_start_threads(&pi->tq, 1, PI_NET, "%s taskq", device_get_nameunit(dev)); if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_init = cxgbe_init; ifp->if_ioctl = cxgbe_ioctl; ifp->if_start = cxgbe_start; ifp->if_transmit = cxgbe_transmit; ifp->if_qflush = cxgbe_qflush; ifp->if_snd.ifq_drv_maxlen = 1024; IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); IFQ_SET_READY(&ifp->if_snd); ifp->if_capabilities = T4_CAP; ifp->if_capenable = T4_CAP_ENABLE; ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO; /* Initialize ifmedia for this port */ ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, cxgbe_media_status); build_medialist(pi); ether_ifattach(ifp, pi->hw_addr); #ifdef INVARIANTS device_printf(dev, "%p, %d txq, %d rxq\n", pi, pi->ntxq, pi->nrxq); #endif cxgbe_sysctls(pi); return (0); } static int cxgbe_detach(device_t dev) { struct port_info *pi = device_get_softc(dev); struct adapter *sc = pi->adapter; int rc; /* Tell if_ioctl and if_init that the port is going away */ ADAPTER_LOCK(sc); SET_DOOMED(pi); wakeup(&sc->flags); while (IS_BUSY(sc)) mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); SET_BUSY(sc); ADAPTER_UNLOCK(sc); rc = cxgbe_uninit_synchronized(pi); if (rc != 0) device_printf(dev, "port uninit failed: %d.\n", rc); taskqueue_free(pi->tq); ifmedia_removeall(&pi->media); ether_ifdetach(pi->ifp); if_free(pi->ifp); ADAPTER_LOCK(sc); CLR_BUSY(sc); wakeup_one(&sc->flags); ADAPTER_UNLOCK(sc); return (0); } static void cxgbe_init(void *arg) { struct port_info *pi = arg; struct adapter *sc = pi->adapter; ADAPTER_LOCK(sc); cxgbe_init_locked(pi); /* releases adapter lock */ ADAPTER_LOCK_ASSERT_NOTOWNED(sc); } static int cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) { int rc = 0, mtu, flags; struct port_info *pi = ifp->if_softc; struct adapter *sc = pi->adapter; struct ifreq *ifr = (struct ifreq *)data; uint32_t mask; switch (cmd) { case SIOCSIFMTU: ADAPTER_LOCK(sc); rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (rc) { fail: ADAPTER_UNLOCK(sc); return (rc); } mtu = ifr->ifr_mtu; if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) { rc = EINVAL; } else { ifp->if_mtu = mtu; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { t4_update_fl_bufsize(ifp); PORT_LOCK(pi); rc = update_mac_settings(pi, XGMAC_MTU); PORT_UNLOCK(pi); } } ADAPTER_UNLOCK(sc); break; case SIOCSIFFLAGS: ADAPTER_LOCK(sc); if (IS_DOOMED(pi)) { rc = ENXIO; goto fail; } if (ifp->if_flags & IFF_UP) { if (ifp->if_drv_flags & IFF_DRV_RUNNING) { flags = pi->if_flags; if ((ifp->if_flags ^ flags) & (IFF_PROMISC | IFF_ALLMULTI)) { if (IS_BUSY(sc)) { rc = EBUSY; goto fail; } PORT_LOCK(pi); rc = update_mac_settings(pi, XGMAC_PROMISC | XGMAC_ALLMULTI); PORT_UNLOCK(pi); } ADAPTER_UNLOCK(sc); } else rc = cxgbe_init_locked(pi); pi->if_flags = ifp->if_flags; } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) rc = cxgbe_uninit_locked(pi); else ADAPTER_UNLOCK(sc); ADAPTER_LOCK_ASSERT_NOTOWNED(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: /* these two can be called with a mutex held :-( */ ADAPTER_LOCK(sc); rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (rc) goto fail; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { PORT_LOCK(pi); rc = update_mac_settings(pi, XGMAC_MCADDRS); PORT_UNLOCK(pi); } ADAPTER_UNLOCK(sc); break; case SIOCSIFCAP: ADAPTER_LOCK(sc); rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (rc) goto fail; mask = ifr->ifr_reqcap ^ ifp->if_capenable; if (mask & IFCAP_TXCSUM) { ifp->if_capenable ^= IFCAP_TXCSUM; ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); if (IFCAP_TSO & ifp->if_capenable && !(IFCAP_TXCSUM & ifp->if_capenable)) { ifp->if_capenable &= ~IFCAP_TSO; ifp->if_hwassist &= ~CSUM_TSO; if_printf(ifp, "tso disabled due to -txcsum.\n"); } } if (mask & IFCAP_RXCSUM) ifp->if_capenable ^= IFCAP_RXCSUM; if (mask & IFCAP_TSO4) { ifp->if_capenable ^= IFCAP_TSO4; if (IFCAP_TSO & ifp->if_capenable) { if (IFCAP_TXCSUM & ifp->if_capenable) ifp->if_hwassist |= CSUM_TSO; else { ifp->if_capenable &= ~IFCAP_TSO; ifp->if_hwassist &= ~CSUM_TSO; if_printf(ifp, "enable txcsum first.\n"); rc = EAGAIN; } } else ifp->if_hwassist &= ~CSUM_TSO; } if (mask & IFCAP_LRO) { #ifdef INET int i; struct sge_rxq *rxq; ifp->if_capenable ^= IFCAP_LRO; for_each_rxq(pi, i, rxq) { if (ifp->if_capenable & IFCAP_LRO) rxq->flags |= RXQ_LRO_ENABLED; else rxq->flags &= ~RXQ_LRO_ENABLED; } #endif } #ifndef TCP_OFFLOAD_DISABLE if (mask & IFCAP_TOE4) { rc = EOPNOTSUPP; } #endif if (mask & IFCAP_VLAN_HWTAGGING) { ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { PORT_LOCK(pi); rc = update_mac_settings(pi, XGMAC_VLANEX); PORT_UNLOCK(pi); } } if (mask & IFCAP_VLAN_MTU) { ifp->if_capenable ^= IFCAP_VLAN_MTU; /* Need to find out how to disable auto-mtu-inflation */ } if (mask & IFCAP_VLAN_HWTSO) ifp->if_capenable ^= IFCAP_VLAN_HWTSO; if (mask & IFCAP_VLAN_HWCSUM) ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; #ifdef VLAN_CAPABILITIES VLAN_CAPABILITIES(ifp); #endif ADAPTER_UNLOCK(sc); break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: ifmedia_ioctl(ifp, ifr, &pi->media, cmd); break; default: rc = ether_ioctl(ifp, cmd, data); } return (rc); } static void cxgbe_start(struct ifnet *ifp) { struct port_info *pi = ifp->if_softc; struct sge_txq *txq; int i; for_each_txq(pi, i, txq) { if (TXQ_TRYLOCK(txq)) { txq_start(ifp, txq); TXQ_UNLOCK(txq); } } } static int cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) { struct port_info *pi = ifp->if_softc; struct adapter *sc = pi->adapter; struct sge_txq *txq = &sc->sge.txq[pi->first_txq]; struct buf_ring *br; int rc; M_ASSERTPKTHDR(m); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { m_freem(m); return (0); } if (m->m_flags & M_FLOWID) txq += (m->m_pkthdr.flowid % pi->ntxq); br = txq->br; if (TXQ_TRYLOCK(txq) == 0) { /* * XXX: make sure that this packet really is sent out. There is * a small race where t4_eth_tx may stop draining the drbr and * goes away, just before we enqueued this mbuf. */ return (drbr_enqueue(ifp, br, m)); } /* * txq->m is the mbuf that is held up due to a temporary shortage of * resources and it should be put on the wire first. Then what's in * drbr and finally the mbuf that was just passed in to us. * * Return code should indicate the fate of the mbuf that was passed in * this time. */ TXQ_LOCK_ASSERT_OWNED(txq); if (drbr_needs_enqueue(ifp, br) || txq->m) { /* Queued for transmission. */ rc = drbr_enqueue(ifp, br, m); m = txq->m ? txq->m : drbr_dequeue(ifp, br); (void) t4_eth_tx(ifp, txq, m); TXQ_UNLOCK(txq); return (rc); } /* Direct transmission. */ rc = t4_eth_tx(ifp, txq, m); if (rc != 0 && txq->m) rc = 0; /* held, will be transmitted soon (hopefully) */ TXQ_UNLOCK(txq); return (rc); } static void cxgbe_qflush(struct ifnet *ifp) { struct port_info *pi = ifp->if_softc; struct sge_txq *txq; int i; struct mbuf *m; /* queues do not exist if !IFF_DRV_RUNNING. */ if (ifp->if_drv_flags & IFF_DRV_RUNNING) { for_each_txq(pi, i, txq) { TXQ_LOCK(txq); m_freem(txq->m); while ((m = buf_ring_dequeue_sc(txq->br)) != NULL) m_freem(m); TXQ_UNLOCK(txq); } } if_qflush(ifp); } static int cxgbe_media_change(struct ifnet *ifp) { struct port_info *pi = ifp->if_softc; device_printf(pi->dev, "%s unimplemented.\n", __func__); return (EOPNOTSUPP); } static void cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct port_info *pi = ifp->if_softc; struct ifmedia_entry *cur = pi->media.ifm_cur; int speed = pi->link_cfg.speed; int data = (pi->port_type << 8) | pi->mod_type; if (cur->ifm_data != data) { build_medialist(pi); cur = pi->media.ifm_cur; } ifmr->ifm_status = IFM_AVALID; if (!pi->link_cfg.link_ok) return; ifmr->ifm_status |= IFM_ACTIVE; /* active and current will differ iff current media is autoselect. */ if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) return; ifmr->ifm_active = IFM_ETHER | IFM_FDX; if (speed == SPEED_10000) ifmr->ifm_active |= IFM_10G_T; else if (speed == SPEED_1000) ifmr->ifm_active |= IFM_1000_T; else if (speed == SPEED_100) ifmr->ifm_active |= IFM_100_TX; else if (speed == SPEED_10) ifmr->ifm_active |= IFM_10_T; else KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, speed)); } void t4_fatal_err(struct adapter *sc) { t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); t4_intr_disable(sc); log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", device_get_nameunit(sc->dev)); } static int map_bars(struct adapter *sc) { sc->regs_rid = PCIR_BAR(0); sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &sc->regs_rid, RF_ACTIVE); if (sc->regs_res == NULL) { device_printf(sc->dev, "cannot map registers.\n"); return (ENXIO); } sc->bt = rman_get_bustag(sc->regs_res); sc->bh = rman_get_bushandle(sc->regs_res); sc->mmio_len = rman_get_size(sc->regs_res); sc->msix_rid = PCIR_BAR(4); sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &sc->msix_rid, RF_ACTIVE); if (sc->msix_res == NULL) { device_printf(sc->dev, "cannot map MSI-X BAR.\n"); return (ENXIO); } return (0); } static void setup_memwin(struct adapter *sc) { u_long bar0; bar0 = rman_get_start(sc->regs_res); t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), (bar0 + MEMWIN0_BASE) | V_BIR(0) | V_WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), (bar0 + MEMWIN1_BASE) | V_BIR(0) | V_WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), (bar0 + MEMWIN2_BASE) | V_BIR(0) | V_WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); } static int cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, struct intrs_and_queues *iaq) { int rc, itype, navail, nc, nrxq10g, nrxq1g; bzero(iaq, sizeof(*iaq)); nc = mp_ncpus; /* our snapshot of the number of CPUs */ for (itype = INTR_MSIX; itype; itype >>= 1) { if ((itype & intr_types) == 0) continue; /* not allowed */ if (itype == INTR_MSIX) navail = pci_msix_count(sc->dev); else if (itype == INTR_MSI) navail = pci_msi_count(sc->dev); else navail = 1; if (navail == 0) continue; iaq->intr_type = itype; iaq->ntxq10g = min(nc, max_ntxq_10g); iaq->ntxq1g = min(nc, max_ntxq_1g); nrxq10g = min(nc, max_nrxq_10g); nrxq1g = min(nc, max_nrxq_1g); - /* Extra 2 is for a) error interrupt b) firmware event */ - iaq->nirq = n10g * nrxq10g + n1g * nrxq1g + 2; - if (iaq->nirq <= navail && intr_fwd == 0) { + iaq->nirq = n10g * nrxq10g + n1g * nrxq1g + T4_EXTRA_INTR; + if (iaq->nirq <= navail && intr_shared == 0) { if (itype == INTR_MSI && !powerof2(iaq->nirq)) - goto fwd; + goto share; /* One for err, one for fwq, and one for each rxq */ - iaq->intr_fwd = 0; + iaq->intr_shared = 0; iaq->nrxq10g = nrxq10g; iaq->nrxq1g = nrxq1g; } else { -fwd: - iaq->intr_fwd = 1; +share: + iaq->intr_shared = 1; - if (navail > nc) { + if (navail >= nc + T4_EXTRA_INTR) { if (itype == INTR_MSIX) - navail = nc + 1; + navail = nc + T4_EXTRA_INTR; /* navail is and must remain a pow2 for MSI */ if (itype == INTR_MSI) { KASSERT(powerof2(navail), ("%d not power of 2", navail)); - while (navail / 2 > nc) + while (navail / 2 >= nc + T4_EXTRA_INTR) navail /= 2; } } iaq->nirq = navail; /* total # of interrupts */ /* * If we have multiple vectors available reserve one * exclusively for errors. The rest will be shared by * the fwq and data. */ if (navail > 1) navail--; iaq->nrxq10g = min(nrxq10g, navail); iaq->nrxq1g = min(nrxq1g, navail); } navail = iaq->nirq; rc = 0; if (itype == INTR_MSIX) rc = pci_alloc_msix(sc->dev, &navail); else if (itype == INTR_MSI) rc = pci_alloc_msi(sc->dev, &navail); if (rc == 0) { if (navail == iaq->nirq) return (0); /* * Didn't get the number requested. Use whatever number * the kernel is willing to allocate (it's in navail). */ pci_release_msi(sc->dev); - goto fwd; + goto share; } device_printf(sc->dev, "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", itype, rc, iaq->nirq, navail); } device_printf(sc->dev, "failed to find a usable interrupt type. " "allowed=%d, msi-x=%d, msi=%d, intx=1", intr_types, pci_msix_count(sc->dev), pci_msi_count(sc->dev)); return (ENXIO); } /* * Install a compatible firmware (if required), establish contact with it, * become the master, and reset the device. */ static int prep_firmware(struct adapter *sc) { const struct firmware *fw; int rc; enum dev_state state; /* Check firmware version and install a different one if necessary */ rc = t4_check_fw_version(sc); if (rc != 0 || force_firmware_install) { uint32_t v = 0; fw = firmware_get(T4_FWNAME); if (fw != NULL) { const struct fw_hdr *hdr = (const void *)fw->data; v = ntohl(hdr->fw_ver); /* * The firmware module will not be used if it isn't the * same major version as what the driver was compiled * with. This check trumps force_firmware_install. */ if (G_FW_HDR_FW_VER_MAJOR(v) != FW_VERSION_MAJOR) { device_printf(sc->dev, "Found firmware image but version %d " "can not be used with this driver (%d)\n", G_FW_HDR_FW_VER_MAJOR(v), FW_VERSION_MAJOR); firmware_put(fw, FIRMWARE_UNLOAD); fw = NULL; } } if (fw == NULL && (rc < 0 || force_firmware_install)) { device_printf(sc->dev, "No usable firmware. " "card has %d.%d.%d, driver compiled with %d.%d.%d, " "force_firmware_install%s set", G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO, force_firmware_install ? "" : " not"); return (EAGAIN); } /* * Always upgrade, even for minor/micro/build mismatches. * Downgrade only for a major version mismatch or if * force_firmware_install was specified. */ if (fw != NULL && (rc < 0 || force_firmware_install || v > sc->params.fw_vers)) { device_printf(sc->dev, "installing firmware %d.%d.%d.%d on card.\n", G_FW_HDR_FW_VER_MAJOR(v), G_FW_HDR_FW_VER_MINOR(v), G_FW_HDR_FW_VER_MICRO(v), G_FW_HDR_FW_VER_BUILD(v)); rc = -t4_load_fw(sc, fw->data, fw->datasize); if (rc != 0) { device_printf(sc->dev, "failed to install firmware: %d\n", rc); firmware_put(fw, FIRMWARE_UNLOAD); return (rc); } else { /* refresh */ (void) t4_check_fw_version(sc); } } if (fw != NULL) firmware_put(fw, FIRMWARE_UNLOAD); } /* Contact firmware, request master */ rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MUST, &state); if (rc < 0) { rc = -rc; device_printf(sc->dev, "failed to connect to the firmware: %d.\n", rc); return (rc); } /* Reset device */ rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); if (rc != 0) { device_printf(sc->dev, "firmware reset failed: %d.\n", rc); if (rc != ETIMEDOUT && rc != EIO) t4_fw_bye(sc, sc->mbox); return (rc); } snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); sc->flags |= FW_OK; return (0); } static int +get_devlog_params(struct adapter *sc, struct devlog_params *dlog) +{ + struct fw_devlog_cmd devlog_cmd; + uint32_t meminfo; + int rc; + + bzero(&devlog_cmd, sizeof(devlog_cmd)); + devlog_cmd.op_to_write = htobe32(V_FW_CMD_OP(FW_DEVLOG_CMD) | + F_FW_CMD_REQUEST | F_FW_CMD_READ); + devlog_cmd.retval_len16 = htobe32(FW_LEN16(devlog_cmd)); + rc = -t4_wr_mbox(sc, sc->mbox, &devlog_cmd, sizeof(devlog_cmd), + &devlog_cmd); + if (rc != 0) { + device_printf(sc->dev, + "failed to get devlog parameters: %d.\n", rc); + bzero(dlog, sizeof (*dlog)); + return (rc); + } + + meminfo = be32toh(devlog_cmd.memtype_devlog_memaddr16_devlog); + dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(meminfo); + dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(meminfo) << 4; + dlog->size = be32toh(devlog_cmd.memsize_devlog); + + return (0); +} + +static int get_capabilities(struct adapter *sc, struct fw_caps_config_cmd *caps) { int rc; bzero(caps, sizeof(*caps)); caps->op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | F_FW_CMD_REQUEST | F_FW_CMD_READ); caps->retval_len16 = htobe32(FW_LEN16(*caps)); rc = -t4_wr_mbox(sc, sc->mbox, caps, sizeof(*caps), caps); if (rc != 0) return (rc); if (caps->niccaps & htobe16(FW_CAPS_CONFIG_NIC_VM)) caps->niccaps ^= htobe16(FW_CAPS_CONFIG_NIC_VM); caps->op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | F_FW_CMD_REQUEST | F_FW_CMD_WRITE); rc = -t4_wr_mbox(sc, sc->mbox, caps, sizeof(*caps), NULL); return (rc); } static int get_params(struct adapter *sc, struct fw_caps_config_cmd *caps) { int rc; uint32_t params[7], val[7]; #define FW_PARAM_DEV(param) \ (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) #define FW_PARAM_PFVF(param) \ (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) params[0] = FW_PARAM_DEV(PORTVEC); params[1] = FW_PARAM_PFVF(IQFLINT_START); params[2] = FW_PARAM_PFVF(EQ_START); params[3] = FW_PARAM_PFVF(FILTER_START); params[4] = FW_PARAM_PFVF(FILTER_END); rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 5, params, val); if (rc != 0) { device_printf(sc->dev, "failed to query parameters: %d.\n", rc); goto done; } sc->params.portvec = val[0]; sc->params.nports = 0; while (val[0]) { sc->params.nports++; val[0] &= val[0] - 1; } sc->sge.iq_start = val[1]; sc->sge.eq_start = val[2]; sc->tids.ftid_base = val[3]; sc->tids.nftids = val[4] - val[3] + 1; if (caps->toecaps) { /* query offload-related parameters */ params[0] = FW_PARAM_DEV(NTID); params[1] = FW_PARAM_PFVF(SERVER_START); params[2] = FW_PARAM_PFVF(SERVER_END); params[3] = FW_PARAM_PFVF(TDDP_START); params[4] = FW_PARAM_PFVF(TDDP_END); params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, params, val); if (rc != 0) { device_printf(sc->dev, "failed to query TOE parameters: %d.\n", rc); goto done; } sc->tids.ntids = val[0]; sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); sc->tids.stid_base = val[1]; sc->tids.nstids = val[2] - val[1] + 1; sc->vres.ddp.start = val[3]; sc->vres.ddp.size = val[4] - val[3] + 1; sc->params.ofldq_wr_cred = val[5]; sc->params.offload = 1; } if (caps->rdmacaps) { params[0] = FW_PARAM_PFVF(STAG_START); params[1] = FW_PARAM_PFVF(STAG_END); params[2] = FW_PARAM_PFVF(RQ_START); params[3] = FW_PARAM_PFVF(RQ_END); params[4] = FW_PARAM_PFVF(PBL_START); params[5] = FW_PARAM_PFVF(PBL_END); rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, params, val); if (rc != 0) { device_printf(sc->dev, "failed to query RDMA parameters: %d.\n", rc); goto done; } sc->vres.stag.start = val[0]; sc->vres.stag.size = val[1] - val[0] + 1; sc->vres.rq.start = val[2]; sc->vres.rq.size = val[3] - val[2] + 1; sc->vres.pbl.start = val[4]; sc->vres.pbl.size = val[5] - val[4] + 1; } if (caps->iscsicaps) { params[0] = FW_PARAM_PFVF(ISCSI_START); params[1] = FW_PARAM_PFVF(ISCSI_END); rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, params, val); if (rc != 0) { device_printf(sc->dev, "failed to query iSCSI parameters: %d.\n", rc); goto done; } sc->vres.iscsi.start = val[0]; sc->vres.iscsi.size = val[1] - val[0] + 1; } #undef FW_PARAM_PFVF #undef FW_PARAM_DEV done: return (rc); } static void t4_set_desc(struct adapter *sc) { char buf[128]; struct adapter_params *p = &sc->params; snprintf(buf, sizeof(buf), "Chelsio %s (rev %d) %d port %sNIC PCIe-x%d %d %s, S/N:%s, E/C:%s", p->vpd.id, p->rev, p->nports, is_offload(sc) ? "R" : "", p->pci.width, sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), p->vpd.sn, p->vpd.ec); device_set_desc_copy(sc->dev, buf); } static void build_medialist(struct port_info *pi) { struct ifmedia *media = &pi->media; int data, m; PORT_LOCK(pi); ifmedia_removeall(media); m = IFM_ETHER | IFM_FDX; data = (pi->port_type << 8) | pi->mod_type; switch(pi->port_type) { case FW_PORT_TYPE_BT_XFI: ifmedia_add(media, m | IFM_10G_T, data, NULL); break; case FW_PORT_TYPE_BT_XAUI: ifmedia_add(media, m | IFM_10G_T, data, NULL); /* fall through */ case FW_PORT_TYPE_BT_SGMII: ifmedia_add(media, m | IFM_1000_T, data, NULL); ifmedia_add(media, m | IFM_100_TX, data, NULL); ifmedia_add(media, IFM_ETHER | IFM_AUTO, data, NULL); ifmedia_set(media, IFM_ETHER | IFM_AUTO); break; case FW_PORT_TYPE_CX4: ifmedia_add(media, m | IFM_10G_CX4, data, NULL); ifmedia_set(media, m | IFM_10G_CX4); break; case FW_PORT_TYPE_SFP: case FW_PORT_TYPE_FIBER_XFI: case FW_PORT_TYPE_FIBER_XAUI: switch (pi->mod_type) { case FW_PORT_MOD_TYPE_LR: ifmedia_add(media, m | IFM_10G_LR, data, NULL); ifmedia_set(media, m | IFM_10G_LR); break; case FW_PORT_MOD_TYPE_SR: ifmedia_add(media, m | IFM_10G_SR, data, NULL); ifmedia_set(media, m | IFM_10G_SR); break; case FW_PORT_MOD_TYPE_LRM: ifmedia_add(media, m | IFM_10G_LRM, data, NULL); ifmedia_set(media, m | IFM_10G_LRM); break; case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: ifmedia_add(media, m | IFM_10G_TWINAX, data, NULL); ifmedia_set(media, m | IFM_10G_TWINAX); break; case FW_PORT_MOD_TYPE_NONE: m &= ~IFM_FDX; ifmedia_add(media, m | IFM_NONE, data, NULL); ifmedia_set(media, m | IFM_NONE); break; case FW_PORT_MOD_TYPE_NA: case FW_PORT_MOD_TYPE_ER: default: ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); ifmedia_set(media, m | IFM_UNKNOWN); break; } break; case FW_PORT_TYPE_KX4: case FW_PORT_TYPE_KX: case FW_PORT_TYPE_KR: default: ifmedia_add(media, m | IFM_UNKNOWN, data, NULL); ifmedia_set(media, m | IFM_UNKNOWN); break; } PORT_UNLOCK(pi); } /* * Program the port's XGMAC based on parameters in ifnet. The caller also * indicates which parameters should be programmed (the rest are left alone). */ static int update_mac_settings(struct port_info *pi, int flags) { int rc; struct ifnet *ifp = pi->ifp; struct adapter *sc = pi->adapter; int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; PORT_LOCK_ASSERT_OWNED(pi); KASSERT(flags, ("%s: not told what to update.", __func__)); if (flags & XGMAC_MTU) mtu = ifp->if_mtu; if (flags & XGMAC_PROMISC) promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; if (flags & XGMAC_ALLMULTI) allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; if (flags & XGMAC_VLANEX) vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; rc = -t4_set_rxmode(sc, sc->mbox, pi->viid, mtu, promisc, allmulti, 1, vlanex, false); if (rc) { if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, rc); return (rc); } if (flags & XGMAC_UCADDR) { uint8_t ucaddr[ETHER_ADDR_LEN]; bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); rc = t4_change_mac(sc, sc->mbox, pi->viid, pi->xact_addr_filt, ucaddr, true, true); if (rc < 0) { rc = -rc; if_printf(ifp, "change_mac failed: %d\n", rc); return (rc); } else { pi->xact_addr_filt = rc; rc = 0; } } if (flags & XGMAC_MCADDRS) { const uint8_t *mcaddr; int del = 1; uint64_t hash = 0; struct ifmultiaddr *ifma; if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; mcaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); rc = t4_alloc_mac_filt(sc, sc->mbox, pi->viid, del, 1, &mcaddr, NULL, &hash, 0); if (rc < 0) { rc = -rc; if_printf(ifp, "failed to add mc address" " %02x:%02x:%02x:%02x:%02x:%02x rc=%d\n", mcaddr[0], mcaddr[1], mcaddr[2], mcaddr[3], mcaddr[4], mcaddr[5], rc); goto mcfail; } del = 0; } rc = -t4_set_addr_hash(sc, sc->mbox, pi->viid, 0, hash, 0); if (rc != 0) if_printf(ifp, "failed to set mc address hash: %d", rc); mcfail: if_maddr_runlock(ifp); } return (rc); } static int cxgbe_init_locked(struct port_info *pi) { struct adapter *sc = pi->adapter; int rc = 0; ADAPTER_LOCK_ASSERT_OWNED(sc); while (!IS_DOOMED(pi) && IS_BUSY(sc)) { if (mtx_sleep(&sc->flags, &sc->sc_lock, PCATCH, "t4init", 0)) { rc = EINTR; goto done; } } if (IS_DOOMED(pi)) { rc = ENXIO; goto done; } KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); /* Give up the adapter lock, port init code can sleep. */ SET_BUSY(sc); ADAPTER_UNLOCK(sc); rc = cxgbe_init_synchronized(pi); done: ADAPTER_LOCK(sc); KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); CLR_BUSY(sc); wakeup_one(&sc->flags); ADAPTER_UNLOCK(sc); return (rc); } static int cxgbe_init_synchronized(struct port_info *pi) { struct adapter *sc = pi->adapter; struct ifnet *ifp = pi->ifp; int rc = 0, i; uint16_t *rss; struct sge_rxq *rxq; ADAPTER_LOCK_ASSERT_NOTOWNED(sc); if (isset(&sc->open_device_map, pi->port_id)) { KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("mismatch between open_device_map and if_drv_flags")); return (0); /* already running */ } if (sc->open_device_map == 0 && ((rc = first_port_up(sc)) != 0)) return (rc); /* error message displayed already */ /* * Allocate tx/rx/fl queues for this port. */ rc = t4_setup_eth_queues(pi); if (rc != 0) goto done; /* error message displayed already */ /* * Setup RSS for this port. */ rss = malloc(pi->nrxq * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); for_each_rxq(pi, i, rxq) { rss[i] = rxq->iq.abs_id; } rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, pi->rss_size, rss, pi->nrxq); free(rss, M_CXGBE); if (rc != 0) { if_printf(ifp, "rss_config failed: %d\n", rc); goto done; } PORT_LOCK(pi); rc = update_mac_settings(pi, XGMAC_ALL); PORT_UNLOCK(pi); if (rc) goto done; /* error message displayed already */ rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, &pi->link_cfg); if (rc != 0) { if_printf(ifp, "start_link failed: %d\n", rc); goto done; } rc = -t4_enable_vi(sc, sc->mbox, pi->viid, true, true); if (rc != 0) { if_printf(ifp, "enable_vi failed: %d\n", rc); goto done; } pi->flags |= VI_ENABLED; /* all ok */ setbit(&sc->open_device_map, pi->port_id); ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; callout_reset(&pi->tick, hz, cxgbe_tick, pi); done: if (rc != 0) cxgbe_uninit_synchronized(pi); return (rc); } static int cxgbe_uninit_locked(struct port_info *pi) { struct adapter *sc = pi->adapter; int rc; ADAPTER_LOCK_ASSERT_OWNED(sc); while (!IS_DOOMED(pi) && IS_BUSY(sc)) { if (mtx_sleep(&sc->flags, &sc->sc_lock, PCATCH, "t4uninit", 0)) { rc = EINTR; goto done; } } if (IS_DOOMED(pi)) { rc = ENXIO; goto done; } KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); SET_BUSY(sc); ADAPTER_UNLOCK(sc); rc = cxgbe_uninit_synchronized(pi); ADAPTER_LOCK(sc); KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); CLR_BUSY(sc); wakeup_one(&sc->flags); done: ADAPTER_UNLOCK(sc); return (rc); } /* * Idempotent. */ static int cxgbe_uninit_synchronized(struct port_info *pi) { struct adapter *sc = pi->adapter; struct ifnet *ifp = pi->ifp; int rc; /* * taskqueue_drain may cause a deadlock if the adapter lock is held. */ ADAPTER_LOCK_ASSERT_NOTOWNED(sc); /* * Clear this port's bit from the open device map, and then drain * tasks and callouts. */ clrbit(&sc->open_device_map, pi->port_id); PORT_LOCK(pi); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); callout_stop(&pi->tick); PORT_UNLOCK(pi); callout_drain(&pi->tick); /* * Stop and then free the queues' resources, including the queues * themselves. * * XXX: we could just stop the queues here (on ifconfig down) and free * them later (on port detach), but having up/down go through the entire * allocate/activate/deactivate/free sequence is a good way to find * leaks and bugs. */ rc = t4_teardown_eth_queues(pi); if (rc != 0) if_printf(ifp, "teardown failed: %d\n", rc); if (pi->flags & VI_ENABLED) { rc = -t4_enable_vi(sc, sc->mbox, pi->viid, false, false); if (rc) if_printf(ifp, "disable_vi failed: %d\n", rc); else pi->flags &= ~VI_ENABLED; } pi->link_cfg.link_ok = 0; pi->link_cfg.speed = 0; t4_os_link_changed(sc, pi->port_id, 0); if (sc->open_device_map == 0) last_port_down(sc); return (0); } -#define T4_ALLOC_IRQ(sc, irqid, rid, handler, arg, name) do { \ - rc = t4_alloc_irq(sc, &sc->irq[irqid], rid, handler, arg, name); \ +#define T4_ALLOC_IRQ(sc, irq, rid, handler, arg, name) do { \ + rc = t4_alloc_irq(sc, irq, rid, handler, arg, name); \ if (rc != 0) \ goto done; \ } while (0) static int first_port_up(struct adapter *sc) { - int rc, i; - char name[8]; + int rc, i, rid, p, q; + char s[8]; + struct irq *irq; + struct sge_iq *intrq; ADAPTER_LOCK_ASSERT_NOTOWNED(sc); /* * queues that belong to the adapter (not any particular port). */ rc = t4_setup_adapter_queues(sc); if (rc != 0) goto done; /* * Setup interrupts. */ + irq = &sc->irq[0]; + rid = sc->intr_type == INTR_INTX ? 0 : 1; if (sc->intr_count == 1) { - KASSERT(sc->flags & INTR_FWD, - ("%s: single interrupt but not forwarded?", __func__)); - T4_ALLOC_IRQ(sc, 0, 0, t4_intr_all, sc, "all"); + KASSERT(sc->flags & INTR_SHARED, + ("%s: single interrupt but not shared?", __func__)); + + T4_ALLOC_IRQ(sc, irq, rid, t4_intr_all, sc, "all"); } else { /* Multiple interrupts. The first one is always error intr */ - T4_ALLOC_IRQ(sc, 0, 1, t4_intr_err, sc, "err"); + T4_ALLOC_IRQ(sc, irq, rid, t4_intr_err, sc, "err"); + irq++; + rid++; - if (sc->flags & INTR_FWD) { - /* The rest are shared by the fwq and all data intr */ - for (i = 1; i < sc->intr_count; i++) { - snprintf(name, sizeof(name), "mux%d", i - 1); - T4_ALLOC_IRQ(sc, i, i + 1, t4_intr_fwd, - &sc->sge.fiq[i - 1], name); + /* Firmware event queue normally has an interrupt of its own */ + if (sc->intr_count > T4_EXTRA_INTR) { + T4_ALLOC_IRQ(sc, irq, rid, t4_intr_evt, &sc->sge.fwq, + "evt"); + irq++; + rid++; + } + + intrq = &sc->sge.intrq[0]; + if (sc->flags & INTR_SHARED) { + + /* All ports share these interrupt queues */ + + for (i = 0; i < NINTRQ(sc); i++) { + snprintf(s, sizeof(s), "*.%d", i); + T4_ALLOC_IRQ(sc, irq, rid, t4_intr, intrq, s); + irq++; + rid++; + intrq++; } } else { - struct port_info *pi; - int p, q; - T4_ALLOC_IRQ(sc, 1, 2, t4_intr_evt, &sc->sge.fwq, - "evt"); + /* Each port has its own set of interrupt queues */ - p = q = 0; - pi = sc->port[p]; - for (i = 2; i < sc->intr_count; i++) { - snprintf(name, sizeof(name), "p%dq%d", p, q); - if (++q >= pi->nrxq) { - p++; - q = 0; - pi = sc->port[p]; + for (p = 0; p < sc->params.nports; p++) { + for (q = 0; q < sc->port[p]->nrxq; q++) { + snprintf(s, sizeof(s), "%d.%d", p, q); + T4_ALLOC_IRQ(sc, irq, rid, t4_intr, + intrq, s); + irq++; + rid++; + intrq++; } - T4_ALLOC_IRQ(sc, i, i + 1, t4_intr_data, - &sc->sge.rxq[i - 2], name); } } } t4_intr_enable(sc); sc->flags |= FULL_INIT_DONE; done: if (rc != 0) last_port_down(sc); return (rc); } #undef T4_ALLOC_IRQ /* * Idempotent. */ static int last_port_down(struct adapter *sc) { int i; ADAPTER_LOCK_ASSERT_NOTOWNED(sc); t4_intr_disable(sc); t4_teardown_adapter_queues(sc); for (i = 0; i < sc->intr_count; i++) t4_free_irq(sc, &sc->irq[i]); sc->flags &= ~FULL_INIT_DONE; return (0); } static int t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, iq_intr_handler_t *handler, void *arg, char *name) { int rc; irq->rid = rid; irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, RF_SHAREABLE | RF_ACTIVE); if (irq->res == NULL) { device_printf(sc->dev, "failed to allocate IRQ for rid %d, name %s.\n", rid, name); return (ENOMEM); } rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, NULL, handler, arg, &irq->tag); if (rc != 0) { device_printf(sc->dev, "failed to setup interrupt for rid %d, name %s: %d\n", rid, name, rc); } else if (name) bus_describe_intr(sc->dev, irq->res, irq->tag, name); return (rc); } static int t4_free_irq(struct adapter *sc, struct irq *irq) { if (irq->tag) bus_teardown_intr(sc->dev, irq->res, irq->tag); if (irq->res) bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); bzero(irq, sizeof(*irq)); return (0); } static void reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start, unsigned int end) { uint32_t *p = (uint32_t *)(buf + start); for ( ; start <= end; start += sizeof(uint32_t)) *p++ = t4_read_reg(sc, start); } static void t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) { int i; static const unsigned int reg_ranges[] = { 0x1008, 0x1108, 0x1180, 0x11b4, 0x11fc, 0x123c, 0x1300, 0x173c, 0x1800, 0x18fc, 0x3000, 0x30d8, 0x30e0, 0x5924, 0x5960, 0x59d4, 0x5a00, 0x5af8, 0x6000, 0x6098, 0x6100, 0x6150, 0x6200, 0x6208, 0x6240, 0x6248, 0x6280, 0x6338, 0x6370, 0x638c, 0x6400, 0x643c, 0x6500, 0x6524, 0x6a00, 0x6a38, 0x6a60, 0x6a78, 0x6b00, 0x6b84, 0x6bf0, 0x6c84, 0x6cf0, 0x6d84, 0x6df0, 0x6e84, 0x6ef0, 0x6f84, 0x6ff0, 0x7084, 0x70f0, 0x7184, 0x71f0, 0x7284, 0x72f0, 0x7384, 0x73f0, 0x7450, 0x7500, 0x7530, 0x7600, 0x761c, 0x7680, 0x76cc, 0x7700, 0x7798, 0x77c0, 0x77fc, 0x7900, 0x79fc, 0x7b00, 0x7c38, 0x7d00, 0x7efc, 0x8dc0, 0x8e1c, 0x8e30, 0x8e78, 0x8ea0, 0x8f6c, 0x8fc0, 0x9074, 0x90fc, 0x90fc, 0x9400, 0x9458, 0x9600, 0x96bc, 0x9800, 0x9808, 0x9820, 0x983c, 0x9850, 0x9864, 0x9c00, 0x9c6c, 0x9c80, 0x9cec, 0x9d00, 0x9d6c, 0x9d80, 0x9dec, 0x9e00, 0x9e6c, 0x9e80, 0x9eec, 0x9f00, 0x9f6c, 0x9f80, 0x9fec, 0xd004, 0xd03c, 0xdfc0, 0xdfe0, 0xe000, 0xea7c, 0xf000, 0x11190, 0x19040, 0x19124, 0x19150, 0x191b0, 0x191d0, 0x191e8, 0x19238, 0x1924c, 0x193f8, 0x19474, 0x19490, 0x194f8, 0x19800, 0x19f30, 0x1a000, 0x1a06c, 0x1a0b0, 0x1a120, 0x1a128, 0x1a138, 0x1a190, 0x1a1c4, 0x1a1fc, 0x1a1fc, 0x1e040, 0x1e04c, 0x1e240, 0x1e28c, 0x1e2c0, 0x1e2c0, 0x1e2e0, 0x1e2e0, 0x1e300, 0x1e384, 0x1e3c0, 0x1e3c8, 0x1e440, 0x1e44c, 0x1e640, 0x1e68c, 0x1e6c0, 0x1e6c0, 0x1e6e0, 0x1e6e0, 0x1e700, 0x1e784, 0x1e7c0, 0x1e7c8, 0x1e840, 0x1e84c, 0x1ea40, 0x1ea8c, 0x1eac0, 0x1eac0, 0x1eae0, 0x1eae0, 0x1eb00, 0x1eb84, 0x1ebc0, 0x1ebc8, 0x1ec40, 0x1ec4c, 0x1ee40, 0x1ee8c, 0x1eec0, 0x1eec0, 0x1eee0, 0x1eee0, 0x1ef00, 0x1ef84, 0x1efc0, 0x1efc8, 0x1f040, 0x1f04c, 0x1f240, 0x1f28c, 0x1f2c0, 0x1f2c0, 0x1f2e0, 0x1f2e0, 0x1f300, 0x1f384, 0x1f3c0, 0x1f3c8, 0x1f440, 0x1f44c, 0x1f640, 0x1f68c, 0x1f6c0, 0x1f6c0, 0x1f6e0, 0x1f6e0, 0x1f700, 0x1f784, 0x1f7c0, 0x1f7c8, 0x1f840, 0x1f84c, 0x1fa40, 0x1fa8c, 0x1fac0, 0x1fac0, 0x1fae0, 0x1fae0, 0x1fb00, 0x1fb84, 0x1fbc0, 0x1fbc8, 0x1fc40, 0x1fc4c, 0x1fe40, 0x1fe8c, 0x1fec0, 0x1fec0, 0x1fee0, 0x1fee0, 0x1ff00, 0x1ff84, 0x1ffc0, 0x1ffc8, 0x20000, 0x2002c, 0x20100, 0x2013c, 0x20190, 0x201c8, 0x20200, 0x20318, 0x20400, 0x20528, 0x20540, 0x20614, 0x21000, 0x21040, 0x2104c, 0x21060, 0x210c0, 0x210ec, 0x21200, 0x21268, 0x21270, 0x21284, 0x212fc, 0x21388, 0x21400, 0x21404, 0x21500, 0x21518, 0x2152c, 0x2153c, 0x21550, 0x21554, 0x21600, 0x21600, 0x21608, 0x21628, 0x21630, 0x2163c, 0x21700, 0x2171c, 0x21780, 0x2178c, 0x21800, 0x21c38, 0x21c80, 0x21d7c, 0x21e00, 0x21e04, 0x22000, 0x2202c, 0x22100, 0x2213c, 0x22190, 0x221c8, 0x22200, 0x22318, 0x22400, 0x22528, 0x22540, 0x22614, 0x23000, 0x23040, 0x2304c, 0x23060, 0x230c0, 0x230ec, 0x23200, 0x23268, 0x23270, 0x23284, 0x232fc, 0x23388, 0x23400, 0x23404, 0x23500, 0x23518, 0x2352c, 0x2353c, 0x23550, 0x23554, 0x23600, 0x23600, 0x23608, 0x23628, 0x23630, 0x2363c, 0x23700, 0x2371c, 0x23780, 0x2378c, 0x23800, 0x23c38, 0x23c80, 0x23d7c, 0x23e00, 0x23e04, 0x24000, 0x2402c, 0x24100, 0x2413c, 0x24190, 0x241c8, 0x24200, 0x24318, 0x24400, 0x24528, 0x24540, 0x24614, 0x25000, 0x25040, 0x2504c, 0x25060, 0x250c0, 0x250ec, 0x25200, 0x25268, 0x25270, 0x25284, 0x252fc, 0x25388, 0x25400, 0x25404, 0x25500, 0x25518, 0x2552c, 0x2553c, 0x25550, 0x25554, 0x25600, 0x25600, 0x25608, 0x25628, 0x25630, 0x2563c, 0x25700, 0x2571c, 0x25780, 0x2578c, 0x25800, 0x25c38, 0x25c80, 0x25d7c, 0x25e00, 0x25e04, 0x26000, 0x2602c, 0x26100, 0x2613c, 0x26190, 0x261c8, 0x26200, 0x26318, 0x26400, 0x26528, 0x26540, 0x26614, 0x27000, 0x27040, 0x2704c, 0x27060, 0x270c0, 0x270ec, 0x27200, 0x27268, 0x27270, 0x27284, 0x272fc, 0x27388, 0x27400, 0x27404, 0x27500, 0x27518, 0x2752c, 0x2753c, 0x27550, 0x27554, 0x27600, 0x27600, 0x27608, 0x27628, 0x27630, 0x2763c, 0x27700, 0x2771c, 0x27780, 0x2778c, 0x27800, 0x27c38, 0x27c80, 0x27d7c, 0x27e00, 0x27e04 }; regs->version = 4 | (sc->params.rev << 10); for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2) reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]); } static void cxgbe_tick(void *arg) { struct port_info *pi = arg; struct ifnet *ifp = pi->ifp; struct sge_txq *txq; int i, drops; struct port_stats *s = &pi->stats; PORT_LOCK(pi); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { PORT_UNLOCK(pi); return; /* without scheduling another callout */ } t4_get_port_stats(pi->adapter, pi->tx_chan, s); ifp->if_opackets = s->tx_frames; ifp->if_ipackets = s->rx_frames; ifp->if_obytes = s->tx_octets; ifp->if_ibytes = s->rx_octets; ifp->if_omcasts = s->tx_mcast_frames; ifp->if_imcasts = s->rx_mcast_frames; ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + s->rx_ovflow3; drops = s->tx_drop; for_each_txq(pi, i, txq) drops += txq->br->br_drops; ifp->if_snd.ifq_drops = drops; ifp->if_oerrors = s->tx_error_frames; ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long + s->rx_fcs_err + s->rx_len_err; callout_schedule(&pi->tick, hz); PORT_UNLOCK(pi); } static int t4_sysctls(struct adapter *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid *oid; struct sysctl_oid_list *children; ctx = device_get_sysctl_ctx(sc->dev); oid = device_get_sysctl_tree(sc->dev); children = SYSCTL_CHILDREN(oid); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, &sc->params.nports, 0, "# of ports"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, &sc->params.rev, 0, "chip hardware revision"); SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", CTLFLAG_RD, &sc->fw_version, 0, "firmware version"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "TOE", CTLFLAG_RD, &sc->params.offload, 0, "hardware is capable of TCP offload"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, &sc->params.vpd.cclk, 0, "core clock frequency (in KHz)"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", CTLTYPE_STRING | CTLFLAG_RD, &intr_timer, sizeof(intr_timer), sysctl_int_array, "A", "interrupt holdoff timer values (us)"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", CTLTYPE_STRING | CTLFLAG_RD, &intr_pktcount, sizeof(intr_pktcount), sysctl_int_array, "A", "interrupt holdoff packet counter values"); +#ifdef T4_DEVLOG + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", + CTLTYPE_STRING | CTLFLAG_RD, sc, 0, + sysctl_devlog, "A", "device log"); +#endif + return (0); } static int cxgbe_sysctls(struct port_info *pi) { struct sysctl_ctx_list *ctx; struct sysctl_oid *oid; struct sysctl_oid_list *children; ctx = device_get_sysctl_ctx(pi->dev); /* * dev.cxgbe.X. */ oid = device_get_sysctl_tree(pi->dev); children = SYSCTL_CHILDREN(oid); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, &pi->nrxq, 0, "# of rx queues"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, &pi->ntxq, 0, "# of tx queues"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, &pi->first_rxq, 0, "index of first rx queue"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, &pi->first_txq, 0, "index of first tx queue"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I", "holdoff timer index"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_pktc_idx, "I", "holdoff packet counter index"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_rxq, "I", "rx queue size"); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_txq, "I", "tx queue size"); /* * dev.cxgbe.X.stats. */ oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, NULL, "port statistics"); children = SYSCTL_CHILDREN(oid); #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ - CTLTYPE_QUAD | CTLFLAG_RD, pi->adapter, reg, \ + CTLTYPE_U64 | CTLFLAG_RD, pi->adapter, reg, \ sysctl_handle_t4_reg64, "QU", desc) SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", "# of tx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", "# of tx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", "# of tx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", "# of tx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", "# of tx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", "# of tx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", "# of tx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", "# of frames received with bad FCS", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); SYSCTL_ADD_T4_REG64(pi, "rx_len_err", "# of frames received with length error", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", "# of rx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", "# of rx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", "# of rx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", "# of rx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", "# of rx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", "# of rx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", "# of rx frames in this range", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); #undef SYSCTL_ADD_T4_REG64 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ - SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ + SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ &pi->stats.name, desc) /* We get these from port_stats and they may be stale by upto 1s */ SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, "# drops due to buffer-group 0 overflows"); SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, "# drops due to buffer-group 1 overflows"); SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, "# drops due to buffer-group 2 overflows"); SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, "# drops due to buffer-group 3 overflows"); SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, "# of buffer-group 0 truncated packets"); SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, "# of buffer-group 1 truncated packets"); SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, "# of buffer-group 2 truncated packets"); SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, "# of buffer-group 3 truncated packets"); #undef SYSCTL_ADD_T4_PORTSTAT return (0); } static int sysctl_int_array(SYSCTL_HANDLER_ARGS) { int rc, *i; struct sbuf sb; sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND); for (i = arg1; arg2; arg2 -= sizeof(int), i++) sbuf_printf(&sb, "%d ", *i); sbuf_trim(&sb); sbuf_finish(&sb); rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); sbuf_delete(&sb); return (rc); } static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) { struct port_info *pi = arg1; struct adapter *sc = pi->adapter; struct sge_rxq *rxq; int idx, rc, i; idx = pi->tmr_idx; rc = sysctl_handle_int(oidp, &idx, 0, req); if (rc != 0 || req->newptr == NULL) return (rc); if (idx < 0 || idx >= SGE_NTIMERS) return (EINVAL); ADAPTER_LOCK(sc); rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (rc == 0) { for_each_rxq(pi, i, rxq) { rxq->iq.intr_params = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(pi->pktc_idx != -1); } pi->tmr_idx = idx; } ADAPTER_UNLOCK(sc); return (rc); } static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) { struct port_info *pi = arg1; struct adapter *sc = pi->adapter; int idx, rc; idx = pi->pktc_idx; rc = sysctl_handle_int(oidp, &idx, 0, req); if (rc != 0 || req->newptr == NULL) return (rc); if (idx < -1 || idx >= SGE_NCOUNTERS) return (EINVAL); ADAPTER_LOCK(sc); rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) rc = EBUSY; /* can be changed only when port is down */ if (rc == 0) pi->pktc_idx = idx; ADAPTER_UNLOCK(sc); return (rc); } static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) { struct port_info *pi = arg1; struct adapter *sc = pi->adapter; int qsize, rc; qsize = pi->qsize_rxq; rc = sysctl_handle_int(oidp, &qsize, 0, req); if (rc != 0 || req->newptr == NULL) return (rc); if (qsize < 128 || (qsize & 7)) return (EINVAL); ADAPTER_LOCK(sc); rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) rc = EBUSY; /* can be changed only when port is down */ if (rc == 0) pi->qsize_rxq = qsize; ADAPTER_UNLOCK(sc); return (rc); } static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) { struct port_info *pi = arg1; struct adapter *sc = pi->adapter; int qsize, rc; qsize = pi->qsize_txq; rc = sysctl_handle_int(oidp, &qsize, 0, req); if (rc != 0 || req->newptr == NULL) return (rc); if (qsize < 128) return (EINVAL); ADAPTER_LOCK(sc); rc = IS_DOOMED(pi) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (rc == 0 && pi->ifp->if_drv_flags & IFF_DRV_RUNNING) rc = EBUSY; /* can be changed only when port is down */ if (rc == 0) pi->qsize_txq = qsize; ADAPTER_UNLOCK(sc); return (rc); } static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) { struct adapter *sc = arg1; int reg = arg2; uint64_t val; val = t4_read_reg64(sc, reg); - return (sysctl_handle_quad(oidp, &val, 0, req)); + return (sysctl_handle_64(oidp, &val, 0, req)); } +#ifdef T4_DEVLOG +const char *devlog_level_strings[] = { + [FW_DEVLOG_LEVEL_EMERG] = "EMERG", + [FW_DEVLOG_LEVEL_CRIT] = "CRIT", + [FW_DEVLOG_LEVEL_ERR] = "ERR", + [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", + [FW_DEVLOG_LEVEL_INFO] = "INFO", + [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" +}; + +const char *devlog_facility_strings[] = { + [FW_DEVLOG_FACILITY_CORE] = "CORE", + [FW_DEVLOG_FACILITY_SCHED] = "SCHED", + [FW_DEVLOG_FACILITY_TIMER] = "TIMER", + [FW_DEVLOG_FACILITY_RES] = "RES", + [FW_DEVLOG_FACILITY_HW] = "HW", + [FW_DEVLOG_FACILITY_FLR] = "FLR", + [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", + [FW_DEVLOG_FACILITY_PHY] = "PHY", + [FW_DEVLOG_FACILITY_MAC] = "MAC", + [FW_DEVLOG_FACILITY_PORT] = "PORT", + [FW_DEVLOG_FACILITY_VI] = "VI", + [FW_DEVLOG_FACILITY_FILTER] = "FILTER", + [FW_DEVLOG_FACILITY_ACL] = "ACL", + [FW_DEVLOG_FACILITY_TM] = "TM", + [FW_DEVLOG_FACILITY_QFC] = "QFC", + [FW_DEVLOG_FACILITY_DCB] = "DCB", + [FW_DEVLOG_FACILITY_ETH] = "ETH", + [FW_DEVLOG_FACILITY_OFLD] = "OFLD", + [FW_DEVLOG_FACILITY_RI] = "RI", + [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", + [FW_DEVLOG_FACILITY_FCOE] = "FCOE", + [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", + [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE" +}; + +static int +sysctl_devlog(SYSCTL_HANDLER_ARGS) +{ + struct adapter *sc = arg1; + struct devlog_params *dparams = &sc->params.devlog; + struct fw_devlog_e *buf, *e; + int i, j, rc, nentries, first = 0; + struct sbuf *sb; + uint64_t ftstamp = UINT64_MAX; + + if (dparams->start == 0) + return (ENXIO); + + nentries = dparams->size / sizeof(struct fw_devlog_e); + + buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); + if (buf == NULL) + return (ENOMEM); + + rc = -t4_mem_read(sc, dparams->memtype, dparams->start, dparams->size, + (void *)buf); + if (rc != 0) + goto done; + + for (i = 0; i < nentries; i++) { + e = &buf[i]; + + if (e->timestamp == 0) + break; /* end */ + + e->timestamp = be64toh(e->timestamp); + e->seqno = be32toh(e->seqno); + for (j = 0; j < 8; j++) + e->params[j] = be32toh(e->params[j]); + + if (e->timestamp < ftstamp) { + ftstamp = e->timestamp; + first = i; + } + } + + if (buf[first].timestamp == 0) + goto done; /* nothing in the log */ + + rc = sysctl_wire_old_buffer(req, 0); + if (rc != 0) + goto done; + + sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); + sbuf_printf(sb, "\n%10s %15s %8s %8s %s\n", + "Seq#", "Tstamp", "Level", "Facility", "Message"); + + i = first; + do { + e = &buf[i]; + if (e->timestamp == 0) + break; /* end */ + + sbuf_printf(sb, "%10d %15ju %8s %8s ", + e->seqno, e->timestamp, + (e->level < ARRAY_SIZE(devlog_level_strings) ? + devlog_level_strings[e->level] : "UNKNOWN"), + (e->facility < ARRAY_SIZE(devlog_facility_strings) ? + devlog_facility_strings[e->facility] : "UNKNOWN")); + sbuf_printf(sb, e->fmt, e->params[0], e->params[1], + e->params[2], e->params[3], e->params[4], + e->params[5], e->params[6], e->params[7]); + + if (++i == nentries) + i = 0; + } while (i != first); + + rc = sbuf_finish(sb); + sbuf_delete(sb); +done: + free(buf, M_CXGBE); + return (rc); +} +#endif + static inline void txq_start(struct ifnet *ifp, struct sge_txq *txq) { struct buf_ring *br; struct mbuf *m; TXQ_LOCK_ASSERT_OWNED(txq); br = txq->br; m = txq->m ? txq->m : drbr_dequeue(ifp, br); if (m) t4_eth_tx(ifp, txq, m); } void cxgbe_txq_start(void *arg, int count) { struct sge_txq *txq = arg; TXQ_LOCK(txq); if (txq->eq.flags & EQ_CRFLUSHED) { txq->eq.flags &= ~EQ_CRFLUSHED; txq_start(txq->ifp, txq); } else wakeup_one(txq); /* txq is going away, wakeup free_txq */ TXQ_UNLOCK(txq); } static uint32_t fconf_to_mode(uint32_t fconf) { uint32_t mode; mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR | T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT; if (fconf & F_FRAGMENTATION) mode |= T4_FILTER_IP_FRAGMENT; if (fconf & F_MPSHITTYPE) mode |= T4_FILTER_MPS_HIT_TYPE; if (fconf & F_MACMATCH) mode |= T4_FILTER_MAC_IDX; if (fconf & F_ETHERTYPE) mode |= T4_FILTER_ETH_TYPE; if (fconf & F_PROTOCOL) mode |= T4_FILTER_IP_PROTO; if (fconf & F_TOS) mode |= T4_FILTER_IP_TOS; if (fconf & F_VLAN) mode |= T4_FILTER_IVLAN; if (fconf & F_VNIC_ID) mode |= T4_FILTER_OVLAN; if (fconf & F_PORT) mode |= T4_FILTER_PORT; if (fconf & F_FCOE) mode |= T4_FILTER_FCoE; return (mode); } static uint32_t mode_to_fconf(uint32_t mode) { uint32_t fconf = 0; if (mode & T4_FILTER_IP_FRAGMENT) fconf |= F_FRAGMENTATION; if (mode & T4_FILTER_MPS_HIT_TYPE) fconf |= F_MPSHITTYPE; if (mode & T4_FILTER_MAC_IDX) fconf |= F_MACMATCH; if (mode & T4_FILTER_ETH_TYPE) fconf |= F_ETHERTYPE; if (mode & T4_FILTER_IP_PROTO) fconf |= F_PROTOCOL; if (mode & T4_FILTER_IP_TOS) fconf |= F_TOS; if (mode & T4_FILTER_IVLAN) fconf |= F_VLAN; if (mode & T4_FILTER_OVLAN) fconf |= F_VNIC_ID; if (mode & T4_FILTER_PORT) fconf |= F_PORT; if (mode & T4_FILTER_FCoE) fconf |= F_FCOE; return (fconf); } static uint32_t fspec_to_fconf(struct t4_filter_specification *fs) { uint32_t fconf = 0; if (fs->val.frag || fs->mask.frag) fconf |= F_FRAGMENTATION; if (fs->val.matchtype || fs->mask.matchtype) fconf |= F_MPSHITTYPE; if (fs->val.macidx || fs->mask.macidx) fconf |= F_MACMATCH; if (fs->val.ethtype || fs->mask.ethtype) fconf |= F_ETHERTYPE; if (fs->val.proto || fs->mask.proto) fconf |= F_PROTOCOL; if (fs->val.tos || fs->mask.tos) fconf |= F_TOS; if (fs->val.ivlan_vld || fs->mask.ivlan_vld) fconf |= F_VLAN; if (fs->val.ovlan_vld || fs->mask.ovlan_vld) fconf |= F_VNIC_ID; if (fs->val.iport || fs->mask.iport) fconf |= F_PORT; if (fs->val.fcoe || fs->mask.fcoe) fconf |= F_FCOE; return (fconf); } static int get_filter_mode(struct adapter *sc, uint32_t *mode) { uint32_t fconf; t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &fconf, 1, A_TP_VLAN_PRI_MAP); *mode = fconf_to_mode(fconf); return (0); } static int set_filter_mode(struct adapter *sc, uint32_t mode) { uint32_t fconf; int rc; fconf = mode_to_fconf(mode); ADAPTER_LOCK(sc); if (IS_BUSY(sc)) { rc = EAGAIN; goto done; } if (sc->tids.ftids_in_use > 0) { rc = EBUSY; goto done; } rc = -t4_set_filter_mode(sc, fconf); done: ADAPTER_UNLOCK(sc); return (rc); } +static inline uint64_t +get_filter_hits(struct adapter *sc, uint32_t fid) +{ + uint32_t tcb_base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); + uint64_t hits; + + t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 0), + tcb_base + (fid + sc->tids.ftid_base) * TCB_SIZE); + t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 0)); + hits = t4_read_reg64(sc, MEMWIN0_BASE + 16); + + return (be64toh(hits)); +} + static int get_filter(struct adapter *sc, struct t4_filter *t) { int i, nfilters = sc->tids.nftids; struct filter_entry *f; ADAPTER_LOCK_ASSERT_OWNED(sc); if (IS_BUSY(sc)) return (EAGAIN); if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL || t->idx >= nfilters) { t->idx = 0xffffffff; return (0); } f = &sc->tids.ftid_tab[t->idx]; for (i = t->idx; i < nfilters; i++, f++) { if (f->valid) { t->idx = i; + t->l2tidx = f->l2t ? f->l2t->idx : 0; + t->smtidx = f->smtidx; + if (f->fs.hitcnts) + t->hits = get_filter_hits(sc, t->idx); + else + t->hits = UINT64_MAX; t->fs = f->fs; - t->hits = 0; /* XXX implement */ return (0); } } t->idx = 0xffffffff; return (0); } static int set_filter(struct adapter *sc, struct t4_filter *t) { uint32_t fconf; unsigned int nfilters, nports; struct filter_entry *f; int i; ADAPTER_LOCK_ASSERT_OWNED(sc); nfilters = sc->tids.nftids; nports = sc->params.nports; if (nfilters == 0) return (ENOTSUP); if (!(sc->flags & FULL_INIT_DONE)) return (EAGAIN); if (t->idx >= nfilters) return (EINVAL); /* Validate against the global filter mode */ t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &fconf, 1, A_TP_VLAN_PRI_MAP); if ((fconf | fspec_to_fconf(&t->fs)) != fconf) return (E2BIG); if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) return (EINVAL); if (t->fs.val.iport >= nports) return (EINVAL); /* Can't specify an iq if not steering to it */ if (!t->fs.dirsteer && t->fs.iq) return (EINVAL); /* IPv6 filter idx must be 4 aligned */ if (t->fs.type == 1 && ((t->idx & 0x3) || t->idx + 4 >= nfilters)) return (EINVAL); if (sc->tids.ftid_tab == NULL) { KASSERT(sc->tids.ftids_in_use == 0, ("%s: no memory allocated but filters_in_use > 0", __func__)); sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) * nfilters, M_CXGBE, M_NOWAIT | M_ZERO); if (sc->tids.ftid_tab == NULL) return (ENOMEM); } for (i = 0; i < 4; i++) { f = &sc->tids.ftid_tab[t->idx + i]; if (f->pending || f->valid) return (EBUSY); if (f->locked) return (EPERM); if (t->fs.type == 0) break; } f = &sc->tids.ftid_tab[t->idx]; f->fs = t->fs; return set_filter_wr(sc, t->idx); } static int del_filter(struct adapter *sc, struct t4_filter *t) { unsigned int nfilters; struct filter_entry *f; ADAPTER_LOCK_ASSERT_OWNED(sc); if (IS_BUSY(sc)) return (EAGAIN); nfilters = sc->tids.nftids; if (nfilters == 0) return (ENOTSUP); if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 || t->idx >= nfilters) return (EINVAL); if (!(sc->flags & FULL_INIT_DONE)) return (EAGAIN); f = &sc->tids.ftid_tab[t->idx]; if (f->pending) return (EBUSY); if (f->locked) return (EPERM); if (f->valid) { t->fs = f->fs; /* extra info for the caller */ return del_filter_wr(sc, t->idx); } return (0); } -/* XXX: L2T */ static void -clear_filter(struct adapter *sc, struct filter_entry *f) +clear_filter(struct filter_entry *f) { - (void) sc; + if (f->l2t) + t4_l2t_release(f->l2t); + bzero(f, sizeof (*f)); } static int set_filter_wr(struct adapter *sc, int fidx) { int rc; struct filter_entry *f = &sc->tids.ftid_tab[fidx]; struct mbuf *m; struct fw_filter_wr *fwr; unsigned int ftid; ADAPTER_LOCK_ASSERT_OWNED(sc); - if (f->fs.newdmac || f->fs.newvlan) - return (ENOTSUP); /* XXX: fix after L2T code */ + if (f->fs.newdmac || f->fs.newvlan) { + /* This filter needs an L2T entry; allocate one. */ + f->l2t = t4_l2t_alloc_switching(sc->l2t); + if (f->l2t == NULL) + return (EAGAIN); + if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport, + f->fs.dmac)) { + t4_l2t_release(f->l2t); + f->l2t = NULL; + return (ENOMEM); + } + } ftid = sc->tids.ftid_base + fidx; m = m_gethdr(M_NOWAIT, MT_DATA); if (m == NULL) return (ENOMEM); fwr = mtod(m, struct fw_filter_wr *); m->m_len = m->m_pkthdr.len = sizeof(*fwr); bzero(fwr, sizeof (*fwr)); fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR)); fwr->len16_pkd = htobe32(FW_LEN16(*fwr)); fwr->tid_to_iq = htobe32(V_FW_FILTER_WR_TID(ftid) | V_FW_FILTER_WR_RQTYPE(f->fs.type) | V_FW_FILTER_WR_NOREPLY(0) | V_FW_FILTER_WR_IQ(f->fs.iq)); fwr->del_filter_to_l2tix = htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) | V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) | V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) | V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) | V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) | V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) | V_FW_FILTER_WR_DMAC(f->fs.newdmac) | V_FW_FILTER_WR_SMAC(f->fs.newsmac) | V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT || f->fs.newvlan == VLAN_REWRITE) | V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE || f->fs.newvlan == VLAN_REWRITE) | V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) | V_FW_FILTER_WR_TXCHAN(f->fs.eport) | V_FW_FILTER_WR_PRIO(f->fs.prio) | - V_FW_FILTER_WR_L2TIX(0)); /* XXX: L2T */ + V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0)); fwr->ethtype = htobe16(f->fs.val.ethtype); fwr->ethtypem = htobe16(f->fs.mask.ethtype); fwr->frag_to_ovlan_vldm = (V_FW_FILTER_WR_FRAG(f->fs.val.frag) | V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) | V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) | V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) | V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) | V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld)); fwr->smac_sel = 0; fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) | - V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id)); + V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.intrq[0].abs_id)); fwr->maci_to_matchtypem = htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) | V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) | V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) | V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) | V_FW_FILTER_WR_PORT(f->fs.val.iport) | V_FW_FILTER_WR_PORTM(f->fs.mask.iport) | V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) | V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype)); fwr->ptcl = f->fs.val.proto; fwr->ptclm = f->fs.mask.proto; fwr->ttyp = f->fs.val.tos; fwr->ttypm = f->fs.mask.tos; fwr->ivlan = htobe16(f->fs.val.ivlan); fwr->ivlanm = htobe16(f->fs.mask.ivlan); fwr->ovlan = htobe16(f->fs.val.ovlan); fwr->ovlanm = htobe16(f->fs.mask.ovlan); bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip)); bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm)); bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip)); bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm)); fwr->lp = htobe16(f->fs.val.dport); fwr->lpm = htobe16(f->fs.mask.dport); fwr->fp = htobe16(f->fs.val.sport); fwr->fpm = htobe16(f->fs.mask.sport); if (f->fs.newsmac) bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma)); f->pending = 1; sc->tids.ftids_in_use++; rc = t4_mgmt_tx(sc, m); if (rc != 0) { sc->tids.ftids_in_use--; m_freem(m); - clear_filter(sc, f); + clear_filter(f); } return (rc); } static int del_filter_wr(struct adapter *sc, int fidx) { struct filter_entry *f = &sc->tids.ftid_tab[fidx]; struct mbuf *m; struct fw_filter_wr *fwr; unsigned int rc, ftid; ADAPTER_LOCK_ASSERT_OWNED(sc); ftid = sc->tids.ftid_base + fidx; m = m_gethdr(M_NOWAIT, MT_DATA); if (m == NULL) return (ENOMEM); fwr = mtod(m, struct fw_filter_wr *); m->m_len = m->m_pkthdr.len = sizeof(*fwr); bzero(fwr, sizeof (*fwr)); - t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id); + t4_mk_filtdelwr(ftid, fwr, sc->sge.intrq[0].abs_id); f->pending = 1; rc = t4_mgmt_tx(sc, m); if (rc != 0) { f->pending = 0; m_freem(m); } return (rc); } /* XXX move intr handlers to main.c and make this static */ void filter_rpl(struct adapter *sc, const struct cpl_set_tcb_rpl *rpl) { unsigned int idx = GET_TID(rpl); if (idx >= sc->tids.ftid_base && (idx -= sc->tids.ftid_base) < sc->tids.nftids) { unsigned int rc = G_COOKIE(rpl->cookie); struct filter_entry *f = &sc->tids.ftid_tab[idx]; if (rc == FW_FILTER_WR_FLT_DELETED) { /* * Clear the filter when we get confirmation from the * hardware that the filter has been deleted. */ - clear_filter(sc, f); + clear_filter(f); sc->tids.ftids_in_use--; } else if (rc == FW_FILTER_WR_SMT_TBL_FULL) { device_printf(sc->dev, "filter %u setup failed due to full SMT\n", idx); - clear_filter(sc, f); + clear_filter(f); sc->tids.ftids_in_use--; } else if (rc == FW_FILTER_WR_FLT_ADDED) { f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; f->pending = 0; /* asynchronous setup completed */ f->valid = 1; } else { /* * Something went wrong. Issue a warning about the * problem and clear everything out. */ device_printf(sc->dev, "filter %u setup failed with error %u\n", idx, rc); - clear_filter(sc, f); + clear_filter(f); sc->tids.ftids_in_use--; } } } int t4_os_find_pci_capability(struct adapter *sc, int cap) { int i; return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); } int t4_os_pci_save_state(struct adapter *sc) { device_t dev; struct pci_devinfo *dinfo; dev = sc->dev; dinfo = device_get_ivars(dev); pci_cfg_save(dev, dinfo, 0); return (0); } int t4_os_pci_restore_state(struct adapter *sc) { device_t dev; struct pci_devinfo *dinfo; dev = sc->dev; dinfo = device_get_ivars(dev); pci_cfg_restore(dev, dinfo); return (0); } void t4_os_portmod_changed(const struct adapter *sc, int idx) { struct port_info *pi = sc->port[idx]; static const char *mod_str[] = { NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" }; if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) if_printf(pi->ifp, "transceiver unplugged.\n"); else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) if_printf(pi->ifp, "unknown transceiver inserted.\n"); else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) if_printf(pi->ifp, "unsupported transceiver inserted.\n"); else if (pi->mod_type > 0 && pi->mod_type < ARRAY_SIZE(mod_str)) { if_printf(pi->ifp, "%s transceiver inserted.\n", mod_str[pi->mod_type]); } else { if_printf(pi->ifp, "transceiver (type %d) inserted.\n", pi->mod_type); } } void t4_os_link_changed(struct adapter *sc, int idx, int link_stat) { struct port_info *pi = sc->port[idx]; struct ifnet *ifp = pi->ifp; if (link_stat) { ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed); if_link_state_change(ifp, LINK_STATE_UP); } else if_link_state_change(ifp, LINK_STATE_DOWN); } static int t4_open(struct cdev *dev, int flags, int type, struct thread *td) { return (0); } static int t4_close(struct cdev *dev, int flags, int type, struct thread *td) { return (0); } static int t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, struct thread *td) { int rc; struct adapter *sc = dev->si_drv1; rc = priv_check(td, PRIV_DRIVER); if (rc != 0) return (rc); switch (cmd) { case CHELSIO_T4_GETREG: { struct t4_reg *edata = (struct t4_reg *)data; if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) return (EFAULT); if (edata->size == 4) edata->val = t4_read_reg(sc, edata->addr); else if (edata->size == 8) edata->val = t4_read_reg64(sc, edata->addr); else return (EINVAL); break; } case CHELSIO_T4_SETREG: { struct t4_reg *edata = (struct t4_reg *)data; if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) return (EFAULT); if (edata->size == 4) { if (edata->val & 0xffffffff00000000) return (EINVAL); t4_write_reg(sc, edata->addr, (uint32_t) edata->val); } else if (edata->size == 8) t4_write_reg64(sc, edata->addr, edata->val); else return (EINVAL); break; } case CHELSIO_T4_REGDUMP: { struct t4_regdump *regs = (struct t4_regdump *)data; int reglen = T4_REGDUMP_SIZE; uint8_t *buf; if (regs->len < reglen) { regs->len = reglen; /* hint to the caller */ return (ENOBUFS); } regs->len = reglen; buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); t4_get_regs(sc, regs, buf); rc = copyout(buf, regs->data, reglen); free(buf, M_CXGBE); break; } case CHELSIO_T4_GET_FILTER_MODE: rc = get_filter_mode(sc, (uint32_t *)data); break; case CHELSIO_T4_SET_FILTER_MODE: rc = set_filter_mode(sc, *(uint32_t *)data); break; case CHELSIO_T4_GET_FILTER: ADAPTER_LOCK(sc); rc = get_filter(sc, (struct t4_filter *)data); ADAPTER_UNLOCK(sc); break; case CHELSIO_T4_SET_FILTER: ADAPTER_LOCK(sc); rc = set_filter(sc, (struct t4_filter *)data); ADAPTER_UNLOCK(sc); break; case CHELSIO_T4_DEL_FILTER: ADAPTER_LOCK(sc); rc = del_filter(sc, (struct t4_filter *)data); ADAPTER_UNLOCK(sc); break; default: rc = EINVAL; } return (rc); } static int t4_mod_event(module_t mod, int cmd, void *arg) { if (cmd == MOD_LOAD) t4_sge_modload(); return (0); } static devclass_t t4_devclass; static devclass_t cxgbe_devclass; DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, t4_mod_event, 0); MODULE_VERSION(t4nex, 1); DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); MODULE_VERSION(cxgbe, 1); Index: stable/8/sys/dev/cxgbe/t4_sge.c =================================================================== --- stable/8/sys/dev/cxgbe/t4_sge.c (revision 222793) +++ stable/8/sys/dev/cxgbe/t4_sge.c (revision 222794) @@ -1,2745 +1,2833 @@ /*- * Copyright (c) 2011 Chelsio Communications, Inc. * All rights reserved. * Written by: Navdeep Parhar * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_inet.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "common/common.h" #include "common/t4_regs.h" #include "common/t4_regs_values.h" #include "common/t4_msg.h" #include "common/t4fw_interface.h" struct fl_buf_info { int size; int type; uma_zone_t zone; }; /* Filled up by t4_sge_modload */ static struct fl_buf_info fl_buf_info[FL_BUF_SIZES]; #define FL_BUF_SIZE(x) (fl_buf_info[x].size) #define FL_BUF_TYPE(x) (fl_buf_info[x].type) #define FL_BUF_ZONE(x) (fl_buf_info[x].zone) enum { FL_PKTSHIFT = 2 }; #define FL_ALIGN min(CACHE_LINE_SIZE, 32) #if CACHE_LINE_SIZE > 64 #define SPG_LEN 128 #else #define SPG_LEN 64 #endif /* Used to track coalesced tx work request */ struct txpkts { uint64_t *flitp; /* ptr to flit where next pkt should start */ uint8_t npkt; /* # of packets in this work request */ uint8_t nflits; /* # of flits used by this work request */ uint16_t plen; /* total payload (sum of all packets) */ }; /* A packet's SGL. This + m_pkthdr has all info needed for tx */ struct sgl { int nsegs; /* # of segments in the SGL, 0 means imm. tx */ int nflits; /* # of flits needed for the SGL */ bus_dma_segment_t seg[TX_SGL_SEGS]; }; +static void t4_evt_rx(void *); +static void t4_eth_rx(void *); static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int, int, iq_intr_handler_t *, char *); static inline void init_fl(struct sge_fl *, int, char *); static inline void init_eq(struct sge_eq *, int, char *); static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, bus_addr_t *, void **); static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, void *); static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *, int, int); static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *); -static int alloc_iq(struct sge_iq *, int); -static int free_iq(struct sge_iq *); +static int alloc_intrq(struct adapter *, int, int, int); +static int free_intrq(struct sge_iq *); +static int alloc_fwq(struct adapter *, int); +static int free_fwq(struct sge_iq *); static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int); static int free_rxq(struct port_info *, struct sge_rxq *); static int alloc_ctrlq(struct adapter *, struct sge_ctrlq *, int); static int free_ctrlq(struct adapter *, struct sge_ctrlq *); static int alloc_txq(struct port_info *, struct sge_txq *, int); static int free_txq(struct port_info *, struct sge_txq *); static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int); static inline bool is_new_response(const struct sge_iq *, struct rsp_ctrl **); static inline void iq_next(struct sge_iq *); static inline void ring_fl_db(struct adapter *, struct sge_fl *); static void refill_fl(struct adapter *, struct sge_fl *, int, int); static int alloc_fl_sdesc(struct sge_fl *); static void free_fl_sdesc(struct sge_fl *); static int alloc_tx_maps(struct sge_txq *); static void free_tx_maps(struct sge_txq *); static void set_fl_tag_idx(struct sge_fl *, int); static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int); static int free_pkt_sgl(struct sge_txq *, struct sgl *); static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *, struct sgl *); static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *, struct mbuf *, struct sgl *); static void write_txpkts_wr(struct sge_txq *, struct txpkts *); static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *, struct txpkts *, struct mbuf *, struct sgl *); static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *); static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int); static inline void ring_eq_db(struct adapter *, struct sge_eq *); static inline int reclaimable(struct sge_eq *); static int reclaim_tx_descs(struct sge_txq *, int, int); static void write_eqflush_wr(struct sge_eq *); static __be64 get_flit(bus_dma_segment_t *, int, int); static int handle_sge_egr_update(struct adapter *, const struct cpl_sge_egr_update *); +static void handle_cpl(struct adapter *, struct sge_iq *); static int ctrl_tx(struct adapter *, struct sge_ctrlq *, struct mbuf *); +static int sysctl_uint16(SYSCTL_HANDLER_ARGS); extern void filter_rpl(struct adapter *, const struct cpl_set_tcb_rpl *); /* * Called on MOD_LOAD and fills up fl_buf_info[]. */ void t4_sge_modload(void) { int i; int bufsize[FL_BUF_SIZES] = { MCLBYTES, #if MJUMPAGESIZE != MCLBYTES MJUMPAGESIZE, #endif MJUM9BYTES, MJUM16BYTES }; for (i = 0; i < FL_BUF_SIZES; i++) { FL_BUF_SIZE(i) = bufsize[i]; FL_BUF_TYPE(i) = m_gettype(bufsize[i]); FL_BUF_ZONE(i) = m_getzone(bufsize[i]); } } /** * t4_sge_init - initialize SGE * @sc: the adapter * * Performs SGE initialization needed every time after a chip reset. * We do not initialize any of the queues here, instead the driver * top-level must request them individually. */ void t4_sge_init(struct adapter *sc) { struct sge *s = &sc->sge; int i; t4_set_reg_field(sc, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT) | V_INGPADBOUNDARY(M_INGPADBOUNDARY) | F_EGRSTATUSPAGESIZE, V_INGPADBOUNDARY(ilog2(FL_ALIGN) - 5) | V_PKTSHIFT(FL_PKTSHIFT) | F_RXPKTCPLMODE | V_EGRSTATUSPAGESIZE(SPG_LEN == 128)); t4_set_reg_field(sc, A_SGE_HOST_PAGE_SIZE, V_HOSTPAGESIZEPF0(M_HOSTPAGESIZEPF0), V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10)); for (i = 0; i < FL_BUF_SIZES; i++) { t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i), FL_BUF_SIZE(i)); } + i = t4_read_reg(sc, A_SGE_CONM_CTRL); + s->fl_starve_threshold = G_EGRTHRESHOLD(i) * 2 + 1; + t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, V_THRESHOLD_0(s->counter_val[0]) | V_THRESHOLD_1(s->counter_val[1]) | V_THRESHOLD_2(s->counter_val[2]) | V_THRESHOLD_3(s->counter_val[3])); t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, V_TIMERVALUE0(us_to_core_ticks(sc, s->timer_val[0])) | V_TIMERVALUE1(us_to_core_ticks(sc, s->timer_val[1]))); t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, V_TIMERVALUE2(us_to_core_ticks(sc, s->timer_val[2])) | V_TIMERVALUE3(us_to_core_ticks(sc, s->timer_val[3]))); t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, V_TIMERVALUE4(us_to_core_ticks(sc, s->timer_val[4])) | V_TIMERVALUE5(us_to_core_ticks(sc, s->timer_val[5]))); } int t4_create_dma_tag(struct adapter *sc) { int rc; rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmat); if (rc != 0) { device_printf(sc->dev, "failed to create main DMA tag: %d\n", rc); } return (rc); } int t4_destroy_dma_tag(struct adapter *sc) { if (sc->dmat) bus_dma_tag_destroy(sc->dmat); return (0); } /* * Allocate and initialize the firmware event queue, control queues, and the - * forwarded interrupt queues (if any). The adapter owns all these queues as - * they are not associated with any particular port. + * interrupt queues. The adapter owns all of these queues. * * Returns errno on failure. Resources allocated up to that point may still be * allocated. Caller is responsible for cleanup in case this function fails. */ int t4_setup_adapter_queues(struct adapter *sc) { - int i, rc; - struct sge_iq *iq, *fwq; + int i, j, rc, intr_idx, qsize; + struct sge_iq *iq; struct sge_ctrlq *ctrlq; iq_intr_handler_t *handler; char name[16]; ADAPTER_LOCK_ASSERT_NOTOWNED(sc); if (sysctl_ctx_init(&sc->ctx) == 0) { struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev); struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); + sc->oid_fwq = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, + "fwq", CTLFLAG_RD, NULL, "firmware event queue"); sc->oid_ctrlq = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD, NULL, "ctrl queues"); + sc->oid_intrq = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, + "intrq", CTLFLAG_RD, NULL, "interrupt queues"); } - fwq = &sc->sge.fwq; - if (sc->flags & INTR_FWD) { - iq = &sc->sge.fiq[0]; - - /* - * Forwarded interrupt queues - allocate 1 if there's only 1 - * vector available, one less than the number of vectors - * otherwise (the first vector is reserved for the error - * interrupt in that case). - */ - i = sc->intr_count > 1 ? 1 : 0; - for (; i < sc->intr_count; i++, iq++) { - - snprintf(name, sizeof(name), "%s fiq%d", + /* + * Interrupt queues + */ + intr_idx = sc->intr_count - NINTRQ(sc); + if (sc->flags & INTR_SHARED) { + qsize = max((sc->sge.nrxq + 1) * 2, INTR_IQ_QSIZE); + for (i = 0; i < NINTRQ(sc); i++, intr_idx++) { + snprintf(name, sizeof(name), "%s intrq%d", device_get_nameunit(sc->dev), i); - init_iq(iq, sc, 0, 0, (sc->sge.nrxq + 1) * 2, 16, NULL, - name); - rc = alloc_iq(iq, i); + iq = &sc->sge.intrq[i]; + init_iq(iq, sc, 0, 0, qsize, INTR_IQ_ESIZE, NULL, name); + rc = alloc_intrq(sc, i % sc->params.nports, i, + intr_idx); + if (rc != 0) { device_printf(sc->dev, - "failed to create fwd intr queue %d: %d\n", - i, rc); + "failed to create %s: %d\n", name, rc); return (rc); } } - - handler = t4_evt_rx; - i = 0; /* forward fwq's interrupt to the first fiq */ } else { - handler = NULL; - i = 1; /* fwq should use vector 1 (0 is used by error) */ + int qidx = 0; + struct port_info *pi; + + for (i = 0; i < sc->params.nports; i++) { + pi = sc->port[i]; + qsize = max((pi->nrxq + 1) * 2, INTR_IQ_QSIZE); + for (j = 0; j < pi->nrxq; j++, qidx++, intr_idx++) { + snprintf(name, sizeof(name), "%s intrq%d", + device_get_nameunit(pi->dev), j); + + iq = &sc->sge.intrq[qidx]; + init_iq(iq, sc, 0, 0, qsize, INTR_IQ_ESIZE, + NULL, name); + rc = alloc_intrq(sc, i, qidx, intr_idx); + + if (rc != 0) { + device_printf(sc->dev, + "failed to create %s: %d\n", + name, rc); + return (rc); + } + } + } } + /* + * Firmware event queue + */ snprintf(name, sizeof(name), "%s fwq", device_get_nameunit(sc->dev)); - init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE, handler, name); - rc = alloc_iq(fwq, i); + if (sc->intr_count > T4_EXTRA_INTR) { + handler = NULL; + intr_idx = 1; + } else { + handler = t4_evt_rx; + intr_idx = 0; + } + + iq = &sc->sge.fwq; + init_iq(iq, sc, 0, 0, FW_IQ_QSIZE, FW_IQ_ESIZE, handler, name); + rc = alloc_fwq(sc, intr_idx); if (rc != 0) { device_printf(sc->dev, "failed to create firmware event queue: %d\n", rc); return (rc); } /* - * Control queues - one per hardware channel. + * Control queues - one per port. */ ctrlq = &sc->sge.ctrlq[0]; - for (i = 0; i < NCHAN; i++, ctrlq++) { + for (i = 0; i < sc->params.nports; i++, ctrlq++) { snprintf(name, sizeof(name), "%s ctrlq%d", device_get_nameunit(sc->dev), i); init_eq(&ctrlq->eq, CTRL_EQ_QSIZE, name); rc = alloc_ctrlq(sc, ctrlq, i); if (rc != 0) { device_printf(sc->dev, "failed to create control queue %d: %d\n", i, rc); return (rc); } } return (rc); } /* * Idempotent */ int t4_teardown_adapter_queues(struct adapter *sc) { int i; struct sge_iq *iq; ADAPTER_LOCK_ASSERT_NOTOWNED(sc); /* Do this before freeing the queues */ - if (sc->oid_ctrlq) { + if (sc->oid_fwq || sc->oid_ctrlq || sc->oid_intrq) { sysctl_ctx_free(&sc->ctx); + sc->oid_fwq = NULL; sc->oid_ctrlq = NULL; + sc->oid_intrq = NULL; } - for (i = 0; i < NCHAN; i++) + for (i = 0; i < sc->params.nports; i++) free_ctrlq(sc, &sc->sge.ctrlq[i]); iq = &sc->sge.fwq; - free_iq(iq); - if (sc->flags & INTR_FWD) { - for (i = 0; i < NFIQ(sc); i++) { - iq = &sc->sge.fiq[i]; - free_iq(iq); - } + free_fwq(iq); + + for (i = 0; i < NINTRQ(sc); i++) { + iq = &sc->sge.intrq[i]; + free_intrq(iq); } return (0); } int t4_setup_eth_queues(struct port_info *pi) { int rc = 0, i, intr_idx; struct sge_rxq *rxq; struct sge_txq *txq; char name[16]; struct adapter *sc = pi->adapter; if (sysctl_ctx_init(&pi->ctx) == 0) { struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev); struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid); pi->oid_rxq = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq", CTLFLAG_RD, NULL, "rx queues"); pi->oid_txq = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD, NULL, "tx queues"); } for_each_rxq(pi, i, rxq) { snprintf(name, sizeof(name), "%s rxq%d-iq", device_get_nameunit(pi->dev), i); init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, - pi->qsize_rxq, RX_IQ_ESIZE, - sc->flags & INTR_FWD ? t4_eth_rx : NULL, name); + pi->qsize_rxq, RX_IQ_ESIZE, t4_eth_rx, name); snprintf(name, sizeof(name), "%s rxq%d-fl", device_get_nameunit(pi->dev), i); init_fl(&rxq->fl, pi->qsize_rxq / 8, name); - if (sc->flags & INTR_FWD) - intr_idx = (pi->first_rxq + i) % NFIQ(sc); - else - intr_idx = pi->first_rxq + i + 2; + intr_idx = pi->first_rxq + i; + if (sc->flags & INTR_SHARED) + intr_idx %= NINTRQ(sc); rc = alloc_rxq(pi, rxq, intr_idx, i); if (rc != 0) goto done; - - intr_idx++; } for_each_txq(pi, i, txq) { snprintf(name, sizeof(name), "%s txq%d", device_get_nameunit(pi->dev), i); init_eq(&txq->eq, pi->qsize_txq, name); rc = alloc_txq(pi, txq, i); if (rc != 0) goto done; } done: if (rc) t4_teardown_eth_queues(pi); return (rc); } /* * Idempotent */ int t4_teardown_eth_queues(struct port_info *pi) { int i; struct sge_rxq *rxq; struct sge_txq *txq; /* Do this before freeing the queues */ if (pi->oid_txq || pi->oid_rxq) { sysctl_ctx_free(&pi->ctx); pi->oid_txq = pi->oid_rxq = NULL; } for_each_txq(pi, i, txq) { free_txq(pi, txq); } for_each_rxq(pi, i, rxq) { free_rxq(pi, rxq); } return (0); } -/* Deals with errors and forwarded interrupts */ +/* Deals with errors and the first (and only) interrupt queue */ void t4_intr_all(void *arg) { struct adapter *sc = arg; t4_intr_err(arg); - t4_intr_fwd(&sc->sge.fiq[0]); + t4_intr(&sc->sge.intrq[0]); } -/* Deals with forwarded interrupts on the given ingress queue */ +/* Deals with interrupts, and a few CPLs, on the given interrupt queue */ void -t4_intr_fwd(void *arg) +t4_intr(void *arg) { struct sge_iq *iq = arg, *q; struct adapter *sc = iq->adapter; struct rsp_ctrl *ctrl; + const struct rss_header *rss; int ndesc_pending = 0, ndesc_total = 0; - int qid; + int qid, rsp_type; if (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY)) return; while (is_new_response(iq, &ctrl)) { rmb(); - /* Only interrupt muxing expected on this queue */ - KASSERT(G_RSPD_TYPE(ctrl->u.type_gen) == X_RSPD_TYPE_INTR, - ("unexpected event on forwarded interrupt queue: %x", - G_RSPD_TYPE(ctrl->u.type_gen))); + rss = (const void *)iq->cdesc; + rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); + if (__predict_false(rsp_type == X_RSPD_TYPE_CPL)) { + handle_cpl(sc, iq); + goto nextdesc; + } + qid = ntohl(ctrl->pldbuflen_qid) - sc->sge.iq_start; q = sc->sge.iqmap[qid]; - q->handler(q); + if (atomic_cmpset_32(&q->state, IQS_IDLE, IQS_BUSY)) { + q->handler(q); + atomic_cmpset_32(&q->state, IQS_BUSY, IQS_IDLE); + } - ndesc_total++; +nextdesc: ndesc_total++; if (++ndesc_pending >= iq->qsize / 4) { t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndesc_pending) | V_INGRESSQID(iq->cntxt_id) | V_SEINTARM( V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); ndesc_pending = 0; } iq_next(iq); } t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndesc_pending) | V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params)); atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE); } /* Deals with error interrupts */ void t4_intr_err(void *arg) { struct adapter *sc = arg; - if (sc->intr_type == INTR_INTX) - t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); - + t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0); t4_slow_intr_handler(sc); } /* Deals with the firmware event queue */ void t4_intr_evt(void *arg) { struct sge_iq *iq = arg; - if (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY)) - return; - - t4_evt_rx(arg); - - atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE); + if (atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY)) { + t4_evt_rx(arg); + atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE); + } } -void -t4_intr_data(void *arg) -{ - struct sge_iq *iq = arg; - - if (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY)) - return; - - t4_eth_rx(arg); - - atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE); -} - -void +static void t4_evt_rx(void *arg) { struct sge_iq *iq = arg; struct adapter *sc = iq->adapter; struct rsp_ctrl *ctrl; - const struct rss_header *rss; int ndesc_pending = 0, ndesc_total = 0; KASSERT(iq == &sc->sge.fwq, ("%s: unexpected ingress queue", __func__)); while (is_new_response(iq, &ctrl)) { + int rsp_type; rmb(); - rss = (const void *)iq->cdesc; + rsp_type = G_RSPD_TYPE(ctrl->u.type_gen); + if (__predict_false(rsp_type != X_RSPD_TYPE_CPL)) + panic("%s: unexpected rsp_type %d", __func__, rsp_type); - /* Should only get CPL on this queue */ - KASSERT(G_RSPD_TYPE(ctrl->u.type_gen) == X_RSPD_TYPE_CPL, - ("%s: unexpected type %d", __func__, - G_RSPD_TYPE(ctrl->u.type_gen))); + handle_cpl(sc, iq); - switch (rss->opcode) { - case CPL_FW4_MSG: - case CPL_FW6_MSG: { - const struct cpl_fw6_msg *cpl; - - cpl = (const void *)(rss + 1); - if (cpl->type == FW6_TYPE_CMD_RPL) - t4_handle_fw_rpl(sc, cpl->data); - - break; - } - case CPL_SGE_EGR_UPDATE: - handle_sge_egr_update(sc, (const void *)(rss + 1)); - break; - case CPL_SET_TCB_RPL: - filter_rpl(sc, (const void *) (rss + 1)); - break; - default: - device_printf(sc->dev, - "can't handle CPL opcode %d.", rss->opcode); - } - ndesc_total++; if (++ndesc_pending >= iq->qsize / 4) { t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndesc_pending) | V_INGRESSQID(iq->cntxt_id) | V_SEINTARM( V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); ndesc_pending = 0; } + iq_next(iq); } t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndesc_pending) | V_INGRESSQID(iq->cntxt_id) | V_SEINTARM(iq->intr_params)); } #ifdef T4_PKT_TIMESTAMP #define RX_COPY_THRESHOLD (MINCLSIZE - 8) #else #define RX_COPY_THRESHOLD MINCLSIZE #endif -void +static void t4_eth_rx(void *arg) { struct sge_rxq *rxq = arg; struct sge_iq *iq = arg; struct adapter *sc = iq->adapter; struct rsp_ctrl *ctrl; struct ifnet *ifp = rxq->ifp; struct sge_fl *fl = &rxq->fl; struct fl_sdesc *sd = &fl->sdesc[fl->cidx], *sd_next; const struct rss_header *rss; const struct cpl_rx_pkt *cpl; uint32_t len; int ndescs = 0, i; struct mbuf *m0, *m; #ifdef INET struct lro_ctrl *lro = &rxq->lro; struct lro_entry *l; #endif prefetch(sd->m); prefetch(sd->cl); iq->intr_next = iq->intr_params; while (is_new_response(iq, &ctrl)) { rmb(); rss = (const void *)iq->cdesc; i = G_RSPD_TYPE(ctrl->u.type_gen); - if (__predict_false(i == X_RSPD_TYPE_CPL)) { - - /* Can't be anything except an egress update */ - KASSERT(rss->opcode == CPL_SGE_EGR_UPDATE, - ("%s: unexpected CPL %x", __func__, rss->opcode)); - - handle_sge_egr_update(sc, (const void *)(rss + 1)); - goto nextdesc; - } KASSERT(i == X_RSPD_TYPE_FLBUF && rss->opcode == CPL_RX_PKT, - ("%s: unexpected CPL %x rsp %d", __func__, rss->opcode, i)); + ("%s: unexpected type %d CPL opcode 0x%x", + __func__, i, rss->opcode)); sd_next = sd + 1; if (__predict_false(fl->cidx + 1 == fl->cap)) sd_next = fl->sdesc; prefetch(sd_next->m); prefetch(sd_next->cl); cpl = (const void *)(rss + 1); m0 = sd->m; sd->m = NULL; /* consumed */ len = be32toh(ctrl->pldbuflen_qid); if (__predict_false((len & F_RSPD_NEWBUF) == 0)) panic("%s: cannot handle packed frames", __func__); len = G_RSPD_LEN(len); bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD); m_init(m0, NULL, 0, M_NOWAIT, MT_DATA, M_PKTHDR); #ifdef T4_PKT_TIMESTAMP *mtod(m0, uint64_t *) = be64toh(ctrl->u.last_flit & 0xfffffffffffffff); m0->m_data += 8; /* * 60 bit timestamp value is *(uint64_t *)m0->m_pktdat. Note * that it is in the leading free-space (see M_LEADINGSPACE) in * the mbuf. The kernel can clobber it during a pullup, * m_copymdata, etc. You need to make sure that the mbuf * reaches you unmolested if you care about the timestamp. */ #endif if (len < RX_COPY_THRESHOLD) { /* copy data to mbuf, buffer will be recycled */ bcopy(sd->cl, mtod(m0, caddr_t), len); m0->m_len = len; } else { bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); m_cljset(m0, sd->cl, FL_BUF_TYPE(sd->tag_idx)); sd->cl = NULL; /* consumed */ m0->m_len = min(len, FL_BUF_SIZE(sd->tag_idx)); } len -= FL_PKTSHIFT; m0->m_len -= FL_PKTSHIFT; m0->m_data += FL_PKTSHIFT; m0->m_pkthdr.len = len; m0->m_pkthdr.rcvif = ifp; m0->m_flags |= M_FLOWID; m0->m_pkthdr.flowid = rss->hash_val; if (cpl->csum_calc && !cpl->err_vec && ifp->if_capenable & IFCAP_RXCSUM) { m0->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED | CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR); if (cpl->ip_frag) m0->m_pkthdr.csum_data = be16toh(cpl->csum); else m0->m_pkthdr.csum_data = 0xffff; rxq->rxcsum++; } if (cpl->vlan_ex) { m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan); m0->m_flags |= M_VLANTAG; rxq->vlan_extraction++; } i = 1; /* # of fl sdesc used */ sd = sd_next; if (__predict_false(++fl->cidx == fl->cap)) fl->cidx = 0; len -= m0->m_len; m = m0; while (len) { i++; sd_next = sd + 1; if (__predict_false(fl->cidx + 1 == fl->cap)) sd_next = fl->sdesc; prefetch(sd_next->m); prefetch(sd_next->cl); m->m_next = sd->m; sd->m = NULL; /* consumed */ m = m->m_next; bus_dmamap_sync(fl->tag[sd->tag_idx], sd->map, BUS_DMASYNC_POSTREAD); m_init(m, NULL, 0, M_NOWAIT, MT_DATA, 0); if (len <= MLEN) { bcopy(sd->cl, mtod(m, caddr_t), len); m->m_len = len; } else { bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); m_cljset(m, sd->cl, FL_BUF_TYPE(sd->tag_idx)); sd->cl = NULL; /* consumed */ m->m_len = min(len, FL_BUF_SIZE(sd->tag_idx)); } i++; sd = sd_next; if (__predict_false(++fl->cidx == fl->cap)) fl->cidx = 0; len -= m->m_len; } #ifdef INET if (cpl->l2info & htobe32(F_RXF_LRO) && rxq->flags & RXQ_LRO_ENABLED && tcp_lro_rx(lro, m0, 0) == 0) { /* queued for LRO */ } else #endif ifp->if_input(ifp, m0); FL_LOCK(fl); fl->needed += i; if (fl->needed >= 32) refill_fl(sc, fl, 64, 32); FL_UNLOCK(fl); -nextdesc: ndescs++; - iq_next(iq); - - if (ndescs > 32) { + if (++ndescs > 32) { t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); ndescs = 0; } + + iq_next(iq); } #ifdef INET while (!SLIST_EMPTY(&lro->lro_active)) { l = SLIST_FIRST(&lro->lro_active); SLIST_REMOVE_HEAD(&lro->lro_active, next); tcp_lro_flush(lro, l); } #endif t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) | V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_next)); FL_LOCK(fl); if (fl->needed >= 32) refill_fl(sc, fl, 128, 8); FL_UNLOCK(fl); } int t4_mgmt_tx(struct adapter *sc, struct mbuf *m) { return ctrl_tx(sc, &sc->sge.ctrlq[0], m); } /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */ #define TXPKTS_PKT_HDR ((\ sizeof(struct ulp_txpkt) + \ sizeof(struct ulptx_idata) + \ sizeof(struct cpl_tx_pkt_core) \ ) / 8) /* Header of a coalesced tx WR, before SGL of first packet (in flits) */ #define TXPKTS_WR_HDR (\ sizeof(struct fw_eth_tx_pkts_wr) / 8 + \ TXPKTS_PKT_HDR) /* Header of a tx WR, before SGL of first packet (in flits) */ #define TXPKT_WR_HDR ((\ sizeof(struct fw_eth_tx_pkt_wr) + \ sizeof(struct cpl_tx_pkt_core) \ ) / 8 ) /* Header of a tx LSO WR, before SGL of first packet (in flits) */ #define TXPKT_LSO_WR_HDR ((\ sizeof(struct fw_eth_tx_pkt_wr) + \ sizeof(struct cpl_tx_pkt_lso) + \ sizeof(struct cpl_tx_pkt_core) \ ) / 8 ) int t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m) { struct port_info *pi = (void *)ifp->if_softc; struct adapter *sc = pi->adapter; struct sge_eq *eq = &txq->eq; struct buf_ring *br = txq->br; struct mbuf *next; int rc, coalescing, can_reclaim; struct txpkts txpkts; struct sgl sgl; TXQ_LOCK_ASSERT_OWNED(txq); KASSERT(m, ("%s: called with nothing to do.", __func__)); prefetch(&eq->desc[eq->pidx]); prefetch(&txq->sdesc[eq->pidx]); txpkts.npkt = 0;/* indicates there's nothing in txpkts */ coalescing = 0; if (eq->avail < 8) reclaim_tx_descs(txq, 0, 8); for (; m; m = next ? next : drbr_dequeue(ifp, br)) { if (eq->avail < 8) break; next = m->m_nextpkt; m->m_nextpkt = NULL; if (next || buf_ring_peek(br)) coalescing = 1; rc = get_pkt_sgl(txq, &m, &sgl, coalescing); if (rc != 0) { if (rc == ENOMEM) { /* Short of resources, suspend tx */ m->m_nextpkt = next; break; } /* * Unrecoverable error for this packet, throw it away * and move on to the next. get_pkt_sgl may already * have freed m (it will be NULL in that case and the * m_freem here is still safe). */ m_freem(m); continue; } if (coalescing && add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) { /* Successfully absorbed into txpkts */ write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl); goto doorbell; } /* * We weren't coalescing to begin with, or current frame could * not be coalesced (add_to_txpkts flushes txpkts if a frame * given to it can't be coalesced). Either way there should be * nothing in txpkts. */ KASSERT(txpkts.npkt == 0, ("%s: txpkts not empty: %d", __func__, txpkts.npkt)); /* We're sending out individual packets now */ coalescing = 0; if (eq->avail < 8) reclaim_tx_descs(txq, 0, 8); rc = write_txpkt_wr(pi, txq, m, &sgl); if (rc != 0) { /* Short of hardware descriptors, suspend tx */ /* * This is an unlikely but expensive failure. We've * done all the hard work (DMA mappings etc.) and now we * can't send out the packet. What's worse, we have to * spend even more time freeing up everything in sgl. */ txq->no_desc++; free_pkt_sgl(txq, &sgl); m->m_nextpkt = next; break; } ETHER_BPF_MTAP(ifp, m); if (sgl.nsegs == 0) m_freem(m); doorbell: /* Fewer and fewer doorbells as the queue fills up */ if (eq->pending >= (1 << (fls(eq->qsize - eq->avail) / 2))) ring_eq_db(sc, eq); can_reclaim = reclaimable(eq); if (can_reclaim >= 32) reclaim_tx_descs(txq, can_reclaim, 32); } if (txpkts.npkt > 0) write_txpkts_wr(txq, &txpkts); /* * m not NULL means there was an error but we haven't thrown it away. * This can happen when we're short of tx descriptors (no_desc) or maybe * even DMA maps (no_dmamap). Either way, a credit flush and reclaim * will get things going again. * * If eq->avail is already 0 we know a credit flush was requested in the * WR that reduced it to 0 so we don't need another flush (we don't have * any descriptor for a flush WR anyway, duh). */ if (m && eq->avail > 0 && !(eq->flags & EQ_CRFLUSHED)) { struct tx_sdesc *txsd = &txq->sdesc[eq->pidx]; txsd->desc_used = 1; txsd->credits = 0; write_eqflush_wr(eq); } txq->m = m; if (eq->pending) ring_eq_db(sc, eq); can_reclaim = reclaimable(eq); if (can_reclaim >= 32) reclaim_tx_descs(txq, can_reclaim, 128); return (0); } void t4_update_fl_bufsize(struct ifnet *ifp) { struct port_info *pi = ifp->if_softc; struct sge_rxq *rxq; struct sge_fl *fl; int i; for_each_rxq(pi, i, rxq) { fl = &rxq->fl; FL_LOCK(fl); set_fl_tag_idx(fl, ifp->if_mtu); FL_UNLOCK(fl); } } /* * A non-NULL handler indicates this iq will not receive direct interrupts, the - * handler will be invoked by a forwarded interrupt queue. + * handler will be invoked by an interrupt queue. */ static inline void init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx, int qsize, int esize, iq_intr_handler_t *handler, char *name) { KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS, ("%s: bad tmr_idx %d", __func__, tmr_idx)); KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */ ("%s: bad pktc_idx %d", __func__, pktc_idx)); iq->flags = 0; iq->adapter = sc; iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx) | V_QINTR_CNT_EN(pktc_idx >= 0); iq->intr_pktc_idx = pktc_idx; iq->qsize = roundup(qsize, 16); /* See FW_IQ_CMD/iqsize */ iq->esize = max(esize, 16); /* See FW_IQ_CMD/iqesize */ iq->handler = handler; strlcpy(iq->lockname, name, sizeof(iq->lockname)); } static inline void init_fl(struct sge_fl *fl, int qsize, char *name) { fl->qsize = qsize; strlcpy(fl->lockname, name, sizeof(fl->lockname)); } static inline void init_eq(struct sge_eq *eq, int qsize, char *name) { eq->qsize = qsize; strlcpy(eq->lockname, name, sizeof(eq->lockname)); } static int alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag, bus_dmamap_t *map, bus_addr_t *pa, void **va) { int rc; rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag); if (rc != 0) { device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc); goto done; } rc = bus_dmamem_alloc(*tag, va, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map); if (rc != 0) { device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc); goto done; } rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0); if (rc != 0) { device_printf(sc->dev, "cannot load DMA map: %d\n", rc); goto done; } done: if (rc) free_ring(sc, *tag, *map, *pa, *va); return (rc); } static int free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map, bus_addr_t pa, void *va) { if (pa) bus_dmamap_unload(tag, map); if (va) bus_dmamem_free(tag, va, map); if (tag) bus_dma_tag_destroy(tag); return (0); } /* * Allocates the ring for an ingress queue and an optional freelist. If the * freelist is specified it will be allocated and then associated with the * ingress queue. * * Returns errno on failure. Resources allocated up to that point may still be * allocated. Caller is responsible for cleanup in case this function fails. * * If the ingress queue will take interrupts directly (iq->handler == NULL) then * the intr_idx specifies the vector, starting from 0. Otherwise it specifies - * the index of the queue to which its interrupts will be forwarded. + * the index of the interrupt queue to which its interrupts will be forwarded. */ static int alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, int intr_idx, int cong) { int rc, i, cntxt_id; size_t len; struct fw_iq_cmd c; struct adapter *sc = iq->adapter; __be32 v = 0; - /* The adapter queues are nominally allocated in port[0]'s name */ - if (pi == NULL) - pi = sc->port[0]; - len = iq->qsize * iq->esize; rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba, (void **)&iq->desc); if (rc != 0) return (rc); bzero(&c, sizeof(c)); c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | V_FW_IQ_CMD_VFN(0)); c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | FW_LEN16(c)); /* Special handling for firmware event queue */ if (iq == &sc->sge.fwq) v |= F_FW_IQ_CMD_IQASYNCH; if (iq->handler) { - KASSERT(intr_idx < NFIQ(sc), + KASSERT(intr_idx < NINTRQ(sc), ("%s: invalid indirect intr_idx %d", __func__, intr_idx)); v |= F_FW_IQ_CMD_IQANDST; - v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fiq[intr_idx].abs_id); + v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.intrq[intr_idx].abs_id); } else { KASSERT(intr_idx < sc->intr_count, ("%s: invalid direct intr_idx %d", __func__, intr_idx)); v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx); } c.type_to_iqandstindex = htobe32(v | V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | V_FW_IQ_CMD_VIID(pi->viid) | V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) | F_FW_IQ_CMD_IQGTSMODE | V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) | V_FW_IQ_CMD_IQESIZE(ilog2(iq->esize) - 4)); c.iqsize = htobe16(iq->qsize); c.iqaddr = htobe64(iq->ba); if (cong >= 0) c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN); if (fl) { mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF); for (i = 0; i < FL_BUF_SIZES; i++) { /* * A freelist buffer must be 16 byte aligned as the SGE * uses the low 4 bits of the bus addr to figure out the * buffer size. */ rc = bus_dma_tag_create(sc->dmat, 16, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, FL_BUF_SIZE(i), 1, FL_BUF_SIZE(i), BUS_DMA_ALLOCNOW, NULL, NULL, &fl->tag[i]); if (rc != 0) { device_printf(sc->dev, "failed to create fl DMA tag[%d]: %d\n", i, rc); return (rc); } } len = fl->qsize * RX_FL_ESIZE; rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map, &fl->ba, (void **)&fl->desc); if (rc) return (rc); /* Allocate space for one software descriptor per buffer. */ fl->cap = (fl->qsize - SPG_LEN / RX_FL_ESIZE) * 8; FL_LOCK(fl); set_fl_tag_idx(fl, pi->ifp->if_mtu); rc = alloc_fl_sdesc(fl); FL_UNLOCK(fl); if (rc != 0) { device_printf(sc->dev, "failed to setup fl software descriptors: %d\n", rc); return (rc); } fl->needed = fl->cap; c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | F_FW_IQ_CMD_FL0PADEN); if (cong >= 0) { c.iqns_to_fl0congen |= htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | F_FW_IQ_CMD_FL0CONGEN); } c.fl0dcaen_to_fl0cidxfthresh = htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) | V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); c.fl0size = htobe16(fl->qsize); c.fl0addr = htobe64(fl->ba); } rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); if (rc != 0) { device_printf(sc->dev, "failed to create ingress queue: %d\n", rc); return (rc); } iq->cdesc = iq->desc; iq->cidx = 0; iq->gen = 1; iq->intr_next = iq->intr_params; iq->cntxt_id = be16toh(c.iqid); iq->abs_id = be16toh(c.physiqid); iq->flags |= (IQ_ALLOCATED | IQ_STARTED); cntxt_id = iq->cntxt_id - sc->sge.iq_start; KASSERT(cntxt_id < sc->sge.niq, ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__, cntxt_id, sc->sge.niq - 1)); sc->sge.iqmap[cntxt_id] = iq; if (fl) { fl->cntxt_id = be16toh(c.fl0id); fl->pidx = fl->cidx = 0; cntxt_id = fl->cntxt_id - sc->sge.eq_start; KASSERT(cntxt_id < sc->sge.neq, ("%s: fl->cntxt_id (%d) more than the max (%d)", __func__, cntxt_id, sc->sge.neq - 1)); sc->sge.eqmap[cntxt_id] = (void *)fl; FL_LOCK(fl); - refill_fl(sc, fl, -1, 8); + /* Just enough to make sure it doesn't starve right away. */ + refill_fl(sc, fl, roundup(sc->sge.fl_starve_threshold, 8), 8); FL_UNLOCK(fl); } /* Enable IQ interrupts */ atomic_store_rel_32(&iq->state, IQS_IDLE); t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | V_INGRESSQID(iq->cntxt_id)); return (0); } /* * This can be called with the iq/fl in any state - fully allocated and * functional, partially allocated, even all-zeroed out. */ static int free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl) { int i, rc; struct adapter *sc = iq->adapter; device_t dev; if (sc == NULL) return (0); /* nothing to do */ dev = pi ? pi->dev : sc->dev; if (iq->flags & IQ_STARTED) { rc = -t4_iq_start_stop(sc, sc->mbox, 0, sc->pf, 0, iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); if (rc != 0) { device_printf(dev, "failed to stop queue %p: %d\n", iq, rc); return (rc); } iq->flags &= ~IQ_STARTED; /* Synchronize with the interrupt handler */ while (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_DISABLED)) pause("iqfree", hz / 1000); } if (iq->flags & IQ_ALLOCATED) { rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff); if (rc != 0) { device_printf(dev, "failed to free queue %p: %d\n", iq, rc); return (rc); } iq->flags &= ~IQ_ALLOCATED; } free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc); bzero(iq, sizeof(*iq)); if (fl) { free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc); if (fl->sdesc) { FL_LOCK(fl); free_fl_sdesc(fl); FL_UNLOCK(fl); } if (mtx_initialized(&fl->fl_lock)) mtx_destroy(&fl->fl_lock); for (i = 0; i < FL_BUF_SIZES; i++) { if (fl->tag[i]) bus_dma_tag_destroy(fl->tag[i]); } bzero(fl, sizeof(*fl)); } return (0); } static int -alloc_iq(struct sge_iq *iq, int intr_idx) +alloc_intrq(struct adapter *sc, int port_idx, int intrq_idx, int intr_idx) { - return alloc_iq_fl(NULL, iq, NULL, intr_idx, -1); + int rc; + struct sysctl_oid *oid; + struct sysctl_oid_list *children; + char name[16]; + struct sge_iq *intrq = &sc->sge.intrq[intrq_idx]; + + rc = alloc_iq_fl(sc->port[port_idx], intrq, NULL, intr_idx, -1); + if (rc != 0) + return (rc); + + children = SYSCTL_CHILDREN(sc->oid_intrq); + + snprintf(name, sizeof(name), "%d", intrq_idx); + oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, + NULL, "interrupt queue"); + children = SYSCTL_CHILDREN(oid); + + SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", + CTLTYPE_INT | CTLFLAG_RD, &intrq->cidx, 0, sysctl_uint16, "I", + "consumer index"); + + return (rc); } static int -free_iq(struct sge_iq *iq) +free_intrq(struct sge_iq *iq) { return free_iq_fl(NULL, iq, NULL); + } static int +alloc_fwq(struct adapter *sc, int intr_idx) +{ + int rc; + struct sysctl_oid_list *children; + struct sge_iq *fwq = &sc->sge.fwq; + + rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1); + if (rc != 0) + return (rc); + + children = SYSCTL_CHILDREN(sc->oid_fwq); + + SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx", + CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I", + "consumer index"); + + return (rc); +} + +static int +free_fwq(struct sge_iq *iq) +{ + return free_iq_fl(NULL, iq, NULL); +} + +static int alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx) { int rc; struct sysctl_oid *oid; struct sysctl_oid_list *children; char name[16]; rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, 1 << pi->tx_chan); if (rc != 0) return (rc); + FL_LOCK(&rxq->fl); + refill_fl(pi->adapter, &rxq->fl, rxq->fl.needed / 8, 8); + FL_UNLOCK(&rxq->fl); + #ifdef INET rc = tcp_lro_init(&rxq->lro); if (rc != 0) return (rc); rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */ if (pi->ifp->if_capenable & IFCAP_LRO) rxq->flags |= RXQ_LRO_ENABLED; #endif rxq->ifp = pi->ifp; children = SYSCTL_CHILDREN(pi->oid_rxq); snprintf(name, sizeof(name), "%d", idx); oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, "rx queue"); children = SYSCTL_CHILDREN(oid); + SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id", + CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I", + "absolute id of the queue"); #ifdef INET SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD, &rxq->lro.lro_queued, 0, NULL); SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD, &rxq->lro.lro_flushed, 0, NULL); #endif - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD, &rxq->rxcsum, "# of times hardware assisted with checksum"); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD, &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag"); return (rc); } static int free_rxq(struct port_info *pi, struct sge_rxq *rxq) { int rc; #ifdef INET if (rxq->lro.ifp) { tcp_lro_free(&rxq->lro); rxq->lro.ifp = NULL; } #endif rc = free_iq_fl(pi, &rxq->iq, &rxq->fl); if (rc == 0) bzero(rxq, sizeof(*rxq)); return (rc); } static int alloc_ctrlq(struct adapter *sc, struct sge_ctrlq *ctrlq, int idx) { int rc, cntxt_id; size_t len; struct fw_eq_ctrl_cmd c; struct sge_eq *eq = &ctrlq->eq; char name[16]; struct sysctl_oid *oid; struct sysctl_oid_list *children; mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); len = eq->qsize * CTRL_EQ_ESIZE; rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, (void **)&eq->desc); if (rc) return (rc); eq->cap = eq->qsize - SPG_LEN / CTRL_EQ_ESIZE; eq->spg = (void *)&eq->desc[eq->cap]; eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ - eq->iqid = sc->sge.fwq.cntxt_id; + if (sc->flags & INTR_SHARED) + eq->iqid = sc->sge.intrq[idx % NINTRQ(sc)].cntxt_id; + else + eq->iqid = sc->sge.intrq[sc->port[idx]->first_rxq].cntxt_id; bzero(&c, sizeof(c)); c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST | F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) | V_FW_EQ_CTRL_CMD_VFN(0)); c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC | F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c)); c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */ c.physeqid_pkd = htobe32(0); c.fetchszm_to_iqid = htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | - V_FW_EQ_CTRL_CMD_PCIECHN(idx) | F_FW_EQ_CTRL_CMD_FETCHRO | - V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); + V_FW_EQ_CTRL_CMD_PCIECHN(sc->port[idx]->tx_chan) | + F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid)); c.dcaen_to_eqsize = htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) | V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) | V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize)); c.eqaddr = htobe64(eq->ba); rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); if (rc != 0) { device_printf(sc->dev, "failed to create control queue %d: %d\n", idx, rc); return (rc); } eq->pidx = eq->cidx = 0; eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid)); eq->flags |= (EQ_ALLOCATED | EQ_STARTED); cntxt_id = eq->cntxt_id - sc->sge.eq_start; KASSERT(cntxt_id < sc->sge.neq, ("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, cntxt_id, sc->sge.neq - 1)); sc->sge.eqmap[cntxt_id] = eq; children = SYSCTL_CHILDREN(sc->oid_ctrlq); snprintf(name, sizeof(name), "%d", idx); oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, "ctrl queue"); children = SYSCTL_CHILDREN(oid); - SYSCTL_ADD_QUAD(&sc->ctx, children, OID_AUTO, "total_wrs", CTLFLAG_RD, - &ctrlq->total_wrs, "total # of work requests"); + SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "pidx", + CTLTYPE_INT | CTLFLAG_RD, &ctrlq->eq.pidx, 0, sysctl_uint16, "I", + "producer index"); SYSCTL_ADD_UINT(&sc->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, &ctrlq->no_desc, 0, "# of times ctrlq ran out of hardware descriptors"); - SYSCTL_ADD_UINT(&sc->ctx, children, OID_AUTO, "too_long", CTLFLAG_RD, - &ctrlq->too_long, 0, "# of oversized work requests"); return (rc); } static int free_ctrlq(struct adapter *sc, struct sge_ctrlq *ctrlq) { int rc; struct sge_eq *eq = &ctrlq->eq; if (eq->flags & (EQ_ALLOCATED | EQ_STARTED)) { rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); if (rc != 0) { device_printf(sc->dev, "failed to free ctrl queue %p: %d\n", eq, rc); return (rc); } eq->flags &= ~(EQ_ALLOCATED | EQ_STARTED); } free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); if (mtx_initialized(&eq->eq_lock)) mtx_destroy(&eq->eq_lock); bzero(ctrlq, sizeof(*ctrlq)); return (0); } static int alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx) { int rc, cntxt_id; size_t len; struct adapter *sc = pi->adapter; struct fw_eq_eth_cmd c; struct sge_eq *eq = &txq->eq; char name[16]; struct sysctl_oid *oid; struct sysctl_oid_list *children; + struct sge_iq *intrq; txq->ifp = pi->ifp; TASK_INIT(&txq->resume_tx, 0, cxgbe_txq_start, txq); mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF); len = eq->qsize * TX_EQ_ESIZE; rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba, (void **)&eq->desc); if (rc) return (rc); eq->cap = eq->qsize - SPG_LEN / TX_EQ_ESIZE; eq->spg = (void *)&eq->desc[eq->cap]; eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE, M_ZERO | M_WAITOK); txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock); - eq->iqid = sc->sge.rxq[pi->first_rxq].iq.cntxt_id; + intrq = &sc->sge.intrq[0]; + if (sc->flags & INTR_SHARED) + eq->iqid = intrq[(pi->first_txq + idx) % NINTRQ(sc)].cntxt_id; + else + eq->iqid = intrq[pi->first_rxq + (idx % pi->nrxq)].cntxt_id; + rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag); if (rc != 0) { device_printf(sc->dev, "failed to create tx DMA tag: %d\n", rc); return (rc); } rc = alloc_tx_maps(txq); if (rc != 0) { device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc); return (rc); } bzero(&c, sizeof(c)); c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | V_FW_EQ_ETH_CMD_VFN(0)); c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid)); c.fetchszm_to_iqid = htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) | V_FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | V_FW_EQ_ETH_CMD_IQID(eq->iqid)); c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) | V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize)); c.eqaddr = htobe64(eq->ba); rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); if (rc != 0) { device_printf(pi->dev, "failed to create egress queue: %d\n", rc); return (rc); } eq->pidx = eq->cidx = 0; eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); eq->flags |= (EQ_ALLOCATED | EQ_STARTED); cntxt_id = eq->cntxt_id - sc->sge.eq_start; KASSERT(cntxt_id < sc->sge.neq, ("%s: eq->cntxt_id (%d) more than the max (%d)", __func__, cntxt_id, sc->sge.neq - 1)); sc->sge.eqmap[cntxt_id] = eq; children = SYSCTL_CHILDREN(pi->oid_txq); snprintf(name, sizeof(name), "%d", idx); oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL, "tx queue"); children = SYSCTL_CHILDREN(oid); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD, &txq->txcsum, "# of times hardware assisted with checksum"); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD, &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag"); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD, &txq->tso_wrs, "# of IPv4 TSO work requests"); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD, &txq->imm_wrs, "# of work requests with immediate data"); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD, &txq->sgl_wrs, "# of work requests with direct SGL"); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD, &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)"); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD, &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)"); - SYSCTL_ADD_QUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, + SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD, &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests"); SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD, &txq->no_dmamap, 0, "# of times txq ran out of DMA maps"); SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD, &txq->no_desc, 0, "# of times txq ran out of hardware descriptors"); SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD, &txq->egr_update, 0, "egress update notifications from the SGE"); return (rc); } static int free_txq(struct port_info *pi, struct sge_txq *txq) { int rc; struct adapter *sc = pi->adapter; struct sge_eq *eq = &txq->eq; if (eq->flags & (EQ_ALLOCATED | EQ_STARTED)) { /* * Wait for the response to a credit flush if there's one * pending. Clearing the flag tells handle_sge_egr_update or * cxgbe_txq_start (depending on how far the response has made * it) that they should ignore the response and wake up free_txq * instead. * * The interface has been marked down by the time we get here * (both IFF_UP and IFF_DRV_RUNNING cleared). qflush has * emptied the tx buf_rings and we know nothing new is being * queued for tx so we don't have to worry about a new credit * flush request. */ TXQ_LOCK(txq); if (eq->flags & EQ_CRFLUSHED) { eq->flags &= ~EQ_CRFLUSHED; msleep(txq, &eq->eq_lock, 0, "crflush", 0); } TXQ_UNLOCK(txq); rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id); if (rc != 0) { device_printf(pi->dev, "failed to free egress queue %p: %d\n", eq, rc); return (rc); } eq->flags &= ~(EQ_ALLOCATED | EQ_STARTED); } free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc); free(txq->sdesc, M_CXGBE); if (txq->maps) free_tx_maps(txq); buf_ring_free(txq->br, M_CXGBE); if (txq->tx_tag) bus_dma_tag_destroy(txq->tx_tag); if (mtx_initialized(&eq->eq_lock)) mtx_destroy(&eq->eq_lock); bzero(txq, sizeof(*txq)); return (0); } static void oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) { bus_addr_t *ba = arg; KASSERT(nseg == 1, ("%s meant for single segment mappings only.", __func__)); *ba = error ? 0 : segs->ds_addr; } static inline bool is_new_response(const struct sge_iq *iq, struct rsp_ctrl **ctrl) { *ctrl = (void *)((uintptr_t)iq->cdesc + (iq->esize - sizeof(struct rsp_ctrl))); return (((*ctrl)->u.type_gen >> S_RSPD_GEN) == iq->gen); } static inline void iq_next(struct sge_iq *iq) { iq->cdesc = (void *) ((uintptr_t)iq->cdesc + iq->esize); if (__predict_false(++iq->cidx == iq->qsize - 1)) { iq->cidx = 0; iq->gen ^= 1; iq->cdesc = iq->desc; } } #define FL_HW_IDX(x) ((x) >> 3) static inline void ring_fl_db(struct adapter *sc, struct sge_fl *fl) { int ndesc = fl->pending / 8; if (FL_HW_IDX(fl->pidx) == FL_HW_IDX(fl->cidx)) ndesc--; /* hold back one credit */ if (ndesc <= 0) return; /* nothing to do */ wmb(); t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc)); fl->pending -= ndesc * 8; } /* * Fill up the freelist by upto nbufs and ring its doorbell if the number of * buffers ready to be handed to the hardware >= dbthresh. */ static void refill_fl(struct adapter *sc, struct sge_fl *fl, int nbufs, int dbthresh) { __be64 *d = &fl->desc[fl->pidx]; struct fl_sdesc *sd = &fl->sdesc[fl->pidx]; bus_dma_tag_t tag; bus_addr_t pa; caddr_t cl; int rc; FL_LOCK_ASSERT_OWNED(fl); if (nbufs < 0 || nbufs > fl->needed) nbufs = fl->needed; while (nbufs--) { if (sd->cl != NULL) { /* * This happens when a frame small enough to fit * entirely in an mbuf was received in cl last time. * We'd held on to cl and can reuse it now. Note that * we reuse a cluster of the old size if fl->tag_idx is * no longer the same as sd->tag_idx. */ KASSERT(*d == sd->ba_tag, ("%s: recyling problem at pidx %d", __func__, fl->pidx)); d++; goto recycled; } if (fl->tag_idx != sd->tag_idx) { bus_dmamap_t map; bus_dma_tag_t newtag = fl->tag[fl->tag_idx]; bus_dma_tag_t oldtag = fl->tag[sd->tag_idx]; /* * An MTU change can get us here. Discard the old map * which was created with the old tag, but only if * we're able to get a new one. */ rc = bus_dmamap_create(newtag, 0, &map); if (rc == 0) { bus_dmamap_destroy(oldtag, sd->map); sd->map = map; sd->tag_idx = fl->tag_idx; } } tag = fl->tag[sd->tag_idx]; cl = m_cljget(NULL, M_NOWAIT, FL_BUF_SIZE(sd->tag_idx)); if (cl == NULL) break; rc = bus_dmamap_load(tag, sd->map, cl, FL_BUF_SIZE(sd->tag_idx), oneseg_dma_callback, &pa, 0); if (rc != 0 || pa == 0) { fl->dmamap_failed++; uma_zfree(FL_BUF_ZONE(sd->tag_idx), cl); break; } sd->cl = cl; *d++ = htobe64(pa | sd->tag_idx); #ifdef INVARIANTS sd->ba_tag = htobe64(pa | sd->tag_idx); #endif recycled: /* sd->m is never recycled, should always be NULL */ KASSERT(sd->m == NULL, ("%s: stray mbuf", __func__)); sd->m = m_gethdr(M_NOWAIT, MT_NOINIT); if (sd->m == NULL) break; fl->pending++; fl->needed--; sd++; if (++fl->pidx == fl->cap) { fl->pidx = 0; sd = fl->sdesc; d = fl->desc; } } if (fl->pending >= dbthresh) ring_fl_db(sc, fl); } static int alloc_fl_sdesc(struct sge_fl *fl) { struct fl_sdesc *sd; bus_dma_tag_t tag; int i, rc; FL_LOCK_ASSERT_OWNED(fl); fl->sdesc = malloc(fl->cap * sizeof(struct fl_sdesc), M_CXGBE, M_ZERO | M_WAITOK); tag = fl->tag[fl->tag_idx]; sd = fl->sdesc; for (i = 0; i < fl->cap; i++, sd++) { sd->tag_idx = fl->tag_idx; rc = bus_dmamap_create(tag, 0, &sd->map); if (rc != 0) goto failed; } return (0); failed: while (--i >= 0) { sd--; bus_dmamap_destroy(tag, sd->map); if (sd->m) { m_init(sd->m, NULL, 0, M_NOWAIT, MT_DATA, 0); m_free(sd->m); sd->m = NULL; } } KASSERT(sd == fl->sdesc, ("%s: EDOOFUS", __func__)); free(fl->sdesc, M_CXGBE); fl->sdesc = NULL; return (rc); } static void free_fl_sdesc(struct sge_fl *fl) { struct fl_sdesc *sd; int i; FL_LOCK_ASSERT_OWNED(fl); sd = fl->sdesc; for (i = 0; i < fl->cap; i++, sd++) { if (sd->m) { m_init(sd->m, NULL, 0, M_NOWAIT, MT_DATA, 0); m_free(sd->m); sd->m = NULL; } if (sd->cl) { bus_dmamap_unload(fl->tag[sd->tag_idx], sd->map); uma_zfree(FL_BUF_ZONE(sd->tag_idx), sd->cl); sd->cl = NULL; } bus_dmamap_destroy(fl->tag[sd->tag_idx], sd->map); } free(fl->sdesc, M_CXGBE); fl->sdesc = NULL; } static int alloc_tx_maps(struct sge_txq *txq) { struct tx_map *txm; int i, rc, count; /* * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE * limit for any WR). txq->no_dmamap events shouldn't occur if maps is * sized for the worst case. */ count = txq->eq.qsize * 10 / 8; txq->map_total = txq->map_avail = count; txq->map_cidx = txq->map_pidx = 0; txq->maps = malloc(count * sizeof(struct tx_map), M_CXGBE, M_ZERO | M_WAITOK); txm = txq->maps; for (i = 0; i < count; i++, txm++) { rc = bus_dmamap_create(txq->tx_tag, 0, &txm->map); if (rc != 0) goto failed; } return (0); failed: while (--i >= 0) { txm--; bus_dmamap_destroy(txq->tx_tag, txm->map); } KASSERT(txm == txq->maps, ("%s: EDOOFUS", __func__)); free(txq->maps, M_CXGBE); txq->maps = NULL; return (rc); } static void free_tx_maps(struct sge_txq *txq) { struct tx_map *txm; int i; txm = txq->maps; for (i = 0; i < txq->map_total; i++, txm++) { if (txm->m) { bus_dmamap_unload(txq->tx_tag, txm->map); m_freem(txm->m); txm->m = NULL; } bus_dmamap_destroy(txq->tx_tag, txm->map); } free(txq->maps, M_CXGBE); txq->maps = NULL; } /* * We'll do immediate data tx for non-TSO, but only when not coalescing. We're * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes * of immediate data. */ #define IMM_LEN ( \ 2 * TX_EQ_ESIZE \ - sizeof(struct fw_eth_tx_pkt_wr) \ - sizeof(struct cpl_tx_pkt_core)) /* * Returns non-zero on failure, no need to cleanup anything in that case. * * Note 1: We always try to defrag the mbuf if required and return EFBIG only * if the resulting chain still won't fit in a tx descriptor. * * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf * does not have the TCP header in it. */ static int get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl, int sgl_only) { struct mbuf *m = *fp; struct tx_map *txm; int rc, defragged = 0, n; TXQ_LOCK_ASSERT_OWNED(txq); if (m->m_pkthdr.tso_segsz) sgl_only = 1; /* Do not allow immediate data with LSO */ start: sgl->nsegs = 0; if (m->m_pkthdr.len <= IMM_LEN && !sgl_only) return (0); /* nsegs = 0 tells caller to use imm. tx */ if (txq->map_avail == 0) { txq->no_dmamap++; return (ENOMEM); } txm = &txq->maps[txq->map_pidx]; if (m->m_pkthdr.tso_segsz && m->m_len < 50) { *fp = m_pullup(m, 50); m = *fp; if (m == NULL) return (ENOBUFS); } rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg, &sgl->nsegs, BUS_DMA_NOWAIT); if (rc == EFBIG && defragged == 0) { m = m_defrag(m, M_DONTWAIT); if (m == NULL) return (EFBIG); defragged = 1; *fp = m; goto start; } if (rc != 0) return (rc); txm->m = m; txq->map_avail--; if (++txq->map_pidx == txq->map_total) txq->map_pidx = 0; KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS, ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs)); /* * Store the # of flits required to hold this frame's SGL in nflits. An * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used * then len1 must be set to 0. */ n = sgl->nsegs - 1; sgl->nflits = (3 * n) / 2 + (n & 1) + 2; return (0); } /* * Releases all the txq resources used up in the specified sgl. */ static int free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl) { struct tx_map *txm; TXQ_LOCK_ASSERT_OWNED(txq); if (sgl->nsegs == 0) return (0); /* didn't use any map */ /* 1 pkt uses exactly 1 map, back it out */ txq->map_avail++; if (txq->map_pidx > 0) txq->map_pidx--; else txq->map_pidx = txq->map_total - 1; txm = &txq->maps[txq->map_pidx]; bus_dmamap_unload(txq->tx_tag, txm->map); txm->m = NULL; return (0); } static int write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m, struct sgl *sgl) { struct sge_eq *eq = &txq->eq; struct fw_eth_tx_pkt_wr *wr; struct cpl_tx_pkt_core *cpl; uint32_t ctrl; /* used in many unrelated places */ uint64_t ctrl1; int nflits, ndesc, pktlen; struct tx_sdesc *txsd; caddr_t dst; TXQ_LOCK_ASSERT_OWNED(txq); pktlen = m->m_pkthdr.len; /* * Do we have enough flits to send this frame out? */ ctrl = sizeof(struct cpl_tx_pkt_core); if (m->m_pkthdr.tso_segsz) { nflits = TXPKT_LSO_WR_HDR; ctrl += sizeof(struct cpl_tx_pkt_lso); } else nflits = TXPKT_WR_HDR; if (sgl->nsegs > 0) nflits += sgl->nflits; else { nflits += howmany(pktlen, 8); ctrl += pktlen; } ndesc = howmany(nflits, 8); if (ndesc > eq->avail) return (ENOMEM); /* Firmware work request header */ wr = (void *)&eq->desc[eq->pidx]; wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) | V_FW_WR_IMMDLEN(ctrl)); ctrl = V_FW_WR_LEN16(howmany(nflits, 2)); if (eq->avail == ndesc && !(eq->flags & EQ_CRFLUSHED)) { ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; eq->flags |= EQ_CRFLUSHED; } wr->equiq_to_len16 = htobe32(ctrl); wr->r3 = 0; if (m->m_pkthdr.tso_segsz) { struct cpl_tx_pkt_lso *lso = (void *)(wr + 1); struct ether_header *eh; struct ip *ip; struct tcphdr *tcp; ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE; eh = mtod(m, struct ether_header *); if (eh->ether_type == htons(ETHERTYPE_VLAN)) { ctrl |= V_LSO_ETHHDR_LEN(1); ip = (void *)((struct ether_vlan_header *)eh + 1); } else ip = (void *)(eh + 1); tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4); ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) | V_LSO_TCPHDR_LEN(tcp->th_off); lso->lso_ctrl = htobe32(ctrl); lso->ipid_ofst = htobe16(0); lso->mss = htobe16(m->m_pkthdr.tso_segsz); lso->seqno_offset = htobe32(0); lso->len = htobe32(pktlen); cpl = (void *)(lso + 1); txq->tso_wrs++; } else cpl = (void *)(wr + 1); /* Checksum offload */ ctrl1 = 0; if (!(m->m_pkthdr.csum_flags & CSUM_IP)) ctrl1 |= F_TXPKT_IPCSUM_DIS; if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))) ctrl1 |= F_TXPKT_L4CSUM_DIS; if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP)) txq->txcsum++; /* some hardware assistance provided */ /* VLAN tag insertion */ if (m->m_flags & M_VLANTAG) { ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); txq->vlan_insertion++; } /* CPL header */ cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); cpl->pack = 0; cpl->len = htobe16(pktlen); cpl->ctrl1 = htobe64(ctrl1); /* Software descriptor */ txsd = &txq->sdesc[eq->pidx]; txsd->desc_used = ndesc; eq->pending += ndesc; eq->avail -= ndesc; eq->pidx += ndesc; if (eq->pidx >= eq->cap) eq->pidx -= eq->cap; /* SGL */ dst = (void *)(cpl + 1); if (sgl->nsegs > 0) { txsd->credits = 1; txq->sgl_wrs++; write_sgl_to_txd(eq, sgl, &dst); } else { txsd->credits = 0; txq->imm_wrs++; for (; m; m = m->m_next) { copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); #ifdef INVARIANTS pktlen -= m->m_len; #endif } #ifdef INVARIANTS KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen)); #endif } txq->txpkt_wrs++; return (0); } /* * Returns 0 to indicate that m has been accepted into a coalesced tx work * request. It has either been folded into txpkts or txpkts was flushed and m * has started a new coalesced work request (as the first frame in a fresh * txpkts). * * Returns non-zero to indicate a failure - caller is responsible for * transmitting m, if there was anything in txpkts it has been flushed. */ static int add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) { struct sge_eq *eq = &txq->eq; int can_coalesce; struct tx_sdesc *txsd; int flits; TXQ_LOCK_ASSERT_OWNED(txq); if (txpkts->npkt > 0) { flits = TXPKTS_PKT_HDR + sgl->nflits; can_coalesce = m->m_pkthdr.tso_segsz == 0 && txpkts->nflits + flits <= TX_WR_FLITS && txpkts->nflits + flits <= eq->avail * 8 && txpkts->plen + m->m_pkthdr.len < 65536; if (can_coalesce) { txpkts->npkt++; txpkts->nflits += flits; txpkts->plen += m->m_pkthdr.len; txsd = &txq->sdesc[eq->pidx]; txsd->credits++; return (0); } /* * Couldn't coalesce m into txpkts. The first order of business * is to send txpkts on its way. Then we'll revisit m. */ write_txpkts_wr(txq, txpkts); } /* * Check if we can start a new coalesced tx work request with m as * the first packet in it. */ KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__)); flits = TXPKTS_WR_HDR + sgl->nflits; can_coalesce = m->m_pkthdr.tso_segsz == 0 && flits <= eq->avail * 8 && flits <= TX_WR_FLITS; if (can_coalesce == 0) return (EINVAL); /* * Start a fresh coalesced tx WR with m as the first frame in it. */ txpkts->npkt = 1; txpkts->nflits = flits; txpkts->flitp = &eq->desc[eq->pidx].flit[2]; txpkts->plen = m->m_pkthdr.len; txsd = &txq->sdesc[eq->pidx]; txsd->credits = 1; return (0); } /* * Note that write_txpkts_wr can never run out of hardware descriptors (but * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for * coalescing only if sufficient hardware descriptors are available. */ static void write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts) { struct sge_eq *eq = &txq->eq; struct fw_eth_tx_pkts_wr *wr; struct tx_sdesc *txsd; uint32_t ctrl; int ndesc; TXQ_LOCK_ASSERT_OWNED(txq); ndesc = howmany(txpkts->nflits, 8); wr = (void *)&eq->desc[eq->pidx]; wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR) | V_FW_WR_IMMDLEN(0)); /* immdlen does not matter in this WR */ ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2)); if (eq->avail == ndesc && !(eq->flags & EQ_CRFLUSHED)) { ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ; eq->flags |= EQ_CRFLUSHED; } wr->equiq_to_len16 = htobe32(ctrl); wr->plen = htobe16(txpkts->plen); wr->npkt = txpkts->npkt; - wr->r3 = wr->r4 = 0; + wr->r3 = wr->type = 0; /* Everything else already written */ txsd = &txq->sdesc[eq->pidx]; txsd->desc_used = ndesc; KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__)); eq->pending += ndesc; eq->avail -= ndesc; eq->pidx += ndesc; if (eq->pidx >= eq->cap) eq->pidx -= eq->cap; txq->txpkts_pkts += txpkts->npkt; txq->txpkts_wrs++; txpkts->npkt = 0; /* emptied */ } static inline void write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl) { struct ulp_txpkt *ulpmc; struct ulptx_idata *ulpsc; struct cpl_tx_pkt_core *cpl; struct sge_eq *eq = &txq->eq; uintptr_t flitp, start, end; uint64_t ctrl; caddr_t dst; KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__)); start = (uintptr_t)eq->desc; end = (uintptr_t)eq->spg; /* Checksum offload */ ctrl = 0; if (!(m->m_pkthdr.csum_flags & CSUM_IP)) ctrl |= F_TXPKT_IPCSUM_DIS; if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))) ctrl |= F_TXPKT_L4CSUM_DIS; if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP)) txq->txcsum++; /* some hardware assistance provided */ /* VLAN tag insertion */ if (m->m_flags & M_VLANTAG) { ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag); txq->vlan_insertion++; } /* * The previous packet's SGL must have ended at a 16 byte boundary (this * is required by the firmware/hardware). It follows that flitp cannot * wrap around between the ULPTX master command and ULPTX subcommand (8 * bytes each), and that it can not wrap around in the middle of the * cpl_tx_pkt_core either. */ flitp = (uintptr_t)txpkts->flitp; KASSERT((flitp & 0xf) == 0, ("%s: last SGL did not end at 16 byte boundary: %p", __func__, txpkts->flitp)); /* ULP master command */ ulpmc = (void *)flitp; ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid)); ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) + sizeof(*cpl) + 8 * sgl->nflits, 16)); /* ULP subcommand */ ulpsc = (void *)(ulpmc + 1); ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) | F_ULP_TX_SC_MORE); ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core)); flitp += sizeof(*ulpmc) + sizeof(*ulpsc); if (flitp == end) flitp = start; /* CPL_TX_PKT */ cpl = (void *)flitp; cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) | V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf)); cpl->pack = 0; cpl->len = htobe16(m->m_pkthdr.len); cpl->ctrl1 = htobe64(ctrl); flitp += sizeof(*cpl); if (flitp == end) flitp = start; /* SGL for this frame */ dst = (caddr_t)flitp; txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst); txpkts->flitp = (void *)dst; KASSERT(((uintptr_t)dst & 0xf) == 0, ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst)); } /* * If the SGL ends on an address that is not 16 byte aligned, this function will * add a 0 filled flit at the end. It returns 1 in that case. */ static int write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to) { __be64 *flitp, *end; struct ulptx_sgl *usgl; bus_dma_segment_t *seg; int i, padded; KASSERT(sgl->nsegs > 0 && sgl->nflits > 0, ("%s: bad SGL - nsegs=%d, nflits=%d", __func__, sgl->nsegs, sgl->nflits)); KASSERT(((uintptr_t)(*to) & 0xf) == 0, ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to)); flitp = (__be64 *)(*to); end = flitp + sgl->nflits; seg = &sgl->seg[0]; usgl = (void *)flitp; /* * We start at a 16 byte boundary somewhere inside the tx descriptor * ring, so we're at least 16 bytes away from the status page. There is * no chance of a wrap around in the middle of usgl (which is 16 bytes). */ usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | V_ULPTX_NSGE(sgl->nsegs)); usgl->len0 = htobe32(seg->ds_len); usgl->addr0 = htobe64(seg->ds_addr); seg++; if ((uintptr_t)end <= (uintptr_t)eq->spg) { /* Won't wrap around at all */ for (i = 0; i < sgl->nsegs - 1; i++, seg++) { usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len); usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr); } if (i & 1) usgl->sge[i / 2].len[1] = htobe32(0); } else { /* Will wrap somewhere in the rest of the SGL */ /* 2 flits already written, write the rest flit by flit */ flitp = (void *)(usgl + 1); for (i = 0; i < sgl->nflits - 2; i++) { if ((uintptr_t)flitp == (uintptr_t)eq->spg) flitp = (void *)eq->desc; *flitp++ = get_flit(seg, sgl->nsegs - 1, i); } end = flitp; } if ((uintptr_t)end & 0xf) { *(uint64_t *)end = 0; end++; padded = 1; } else padded = 0; if ((uintptr_t)end == (uintptr_t)eq->spg) *to = (void *)eq->desc; else *to = (void *)end; return (padded); } static inline void copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) { if ((uintptr_t)(*to) + len <= (uintptr_t)eq->spg) { bcopy(from, *to, len); (*to) += len; } else { int portion = (uintptr_t)eq->spg - (uintptr_t)(*to); bcopy(from, *to, portion); from += portion; portion = len - portion; /* remaining */ bcopy(from, (void *)eq->desc, portion); (*to) = (caddr_t)eq->desc + portion; } } static inline void ring_eq_db(struct adapter *sc, struct sge_eq *eq) { wmb(); t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), V_QID(eq->cntxt_id) | V_PIDX(eq->pending)); eq->pending = 0; } static inline int reclaimable(struct sge_eq *eq) { unsigned int cidx; cidx = eq->spg->cidx; /* stable snapshot */ cidx = be16_to_cpu(cidx); if (cidx >= eq->cidx) return (cidx - eq->cidx); else return (cidx + eq->cap - eq->cidx); } /* * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as * many as possible but stop when there are around "n" mbufs to free. * * The actual number reclaimed is provided as the return value. */ static int reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n) { struct tx_sdesc *txsd; struct tx_map *txm; unsigned int reclaimed, maps; struct sge_eq *eq = &txq->eq; EQ_LOCK_ASSERT_OWNED(eq); if (can_reclaim == 0) can_reclaim = reclaimable(eq); maps = reclaimed = 0; while (can_reclaim && maps < n) { int ndesc; txsd = &txq->sdesc[eq->cidx]; ndesc = txsd->desc_used; /* Firmware doesn't return "partial" credits. */ KASSERT(can_reclaim >= ndesc, ("%s: unexpected number of credits: %d, %d", __func__, can_reclaim, ndesc)); maps += txsd->credits; reclaimed += ndesc; can_reclaim -= ndesc; eq->cidx += ndesc; if (__predict_false(eq->cidx >= eq->cap)) eq->cidx -= eq->cap; } txm = &txq->maps[txq->map_cidx]; if (maps) prefetch(txm->m); eq->avail += reclaimed; KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */ ("%s: too many descriptors available", __func__)); txq->map_avail += maps; KASSERT(txq->map_avail <= txq->map_total, ("%s: too many maps available", __func__)); while (maps--) { struct tx_map *next; next = txm + 1; if (__predict_false(txq->map_cidx + 1 == txq->map_total)) next = txq->maps; prefetch(next->m); bus_dmamap_unload(txq->tx_tag, txm->map); m_freem(txm->m); txm->m = NULL; txm = next; if (__predict_false(++txq->map_cidx == txq->map_total)) txq->map_cidx = 0; } return (reclaimed); } static void write_eqflush_wr(struct sge_eq *eq) { struct fw_eq_flush_wr *wr; EQ_LOCK_ASSERT_OWNED(eq); KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__)); wr = (void *)&eq->desc[eq->pidx]; bzero(wr, sizeof(*wr)); wr->opcode = FW_EQ_FLUSH_WR; wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) | F_FW_WR_EQUEQ | F_FW_WR_EQUIQ); eq->flags |= EQ_CRFLUSHED; eq->pending++; eq->avail--; if (++eq->pidx == eq->cap) eq->pidx = 0; } static __be64 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx) { int i = (idx / 3) * 2; switch (idx % 3) { case 0: { __be64 rc; rc = htobe32(sgl[i].ds_len); if (i + 1 < nsegs) rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32; return (rc); } case 1: return htobe64(sgl[i].ds_addr); case 2: return htobe64(sgl[i + 1].ds_addr); } return (0); } static void set_fl_tag_idx(struct sge_fl *fl, int mtu) { int i; FL_LOCK_ASSERT_OWNED(fl); for (i = 0; i < FL_BUF_SIZES - 1; i++) { if (FL_BUF_SIZE(i) >= (mtu + FL_PKTSHIFT)) break; } fl->tag_idx = i; } static int handle_sge_egr_update(struct adapter *sc, const struct cpl_sge_egr_update *cpl) { unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid)); struct sge *s = &sc->sge; struct sge_txq *txq; struct port_info *pi; txq = (void *)s->eqmap[qid - s->eq_start]; TXQ_LOCK(txq); if (txq->eq.flags & EQ_CRFLUSHED) { pi = txq->ifp->if_softc; taskqueue_enqueue(pi->tq, &txq->resume_tx); txq->egr_update++; } else wakeup_one(txq); /* txq is going away, wakeup free_txq */ TXQ_UNLOCK(txq); return (0); } +static void +handle_cpl(struct adapter *sc, struct sge_iq *iq) +{ + const struct rss_header *rss = (const void *)iq->cdesc; + const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); + + switch (rss->opcode) { + case CPL_FW4_MSG: + case CPL_FW6_MSG: + if (cpl->type == FW6_TYPE_CMD_RPL) + t4_handle_fw_rpl(sc, cpl->data); + break; + + case CPL_SGE_EGR_UPDATE: + handle_sge_egr_update(sc, (const void *)cpl); + break; + + case CPL_SET_TCB_RPL: + filter_rpl(sc, (const void *)cpl); + break; + + default: + panic("%s: unexpected CPL opcode 0x%x", __func__, rss->opcode); + } +} + /* * m0 is freed on successful transmission. */ static int ctrl_tx(struct adapter *sc, struct sge_ctrlq *ctrlq, struct mbuf *m0) { struct sge_eq *eq = &ctrlq->eq; int rc = 0, ndesc; int can_reclaim; caddr_t dst; struct mbuf *m; M_ASSERTPKTHDR(m0); if (m0->m_pkthdr.len > SGE_MAX_WR_LEN) { - ctrlq->too_long++; + log(LOG_ERR, "%s: %s work request too long (%d)", + device_get_nameunit(sc->dev), __func__, m0->m_pkthdr.len); return (EMSGSIZE); } ndesc = howmany(m0->m_pkthdr.len, CTRL_EQ_ESIZE); EQ_LOCK(eq); can_reclaim = reclaimable(eq); eq->cidx += can_reclaim; eq->avail += can_reclaim; if (__predict_false(eq->cidx >= eq->cap)) eq->cidx -= eq->cap; if (eq->avail < ndesc) { rc = EAGAIN; ctrlq->no_desc++; goto failed; } dst = (void *)&eq->desc[eq->pidx]; for (m = m0; m; m = m->m_next) copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len); eq->pidx += ndesc; if (__predict_false(eq->pidx >= eq->cap)) eq->pidx -= eq->cap; eq->pending += ndesc; - ctrlq->total_wrs++; ring_eq_db(sc, eq); failed: EQ_UNLOCK(eq); if (rc == 0) m_freem(m0); return (rc); +} + +static int +sysctl_uint16(SYSCTL_HANDLER_ARGS) +{ + uint16_t *id = arg1; + int i = *id; + + return sysctl_handle_int(oidp, &i, 0, req); } Index: stable/8/sys/modules/cxgbe/if_cxgbe/Makefile =================================================================== --- stable/8/sys/modules/cxgbe/if_cxgbe/Makefile (revision 222793) +++ stable/8/sys/modules/cxgbe/if_cxgbe/Makefile (revision 222794) @@ -1,19 +1,19 @@ # # $FreeBSD$ # CXGBE = ${.CURDIR}/../../../dev/cxgbe .PATH: ${CXGBE} ${CXGBE}/common KMOD = if_cxgbe -SRCS = t4_main.c t4_sge.c +SRCS = t4_main.c t4_sge.c t4_l2t.c SRCS+= t4_hw.c SRCS+= device_if.h bus_if.h pci_if.h SRCS+= opt_inet.h CFLAGS+= -I${CXGBE} # Provide the timestamp of a packet in its header mbuf. #CFLAGS+= -DT4_PKT_TIMESTAMP .include Index: stable/8/sys =================================================================== --- stable/8/sys (revision 222793) +++ stable/8/sys (revision 222794) Property changes on: stable/8/sys ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys:r222509-222510,222513,222551-222552,222701,222703