Index: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h =================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h (revision 221805) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h (revision 221806) @@ -1,746 +1,656 @@ /* * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting * Copyright (c) 2002-2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _DEV_ATH_AR5416REG_H #define _DEV_ATH_AR5416REG_H #include /* * Register added starting with the AR5416 */ #define AR_MIRT 0x0020 /* interrupt rate threshold */ #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ #define AR_GTXTO 0x0064 /* global transmit timeout */ #define AR_GTTM 0x0068 /* global transmit timeout mode */ #define AR_CST 0x006C /* carrier sense timeout */ #define AR_MAC_LED 0x1f04 /* LED control */ #define AR_WA 0x4004 /* PCIE work-arounds */ #define AR_PCIE_PM_CTRL 0x4014 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */ #define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ #define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ #define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ #define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ #define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ #define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ #define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ #define AR5416_PCIE_SERDES 0x4040 #define AR5416_PCIE_SERDES2 0x4044 #define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ #define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ #define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ #define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ #define AR_GPIO_INPUT_MUX1 0x4058 #define AR_GPIO_INPUT_MUX2 0x405c #define AR_GPIO_OUTPUT_MUX1 0x4060 #define AR_GPIO_OUTPUT_MUX2 0x4064 #define AR_GPIO_OUTPUT_MUX3 0x4068 #define AR_EEPROM_STATUS_DATA 0x407c #define AR_OBS 0x4080 #ifdef AH_SUPPORT_AR9130 #define AR_RTC_BASE 0x20000 #else #define AR_RTC_BASE 0x7000 #endif /* AH_SUPPORT_AR9130 */ #define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ #define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 #define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ #define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ #define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 #define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ #define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ #define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ #define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ #ifdef AH_SUPPORT_AR9130 /* RTC_DERIVED_* - only for AR9130 */ #define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) #define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe #define AR_RTC_DERIVED_CLK_PERIOD_S 1 #endif /* AH_SUPPORT_AR9130 */ -/* AR9280: rf long shift registers */ -#define AR_AN_RF2G1_CH0 0x7810 -#define AR_AN_RF5G1_CH0 0x7818 -#define AR_AN_RF2G1_CH1 0x7834 -#define AR_AN_RF5G1_CH1 0x783C -#define AR_AN_TOP2 0x7894 -#define AR_AN_SYNTH9 0x7868 -#define AR9285_AN_RF2G1 0x7820 -#define AR9285_AN_RF2G2 0x7824 -#define AR9285_AN_RF2G3 0x7828 -#define AR9285_AN_RF2G4 0x782C -#define AR9285_AN_RF2G6 0x7834 -#define AR9285_AN_RF2G7 0x7838 -#define AR9285_AN_RF2G8 0x783C -#define AR9285_AN_RF2G9 0x7840 -#define AR9285_AN_RXTXBB1 0x7854 -#define AR9285_AN_TOP2 0x7868 -#define AR9285_AN_TOP3 0x786c -#define AR9285_AN_TOP4 0x7870 -#define AR9285_AN_TOP4_DEFAULT 0x10142c00 - #define AR_RESET_TSF 0x8020 #define AR_RXFIFO_CFG 0x8114 #define AR_PHY_ERR_1 0x812c #define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ #define AR_PHY_ERR_2 0x8134 #define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ #define AR_TSFOOR_THRESHOLD 0x813c #define AR_PHY_ERR_3 0x8168 #define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ #define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ #define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ #define AR_TXOP_4_7 0x81f4 #define AR_TXOP_8_11 0x81f8 #define AR_TXOP_12_15 0x81fc /* generic timers based on tsf - all uS */ #define AR_NEXT_TBTT 0x8200 #define AR_NEXT_DBA 0x8204 #define AR_NEXT_SWBA 0x8208 #define AR_NEXT_CFP 0x8208 #define AR_NEXT_HCF 0x820C #define AR_NEXT_TIM 0x8210 #define AR_NEXT_DTIM 0x8214 #define AR_NEXT_QUIET 0x8218 #define AR_NEXT_NDP 0x821C #define AR5416_BEACON_PERIOD 0x8220 #define AR_DBA_PERIOD 0x8224 #define AR_SWBA_PERIOD 0x8228 #define AR_HCF_PERIOD 0x822C #define AR_TIM_PERIOD 0x8230 #define AR_DTIM_PERIOD 0x8234 #define AR_QUIET_PERIOD 0x8238 #define AR_NDP_PERIOD 0x823C #define AR_TIMER_MODE 0x8240 #define AR_SLP32_MODE 0x8244 #define AR_SLP32_WAKE 0x8248 #define AR_SLP32_INC 0x824c #define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ #define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ #define AR_SLP_MIB_CTRL 0x8258 #define AR_2040_MODE 0x8318 #define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ #define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ #define AR_PCU_TXBUF_CTRL 0x8340 #define AR_PCU_MISC_MODE2 0x8344 /* DMA & PCI Registers in PCI space (usable during sleep)*/ #define AR_RC_AHB 0x00000001 /* AHB reset */ #define AR_RC_APB 0x00000002 /* APB reset */ #define AR_RC_HOSTIF 0x00000100 /* host interface reset */ #define AR_MIRT_VAL 0x0000ffff /* in uS */ #define AR_MIRT_VAL_S 16 #define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ #define AR_TIMT_LAST_S 0 #define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ #define AR_TIMT_FIRST_S 16 #define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ #define AR_RIMT_LAST_S 0 #define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ #define AR_RIMT_FIRST_S 16 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit #define AR_GTTM_USEC 0x00000001 // usec strobe #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit /* MAC tx DMA size config */ #define AR_TXCFG_DMASZ_MASK 0x00000003 #define AR_TXCFG_DMASZ_4B 0 #define AR_TXCFG_DMASZ_8B 1 #define AR_TXCFG_DMASZ_16B 2 #define AR_TXCFG_DMASZ_32B 3 #define AR_TXCFG_DMASZ_64B 4 #define AR_TXCFG_DMASZ_128B 5 #define AR_TXCFG_DMASZ_256B 6 #define AR_TXCFG_DMASZ_512B 7 #define AR_TXCFG_ATIM_TXPOLICY 0x00000800 /* MAC rx DMA size config */ #define AR_RXCFG_DMASZ_MASK 0x00000007 #define AR_RXCFG_DMASZ_4B 0 #define AR_RXCFG_DMASZ_8B 1 #define AR_RXCFG_DMASZ_16B 2 #define AR_RXCFG_DMASZ_32B 3 #define AR_RXCFG_DMASZ_64B 4 #define AR_RXCFG_DMASZ_128B 5 #define AR_RXCFG_DMASZ_256B 6 #define AR_RXCFG_DMASZ_512B 7 /* MAC Led registers */ #define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ #define AR_CFG_SCLK_RATE_IND_S 0 #define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ #define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ #define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ #define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ #define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ #define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ #define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ #define AR_MAC_LED_MODE_S 7 #define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ #define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ #define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ #define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ #define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ #define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ #define AR_MAC_LED_ASSOC 0x00000c00 #define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ #define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ #define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ #define AR_MAC_LED_ASSOC_S 10 #define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ #define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ #define AR_WA_ANALOG_SHIFT 0x00100000 #define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ #define AR_WA_DEFAULT 0x0000073f #define AR9280_WA_DEFAULT 0x0040073f #define AR9285_WA_DEFAULT 0x004a05cb #define AR_PCIE_PM_CTRL_ENA 0x00080000 #define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ #define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ #define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ #define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ #define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ #define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ #define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ #define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ /* MAC PCU Registers */ #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ /* Extended PCU DIAG_SW control fields */ #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ #define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ #define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ #define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ #define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ #define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ #define AR_TXOP_X_VAL 0x000000FF #define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ /* Interrupts */ #define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ #define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ #define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ #define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ #define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ #define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ #define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ #define AR_ISR_S5 0x0098 #define AR_ISR_S5_S 0x00d8 #define AR_ISR_S5_TIM_TIMER 0x00000010 #define AR_INTR_SPURIOUS 0xffffffff #define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ #define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ #define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ #define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ #define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ /* Interrupt Mask Registers */ #define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ #define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ #define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ #define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ #define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ #define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ /* synchronous interrupt signals */ #define AR_INTR_SYNC_RTC_IRQ 0x00000001 #define AR_INTR_SYNC_MAC_IRQ 0x00000002 #define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 #define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 #define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 #define AR_INTR_SYNC_HOST1_FATAL 0x00000020 #define AR_INTR_SYNC_HOST1_PERR 0x00000040 #define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 #define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 #define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 #define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 #define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 #define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 #define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 #define AR_INTR_SYNC_PM_ACCESS 0x00004000 #define AR_INTR_SYNC_MAC_AWAKE 0x00008000 #define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 #define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 #define AR_INTR_SYNC_ALL 0x0003FFFF /* default synchronous interrupt signals enabled */ #define AR_INTR_SYNC_DEFAULT \ (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ AR_INTR_SYNC_MAC_SLEEP_ACCESS) #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 #define AR_INTR_SYNC_MASK_GPIO_S 18 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 #define AR_INTR_SYNC_ENABLE_GPIO_S 18 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ #define AR_INTR_ASYNC_MASK_GPIO_S 18 #define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 /* RTC registers */ #define AR_RTC_RC_M 0x00000003 #define AR_RTC_RC_MAC_WARM 0x00000001 #define AR_RTC_RC_MAC_COLD 0x00000002 #ifdef AH_SUPPORT_AR9130 #define AR_RTC_RC_COLD_RESET 0x00000004 #define AR_RTC_RC_WARM_RESET 0x00000008 #endif /* AH_SUPPORT_AR9130 */ #define AR_RTC_PLL_DIV 0x0000001f #define AR_RTC_PLL_DIV_S 0 #define AR_RTC_PLL_DIV2 0x00000020 #define AR_RTC_PLL_REFDIV_5 0x000000c0 #define AR_RTC_SOWL_PLL_DIV 0x000003ff #define AR_RTC_SOWL_PLL_DIV_S 0 #define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 #define AR_RTC_SOWL_PLL_REFDIV_S 10 #define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 #define AR_RTC_SOWL_PLL_CLKSEL_S 14 #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ #define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ #ifdef AH_SUPPORT_AR9130 #define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ #else #define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ #endif /* AH_SUPPORT_AR9130 */ #define AR_RTC_STATUS_SHUTDOWN 0x00000001 #define AR_RTC_STATUS_ON 0x00000002 #define AR_RTC_STATUS_SLEEP 0x00000004 #define AR_RTC_STATUS_WAKEUP 0x00000008 #define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ #define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ #define AR_RTC_SLEEP_DERIVED_CLK 0x2 #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ #define AR_RTC_PLL_CLKSEL 0x00000300 #define AR_RTC_PLL_CLKSEL_S 8 /* AR9280: rf long shift registers */ +#define AR_AN_RF2G1_CH0 0x7810 +#define AR_AN_RF5G1_CH0 0x7818 +#define AR_AN_RF2G1_CH1 0x7834 +#define AR_AN_RF5G1_CH1 0x783C +#define AR_AN_TOP2 0x7894 +#define AR_AN_SYNTH9 0x7868 + #define AR_AN_RF2G1_CH0_OB 0x03800000 #define AR_AN_RF2G1_CH0_OB_S 23 #define AR_AN_RF2G1_CH0_DB 0x1C000000 #define AR_AN_RF2G1_CH0_DB_S 26 #define AR_AN_RF5G1_CH0_OB5 0x00070000 #define AR_AN_RF5G1_CH0_OB5_S 16 #define AR_AN_RF5G1_CH0_DB5 0x00380000 #define AR_AN_RF5G1_CH0_DB5_S 19 #define AR_AN_RF2G1_CH1_OB 0x03800000 #define AR_AN_RF2G1_CH1_OB_S 23 #define AR_AN_RF2G1_CH1_DB 0x1C000000 #define AR_AN_RF2G1_CH1_DB_S 26 #define AR_AN_RF5G1_CH1_OB5 0x00070000 #define AR_AN_RF5G1_CH1_OB5_S 16 #define AR_AN_RF5G1_CH1_DB5 0x00380000 #define AR_AN_RF5G1_CH1_DB5_S 19 #define AR_AN_TOP1 0x7890 #define AR_AN_TOP1_DACIPMODE 0x00040000 #define AR_AN_TOP1_DACIPMODE_S 18 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 #define AR_AN_TOP2_XPABIAS_LVL_S 30 #define AR_AN_TOP2_LOCALBIAS 0x00200000 #define AR_AN_TOP2_LOCALBIAS_S 21 #define AR_AN_TOP2_PWDCLKIND 0x00400000 #define AR_AN_TOP2_PWDCLKIND_S 22 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 #define AR_AN_SYNTH9_REFDIVA_S 27 -/* AR9285 Analog registers */ -#define AR9285_AN_RF2G1_ENPACAL 0x00000800 -#define AR9285_AN_RF2G1_ENPACAL_S 11 -#define AR9285_AN_RF2G1_PDPADRV1 0x02000000 -#define AR9285_AN_RF2G1_PDPADRV1_S 25 -#define AR9285_AN_RF2G1_PDPADRV2 0x01000000 -#define AR9285_AN_RF2G1_PDPADRV2_S 24 -#define AR9285_AN_RF2G1_PDPAOUT 0x00800000 -#define AR9285_AN_RF2G1_PDPAOUT_S 23 - -#define AR9285_AN_RF2G2_OFFCAL 0x00001000 -#define AR9285_AN_RF2G2_OFFCAL_S 12 - -#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 -#define AR9285_AN_RF2G3_PDVCCOMP_S 25 -#define AR9285_AN_RF2G3_OB_0 0x00E00000 -#define AR9285_AN_RF2G3_OB_0_S 21 -#define AR9285_AN_RF2G3_OB_1 0x001C0000 -#define AR9285_AN_RF2G3_OB_1_S 18 -#define AR9285_AN_RF2G3_OB_2 0x00038000 -#define AR9285_AN_RF2G3_OB_2_S 15 -#define AR9285_AN_RF2G3_OB_3 0x00007000 -#define AR9285_AN_RF2G3_OB_3_S 12 -#define AR9285_AN_RF2G3_OB_4 0x00000E00 -#define AR9285_AN_RF2G3_OB_4_S 9 - -#define AR9285_AN_RF2G3_DB1_0 0x000001C0 -#define AR9285_AN_RF2G3_DB1_0_S 6 -#define AR9285_AN_RF2G3_DB1_1 0x00000038 -#define AR9285_AN_RF2G3_DB1_1_S 3 -#define AR9285_AN_RF2G3_DB1_2 0x00000007 -#define AR9285_AN_RF2G3_DB1_2_S 0 - -#define AR9285_AN_RF2G4_DB1_3 0xE0000000 -#define AR9285_AN_RF2G4_DB1_3_S 29 -#define AR9285_AN_RF2G4_DB1_4 0x1C000000 -#define AR9285_AN_RF2G4_DB1_4_S 26 - -#define AR9285_AN_RF2G4_DB2_0 0x03800000 -#define AR9285_AN_RF2G4_DB2_0_S 23 -#define AR9285_AN_RF2G4_DB2_1 0x00700000 -#define AR9285_AN_RF2G4_DB2_1_S 20 -#define AR9285_AN_RF2G4_DB2_2 0x000E0000 -#define AR9285_AN_RF2G4_DB2_2_S 17 -#define AR9285_AN_RF2G4_DB2_3 0x0001C000 -#define AR9285_AN_RF2G4_DB2_3_S 14 -#define AR9285_AN_RF2G4_DB2_4 0x00003800 -#define AR9285_AN_RF2G4_DB2_4_S 11 - -#define AR9285_AN_RF2G6_CCOMP 0x00007800 -#define AR9285_AN_RF2G6_CCOMP_S 11 -#define AR9285_AN_RF2G6_OFFS 0x03f00000 -#define AR9285_AN_RF2G6_OFFS_S 20 - #define AR9271_AN_RF2G6_OFFS 0x07f00000 #define AR9271_AN_RF2G6_OFFS_S 20 - -#define AR9285_AN_RF2G7_PWDDB 0x00000002 -#define AR9285_AN_RF2G7_PWDDB_S 1 -#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 -#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 - -#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 -#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 - -#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 -#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 -#define AR9285_AN_RXTXBB1_PDV2I 0x00000080 -#define AR9285_AN_RXTXBB1_PDV2I_S 7 -#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 -#define AR9285_AN_RXTXBB1_PDDACIF_S 8 -#define AR9285_AN_RXTXBB1_SPARE9 0x00000001 -#define AR9285_AN_RXTXBB1_SPARE9_S 0 - -#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C -#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 -#define AR9285_AN_TOP3_PWDDAC 0x00800000 -#define AR9285_AN_TOP3_PWDDAC_S 23 /* Sleep control */ #define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ #define AR5416_SLEEP1_CAB_TIMEOUT_S 22 #define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ #define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 /* Sleep Registers */ #define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ #define AR_SLP32_ENA 0x00100000 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ #define AR_SLP32_TST_INC 0x000FFFFF #define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ #define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ #define AR_TIMER_MODE_TBTT 0x00000001 #define AR_TIMER_MODE_DBA 0x00000002 #define AR_TIMER_MODE_SWBA 0x00000004 #define AR_TIMER_MODE_HCF 0x00000008 #define AR_TIMER_MODE_TIM 0x00000010 #define AR_TIMER_MODE_DTIM 0x00000020 #define AR_TIMER_MODE_QUIET 0x00000040 #define AR_TIMER_MODE_NDP 0x00000080 #define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 #define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 #define AR_TIMER_MODE_THRESH 0xFFFFF000 #define AR_TIMER_MODE_THRESH_S 12 /* PCU Misc modes */ #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ #define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ #define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ #define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ #define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ #define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ #define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ #define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 /* * This bit enables the Multicast search based on both MAC Address and Key ID. * If bit is 0, then Multicast search is based on MAC address only. * For Merlin and above only. */ #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 /* GPIO Interrupt */ #define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ #define AR_INTR_GPIO_S 20 #define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ #define AR_GPIO_OUT_VAL 0x000FFC00 #define AR_GPIO_OUT_VAL_S 10 #define AR_GPIO_INTR_CTRL 0x3FF00000 #define AR_GPIO_INTR_CTRL_S 20 #define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ #define AR_GPIO_IN_VAL_S 14 #define AR928X_GPIO_IN_VAL 0x000FFC00 #define AR928X_GPIO_IN_VAL_S 10 #define AR9285_GPIO_IN_VAL 0x00FFF000 #define AR9285_GPIO_IN_VAL_S 12 #define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ #define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ #define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ #define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ #define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ #define AR_GPIO_INTR_POL_VAL 0x1FFF #define AR_GPIO_INTR_POL_VAL_S 0 #define AR_GPIO_JTAG_DISABLE 0x00020000 #define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 /* Eeprom defines */ #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff #define AR_EEPROM_STATUS_DATA_VAL_S 0 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 /* * AR5212 defines the MAC revision mask as 0xF, but both ath9k and * the Atheros HAL define it as 0x7. * * What this means however is AR5416 silicon revisions have * changed. The below macros are for what is contained in the * lower four bits; if the lower three bits are taken into account * the revisions become 1.0 => 0x0, 2.0 => 0x1, 2.2 => 0x2. */ /* These are the legacy revisions, with a four bit AR_SREV_REVISION mask */ #define AR_SREV_REVISION_OWL_10 0x08 #define AR_SREV_REVISION_OWL_20 0x09 #define AR_SREV_REVISION_OWL_22 0x0a #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ /* Test macro for owl 1.0 */ #define IS_5416V1(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_10) #define IS_5416V2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) #define IS_5416V2_2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_22) /* Misc; compatibility with Atheros HAL */ #define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) #define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) /* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ #define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ #define AR_XSREV_ID_S 0 #define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ #define AR_XSREV_VERSION_S 18 #define AR_XSREV_TYPE 0x0003F000 /* Chip type */ #define AR_XSREV_TYPE_S 12 #define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, * 0:2 chains) */ #define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ #define AR_XSREV_REVISION 0x00000F00 #define AR_XSREV_REVISION_S 8 #define AR_XSREV_VERSION_OWL_PCI 0x0D #define AR_XSREV_VERSION_OWL_PCIE 0x0C /* * These are from ath9k/Atheros and assume an AR_SREV version mask * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. * Thus, don't use these values as they're incorrect here; use * AR_SREV_REVISION_OWL_{10,20,22}. */ #if 0 #define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ #define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ #define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ #endif #define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ #define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ #define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ #define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ #define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ #define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ #define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ #define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ #define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ #define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ #define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ #define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ /* Owl (AR5416) */ #define AR_SREV_OWL(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) #define AR_SREV_OWL_20_OR_LATER(_ah) \ ((AR_SREV_OWL(_ah) && \ AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) || \ AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) #define AR_SREV_OWL_22_OR_LATER(_ah) \ ((AR_SREV_OWL(_ah) && \ AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22) || \ AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) /* Howl (AR9130) */ #define AR_SREV_HOWL(_ah) \ (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) #define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) /* Sowl (AR9160) */ #define AR_SREV_SOWL(_ah) \ (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) #define AR_SREV_SOWL_10_OR_LATER(_ah) \ (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) #define AR_SREV_SOWL_11(_ah) \ (AR_SREV_SOWL(_ah) && \ AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) /* Merlin (AR9280) */ #define AR_SREV_MERLIN(_ah) \ (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) #define AR_SREV_MERLIN_10_OR_LATER(_ah) \ (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) #define AR_SREV_MERLIN_20(_ah) \ (AR_SREV_MERLIN(_ah) && \ AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) #define AR_SREV_MERLIN_20_OR_LATER(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ (AR_SREV_MERLIN((_ah)) && \ AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) /* Kite (AR9285) */ #define AR_SREV_KITE(_ah) \ (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) #define AR_SREV_KITE_10_OR_LATER(_ah) \ (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) #define AR_SREV_KITE_11(_ah) \ (AR_SREV_KITE(ah) && \ AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) #define AR_SREV_KITE_11_OR_LATER(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ (AR_SREV_KITE((_ah)) && \ AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)) #define AR_SREV_KITE_12(_ah) \ (AR_SREV_KITE(ah) && \ AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) #define AR_SREV_KITE_12_OR_LATER(_ah) \ ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ (AR_SREV_KITE((_ah)) && \ AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)) #define AR_SREV_9285E_20(_ah) \ (AR_SREV_KITE_12_OR_LATER(_ah) && \ ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) /* Not yet implemented chips */ #define AR_SREV_9271(_ah) 0 #define AR_SREV_9287_11_OR_LATER(_ah) 0 #define AR_SREV_KIWI_10_OR_LATER(_ah) 0 #endif /* _DEV_ATH_AR5416REG_H */ Index: head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.c =================================================================== --- head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.c (revision 221805) +++ head/sys/dev/ath/ath_hal/ar9002/ar9285_cal.c (revision 221806) @@ -1,268 +1,269 @@ /* * Copyright (c) 2008-2010 Atheros Communications Inc. * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include "opt_ah.h" #include "ah.h" #include "ah_internal.h" #include "ah_eeprom_v4k.h" #include "ar9002/ar9285.h" #include "ar5416/ar5416reg.h" #include "ar5416/ar5416phy.h" #include "ar9002/ar9002phy.h" #include "ar9002/ar9285phy.h" +#include "ar9002/ar9285an.h" #include "ar9002/ar9285_cal.h" #define AR9285_CLCAL_REDO_THRESH 1 #define MAX_PACAL_SKIPCOUNT 8 #define N(a) (sizeof (a) / sizeof (a[0])) static void ar9285_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset) { uint32_t regVal; int i, offset, offs_6_1, offs_0; uint32_t ccomp_org, reg_field; uint32_t regList[][2] = { { 0x786c, 0 }, { 0x7854, 0 }, { 0x7820, 0 }, { 0x7824, 0 }, { 0x7868, 0 }, { 0x783c, 0 }, { 0x7838, 0 }, }; /* PA CAL is not needed for high power solution */ if (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL) == AR5416_EEP_TXGAIN_HIGH_POWER) return; HALDEBUG(ah, HAL_DEBUG_PERCAL, "Running PA Calibration\n"); for (i = 0; i < N(regList); i++) regList[i][1] = OS_REG_READ(ah, regList[i][0]); regVal = OS_REG_READ(ah, 0x7834); regVal &= (~(0x1)); OS_REG_WRITE(ah, 0x7834, regVal); regVal = OS_REG_READ(ah, 0x9808); regVal |= (0x1 << 27); OS_REG_WRITE(ah, 0x9808, regVal); OS_REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf); OS_REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); OS_DELAY(30); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0); for (i = 6; i > 0; i--) { regVal = OS_REG_READ(ah, 0x7834); regVal |= (1 << (19 + i)); OS_REG_WRITE(ah, 0x7834, regVal); OS_DELAY(1); regVal = OS_REG_READ(ah, 0x7834); regVal &= (~(0x1 << (19 + i))); reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); regVal |= (reg_field << (19 + i)); OS_REG_WRITE(ah, 0x7834, regVal); } OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1); OS_DELAY(1); reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field); offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); offs_0 = MS(OS_REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); offset = (offs_6_1<<1) | offs_0; offset = offset - 0; offs_6_1 = offset>>1; offs_0 = offset & 1; if ((!is_reset) && (AH9285(ah)->pacal_info.prev_offset == offset)) { if (AH9285(ah)->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) AH9285(ah)->pacal_info.max_skipcount = 2 * AH9285(ah)->pacal_info.max_skipcount; AH9285(ah)->pacal_info.skipcount = AH9285(ah)->pacal_info.max_skipcount; } else { AH9285(ah)->pacal_info.max_skipcount = 1; AH9285(ah)->pacal_info.skipcount = 0; AH9285(ah)->pacal_info.prev_offset = offset; } OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); regVal = OS_REG_READ(ah, 0x7834); regVal |= 0x1; OS_REG_WRITE(ah, 0x7834, regVal); regVal = OS_REG_READ(ah, 0x9808); regVal &= (~(0x1 << 27)); OS_REG_WRITE(ah, 0x9808, regVal); for (i = 0; i < N(regList); i++) OS_REG_WRITE(ah, regList[i][0], regList[i][1]); OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org); } void ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset) { if (AR_SREV_KITE_11_OR_LATER(ah)) { if (is_reset || !AH9285(ah)->pacal_info.skipcount) ar9285_hw_pa_cal(ah, is_reset); else AH9285(ah)->pacal_info.skipcount--; } } /* Carrier leakage Calibration fix */ static HAL_BOOL ar9285_hw_cl_cal(struct ath_hal *ah, const struct ieee80211_channel *chan) { OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); if (IEEE80211_IS_CHAN_HT20(chan)) { OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); OS_REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { HALDEBUG(ah, HAL_DEBUG_PERCAL, "offset calibration failed to complete in 1ms; noisy environment?\n"); return AH_FALSE; } OS_REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); } OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { HALDEBUG(ah, HAL_DEBUG_PERCAL, "offset calibration failed to complete in 1ms; noisy environment?\n"); return AH_FALSE; } OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); return AH_TRUE; } static HAL_BOOL ar9285_hw_clc(struct ath_hal *ah, const struct ieee80211_channel *chan) { int i; uint32_t txgain_max; uint32_t clc_gain, gain_mask = 0, clc_num = 0; uint32_t reg_clc_I0, reg_clc_Q0; uint32_t i0_num = 0; uint32_t q0_num = 0; uint32_t total_num = 0; uint32_t reg_rf2g5_org; HAL_BOOL retv = AH_TRUE; if (!(ar9285_hw_cl_cal(ah, chan))) return AH_FALSE; txgain_max = MS(OS_REG_READ(ah, AR_PHY_TX_PWRCTRL7), AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX); for (i = 0; i < (txgain_max+1); i++) { clc_gain = (OS_REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) & AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S; if (!(gain_mask & (1 << clc_gain))) { gain_mask |= (1 << clc_gain); clc_num++; } } for (i = 0; i < clc_num; i++) { reg_clc_I0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S; reg_clc_Q0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S; if (reg_clc_I0 == 0) i0_num++; if (reg_clc_Q0 == 0) q0_num++; } total_num = i0_num + q0_num; if (total_num > AR9285_CLCAL_REDO_THRESH) { reg_rf2g5_org = OS_REG_READ(ah, AR9285_RF2G5); if (AR_SREV_9285E_20(ah)) { OS_REG_WRITE(ah, AR9285_RF2G5, (reg_rf2g5_org & AR9285_RF2G5_IC50TX) | AR9285_RF2G5_IC50TX_XE_SET); } else { OS_REG_WRITE(ah, AR9285_RF2G5, (reg_rf2g5_org & AR9285_RF2G5_IC50TX) | AR9285_RF2G5_IC50TX_SET); } retv = ar9285_hw_cl_cal(ah, chan); OS_REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org); } return retv; } HAL_BOOL ar9285InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan) { if (AR_SREV_KITE(ah) && AR_SREV_KITE_10_OR_LATER(ah) && (! ar9285_hw_clc(ah, chan))) return AH_FALSE; return AH_TRUE; } Index: head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c =================================================================== --- head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c (revision 221805) +++ head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c (revision 221806) @@ -1,807 +1,808 @@ /* * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting * Copyright (c) 2002-2008 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ /* * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and * supports only 2Ghz operation. */ #include "opt_ah.h" #include "ah.h" #include "ah_internal.h" #include "ah_devid.h" #include "ah_eeprom_v14.h" #include "ah_eeprom_v4k.h" #include "ar9002/ar9285.h" #include "ar5416/ar5416.h" #include "ar5416/ar5416reg.h" #include "ar5416/ar5416phy.h" #include "ar9002/ar9002phy.h" #include "ar9002/ar9285phy.h" +#include "ar9002/ar9285an.h" /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ #define EEP_MINOR(_ah) \ (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) /* Additional Time delay to wait after activiting the Base band */ #define BASE_ACTIVATE_DELAY 100 /* 100 usec */ #define PLL_SETTLE_DELAY 300 /* 300 usec */ #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, const struct ieee80211_channel *chan, int16_t *ratesArray, uint16_t cfgCtl, uint16_t AntennaReduction, uint16_t twiceMaxRegulatoryPower, uint16_t powerLimit); static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset); static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, uint8_t * bChans, uint16_t availPiers, uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, uint16_t numXpdGains); HAL_BOOL ar9285SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan, uint16_t *rfXpdGain) { #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) #define N(a) (sizeof (a) / sizeof (a[0])) MODAL_EEP4K_HEADER *pModal; struct ath_hal_5212 *ahp = AH5212(ah); int16_t ratesArray[Ar5416RateSize]; int16_t txPowerIndexOffset = 0; uint8_t ht40PowerIncForPdadc = 2; int i; uint16_t cfgCtl; uint16_t powerLimit; uint16_t twiceAntennaReduction; uint16_t twiceMaxRegulatoryPower; int16_t maxPower; HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; struct ar5416eeprom_4k *pEepData = &ee->ee_base; HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); /* Setup info for the actual eeprom */ OS_MEMZERO(ratesArray, sizeof(ratesArray)); cfgCtl = ath_hal_getctl(ah, chan); powerLimit = chan->ic_maxregpower * 2; twiceAntennaReduction = chan->ic_maxantgain; twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); pModal = &pEepData->modalHeader; HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", __func__,chan->ic_freq, cfgCtl ); if (IS_EEP_MINOR_V2(ah)) { ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; } if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, &ratesArray[0],cfgCtl, twiceAntennaReduction, twiceMaxRegulatoryPower, powerLimit)) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set tx power per rate table\n", __func__); return AH_FALSE; } if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", __func__); return AH_FALSE; } maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); maxPower = AH_MAX(maxPower, ratesArray[rate1l]); if (IEEE80211_IS_CHAN_HT40(chan)) { maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); } ahp->ah_tx6PowerInHalfDbm = maxPower; AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; ahp->ah_txPowerIndexOffset = txPowerIndexOffset; /* * txPowerIndexOffset is set by the SetPowerTable() call - * adjust the rate table (0 offset if rates EEPROM not loaded) */ for (i = 0; i < N(ratesArray); i++) { ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); /* -5 dBm offset for Merlin and later; this includes Kite */ ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; if (ratesArray[i] > AR5416_MAX_RATE_POWER) ratesArray[i] = AR5416_MAX_RATE_POWER; if (ratesArray[i] < 0) ratesArray[i] = 0; } #ifdef AH_EEPROM_DUMP ar5416PrintPowerPerRate(ah, ratesArray); #endif /* * Adjust the HT40 power to meet the correct target TX power * for 40MHz mode, based on TX power curves that are established * for 20MHz mode. * * XXX handle overflow/too high power level? */ if (IEEE80211_IS_CHAN_HT40(chan)) { ratesArray[rateHt40_0] += ht40PowerIncForPdadc; ratesArray[rateHt40_1] += ht40PowerIncForPdadc; ratesArray[rateHt40_2] += ht40PowerIncForPdadc; ratesArray[rateHt40_3] += ht40PowerIncForPdadc; ratesArray[rateHt40_4] += ht40PowerIncForPdadc; ratesArray[rateHt40_5] += ht40PowerIncForPdadc; ratesArray[rateHt40_6] += ht40PowerIncForPdadc; ratesArray[rateHt40_7] += ht40PowerIncForPdadc; } /* Write the TX power rate registers */ ar5416WriteTxPowerRateRegisters(ah, chan, ratesArray); return AH_TRUE; #undef POW_SM #undef N } static void ar9285SetBoardGain(struct ath_hal *ah, const MODAL_EEP4K_HEADER *pModal, const struct ar5416eeprom_4k *eep, uint8_t txRxAttenLocal) { OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, pModal->antCtrlChain[0]); OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)) & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_3) { txRxAttenLocal = pModal->txRxAttenCh[0]; OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); /* Set the block 1 value to block 0 value */ OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]); OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); } OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); } /* * Read EEPROM header info and program the device for correct operation * given the channel value. */ HAL_BOOL ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) { const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; const struct ar5416eeprom_4k *eep = &ee->ee_base; const MODAL_EEP4K_HEADER *pModal; uint8_t txRxAttenLocal; uint8_t ob[5], db1[5], db2[5]; pModal = &eep->modalHeader; txRxAttenLocal = 23; OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); /* Single chain for 4K EEPROM*/ ar9285SetBoardGain(ah, pModal, eep, txRxAttenLocal); /* Initialize Ant Diversity settings if supported */ (void) ar9285SetAntennaSwitch(ah, AH5212(ah)->ah_antControl); /* Configure TX power calibration */ if (pModal->version >= 2) { ob[0] = pModal->ob_0; ob[1] = pModal->ob_1; ob[2] = pModal->ob_2; ob[3] = pModal->ob_3; ob[4] = pModal->ob_4; db1[0] = pModal->db1_0; db1[1] = pModal->db1_1; db1[2] = pModal->db1_2; db1[3] = pModal->db1_3; db1[4] = pModal->db1_4; db2[0] = pModal->db2_0; db2[1] = pModal->db2_1; db2[2] = pModal->db2_2; db2[3] = pModal->db2_3; db2[4] = pModal->db2_4; } else if (pModal->version == 1) { ob[0] = pModal->ob_0; ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; db1[0] = pModal->db1_0; db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; db2[0] = pModal->db2_0; db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; } else { int i; for (i = 0; i < 5; i++) { ob[i] = pModal->ob_0; db1[i] = pModal->db1_0; db2[i] = pModal->db1_0; } } OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_0, ob[0]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_1, ob[1]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_2, ob[2]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_3, ob[3]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_OB_4, ob[4]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_0, db1[0]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_1, db1[1]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_DB1_2, db1[2]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_3, db1[3]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB1_4, db1[4]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_0, db2[0]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_1, db2[1]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_2, db2[2]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_3, db2[3]); OS_A_REG_RMW_FIELD(ah, AR9285_AN_RF2G4, AR9285_AN_RF2G4_DB2_4, db2[4]); OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); OS_REG_WRITE(ah, AR_PHY_RF_CTL4, SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, pModal->thresh62); OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62); if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_2) { OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart); OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn); } if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_3) { if (IEEE80211_IS_CHAN_HT40(chan)) OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); } /* * Program the CCK TX gain factor appropriately if needed. * The AR9285/AR9271 has a non-constant PA tx gain behaviour * for CCK versus OFDM rates; other chips deal with this * differently. * * The mask/shift/multiply hackery is done so place the same * value (bb_desired_scale) into multiple 5-bit fields. * For example, AR_PHY_TX_PWRCTRL9 has bb_desired_scale written * to three fields: (0..4), (5..9) and (10..14). */ if (AR_SREV_9271(ah) || AR_SREV_KITE(ah)) { uint8_t bb_desired_scale = (pModal->bb_scale_smrt_antenna & EEP_4K_BB_DESIRED_SCALE_MASK); if ((eep->baseEepHeader.txGainType == 0) && (bb_desired_scale != 0)) { ath_hal_printf(ah, "[ath]: adjusting cck tx gain factor\n"); uint32_t pwrctrl, mask, clr; mask = (1<<0) | (1<<5) | (1<<10) | (1<<15) | (1<<20) | (1<<25); pwrctrl = mask * bb_desired_scale; clr = mask * 0x1f; OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); mask = (1<<0) | (1<<5) | (1<<15); pwrctrl = mask * bb_desired_scale; clr = mask * 0x1f; OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); mask = (1<<0) | (1<<5); pwrctrl = mask * bb_desired_scale; clr = mask * 0x1f; OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); } } return AH_TRUE; } /* * Helper functions common for AP/CB/XB */ static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, const struct ieee80211_channel *chan, int16_t *ratesArray, uint16_t cfgCtl, uint16_t AntennaReduction, uint16_t twiceMaxRegulatoryPower, uint16_t powerLimit) { #define N(a) (sizeof(a)/sizeof(a[0])) /* Local defines to distinguish between extension and control CTL's */ #define EXT_ADDITIVE (0x8000) #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; int i; int16_t twiceLargestAntenna; CAL_CTL_DATA_4K *rep; CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; int16_t scaledPower, minCtlPower; #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ static const uint16_t ctlModesFor11g[] = { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 }; const uint16_t *pCtlMode; uint16_t numCtlModes, ctlMode, freq; CHAN_CENTERS centers; ar5416GetChannelCenters(ah, chan, ¢ers); /* Compute TxPower reduction due to Antenna Gain */ twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); /* XXX setup for 5212 use (really used?) */ ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna); /* * scaledPower is the minimum of the user input power level and * the regulatory allowed power level */ scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); /* Get target powers from EEPROM - our baseline for TX Power */ /* Setup for CTL modes */ numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ pCtlMode = ctlModesFor11g; ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); if (IEEE80211_IS_CHAN_HT40(chan)) { numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); /* Get target powers for extension channels */ ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); } /* * For MIMO, need to apply regulatory caps individually across dynamically * running modes: CCK, OFDM, HT20, HT40 * * The outer loop walks through each possible applicable runtime mode. * The inner loop walks through each ctlIndex entry in EEPROM. * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. * */ for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || (pCtlMode[ctlMode] == CTL_2GHT40); if (isHt40CtlMode) { freq = centers.ctl_center; } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { freq = centers.ext_center; } else { freq = centers.ctl_center; } /* walk through each CTL index stored in EEPROM */ for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { uint16_t twiceMinEdgePower; /* compare test group from regulatory channel list with test mode from pCtlMode list */ if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { rep = &(pEepData->ctlData[i]); twiceMinEdgePower = ar5416GetMaxEdgePower(freq, rep->ctlEdges[ owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], AH_TRUE); if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { /* Find the minimum of all CTL edge powers that apply to this channel */ twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); } else { /* specific */ twiceMaxEdgePower = twiceMinEdgePower; break; } } } minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); /* Apply ctl mode to correct target power set */ switch(pCtlMode[ctlMode]) { case CTL_11B: for (i = 0; i < N(targetPowerCck.tPow2x); i++) { targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); } break; case CTL_11A: case CTL_11G: for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); } break; case CTL_5GHT20: case CTL_2GHT20: for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); } break; case CTL_11B_EXT: targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); break; case CTL_11G_EXT: targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); break; case CTL_5GHT40: case CTL_2GHT40: for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); } break; default: return AH_FALSE; break; } } /* end ctl mode checking */ /* Set rates Array from collected data */ ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; } ratesArray[rate1l] = targetPowerCck.tPow2x[0]; ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; if (IEEE80211_IS_CHAN_HT40(chan)) { for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; } ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; if (IEEE80211_IS_CHAN_2GHZ(chan)) { ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; } } return AH_TRUE; #undef EXT_ADDITIVE #undef CTL_11G_EXT #undef CTL_11B_EXT #undef SUB_NUM_CTL_MODES_AT_2G_40 #undef N } static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData, const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) { CAL_DATA_PER_FREQ_4K *pRawDataset; uint8_t *pCalBChans = AH_NULL; uint16_t pdGainOverlap_t2; static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; uint16_t numPiers, i; int16_t tMinCalPower; uint16_t numXpdGain, xpdMask; uint16_t xpdGainValues[4]; /* v4k eeprom has 2; the other two stay 0 */ uint32_t regChainOffset; OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); xpdMask = pEepData->modalHeader.xpdGain; if (IS_EEP_MINOR_V2(ah)) { pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; } else { pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); } pCalBChans = pEepData->calFreqPier2G; numPiers = AR5416_4K_NUM_2G_CAL_PIERS; numXpdGain = 0; /* Calculate the value of xpdgains from the xpdGain Mask */ for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) { HALASSERT(0); break; } xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); numXpdGain++; } } /* Write the detector gain biases and their number */ ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); for (i = 0; i < AR5416_MAX_CHAINS; i++) { regChainOffset = ar5416GetRegChainOffset(ah, i); if (pEepData->baseEepHeader.txMask & (1 << i)) { pRawDataset = pEepData->calPierData2G[i]; ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, pCalBChans, numPiers, pdGainOverlap_t2, &tMinCalPower, gainBoundaries, pdadcValues, numXpdGain); if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { /* * Note the pdadc table may not start at 0 dBm power, could be * negative or greater than 0. Need to offset the power * values by the amount of minPower for griffin */ ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, gainBoundaries); } /* Write the power values into the baseband power table */ ar5416WritePdadcValues(ah, i, pdadcValues); } } *pTxPowerIndexOffset = 0; return AH_TRUE; } static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah, const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet, uint8_t * bChans, uint16_t availPiers, uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, uint16_t numXpdGains) { int i, j, k; int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ uint16_t idxL, idxR, numPiers; /* Pier indexes */ /* filled out Vpd table for all pdGains (chanL) */ static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; /* filled out Vpd table for all pdGains (chanR) */ static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; /* filled out Vpd table for all pdGains (interpolated) */ static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS]; uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS]; int16_t vpdStep; int16_t tmpVal; uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; HAL_BOOL match; int16_t minDelta = 0; CHAN_CENTERS centers; ar5416GetChannelCenters(ah, chan, ¢ers); /* Trim numPiers for the number of populated channel Piers */ for (numPiers = 0; numPiers < availPiers; numPiers++) { if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { break; } } /* Find pier indexes around the current channel */ match = ath_ee_getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), bChans, numPiers, &idxL, &idxR); if (match) { /* Directly fill both vpd tables from the matching index */ for (i = 0; i < numXpdGains; i++) { minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i], pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); } } else { for (i = 0; i < numXpdGains; i++) { pVpdL = pRawDataSet[idxL].vpdPdg[i]; pPwrL = pRawDataSet[idxL].pwrPdg[i]; pVpdR = pRawDataSet[idxR].vpdPdg[i]; pPwrR = pRawDataSet[idxR].pwrPdg[i]; /* Start Vpd interpolation from the max of the minimum powers */ minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); /* End Vpd interpolation from the min of the max powers */ maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); HALASSERT(maxPwrT4[i] > minPwrT4[i]); /* Fill pier Vpds */ ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); ath_ee_FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); /* Interpolate the final vpd */ for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { vpdTableI[i][j] = (uint8_t)(ath_ee_interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); } } } *pMinCalPower = (int16_t)(minPwrT4[0] / 2); k = 0; /* index for the final table */ for (i = 0; i < numXpdGains; i++) { if (i == (numXpdGains - 1)) { pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); } else { pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); } pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); /* NB: only applies to owl 1.0 */ if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { /* * fix the gain delta, but get a delta that can be applied to min to * keep the upper power values accurate, don't think max needs to * be adjusted because should not be at that area of the table? */ minDelta = pPdGainBoundaries[0] - 23; pPdGainBoundaries[0] = 23; } else { minDelta = 0; } /* Find starting index for this pdGain */ if (i == 0) { if (AR_SREV_MERLIN_20_OR_LATER(ah)) ss = (int16_t)(0 - (minPwrT4[i] / 2)); else ss = 0; /* for the first pdGain, start from index 0 */ } else { /* need overlap entries extrapolated below. */ ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); } vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); /* *-ve ss indicates need to extrapolate data below for this pdGain */ while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); ss++; } sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { pPDADCValues[k++] = vpdTableI[i][ss++]; } vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); /* * for last gain, pdGainBoundary == Pmax_t2, so will * have to extrapolate */ if (tgtIndex >= maxIndex) { /* need to extrapolate above */ while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex +1) * vpdStep)); pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); ss++; } } /* extrapolated above */ } /* for all pdGainUsed */ /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ while (i < AR5416_PD_GAINS_IN_MASK) { pPdGainBoundaries[i] = AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT; i++; } while (k < AR5416_NUM_PDADC_VALUES) { pPDADCValues[k] = pPDADCValues[k-1]; k++; } return; } Index: head/sys/dev/ath/ath_hal/ar9002/ar9285an.h =================================================================== --- head/sys/dev/ath/ath_hal/ar9002/ar9285an.h (nonexistent) +++ head/sys/dev/ath/ath_hal/ar9002/ar9285an.h (revision 221806) @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting + * Copyright (c) 2008 Atheros Communications, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD$ + */ + +#ifndef __AR9285_AN_H__ +#define __AR9285_AN_H__ + +/* AR9285 Analog register definitions */ + +#define AR9285_AN_RF2G1 0x7820 + +#define AR9285_AN_RF2G1_ENPACAL 0x00000800 +#define AR9285_AN_RF2G1_ENPACAL_S 11 +#define AR9285_AN_RF2G1_PDPADRV1 0x02000000 +#define AR9285_AN_RF2G1_PDPADRV1_S 25 +#define AR9285_AN_RF2G1_PDPADRV2 0x01000000 +#define AR9285_AN_RF2G1_PDPADRV2_S 24 +#define AR9285_AN_RF2G1_PDPAOUT 0x00800000 +#define AR9285_AN_RF2G1_PDPAOUT_S 23 + +#define AR9285_AN_RF2G2 0x7824 + +#define AR9285_AN_RF2G2_OFFCAL 0x00001000 +#define AR9285_AN_RF2G2_OFFCAL_S 12 + +#define AR9285_AN_RF2G3 0x7828 + +#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 +#define AR9285_AN_RF2G3_PDVCCOMP_S 25 +#define AR9285_AN_RF2G3_OB_0 0x00E00000 +#define AR9285_AN_RF2G3_OB_0_S 21 +#define AR9285_AN_RF2G3_OB_1 0x001C0000 +#define AR9285_AN_RF2G3_OB_1_S 18 +#define AR9285_AN_RF2G3_OB_2 0x00038000 +#define AR9285_AN_RF2G3_OB_2_S 15 +#define AR9285_AN_RF2G3_OB_3 0x00007000 +#define AR9285_AN_RF2G3_OB_3_S 12 +#define AR9285_AN_RF2G3_OB_4 0x00000E00 +#define AR9285_AN_RF2G3_OB_4_S 9 +#define AR9285_AN_RF2G3_DB1_0 0x000001C0 +#define AR9285_AN_RF2G3_DB1_0_S 6 +#define AR9285_AN_RF2G3_DB1_1 0x00000038 +#define AR9285_AN_RF2G3_DB1_1_S 3 +#define AR9285_AN_RF2G3_DB1_2 0x00000007 +#define AR9285_AN_RF2G3_DB1_2_S 0 + +#define AR9285_AN_RF2G4 0x782C + +#define AR9285_AN_RF2G4_DB1_3 0xE0000000 +#define AR9285_AN_RF2G4_DB1_3_S 29 +#define AR9285_AN_RF2G4_DB1_4 0x1C000000 +#define AR9285_AN_RF2G4_DB1_4_S 26 + +#define AR9285_AN_RF2G4_DB2_0 0x03800000 +#define AR9285_AN_RF2G4_DB2_0_S 23 +#define AR9285_AN_RF2G4_DB2_1 0x00700000 +#define AR9285_AN_RF2G4_DB2_1_S 20 +#define AR9285_AN_RF2G4_DB2_2 0x000E0000 +#define AR9285_AN_RF2G4_DB2_2_S 17 +#define AR9285_AN_RF2G4_DB2_3 0x0001C000 +#define AR9285_AN_RF2G4_DB2_3_S 14 +#define AR9285_AN_RF2G4_DB2_4 0x00003800 +#define AR9285_AN_RF2G4_DB2_4_S 11 + +#define AR9285_AN_RF2G6 0x7834 + +#define AR9285_AN_RF2G6_CCOMP 0x00007800 +#define AR9285_AN_RF2G6_CCOMP_S 11 +#define AR9285_AN_RF2G6_OFFS 0x03f00000 +#define AR9285_AN_RF2G6_OFFS_S 20 + +#define AR9285_AN_RF2G7 0x7838 + +#define AR9285_AN_RF2G7_PWDDB 0x00000002 +#define AR9285_AN_RF2G7_PWDDB_S 1 +#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 +#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 + +#define AR9285_AN_RF2G8 0x783C + +#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 +#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 + +#define AR9285_AN_RF2G9 0x7840 + +#define AR9285_AN_RXTXBB1 0x7854 + +#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 +#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 +#define AR9285_AN_RXTXBB1_PDV2I 0x00000080 +#define AR9285_AN_RXTXBB1_PDV2I_S 7 +#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 +#define AR9285_AN_RXTXBB1_PDDACIF_S 8 +#define AR9285_AN_RXTXBB1_SPARE9 0x00000001 +#define AR9285_AN_RXTXBB1_SPARE9_S 0 + +#define AR9285_AN_TOP2 0x7868 + +#define AR9285_AN_TOP3 0x786c + +#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C +#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 +#define AR9285_AN_TOP3_PWDDAC 0x00800000 +#define AR9285_AN_TOP3_PWDDAC_S 23 + +#define AR9285_AN_TOP4 0x7870 +#define AR9285_AN_TOP4_DEFAULT 0x10142c00 + +#endif /* __AR9285_AN_H__ */ Property changes on: head/sys/dev/ath/ath_hal/ar9002/ar9285an.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property