Index: stable/7/sys/cddl/contrib/opensolaris =================================================================== --- stable/7/sys/cddl/contrib/opensolaris (revision 220340) +++ stable/7/sys/cddl/contrib/opensolaris (revision 220341) Property changes on: stable/7/sys/cddl/contrib/opensolaris ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/cddl/contrib/opensolaris:r219945-219946,220009 Index: stable/7/sys/contrib/dev/acpica =================================================================== --- stable/7/sys/contrib/dev/acpica (revision 220340) +++ stable/7/sys/contrib/dev/acpica (revision 220341) Property changes on: stable/7/sys/contrib/dev/acpica ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/contrib/dev/acpica:r219945-219946,220009 Index: stable/7/sys/contrib/pf =================================================================== --- stable/7/sys/contrib/pf (revision 220340) +++ stable/7/sys/contrib/pf (revision 220341) Property changes on: stable/7/sys/contrib/pf ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys/contrib/pf:r219945-219946,220009 Index: stable/7/sys/dev/cxgb/common/cxgb_common.h =================================================================== --- stable/7/sys/dev/cxgb/common/cxgb_common.h (revision 220340) +++ stable/7/sys/dev/cxgb/common/cxgb_common.h (revision 220341) @@ -1,874 +1,874 @@ /************************************************************************** Copyright (c) 2007-2009, Chelsio Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Neither the name of the Chelsio Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. $FreeBSD$ ***************************************************************************/ #ifndef __CHELSIO_COMMON_H #define __CHELSIO_COMMON_H #ifdef CONFIG_DEFINED #include #else #include #endif enum { MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ EEPROMSIZE = 8192, /* Serial EEPROM size */ SERNUM_LEN = 16, /* Serial # length */ ECNUM_LEN = 16, /* EC # length */ RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ TCB_SIZE = 128, /* TCB size */ NMTUS = 16, /* size of MTU table */ NCCTRL_WIN = 32, /* # of congestion control windows */ NTX_SCHED = 8, /* # of HW Tx scheduling queues */ PROTO_SRAM_LINES = 128, /* size of protocol sram */ EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ }; #define MAX_RX_COALESCING_LEN 12288U enum { PAUSE_RX = 1 << 0, PAUSE_TX = 1 << 1, PAUSE_AUTONEG = 1 << 2 }; enum { SUPPORTED_LINK_IRQ = 1 << 24, /* skip 25 */ SUPPORTED_MISC_IRQ = 1 << 26, SUPPORTED_IRQ = (SUPPORTED_LINK_IRQ | SUPPORTED_MISC_IRQ), }; enum { /* adapter interrupt-maintained statistics */ STAT_ULP_CH0_PBL_OOB, STAT_ULP_CH1_PBL_OOB, STAT_PCI_CORR_ECC, IRQ_NUM_STATS /* keep last */ }; enum { TP_VERSION_MAJOR = 1, TP_VERSION_MINOR = 1, TP_VERSION_MICRO = 0 }; #define S_TP_VERSION_MAJOR 16 #define M_TP_VERSION_MAJOR 0xFF #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) #define G_TP_VERSION_MAJOR(x) \ (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) #define S_TP_VERSION_MINOR 8 #define M_TP_VERSION_MINOR 0xFF #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) #define G_TP_VERSION_MINOR(x) \ (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) #define S_TP_VERSION_MICRO 0 #define M_TP_VERSION_MICRO 0xFF #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) #define G_TP_VERSION_MICRO(x) \ (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) enum { FW_VERSION_MAJOR = 7, - FW_VERSION_MINOR = 8, + FW_VERSION_MINOR = 11, FW_VERSION_MICRO = 0 }; enum { LA_CTRL = 0x80, LA_DATA = 0x84, LA_ENTRIES = 512 }; enum { IOQ_ENTRIES = 7 }; enum { SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ }; enum sge_context_type { /* SGE egress context types */ SGE_CNTXT_RDMA = 0, SGE_CNTXT_ETH = 2, SGE_CNTXT_OFLD = 4, SGE_CNTXT_CTRL = 5 }; enum { AN_PKT_SIZE = 32, /* async notification packet size */ IMMED_PKT_SIZE = 48 /* packet size for immediate data */ }; struct sg_ent { /* SGE scatter/gather entry */ __be32 len[2]; __be64 addr[2]; }; #ifndef SGE_NUM_GENBITS /* Must be 1 or 2 */ # define SGE_NUM_GENBITS 2 #endif #define TX_DESC_FLITS 16U #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) #define MAX_PHYINTRS 4 struct cphy; struct mdio_ops { int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *val); int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val); }; struct adapter_info { unsigned char nports0; /* # of ports on channel 0 */ unsigned char nports1; /* # of ports on channel 1 */ unsigned char phy_base_addr; /* MDIO PHY base address */ unsigned int gpio_out; /* GPIO output settings */ unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */ unsigned long caps; /* adapter capabilities */ const struct mdio_ops *mdio_ops; /* MDIO operations */ const char *desc; /* product description */ }; struct mc5_stats { unsigned long parity_err; unsigned long active_rgn_full; unsigned long nfa_srch_err; unsigned long unknown_cmd; unsigned long reqq_parity_err; unsigned long dispq_parity_err; unsigned long del_act_empty; }; struct mc7_stats { unsigned long corr_err; unsigned long uncorr_err; unsigned long parity_err; unsigned long addr_err; }; struct mac_stats { u64 tx_octets; /* total # of octets in good frames */ u64 tx_octets_bad; /* total # of octets in error frames */ u64 tx_frames; /* all good frames */ u64 tx_mcast_frames; /* good multicast frames */ u64 tx_bcast_frames; /* good broadcast frames */ u64 tx_pause; /* # of transmitted pause frames */ u64 tx_deferred; /* frames with deferred transmissions */ u64 tx_late_collisions; /* # of late collisions */ u64 tx_total_collisions; /* # of total collisions */ u64 tx_excess_collisions; /* frame errors from excessive collissions */ u64 tx_underrun; /* # of Tx FIFO underruns */ u64 tx_len_errs; /* # of Tx length errors */ u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ u64 tx_excess_deferral; /* # of frames with excessive deferral */ u64 tx_fcs_errs; /* # of frames with bad FCS */ u64 tx_frames_64; /* # of Tx frames in a particular range */ u64 tx_frames_65_127; u64 tx_frames_128_255; u64 tx_frames_256_511; u64 tx_frames_512_1023; u64 tx_frames_1024_1518; u64 tx_frames_1519_max; u64 rx_octets; /* total # of octets in good frames */ u64 rx_octets_bad; /* total # of octets in error frames */ u64 rx_frames; /* all good frames */ u64 rx_mcast_frames; /* good multicast frames */ u64 rx_bcast_frames; /* good broadcast frames */ u64 rx_pause; /* # of received pause frames */ u64 rx_fcs_errs; /* # of received frames with bad FCS */ u64 rx_align_errs; /* alignment errors */ u64 rx_symbol_errs; /* symbol errors */ u64 rx_data_errs; /* data errors */ u64 rx_sequence_errs; /* sequence errors */ u64 rx_runt; /* # of runt frames */ u64 rx_jabber; /* # of jabber frames */ u64 rx_short; /* # of short frames */ u64 rx_too_long; /* # of oversized frames */ u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ u64 rx_frames_64; /* # of Rx frames in a particular range */ u64 rx_frames_65_127; u64 rx_frames_128_255; u64 rx_frames_256_511; u64 rx_frames_512_1023; u64 rx_frames_1024_1518; u64 rx_frames_1519_max; u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ unsigned long tx_fifo_parity_err; unsigned long rx_fifo_parity_err; unsigned long tx_fifo_urun; unsigned long rx_fifo_ovfl; unsigned long serdes_signal_loss; unsigned long xaui_pcs_ctc_err; unsigned long xaui_pcs_align_change; unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ unsigned long num_resets; /* # times reset due to stuck TX */ unsigned long link_faults; /* # detected link faults */ }; struct tp_mib_stats { u32 ipInReceive_hi; u32 ipInReceive_lo; u32 ipInHdrErrors_hi; u32 ipInHdrErrors_lo; u32 ipInAddrErrors_hi; u32 ipInAddrErrors_lo; u32 ipInUnknownProtos_hi; u32 ipInUnknownProtos_lo; u32 ipInDiscards_hi; u32 ipInDiscards_lo; u32 ipInDelivers_hi; u32 ipInDelivers_lo; u32 ipOutRequests_hi; u32 ipOutRequests_lo; u32 ipOutDiscards_hi; u32 ipOutDiscards_lo; u32 ipOutNoRoutes_hi; u32 ipOutNoRoutes_lo; u32 ipReasmTimeout; u32 ipReasmReqds; u32 ipReasmOKs; u32 ipReasmFails; u32 reserved[8]; u32 tcpActiveOpens; u32 tcpPassiveOpens; u32 tcpAttemptFails; u32 tcpEstabResets; u32 tcpOutRsts; u32 tcpCurrEstab; u32 tcpInSegs_hi; u32 tcpInSegs_lo; u32 tcpOutSegs_hi; u32 tcpOutSegs_lo; u32 tcpRetransSeg_hi; u32 tcpRetransSeg_lo; u32 tcpInErrs_hi; u32 tcpInErrs_lo; u32 tcpRtoMin; u32 tcpRtoMax; }; struct tp_params { unsigned int nchan; /* # of channels */ unsigned int pmrx_size; /* total PMRX capacity */ unsigned int pmtx_size; /* total PMTX capacity */ unsigned int cm_size; /* total CM capacity */ unsigned int chan_rx_size; /* per channel Rx size */ unsigned int chan_tx_size; /* per channel Tx size */ unsigned int rx_pg_size; /* Rx page size */ unsigned int tx_pg_size; /* Tx page size */ unsigned int rx_num_pgs; /* # of Rx pages */ unsigned int tx_num_pgs; /* # of Tx pages */ unsigned int ntimer_qs; /* # of timer queues */ unsigned int tre; /* log2 of core clocks per TP tick */ unsigned int dack_re; /* DACK timer resolution */ }; struct qset_params { /* SGE queue set parameters */ unsigned int polling; /* polling/interrupt service for rspq */ unsigned int lro; /* large receive offload */ unsigned int coalesce_usecs; /* irq coalescing timer */ unsigned int rspq_size; /* # of entries in response queue */ unsigned int fl_size; /* # of entries in regular free list */ unsigned int jumbo_size; /* # of entries in jumbo free list */ unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ unsigned int cong_thres; /* FL congestion threshold */ unsigned int vector; /* Interrupt (line or vector) number */ }; struct sge_params { unsigned int max_pkt_size; /* max offload pkt size */ struct qset_params qset[SGE_QSETS]; }; struct mc5_params { unsigned int mode; /* selects MC5 width */ unsigned int nservers; /* size of server region */ unsigned int nfilters; /* size of filter region */ unsigned int nroutes; /* size of routing region */ }; /* Default MC5 region sizes */ enum { DEFAULT_NSERVERS = 512, DEFAULT_NFILTERS = 128 }; /* MC5 modes, these must be non-0 */ enum { MC5_MODE_144_BIT = 1, MC5_MODE_72_BIT = 2 }; /* MC5 min active region size */ enum { MC5_MIN_TIDS = 16 }; struct vpd_params { unsigned int cclk; unsigned int mclk; unsigned int uclk; unsigned int mdc; unsigned int mem_timing; u8 sn[SERNUM_LEN + 1]; u8 ec[ECNUM_LEN + 1]; u8 eth_base[6]; u8 port_type[MAX_NPORTS]; unsigned short xauicfg[2]; }; struct generic_vpd { u32 offset; u32 len; u8 *data; }; enum { MAX_VPD_BYTES = 32000 }; struct pci_params { unsigned int vpd_cap_addr; unsigned int pcie_cap_addr; unsigned short speed; unsigned char width; unsigned char variant; }; enum { PCI_VARIANT_PCI, PCI_VARIANT_PCIX_MODE1_PARITY, PCI_VARIANT_PCIX_MODE1_ECC, PCI_VARIANT_PCIX_266_MODE2, PCI_VARIANT_PCIE }; struct adapter_params { struct sge_params sge; struct mc5_params mc5; struct tp_params tp; struct vpd_params vpd; struct pci_params pci; const struct adapter_info *info; #ifdef CONFIG_CHELSIO_T3_CORE unsigned short mtus[NMTUS]; unsigned short a_wnd[NCCTRL_WIN]; unsigned short b_wnd[NCCTRL_WIN]; #endif unsigned int nports; /* # of ethernet ports */ unsigned int chan_map; /* bitmap of in-use Tx channels */ unsigned int stats_update_period; /* MAC stats accumulation period */ unsigned int linkpoll_period; /* link poll period in 0.1s */ unsigned int rev; /* chip revision */ unsigned int offload; }; enum { /* chip revisions */ T3_REV_A = 0, T3_REV_B = 2, T3_REV_B2 = 3, T3_REV_C = 4, }; struct trace_params { u32 sip; u32 sip_mask; u32 dip; u32 dip_mask; u16 sport; u16 sport_mask; u16 dport; u16 dport_mask; u32 vlan:12; u32 vlan_mask:12; u32 intf:4; u32 intf_mask:4; u8 proto; u8 proto_mask; }; struct link_config { unsigned int supported; /* link capabilities */ unsigned int advertising; /* advertised capabilities */ unsigned short requested_speed; /* speed user has requested */ unsigned short speed; /* actual link speed */ unsigned char requested_duplex; /* duplex user has requested */ unsigned char duplex; /* actual link duplex */ unsigned char requested_fc; /* flow control user has requested */ unsigned char fc; /* actual link flow control */ unsigned char autoneg; /* autonegotiating? */ unsigned int link_ok; /* link up? */ }; #define SPEED_INVALID 0xffff #define DUPLEX_INVALID 0xff struct mc5 { adapter_t *adapter; unsigned int tcam_size; unsigned char part_type; unsigned char parity_enabled; unsigned char mode; struct mc5_stats stats; }; static inline unsigned int t3_mc5_size(const struct mc5 *p) { return p->tcam_size; } struct mc7 { adapter_t *adapter; /* backpointer to adapter */ unsigned int size; /* memory size in bytes */ unsigned int width; /* MC7 interface width */ unsigned int offset; /* register address offset for MC7 instance */ const char *name; /* name of MC7 instance */ struct mc7_stats stats; /* MC7 statistics */ }; static inline unsigned int t3_mc7_size(const struct mc7 *p) { return p->size; } struct cmac { adapter_t *adapter; unsigned int offset; unsigned char nucast; /* # of address filters for unicast MACs */ unsigned char multiport; /* multiple ports connected to this MAC */ unsigned char ext_port; /* external MAC port */ unsigned char promisc_map; /* which external ports are promiscuous */ unsigned int tx_tcnt; unsigned int tx_xcnt; u64 tx_mcnt; unsigned int rx_xcnt; unsigned int rx_ocnt; u64 rx_mcnt; unsigned int toggle_cnt; unsigned int txen; unsigned int was_reset; u64 rx_pause; struct mac_stats stats; }; enum { MAC_DIRECTION_RX = 1, MAC_DIRECTION_TX = 2, MAC_RXFIFO_SIZE = 32768 }; /* IEEE 802.3 specified MDIO devices */ enum { MDIO_DEV_PMA_PMD = 1, MDIO_DEV_WIS = 2, MDIO_DEV_PCS = 3, MDIO_DEV_XGXS = 4, MDIO_DEV_ANEG = 7, MDIO_DEV_VEND1 = 30, MDIO_DEV_VEND2 = 31 }; /* LASI control and status registers */ enum { RX_ALARM_CTRL = 0x9000, TX_ALARM_CTRL = 0x9001, LASI_CTRL = 0x9002, RX_ALARM_STAT = 0x9003, TX_ALARM_STAT = 0x9004, LASI_STAT = 0x9005 }; /* PHY loopback direction */ enum { PHY_LOOPBACK_TX = 1, PHY_LOOPBACK_RX = 2 }; /* PHY interrupt types */ enum { cphy_cause_link_change = 1, cphy_cause_fifo_error = 2, cphy_cause_module_change = 4, cphy_cause_alarm = 8, }; /* PHY module types */ enum { phy_modtype_none, phy_modtype_sr, phy_modtype_lr, phy_modtype_lrm, phy_modtype_twinax, phy_modtype_twinax_long, phy_modtype_unknown }; /* PHY operations */ struct cphy_ops { int (*reset)(struct cphy *phy, int wait); int (*intr_enable)(struct cphy *phy); int (*intr_disable)(struct cphy *phy); int (*intr_clear)(struct cphy *phy); int (*intr_handler)(struct cphy *phy); int (*autoneg_enable)(struct cphy *phy); int (*autoneg_restart)(struct cphy *phy); int (*advertise)(struct cphy *phy, unsigned int advertise_map); int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, int *duplex, int *fc); int (*power_down)(struct cphy *phy, int enable); }; /* A PHY instance */ struct cphy { u8 addr; /* PHY address */ u8 modtype; /* PHY module type */ unsigned int priv; /* scratch pad */ unsigned int caps; /* PHY capabilities */ adapter_t *adapter; /* associated adapter */ pinfo_t *pinfo; /* associated port */ const char *desc; /* PHY description */ unsigned long fifo_errors; /* FIFO over/under-flows */ const struct cphy_ops *ops; /* PHY operations */ int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *val); int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val); }; /* Convenience MDIO read/write wrappers */ static inline int mdio_read(struct cphy *phy, int mmd, int reg, unsigned int *valp) { return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); } static inline int mdio_write(struct cphy *phy, int mmd, int reg, unsigned int val) { return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); } /* Convenience initializer */ static inline void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo, int phy_addr, struct cphy_ops *phy_ops, const struct mdio_ops *mdio_ops, unsigned int caps, const char *desc) { phy->addr = (u8)phy_addr; phy->caps = caps; phy->adapter = adapter; phy->pinfo = pinfo; phy->desc = desc; phy->ops = phy_ops; if (mdio_ops) { phy->mdio_read = mdio_ops->read; phy->mdio_write = mdio_ops->write; } } /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ #define MAC_STATS_ACCUM_SECS 180 /* The external MAC needs accumulation every 30 seconds */ #define VSC_STATS_ACCUM_SECS 30 #define XGM_REG(reg_addr, idx) \ ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) struct addr_val_pair { unsigned int reg_addr; unsigned int val; }; #ifdef CONFIG_DEFINED #include #else #include #endif #ifndef PCI_VENDOR_ID_CHELSIO # define PCI_VENDOR_ID_CHELSIO 0x1425 #endif #define for_each_port(adapter, iter) \ for (iter = 0; iter < (adapter)->params.nports; ++iter) #define adapter_info(adap) ((adap)->params.info) static inline int uses_xaui(const adapter_t *adap) { return adapter_info(adap)->caps & SUPPORTED_AUI; } static inline int is_10G(const adapter_t *adap) { return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; } static inline int is_offload(const adapter_t *adap) { #if defined(CONFIG_CHELSIO_T3_CORE) return adap->params.offload; #else return 0; #endif } static inline unsigned int core_ticks_per_usec(const adapter_t *adap) { return adap->params.vpd.cclk / 1000; } static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, unsigned int ticks) { return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); } static inline unsigned int is_pcie(const adapter_t *adap) { return adap->params.pci.variant == PCI_VARIANT_PCIE; } void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, unsigned int offset); int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, int attempts, int delay, u32 *valp); static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, int attempts, int delay) { return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, delay, NULL); } int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, unsigned int set); int t3_phy_reset(struct cphy *phy, int mmd, int wait); int t3_phy_advertise(struct cphy *phy, unsigned int advert); int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); int t3_phy_lasi_intr_enable(struct cphy *phy); int t3_phy_lasi_intr_disable(struct cphy *phy); int t3_phy_lasi_intr_clear(struct cphy *phy); int t3_phy_lasi_intr_handler(struct cphy *phy); void t3_intr_enable(adapter_t *adapter); void t3_intr_disable(adapter_t *adapter); void t3_intr_clear(adapter_t *adapter); void t3_xgm_intr_enable(adapter_t *adapter, int idx); void t3_xgm_intr_disable(adapter_t *adapter, int idx); void t3_port_intr_enable(adapter_t *adapter, int idx); void t3_port_intr_disable(adapter_t *adapter, int idx); void t3_port_intr_clear(adapter_t *adapter, int idx); int t3_slow_intr_handler(adapter_t *adapter); void t3_link_changed(adapter_t *adapter, int port_id); int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); const struct adapter_info *t3_get_adapter_info(unsigned int board_id); int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); int t3_seeprom_wp(adapter_t *adapter, int enable); int t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd); int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd); int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented); int t3_get_tp_version(adapter_t *adapter, u32 *vers); int t3_check_tpsram_version(adapter_t *adapter); int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); int t3_get_fw_version(adapter_t *adapter, u32 *vers); int t3_check_fw_version(adapter_t *adapter); int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); int t3_init_hw(adapter_t *adapter, u32 fw_params); void mac_prep(struct cmac *mac, adapter_t *adapter, int index); void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); int t3_reset_adapter(adapter_t *adapter); int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); int t3_reinit_adapter(adapter_t *adap); void t3_led_ready(adapter_t *adapter); void t3_fatal_err(adapter_t *adapter); void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); void t3_enable_filters(adapter_t *adap); void t3_disable_filters(adapter_t *adap); void t3_tp_set_offload_mode(adapter_t *adap, int enable); void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, const u16 *rspq); int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); int t3_set_proto_sram(adapter_t *adap, const u8 *data); int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); void t3_port_failover(adapter_t *adapter, int port); void t3_failover_done(adapter_t *adapter, int port); void t3_failover_clear(adapter_t *adapter); int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, unsigned int *valp); int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, u64 *buf); int t3_mac_init(struct cmac *mac); void t3b_pcs_reset(struct cmac *mac); void t3c_pcs_force_los(struct cmac *mac); void t3_mac_disable_exact_filters(struct cmac *mac); void t3_mac_enable_exact_filters(struct cmac *mac); int t3_mac_enable(struct cmac *mac, int which); int t3_mac_disable(struct cmac *mac, int which); int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); const struct mac_stats *t3_mac_update_stats(struct cmac *mac); int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); int t3b2_mac_watchdog_task(struct cmac *mac); void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, unsigned int nroutes); void t3_mc5_intr_handler(struct mc5 *mc5); int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, u32 *buf); #ifdef CONFIG_CHELSIO_T3_CORE int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], unsigned short alpha[NCCTRL_WIN], unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); void t3_get_cong_cntl_tab(adapter_t *adap, unsigned short incr[NMTUS][NCCTRL_WIN]); void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, int filter_index, int invert, int enable); void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, int filter_index, int *inverted, int *enabled); int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, unsigned int *ipg); void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, unsigned int start, unsigned int n); #endif int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, u32 *size, void *data); int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data); void t3_sge_prep(adapter_t *adap, struct sge_params *p); void t3_sge_init(adapter_t *adap, struct sge_params *p); int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, enum sge_context_type type, int respq, u64 base_addr, unsigned int size, unsigned int token, int gen, unsigned int cidx); int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, u64 base_addr, unsigned int size, unsigned int esize, unsigned int cong_thres, int gen, unsigned int cidx); int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, u64 base_addr, unsigned int size, unsigned int fl_thres, int gen, unsigned int cidx); int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, unsigned int size, int rspq, int ovfl_mode, unsigned int credits, unsigned int credit_thres); int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, unsigned int credits); int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); int t3_vsc7323_init(adapter_t *adap, int nports); int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); int t3_vsc7323_enable(adapter_t *adap, int port, int which); int t3_vsc7323_disable(adapter_t *adap, int port, int which); const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); int t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp); int t3_i2c_write8(adapter_t *adapter, int chained, u8 val); int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *valp); int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val); int t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port); int t3_ael1002_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_ael1006_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_ael2005_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_ael2020_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_qt2045_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_xaui_direct_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); int t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops); #endif /* __CHELSIO_COMMON_H */ Index: stable/7/sys/dev/cxgb/common/cxgb_t3_hw.c =================================================================== --- stable/7/sys/dev/cxgb/common/cxgb_t3_hw.c (revision 220340) +++ stable/7/sys/dev/cxgb/common/cxgb_t3_hw.c (revision 220341) @@ -1,4801 +1,4802 @@ /************************************************************************** Copyright (c) 2007-2009, Chelsio Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Neither the name of the Chelsio Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ***************************************************************************/ #include __FBSDID("$FreeBSD$"); #ifdef CONFIG_DEFINED #include #else #include #endif #undef msleep #define msleep t3_os_sleep /** * t3_wait_op_done_val - wait until an operation is completed * @adapter: the adapter performing the operation * @reg: the register to check for completion * @mask: a single-bit field within @reg that indicates completion * @polarity: the value of the field when the operation is completed * @attempts: number of check iterations * @delay: delay in usecs between iterations * @valp: where to store the value of the register at completion time * * Wait until an operation is completed by checking a bit in a register * up to @attempts times. If @valp is not NULL the value of the register * at the time it indicated completion is stored there. Returns 0 if the * operation completes and -EAGAIN otherwise. */ int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, int attempts, int delay, u32 *valp) { while (1) { u32 val = t3_read_reg(adapter, reg); if (!!(val & mask) == polarity) { if (valp) *valp = val; return 0; } if (--attempts == 0) return -EAGAIN; if (delay) udelay(delay); } } /** * t3_write_regs - write a bunch of registers * @adapter: the adapter to program * @p: an array of register address/register value pairs * @n: the number of address/value pairs * @offset: register address offset * * Takes an array of register address/register value pairs and writes each * value to the corresponding register. Register addresses are adjusted * by the supplied offset. */ void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, unsigned int offset) { while (n--) { t3_write_reg(adapter, p->reg_addr + offset, p->val); p++; } } /** * t3_set_reg_field - set a register field to a value * @adapter: the adapter to program * @addr: the register address * @mask: specifies the portion of the register to modify * @val: the new value for the register field * * Sets a register field specified by the supplied mask to the * given value. */ void t3_set_reg_field(adapter_t *adapter, unsigned int addr, u32 mask, u32 val) { u32 v = t3_read_reg(adapter, addr) & ~mask; t3_write_reg(adapter, addr, v | val); (void) t3_read_reg(adapter, addr); /* flush */ } /** * t3_read_indirect - read indirectly addressed registers * @adap: the adapter * @addr_reg: register holding the indirect address * @data_reg: register holding the value of the indirect register * @vals: where the read register values are stored * @start_idx: index of first indirect register to read * @nregs: how many indirect registers to read * * Reads registers that are accessed indirectly through an address/data * register pair. */ static void t3_read_indirect(adapter_t *adap, unsigned int addr_reg, unsigned int data_reg, u32 *vals, unsigned int nregs, unsigned int start_idx) { while (nregs--) { t3_write_reg(adap, addr_reg, start_idx); *vals++ = t3_read_reg(adap, data_reg); start_idx++; } } /** * t3_mc7_bd_read - read from MC7 through backdoor accesses * @mc7: identifies MC7 to read from * @start: index of first 64-bit word to read * @n: number of 64-bit words to read * @buf: where to store the read result * * Read n 64-bit words from MC7 starting at word start, using backdoor * accesses. */ int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, u64 *buf) { static int shift[] = { 0, 0, 16, 24 }; static int step[] = { 0, 32, 16, 8 }; unsigned int size64 = mc7->size / 8; /* # of 64-bit words */ adapter_t *adap = mc7->adapter; if (start >= size64 || start + n > size64) return -EINVAL; start *= (8 << mc7->width); while (n--) { int i; u64 val64 = 0; for (i = (1 << mc7->width) - 1; i >= 0; --i) { int attempts = 10; u32 val; t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start); t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0); val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP); while ((val & F_BUSY) && attempts--) val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP); if (val & F_BUSY) return -EIO; val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1); if (mc7->width == 0) { val64 = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA0); val64 |= (u64)val << 32; } else { if (mc7->width > 1) val >>= shift[mc7->width]; val64 |= (u64)val << (step[mc7->width] * i); } start += 8; } *buf++ = val64; } return 0; } /* * Low-level I2C read and write routines. These simply read and write a * single byte with the option of indicating a "continue" if another operation * is to be chained. Generally most code will use higher-level routines to * read and write to I2C Slave Devices. */ #define I2C_ATTEMPTS 100 /* * Read an 8-bit value from the I2C bus. If the "chained" parameter is * non-zero then a STOP bit will not be written after the read command. On * error (the read timed out, etc.), a negative errno will be returned (e.g. * -EAGAIN, etc.). On success, the 8-bit value read from the I2C bus is * stored into the buffer *valp and the value of the I2C ACK bit is returned * as a 0/1 value. */ int t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp) { int ret; u32 opval; MDIO_LOCK(adapter); t3_write_reg(adapter, A_I2C_OP, F_I2C_READ | (chained ? F_I2C_CONT : 0)); ret = t3_wait_op_done_val(adapter, A_I2C_OP, F_I2C_BUSY, 0, I2C_ATTEMPTS, 10, &opval); if (ret >= 0) { ret = ((opval & F_I2C_ACK) == F_I2C_ACK); *valp = G_I2C_DATA(t3_read_reg(adapter, A_I2C_DATA)); } MDIO_UNLOCK(adapter); return ret; } /* * Write an 8-bit value to the I2C bus. If the "chained" parameter is * non-zero, then a STOP bit will not be written after the write command. On * error (the write timed out, etc.), a negative errno will be returned (e.g. * -EAGAIN, etc.). On success, the value of the I2C ACK bit is returned as a * 0/1 value. */ int t3_i2c_write8(adapter_t *adapter, int chained, u8 val) { int ret; u32 opval; MDIO_LOCK(adapter); t3_write_reg(adapter, A_I2C_DATA, V_I2C_DATA(val)); t3_write_reg(adapter, A_I2C_OP, F_I2C_WRITE | (chained ? F_I2C_CONT : 0)); ret = t3_wait_op_done_val(adapter, A_I2C_OP, F_I2C_BUSY, 0, I2C_ATTEMPTS, 10, &opval); if (ret >= 0) ret = ((opval & F_I2C_ACK) == F_I2C_ACK); MDIO_UNLOCK(adapter); return ret; } /* * Initialize MI1. */ static void mi1_init(adapter_t *adap, const struct adapter_info *ai) { u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1; u32 val = F_PREEN | V_CLKDIV(clkdiv); t3_write_reg(adap, A_MI1_CFG, val); } #define MDIO_ATTEMPTS 20 /* * MI1 read/write operations for clause 22 PHYs. */ int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *valp) { int ret; u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr); if (mmd_addr) return -EINVAL; MDIO_LOCK(adapter); t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); t3_write_reg(adapter, A_MI1_ADDR, addr); t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2)); ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); if (!ret) *valp = t3_read_reg(adapter, A_MI1_DATA); MDIO_UNLOCK(adapter); return ret; } int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val) { int ret; u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr); if (mmd_addr) return -EINVAL; MDIO_LOCK(adapter); t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); t3_write_reg(adapter, A_MI1_ADDR, addr); t3_write_reg(adapter, A_MI1_DATA, val); t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); MDIO_UNLOCK(adapter); return ret; } static struct mdio_ops mi1_mdio_ops = { t3_mi1_read, t3_mi1_write }; /* * MI1 read/write operations for clause 45 PHYs. */ static int mi1_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int *valp) { int ret; u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr); MDIO_LOCK(adapter); t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0); t3_write_reg(adapter, A_MI1_ADDR, addr); t3_write_reg(adapter, A_MI1_DATA, reg_addr); t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); if (!ret) { t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3)); ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); if (!ret) *valp = t3_read_reg(adapter, A_MI1_DATA); } MDIO_UNLOCK(adapter); return ret; } static int mi1_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, unsigned int val) { int ret; u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr); MDIO_LOCK(adapter); t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0); t3_write_reg(adapter, A_MI1_ADDR, addr); t3_write_reg(adapter, A_MI1_DATA, reg_addr); t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); if (!ret) { t3_write_reg(adapter, A_MI1_DATA, val); t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); } MDIO_UNLOCK(adapter); return ret; } static struct mdio_ops mi1_mdio_ext_ops = { mi1_ext_read, mi1_ext_write }; /** * t3_mdio_change_bits - modify the value of a PHY register * @phy: the PHY to operate on * @mmd: the device address * @reg: the register address * @clear: what part of the register value to mask off * @set: what part of the register value to set * * Changes the value of a PHY register by applying a mask to its current * value and ORing the result with a new value. */ int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, unsigned int set) { int ret; unsigned int val; ret = mdio_read(phy, mmd, reg, &val); if (!ret) { val &= ~clear; ret = mdio_write(phy, mmd, reg, val | set); } return ret; } /** * t3_phy_reset - reset a PHY block * @phy: the PHY to operate on * @mmd: the device address of the PHY block to reset * @wait: how long to wait for the reset to complete in 1ms increments * * Resets a PHY block and optionally waits for the reset to complete. * @mmd should be 0 for 10/100/1000 PHYs and the device address to reset * for 10G PHYs. */ int t3_phy_reset(struct cphy *phy, int mmd, int wait) { int err; unsigned int ctl; err = t3_mdio_change_bits(phy, mmd, MII_BMCR, BMCR_PDOWN, BMCR_RESET); if (err || !wait) return err; do { err = mdio_read(phy, mmd, MII_BMCR, &ctl); if (err) return err; ctl &= BMCR_RESET; if (ctl) msleep(1); } while (ctl && --wait); return ctl ? -1 : 0; } /** * t3_phy_advertise - set the PHY advertisement registers for autoneg * @phy: the PHY to operate on * @advert: bitmap of capabilities the PHY should advertise * * Sets a 10/100/1000 PHY's advertisement registers to advertise the * requested capabilities. */ int t3_phy_advertise(struct cphy *phy, unsigned int advert) { int err; unsigned int val = 0; err = mdio_read(phy, 0, MII_CTRL1000, &val); if (err) return err; val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); if (advert & ADVERTISED_1000baseT_Half) val |= ADVERTISE_1000HALF; if (advert & ADVERTISED_1000baseT_Full) val |= ADVERTISE_1000FULL; err = mdio_write(phy, 0, MII_CTRL1000, val); if (err) return err; val = 1; if (advert & ADVERTISED_10baseT_Half) val |= ADVERTISE_10HALF; if (advert & ADVERTISED_10baseT_Full) val |= ADVERTISE_10FULL; if (advert & ADVERTISED_100baseT_Half) val |= ADVERTISE_100HALF; if (advert & ADVERTISED_100baseT_Full) val |= ADVERTISE_100FULL; if (advert & ADVERTISED_Pause) val |= ADVERTISE_PAUSE_CAP; if (advert & ADVERTISED_Asym_Pause) val |= ADVERTISE_PAUSE_ASYM; return mdio_write(phy, 0, MII_ADVERTISE, val); } /** * t3_phy_advertise_fiber - set fiber PHY advertisement register * @phy: the PHY to operate on * @advert: bitmap of capabilities the PHY should advertise * * Sets a fiber PHY's advertisement register to advertise the * requested capabilities. */ int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert) { unsigned int val = 0; if (advert & ADVERTISED_1000baseT_Half) val |= ADVERTISE_1000XHALF; if (advert & ADVERTISED_1000baseT_Full) val |= ADVERTISE_1000XFULL; if (advert & ADVERTISED_Pause) val |= ADVERTISE_1000XPAUSE; if (advert & ADVERTISED_Asym_Pause) val |= ADVERTISE_1000XPSE_ASYM; return mdio_write(phy, 0, MII_ADVERTISE, val); } /** * t3_set_phy_speed_duplex - force PHY speed and duplex * @phy: the PHY to operate on * @speed: requested PHY speed * @duplex: requested PHY duplex * * Force a 10/100/1000 PHY's speed and duplex. This also disables * auto-negotiation except for GigE, where auto-negotiation is mandatory. */ int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex) { int err; unsigned int ctl; err = mdio_read(phy, 0, MII_BMCR, &ctl); if (err) return err; if (speed >= 0) { ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); if (speed == SPEED_100) ctl |= BMCR_SPEED100; else if (speed == SPEED_1000) ctl |= BMCR_SPEED1000; } if (duplex >= 0) { ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE); if (duplex == DUPLEX_FULL) ctl |= BMCR_FULLDPLX; } if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */ ctl |= BMCR_ANENABLE; return mdio_write(phy, 0, MII_BMCR, ctl); } int t3_phy_lasi_intr_enable(struct cphy *phy) { return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 1); } int t3_phy_lasi_intr_disable(struct cphy *phy) { return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 0); } int t3_phy_lasi_intr_clear(struct cphy *phy) { u32 val; return mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &val); } int t3_phy_lasi_intr_handler(struct cphy *phy) { unsigned int status; int err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &status); if (err) return err; return (status & 1) ? cphy_cause_link_change : 0; } static struct adapter_info t3_adap_info[] = { { 1, 1, 0, F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0, &mi1_mdio_ops, "Chelsio PE9000" }, { 1, 1, 0, F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0, &mi1_mdio_ops, "Chelsio T302" }, { 1, 0, 0, F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, { 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, &mi1_mdio_ext_ops, "Chelsio T310" }, { 1, 1, 0, F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, &mi1_mdio_ext_ops, "Chelsio T320" }, { 4, 0, 0, F_GPIO5_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO7_OUT_VAL, { S_GPIO1, S_GPIO2, S_GPIO3, S_GPIO4 }, SUPPORTED_AUI, &mi1_mdio_ops, "Chelsio T304" }, { 0 }, { 1, 0, 0, F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, { S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, &mi1_mdio_ext_ops, "Chelsio T310" }, { 1, 0, 0, F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL, { S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, &mi1_mdio_ext_ops, "Chelsio N320E-G2" }, }; /* * Return the adapter_info structure with a given index. Out-of-range indices * return NULL. */ const struct adapter_info *t3_get_adapter_info(unsigned int id) { return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL; } struct port_type_info { int (*phy_prep)(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *ops); }; static struct port_type_info port_types[] = { { NULL }, { t3_ael1002_phy_prep }, { t3_vsc8211_phy_prep }, { t3_mv88e1xxx_phy_prep }, { t3_xaui_direct_phy_prep }, { t3_ael2005_phy_prep }, { t3_qt2045_phy_prep }, { t3_ael1006_phy_prep }, { t3_tn1010_phy_prep }, { t3_aq100x_phy_prep }, { t3_ael2020_phy_prep }, }; #define VPD_ENTRY(name, len) \ u8 name##_kword[2]; u8 name##_len; u8 name##_data[len] /* * Partial EEPROM Vital Product Data structure. Includes only the ID and * VPD-R sections. */ struct t3_vpd { u8 id_tag; u8 id_len[2]; u8 id_data[16]; u8 vpdr_tag; u8 vpdr_len[2]; VPD_ENTRY(pn, 16); /* part number */ VPD_ENTRY(ec, ECNUM_LEN); /* EC level */ VPD_ENTRY(sn, SERNUM_LEN); /* serial number */ VPD_ENTRY(na, 12); /* MAC address base */ VPD_ENTRY(cclk, 6); /* core clock */ VPD_ENTRY(mclk, 6); /* mem clock */ VPD_ENTRY(uclk, 6); /* uP clk */ VPD_ENTRY(mdc, 6); /* MDIO clk */ VPD_ENTRY(mt, 2); /* mem timing */ VPD_ENTRY(xaui0cfg, 6); /* XAUI0 config */ VPD_ENTRY(xaui1cfg, 6); /* XAUI1 config */ VPD_ENTRY(port0, 2); /* PHY0 complex */ VPD_ENTRY(port1, 2); /* PHY1 complex */ VPD_ENTRY(port2, 2); /* PHY2 complex */ VPD_ENTRY(port3, 2); /* PHY3 complex */ VPD_ENTRY(rv, 1); /* csum */ u32 pad; /* for multiple-of-4 sizing and alignment */ }; #define EEPROM_MAX_POLL 40 #define EEPROM_STAT_ADDR 0x4000 #define VPD_BASE 0xc00 /** * t3_seeprom_read - read a VPD EEPROM location * @adapter: adapter to read * @addr: EEPROM address * @data: where to store the read data * * Read a 32-bit word from a location in VPD EEPROM using the card's PCI * VPD ROM capability. A zero is written to the flag bit when the * addres is written to the control register. The hardware device will * set the flag to 1 when 4 bytes have been read into the data register. */ int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data) { u16 val; int attempts = EEPROM_MAX_POLL; unsigned int base = adapter->params.pci.vpd_cap_addr; if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3)) return -EINVAL; t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR, (u16)addr); do { udelay(10); t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val); } while (!(val & PCI_VPD_ADDR_F) && --attempts); if (!(val & PCI_VPD_ADDR_F)) { CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr); return -EIO; } t3_os_pci_read_config_4(adapter, base + PCI_VPD_DATA, data); *data = le32_to_cpu(*data); return 0; } /** * t3_seeprom_write - write a VPD EEPROM location * @adapter: adapter to write * @addr: EEPROM address * @data: value to write * * Write a 32-bit word to a location in VPD EEPROM using the card's PCI * VPD ROM capability. */ int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data) { u16 val; int attempts = EEPROM_MAX_POLL; unsigned int base = adapter->params.pci.vpd_cap_addr; if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3)) return -EINVAL; t3_os_pci_write_config_4(adapter, base + PCI_VPD_DATA, cpu_to_le32(data)); t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR, (u16)addr | PCI_VPD_ADDR_F); do { msleep(1); t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val); } while ((val & PCI_VPD_ADDR_F) && --attempts); if (val & PCI_VPD_ADDR_F) { CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr); return -EIO; } return 0; } /** * t3_seeprom_wp - enable/disable EEPROM write protection * @adapter: the adapter * @enable: 1 to enable write protection, 0 to disable it * * Enables or disables write protection on the serial EEPROM. */ int t3_seeprom_wp(adapter_t *adapter, int enable) { return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); } /* * Convert a character holding a hex digit to a number. */ static unsigned int hex2int(unsigned char c) { return isdigit(c) ? c - '0' : toupper(c) - 'A' + 10; } /** * get_desc_len - get the length of a vpd descriptor. * @adapter: the adapter * @offset: first byte offset of the vpd descriptor * * Retrieves the length of the small/large resource * data type starting at offset. */ static int get_desc_len(adapter_t *adapter, u32 offset) { u32 read_offset, tmp, shift, len = 0; u8 tag, buf[8]; int ret; read_offset = offset & 0xfffffffc; shift = offset & 0x03; ret = t3_seeprom_read(adapter, read_offset, &tmp); if (ret < 0) return ret; *((u32 *)buf) = cpu_to_le32(tmp); tag = buf[shift]; if (tag & 0x80) { ret = t3_seeprom_read(adapter, read_offset + 4, &tmp); if (ret < 0) return ret; *((u32 *)(&buf[4])) = cpu_to_le32(tmp); len = (buf[shift + 1] & 0xff) + ((buf[shift+2] << 8) & 0xff00) + 3; } else len = (tag & 0x07) + 1; return len; } /** * is_end_tag - Check if a vpd tag is the end tag. * @adapter: the adapter * @offset: first byte offset of the tag * * Checks if the tag located at offset is the end tag. */ static int is_end_tag(adapter_t * adapter, u32 offset) { u32 read_offset, shift, ret, tmp; u8 buf[4]; read_offset = offset & 0xfffffffc; shift = offset & 0x03; ret = t3_seeprom_read(adapter, read_offset, &tmp); if (ret) return ret; *((u32 *)buf) = cpu_to_le32(tmp); if (buf[shift] == 0x78) return 1; else return 0; } /** * t3_get_vpd_len - computes the length of a vpd structure * @adapter: the adapter * @vpd: contains the offset of first byte of vpd * * Computes the lentgh of the vpd structure starting at vpd->offset. */ int t3_get_vpd_len(adapter_t * adapter, struct generic_vpd *vpd) { u32 len=0, offset; int inc, ret; offset = vpd->offset; while (offset < (vpd->offset + MAX_VPD_BYTES)) { ret = is_end_tag(adapter, offset); if (ret < 0) return ret; else if (ret == 1) break; inc = get_desc_len(adapter, offset); if (inc < 0) return inc; len += inc; offset += inc; } return (len + 1); } /** * t3_read_vpd - reads the stream of bytes containing a vpd structure * @adapter: the adapter * @vpd: contains a buffer that would hold the stream of bytes * * Reads the vpd structure starting at vpd->offset into vpd->data, * the length of the byte stream to read is vpd->len. */ int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd) { u32 i, ret; for (i = 0; i < vpd->len; i += 4) { ret = t3_seeprom_read(adapter, vpd->offset + i, (u32 *) &(vpd->data[i])); if (ret) return ret; } return 0; } /** * get_vpd_params - read VPD parameters from VPD EEPROM * @adapter: adapter to read * @p: where to store the parameters * * Reads card parameters stored in VPD EEPROM. */ static int get_vpd_params(adapter_t *adapter, struct vpd_params *p) { int i, addr, ret; struct t3_vpd vpd; /* * Card information is normally at VPD_BASE but some early cards had * it at 0. */ ret = t3_seeprom_read(adapter, VPD_BASE, (u32 *)&vpd); if (ret) return ret; addr = vpd.id_tag == 0x82 ? VPD_BASE : 0; for (i = 0; i < sizeof(vpd); i += 4) { ret = t3_seeprom_read(adapter, addr + i, (u32 *)((u8 *)&vpd + i)); if (ret) return ret; } p->cclk = simple_strtoul(vpd.cclk_data, NULL, 10); p->mclk = simple_strtoul(vpd.mclk_data, NULL, 10); p->uclk = simple_strtoul(vpd.uclk_data, NULL, 10); p->mdc = simple_strtoul(vpd.mdc_data, NULL, 10); p->mem_timing = simple_strtoul(vpd.mt_data, NULL, 10); memcpy(p->sn, vpd.sn_data, SERNUM_LEN); memcpy(p->ec, vpd.ec_data, ECNUM_LEN); /* Old eeproms didn't have port information */ if (adapter->params.rev == 0 && !vpd.port0_data[0]) { p->port_type[0] = uses_xaui(adapter) ? 1 : 2; p->port_type[1] = uses_xaui(adapter) ? 6 : 2; } else { p->port_type[0] = (u8)hex2int(vpd.port0_data[0]); p->port_type[1] = (u8)hex2int(vpd.port1_data[0]); p->port_type[2] = (u8)hex2int(vpd.port2_data[0]); p->port_type[3] = (u8)hex2int(vpd.port3_data[0]); p->xauicfg[0] = simple_strtoul(vpd.xaui0cfg_data, NULL, 16); p->xauicfg[1] = simple_strtoul(vpd.xaui1cfg_data, NULL, 16); } for (i = 0; i < 6; i++) p->eth_base[i] = hex2int(vpd.na_data[2 * i]) * 16 + hex2int(vpd.na_data[2 * i + 1]); return 0; } /* BIOS boot header */ typedef struct boot_header_s { u8 signature[2]; /* signature */ u8 length; /* image length (include header) */ u8 offset[4]; /* initialization vector */ u8 reserved[19]; /* reserved */ u8 exheader[2]; /* offset to expansion header */ } boot_header_t; /* serial flash and firmware constants */ enum { SF_ATTEMPTS = 5, /* max retries for SF1 operations */ SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */ /* flash command opcodes */ SF_PROG_PAGE = 2, /* program page */ SF_WR_DISABLE = 4, /* disable writes */ SF_RD_STATUS = 5, /* read status register */ SF_WR_ENABLE = 6, /* enable writes */ SF_RD_DATA_FAST = 0xb, /* read flash */ SF_ERASE_SECTOR = 0xd8, /* erase sector */ FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */ FW_VERS_ADDR = 0x7fffc, /* flash address holding FW version */ FW_VERS_ADDR_PRE8 = 0x77ffc,/* flash address holding FW version pre8 */ FW_MIN_SIZE = 8, /* at least version and csum */ FW_MAX_SIZE = FW_VERS_ADDR - FW_FLASH_BOOT_ADDR, FW_MAX_SIZE_PRE8 = FW_VERS_ADDR_PRE8 - FW_FLASH_BOOT_ADDR, BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ BOOT_MIN_SIZE = sizeof(boot_header_t), /* at least basic header */ BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC /* 1 byte * length increment */ }; /** * sf1_read - read data from the serial flash * @adapter: the adapter * @byte_cnt: number of bytes to read * @cont: whether another operation will be chained * @valp: where to store the read data * * Reads up to 4 bytes of data from the serial flash. The location of * the read needs to be specified prior to calling this by issuing the * appropriate commands to the serial flash. */ static int sf1_read(adapter_t *adapter, unsigned int byte_cnt, int cont, u32 *valp) { int ret; if (!byte_cnt || byte_cnt > 4) return -EINVAL; if (t3_read_reg(adapter, A_SF_OP) & F_BUSY) return -EBUSY; t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10); if (!ret) *valp = t3_read_reg(adapter, A_SF_DATA); return ret; } /** * sf1_write - write data to the serial flash * @adapter: the adapter * @byte_cnt: number of bytes to write * @cont: whether another operation will be chained * @val: value to write * * Writes up to 4 bytes of data to the serial flash. The location of * the write needs to be specified prior to calling this by issuing the * appropriate commands to the serial flash. */ static int sf1_write(adapter_t *adapter, unsigned int byte_cnt, int cont, u32 val) { if (!byte_cnt || byte_cnt > 4) return -EINVAL; if (t3_read_reg(adapter, A_SF_OP) & F_BUSY) return -EBUSY; t3_write_reg(adapter, A_SF_DATA, val); t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10); } /** * flash_wait_op - wait for a flash operation to complete * @adapter: the adapter * @attempts: max number of polls of the status register * @delay: delay between polls in ms * * Wait for a flash operation to complete by polling the status register. */ static int flash_wait_op(adapter_t *adapter, int attempts, int delay) { int ret; u32 status; while (1) { if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 || (ret = sf1_read(adapter, 1, 0, &status)) != 0) return ret; if (!(status & 1)) return 0; if (--attempts == 0) return -EAGAIN; if (delay) msleep(delay); } } /** * t3_read_flash - read words from serial flash * @adapter: the adapter * @addr: the start address for the read * @nwords: how many 32-bit words to read * @data: where to store the read data * @byte_oriented: whether to store data as bytes or as words * * Read the specified number of 32-bit words from the serial flash. * If @byte_oriented is set the read data is stored as a byte array * (i.e., big-endian), otherwise as 32-bit words in the platform's * natural endianess. */ int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented) { int ret; if (addr + nwords * sizeof(u32) > SF_SIZE || (addr & 3)) return -EINVAL; addr = swab32(addr) | SF_RD_DATA_FAST; if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 || (ret = sf1_read(adapter, 1, 1, data)) != 0) return ret; for ( ; nwords; nwords--, data++) { ret = sf1_read(adapter, 4, nwords > 1, data); if (ret) return ret; if (byte_oriented) *data = htonl(*data); } return 0; } /** * t3_write_flash - write up to a page of data to the serial flash * @adapter: the adapter * @addr: the start address to write * @n: length of data to write * @data: the data to write * @byte_oriented: whether to store data as bytes or as words * * Writes up to a page of data (256 bytes) to the serial flash starting * at the given address. * If @byte_oriented is set the write data is stored as a 32-bit * big-endian array, otherwise in the processor's native endianess. * */ static int t3_write_flash(adapter_t *adapter, unsigned int addr, unsigned int n, const u8 *data, int byte_oriented) { int ret; u32 buf[64]; unsigned int c, left, val, offset = addr & 0xff; if (addr + n > SF_SIZE || offset + n > 256) return -EINVAL; val = swab32(addr) | SF_PROG_PAGE; if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 || (ret = sf1_write(adapter, 4, 1, val)) != 0) return ret; for (left = n; left; left -= c) { c = min(left, 4U); val = *(const u32*)data; data += c; if (byte_oriented) val = htonl(val); ret = sf1_write(adapter, c, c != left, val); if (ret) return ret; } if ((ret = flash_wait_op(adapter, 5, 1)) != 0) return ret; /* Read the page to verify the write succeeded */ ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, byte_oriented); if (ret) return ret; if (memcmp(data - n, (u8 *)buf + offset, n)) return -EIO; return 0; } /** * t3_get_tp_version - read the tp sram version * @adapter: the adapter * @vers: where to place the version * * Reads the protocol sram version from sram. */ int t3_get_tp_version(adapter_t *adapter, u32 *vers) { int ret; /* Get version loaded in SRAM */ t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0); ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1); if (ret) return ret; *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1); return 0; } /** * t3_check_tpsram_version - read the tp sram version * @adapter: the adapter * */ int t3_check_tpsram_version(adapter_t *adapter) { int ret; u32 vers; unsigned int major, minor; if (adapter->params.rev == T3_REV_A) return 0; ret = t3_get_tp_version(adapter, &vers); if (ret) return ret; vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1); major = G_TP_VERSION_MAJOR(vers); minor = G_TP_VERSION_MINOR(vers); if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) return 0; else { CH_ERR(adapter, "found wrong TP version (%u.%u), " "driver compiled for version %d.%d\n", major, minor, TP_VERSION_MAJOR, TP_VERSION_MINOR); } return -EINVAL; } /** * t3_check_tpsram - check if provided protocol SRAM * is compatible with this driver * @adapter: the adapter * @tp_sram: the firmware image to write * @size: image size * * Checks if an adapter's tp sram is compatible with the driver. * Returns 0 if the versions are compatible, a negative error otherwise. */ int t3_check_tpsram(adapter_t *adapter, const u8 *tp_sram, unsigned int size) { u32 csum; unsigned int i; const u32 *p = (const u32 *)tp_sram; /* Verify checksum */ for (csum = 0, i = 0; i < size / sizeof(csum); i++) csum += ntohl(p[i]); if (csum != 0xffffffff) { CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n", csum); return -EINVAL; } return 0; } enum fw_version_type { FW_VERSION_N3, FW_VERSION_T3 }; /** * t3_get_fw_version - read the firmware version * @adapter: the adapter * @vers: where to place the version * * Reads the FW version from flash. Note that we had to move the version * due to FW size. If we don't find a valid FW version in the new location * we fall back and read the old location. */ int t3_get_fw_version(adapter_t *adapter, u32 *vers) { int ret = t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0); if (!ret && *vers != 0xffffffff) return 0; else return t3_read_flash(adapter, FW_VERS_ADDR_PRE8, 1, vers, 0); } /** * t3_check_fw_version - check if the FW is compatible with this driver * @adapter: the adapter * * Checks if an adapter's FW is compatible with the driver. Returns 0 * if the versions are compatible, a negative error otherwise. */ int t3_check_fw_version(adapter_t *adapter) { int ret; u32 vers; unsigned int type, major, minor; ret = t3_get_fw_version(adapter, &vers); if (ret) return ret; type = G_FW_VERSION_TYPE(vers); major = G_FW_VERSION_MAJOR(vers); minor = G_FW_VERSION_MINOR(vers); if (type == FW_VERSION_T3 && major == FW_VERSION_MAJOR && minor == FW_VERSION_MINOR) return 0; else if (major != FW_VERSION_MAJOR || minor < FW_VERSION_MINOR) CH_WARN(adapter, "found old FW minor version(%u.%u), " "driver compiled for version %u.%u\n", major, minor, FW_VERSION_MAJOR, FW_VERSION_MINOR); else { CH_WARN(adapter, "found newer FW version(%u.%u), " "driver compiled for version %u.%u\n", major, minor, FW_VERSION_MAJOR, FW_VERSION_MINOR); return 0; } return -EINVAL; } /** * t3_flash_erase_sectors - erase a range of flash sectors * @adapter: the adapter * @start: the first sector to erase * @end: the last sector to erase * * Erases the sectors in the given range. */ static int t3_flash_erase_sectors(adapter_t *adapter, int start, int end) { while (start <= end) { int ret; if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 || (ret = sf1_write(adapter, 4, 0, SF_ERASE_SECTOR | (start << 8))) != 0 || (ret = flash_wait_op(adapter, 5, 500)) != 0) return ret; start++; } return 0; } /* * t3_load_fw - download firmware * @adapter: the adapter * @fw_data: the firmware image to write * @size: image size * * Write the supplied firmware image to the card's serial flash. * The FW image has the following sections: @size - 8 bytes of code and * data, followed by 4 bytes of FW version, followed by the 32-bit * 1's complement checksum of the whole image. */ int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size) { u32 version, csum, fw_version_addr; unsigned int i; const u32 *p = (const u32 *)fw_data; int ret, addr, fw_sector = FW_FLASH_BOOT_ADDR >> 16; if ((size & 3) || size < FW_MIN_SIZE) return -EINVAL; if (size - 8 > FW_MAX_SIZE) return -EFBIG; version = ntohl(*(const u32 *)(fw_data + size - 8)); if (G_FW_VERSION_MAJOR(version) < 8) { fw_version_addr = FW_VERS_ADDR_PRE8; if (size - 8 > FW_MAX_SIZE_PRE8) return -EFBIG; } else fw_version_addr = FW_VERS_ADDR; for (csum = 0, i = 0; i < size / sizeof(csum); i++) csum += ntohl(p[i]); if (csum != 0xffffffff) { CH_ERR(adapter, "corrupted firmware image, checksum %u\n", csum); return -EINVAL; } ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector); if (ret) goto out; size -= 8; /* trim off version and checksum */ for (addr = FW_FLASH_BOOT_ADDR; size; ) { unsigned int chunk_size = min(size, 256U); ret = t3_write_flash(adapter, addr, chunk_size, fw_data, 1); if (ret) goto out; addr += chunk_size; fw_data += chunk_size; size -= chunk_size; } ret = t3_write_flash(adapter, fw_version_addr, 4, fw_data, 1); out: if (ret) CH_ERR(adapter, "firmware download failed, error %d\n", ret); return ret; } /* * t3_load_boot - download boot flash * @adapter: the adapter * @boot_data: the boot image to write * @size: image size * * Write the supplied boot image to the card's serial flash. * The boot image has the following sections: a 28-byte header and the * boot image. */ int t3_load_boot(adapter_t *adapter, u8 *boot_data, unsigned int size) { boot_header_t *header = (boot_header_t *)boot_data; int ret; unsigned int addr; unsigned int boot_sector = BOOT_FLASH_BOOT_ADDR >> 16; unsigned int boot_end = (BOOT_FLASH_BOOT_ADDR + size - 1) >> 16; /* * Perform some primitive sanity testing to avoid accidentally * writing garbage over the boot sectors. We ought to check for * more but it's not worth it for now ... */ if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { CH_ERR(adapter, "boot image too small/large\n"); return -EFBIG; } if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE) { CH_ERR(adapter, "boot image missing signature\n"); return -EINVAL; } if (header->length * BOOT_SIZE_INC != size) { CH_ERR(adapter, "boot image header length != image length\n"); return -EINVAL; } ret = t3_flash_erase_sectors(adapter, boot_sector, boot_end); if (ret) goto out; for (addr = BOOT_FLASH_BOOT_ADDR; size; ) { unsigned int chunk_size = min(size, 256U); ret = t3_write_flash(adapter, addr, chunk_size, boot_data, 0); if (ret) goto out; addr += chunk_size; boot_data += chunk_size; size -= chunk_size; } out: if (ret) CH_ERR(adapter, "boot image download failed, error %d\n", ret); return ret; } #define CIM_CTL_BASE 0x2000 /** * t3_cim_ctl_blk_read - read a block from CIM control region * @adap: the adapter * @addr: the start address within the CIM control region * @n: number of words to read * @valp: where to store the result * * Reads a block of 4-byte words from the CIM control region. */ int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, unsigned int *valp) { int ret = 0; if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) return -EBUSY; for ( ; !ret && n--; addr += 4) { t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr); ret = t3_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 0, 5, 2); if (!ret) *valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA); } return ret; } static void t3_gate_rx_traffic(struct cmac *mac, u32 *rx_cfg, u32 *rx_hash_high, u32 *rx_hash_low) { /* stop Rx unicast traffic */ t3_mac_disable_exact_filters(mac); /* stop broadcast, multicast, promiscuous mode traffic */ *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG + mac->offset); t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset, F_ENHASHMCAST | F_DISBCAST | F_COPYALLFRAMES, F_DISBCAST); *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset); t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset, 0); *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset); t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset, 0); /* Leave time to drain max RX fifo */ msleep(1); } static void t3_open_rx_traffic(struct cmac *mac, u32 rx_cfg, u32 rx_hash_high, u32 rx_hash_low) { t3_mac_enable_exact_filters(mac); t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset, F_ENHASHMCAST | F_DISBCAST | F_COPYALLFRAMES, rx_cfg); t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset, rx_hash_high); t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset, rx_hash_low); } static int t3_detect_link_fault(adapter_t *adapter, int port_id) { struct port_info *pi = adap2pinfo(adapter, port_id); struct cmac *mac = &pi->mac; uint32_t rx_cfg, rx_hash_high, rx_hash_low; int link_fault; /* stop rx */ t3_gate_rx_traffic(mac, &rx_cfg, &rx_hash_high, &rx_hash_low); t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); /* clear status and make sure intr is enabled */ (void) t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); t3_xgm_intr_enable(adapter, port_id); /* restart rx */ t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, F_RXEN); t3_open_rx_traffic(mac, rx_cfg, rx_hash_high, rx_hash_low); link_fault = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); return (link_fault & F_LINKFAULTCHANGE ? 1 : 0); } static void t3_clear_faults(adapter_t *adapter, int port_id) { struct port_info *pi = adap2pinfo(adapter, port_id); struct cmac *mac = &pi->mac; if (adapter->params.nports <= 2) { t3_xgm_intr_disable(adapter, pi->port_id); t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, F_XGM_INT); t3_set_reg_field(adapter, A_XGM_INT_ENABLE + mac->offset, F_XGM_INT, F_XGM_INT); t3_xgm_intr_enable(adapter, pi->port_id); } } /** * t3_link_changed - handle interface link changes * @adapter: the adapter * @port_id: the port index that changed link state * * Called when a port's link settings change to propagate the new values * to the associated PHY and MAC. After performing the common tasks it * invokes an OS-specific handler. */ void t3_link_changed(adapter_t *adapter, int port_id) { int link_ok, speed, duplex, fc, link_fault; struct port_info *pi = adap2pinfo(adapter, port_id); struct cphy *phy = &pi->phy; struct cmac *mac = &pi->mac; struct link_config *lc = &pi->link_config; link_ok = lc->link_ok; speed = lc->speed; duplex = lc->duplex; fc = lc->fc; link_fault = 0; phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc); if (link_ok == 0) pi->link_fault = LF_NO; if (lc->requested_fc & PAUSE_AUTONEG) fc &= lc->requested_fc; else fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); /* Update mac speed before checking for link fault. */ if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE && (speed != lc->speed || duplex != lc->duplex || fc != lc->fc)) t3_mac_set_speed_duplex_fc(mac, speed, duplex, fc); /* * Check for link faults if any of these is true: * a) A link fault is suspected, and PHY says link ok * b) PHY link transitioned from down -> up */ if (adapter->params.nports <= 2 && ((pi->link_fault && link_ok) || (!lc->link_ok && link_ok))) { link_fault = t3_detect_link_fault(adapter, port_id); if (link_fault) { if (pi->link_fault != LF_YES) { mac->stats.link_faults++; pi->link_fault = LF_YES; } if (uses_xaui(adapter)) { if (adapter->params.rev >= T3_REV_C) t3c_pcs_force_los(mac); else t3b_pcs_reset(mac); } /* Don't report link up */ link_ok = 0; } else { /* clear faults here if this was a false alarm. */ if (pi->link_fault == LF_MAYBE && link_ok && lc->link_ok) t3_clear_faults(adapter, port_id); pi->link_fault = LF_NO; } } if (link_ok == lc->link_ok && speed == lc->speed && duplex == lc->duplex && fc == lc->fc) return; /* nothing changed */ lc->link_ok = (unsigned char)link_ok; lc->speed = speed < 0 ? SPEED_INVALID : speed; lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex; lc->fc = fc; if (link_ok) { /* down -> up, or up -> up with changed settings */ if (adapter->params.rev > 0 && uses_xaui(adapter)) { if (adapter->params.rev >= T3_REV_C) t3c_pcs_force_los(mac); else t3b_pcs_reset(mac); t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, F_TXACTENABLE | F_RXEN); } /* disable TX FIFO drain */ t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + mac->offset, F_ENDROPPKT, 0); t3_mac_enable(mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX); t3_set_reg_field(adapter, A_XGM_STAT_CTRL + mac->offset, F_CLRSTATS, 1); t3_clear_faults(adapter, port_id); } else { /* up -> down */ if (adapter->params.rev > 0 && uses_xaui(adapter)) { t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, 0); } t3_xgm_intr_disable(adapter, pi->port_id); if (adapter->params.nports <= 2) { t3_set_reg_field(adapter, A_XGM_INT_ENABLE + mac->offset, F_XGM_INT, 0); t3_mac_disable(mac, MAC_DIRECTION_RX); /* * Make sure Tx FIFO continues to drain, even as rxen is * left high to help detect and indicate remote faults. */ t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + mac->offset, 0, F_ENDROPPKT); t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); t3_write_reg(adapter, A_XGM_TX_CTRL + mac->offset, F_TXEN); t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, F_RXEN); } } t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc, mac->was_reset); mac->was_reset = 0; } /** * t3_link_start - apply link configuration to MAC/PHY * @phy: the PHY to setup * @mac: the MAC to setup * @lc: the requested link configuration * * Set up a port's MAC and PHY according to a desired link configuration. * - If the PHY can auto-negotiate first decide what to advertise, then * enable/disable auto-negotiation as desired, and reset. * - If the PHY does not auto-negotiate just reset it. * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, * otherwise do it later based on the outcome of auto-negotiation. */ int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc) { unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); lc->link_ok = 0; if (lc->supported & SUPPORTED_Autoneg) { lc->advertising &= ~(ADVERTISED_Asym_Pause | ADVERTISED_Pause); if (fc) { lc->advertising |= ADVERTISED_Asym_Pause; if (fc & PAUSE_RX) lc->advertising |= ADVERTISED_Pause; } phy->ops->advertise(phy, lc->advertising); if (lc->autoneg == AUTONEG_DISABLE) { lc->speed = lc->requested_speed; lc->duplex = lc->requested_duplex; lc->fc = (unsigned char)fc; t3_mac_set_speed_duplex_fc(mac, lc->speed, lc->duplex, fc); /* Also disables autoneg */ phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex); /* PR 5666. Power phy up when doing an ifup */ if (!is_10G(phy->adapter)) phy->ops->power_down(phy, 0); } else phy->ops->autoneg_enable(phy); } else { t3_mac_set_speed_duplex_fc(mac, -1, -1, fc); lc->fc = (unsigned char)fc; phy->ops->reset(phy, 0); } return 0; } /** * t3_set_vlan_accel - control HW VLAN extraction * @adapter: the adapter * @ports: bitmap of adapter ports to operate on * @on: enable (1) or disable (0) HW VLAN extraction * * Enables or disables HW extraction of VLAN tags for the given port. */ void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on) { t3_set_reg_field(adapter, A_TP_OUT_CONFIG, ports << S_VLANEXTRACTIONENABLE, on ? (ports << S_VLANEXTRACTIONENABLE) : 0); } struct intr_info { unsigned int mask; /* bits to check in interrupt status */ const char *msg; /* message to print or NULL */ short stat_idx; /* stat counter to increment or -1 */ unsigned short fatal; /* whether the condition reported is fatal */ }; /** * t3_handle_intr_status - table driven interrupt handler * @adapter: the adapter that generated the interrupt * @reg: the interrupt status register to process * @mask: a mask to apply to the interrupt status * @acts: table of interrupt actions * @stats: statistics counters tracking interrupt occurences * * A table driven interrupt handler that applies a set of masks to an * interrupt status word and performs the corresponding actions if the * interrupts described by the mask have occured. The actions include * optionally printing a warning or alert message, and optionally * incrementing a stat counter. The table is terminated by an entry * specifying mask 0. Returns the number of fatal interrupt conditions. */ static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg, unsigned int mask, const struct intr_info *acts, unsigned long *stats) { int fatal = 0; unsigned int status = t3_read_reg(adapter, reg) & mask; for ( ; acts->mask; ++acts) { if (!(status & acts->mask)) continue; if (acts->fatal) { fatal++; CH_ALERT(adapter, "%s (0x%x)\n", acts->msg, status & acts->mask); CTR2(KTR_CXGB, "%s (0x%x)\n", acts->msg, status & acts->mask); + status &= ~acts->mask; } else if (acts->msg) CH_WARN(adapter, "%s (0x%x)\n", acts->msg, status & acts->mask); if (acts->stat_idx >= 0) stats[acts->stat_idx]++; } if (status) /* clear processed interrupts */ t3_write_reg(adapter, reg, status); return fatal; } #define SGE_INTR_MASK (F_RSPQDISABLED | \ F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR | \ F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \ F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \ V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \ F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \ F_HIRCQPARITYERROR) #define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \ F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \ F_NFASRCHFAIL) #define MC7_INTR_MASK (F_AE | F_UE | F_CE | V_PE(M_PE)) #define XGM_INTR_MASK (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \ V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR) | \ F_TXFIFO_UNDERRUN) #define PCIX_INTR_MASK (F_MSTDETPARERR | F_SIGTARABT | F_RCVTARABT | \ F_RCVMSTABT | F_SIGSYSERR | F_DETPARERR | \ F_SPLCMPDIS | F_UNXSPLCMP | F_RCVSPLCMPERR | \ F_DETCORECCERR | F_DETUNCECCERR | F_PIOPARERR | \ V_WFPARERR(M_WFPARERR) | V_RFPARERR(M_RFPARERR) | \ V_CFPARERR(M_CFPARERR) /* | V_MSIXPARERR(M_MSIXPARERR) */) #define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\ F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \ /* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \ F_RETRYBUFPARERR | F_RETRYLUTPARERR | F_RXPARERR | \ F_TXPARERR | V_BISTERR(M_BISTERR)) #define ULPRX_INTR_MASK (F_PARERRDATA | F_PARERRPCMD | F_ARBPF1PERR | \ F_ARBPF0PERR | F_ARBFPERR | F_PCMDMUXPERR | \ F_DATASELFRAMEERR1 | F_DATASELFRAMEERR0) #define ULPTX_INTR_MASK 0xfc #define CPLSW_INTR_MASK (F_CIM_OP_MAP_PERR | F_TP_FRAMING_ERROR | \ F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \ F_ZERO_SWITCH_ERROR) #define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \ F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \ F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \ F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT | \ F_DRAMPARERR | F_ICACHEPARERR | F_DCACHEPARERR | \ F_OBQSGEPARERR | F_OBQULPHIPARERR | F_OBQULPLOPARERR | \ F_IBQSGELOPARERR | F_IBQSGEHIPARERR | F_IBQULPPARERR | \ F_IBQTPPARERR | F_ITAGPARERR | F_DTAGPARERR) #define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \ V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \ V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR)) #define PMRX_INTR_MASK (F_ZERO_E_CMD_ERROR | IESPI_FRM_ERR | OCSPI_FRM_ERR | \ V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR) | \ V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR)) #define MPS_INTR_MASK (V_TX0TPPARERRENB(M_TX0TPPARERRENB) | \ V_TX1TPPARERRENB(M_TX1TPPARERRENB) | \ V_RXTPPARERRENB(M_RXTPPARERRENB) | \ V_MCAPARERRENB(M_MCAPARERRENB)) #define XGM_EXTRA_INTR_MASK (F_LINKFAULTCHANGE) #define PL_INTR_MASK (F_T3DBG | F_XGMAC0_0 | F_XGMAC0_1 | F_MC5A | F_PM1_TX | \ F_PM1_RX | F_ULP2_TX | F_ULP2_RX | F_TP1 | F_CIM | \ F_MC7_CM | F_MC7_PMTX | F_MC7_PMRX | F_SGE3 | F_PCIM0 | \ F_MPS0 | F_CPL_SWITCH) /* * Interrupt handler for the PCIX1 module. */ static void pci_intr_handler(adapter_t *adapter) { static struct intr_info pcix1_intr_info[] = { { F_MSTDETPARERR, "PCI master detected parity error", -1, 1 }, { F_SIGTARABT, "PCI signaled target abort", -1, 1 }, { F_RCVTARABT, "PCI received target abort", -1, 1 }, { F_RCVMSTABT, "PCI received master abort", -1, 1 }, { F_SIGSYSERR, "PCI signaled system error", -1, 1 }, { F_DETPARERR, "PCI detected parity error", -1, 1 }, { F_SPLCMPDIS, "PCI split completion discarded", -1, 1 }, { F_UNXSPLCMP, "PCI unexpected split completion error", -1, 1 }, { F_RCVSPLCMPERR, "PCI received split completion error", -1, 1 }, { F_DETCORECCERR, "PCI correctable ECC error", STAT_PCI_CORR_ECC, 0 }, { F_DETUNCECCERR, "PCI uncorrectable ECC error", -1, 1 }, { F_PIOPARERR, "PCI PIO FIFO parity error", -1, 1 }, { V_WFPARERR(M_WFPARERR), "PCI write FIFO parity error", -1, 1 }, { V_RFPARERR(M_RFPARERR), "PCI read FIFO parity error", -1, 1 }, { V_CFPARERR(M_CFPARERR), "PCI command FIFO parity error", -1, 1 }, { V_MSIXPARERR(M_MSIXPARERR), "PCI MSI-X table/PBA parity " "error", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK, pcix1_intr_info, adapter->irq_stats)) t3_fatal_err(adapter); } /* * Interrupt handler for the PCIE module. */ static void pcie_intr_handler(adapter_t *adapter) { static struct intr_info pcie_intr_info[] = { { F_PEXERR, "PCI PEX error", -1, 1 }, { F_UNXSPLCPLERRR, "PCI unexpected split completion DMA read error", -1, 1 }, { F_UNXSPLCPLERRC, "PCI unexpected split completion DMA command error", -1, 1 }, { F_PCIE_PIOPARERR, "PCI PIO FIFO parity error", -1, 1 }, { F_PCIE_WFPARERR, "PCI write FIFO parity error", -1, 1 }, { F_PCIE_RFPARERR, "PCI read FIFO parity error", -1, 1 }, { F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1 }, { V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR), "PCI MSI-X table/PBA parity error", -1, 1 }, { F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1 }, { F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1 }, { F_RXPARERR, "PCI Rx parity error", -1, 1 }, { F_TXPARERR, "PCI Tx parity error", -1, 1 }, { V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1 }, { 0 } }; if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR) CH_ALERT(adapter, "PEX error code 0x%x\n", t3_read_reg(adapter, A_PCIE_PEX_ERR)); if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK, pcie_intr_info, adapter->irq_stats)) t3_fatal_err(adapter); } /* * TP interrupt handler. */ static void tp_intr_handler(adapter_t *adapter) { static struct intr_info tp_intr_info[] = { { 0xffffff, "TP parity error", -1, 1 }, { 0x1000000, "TP out of Rx pages", -1, 1 }, { 0x2000000, "TP out of Tx pages", -1, 1 }, { 0 } }; static struct intr_info tp_intr_info_t3c[] = { { 0x1fffffff, "TP parity error", -1, 1 }, { F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1 }, { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff, adapter->params.rev < T3_REV_C ? tp_intr_info : tp_intr_info_t3c, NULL)) t3_fatal_err(adapter); } /* * CIM interrupt handler. */ static void cim_intr_handler(adapter_t *adapter) { static struct intr_info cim_intr_info[] = { { F_RSVDSPACEINT, "CIM reserved space write", -1, 1 }, { F_SDRAMRANGEINT, "CIM SDRAM address out of range", -1, 1 }, { F_FLASHRANGEINT, "CIM flash address out of range", -1, 1 }, { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, { F_WRBLKFLASHINT, "CIM write to cached flash space", -1, 1 }, { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, { F_BLKRDFLASHINT, "CIM block read from flash space", -1, 1 }, { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, { F_BLKRDCTLINT, "CIM block read from CTL space", -1, 1 }, { F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1 }, { F_BLKRDPLINT, "CIM block read from PL space", -1, 1 }, { F_BLKWRPLINT, "CIM block write to PL space", -1, 1 }, { F_DRAMPARERR, "CIM DRAM parity error", -1, 1 }, { F_ICACHEPARERR, "CIM icache parity error", -1, 1 }, { F_DCACHEPARERR, "CIM dcache parity error", -1, 1 }, { F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1 }, { F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1 }, { F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1 }, { F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1 }, { F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1 }, { F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1 }, { F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1 }, { F_ITAGPARERR, "CIM itag parity error", -1, 1 }, { F_DTAGPARERR, "CIM dtag parity error", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, CIM_INTR_MASK, cim_intr_info, NULL)) t3_fatal_err(adapter); } /* * ULP RX interrupt handler. */ static void ulprx_intr_handler(adapter_t *adapter) { static struct intr_info ulprx_intr_info[] = { { F_PARERRDATA, "ULP RX data parity error", -1, 1 }, { F_PARERRPCMD, "ULP RX command parity error", -1, 1 }, { F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1 }, { F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1 }, { F_ARBFPERR, "ULP RX ArbF parity error", -1, 1 }, { F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1 }, { F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1 }, { F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff, ulprx_intr_info, NULL)) t3_fatal_err(adapter); } /* * ULP TX interrupt handler. */ static void ulptx_intr_handler(adapter_t *adapter) { static struct intr_info ulptx_intr_info[] = { { F_PBL_BOUND_ERR_CH0, "ULP TX channel 0 PBL out of bounds", STAT_ULP_CH0_PBL_OOB, 0 }, { F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds", STAT_ULP_CH1_PBL_OOB, 0 }, { 0xfc, "ULP TX parity error", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff, ulptx_intr_info, adapter->irq_stats)) t3_fatal_err(adapter); } #define ICSPI_FRM_ERR (F_ICSPI0_FIFO2X_RX_FRAMING_ERROR | \ F_ICSPI1_FIFO2X_RX_FRAMING_ERROR | F_ICSPI0_RX_FRAMING_ERROR | \ F_ICSPI1_RX_FRAMING_ERROR | F_ICSPI0_TX_FRAMING_ERROR | \ F_ICSPI1_TX_FRAMING_ERROR) #define OESPI_FRM_ERR (F_OESPI0_RX_FRAMING_ERROR | \ F_OESPI1_RX_FRAMING_ERROR | F_OESPI0_TX_FRAMING_ERROR | \ F_OESPI1_TX_FRAMING_ERROR | F_OESPI0_OFIFO2X_TX_FRAMING_ERROR | \ F_OESPI1_OFIFO2X_TX_FRAMING_ERROR) /* * PM TX interrupt handler. */ static void pmtx_intr_handler(adapter_t *adapter) { static struct intr_info pmtx_intr_info[] = { { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, { ICSPI_FRM_ERR, "PMTX ispi framing error", -1, 1 }, { OESPI_FRM_ERR, "PMTX ospi framing error", -1, 1 }, { V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR), "PMTX ispi parity error", -1, 1 }, { V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR), "PMTX ospi parity error", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff, pmtx_intr_info, NULL)) t3_fatal_err(adapter); } #define IESPI_FRM_ERR (F_IESPI0_FIFO2X_RX_FRAMING_ERROR | \ F_IESPI1_FIFO2X_RX_FRAMING_ERROR | F_IESPI0_RX_FRAMING_ERROR | \ F_IESPI1_RX_FRAMING_ERROR | F_IESPI0_TX_FRAMING_ERROR | \ F_IESPI1_TX_FRAMING_ERROR) #define OCSPI_FRM_ERR (F_OCSPI0_RX_FRAMING_ERROR | \ F_OCSPI1_RX_FRAMING_ERROR | F_OCSPI0_TX_FRAMING_ERROR | \ F_OCSPI1_TX_FRAMING_ERROR | F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR | \ F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR) /* * PM RX interrupt handler. */ static void pmrx_intr_handler(adapter_t *adapter) { static struct intr_info pmrx_intr_info[] = { { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, { IESPI_FRM_ERR, "PMRX ispi framing error", -1, 1 }, { OCSPI_FRM_ERR, "PMRX ospi framing error", -1, 1 }, { V_IESPI_PAR_ERROR(M_IESPI_PAR_ERROR), "PMRX ispi parity error", -1, 1 }, { V_OCSPI_PAR_ERROR(M_OCSPI_PAR_ERROR), "PMRX ospi parity error", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff, pmrx_intr_info, NULL)) t3_fatal_err(adapter); } /* * CPL switch interrupt handler. */ static void cplsw_intr_handler(adapter_t *adapter) { static struct intr_info cplsw_intr_info[] = { { F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1 }, { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 }, { F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1 }, { F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1 }, { F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1 }, { F_ZERO_SWITCH_ERROR, "CPL switch no-switch error", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff, cplsw_intr_info, NULL)) t3_fatal_err(adapter); } /* * MPS interrupt handler. */ static void mps_intr_handler(adapter_t *adapter) { static struct intr_info mps_intr_info[] = { { 0x1ff, "MPS parity error", -1, 1 }, { 0 } }; if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff, mps_intr_info, NULL)) t3_fatal_err(adapter); } #define MC7_INTR_FATAL (F_UE | V_PE(M_PE) | F_AE) /* * MC7 interrupt handler. */ static void mc7_intr_handler(struct mc7 *mc7) { adapter_t *adapter = mc7->adapter; u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE); if (cause & F_CE) { mc7->stats.corr_err++; CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, " "data 0x%x 0x%x 0x%x\n", mc7->name, t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR), t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0), t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1), t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2)); } if (cause & F_UE) { mc7->stats.uncorr_err++; CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, " "data 0x%x 0x%x 0x%x\n", mc7->name, t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR), t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0), t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1), t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2)); } if (G_PE(cause)) { mc7->stats.parity_err++; CH_ALERT(adapter, "%s MC7 parity error 0x%x\n", mc7->name, G_PE(cause)); } if (cause & F_AE) { u32 addr = 0; if (adapter->params.rev > 0) addr = t3_read_reg(adapter, mc7->offset + A_MC7_ERR_ADDR); mc7->stats.addr_err++; CH_ALERT(adapter, "%s MC7 address error: 0x%x\n", mc7->name, addr); } if (cause & MC7_INTR_FATAL) t3_fatal_err(adapter); t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause); } #define XGM_INTR_FATAL (V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR) | \ V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR)) /* * XGMAC interrupt handler. */ static int mac_intr_handler(adapter_t *adap, unsigned int idx) { u32 cause; struct port_info *pi; struct cmac *mac; idx = idx == 0 ? 0 : adapter_info(adap)->nports0; /* MAC idx -> port */ pi = adap2pinfo(adap, idx); mac = &pi->mac; /* * We mask out interrupt causes for which we're not taking interrupts. * This allows us to use polling logic to monitor some of the other * conditions when taking interrupts would impose too much load on the * system. */ cause = (t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset) & ~(F_RXFIFO_OVERFLOW)); if (cause & V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR)) { mac->stats.tx_fifo_parity_err++; CH_ALERT(adap, "port%d: MAC TX FIFO parity error\n", idx); } if (cause & V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR)) { mac->stats.rx_fifo_parity_err++; CH_ALERT(adap, "port%d: MAC RX FIFO parity error\n", idx); } if (cause & F_TXFIFO_UNDERRUN) mac->stats.tx_fifo_urun++; if (cause & F_RXFIFO_OVERFLOW) mac->stats.rx_fifo_ovfl++; if (cause & V_SERDES_LOS(M_SERDES_LOS)) mac->stats.serdes_signal_loss++; if (cause & F_XAUIPCSCTCERR) mac->stats.xaui_pcs_ctc_err++; if (cause & F_XAUIPCSALIGNCHANGE) mac->stats.xaui_pcs_align_change++; if (cause & F_XGM_INT & t3_read_reg(adap, A_XGM_INT_ENABLE + mac->offset)) { t3_set_reg_field(adap, A_XGM_INT_ENABLE + mac->offset, F_XGM_INT, 0); /* link fault suspected */ pi->link_fault = LF_MAYBE; t3_os_link_intr(pi); } - t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause); - if (cause & XGM_INTR_FATAL) t3_fatal_err(adap); + t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause); return cause != 0; } /* * Interrupt handler for PHY events. */ static int phy_intr_handler(adapter_t *adapter) { u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE); for_each_port(adapter, i) { struct port_info *p = adap2pinfo(adapter, i); if (!(p->phy.caps & SUPPORTED_IRQ)) continue; if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) { int phy_cause = p->phy.ops->intr_handler(&p->phy); if (phy_cause & cphy_cause_link_change) t3_os_link_intr(p); if (phy_cause & cphy_cause_fifo_error) p->phy.fifo_errors++; if (phy_cause & cphy_cause_module_change) t3_os_phymod_changed(adapter, i); if (phy_cause & cphy_cause_alarm) CH_WARN(adapter, "Operation affected due to " "adverse environment. Check the spec " "sheet for corrective action."); } } t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause); return 0; } /** * t3_slow_intr_handler - control path interrupt handler * @adapter: the adapter * * T3 interrupt handler for non-data interrupt events, e.g., errors. * The designation 'slow' is because it involves register reads, while * data interrupts typically don't involve any MMIOs. */ int t3_slow_intr_handler(adapter_t *adapter) { u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0); cause &= adapter->slow_intr_mask; if (!cause) return 0; if (cause & F_PCIM0) { if (is_pcie(adapter)) pcie_intr_handler(adapter); else pci_intr_handler(adapter); } if (cause & F_SGE3) t3_sge_err_intr_handler(adapter); if (cause & F_MC7_PMRX) mc7_intr_handler(&adapter->pmrx); if (cause & F_MC7_PMTX) mc7_intr_handler(&adapter->pmtx); if (cause & F_MC7_CM) mc7_intr_handler(&adapter->cm); if (cause & F_CIM) cim_intr_handler(adapter); if (cause & F_TP1) tp_intr_handler(adapter); if (cause & F_ULP2_RX) ulprx_intr_handler(adapter); if (cause & F_ULP2_TX) ulptx_intr_handler(adapter); if (cause & F_PM1_RX) pmrx_intr_handler(adapter); if (cause & F_PM1_TX) pmtx_intr_handler(adapter); if (cause & F_CPL_SWITCH) cplsw_intr_handler(adapter); if (cause & F_MPS0) mps_intr_handler(adapter); if (cause & F_MC5A) t3_mc5_intr_handler(&adapter->mc5); if (cause & F_XGMAC0_0) mac_intr_handler(adapter, 0); if (cause & F_XGMAC0_1) mac_intr_handler(adapter, 1); if (cause & F_T3DBG) phy_intr_handler(adapter); /* Clear the interrupts just processed. */ t3_write_reg(adapter, A_PL_INT_CAUSE0, cause); (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ return 1; } static unsigned int calc_gpio_intr(adapter_t *adap) { unsigned int i, gpi_intr = 0; for_each_port(adap, i) if ((adap2pinfo(adap, i)->phy.caps & SUPPORTED_IRQ) && adapter_info(adap)->gpio_intr[i]) gpi_intr |= 1 << adapter_info(adap)->gpio_intr[i]; return gpi_intr; } /** * t3_intr_enable - enable interrupts * @adapter: the adapter whose interrupts should be enabled * * Enable interrupts by setting the interrupt enable registers of the * various HW modules and then enabling the top-level interrupt * concentrator. */ void t3_intr_enable(adapter_t *adapter) { static struct addr_val_pair intr_en_avp[] = { { A_MC7_INT_ENABLE, MC7_INTR_MASK }, { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR, MC7_INTR_MASK }, { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR, MC7_INTR_MASK }, { A_MC5_DB_INT_ENABLE, MC5_INTR_MASK }, { A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK }, { A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK }, { A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK }, { A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK }, { A_MPS_INT_ENABLE, MPS_INTR_MASK }, }; adapter->slow_intr_mask = PL_INTR_MASK; t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0); t3_write_reg(adapter, A_TP_INT_ENABLE, adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff); t3_write_reg(adapter, A_SG_INT_ENABLE, SGE_INTR_MASK); if (adapter->params.rev > 0) { t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK | F_CIM_OVFL_ERROR); t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 | F_PBL_BOUND_ERR_CH1); } else { t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK); t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK); } t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter)); if (is_pcie(adapter)) t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK); else t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK); t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask); (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ } /** * t3_intr_disable - disable a card's interrupts * @adapter: the adapter whose interrupts should be disabled * * Disable interrupts. We only disable the top-level interrupt * concentrator and the SGE data interrupts. */ void t3_intr_disable(adapter_t *adapter) { t3_write_reg(adapter, A_PL_INT_ENABLE0, 0); (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ adapter->slow_intr_mask = 0; } /** * t3_intr_clear - clear all interrupts * @adapter: the adapter whose interrupts should be cleared * * Clears all interrupts. */ void t3_intr_clear(adapter_t *adapter) { static const unsigned int cause_reg_addr[] = { A_SG_INT_CAUSE, A_SG_RSPQ_FL_STATUS, A_PCIX_INT_CAUSE, A_MC7_INT_CAUSE, A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR, A_MC7_INT_CAUSE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR, A_CIM_HOST_INT_CAUSE, A_TP_INT_CAUSE, A_MC5_DB_INT_CAUSE, A_ULPRX_INT_CAUSE, A_ULPTX_INT_CAUSE, A_CPL_INTR_CAUSE, A_PM1_TX_INT_CAUSE, A_PM1_RX_INT_CAUSE, A_MPS_INT_CAUSE, A_T3DBG_INT_CAUSE, }; unsigned int i; /* Clear PHY and MAC interrupts for each port. */ for_each_port(adapter, i) t3_port_intr_clear(adapter, i); for (i = 0; i < ARRAY_SIZE(cause_reg_addr); ++i) t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff); if (is_pcie(adapter)) t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff); t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff); (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ } void t3_xgm_intr_enable(adapter_t *adapter, int idx) { struct port_info *pi = adap2pinfo(adapter, idx); t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset, XGM_EXTRA_INTR_MASK); } void t3_xgm_intr_disable(adapter_t *adapter, int idx) { struct port_info *pi = adap2pinfo(adapter, idx); t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset, 0x7ff); } /** * t3_port_intr_enable - enable port-specific interrupts * @adapter: associated adapter * @idx: index of port whose interrupts should be enabled * * Enable port-specific (i.e., MAC and PHY) interrupts for the given * adapter port. */ void t3_port_intr_enable(adapter_t *adapter, int idx) { struct port_info *pi = adap2pinfo(adapter, idx); t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, XGM_INTR_MASK); pi->phy.ops->intr_enable(&pi->phy); } /** * t3_port_intr_disable - disable port-specific interrupts * @adapter: associated adapter * @idx: index of port whose interrupts should be disabled * * Disable port-specific (i.e., MAC and PHY) interrupts for the given * adapter port. */ void t3_port_intr_disable(adapter_t *adapter, int idx) { struct port_info *pi = adap2pinfo(adapter, idx); t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, 0); pi->phy.ops->intr_disable(&pi->phy); } /** * t3_port_intr_clear - clear port-specific interrupts * @adapter: associated adapter * @idx: index of port whose interrupts to clear * * Clear port-specific (i.e., MAC and PHY) interrupts for the given * adapter port. */ void t3_port_intr_clear(adapter_t *adapter, int idx) { struct port_info *pi = adap2pinfo(adapter, idx); t3_write_reg(adapter, A_XGM_INT_CAUSE + pi->mac.offset, 0xffffffff); pi->phy.ops->intr_clear(&pi->phy); } #define SG_CONTEXT_CMD_ATTEMPTS 100 /** * t3_sge_write_context - write an SGE context * @adapter: the adapter * @id: the context id * @type: the context type * * Program an SGE context with the values already loaded in the * CONTEXT_DATA? registers. */ static int t3_sge_write_context(adapter_t *adapter, unsigned int id, unsigned int type) { if (type == F_RESPONSEQ) { /* * Can't write the Response Queue Context bits for * Interrupt Armed or the Reserve bits after the chip * has been initialized out of reset. Writing to these * bits can confuse the hardware. */ t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff); t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); } else { t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff); t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); } t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id)); return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1); } /** * clear_sge_ctxt - completely clear an SGE context * @adapter: the adapter * @id: the context id * @type: the context type * * Completely clear an SGE context. Used predominantly at post-reset * initialization. Note in particular that we don't skip writing to any * "sensitive bits" in the contexts the way that t3_sge_write_context() * does ... */ static int clear_sge_ctxt(adapter_t *adap, unsigned int id, unsigned int type) { t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0); t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0); t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0); t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0); t3_write_reg(adap, A_SG_CONTEXT_MASK0, 0xffffffff); t3_write_reg(adap, A_SG_CONTEXT_MASK1, 0xffffffff); t3_write_reg(adap, A_SG_CONTEXT_MASK2, 0xffffffff); t3_write_reg(adap, A_SG_CONTEXT_MASK3, 0xffffffff); t3_write_reg(adap, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id)); return t3_wait_op_done(adap, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1); } /** * t3_sge_init_ecntxt - initialize an SGE egress context * @adapter: the adapter to configure * @id: the context id * @gts_enable: whether to enable GTS for the context * @type: the egress context type * @respq: associated response queue * @base_addr: base address of queue * @size: number of queue entries * @token: uP token * @gen: initial generation value for the context * @cidx: consumer pointer * * Initialize an SGE egress context and make it ready for use. If the * platform allows concurrent context operations, the caller is * responsible for appropriate locking. */ int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, enum sge_context_type type, int respq, u64 base_addr, unsigned int size, unsigned int token, int gen, unsigned int cidx) { unsigned int credits = type == SGE_CNTXT_OFLD ? 0 : FW_WR_NUM; if (base_addr & 0xfff) /* must be 4K aligned */ return -EINVAL; if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; base_addr >>= 12; t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) | V_EC_CREDITS(credits) | V_EC_GTS(gts_enable)); t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) | V_EC_BASE_LO((u32)base_addr & 0xffff)); base_addr >>= 16; t3_write_reg(adapter, A_SG_CONTEXT_DATA2, (u32)base_addr); base_addr >>= 32; t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_BASE_HI((u32)base_addr & 0xf) | V_EC_RESPQ(respq) | V_EC_TYPE(type) | V_EC_GEN(gen) | V_EC_UP_TOKEN(token) | F_EC_VALID); return t3_sge_write_context(adapter, id, F_EGRESS); } /** * t3_sge_init_flcntxt - initialize an SGE free-buffer list context * @adapter: the adapter to configure * @id: the context id * @gts_enable: whether to enable GTS for the context * @base_addr: base address of queue * @size: number of queue entries * @bsize: size of each buffer for this queue * @cong_thres: threshold to signal congestion to upstream producers * @gen: initial generation value for the context * @cidx: consumer pointer * * Initialize an SGE free list context and make it ready for use. The * caller is responsible for ensuring only one context operation occurs * at a time. */ int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, u64 base_addr, unsigned int size, unsigned int bsize, unsigned int cong_thres, int gen, unsigned int cidx) { if (base_addr & 0xfff) /* must be 4K aligned */ return -EINVAL; if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; base_addr >>= 12; t3_write_reg(adapter, A_SG_CONTEXT_DATA0, (u32)base_addr); base_addr >>= 32; t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_FL_BASE_HI((u32)base_addr) | V_FL_INDEX_LO(cidx & M_FL_INDEX_LO)); t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) | V_FL_GEN(gen) | V_FL_INDEX_HI(cidx >> 12) | V_FL_ENTRY_SIZE_LO(bsize & M_FL_ENTRY_SIZE_LO)); t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_FL_ENTRY_SIZE_HI(bsize >> (32 - S_FL_ENTRY_SIZE_LO)) | V_FL_CONG_THRES(cong_thres) | V_FL_GTS(gts_enable)); return t3_sge_write_context(adapter, id, F_FREELIST); } /** * t3_sge_init_rspcntxt - initialize an SGE response queue context * @adapter: the adapter to configure * @id: the context id * @irq_vec_idx: MSI-X interrupt vector index, 0 if no MSI-X, -1 if no IRQ * @base_addr: base address of queue * @size: number of queue entries * @fl_thres: threshold for selecting the normal or jumbo free list * @gen: initial generation value for the context * @cidx: consumer pointer * * Initialize an SGE response queue context and make it ready for use. * The caller is responsible for ensuring only one context operation * occurs at a time. */ int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, u64 base_addr, unsigned int size, unsigned int fl_thres, int gen, unsigned int cidx) { unsigned int ctrl, intr = 0; if (base_addr & 0xfff) /* must be 4K aligned */ return -EINVAL; if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; base_addr >>= 12; t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) | V_CQ_INDEX(cidx)); t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr); base_addr >>= 32; ctrl = t3_read_reg(adapter, A_SG_CONTROL); if ((irq_vec_idx > 0) || ((irq_vec_idx == 0) && !(ctrl & F_ONEINTMULTQ))) intr = F_RQ_INTR_EN; if (irq_vec_idx >= 0) intr |= V_RQ_MSI_VEC(irq_vec_idx); t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_CQ_BASE_HI((u32)base_addr) | intr | V_RQ_GEN(gen)); t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres); return t3_sge_write_context(adapter, id, F_RESPONSEQ); } /** * t3_sge_init_cqcntxt - initialize an SGE completion queue context * @adapter: the adapter to configure * @id: the context id * @base_addr: base address of queue * @size: number of queue entries * @rspq: response queue for async notifications * @ovfl_mode: CQ overflow mode * @credits: completion queue credits * @credit_thres: the credit threshold * * Initialize an SGE completion queue context and make it ready for use. * The caller is responsible for ensuring only one context operation * occurs at a time. */ int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, unsigned int size, int rspq, int ovfl_mode, unsigned int credits, unsigned int credit_thres) { if (base_addr & 0xfff) /* must be 4K aligned */ return -EINVAL; if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; base_addr >>= 12; t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size)); t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr); base_addr >>= 32; t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_CQ_BASE_HI((u32)base_addr) | V_CQ_RSPQ(rspq) | V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode) | V_CQ_ERR(ovfl_mode)); t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) | V_CQ_CREDIT_THRES(credit_thres)); return t3_sge_write_context(adapter, id, F_CQ); } /** * t3_sge_enable_ecntxt - enable/disable an SGE egress context * @adapter: the adapter * @id: the egress context id * @enable: enable (1) or disable (0) the context * * Enable or disable an SGE egress context. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable) { if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID); t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable)); t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(1) | F_EGRESS | V_CONTEXT(id)); return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1); } /** * t3_sge_disable_fl - disable an SGE free-buffer list * @adapter: the adapter * @id: the free list context id * * Disable an SGE free-buffer list. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_disable_fl(adapter_t *adapter, unsigned int id) { if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE)); t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0); t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(1) | F_FREELIST | V_CONTEXT(id)); return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1); } /** * t3_sge_disable_rspcntxt - disable an SGE response queue * @adapter: the adapter * @id: the response queue context id * * Disable an SGE response queue. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id) { if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(1) | F_RESPONSEQ | V_CONTEXT(id)); return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1); } /** * t3_sge_disable_cqcntxt - disable an SGE completion queue * @adapter: the adapter * @id: the completion queue context id * * Disable an SGE completion queue. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id) { if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(1) | F_CQ | V_CONTEXT(id)); return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1); } /** * t3_sge_cqcntxt_op - perform an operation on a completion queue context * @adapter: the adapter * @id: the context id * @op: the operation to perform * @credits: credits to return to the CQ * * Perform the selected operation on an SGE completion queue context. * The caller is responsible for ensuring only one context operation * occurs at a time. * * For most operations the function returns the current HW position in * the completion queue. */ int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, unsigned int credits) { u32 val; if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16); t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) | V_CONTEXT(id) | F_CQ); if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1, &val)) return -EIO; if (op >= 2 && op < 7) { if (adapter->params.rev > 0) return G_CQ_INDEX(val); t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(0) | F_CQ | V_CONTEXT(id)); if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1)) return -EIO; return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0)); } return 0; } /** * t3_sge_read_context - read an SGE context * @type: the context type * @adapter: the adapter * @id: the context id * @data: holds the retrieved context * * Read an SGE egress context. The caller is responsible for ensuring * only one context operation occurs at a time. */ static int t3_sge_read_context(unsigned int type, adapter_t *adapter, unsigned int id, u32 data[4]) { if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(0) | type | V_CONTEXT(id)); if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, SG_CONTEXT_CMD_ATTEMPTS, 1)) return -EIO; data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0); data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1); data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2); data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3); return 0; } /** * t3_sge_read_ecntxt - read an SGE egress context * @adapter: the adapter * @id: the context id * @data: holds the retrieved context * * Read an SGE egress context. The caller is responsible for ensuring * only one context operation occurs at a time. */ int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]) { if (id >= 65536) return -EINVAL; return t3_sge_read_context(F_EGRESS, adapter, id, data); } /** * t3_sge_read_cq - read an SGE CQ context * @adapter: the adapter * @id: the context id * @data: holds the retrieved context * * Read an SGE CQ context. The caller is responsible for ensuring * only one context operation occurs at a time. */ int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]) { if (id >= 65536) return -EINVAL; return t3_sge_read_context(F_CQ, adapter, id, data); } /** * t3_sge_read_fl - read an SGE free-list context * @adapter: the adapter * @id: the context id * @data: holds the retrieved context * * Read an SGE free-list context. The caller is responsible for ensuring * only one context operation occurs at a time. */ int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]) { if (id >= SGE_QSETS * 2) return -EINVAL; return t3_sge_read_context(F_FREELIST, adapter, id, data); } /** * t3_sge_read_rspq - read an SGE response queue context * @adapter: the adapter * @id: the context id * @data: holds the retrieved context * * Read an SGE response queue context. The caller is responsible for * ensuring only one context operation occurs at a time. */ int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]) { if (id >= SGE_QSETS) return -EINVAL; return t3_sge_read_context(F_RESPONSEQ, adapter, id, data); } /** * t3_config_rss - configure Rx packet steering * @adapter: the adapter * @rss_config: RSS settings (written to TP_RSS_CONFIG) * @cpus: values for the CPU lookup table (0xff terminated) * @rspq: values for the response queue lookup table (0xffff terminated) * * Programs the receive packet steering logic. @cpus and @rspq provide * the values for the CPU and response queue lookup tables. If they * provide fewer values than the size of the tables the supplied values * are used repeatedly until the tables are fully populated. */ void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, const u16 *rspq) { int i, j, cpu_idx = 0, q_idx = 0; if (cpus) for (i = 0; i < RSS_TABLE_SIZE; ++i) { u32 val = i << 16; for (j = 0; j < 2; ++j) { val |= (cpus[cpu_idx++] & 0x3f) << (8 * j); if (cpus[cpu_idx] == 0xff) cpu_idx = 0; } t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val); } if (rspq) for (i = 0; i < RSS_TABLE_SIZE; ++i) { t3_write_reg(adapter, A_TP_RSS_MAP_TABLE, (i << 16) | rspq[q_idx++]); if (rspq[q_idx] == 0xffff) q_idx = 0; } t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config); } /** * t3_read_rss - read the contents of the RSS tables * @adapter: the adapter * @lkup: holds the contents of the RSS lookup table * @map: holds the contents of the RSS map table * * Reads the contents of the receive packet steering tables. */ int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map) { int i; u32 val; if (lkup) for (i = 0; i < RSS_TABLE_SIZE; ++i) { t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, 0xffff0000 | i); val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE); if (!(val & 0x80000000)) return -EAGAIN; *lkup++ = (u8)val; *lkup++ = (u8)(val >> 8); } if (map) for (i = 0; i < RSS_TABLE_SIZE; ++i) { t3_write_reg(adapter, A_TP_RSS_MAP_TABLE, 0xffff0000 | i); val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE); if (!(val & 0x80000000)) return -EAGAIN; *map++ = (u16)val; } return 0; } /** * t3_tp_set_offload_mode - put TP in NIC/offload mode * @adap: the adapter * @enable: 1 to select offload mode, 0 for regular NIC * * Switches TP to NIC/offload mode. */ void t3_tp_set_offload_mode(adapter_t *adap, int enable) { if (is_offload(adap) || !enable) t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, V_NICMODE(!enable)); } /** * tp_wr_bits_indirect - set/clear bits in an indirect TP register * @adap: the adapter * @addr: the indirect TP register address * @mask: specifies the field within the register to modify * @val: new value for the field * * Sets a field of an indirect TP register to the given value. */ static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr, unsigned int mask, unsigned int val) { t3_write_reg(adap, A_TP_PIO_ADDR, addr); val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask; t3_write_reg(adap, A_TP_PIO_DATA, val); } /** * t3_enable_filters - enable the HW filters * @adap: the adapter * * Enables the HW filters for NIC traffic. */ void t3_enable_filters(adapter_t *adap) { t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0); t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN); t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3)); tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT); } /** * t3_disable_filters - disable the HW filters * @adap: the adapter * * Disables the HW filters for NIC traffic. */ void t3_disable_filters(adapter_t *adap) { /* note that we don't want to revert to NIC-only mode */ t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_FILTEREN, 0); t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, V_FIVETUPLELOOKUP(M_FIVETUPLELOOKUP), 0); tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, F_LOOKUPEVERYPKT, 0); } /** * pm_num_pages - calculate the number of pages of the payload memory * @mem_size: the size of the payload memory * @pg_size: the size of each payload memory page * * Calculate the number of pages, each of the given size, that fit in a * memory of the specified size, respecting the HW requirement that the * number of pages must be a multiple of 24. */ static inline unsigned int pm_num_pages(unsigned int mem_size, unsigned int pg_size) { unsigned int n = mem_size / pg_size; return n - n % 24; } #define mem_region(adap, start, size, reg) \ t3_write_reg((adap), A_ ## reg, (start)); \ start += size /** * partition_mem - partition memory and configure TP memory settings * @adap: the adapter * @p: the TP parameters * * Partitions context and payload memory and configures TP's memory * registers. */ static void partition_mem(adapter_t *adap, const struct tp_params *p) { unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5); unsigned int timers = 0, timers_shift = 22; if (adap->params.rev > 0) { if (tids <= 16 * 1024) { timers = 1; timers_shift = 16; } else if (tids <= 64 * 1024) { timers = 2; timers_shift = 18; } else if (tids <= 256 * 1024) { timers = 3; timers_shift = 20; } } t3_write_reg(adap, A_TP_PMM_SIZE, p->chan_rx_size | (p->chan_tx_size >> 16)); t3_write_reg(adap, A_TP_PMM_TX_BASE, 0); t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size); t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs); t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX), V_TXDATAACKIDX(fls(p->tx_pg_size) - 12)); t3_write_reg(adap, A_TP_PMM_RX_BASE, 0); t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size); t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs); pstructs = p->rx_num_pgs + p->tx_num_pgs; /* Add a bit of headroom and make multiple of 24 */ pstructs += 48; pstructs -= pstructs % 24; t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs); m = tids * TCB_SIZE; mem_region(adap, m, (64 << 10) * 64, SG_EGR_CNTX_BADDR); mem_region(adap, m, (64 << 10) * 64, SG_CQ_CONTEXT_BADDR); t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m); m += ((p->ntimer_qs - 1) << timers_shift) + (1 << 22); mem_region(adap, m, pstructs * 64, TP_CMM_MM_BASE); mem_region(adap, m, 64 * (pstructs / 24), TP_CMM_MM_PS_FLST_BASE); mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE); mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE); m = (m + 4095) & ~0xfff; t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m); t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m); tids = (p->cm_size - m - (3 << 20)) / 3072 - 32; m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers - adap->params.mc5.nfilters - adap->params.mc5.nroutes; if (tids < m) adap->params.mc5.nservers += m - tids; } static inline void tp_wr_indirect(adapter_t *adap, unsigned int addr, u32 val) { t3_write_reg(adap, A_TP_PIO_ADDR, addr); t3_write_reg(adap, A_TP_PIO_DATA, val); } static inline u32 tp_rd_indirect(adapter_t *adap, unsigned int addr) { t3_write_reg(adap, A_TP_PIO_ADDR, addr); return t3_read_reg(adap, A_TP_PIO_DATA); } static void tp_config(adapter_t *adap, const struct tp_params *p) { t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU | F_IPCHECKSUMOFFLOAD | F_UDPCHECKSUMOFFLOAD | F_TCPCHECKSUMOFFLOAD | V_IPTTL(64)); t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) | F_MTUENABLE | V_WINDOWSCALEMODE(1) | V_TIMESTAMPSMODE(1) | V_SACKMODE(1) | V_SACKRX(1)); t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) | V_AUTOSTATE2(1) | V_AUTOSTATE1(0) | V_BYTETHRESHOLD(26880) | V_MSSTHRESHOLD(2) | F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1)); t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO, F_IPV6ENABLE | F_NICMODE); t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814); t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105); t3_set_reg_field(adap, A_TP_PARA_REG6, 0, adap->params.rev > 0 ? F_ENABLEESND : F_T3A_ENABLEESND); t3_set_reg_field(adap, A_TP_PC_CONFIG, F_ENABLEEPCMDAFULL, F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK | F_TXCONGESTIONMODE | F_RXCONGESTIONMODE); t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, F_ENABLEIPV6RSS | F_ENABLENONOFDTNLSYN | F_ENABLEARPMISS | F_DISBLEDAPARBIT0); t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080); t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000); if (adap->params.rev > 0) { tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE); t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTO | F_TXPACEAUTOSTRICT); t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID); tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50); tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688); tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688); } else t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED); if (adap->params.rev == T3_REV_C) t3_set_reg_field(adap, A_TP_PC_CONFIG, V_TABLELATENCYDELTA(M_TABLELATENCYDELTA), V_TABLELATENCYDELTA(4)); t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0); t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0); t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0); t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000); if (adap->params.nports > 2) { t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0, F_ENABLETXPORTFROMDA2 | F_ENABLETXPORTFROMDA | F_ENABLERXPORTFROMADDR); tp_wr_bits_indirect(adap, A_TP_QOS_RX_MAP_MODE, V_RXMAPMODE(M_RXMAPMODE), 0); tp_wr_indirect(adap, A_TP_INGRESS_CONFIG, V_BITPOS0(48) | V_BITPOS1(49) | V_BITPOS2(50) | V_BITPOS3(51) | F_ENABLEEXTRACT | F_ENABLEEXTRACTIONSFD | F_ENABLEINSERTION | F_ENABLEINSERTIONSFD); tp_wr_indirect(adap, A_TP_PREAMBLE_MSB, 0xfb000000); tp_wr_indirect(adap, A_TP_PREAMBLE_LSB, 0xd5); tp_wr_indirect(adap, A_TP_INTF_FROM_TX_PKT, F_INTFFROMTXPKT); } } /* TCP timer values in ms */ #define TP_DACK_TIMER 50 #define TP_RTO_MIN 250 /** * tp_set_timers - set TP timing parameters * @adap: the adapter to set * @core_clk: the core clock frequency in Hz * * Set TP's timing parameters, such as the various timer resolutions and * the TCP timer values. */ static void tp_set_timers(adapter_t *adap, unsigned int core_clk) { unsigned int tre = adap->params.tp.tre; unsigned int dack_re = adap->params.tp.dack_re; unsigned int tstamp_re = fls(core_clk / 1000); /* 1ms, at least */ unsigned int tps = core_clk >> tre; t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) | V_DELAYEDACKRESOLUTION(dack_re) | V_TIMESTAMPRESOLUTION(tstamp_re)); t3_write_reg(adap, A_TP_DACK_TIMER, (core_clk >> dack_re) / (1000 / TP_DACK_TIMER)); t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100); t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504); t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908); t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c); t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) | V_RXTSHIFTMAXR1(4) | V_RXTSHIFTMAXR2(15) | V_PERSHIFTBACKOFFMAX(8) | V_PERSHIFTMAX(8) | V_KEEPALIVEMAX(9)); #define SECONDS * tps t3_write_reg(adap, A_TP_MSL, adap->params.rev > 0 ? 0 : 2 SECONDS); t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN)); t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS); t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS); t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS); t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS); t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS); t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS); t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS); #undef SECONDS } #ifdef CONFIG_CHELSIO_T3_CORE /** * t3_tp_set_coalescing_size - set receive coalescing size * @adap: the adapter * @size: the receive coalescing size * @psh: whether a set PSH bit should deliver coalesced data * * Set the receive coalescing size and PSH bit handling. */ int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh) { u32 val; if (size > MAX_RX_COALESCING_LEN) return -EINVAL; val = t3_read_reg(adap, A_TP_PARA_REG3); val &= ~(F_RXCOALESCEENABLE | F_RXCOALESCEPSHEN); if (size) { val |= F_RXCOALESCEENABLE; if (psh) val |= F_RXCOALESCEPSHEN; size = min(MAX_RX_COALESCING_LEN, size); t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) | V_MAXRXDATA(MAX_RX_COALESCING_LEN)); } t3_write_reg(adap, A_TP_PARA_REG3, val); return 0; } /** * t3_tp_set_max_rxsize - set the max receive size * @adap: the adapter * @size: the max receive size * * Set TP's max receive size. This is the limit that applies when * receive coalescing is disabled. */ void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size) { t3_write_reg(adap, A_TP_PARA_REG7, V_PMMAXXFERLEN0(size) | V_PMMAXXFERLEN1(size)); } static void __devinit init_mtus(unsigned short mtus[]) { /* * See draft-mathis-plpmtud-00.txt for the values. The min is 88 so * it can accomodate max size TCP/IP headers when SACK and timestamps * are enabled and still have at least 8 bytes of payload. */ mtus[0] = 88; mtus[1] = 88; mtus[2] = 256; mtus[3] = 512; mtus[4] = 576; mtus[5] = 1024; mtus[6] = 1280; mtus[7] = 1492; mtus[8] = 1500; mtus[9] = 2002; mtus[10] = 2048; mtus[11] = 4096; mtus[12] = 4352; mtus[13] = 8192; mtus[14] = 9000; mtus[15] = 9600; } /** * init_cong_ctrl - initialize congestion control parameters * @a: the alpha values for congestion control * @b: the beta values for congestion control * * Initialize the congestion control parameters. */ static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b) { a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; a[9] = 2; a[10] = 3; a[11] = 4; a[12] = 5; a[13] = 6; a[14] = 7; a[15] = 8; a[16] = 9; a[17] = 10; a[18] = 14; a[19] = 17; a[20] = 21; a[21] = 25; a[22] = 30; a[23] = 35; a[24] = 45; a[25] = 60; a[26] = 80; a[27] = 100; a[28] = 200; a[29] = 300; a[30] = 400; a[31] = 500; b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; b[9] = b[10] = 1; b[11] = b[12] = 2; b[13] = b[14] = b[15] = b[16] = 3; b[17] = b[18] = b[19] = b[20] = b[21] = 4; b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; b[28] = b[29] = 6; b[30] = b[31] = 7; } /* The minimum additive increment value for the congestion control table */ #define CC_MIN_INCR 2U /** * t3_load_mtus - write the MTU and congestion control HW tables * @adap: the adapter * @mtus: the unrestricted values for the MTU table * @alpha: the values for the congestion control alpha parameter * @beta: the values for the congestion control beta parameter * @mtu_cap: the maximum permitted effective MTU * * Write the MTU table with the supplied MTUs capping each at &mtu_cap. * Update the high-speed congestion control table with the supplied alpha, * beta, and MTUs. */ void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], unsigned short alpha[NCCTRL_WIN], unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap) { static const unsigned int avg_pkts[NCCTRL_WIN] = { 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 28672, 40960, 57344, 81920, 114688, 163840, 229376 }; unsigned int i, w; for (i = 0; i < NMTUS; ++i) { unsigned int mtu = min(mtus[i], mtu_cap); unsigned int log2 = fls(mtu); if (!(mtu & ((1 << log2) >> 2))) /* round */ log2--; t3_write_reg(adap, A_TP_MTU_TABLE, (i << 24) | (log2 << 16) | mtu); for (w = 0; w < NCCTRL_WIN; ++w) { unsigned int inc; inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], CC_MIN_INCR); t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | (w << 16) | (beta[w] << 13) | inc); } } } /** * t3_read_hw_mtus - returns the values in the HW MTU table * @adap: the adapter * @mtus: where to store the HW MTU values * * Reads the HW MTU table. */ void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]) { int i; for (i = 0; i < NMTUS; ++i) { unsigned int val; t3_write_reg(adap, A_TP_MTU_TABLE, 0xff000000 | i); val = t3_read_reg(adap, A_TP_MTU_TABLE); mtus[i] = val & 0x3fff; } } /** * t3_get_cong_cntl_tab - reads the congestion control table * @adap: the adapter * @incr: where to store the alpha values * * Reads the additive increments programmed into the HW congestion * control table. */ void t3_get_cong_cntl_tab(adapter_t *adap, unsigned short incr[NMTUS][NCCTRL_WIN]) { unsigned int mtu, w; for (mtu = 0; mtu < NMTUS; ++mtu) for (w = 0; w < NCCTRL_WIN; ++w) { t3_write_reg(adap, A_TP_CCTRL_TABLE, 0xffff0000 | (mtu << 5) | w); incr[mtu][w] = (unsigned short)t3_read_reg(adap, A_TP_CCTRL_TABLE) & 0x1fff; } } /** * t3_tp_get_mib_stats - read TP's MIB counters * @adap: the adapter * @tps: holds the returned counter values * * Returns the values of TP's MIB counters. */ void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps) { t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *)tps, sizeof(*tps) / sizeof(u32), 0); } /** * t3_read_pace_tbl - read the pace table * @adap: the adapter * @pace_vals: holds the returned values * * Returns the values of TP's pace table in nanoseconds. */ void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]) { unsigned int i, tick_ns = dack_ticks_to_usec(adap, 1000); for (i = 0; i < NTX_SCHED; i++) { t3_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); pace_vals[i] = t3_read_reg(adap, A_TP_PACE_TABLE) * tick_ns; } } /** * t3_set_pace_tbl - set the pace table * @adap: the adapter * @pace_vals: the pace values in nanoseconds * @start: index of the first entry in the HW pace table to set * @n: how many entries to set * * Sets (a subset of the) HW pace table. */ void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, unsigned int start, unsigned int n) { unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); for ( ; n; n--, start++, pace_vals++) t3_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | ((*pace_vals + tick_ns / 2) / tick_ns)); } #define ulp_region(adap, name, start, len) \ t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \ t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \ (start) + (len) - 1); \ start += len #define ulptx_region(adap, name, start, len) \ t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \ t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \ (start) + (len) - 1) static void ulp_config(adapter_t *adap, const struct tp_params *p) { unsigned int m = p->chan_rx_size; ulp_region(adap, ISCSI, m, p->chan_rx_size / 8); ulp_region(adap, TDDP, m, p->chan_rx_size / 8); ulptx_region(adap, TPT, m, p->chan_rx_size / 4); ulp_region(adap, STAG, m, p->chan_rx_size / 4); ulp_region(adap, RQ, m, p->chan_rx_size / 4); ulptx_region(adap, PBL, m, p->chan_rx_size / 4); ulp_region(adap, PBL, m, p->chan_rx_size / 4); t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff); } /** * t3_set_proto_sram - set the contents of the protocol sram * @adapter: the adapter * @data: the protocol image * * Write the contents of the protocol SRAM. */ int t3_set_proto_sram(adapter_t *adap, const u8 *data) { int i; const u32 *buf = (const u32 *)data; for (i = 0; i < PROTO_SRAM_LINES; i++) { t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++)); t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++)); t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++)); t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++)); t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++)); t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31); if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1)) return -EIO; } return 0; } #endif /** * t3_config_trace_filter - configure one of the tracing filters * @adapter: the adapter * @tp: the desired trace filter parameters * @filter_index: which filter to configure * @invert: if set non-matching packets are traced instead of matching ones * @enable: whether to enable or disable the filter * * Configures one of the tracing filters available in HW. */ void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, int filter_index, int invert, int enable) { u32 addr, key[4], mask[4]; key[0] = tp->sport | (tp->sip << 16); key[1] = (tp->sip >> 16) | (tp->dport << 16); key[2] = tp->dip; key[3] = tp->proto | (tp->vlan << 8) | (tp->intf << 20); mask[0] = tp->sport_mask | (tp->sip_mask << 16); mask[1] = (tp->sip_mask >> 16) | (tp->dport_mask << 16); mask[2] = tp->dip_mask; mask[3] = tp->proto_mask | (tp->vlan_mask << 8) | (tp->intf_mask << 20); if (invert) key[3] |= (1 << 29); if (enable) key[3] |= (1 << 28); addr = filter_index ? A_TP_RX_TRC_KEY0 : A_TP_TX_TRC_KEY0; tp_wr_indirect(adapter, addr++, key[0]); tp_wr_indirect(adapter, addr++, mask[0]); tp_wr_indirect(adapter, addr++, key[1]); tp_wr_indirect(adapter, addr++, mask[1]); tp_wr_indirect(adapter, addr++, key[2]); tp_wr_indirect(adapter, addr++, mask[2]); tp_wr_indirect(adapter, addr++, key[3]); tp_wr_indirect(adapter, addr, mask[3]); (void) t3_read_reg(adapter, A_TP_PIO_DATA); } /** * t3_query_trace_filter - query a tracing filter * @adapter: the adapter * @tp: the current trace filter parameters * @filter_index: which filter to query * @inverted: non-zero if the filter is inverted * @enabled: non-zero if the filter is enabled * * Returns the current settings of the specified HW tracing filter. */ void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, int filter_index, int *inverted, int *enabled) { u32 addr, key[4], mask[4]; addr = filter_index ? A_TP_RX_TRC_KEY0 : A_TP_TX_TRC_KEY0; key[0] = tp_rd_indirect(adapter, addr++); mask[0] = tp_rd_indirect(adapter, addr++); key[1] = tp_rd_indirect(adapter, addr++); mask[1] = tp_rd_indirect(adapter, addr++); key[2] = tp_rd_indirect(adapter, addr++); mask[2] = tp_rd_indirect(adapter, addr++); key[3] = tp_rd_indirect(adapter, addr++); mask[3] = tp_rd_indirect(adapter, addr); tp->sport = key[0] & 0xffff; tp->sip = (key[0] >> 16) | ((key[1] & 0xffff) << 16); tp->dport = key[1] >> 16; tp->dip = key[2]; tp->proto = key[3] & 0xff; tp->vlan = key[3] >> 8; tp->intf = key[3] >> 20; tp->sport_mask = mask[0] & 0xffff; tp->sip_mask = (mask[0] >> 16) | ((mask[1] & 0xffff) << 16); tp->dport_mask = mask[1] >> 16; tp->dip_mask = mask[2]; tp->proto_mask = mask[3] & 0xff; tp->vlan_mask = mask[3] >> 8; tp->intf_mask = mask[3] >> 20; *inverted = key[3] & (1 << 29); *enabled = key[3] & (1 << 28); } /** * t3_config_sched - configure a HW traffic scheduler * @adap: the adapter * @kbps: target rate in Kbps * @sched: the scheduler index * * Configure a Tx HW scheduler for the target rate. */ int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched) { unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; unsigned int clk = adap->params.vpd.cclk * 1000; unsigned int selected_cpt = 0, selected_bpt = 0; if (kbps > 0) { kbps *= 125; /* -> bytes */ for (cpt = 1; cpt <= 255; cpt++) { tps = clk / cpt; bpt = (kbps + tps / 2) / tps; if (bpt > 0 && bpt <= 255) { v = bpt * tps; delta = v >= kbps ? v - kbps : kbps - v; if (delta < mindelta) { mindelta = delta; selected_cpt = cpt; selected_bpt = bpt; } } else if (selected_cpt) break; } if (!selected_cpt) return -EINVAL; } t3_write_reg(adap, A_TP_TM_PIO_ADDR, A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); v = t3_read_reg(adap, A_TP_TM_PIO_DATA); if (sched & 1) v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); else v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); t3_write_reg(adap, A_TP_TM_PIO_DATA, v); return 0; } /** * t3_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler * @adap: the adapter * @sched: the scheduler index * @ipg: the interpacket delay in tenths of nanoseconds * * Set the interpacket delay for a HW packet rate scheduler. */ int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg) { unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; /* convert ipg to nearest number of core clocks */ ipg *= core_ticks_per_usec(adap); ipg = (ipg + 5000) / 10000; if (ipg > 0xffff) return -EINVAL; t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); v = t3_read_reg(adap, A_TP_TM_PIO_DATA); if (sched & 1) v = (v & 0xffff) | (ipg << 16); else v = (v & 0xffff0000) | ipg; t3_write_reg(adap, A_TP_TM_PIO_DATA, v); t3_read_reg(adap, A_TP_TM_PIO_DATA); return 0; } /** * t3_get_tx_sched - get the configuration of a Tx HW traffic scheduler * @adap: the adapter * @sched: the scheduler index * @kbps: the byte rate in Kbps * @ipg: the interpacket delay in tenths of nanoseconds * * Return the current configuration of a HW Tx scheduler. */ void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, unsigned int *ipg) { unsigned int v, addr, bpt, cpt; if (kbps) { addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); v = t3_read_reg(adap, A_TP_TM_PIO_DATA); if (sched & 1) v >>= 16; bpt = (v >> 8) & 0xff; cpt = v & 0xff; if (!cpt) *kbps = 0; /* scheduler disabled */ else { v = (adap->params.vpd.cclk * 1000) / cpt; *kbps = (v * bpt) / 125; } } if (ipg) { addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr); v = t3_read_reg(adap, A_TP_TM_PIO_DATA); if (sched & 1) v >>= 16; v &= 0xffff; *ipg = (10000 * v) / core_ticks_per_usec(adap); } } /** * tp_init - configure TP * @adap: the adapter * @p: TP configuration parameters * * Initializes the TP HW module. */ static int tp_init(adapter_t *adap, const struct tp_params *p) { int busy = 0; tp_config(adap, p); t3_set_vlan_accel(adap, 3, 0); if (is_offload(adap)) { tp_set_timers(adap, adap->params.vpd.cclk * 1000); t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE); busy = t3_wait_op_done(adap, A_TP_RESET, F_FLSTINITENABLE, 0, 1000, 5); if (busy) CH_ERR(adap, "TP initialization timed out\n"); } if (!busy) t3_write_reg(adap, A_TP_RESET, F_TPRESET); return busy; } /** * t3_mps_set_active_ports - configure port failover * @adap: the adapter * @port_mask: bitmap of active ports * * Sets the active ports according to the supplied bitmap. */ int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask) { if (port_mask & ~((1 << adap->params.nports) - 1)) return -EINVAL; t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE, port_mask << S_PORT0ACTIVE); return 0; } /** * chan_init_hw - channel-dependent HW initialization * @adap: the adapter * @chan_map: bitmap of Tx channels being used * * Perform the bits of HW initialization that are dependent on the Tx * channels being used. */ static void chan_init_hw(adapter_t *adap, unsigned int chan_map) { int i; if (chan_map != 3) { /* one channel */ t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0); t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0); t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT | (chan_map == 1 ? F_TPTXPORT0EN | F_PORT0ACTIVE : F_TPTXPORT1EN | F_PORT1ACTIVE)); t3_write_reg(adap, A_PM1_TX_CFG, chan_map == 1 ? 0xffffffff : 0); if (chan_map == 2) t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP, V_TX_MOD_QUEUE_REQ_MAP(0xff)); t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xd9c8); t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfbea); } else { /* two channels */ t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN); t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB); t3_write_reg(adap, A_ULPTX_DMA_WEIGHT, V_D1_WEIGHT(16) | V_D0_WEIGHT(16)); t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN | F_TPRXPORTEN | F_PORT0ACTIVE | F_PORT1ACTIVE | F_ENFORCEPKT); t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000); t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE); t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP, V_TX_MOD_QUEUE_REQ_MAP(0xaa)); for (i = 0; i < 16; i++) t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (i << 16) | 0x1010); t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xba98); t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfedc); } } static int calibrate_xgm(adapter_t *adapter) { if (uses_xaui(adapter)) { unsigned int v, i; for (i = 0; i < 5; ++i) { t3_write_reg(adapter, A_XGM_XAUI_IMP, 0); (void) t3_read_reg(adapter, A_XGM_XAUI_IMP); msleep(1); v = t3_read_reg(adapter, A_XGM_XAUI_IMP); if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) { t3_write_reg(adapter, A_XGM_XAUI_IMP, V_XAUIIMP(G_CALIMP(v) >> 2)); return 0; } } CH_ERR(adapter, "MAC calibration failed\n"); return -1; } else { t3_write_reg(adapter, A_XGM_RGMII_IMP, V_RGMIIIMPPD(2) | V_RGMIIIMPPU(3)); t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE, F_XGM_IMPSETUPDATE); } return 0; } static void calibrate_xgm_t3b(adapter_t *adapter) { if (!uses_xaui(adapter)) { t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET | F_CALUPDATE | V_RGMIIIMPPD(2) | V_RGMIIIMPPU(3)); t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0); t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_XGM_IMPSETUPDATE); t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE, 0); t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0); t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE); } } struct mc7_timing_params { unsigned char ActToPreDly; unsigned char ActToRdWrDly; unsigned char PreCyc; unsigned char RefCyc[5]; unsigned char BkCyc; unsigned char WrToRdDly; unsigned char RdToWrDly; }; /* * Write a value to a register and check that the write completed. These * writes normally complete in a cycle or two, so one read should suffice. * The very first read exists to flush the posted write to the device. */ static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val) { t3_write_reg(adapter, addr, val); (void) t3_read_reg(adapter, addr); /* flush */ if (!(t3_read_reg(adapter, addr) & F_BUSY)) return 0; CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr); return -EIO; } static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type) { static const unsigned int mc7_mode[] = { 0x632, 0x642, 0x652, 0x432, 0x442 }; static const struct mc7_timing_params mc7_timings[] = { { 12, 3, 4, { 20, 28, 34, 52, 0 }, 15, 6, 4 }, { 12, 4, 5, { 20, 28, 34, 52, 0 }, 16, 7, 4 }, { 12, 5, 6, { 20, 28, 34, 52, 0 }, 17, 8, 4 }, { 9, 3, 4, { 15, 21, 26, 39, 0 }, 12, 6, 4 }, { 9, 4, 5, { 15, 21, 26, 39, 0 }, 13, 7, 4 } }; u32 val; unsigned int width, density, slow, attempts; adapter_t *adapter = mc7->adapter; const struct mc7_timing_params *p = &mc7_timings[mem_type]; if (!mc7->size) return 0; val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); slow = val & F_SLOW; width = G_WIDTH(val); density = G_DEN(val); t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ msleep(1); if (!slow) { t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN); (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL); msleep(1); if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) & (F_BUSY | F_SGL_CAL_EN | F_CAL_FAULT)) { CH_ERR(adapter, "%s MC7 calibration timed out\n", mc7->name); goto out_fail; } } t3_write_reg(adapter, mc7->offset + A_MC7_PARM, V_ACTTOPREDLY(p->ActToPreDly) | V_ACTTORDWRDLY(p->ActToRdWrDly) | V_PRECYC(p->PreCyc) | V_REFCYC(p->RefCyc[density]) | V_BKCYC(p->BkCyc) | V_WRTORDDLY(p->WrToRdDly) | V_RDTOWRDLY(p->RdToWrDly)); t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_CLKEN | F_TERM150); (void) t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ if (!slow) t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB, F_DLLENB); udelay(1); val = slow ? 3 : 6; if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) || wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) || wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) goto out_fail; if (!slow) { t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100); t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0); udelay(5); } if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || wrreg_wait(adapter, mc7->offset + A_MC7_MODE, mc7_mode[mem_type]) || wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) || wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) goto out_fail; /* clock value is in KHz */ mc7_clock = mc7_clock * 7812 + mc7_clock / 2; /* ns */ mc7_clock /= 1000000; /* KHz->MHz, ns->us */ t3_write_reg(adapter, mc7->offset + A_MC7_REF, F_PERREFEN | V_PREREFDIV(mc7_clock)); (void) t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */ t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN); t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0); t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0); t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END, (mc7->size << width) - 1); t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1)); (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */ attempts = 50; do { msleep(250); val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); } while ((val & F_BUSY) && --attempts); if (val & F_BUSY) { CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name); goto out_fail; } /* Enable normal memory accesses. */ t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY); return 0; out_fail: return -1; } static void config_pcie(adapter_t *adap) { static const u16 ack_lat[4][6] = { { 237, 416, 559, 1071, 2095, 4143 }, { 128, 217, 289, 545, 1057, 2081 }, { 73, 118, 154, 282, 538, 1050 }, { 67, 107, 86, 150, 278, 534 } }; static const u16 rpl_tmr[4][6] = { { 711, 1248, 1677, 3213, 6285, 12429 }, { 384, 651, 867, 1635, 3171, 6243 }, { 219, 354, 462, 846, 1614, 3150 }, { 201, 321, 258, 450, 834, 1602 } }; u16 val, devid; unsigned int log2_width, pldsize; unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; t3_os_pci_read_config_2(adap, adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, &val); pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; /* * Gen2 adapter pcie bridge compatibility requires minimum * Max_Read_Request_size */ t3_os_pci_read_config_2(adap, 0x2, &devid); if (devid == 0x37) { t3_os_pci_write_config_2(adap, adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL, val & ~PCI_EXP_DEVCTL_READRQ & ~PCI_EXP_DEVCTL_PAYLOAD); pldsize = 0; } t3_os_pci_read_config_2(adap, adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL, &val); fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0)); fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx : G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE)); log2_width = fls(adap->params.pci.width) - 1; acklat = ack_lat[log2_width][pldsize]; if (val & 1) /* check LOsEnable */ acklat += fst_trn_tx * 4; rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4; if (adap->params.rev == 0) t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_T3A_ACKLAT(M_T3A_ACKLAT), V_T3A_ACKLAT(acklat)); else t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT), V_ACKLAT(acklat)); t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT), V_REPLAYLMT(rpllmt)); t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff); t3_set_reg_field(adap, A_PCIE_CFG, 0, F_ENABLELINKDWNDRST | F_ENABLELINKDOWNRST | F_PCIE_DMASTOPEN | F_PCIE_CLIDECEN); } /** * t3_init_hw - initialize and configure T3 HW modules * @adapter: the adapter * @fw_params: initial parameters to pass to firmware (optional) * * Initialize and configure T3 HW modules. This performs the * initialization steps that need to be done once after a card is reset. * MAC and PHY initialization is handled separarely whenever a port is * enabled. * * @fw_params are passed to FW and their value is platform dependent. * Only the top 8 bits are available for use, the rest must be 0. */ int t3_init_hw(adapter_t *adapter, u32 fw_params) { int err = -EIO, attempts, i; const struct vpd_params *vpd = &adapter->params.vpd; if (adapter->params.rev > 0) calibrate_xgm_t3b(adapter); else if (calibrate_xgm(adapter)) goto out_err; if (adapter->params.nports > 2) t3_mac_init(&adap2pinfo(adapter, 0)->mac); if (vpd->mclk) { partition_mem(adapter, &adapter->params.tp); if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) || mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) || mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) || t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers, adapter->params.mc5.nfilters, adapter->params.mc5.nroutes)) goto out_err; for (i = 0; i < 32; i++) if (clear_sge_ctxt(adapter, i, F_CQ)) goto out_err; } if (tp_init(adapter, &adapter->params.tp)) goto out_err; #ifdef CONFIG_CHELSIO_T3_CORE t3_tp_set_coalescing_size(adapter, min(adapter->params.sge.max_pkt_size, MAX_RX_COALESCING_LEN), 1); t3_tp_set_max_rxsize(adapter, min(adapter->params.sge.max_pkt_size, 16384U)); ulp_config(adapter, &adapter->params.tp); #endif if (is_pcie(adapter)) config_pcie(adapter); else t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_DMASTOPEN | F_CLIDECEN); if (adapter->params.rev == T3_REV_C) t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0, F_CFG_CQE_SOP_MASK); t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff); t3_write_reg(adapter, A_PM1_RX_MODE, 0); t3_write_reg(adapter, A_PM1_TX_MODE, 0); chan_init_hw(adapter, adapter->params.chan_map); t3_sge_init(adapter, &adapter->params.sge); + t3_set_reg_field(adapter, A_PL_RST, 0, F_FATALPERREN); t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter)); t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); t3_write_reg(adapter, A_CIM_BOOT_CFG, V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2)); (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */ attempts = 100; do { /* wait for uP to initialize */ msleep(20); } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); if (!attempts) { CH_ERR(adapter, "uP initialization timed out\n"); goto out_err; } err = 0; out_err: return err; } /** * get_pci_mode - determine a card's PCI mode * @adapter: the adapter * @p: where to store the PCI settings * * Determines a card's PCI mode and associated parameters, such as speed * and width. */ static void __devinit get_pci_mode(adapter_t *adapter, struct pci_params *p) { static unsigned short speed_map[] = { 33, 66, 100, 133 }; u32 pci_mode, pcie_cap; pcie_cap = t3_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); if (pcie_cap) { u16 val; p->variant = PCI_VARIANT_PCIE; p->pcie_cap_addr = pcie_cap; t3_os_pci_read_config_2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); p->width = (val >> 4) & 0x3f; return; } pci_mode = t3_read_reg(adapter, A_PCIX_MODE); p->speed = speed_map[G_PCLKRANGE(pci_mode)]; p->width = (pci_mode & F_64BIT) ? 64 : 32; pci_mode = G_PCIXINITPAT(pci_mode); if (pci_mode == 0) p->variant = PCI_VARIANT_PCI; else if (pci_mode < 4) p->variant = PCI_VARIANT_PCIX_MODE1_PARITY; else if (pci_mode < 8) p->variant = PCI_VARIANT_PCIX_MODE1_ECC; else p->variant = PCI_VARIANT_PCIX_266_MODE2; } /** * init_link_config - initialize a link's SW state * @lc: structure holding the link state * @caps: link capabilities * * Initializes the SW state maintained for each link, including the link's * capabilities and default speed/duplex/flow-control/autonegotiation * settings. */ static void __devinit init_link_config(struct link_config *lc, unsigned int caps) { lc->supported = caps; lc->requested_speed = lc->speed = SPEED_INVALID; lc->requested_duplex = lc->duplex = DUPLEX_INVALID; lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; if (lc->supported & SUPPORTED_Autoneg) { lc->advertising = lc->supported; lc->autoneg = AUTONEG_ENABLE; lc->requested_fc |= PAUSE_AUTONEG; } else { lc->advertising = 0; lc->autoneg = AUTONEG_DISABLE; } } /** * mc7_calc_size - calculate MC7 memory size * @cfg: the MC7 configuration * * Calculates the size of an MC7 memory in bytes from the value of its * configuration register. */ static unsigned int __devinit mc7_calc_size(u32 cfg) { unsigned int width = G_WIDTH(cfg); unsigned int banks = !!(cfg & F_BKS) + 1; unsigned int org = !!(cfg & F_ORG) + 1; unsigned int density = G_DEN(cfg); unsigned int MBs = ((256 << density) * banks) / (org << width); return MBs << 20; } static void __devinit mc7_prep(adapter_t *adapter, struct mc7 *mc7, unsigned int base_addr, const char *name) { u32 cfg; mc7->adapter = adapter; mc7->name = name; mc7->offset = base_addr - MC7_PMRX_BASE_ADDR; cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg); mc7->width = G_WIDTH(cfg); } void mac_prep(struct cmac *mac, adapter_t *adapter, int index) { u16 devid; mac->adapter = adapter; mac->multiport = adapter->params.nports > 2; if (mac->multiport) { mac->ext_port = (unsigned char)index; mac->nucast = 8; } else mac->nucast = 1; /* Gen2 adapter uses VPD xauicfg[] to notify driver which MAC is connected to each port, its suppose to be using xgmac0 for both ports */ t3_os_pci_read_config_2(adapter, 0x2, &devid); if (mac->multiport || (!adapter->params.vpd.xauicfg[1] && (devid==0x37))) index = 0; mac->offset = (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR) * index; if (adapter->params.rev == 0 && uses_xaui(adapter)) { t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset, is_10G(adapter) ? 0x2901c04 : 0x2301c04); t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset, F_ENRGMII, 0); } } /** * early_hw_init - HW initialization done at card detection time * @adapter: the adapter * @ai: contains information about the adapter type and properties * * Perfoms the part of HW initialization that is done early on when the * driver first detecs the card. Most of the HW state is initialized * lazily later on when a port or an offload function are first used. */ void early_hw_init(adapter_t *adapter, const struct adapter_info *ai) { u32 val = V_PORTSPEED(is_10G(adapter) || adapter->params.nports > 2 ? 3 : 2); u32 gpio_out = ai->gpio_out; mi1_init(adapter, ai); t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */ V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1)); t3_write_reg(adapter, A_T3DBG_GPIO_EN, gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL); t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff)); if (adapter->params.rev == 0 || !uses_xaui(adapter)) val |= F_ENRGMII; /* Enable MAC clocks so we can access the registers */ t3_write_reg(adapter, A_XGM_PORT_CFG, val); (void) t3_read_reg(adapter, A_XGM_PORT_CFG); val |= F_CLKDIVRESET_; t3_write_reg(adapter, A_XGM_PORT_CFG, val); (void) t3_read_reg(adapter, A_XGM_PORT_CFG); t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val); (void) t3_read_reg(adapter, A_XGM_PORT_CFG); } /** * t3_reset_adapter - reset the adapter * @adapter: the adapter * * Reset the adapter. */ int t3_reset_adapter(adapter_t *adapter) { int i, save_and_restore_pcie = adapter->params.rev < T3_REV_B2 && is_pcie(adapter); uint16_t devid = 0; if (save_and_restore_pcie) t3_os_pci_save_state(adapter); t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE); /* * Delay. Give Some time to device to reset fully. * XXX The delay time should be modified. */ for (i = 0; i < 10; i++) { msleep(50); t3_os_pci_read_config_2(adapter, 0x00, &devid); if (devid == 0x1425) break; } if (devid != 0x1425) return -1; if (save_and_restore_pcie) t3_os_pci_restore_state(adapter); return 0; } static int init_parity(adapter_t *adap) { int i, err, addr; if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) return -EBUSY; for (err = i = 0; !err && i < 16; i++) err = clear_sge_ctxt(adap, i, F_EGRESS); for (i = 0xfff0; !err && i <= 0xffff; i++) err = clear_sge_ctxt(adap, i, F_EGRESS); for (i = 0; !err && i < SGE_QSETS; i++) err = clear_sge_ctxt(adap, i, F_RESPONSEQ); if (err) return err; t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0); for (i = 0; i < 4; i++) for (addr = 0; addr <= M_IBQDBGADDR; addr++) { t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN | F_IBQDBGWR | V_IBQDBGQID(i) | V_IBQDBGADDR(addr)); err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 2, 1); if (err) return err; } return 0; } /** * t3_prep_adapter - prepare SW and HW for operation * @adapter: the adapter * @ai: contains information about the adapter type and properties * * Initialize adapter SW state for the various HW modules, set initial * values for some adapter tunables, take PHYs out of reset, and * initialize the MDIO interface. */ int __devinit t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset) { int ret; unsigned int i, j = 0; get_pci_mode(adapter, &adapter->params.pci); adapter->params.info = ai; adapter->params.nports = ai->nports0 + ai->nports1; adapter->params.chan_map = (!!ai->nports0) | (!!ai->nports1 << 1); adapter->params.rev = t3_read_reg(adapter, A_PL_REV); /* * We used to only run the "adapter check task" once a second if * we had PHYs which didn't support interrupts (we would check * their link status once a second). Now we check other conditions * in that routine which would [potentially] impose a very high * interrupt load on the system. As such, we now always scan the * adapter state once a second ... */ adapter->params.linkpoll_period = 10; if (adapter->params.nports > 2) adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS; else adapter->params.stats_update_period = is_10G(adapter) ? MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10); adapter->params.pci.vpd_cap_addr = t3_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); ret = get_vpd_params(adapter, &adapter->params.vpd); if (ret < 0) return ret; if (reset && t3_reset_adapter(adapter)) return -1; t3_sge_prep(adapter, &adapter->params.sge); if (adapter->params.vpd.mclk) { struct tp_params *p = &adapter->params.tp; mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX"); mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX"); mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM"); p->nchan = adapter->params.chan_map == 3 ? 2 : 1; p->pmrx_size = t3_mc7_size(&adapter->pmrx); p->pmtx_size = t3_mc7_size(&adapter->pmtx); p->cm_size = t3_mc7_size(&adapter->cm); p->chan_rx_size = p->pmrx_size / 2; /* only 1 Rx channel */ p->chan_tx_size = p->pmtx_size / p->nchan; p->rx_pg_size = 64 * 1024; p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024; p->rx_num_pgs = pm_num_pages(p->chan_rx_size, p->rx_pg_size); p->tx_num_pgs = pm_num_pages(p->chan_tx_size, p->tx_pg_size); p->ntimer_qs = p->cm_size >= (128 << 20) || adapter->params.rev > 0 ? 12 : 6; p->tre = fls(adapter->params.vpd.cclk / (1000 / TP_TMR_RES)) - 1; p->dack_re = fls(adapter->params.vpd.cclk / 10) - 1; /* 100us */ } adapter->params.offload = t3_mc7_size(&adapter->pmrx) && t3_mc7_size(&adapter->pmtx) && t3_mc7_size(&adapter->cm); if (is_offload(adapter)) { adapter->params.mc5.nservers = DEFAULT_NSERVERS; /* PR 6487. TOE and filtering are mutually exclusive */ adapter->params.mc5.nfilters = 0; adapter->params.mc5.nroutes = 0; t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT); #ifdef CONFIG_CHELSIO_T3_CORE init_mtus(adapter->params.mtus); init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); #endif } early_hw_init(adapter, ai); ret = init_parity(adapter); if (ret) return ret; if (adapter->params.nports > 2 && (ret = t3_vsc7323_init(adapter, adapter->params.nports))) return ret; for_each_port(adapter, i) { u8 hw_addr[6]; const struct port_type_info *pti; struct port_info *p = adap2pinfo(adapter, i); for (;;) { unsigned port_type = adapter->params.vpd.port_type[j]; if (port_type) { if (port_type < ARRAY_SIZE(port_types)) { pti = &port_types[port_type]; break; } else return -EINVAL; } j++; if (j >= ARRAY_SIZE(adapter->params.vpd.port_type)) return -EINVAL; } ret = pti->phy_prep(p, ai->phy_base_addr + j, ai->mdio_ops); if (ret) return ret; mac_prep(&p->mac, adapter, j); ++j; /* * The VPD EEPROM stores the base Ethernet address for the * card. A port's address is derived from the base by adding * the port's index to the base's low octet. */ memcpy(hw_addr, adapter->params.vpd.eth_base, 5); hw_addr[5] = adapter->params.vpd.eth_base[5] + i; t3_os_set_hw_addr(adapter, i, hw_addr); init_link_config(&p->link_config, p->phy.caps); p->phy.ops->power_down(&p->phy, 1); /* * If the PHY doesn't support interrupts for link status * changes, schedule a scan of the adapter links at least * once a second. */ if (!(p->phy.caps & SUPPORTED_IRQ) && adapter->params.linkpoll_period > 10) adapter->params.linkpoll_period = 10; } return 0; } /** * t3_reinit_adapter - prepare HW for operation again * @adapter: the adapter * * Put HW in the same state as @t3_prep_adapter without any changes to * SW state. This is a cut down version of @t3_prep_adapter intended * to be used after events that wipe out HW state but preserve SW state, * e.g., EEH. The device must be reset before calling this. */ int t3_reinit_adapter(adapter_t *adap) { unsigned int i; int ret, j = 0; early_hw_init(adap, adap->params.info); ret = init_parity(adap); if (ret) return ret; if (adap->params.nports > 2 && (ret = t3_vsc7323_init(adap, adap->params.nports))) return ret; for_each_port(adap, i) { const struct port_type_info *pti; struct port_info *p = adap2pinfo(adap, i); for (;;) { unsigned port_type = adap->params.vpd.port_type[j]; if (port_type) { if (port_type < ARRAY_SIZE(port_types)) { pti = &port_types[port_type]; break; } else return -EINVAL; } j++; if (j >= ARRAY_SIZE(adap->params.vpd.port_type)) return -EINVAL; } ret = pti->phy_prep(p, p->phy.addr, NULL); if (ret) return ret; p->phy.ops->power_down(&p->phy, 1); } return 0; } void t3_led_ready(adapter_t *adapter) { t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, F_GPIO0_OUT_VAL); } void t3_port_failover(adapter_t *adapter, int port) { u32 val; val = port ? F_PORT1ACTIVE : F_PORT0ACTIVE; t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, val); } void t3_failover_done(adapter_t *adapter, int port) { t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, F_PORT0ACTIVE | F_PORT1ACTIVE); } void t3_failover_clear(adapter_t *adapter) { t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, F_PORT0ACTIVE | F_PORT1ACTIVE); } static int t3_cim_hac_read(adapter_t *adapter, u32 addr, u32 *val) { u32 v; t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr); if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 0, 10, 10, &v)) return -EIO; *val = t3_read_reg(adapter, A_CIM_HOST_ACC_DATA); return 0; } static int t3_cim_hac_write(adapter_t *adapter, u32 addr, u32 val) { u32 v; t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, val); addr |= F_HOSTWRITE; t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr); if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 0, 10, 5, &v)) return -EIO; return 0; } int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, u32 *size, void *data) { u32 v, *buf = data; int i, cnt, ret; if (*size < LA_ENTRIES * 4) return -EINVAL; ret = t3_cim_hac_read(adapter, LA_CTRL, &v); if (ret) goto out; *stopped = !(v & 1); /* Freeze LA */ if (!*stopped) { ret = t3_cim_hac_write(adapter, LA_CTRL, 0); if (ret) goto out; } for (i = 0; i < LA_ENTRIES; i++) { v = (i << 2) | (1 << 1); ret = t3_cim_hac_write(adapter, LA_CTRL, v); if (ret) goto out; ret = t3_cim_hac_read(adapter, LA_CTRL, &v); if (ret) goto out; cnt = 20; while ((v & (1 << 1)) && cnt) { udelay(5); --cnt; ret = t3_cim_hac_read(adapter, LA_CTRL, &v); if (ret) goto out; } if (v & (1 << 1)) return -EIO; ret = t3_cim_hac_read(adapter, LA_DATA, &v); if (ret) goto out; *buf++ = v; } ret = t3_cim_hac_read(adapter, LA_CTRL, &v); if (ret) goto out; *index = (v >> 16) + 4; *size = LA_ENTRIES * 4; out: /* Unfreeze LA */ t3_cim_hac_write(adapter, LA_CTRL, 1); return ret; } int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data) { u32 v, *buf = data; int i, j, ret; if (*size < IOQ_ENTRIES * sizeof(struct t3_ioq_entry)) return -EINVAL; for (i = 0; i < 4; i++) { ret = t3_cim_hac_read(adapter, (4 * i), &v); if (ret) goto out; *buf++ = v; } for (i = 0; i < IOQ_ENTRIES; i++) { u32 base_addr = 0x10 * (i + 1); for (j = 0; j < 4; j++) { ret = t3_cim_hac_read(adapter, base_addr + 4 * j, &v); if (ret) goto out; *buf++ = v; } } *size = IOQ_ENTRIES * sizeof(struct t3_ioq_entry); out: return ret; } Index: stable/7/sys/dev/cxgb/cxgb_adapter.h =================================================================== --- stable/7/sys/dev/cxgb/cxgb_adapter.h (revision 220340) +++ stable/7/sys/dev/cxgb/cxgb_adapter.h (revision 220341) @@ -1,597 +1,597 @@ /************************************************************************** Copyright (c) 2007-2009, Chelsio Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Neither the name of the Chelsio Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. $FreeBSD$ ***************************************************************************/ #ifndef _CXGB_ADAPTER_H_ #define _CXGB_ADAPTER_H_ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef CONFIG_DEFINED #include #include #include #include #else #include #include #include #include #endif struct adapter; struct sge_qset; extern int cxgb_debug; #ifdef DEBUG_LOCKING #define MTX_INIT(lock, lockname, class, flags) \ do { \ printf("initializing %s at %s:%d\n", lockname, __FILE__, __LINE__); \ mtx_init((lock), lockname, class, flags); \ } while (0) #define MTX_DESTROY(lock) \ do { \ printf("destroying %s at %s:%d\n", (lock)->lock_object.lo_name, __FILE__, __LINE__); \ mtx_destroy((lock)); \ } while (0) #else #define MTX_INIT mtx_init #define MTX_DESTROY mtx_destroy #endif enum { LF_NO = 0, LF_MAYBE, LF_YES }; struct port_info { struct adapter *adapter; struct ifnet *ifp; int if_flags; int flags; const struct port_type_info *port_type; struct cphy phy; struct cmac mac; struct link_config link_config; struct ifmedia media; struct mtx lock; uint32_t port_id; uint32_t tx_chan; uint32_t txpkt_intf; uint32_t first_qset; uint32_t nqsets; int link_fault; uint8_t hw_addr[ETHER_ADDR_LEN]; struct callout link_check_ch; struct task link_check_task; struct task timer_reclaim_task; struct cdev *port_cdev; #define PORT_LOCK_NAME_LEN 32 #define PORT_NAME_LEN 32 char lockbuf[PORT_LOCK_NAME_LEN]; char namebuf[PORT_NAME_LEN]; }; enum { /* adapter flags */ FULL_INIT_DONE = (1 << 0), USING_MSI = (1 << 1), USING_MSIX = (1 << 2), QUEUES_BOUND = (1 << 3), FW_UPTODATE = (1 << 4), TPS_UPTODATE = (1 << 5), CXGB_SHUTDOWN = (1 << 6), CXGB_OFLD_INIT = (1 << 7), TP_PARITY_INIT = (1 << 8), CXGB_BUSY = (1 << 9), /* port flags */ DOOMED = (1 << 0), }; #define IS_DOOMED(p) (p->flags & DOOMED) #define SET_DOOMED(p) do {p->flags |= DOOMED;} while (0) #define IS_BUSY(sc) (sc->flags & CXGB_BUSY) #define SET_BUSY(sc) do {sc->flags |= CXGB_BUSY;} while (0) #define CLR_BUSY(sc) do {sc->flags &= ~CXGB_BUSY;} while (0) #define FL_Q_SIZE 4096 #define JUMBO_Q_SIZE 1024 #define RSPQ_Q_SIZE 2048 #define TX_ETH_Q_SIZE 1024 enum { TXQ_ETH = 0, TXQ_OFLD = 1, TXQ_CTRL = 2, }; /* * work request size in bytes */ #define WR_LEN (WR_FLITS * 8) #define PIO_LEN (WR_LEN - sizeof(struct cpl_tx_pkt_lso)) struct lro_state { unsigned short enabled; struct lro_ctrl ctrl; }; #define RX_BUNDLE_SIZE 8 struct rsp_desc; struct sge_rspq { uint32_t credits; uint32_t size; uint32_t cidx; uint32_t gen; uint32_t polling; uint32_t holdoff_tmr; uint32_t next_holdoff; uint32_t imm_data; uint32_t async_notif; uint32_t cntxt_id; uint32_t offload_pkts; uint32_t offload_bundles; uint32_t pure_rsps; uint32_t unhandled_irqs; uint32_t starved; bus_addr_t phys_addr; bus_dma_tag_t desc_tag; bus_dmamap_t desc_map; struct t3_mbuf_hdr rspq_mh; struct rsp_desc *desc; struct mtx lock; #define RSPQ_NAME_LEN 32 char lockbuf[RSPQ_NAME_LEN]; uint32_t rspq_dump_start; uint32_t rspq_dump_count; }; #ifndef DISABLE_MBUF_IOVEC #define rspq_mbuf rspq_mh.mh_head #endif struct rx_desc; struct rx_sw_desc; struct sge_fl { uint32_t buf_size; uint32_t credits; uint32_t size; uint32_t cidx; uint32_t pidx; uint32_t gen; bus_addr_t phys_addr; uint32_t cntxt_id; uint32_t empty; bus_dma_tag_t desc_tag; bus_dmamap_t desc_map; bus_dma_tag_t entry_tag; uma_zone_t zone; struct rx_desc *desc; struct rx_sw_desc *sdesc; int type; }; struct tx_desc; struct tx_sw_desc; #define TXQ_TRANSMITTING 0x1 struct sge_txq { uint64_t flags; uint32_t in_use; uint32_t size; uint32_t processed; uint32_t cleaned; uint32_t stop_thres; uint32_t cidx; uint32_t pidx; uint32_t gen; uint32_t unacked; struct tx_desc *desc; struct tx_sw_desc *sdesc; uint32_t token; bus_addr_t phys_addr; struct task qresume_task; struct task qreclaim_task; struct port_info *port; uint32_t cntxt_id; uint64_t stops; uint64_t restarts; bus_dma_tag_t desc_tag; bus_dmamap_t desc_map; bus_dma_tag_t entry_tag; struct mbuf_head sendq; /* * cleanq should really be an buf_ring to avoid extra * mbuf touches */ struct mbuf_head cleanq; struct buf_ring txq_mr; struct mbuf *immpkt; uint32_t txq_drops; uint32_t txq_skipped; uint32_t txq_coalesced; uint32_t txq_enqueued; uint32_t txq_dump_start; uint32_t txq_dump_count; unsigned long txq_frees; struct mtx lock; struct sg_ent txq_sgl[TX_MAX_SEGS / 2 + 1]; #define TXQ_NAME_LEN 32 char lockbuf[TXQ_NAME_LEN]; }; enum { SGE_PSTAT_TSO, /* # of TSO requests */ SGE_PSTAT_RX_CSUM_GOOD, /* # of successful RX csum offloads */ SGE_PSTAT_TX_CSUM, /* # of TX checksum offloads */ SGE_PSTAT_VLANEX, /* # of VLAN tag extractions */ SGE_PSTAT_VLANINS, /* # of VLAN tag insertions */ }; #define SGE_PSTAT_MAX (SGE_PSTAT_VLANINS+1) #define QS_EXITING 0x1 #define QS_RUNNING 0x2 #define QS_BOUND 0x4 struct sge_qset { struct sge_rspq rspq; struct sge_fl fl[SGE_RXQ_PER_SET]; struct lro_state lro; struct sge_txq txq[SGE_TXQ_PER_SET]; uint32_t txq_stopped; /* which Tx queues are stopped */ uint64_t port_stats[SGE_PSTAT_MAX]; struct port_info *port; int idx; /* qset # */ int qs_cpuid; int qs_flags; struct cv qs_cv; struct mtx qs_mtx; #define QS_NAME_LEN 32 char namebuf[QS_NAME_LEN]; }; struct sge { struct sge_qset qs[SGE_QSETS]; struct mtx reg_lock; }; struct filter_info; struct adapter { device_t dev; int flags; TAILQ_ENTRY(adapter) adapter_entry; /* PCI register resources */ int regs_rid; struct resource *regs_res; int udbs_rid; struct resource *udbs_res; bus_space_handle_t bh; bus_space_tag_t bt; bus_size_t mmio_len; uint32_t link_width; /* DMA resources */ bus_dma_tag_t parent_dmat; bus_dma_tag_t rx_dmat; bus_dma_tag_t rx_jumbo_dmat; bus_dma_tag_t tx_dmat; /* Interrupt resources */ struct resource *irq_res; int irq_rid; void *intr_tag; uint32_t msix_regs_rid; struct resource *msix_regs_res; struct resource *msix_irq_res[SGE_QSETS]; int msix_irq_rid[SGE_QSETS]; void *msix_intr_tag[SGE_QSETS]; uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */ uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */ uint16_t rspq_map[RSS_TABLE_SIZE]; /* maps 7-bit cookie to qidx */ union { uint8_t fill[SGE_QSETS]; uint64_t coalesce; } u; #define tunq_fill u.fill #define tunq_coalesce u.coalesce struct filter_info *filters; /* Tasks */ struct task slow_intr_task; struct task tick_task; struct taskqueue *tq; struct callout cxgb_tick_ch; struct callout sge_timer_ch; /* Register lock for use by the hardware layer */ struct mtx mdio_lock; struct mtx elmer_lock; /* Bookkeeping for the hardware layer */ struct adapter_params params; unsigned int slow_intr_mask; unsigned long irq_stats[IRQ_NUM_STATS]; struct sge sge; struct mc7 pmrx; struct mc7 pmtx; struct mc7 cm; struct mc5 mc5; struct port_info port[MAX_NPORTS]; device_t portdev[MAX_NPORTS]; struct t3cdev tdev; char fw_version[64]; char port_types[MAX_NPORTS + 1]; uint32_t open_device_map; uint32_t registered_device_map; struct mtx lock; driver_intr_t *cxgb_intr; int msi_count; #define ADAPTER_LOCK_NAME_LEN 32 char lockbuf[ADAPTER_LOCK_NAME_LEN]; char reglockbuf[ADAPTER_LOCK_NAME_LEN]; char mdiolockbuf[ADAPTER_LOCK_NAME_LEN]; char elmerlockbuf[ADAPTER_LOCK_NAME_LEN]; }; struct t3_rx_mode { uint32_t idx; struct port_info *port; }; #define MDIO_LOCK(adapter) mtx_lock(&(adapter)->mdio_lock) #define MDIO_UNLOCK(adapter) mtx_unlock(&(adapter)->mdio_lock) #define ELMR_LOCK(adapter) mtx_lock(&(adapter)->elmer_lock) #define ELMR_UNLOCK(adapter) mtx_unlock(&(adapter)->elmer_lock) #define PORT_LOCK(port) mtx_lock(&(port)->lock); #define PORT_UNLOCK(port) mtx_unlock(&(port)->lock); #define PORT_LOCK_INIT(port, name) mtx_init(&(port)->lock, name, 0, MTX_DEF) #define PORT_LOCK_DEINIT(port) mtx_destroy(&(port)->lock) #define PORT_LOCK_ASSERT_NOTOWNED(port) mtx_assert(&(port)->lock, MA_NOTOWNED) #define PORT_LOCK_ASSERT_OWNED(port) mtx_assert(&(port)->lock, MA_OWNED) #define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock); #define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock); #define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF) #define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock) #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MA_NOTOWNED) #define ADAPTER_LOCK_ASSERT_OWNED(adap) mtx_assert(&(adap)->lock, MA_OWNED) static __inline uint32_t t3_read_reg(adapter_t *adapter, uint32_t reg_addr) { return (bus_space_read_4(adapter->bt, adapter->bh, reg_addr)); } static __inline void t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val) { bus_space_write_4(adapter->bt, adapter->bh, reg_addr, val); } static __inline void t3_os_pci_read_config_4(adapter_t *adapter, int reg, uint32_t *val) { *val = pci_read_config(adapter->dev, reg, 4); } static __inline void t3_os_pci_write_config_4(adapter_t *adapter, int reg, uint32_t val) { pci_write_config(adapter->dev, reg, val, 4); } static __inline void t3_os_pci_read_config_2(adapter_t *adapter, int reg, uint16_t *val) { *val = pci_read_config(adapter->dev, reg, 2); } static __inline void t3_os_pci_write_config_2(adapter_t *adapter, int reg, uint16_t val) { pci_write_config(adapter->dev, reg, val, 2); } static __inline uint8_t * t3_get_next_mcaddr(struct t3_rx_mode *rm) { uint8_t *macaddr = NULL; struct ifnet *ifp = rm->port->ifp; struct ifmultiaddr *ifma; int i = 0; IF_ADDR_LOCK(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; if (i == rm->idx) { macaddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); break; } i++; } IF_ADDR_UNLOCK(ifp); rm->idx++; return (macaddr); } static __inline void t3_init_rx_mode(struct t3_rx_mode *rm, struct port_info *port) { rm->idx = 0; rm->port = port; } static __inline struct port_info * adap2pinfo(struct adapter *adap, int idx) { return &adap->port[idx]; } int t3_os_find_pci_capability(adapter_t *adapter, int cap); int t3_os_pci_save_state(struct adapter *adapter); int t3_os_pci_restore_state(struct adapter *adapter); void t3_os_link_intr(struct port_info *); void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, int duplex, int fc, int mac_was_reset); void t3_os_phymod_changed(struct adapter *adap, int port_id); void t3_sge_err_intr_handler(adapter_t *adapter); int t3_offload_tx(struct t3cdev *, struct mbuf *); void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]); int t3_mgmt_tx(adapter_t *adap, struct mbuf *m); int t3_sge_alloc(struct adapter *); int t3_sge_free(struct adapter *); int t3_sge_alloc_qset(adapter_t *, uint32_t, int, int, const struct qset_params *, int, struct port_info *); -void t3_free_sge_resources(adapter_t *); +void t3_free_sge_resources(adapter_t *, int); void t3_sge_start(adapter_t *); void t3_sge_stop(adapter_t *); void t3b_intr(void *data); void t3_intr_msi(void *data); void t3_intr_msix(void *data); int t3_encap(struct sge_qset *, struct mbuf **, int); int t3_sge_init_adapter(adapter_t *); int t3_sge_reset_adapter(adapter_t *); int t3_sge_init_port(struct port_info *); void t3_sge_deinit_sw(adapter_t *); void t3_free_tx_desc(struct sge_txq *q, int n); void t3_free_tx_desc_all(struct sge_txq *q); void t3_rx_eth(struct adapter *adap, struct sge_rspq *rq, struct mbuf *m, int ethpad); void t3_add_attach_sysctls(adapter_t *sc); void t3_add_configured_sysctls(adapter_t *sc); int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, unsigned char *data); void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p); /* * XXX figure out how we can return this to being private to sge */ #define desc_reclaimable(q) ((int)((q)->processed - (q)->cleaned - TX_MAX_DESC)) #define container_of(p, stype, field) ((stype *)(((uint8_t *)(p)) - offsetof(stype, field))) static __inline struct sge_qset * fl_to_qset(struct sge_fl *q, int qidx) { return container_of(q, struct sge_qset, fl[qidx]); } static __inline struct sge_qset * rspq_to_qset(struct sge_rspq *q) { return container_of(q, struct sge_qset, rspq); } static __inline struct sge_qset * txq_to_qset(struct sge_txq *q, int qidx) { return container_of(q, struct sge_qset, txq[qidx]); } static __inline struct adapter * tdev2adap(struct t3cdev *d) { return container_of(d, struct adapter, tdev); } #undef container_of #define OFFLOAD_DEVMAP_BIT 15 static inline int offload_running(adapter_t *adapter) { return isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); } int cxgb_pcpu_enqueue_packet(struct ifnet *ifp, struct mbuf *m); int cxgb_pcpu_start(struct ifnet *ifp, struct mbuf *m); void cxgb_pcpu_shutdown_threads(struct adapter *sc); void cxgb_pcpu_startup_threads(struct adapter *sc); int process_responses(adapter_t *adap, struct sge_qset *qs, int budget); void t3_free_qset(adapter_t *sc, struct sge_qset *q); void cxgb_start(struct ifnet *ifp); void refill_fl_service(adapter_t *adap, struct sge_fl *fl); #endif Index: stable/7/sys/dev/cxgb/cxgb_main.c =================================================================== --- stable/7/sys/dev/cxgb/cxgb_main.c (revision 220340) +++ stable/7/sys/dev/cxgb/cxgb_main.c (revision 220341) @@ -1,3435 +1,3436 @@ /************************************************************************** Copyright (c) 2007-2009, Chelsio Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Neither the name of the Chelsio Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ***************************************************************************/ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef CONFIG_DEFINED #include #else #include #endif #ifdef PRIV_SUPPORTED #include #endif static int cxgb_setup_interrupts(adapter_t *); static void cxgb_teardown_interrupts(adapter_t *); static void cxgb_init(void *); static int cxgb_init_locked(struct port_info *); static int cxgb_uninit_locked(struct port_info *); static int cxgb_uninit_synchronized(struct port_info *); static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t); static int cxgb_media_change(struct ifnet *); static int cxgb_ifm_type(int); static void cxgb_build_medialist(struct port_info *); static void cxgb_media_status(struct ifnet *, struct ifmediareq *); static int setup_sge_qsets(adapter_t *); static void cxgb_async_intr(void *); static void cxgb_tick_handler(void *, int); static void cxgb_tick(void *); static void link_check_callout(void *); static void check_link_status(void *, int); static void setup_rss(adapter_t *sc); static int alloc_filters(struct adapter *); static int setup_hw_filters(struct adapter *); static int set_filter(struct adapter *, int, const struct filter_info *); static inline void mk_set_tcb_field(struct cpl_set_tcb_field *, unsigned int, unsigned int, u64, u64); static inline void set_tcb_field_ulp(struct cpl_set_tcb_field *, unsigned int, unsigned int, u64, u64); /* Attachment glue for the PCI controller end of the device. Each port of * the device is attached separately, as defined later. */ static int cxgb_controller_probe(device_t); static int cxgb_controller_attach(device_t); static int cxgb_controller_detach(device_t); static void cxgb_free(struct adapter *); static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, unsigned int end); static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf); static int cxgb_get_regs_len(void); static int offload_open(struct port_info *pi); static void touch_bars(device_t dev); static int offload_close(struct t3cdev *tdev); static void cxgb_update_mac_settings(struct port_info *p); static device_method_t cxgb_controller_methods[] = { DEVMETHOD(device_probe, cxgb_controller_probe), DEVMETHOD(device_attach, cxgb_controller_attach), DEVMETHOD(device_detach, cxgb_controller_detach), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), { 0, 0 } }; static driver_t cxgb_controller_driver = { "cxgbc", cxgb_controller_methods, sizeof(struct adapter) }; static devclass_t cxgb_controller_devclass; DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0); /* * Attachment glue for the ports. Attachment is done directly to the * controller device. */ static int cxgb_port_probe(device_t); static int cxgb_port_attach(device_t); static int cxgb_port_detach(device_t); static device_method_t cxgb_port_methods[] = { DEVMETHOD(device_probe, cxgb_port_probe), DEVMETHOD(device_attach, cxgb_port_attach), DEVMETHOD(device_detach, cxgb_port_detach), { 0, 0 } }; static driver_t cxgb_port_driver = { "cxgb", cxgb_port_methods, 0 }; static d_ioctl_t cxgb_extension_ioctl; static d_open_t cxgb_extension_open; static d_close_t cxgb_extension_close; static struct cdevsw cxgb_cdevsw = { .d_version = D_VERSION, .d_flags = 0, .d_open = cxgb_extension_open, .d_close = cxgb_extension_close, .d_ioctl = cxgb_extension_ioctl, .d_name = "cxgb", }; static devclass_t cxgb_port_devclass; DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0); /* * The driver uses the best interrupt scheme available on a platform in the * order MSI-X, MSI, legacy pin interrupts. This parameter determines which * of these schemes the driver may consider as follows: * * msi = 2: choose from among all three options * msi = 1 : only consider MSI and pin interrupts * msi = 0: force pin interrupts */ static int msi_allowed = 2; TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed); SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters"); SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0, "MSI-X, MSI, INTx selector"); /* * The driver enables offload as a default. * To disable it, use ofld_disable = 1. */ static int ofld_disable = 0; TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable); SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0, "disable ULP offload"); /* * The driver uses an auto-queue algorithm by default. * To disable it and force a single queue-set per port, use multiq = 0 */ static int multiq = 1; TUNABLE_INT("hw.cxgb.multiq", &multiq); SYSCTL_UINT(_hw_cxgb, OID_AUTO, multiq, CTLFLAG_RDTUN, &multiq, 0, "use min(ncpus/ports, 8) queue-sets per port"); /* * By default the driver will not update the firmware unless * it was compiled against a newer version * */ static int force_fw_update = 0; TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update); SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0, "update firmware even if up to date"); int cxgb_use_16k_clusters = 1; TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters); SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN, &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue "); /* * Tune the size of the output queue. */ int cxgb_snd_queue_len = IFQ_MAXLEN; TUNABLE_INT("hw.cxgb.snd_queue_len", &cxgb_snd_queue_len); SYSCTL_UINT(_hw_cxgb, OID_AUTO, snd_queue_len, CTLFLAG_RDTUN, &cxgb_snd_queue_len, 0, "send queue size "); static int nfilters = -1; TUNABLE_INT("hw.cxgb.nfilters", &nfilters); SYSCTL_INT(_hw_cxgb, OID_AUTO, nfilters, CTLFLAG_RDTUN, &nfilters, 0, "max number of entries in the filter table"); enum { MAX_TXQ_ENTRIES = 16384, MAX_CTRL_TXQ_ENTRIES = 1024, MAX_RSPQ_ENTRIES = 16384, MAX_RX_BUFFERS = 16384, MAX_RX_JUMBO_BUFFERS = 16384, MIN_TXQ_ENTRIES = 4, MIN_CTRL_TXQ_ENTRIES = 4, MIN_RSPQ_ENTRIES = 32, MIN_FL_ENTRIES = 32, MIN_FL_JUMBO_ENTRIES = 32 }; struct filter_info { u32 sip; u32 sip_mask; u32 dip; u16 sport; u16 dport; u32 vlan:12; u32 vlan_prio:3; u32 mac_hit:1; u32 mac_idx:4; u32 mac_vld:1; u32 pkt_type:2; u32 report_filter_id:1; u32 pass:1; u32 rss:1; u32 qset:3; u32 locked:1; u32 valid:1; }; enum { FILTER_NO_VLAN_PRI = 7 }; #define EEPROM_MAGIC 0x38E2F10C #define PORT_MASK ((1 << MAX_NPORTS) - 1) /* Table for probing the cards. The desc field isn't actually used */ struct cxgb_ident { uint16_t vendor; uint16_t device; int index; char *desc; } cxgb_identifiers[] = { {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"}, {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"}, {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"}, {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"}, {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"}, {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"}, {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"}, {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"}, {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"}, {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"}, {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"}, {PCI_VENDOR_ID_CHELSIO, 0x0035, 6, "T3C10"}, {PCI_VENDOR_ID_CHELSIO, 0x0036, 3, "S320E-CR"}, {PCI_VENDOR_ID_CHELSIO, 0x0037, 7, "N320E-G2"}, {0, 0, 0, NULL} }; static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset); static __inline char t3rev2char(struct adapter *adapter) { char rev = 'z'; switch(adapter->params.rev) { case T3_REV_A: rev = 'a'; break; case T3_REV_B: case T3_REV_B2: rev = 'b'; break; case T3_REV_C: rev = 'c'; break; } return rev; } static struct cxgb_ident * cxgb_get_ident(device_t dev) { struct cxgb_ident *id; for (id = cxgb_identifiers; id->desc != NULL; id++) { if ((id->vendor == pci_get_vendor(dev)) && (id->device == pci_get_device(dev))) { return (id); } } return (NULL); } static const struct adapter_info * cxgb_get_adapter_info(device_t dev) { struct cxgb_ident *id; const struct adapter_info *ai; id = cxgb_get_ident(dev); if (id == NULL) return (NULL); ai = t3_get_adapter_info(id->index); return (ai); } static int cxgb_controller_probe(device_t dev) { const struct adapter_info *ai; char *ports, buf[80]; int nports; ai = cxgb_get_adapter_info(dev); if (ai == NULL) return (ENXIO); nports = ai->nports0 + ai->nports1; if (nports == 1) ports = "port"; else ports = "ports"; snprintf(buf, sizeof(buf), "%s, %d %s", ai->desc, nports, ports); device_set_desc_copy(dev, buf); return (BUS_PROBE_DEFAULT); } #define FW_FNAME "cxgb_t3fw" #define TPEEPROM_NAME "cxgb_t3%c_tp_eeprom" #define TPSRAM_NAME "cxgb_t3%c_protocol_sram" static int upgrade_fw(adapter_t *sc) { #ifdef FIRMWARE_LATEST const struct firmware *fw; #else struct firmware *fw; #endif int status; u32 vers; if ((fw = firmware_get(FW_FNAME)) == NULL) { device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME); return (ENOENT); } else device_printf(sc->dev, "installing firmware on card\n"); status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize); if (status != 0) { device_printf(sc->dev, "failed to install firmware: %d\n", status); } else { t3_get_fw_version(sc, &vers); snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); } firmware_put(fw, FIRMWARE_UNLOAD); return (status); } /* * The cxgb_controller_attach function is responsible for the initial * bringup of the device. Its responsibilities include: * * 1. Determine if the device supports MSI or MSI-X. * 2. Allocate bus resources so that we can access the Base Address Register * 3. Create and initialize mutexes for the controller and its control * logic such as SGE and MDIO. * 4. Call hardware specific setup routine for the adapter as a whole. * 5. Allocate the BAR for doing MSI-X. * 6. Setup the line interrupt iff MSI-X is not supported. * 7. Create the driver's taskq. * 8. Start one task queue service thread. * 9. Check if the firmware and SRAM are up-to-date. They will be * auto-updated later (before FULL_INIT_DONE), if required. * 10. Create a child device for each MAC (port) * 11. Initialize T3 private state. * 12. Trigger the LED * 13. Setup offload iff supported. * 14. Reset/restart the tick callout. * 15. Attach sysctls * * NOTE: Any modification or deviation from this list MUST be reflected in * the above comment. Failure to do so will result in problems on various * error conditions including link flapping. */ static int cxgb_controller_attach(device_t dev) { device_t child; const struct adapter_info *ai; struct adapter *sc; int i, error = 0; uint32_t vers; int port_qsets = 1; #ifdef MSI_SUPPORTED int msi_needed, reg; #endif char buf[80]; sc = device_get_softc(dev); sc->dev = dev; sc->msi_count = 0; ai = cxgb_get_adapter_info(dev); /* * XXX not really related but a recent addition */ #ifdef MSI_SUPPORTED /* find the PCIe link width and set max read request to 4KB*/ if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { uint16_t lnk; lnk = pci_read_config(dev, reg + PCIR_EXPRESS_LINK_STA, 2); sc->link_width = (lnk & PCIM_LINK_STA_WIDTH) >> 4; if (sc->link_width < 8 && (ai->caps & SUPPORTED_10000baseT_Full)) { device_printf(sc->dev, "PCIe x%d Link, expect reduced performance\n", sc->link_width); } pci_set_max_read_req(dev, 4096); } #endif touch_bars(dev); pci_enable_busmaster(dev); /* * Allocate the registers and make them available to the driver. * The registers that we care about for NIC mode are in BAR 0 */ sc->regs_rid = PCIR_BAR(0); if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regs_rid, RF_ACTIVE)) == NULL) { device_printf(dev, "Cannot allocate BAR region 0\n"); return (ENXIO); } sc->udbs_rid = PCIR_BAR(2); sc->udbs_res = NULL; if (is_offload(sc) && ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->udbs_rid, RF_ACTIVE)) == NULL)) { device_printf(dev, "Cannot allocate BAR region 1\n"); error = ENXIO; goto out; } snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d", device_get_unit(dev)); ADAPTER_LOCK_INIT(sc, sc->lockbuf); snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d", device_get_unit(dev)); snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d", device_get_unit(dev)); snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d", device_get_unit(dev)); MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN); MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF); MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF); sc->bt = rman_get_bustag(sc->regs_res); sc->bh = rman_get_bushandle(sc->regs_res); sc->mmio_len = rman_get_size(sc->regs_res); for (i = 0; i < MAX_NPORTS; i++) sc->port[i].adapter = sc; if (t3_prep_adapter(sc, ai, 1) < 0) { printf("prep adapter failed\n"); error = ENODEV; goto out; } /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate * enough messages for the queue sets. If that fails, try falling * back to MSI. If that fails, then try falling back to the legacy * interrupt pin model. */ #ifdef MSI_SUPPORTED sc->msix_regs_rid = 0x20; if ((msi_allowed >= 2) && (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->msix_regs_rid, RF_ACTIVE)) != NULL) { if (multiq) port_qsets = min(SGE_QSETS/sc->params.nports, mp_ncpus); msi_needed = sc->msi_count = sc->params.nports * port_qsets + 1; if (pci_msix_count(dev) == 0 || (error = pci_alloc_msix(dev, &sc->msi_count)) != 0 || sc->msi_count != msi_needed) { device_printf(dev, "alloc msix failed - " "msi_count=%d, msi_needed=%d, err=%d; " "will try MSI\n", sc->msi_count, msi_needed, error); sc->msi_count = 0; port_qsets = 1; pci_release_msi(dev); bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_regs_rid, sc->msix_regs_res); sc->msix_regs_res = NULL; } else { sc->flags |= USING_MSIX; sc->cxgb_intr = cxgb_async_intr; device_printf(dev, "using MSI-X interrupts (%u vectors)\n", sc->msi_count); } } if ((msi_allowed >= 1) && (sc->msi_count == 0)) { sc->msi_count = 1; if ((error = pci_alloc_msi(dev, &sc->msi_count)) != 0) { device_printf(dev, "alloc msi failed - " "err=%d; will try INTx\n", error); sc->msi_count = 0; port_qsets = 1; pci_release_msi(dev); } else { sc->flags |= USING_MSI; sc->cxgb_intr = t3_intr_msi; device_printf(dev, "using MSI interrupts\n"); } } #endif if (sc->msi_count == 0) { device_printf(dev, "using line interrupts\n"); sc->cxgb_intr = t3b_intr; } /* Create a private taskqueue thread for handling driver events */ #ifdef TASKQUEUE_CURRENT sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT, taskqueue_thread_enqueue, &sc->tq); #else sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT, taskqueue_thread_enqueue, &sc->tq); #endif if (sc->tq == NULL) { device_printf(dev, "failed to allocate controller task queue\n"); goto out; } taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq", device_get_nameunit(dev)); TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc); /* Create a periodic callout for checking adapter status */ callout_init(&sc->cxgb_tick_ch, TRUE); if (t3_check_fw_version(sc) < 0 || force_fw_update) { /* * Warn user that a firmware update will be attempted in init. */ device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n", FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO); sc->flags &= ~FW_UPTODATE; } else { sc->flags |= FW_UPTODATE; } if (t3_check_tpsram_version(sc) < 0) { /* * Warn user that a firmware update will be attempted in init. */ device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n", t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); sc->flags &= ~TPS_UPTODATE; } else { sc->flags |= TPS_UPTODATE; } /* * Create a child device for each MAC. The ethernet attachment * will be done in these children. */ for (i = 0; i < (sc)->params.nports; i++) { struct port_info *pi; if ((child = device_add_child(dev, "cxgb", -1)) == NULL) { device_printf(dev, "failed to add child port\n"); error = EINVAL; goto out; } pi = &sc->port[i]; pi->adapter = sc; pi->nqsets = port_qsets; pi->first_qset = i*port_qsets; pi->port_id = i; pi->tx_chan = i >= ai->nports0; pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i; sc->rxpkt_map[pi->txpkt_intf] = i; sc->port[i].tx_chan = i >= ai->nports0; sc->portdev[i] = child; device_set_softc(child, pi); } if ((error = bus_generic_attach(dev)) != 0) goto out; /* initialize sge private state */ t3_sge_init_adapter(sc); t3_led_ready(sc); cxgb_offload_init(); if (is_offload(sc)) { setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); cxgb_adapter_ofld(sc); } error = t3_get_fw_version(sc, &vers); if (error) goto out; snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); snprintf(buf, sizeof(buf), "%s %sNIC\t E/C: %s S/N: %s", ai->desc, is_offload(sc) ? "R" : "", sc->params.vpd.ec, sc->params.vpd.sn); device_set_desc_copy(dev, buf); snprintf(&sc->port_types[0], sizeof(sc->port_types), "%x%x%x%x", sc->params.vpd.port_type[0], sc->params.vpd.port_type[1], sc->params.vpd.port_type[2], sc->params.vpd.port_type[3]); device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]); callout_reset(&sc->cxgb_tick_ch, hz, cxgb_tick, sc); t3_add_attach_sysctls(sc); out: if (error) cxgb_free(sc); return (error); } /* * The cxgb_controller_detach routine is called with the device is * unloaded from the system. */ static int cxgb_controller_detach(device_t dev) { struct adapter *sc; sc = device_get_softc(dev); cxgb_free(sc); return (0); } /* * The cxgb_free() is called by the cxgb_controller_detach() routine * to tear down the structures that were built up in * cxgb_controller_attach(), and should be the final piece of work * done when fully unloading the driver. * * * 1. Shutting down the threads started by the cxgb_controller_attach() * routine. * 2. Stopping the lower level device and all callouts (cxgb_down_locked()). * 3. Detaching all of the port devices created during the * cxgb_controller_attach() routine. * 4. Removing the device children created via cxgb_controller_attach(). * 5. Releasing PCI resources associated with the device. * 6. Turning off the offload support, iff it was turned on. * 7. Destroying the mutexes created in cxgb_controller_attach(). * */ static void cxgb_free(struct adapter *sc) { - int i; + int i, nqsets = 0; ADAPTER_LOCK(sc); sc->flags |= CXGB_SHUTDOWN; ADAPTER_UNLOCK(sc); cxgb_pcpu_shutdown_threads(sc); t3_sge_deinit_sw(sc); /* * Make sure all child devices are gone. */ bus_generic_detach(sc->dev); for (i = 0; i < (sc)->params.nports; i++) { if (sc->portdev[i] && device_delete_child(sc->dev, sc->portdev[i]) != 0) device_printf(sc->dev, "failed to delete child port\n"); + nqsets += sc->port[i].nqsets; } /* * At this point, it is as if cxgb_port_detach has run on all ports, and * cxgb_down has run on the adapter. All interrupts have been silenced, * all open devices have been closed. */ KASSERT(sc->open_device_map == 0, ("%s: device(s) still open (%x)", __func__, sc->open_device_map)); for (i = 0; i < sc->params.nports; i++) { KASSERT(sc->port[i].ifp == NULL, ("%s: port %i undead!", __func__, i)); } /* * Finish off the adapter's callouts. */ callout_drain(&sc->cxgb_tick_ch); callout_drain(&sc->sge_timer_ch); /* * Release resources grabbed under FULL_INIT_DONE by cxgb_up. The * sysctls are cleaned up by the kernel linker. */ if (sc->flags & FULL_INIT_DONE) { - t3_free_sge_resources(sc); + t3_free_sge_resources(sc, nqsets); sc->flags &= ~FULL_INIT_DONE; } /* * Release all interrupt resources. */ cxgb_teardown_interrupts(sc); #ifdef MSI_SUPPORTED if (sc->flags & (USING_MSI | USING_MSIX)) { device_printf(sc->dev, "releasing msi message(s)\n"); pci_release_msi(sc->dev); } else { device_printf(sc->dev, "no msi message to release\n"); } if (sc->msix_regs_res != NULL) { bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid, sc->msix_regs_res); } #endif /* * Free the adapter's taskqueue. */ if (sc->tq != NULL) { taskqueue_free(sc->tq); sc->tq = NULL; } if (is_offload(sc)) { clrbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT); cxgb_adapter_unofld(sc); } #ifdef notyet if (sc->flags & CXGB_OFLD_INIT) cxgb_offload_deactivate(sc); #endif free(sc->filters, M_DEVBUF); t3_sge_free(sc); cxgb_offload_exit(); if (sc->udbs_res != NULL) bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid, sc->udbs_res); if (sc->regs_res != NULL) bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid, sc->regs_res); MTX_DESTROY(&sc->mdio_lock); MTX_DESTROY(&sc->sge.reg_lock); MTX_DESTROY(&sc->elmer_lock); ADAPTER_LOCK_DEINIT(sc); } /** * setup_sge_qsets - configure SGE Tx/Rx/response queues * @sc: the controller softc * * Determines how many sets of SGE queues to use and initializes them. * We support multiple queue sets per port if we have MSI-X, otherwise * just one queue set per port. */ static int setup_sge_qsets(adapter_t *sc) { int i, j, err, irq_idx = 0, qset_idx = 0; u_int ntxq = SGE_TXQ_PER_SET; if ((err = t3_sge_alloc(sc)) != 0) { device_printf(sc->dev, "t3_sge_alloc returned %d\n", err); return (err); } if (sc->params.rev > 0 && !(sc->flags & USING_MSI)) irq_idx = -1; for (i = 0; i < (sc)->params.nports; i++) { struct port_info *pi = &sc->port[i]; for (j = 0; j < pi->nqsets; j++, qset_idx++) { err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports, (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx, &sc->params.sge.qset[qset_idx], ntxq, pi); if (err) { - t3_free_sge_resources(sc); - device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n", - err); + t3_free_sge_resources(sc, qset_idx); + device_printf(sc->dev, + "t3_sge_alloc_qset failed with %d\n", err); return (err); } } } return (0); } static void cxgb_teardown_interrupts(adapter_t *sc) { int i; for (i = 0; i < SGE_QSETS; i++) { if (sc->msix_intr_tag[i] == NULL) { /* Should have been setup fully or not at all */ KASSERT(sc->msix_irq_res[i] == NULL && sc->msix_irq_rid[i] == 0, ("%s: half-done interrupt (%d).", __func__, i)); continue; } bus_teardown_intr(sc->dev, sc->msix_irq_res[i], sc->msix_intr_tag[i]); bus_release_resource(sc->dev, SYS_RES_IRQ, sc->msix_irq_rid[i], sc->msix_irq_res[i]); sc->msix_irq_res[i] = sc->msix_intr_tag[i] = NULL; sc->msix_irq_rid[i] = 0; } if (sc->intr_tag) { KASSERT(sc->irq_res != NULL, ("%s: half-done interrupt.", __func__)); bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag); bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, sc->irq_res); sc->irq_res = sc->intr_tag = NULL; sc->irq_rid = 0; } } static int cxgb_setup_interrupts(adapter_t *sc) { struct resource *res; void *tag; int i, rid, err, intr_flag = sc->flags & (USING_MSI | USING_MSIX); sc->irq_rid = intr_flag ? 1 : 0; sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irq_rid, RF_SHAREABLE | RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(sc->dev, "Cannot allocate interrupt (%x, %u)\n", intr_flag, sc->irq_rid); err = EINVAL; sc->irq_rid = 0; } else { err = bus_setup_intr(sc->dev, sc->irq_res, INTR_MPSAFE | INTR_TYPE_NET, #ifdef INTR_FILTERS NULL, #endif sc->cxgb_intr, sc, &sc->intr_tag); if (err) { device_printf(sc->dev, "Cannot set up interrupt (%x, %u, %d)\n", intr_flag, sc->irq_rid, err); bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid, sc->irq_res); sc->irq_res = sc->intr_tag = NULL; sc->irq_rid = 0; } } /* That's all for INTx or MSI */ if (!(intr_flag & USING_MSIX) || err) return (err); for (i = 0; i < sc->msi_count - 1; i++) { rid = i + 2; res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (res == NULL) { device_printf(sc->dev, "Cannot allocate interrupt " "for message %d\n", rid); err = EINVAL; break; } err = bus_setup_intr(sc->dev, res, INTR_MPSAFE | INTR_TYPE_NET, #ifdef INTR_FILTERS NULL, #endif t3_intr_msix, &sc->sge.qs[i], &tag); if (err) { device_printf(sc->dev, "Cannot set up interrupt " "for message %d (%d)\n", rid, err); bus_release_resource(sc->dev, SYS_RES_IRQ, rid, res); break; } sc->msix_irq_rid[i] = rid; sc->msix_irq_res[i] = res; sc->msix_intr_tag[i] = tag; } if (err) cxgb_teardown_interrupts(sc); return (err); } static int cxgb_port_probe(device_t dev) { struct port_info *p; char buf[80]; const char *desc; p = device_get_softc(dev); desc = p->phy.desc; snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc); device_set_desc_copy(dev, buf); return (0); } static int cxgb_makedev(struct port_info *pi) { pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit, UID_ROOT, GID_WHEEL, 0600, "%s", if_name(pi->ifp)); if (pi->port_cdev == NULL) return (ENOMEM); pi->port_cdev->si_drv1 = (void *)pi; return (0); } #ifdef TSO_SUPPORTED #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | IFCAP_VLAN_HWTSO) /* Don't enable TSO6 yet */ #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_LRO | IFCAP_VLAN_HWTSO) #else #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) /* Don't enable TSO6 yet */ #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU) #define IFCAP_TSO4 0x0 #define IFCAP_TSO6 0x0 #define CSUM_TSO 0x0 #endif static int cxgb_port_attach(device_t dev) { struct port_info *p; struct ifnet *ifp; int err; struct adapter *sc; p = device_get_softc(dev); sc = p->adapter; snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d", device_get_unit(device_get_parent(dev)), p->port_id); PORT_LOCK_INIT(p, p->lockbuf); callout_init(&p->link_check_ch, CALLOUT_MPSAFE); TASK_INIT(&p->link_check_task, 0, check_link_status, p); /* Allocate an ifnet object and set it up */ ifp = p->ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "Cannot allocate ifnet\n"); return (ENOMEM); } /* * Note that there is currently no watchdog timer. */ if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_init = cxgb_init; ifp->if_softc = p; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = cxgb_ioctl; ifp->if_start = cxgb_start; ifp->if_timer = 0; /* Disable ifnet watchdog */ ifp->if_watchdog = NULL; ifp->if_snd.ifq_drv_maxlen = max(cxgb_snd_queue_len, ifqmaxlen); IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); IFQ_SET_READY(&ifp->if_snd); ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0; ifp->if_capabilities |= CXGB_CAP; ifp->if_capenable |= CXGB_CAP_ENABLE; ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO); /* * disable TSO on 4-port - it isn't supported by the firmware yet */ if (sc->params.nports > 2) { ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTSO); ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTSO); ifp->if_hwassist &= ~CSUM_TSO; } ether_ifattach(ifp, p->hw_addr); #ifdef IFNET_MULTIQUEUE ifp->if_transmit = cxgb_pcpu_transmit; #endif /* * Only default to jumbo frames on 10GigE */ if (p->adapter->params.nports <= 2) ifp->if_mtu = ETHERMTU_JUMBO; if ((err = cxgb_makedev(p)) != 0) { printf("makedev failed %d\n", err); return (err); } /* Create a list of media supported by this port */ ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change, cxgb_media_status); cxgb_build_medialist(p); t3_sge_init_port(p); return (err); } /* * cxgb_port_detach() is called via the device_detach methods when * cxgb_free() calls the bus_generic_detach. It is responsible for * removing the device from the view of the kernel, i.e. from all * interfaces lists etc. This routine is only called when the driver is * being unloaded, not when the link goes down. */ static int cxgb_port_detach(device_t dev) { struct port_info *p; struct adapter *sc; p = device_get_softc(dev); sc = p->adapter; /* Tell cxgb_ioctl and if_init that the port is going away */ ADAPTER_LOCK(sc); SET_DOOMED(p); wakeup(&sc->flags); while (IS_BUSY(sc)) mtx_sleep(&sc->flags, &sc->lock, 0, "cxgbdtch", 0); SET_BUSY(sc); ADAPTER_UNLOCK(sc); if (p->port_cdev != NULL) destroy_dev(p->port_cdev); cxgb_uninit_synchronized(p); ether_ifdetach(p->ifp); PORT_LOCK_DEINIT(p); if_free(p->ifp); p->ifp = NULL; ADAPTER_LOCK(sc); CLR_BUSY(sc); wakeup_one(&sc->flags); ADAPTER_UNLOCK(sc); return (0); } void t3_fatal_err(struct adapter *sc) { u_int fw_status[4]; if (sc->flags & FULL_INIT_DONE) { t3_sge_stop(sc); t3_write_reg(sc, A_XGM_TX_CTRL, 0); t3_write_reg(sc, A_XGM_RX_CTRL, 0); t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0); t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0); t3_intr_disable(sc); } device_printf(sc->dev,"encountered fatal error, operation suspended\n"); if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status)) device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n", fw_status[0], fw_status[1], fw_status[2], fw_status[3]); } int t3_os_find_pci_capability(adapter_t *sc, int cap) { device_t dev; struct pci_devinfo *dinfo; pcicfgregs *cfg; uint32_t status; uint8_t ptr; dev = sc->dev; dinfo = device_get_ivars(dev); cfg = &dinfo->cfg; status = pci_read_config(dev, PCIR_STATUS, 2); if (!(status & PCIM_STATUS_CAPPRESENT)) return (0); switch (cfg->hdrtype & PCIM_HDRTYPE) { case 0: case 1: ptr = PCIR_CAP_PTR; break; case 2: ptr = PCIR_CAP_PTR_2; break; default: return (0); break; } ptr = pci_read_config(dev, ptr, 1); while (ptr != 0) { if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap) return (ptr); ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1); } return (0); } int t3_os_pci_save_state(struct adapter *sc) { device_t dev; struct pci_devinfo *dinfo; dev = sc->dev; dinfo = device_get_ivars(dev); pci_cfg_save(dev, dinfo, 0); return (0); } int t3_os_pci_restore_state(struct adapter *sc) { device_t dev; struct pci_devinfo *dinfo; dev = sc->dev; dinfo = device_get_ivars(dev); pci_cfg_restore(dev, dinfo); return (0); } /** * t3_os_link_changed - handle link status changes * @sc: the adapter associated with the link change * @port_id: the port index whose link status has changed * @link_status: the new status of the link * @speed: the new speed setting * @duplex: the new duplex setting * @fc: the new flow-control setting * * This is the OS-dependent handler for link status changes. The OS * neutral handler takes care of most of the processing for these events, * then calls this handler for any OS-specific processing. */ void t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed, int duplex, int fc, int mac_was_reset) { struct port_info *pi = &adapter->port[port_id]; struct ifnet *ifp = pi->ifp; /* no race with detach, so ifp should always be good */ KASSERT(ifp, ("%s: if detached.", __func__)); /* Reapply mac settings if they were lost due to a reset */ if (mac_was_reset) { PORT_LOCK(pi); cxgb_update_mac_settings(pi); PORT_UNLOCK(pi); } if (link_status) { ifp->if_baudrate = IF_Mbps(speed); if_link_state_change(ifp, LINK_STATE_UP); } else if_link_state_change(ifp, LINK_STATE_DOWN); } /** * t3_os_phymod_changed - handle PHY module changes * @phy: the PHY reporting the module change * @mod_type: new module type * * This is the OS-dependent handler for PHY module changes. It is * invoked when a PHY module is removed or inserted for any OS-specific * processing. */ void t3_os_phymod_changed(struct adapter *adap, int port_id) { static const char *mod_str[] = { NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX-L", "unknown" }; struct port_info *pi = &adap->port[port_id]; int mod = pi->phy.modtype; if (mod != pi->media.ifm_cur->ifm_data) cxgb_build_medialist(pi); if (mod == phy_modtype_none) if_printf(pi->ifp, "PHY module unplugged\n"); else { KASSERT(mod < ARRAY_SIZE(mod_str), ("invalid PHY module type %d", mod)); if_printf(pi->ifp, "%s PHY module inserted\n", mod_str[mod]); } } void t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[]) { /* * The ifnet might not be allocated before this gets called, * as this is called early on in attach by t3_prep_adapter * save the address off in the port structure */ if (cxgb_debug) printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":"); bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN); } /* * Programs the XGMAC based on the settings in the ifnet. These settings * include MTU, MAC address, mcast addresses, etc. */ static void cxgb_update_mac_settings(struct port_info *p) { struct ifnet *ifp = p->ifp; struct t3_rx_mode rm; struct cmac *mac = &p->mac; int mtu, hwtagging; PORT_LOCK_ASSERT_OWNED(p); bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN); mtu = ifp->if_mtu; if (ifp->if_capenable & IFCAP_VLAN_MTU) mtu += ETHER_VLAN_ENCAP_LEN; hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0; t3_mac_set_mtu(mac, mtu); t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging); t3_mac_set_address(mac, 0, p->hw_addr); t3_init_rx_mode(&rm, p); t3_mac_set_rx_mode(mac, &rm); } static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, unsigned long n) { int attempts = 5; while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { if (!--attempts) return (ETIMEDOUT); t3_os_sleep(10); } return 0; } static int init_tp_parity(struct adapter *adap) { int i; struct mbuf *m; struct cpl_set_tcb_field *greq; unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; t3_tp_set_offload_mode(adap, 1); for (i = 0; i < 16; i++) { struct cpl_smt_write_req *req; m = m_gethdr(M_WAITOK, MT_DATA); req = mtod(m, struct cpl_smt_write_req *); m->m_len = m->m_pkthdr.len = sizeof(*req); memset(req, 0, sizeof(*req)); req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i)); req->iff = i; t3_mgmt_tx(adap, m); } for (i = 0; i < 2048; i++) { struct cpl_l2t_write_req *req; m = m_gethdr(M_WAITOK, MT_DATA); req = mtod(m, struct cpl_l2t_write_req *); m->m_len = m->m_pkthdr.len = sizeof(*req); memset(req, 0, sizeof(*req)); req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i)); req->params = htonl(V_L2T_W_IDX(i)); t3_mgmt_tx(adap, m); } for (i = 0; i < 2048; i++) { struct cpl_rte_write_req *req; m = m_gethdr(M_WAITOK, MT_DATA); req = mtod(m, struct cpl_rte_write_req *); m->m_len = m->m_pkthdr.len = sizeof(*req); memset(req, 0, sizeof(*req)); req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i)); req->l2t_idx = htonl(V_L2T_W_IDX(i)); t3_mgmt_tx(adap, m); } m = m_gethdr(M_WAITOK, MT_DATA); greq = mtod(m, struct cpl_set_tcb_field *); m->m_len = m->m_pkthdr.len = sizeof(*greq); memset(greq, 0, sizeof(*greq)); greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0)); greq->mask = htobe64(1); t3_mgmt_tx(adap, m); i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1); t3_tp_set_offload_mode(adap, 0); return (i); } /** * setup_rss - configure Receive Side Steering (per-queue connection demux) * @adap: the adapter * * Sets up RSS to distribute packets to multiple receive queues. We * configure the RSS CPU lookup table to distribute to the number of HW * receive queues, and the response queue lookup table to narrow that * down to the response queues actually configured for each port. * We always configure the RSS mapping for two ports since the mapping * table has plenty of entries. */ static void setup_rss(adapter_t *adap) { int i; u_int nq[2]; uint8_t cpus[SGE_QSETS + 1]; uint16_t rspq_map[RSS_TABLE_SIZE]; for (i = 0; i < SGE_QSETS; ++i) cpus[i] = i; cpus[SGE_QSETS] = 0xff; nq[0] = nq[1] = 0; for_each_port(adap, i) { const struct port_info *pi = adap2pinfo(adap, i); nq[pi->tx_chan] += pi->nqsets; } for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) { rspq_map[i] = nq[0] ? i % nq[0] : 0; rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0; } /* Calculate the reverse RSS map table */ for (i = 0; i < SGE_QSETS; ++i) adap->rrss_map[i] = 0xff; for (i = 0; i < RSS_TABLE_SIZE; ++i) if (adap->rrss_map[rspq_map[i]] == 0xff) adap->rrss_map[rspq_map[i]] = i; t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN | F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN | F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map); } /* * Sends an mbuf to an offload queue driver * after dealing with any active network taps. */ static inline int offload_tx(struct t3cdev *tdev, struct mbuf *m) { int ret; ret = t3_offload_tx(tdev, m); return (ret); } static int write_smt_entry(struct adapter *adapter, int idx) { struct port_info *pi = &adapter->port[idx]; struct cpl_smt_write_req *req; struct mbuf *m; if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL) return (ENOMEM); req = mtod(m, struct cpl_smt_write_req *); m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req); req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx)); req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */ req->iff = idx; memset(req->src_mac1, 0, sizeof(req->src_mac1)); memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN); m_set_priority(m, 1); offload_tx(&adapter->tdev, m); return (0); } static int init_smt(struct adapter *adapter) { int i; for_each_port(adapter, i) write_smt_entry(adapter, i); return 0; } static void init_port_mtus(adapter_t *adapter) { unsigned int mtus = ETHERMTU | (ETHERMTU << 16); t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus); } static void send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo, int hi, int port) { struct mbuf *m; struct mngt_pktsched_wr *req; m = m_gethdr(M_DONTWAIT, MT_DATA); if (m) { req = mtod(m, struct mngt_pktsched_wr *); req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT)); req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET; req->sched = sched; req->idx = qidx; req->min = lo; req->max = hi; req->binding = port; m->m_len = m->m_pkthdr.len = sizeof(*req); t3_mgmt_tx(adap, m); } } static void bind_qsets(adapter_t *sc) { int i, j; cxgb_pcpu_startup_threads(sc); for (i = 0; i < (sc)->params.nports; ++i) { const struct port_info *pi = adap2pinfo(sc, i); for (j = 0; j < pi->nqsets; ++j) { send_pktsched_cmd(sc, 1, pi->first_qset + j, -1, -1, pi->tx_chan); } } } static void update_tpeeprom(struct adapter *adap) { #ifdef FIRMWARE_LATEST const struct firmware *tpeeprom; #else struct firmware *tpeeprom; #endif uint32_t version; unsigned int major, minor; int ret, len; char rev, name[32]; t3_seeprom_read(adap, TP_SRAM_OFFSET, &version); major = G_TP_VERSION_MAJOR(version); minor = G_TP_VERSION_MINOR(version); if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR) return; rev = t3rev2char(adap); snprintf(name, sizeof(name), TPEEPROM_NAME, rev); tpeeprom = firmware_get(name); if (tpeeprom == NULL) { device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n", name); return; } len = tpeeprom->datasize - 4; ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize); if (ret) goto release_tpeeprom; if (len != TP_SRAM_LEN) { device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", name, len, TP_SRAM_LEN); return; } ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize, TP_SRAM_OFFSET); if (!ret) { device_printf(adap->dev, "Protocol SRAM image updated in EEPROM to %d.%d.%d\n", TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO); } else device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n"); release_tpeeprom: firmware_put(tpeeprom, FIRMWARE_UNLOAD); return; } static int update_tpsram(struct adapter *adap) { #ifdef FIRMWARE_LATEST const struct firmware *tpsram; #else struct firmware *tpsram; #endif int ret; char rev, name[32]; rev = t3rev2char(adap); snprintf(name, sizeof(name), TPSRAM_NAME, rev); update_tpeeprom(adap); tpsram = firmware_get(name); if (tpsram == NULL){ device_printf(adap->dev, "could not load TP SRAM\n"); return (EINVAL); } else device_printf(adap->dev, "updating TP SRAM\n"); ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize); if (ret) goto release_tpsram; ret = t3_set_proto_sram(adap, tpsram->data); if (ret) device_printf(adap->dev, "loading protocol SRAM failed\n"); release_tpsram: firmware_put(tpsram, FIRMWARE_UNLOAD); return ret; } /** * cxgb_up - enable the adapter * @adap: adapter being enabled * * Called when the first port is enabled, this function performs the * actions necessary to make an adapter operational, such as completing * the initialization of HW modules, and enabling interrupts. */ static int cxgb_up(struct adapter *sc) { int err = 0; unsigned int mxf = t3_mc5_size(&sc->mc5) - MC5_MIN_TIDS; KASSERT(sc->open_device_map == 0, ("%s: device(s) already open (%x)", __func__, sc->open_device_map)); if ((sc->flags & FULL_INIT_DONE) == 0) { ADAPTER_LOCK_ASSERT_NOTOWNED(sc); if ((sc->flags & FW_UPTODATE) == 0) if ((err = upgrade_fw(sc))) goto out; if ((sc->flags & TPS_UPTODATE) == 0) if ((err = update_tpsram(sc))) goto out; if (is_offload(sc) && nfilters != 0) { sc->params.mc5.nservers = 0; if (nfilters < 0) sc->params.mc5.nfilters = mxf; else sc->params.mc5.nfilters = min(nfilters, mxf); } err = t3_init_hw(sc, 0); if (err) goto out; t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT); t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12)); err = setup_sge_qsets(sc); if (err) goto out; alloc_filters(sc); setup_rss(sc); t3_intr_clear(sc); err = cxgb_setup_interrupts(sc); if (err) goto out; t3_add_configured_sysctls(sc); sc->flags |= FULL_INIT_DONE; } t3_intr_clear(sc); t3_sge_start(sc); t3_intr_enable(sc); if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) && is_offload(sc) && init_tp_parity(sc) == 0) sc->flags |= TP_PARITY_INIT; if (sc->flags & TP_PARITY_INIT) { t3_write_reg(sc, A_TP_INT_CAUSE, F_CMCACHEPERR | F_ARPLUTPERR); t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff); } if (!(sc->flags & QUEUES_BOUND)) { bind_qsets(sc); setup_hw_filters(sc); sc->flags |= QUEUES_BOUND; } t3_sge_reset_adapter(sc); out: return (err); } /* * Called when the last open device is closed. Does NOT undo all of cxgb_up's * work. Specifically, the resources grabbed under FULL_INIT_DONE are released * during controller_detach, not here. */ static void cxgb_down(struct adapter *sc) { t3_sge_stop(sc); t3_intr_disable(sc); } static int offload_open(struct port_info *pi) { struct adapter *sc = pi->adapter; struct t3cdev *tdev = &sc->tdev; setbit(&sc->open_device_map, OFFLOAD_DEVMAP_BIT); t3_tp_set_offload_mode(sc, 1); tdev->lldev = pi->ifp; init_port_mtus(sc); t3_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd, sc->params.rev == 0 ? sc->port[0].ifp->if_mtu : 0xffff); init_smt(sc); cxgb_add_clients(tdev); return (0); } static int offload_close(struct t3cdev *tdev) { struct adapter *adapter = tdev2adap(tdev); if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT)) return (0); /* Call back all registered clients */ cxgb_remove_clients(tdev); tdev->lldev = NULL; cxgb_set_dummy_ops(tdev); t3_tp_set_offload_mode(adapter, 0); clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT); return (0); } /* * if_init for cxgb ports. */ static void cxgb_init(void *arg) { struct port_info *p = arg; struct adapter *sc = p->adapter; ADAPTER_LOCK(sc); cxgb_init_locked(p); /* releases adapter lock */ ADAPTER_LOCK_ASSERT_NOTOWNED(sc); } static int cxgb_init_locked(struct port_info *p) { struct adapter *sc = p->adapter; struct ifnet *ifp = p->ifp; struct cmac *mac = &p->mac; int rc = 0, may_sleep = 0, gave_up_lock = 0; ADAPTER_LOCK_ASSERT_OWNED(sc); while (!IS_DOOMED(p) && IS_BUSY(sc)) { gave_up_lock = 1; if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, "cxgbinit", 0)) { rc = EINTR; goto done; } } if (IS_DOOMED(p)) { rc = ENXIO; goto done; } KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); /* * The code that runs during one-time adapter initialization can sleep * so it's important not to hold any locks across it. */ may_sleep = sc->flags & FULL_INIT_DONE ? 0 : 1; if (may_sleep) { SET_BUSY(sc); gave_up_lock = 1; ADAPTER_UNLOCK(sc); } if (sc->open_device_map == 0) { if ((rc = cxgb_up(sc)) != 0) goto done; if (is_offload(sc) && !ofld_disable && offload_open(p)) log(LOG_WARNING, "Could not initialize offload capabilities\n"); } PORT_LOCK(p); if (isset(&sc->open_device_map, p->port_id) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) { PORT_UNLOCK(p); goto done; } t3_port_intr_enable(sc, p->port_id); if (!mac->multiport) t3_mac_init(mac); cxgb_update_mac_settings(p); t3_link_start(&p->phy, mac, &p->link_config); t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; PORT_UNLOCK(p); /* all ok */ setbit(&sc->open_device_map, p->port_id); callout_reset(&p->link_check_ch, p->phy.caps & SUPPORTED_LINK_IRQ ? hz * 3 : hz / 4, link_check_callout, p); done: if (may_sleep) { ADAPTER_LOCK(sc); KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); CLR_BUSY(sc); } if (gave_up_lock) wakeup_one(&sc->flags); ADAPTER_UNLOCK(sc); return (rc); } static int cxgb_uninit_locked(struct port_info *p) { struct adapter *sc = p->adapter; int rc; ADAPTER_LOCK_ASSERT_OWNED(sc); while (!IS_DOOMED(p) && IS_BUSY(sc)) { if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, "cxgbunin", 0)) { rc = EINTR; goto done; } } if (IS_DOOMED(p)) { rc = ENXIO; goto done; } KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); SET_BUSY(sc); ADAPTER_UNLOCK(sc); rc = cxgb_uninit_synchronized(p); ADAPTER_LOCK(sc); KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); CLR_BUSY(sc); wakeup_one(&sc->flags); done: ADAPTER_UNLOCK(sc); return (rc); } /* * Called on "ifconfig down", and from port_detach */ static int cxgb_uninit_synchronized(struct port_info *pi) { struct adapter *sc = pi->adapter; struct ifnet *ifp = pi->ifp; /* * taskqueue_drain may cause a deadlock if the adapter lock is held. */ ADAPTER_LOCK_ASSERT_NOTOWNED(sc); /* * Clear this port's bit from the open device map, and then drain all * the tasks that can access/manipulate this port's port_info or ifp. * We disable this port's interrupts here and so the slow/ext * interrupt tasks won't be enqueued. The tick task will continue to * be enqueued every second but the runs after this drain will not see * this port in the open device map. * * A well behaved task must take open_device_map into account and ignore * ports that are not open. */ clrbit(&sc->open_device_map, pi->port_id); t3_port_intr_disable(sc, pi->port_id); taskqueue_drain(sc->tq, &sc->slow_intr_task); taskqueue_drain(sc->tq, &sc->tick_task); callout_drain(&pi->link_check_ch); taskqueue_drain(sc->tq, &pi->link_check_task); PORT_LOCK(pi); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); /* disable pause frames */ t3_set_reg_field(sc, A_XGM_TX_CFG + pi->mac.offset, F_TXPAUSEEN, 0); /* Reset RX FIFO HWM */ t3_set_reg_field(sc, A_XGM_RXFIFO_CFG + pi->mac.offset, V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0); DELAY(100 * 1000); /* Wait for TXFIFO empty */ t3_wait_op_done(sc, A_XGM_TXFIFO_CFG + pi->mac.offset, F_TXFIFO_EMPTY, 1, 20, 5); DELAY(100 * 1000); t3_mac_disable(&pi->mac, MAC_DIRECTION_RX); pi->phy.ops->power_down(&pi->phy, 1); PORT_UNLOCK(pi); pi->link_config.link_ok = 0; t3_os_link_changed(sc, pi->port_id, 0, 0, 0, 0, 0); if ((sc->open_device_map & PORT_MASK) == 0) offload_close(&sc->tdev); if (sc->open_device_map == 0) cxgb_down(pi->adapter); return (0); } /* * Mark lro enabled or disabled in all qsets for this port */ static int cxgb_set_lro(struct port_info *p, int enabled) { int i; struct adapter *adp = p->adapter; struct sge_qset *q; for (i = 0; i < p->nqsets; i++) { q = &adp->sge.qs[p->first_qset + i]; q->lro.enabled = (enabled != 0); } return (0); } static int cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) { struct port_info *p = ifp->if_softc; struct adapter *sc = p->adapter; struct ifreq *ifr = (struct ifreq *)data; int flags, error = 0, mtu; uint32_t mask; switch (command) { case SIOCSIFMTU: ADAPTER_LOCK(sc); error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (error) { fail: ADAPTER_UNLOCK(sc); return (error); } mtu = ifr->ifr_mtu; if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) { error = EINVAL; } else { ifp->if_mtu = mtu; PORT_LOCK(p); cxgb_update_mac_settings(p); PORT_UNLOCK(p); } ADAPTER_UNLOCK(sc); break; case SIOCSIFFLAGS: ADAPTER_LOCK(sc); if (IS_DOOMED(p)) { error = ENXIO; goto fail; } if (ifp->if_flags & IFF_UP) { if (ifp->if_drv_flags & IFF_DRV_RUNNING) { flags = p->if_flags; if (((ifp->if_flags ^ flags) & IFF_PROMISC) || ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) { if (IS_BUSY(sc)) { error = EBUSY; goto fail; } PORT_LOCK(p); cxgb_update_mac_settings(p); PORT_UNLOCK(p); } ADAPTER_UNLOCK(sc); } else error = cxgb_init_locked(p); p->if_flags = ifp->if_flags; } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) error = cxgb_uninit_locked(p); else ADAPTER_UNLOCK(sc); ADAPTER_LOCK_ASSERT_NOTOWNED(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: ADAPTER_LOCK(sc); error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (error) goto fail; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { PORT_LOCK(p); cxgb_update_mac_settings(p); PORT_UNLOCK(p); } ADAPTER_UNLOCK(sc); break; case SIOCSIFCAP: ADAPTER_LOCK(sc); error = IS_DOOMED(p) ? ENXIO : (IS_BUSY(sc) ? EBUSY : 0); if (error) goto fail; mask = ifr->ifr_reqcap ^ ifp->if_capenable; if (mask & IFCAP_TXCSUM) { ifp->if_capenable ^= IFCAP_TXCSUM; ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); if (IFCAP_TSO & ifp->if_capenable && !(IFCAP_TXCSUM & ifp->if_capenable)) { ifp->if_capenable &= ~IFCAP_TSO; ifp->if_hwassist &= ~CSUM_TSO; if_printf(ifp, "tso disabled due to -txcsum.\n"); } } if (mask & IFCAP_RXCSUM) ifp->if_capenable ^= IFCAP_RXCSUM; if (mask & IFCAP_TSO4) { ifp->if_capenable ^= IFCAP_TSO4; if (IFCAP_TSO & ifp->if_capenable) { if (IFCAP_TXCSUM & ifp->if_capenable) ifp->if_hwassist |= CSUM_TSO; else { ifp->if_capenable &= ~IFCAP_TSO; ifp->if_hwassist &= ~CSUM_TSO; if_printf(ifp, "enable txcsum first.\n"); error = EAGAIN; } } else ifp->if_hwassist &= ~CSUM_TSO; } if (mask & IFCAP_LRO) { ifp->if_capenable ^= IFCAP_LRO; /* Safe to do this even if cxgb_up not called yet */ cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO); } if (mask & IFCAP_VLAN_HWTAGGING) { ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { PORT_LOCK(p); cxgb_update_mac_settings(p); PORT_UNLOCK(p); } } if (mask & IFCAP_VLAN_MTU) { ifp->if_capenable ^= IFCAP_VLAN_MTU; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { PORT_LOCK(p); cxgb_update_mac_settings(p); PORT_UNLOCK(p); } } if (mask & IFCAP_VLAN_HWTSO) ifp->if_capenable ^= IFCAP_VLAN_HWTSO; if (mask & IFCAP_VLAN_HWCSUM) ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; #ifdef VLAN_CAPABILITIES VLAN_CAPABILITIES(ifp); #endif ADAPTER_UNLOCK(sc); break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: error = ifmedia_ioctl(ifp, ifr, &p->media, command); break; default: error = ether_ioctl(ifp, command, data); } return (error); } static int cxgb_media_change(struct ifnet *ifp) { return (EOPNOTSUPP); } /* * Translates phy->modtype to the correct Ethernet media subtype. */ static int cxgb_ifm_type(int mod) { switch (mod) { case phy_modtype_sr: return (IFM_10G_SR); case phy_modtype_lr: return (IFM_10G_LR); case phy_modtype_lrm: return (IFM_10G_LRM); case phy_modtype_twinax: return (IFM_10G_TWINAX); case phy_modtype_twinax_long: return (IFM_10G_TWINAX_LONG); case phy_modtype_none: return (IFM_NONE); case phy_modtype_unknown: return (IFM_UNKNOWN); } KASSERT(0, ("%s: modtype %d unknown", __func__, mod)); return (IFM_UNKNOWN); } /* * Rebuilds the ifmedia list for this port, and sets the current media. */ static void cxgb_build_medialist(struct port_info *p) { struct cphy *phy = &p->phy; struct ifmedia *media = &p->media; int mod = phy->modtype; int m = IFM_ETHER | IFM_FDX; PORT_LOCK(p); ifmedia_removeall(media); if (phy->caps & SUPPORTED_TP && phy->caps & SUPPORTED_Autoneg) { /* Copper (RJ45) */ if (phy->caps & SUPPORTED_10000baseT_Full) ifmedia_add(media, m | IFM_10G_T, mod, NULL); if (phy->caps & SUPPORTED_1000baseT_Full) ifmedia_add(media, m | IFM_1000_T, mod, NULL); if (phy->caps & SUPPORTED_100baseT_Full) ifmedia_add(media, m | IFM_100_TX, mod, NULL); if (phy->caps & SUPPORTED_10baseT_Full) ifmedia_add(media, m | IFM_10_T, mod, NULL); ifmedia_add(media, IFM_ETHER | IFM_AUTO, mod, NULL); ifmedia_set(media, IFM_ETHER | IFM_AUTO); } else if (phy->caps & SUPPORTED_TP) { /* Copper (CX4) */ KASSERT(phy->caps & SUPPORTED_10000baseT_Full, ("%s: unexpected cap 0x%x", __func__, phy->caps)); ifmedia_add(media, m | IFM_10G_CX4, mod, NULL); ifmedia_set(media, m | IFM_10G_CX4); } else if (phy->caps & SUPPORTED_FIBRE && phy->caps & SUPPORTED_10000baseT_Full) { /* 10G optical (but includes SFP+ twinax) */ m |= cxgb_ifm_type(mod); if (IFM_SUBTYPE(m) == IFM_NONE) m &= ~IFM_FDX; ifmedia_add(media, m, mod, NULL); ifmedia_set(media, m); } else if (phy->caps & SUPPORTED_FIBRE && phy->caps & SUPPORTED_1000baseT_Full) { /* 1G optical */ /* XXX: Lie and claim to be SX, could actually be any 1G-X */ ifmedia_add(media, m | IFM_1000_SX, mod, NULL); ifmedia_set(media, m | IFM_1000_SX); } else { KASSERT(0, ("%s: don't know how to handle 0x%x.", __func__, phy->caps)); } PORT_UNLOCK(p); } static void cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct port_info *p = ifp->if_softc; struct ifmedia_entry *cur = p->media.ifm_cur; int speed = p->link_config.speed; if (cur->ifm_data != p->phy.modtype) { cxgb_build_medialist(p); cur = p->media.ifm_cur; } ifmr->ifm_status = IFM_AVALID; if (!p->link_config.link_ok) return; ifmr->ifm_status |= IFM_ACTIVE; /* * active and current will differ iff current media is autoselect. That * can happen only for copper RJ45. */ if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) return; KASSERT(p->phy.caps & SUPPORTED_TP && p->phy.caps & SUPPORTED_Autoneg, ("%s: unexpected PHY caps 0x%x", __func__, p->phy.caps)); ifmr->ifm_active = IFM_ETHER | IFM_FDX; if (speed == SPEED_10000) ifmr->ifm_active |= IFM_10G_T; else if (speed == SPEED_1000) ifmr->ifm_active |= IFM_1000_T; else if (speed == SPEED_100) ifmr->ifm_active |= IFM_100_TX; else if (speed == SPEED_10) ifmr->ifm_active |= IFM_10_T; else KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, speed)); } static void cxgb_async_intr(void *data) { adapter_t *sc = data; t3_write_reg(sc, A_PL_INT_ENABLE0, 0); (void) t3_read_reg(sc, A_PL_INT_ENABLE0); taskqueue_enqueue(sc->tq, &sc->slow_intr_task); } static void link_check_callout(void *arg) { struct port_info *pi = arg; struct adapter *sc = pi->adapter; if (!isset(&sc->open_device_map, pi->port_id)) return; taskqueue_enqueue(sc->tq, &pi->link_check_task); } static void check_link_status(void *arg, int pending) { struct port_info *pi = arg; struct adapter *sc = pi->adapter; if (!isset(&sc->open_device_map, pi->port_id)) return; t3_link_changed(sc, pi->port_id); if (pi->link_fault || !(pi->phy.caps & SUPPORTED_LINK_IRQ)) callout_reset(&pi->link_check_ch, hz, link_check_callout, pi); } void t3_os_link_intr(struct port_info *pi) { /* * Schedule a link check in the near future. If the link is flapping * rapidly we'll keep resetting the callout and delaying the check until * things stabilize a bit. */ callout_reset(&pi->link_check_ch, hz / 4, link_check_callout, pi); } static void check_t3b2_mac(struct adapter *sc) { int i; if (sc->flags & CXGB_SHUTDOWN) return; for_each_port(sc, i) { struct port_info *p = &sc->port[i]; int status; #ifdef INVARIANTS struct ifnet *ifp = p->ifp; #endif if (!isset(&sc->open_device_map, p->port_id) || p->link_fault || !p->link_config.link_ok) continue; KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("%s: state mismatch (drv_flags %x, device_map %x)", __func__, ifp->if_drv_flags, sc->open_device_map)); PORT_LOCK(p); status = t3b2_mac_watchdog_task(&p->mac); if (status == 1) p->mac.stats.num_toggled++; else if (status == 2) { struct cmac *mac = &p->mac; cxgb_update_mac_settings(p); t3_link_start(&p->phy, mac, &p->link_config); t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX); t3_port_intr_enable(sc, p->port_id); p->mac.stats.num_resets++; } PORT_UNLOCK(p); } } static void cxgb_tick(void *arg) { adapter_t *sc = (adapter_t *)arg; if (sc->flags & CXGB_SHUTDOWN) return; taskqueue_enqueue(sc->tq, &sc->tick_task); callout_reset(&sc->cxgb_tick_ch, hz, cxgb_tick, sc); } static void cxgb_tick_handler(void *arg, int count) { adapter_t *sc = (adapter_t *)arg; const struct adapter_params *p = &sc->params; int i; uint32_t cause, reset; if (sc->flags & CXGB_SHUTDOWN || !(sc->flags & FULL_INIT_DONE)) return; if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map) check_t3b2_mac(sc); cause = t3_read_reg(sc, A_SG_INT_CAUSE) & (F_RSPQSTARVE | F_FLEMPTY); if (cause) { struct sge_qset *qs = &sc->sge.qs[0]; uint32_t mask, v; v = t3_read_reg(sc, A_SG_RSPQ_FL_STATUS) & ~0xff00; mask = 1; for (i = 0; i < SGE_QSETS; i++) { if (v & mask) qs[i].rspq.starved++; mask <<= 1; } mask <<= SGE_QSETS; /* skip RSPQXDISABLED */ for (i = 0; i < SGE_QSETS * 2; i++) { if (v & mask) { qs[i / 2].fl[i % 2].empty++; } mask <<= 1; } /* clear */ t3_write_reg(sc, A_SG_RSPQ_FL_STATUS, v); t3_write_reg(sc, A_SG_INT_CAUSE, cause); } for (i = 0; i < sc->params.nports; i++) { struct port_info *pi = &sc->port[i]; struct ifnet *ifp = pi->ifp; struct cmac *mac = &pi->mac; struct mac_stats *mstats = &mac->stats; if (!isset(&sc->open_device_map, pi->port_id)) continue; PORT_LOCK(pi); t3_mac_update_stats(mac); PORT_UNLOCK(pi); ifp->if_opackets = mstats->tx_frames_64 + mstats->tx_frames_65_127 + mstats->tx_frames_128_255 + mstats->tx_frames_256_511 + mstats->tx_frames_512_1023 + mstats->tx_frames_1024_1518 + mstats->tx_frames_1519_max; ifp->if_ipackets = mstats->rx_frames_64 + mstats->rx_frames_65_127 + mstats->rx_frames_128_255 + mstats->rx_frames_256_511 + mstats->rx_frames_512_1023 + mstats->rx_frames_1024_1518 + mstats->rx_frames_1519_max; ifp->if_obytes = mstats->tx_octets; ifp->if_ibytes = mstats->rx_octets; ifp->if_omcasts = mstats->tx_mcast_frames; ifp->if_imcasts = mstats->rx_mcast_frames; ifp->if_collisions = mstats->tx_total_collisions; ifp->if_iqdrops = mstats->rx_cong_drops; ifp->if_oerrors = mstats->tx_excess_collisions + mstats->tx_underrun + mstats->tx_len_errs + mstats->tx_mac_internal_errs + mstats->tx_excess_deferral + mstats->tx_fcs_errs; ifp->if_ierrors = mstats->rx_jabber + mstats->rx_data_errs + mstats->rx_sequence_errs + mstats->rx_runt + mstats->rx_too_long + mstats->rx_mac_internal_errs + mstats->rx_short + mstats->rx_fcs_errs; if (mac->multiport) continue; /* Count rx fifo overflows, once per second */ cause = t3_read_reg(sc, A_XGM_INT_CAUSE + mac->offset); reset = 0; if (cause & F_RXFIFO_OVERFLOW) { mac->stats.rx_fifo_ovfl++; reset |= F_RXFIFO_OVERFLOW; } t3_write_reg(sc, A_XGM_INT_CAUSE + mac->offset, reset); } } static void touch_bars(device_t dev) { /* * Don't enable yet */ #if !defined(__LP64__) && 0 u32 v; pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v); pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v); pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v); #endif } static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset) { uint8_t *buf; int err = 0; u32 aligned_offset, aligned_len, *p; struct adapter *adapter = pi->adapter; aligned_offset = offset & ~3; aligned_len = (len + (offset & 3) + 3) & ~3; if (aligned_offset != offset || aligned_len != len) { buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO); if (!buf) return (ENOMEM); err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf); if (!err && aligned_len > 4) err = t3_seeprom_read(adapter, aligned_offset + aligned_len - 4, (u32 *)&buf[aligned_len - 4]); if (err) goto out; memcpy(buf + (offset & 3), data, len); } else buf = (uint8_t *)(uintptr_t)data; err = t3_seeprom_wp(adapter, 0); if (err) goto out; for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { err = t3_seeprom_write(adapter, aligned_offset, *p); aligned_offset += 4; } if (!err) err = t3_seeprom_wp(adapter, 1); out: if (buf != data) free(buf, M_DEVBUF); return err; } static int in_range(int val, int lo, int hi) { return val < 0 || (val <= hi && val >= lo); } static int cxgb_extension_open(struct cdev *dev, int flags, int fmp, struct thread *td) { return (0); } static int cxgb_extension_close(struct cdev *dev, int flags, int fmt, struct thread *td) { return (0); } static int cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, struct thread *td) { int mmd, error = 0; struct port_info *pi = dev->si_drv1; adapter_t *sc = pi->adapter; #ifdef PRIV_SUPPORTED if (priv_check(td, PRIV_DRIVER)) { if (cxgb_debug) printf("user does not have access to privileged ioctls\n"); return (EPERM); } #else if (suser(td)) { if (cxgb_debug) printf("user does not have access to privileged ioctls\n"); return (EPERM); } #endif switch (cmd) { case CHELSIO_GET_MIIREG: { uint32_t val; struct cphy *phy = &pi->phy; struct ch_mii_data *mid = (struct ch_mii_data *)data; if (!phy->mdio_read) return (EOPNOTSUPP); if (is_10G(sc)) { mmd = mid->phy_id >> 8; if (!mmd) mmd = MDIO_DEV_PCS; else if (mmd > MDIO_DEV_VEND2) return (EINVAL); error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd, mid->reg_num, &val); } else error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0, mid->reg_num & 0x1f, &val); if (error == 0) mid->val_out = val; break; } case CHELSIO_SET_MIIREG: { struct cphy *phy = &pi->phy; struct ch_mii_data *mid = (struct ch_mii_data *)data; if (!phy->mdio_write) return (EOPNOTSUPP); if (is_10G(sc)) { mmd = mid->phy_id >> 8; if (!mmd) mmd = MDIO_DEV_PCS; else if (mmd > MDIO_DEV_VEND2) return (EINVAL); error = phy->mdio_write(sc, mid->phy_id & 0x1f, mmd, mid->reg_num, mid->val_in); } else error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0, mid->reg_num & 0x1f, mid->val_in); break; } case CHELSIO_SETREG: { struct ch_reg *edata = (struct ch_reg *)data; if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) return (EFAULT); t3_write_reg(sc, edata->addr, edata->val); break; } case CHELSIO_GETREG: { struct ch_reg *edata = (struct ch_reg *)data; if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) return (EFAULT); edata->val = t3_read_reg(sc, edata->addr); break; } case CHELSIO_GET_SGE_CONTEXT: { struct ch_cntxt *ecntxt = (struct ch_cntxt *)data; mtx_lock_spin(&sc->sge.reg_lock); switch (ecntxt->cntxt_type) { case CNTXT_TYPE_EGRESS: error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id, ecntxt->data); break; case CNTXT_TYPE_FL: error = -t3_sge_read_fl(sc, ecntxt->cntxt_id, ecntxt->data); break; case CNTXT_TYPE_RSP: error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id, ecntxt->data); break; case CNTXT_TYPE_CQ: error = -t3_sge_read_cq(sc, ecntxt->cntxt_id, ecntxt->data); break; default: error = EINVAL; break; } mtx_unlock_spin(&sc->sge.reg_lock); break; } case CHELSIO_GET_SGE_DESC: { struct ch_desc *edesc = (struct ch_desc *)data; int ret; if (edesc->queue_num >= SGE_QSETS * 6) return (EINVAL); ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6], edesc->queue_num % 6, edesc->idx, edesc->data); if (ret < 0) return (EINVAL); edesc->size = ret; break; } case CHELSIO_GET_QSET_PARAMS: { struct qset_params *q; struct ch_qset_params *t = (struct ch_qset_params *)data; int q1 = pi->first_qset; int nqsets = pi->nqsets; int i; if (t->qset_idx >= nqsets) return EINVAL; i = q1 + t->qset_idx; q = &sc->params.sge.qset[i]; t->rspq_size = q->rspq_size; t->txq_size[0] = q->txq_size[0]; t->txq_size[1] = q->txq_size[1]; t->txq_size[2] = q->txq_size[2]; t->fl_size[0] = q->fl_size; t->fl_size[1] = q->jumbo_size; t->polling = q->polling; t->lro = q->lro; t->intr_lat = q->coalesce_usecs; t->cong_thres = q->cong_thres; t->qnum = i; if ((sc->flags & FULL_INIT_DONE) == 0) t->vector = 0; else if (sc->flags & USING_MSIX) t->vector = rman_get_start(sc->msix_irq_res[i]); else t->vector = rman_get_start(sc->irq_res); break; } case CHELSIO_GET_QSET_NUM: { struct ch_reg *edata = (struct ch_reg *)data; edata->val = pi->nqsets; break; } case CHELSIO_LOAD_FW: { uint8_t *fw_data; uint32_t vers; struct ch_mem_range *t = (struct ch_mem_range *)data; /* * You're allowed to load a firmware only before FULL_INIT_DONE * * FW_UPTODATE is also set so the rest of the initialization * will not overwrite what was loaded here. This gives you the * flexibility to load any firmware (and maybe shoot yourself in * the foot). */ ADAPTER_LOCK(sc); if (sc->open_device_map || sc->flags & FULL_INIT_DONE) { ADAPTER_UNLOCK(sc); return (EBUSY); } fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT); if (!fw_data) error = ENOMEM; else error = copyin(t->buf, fw_data, t->len); if (!error) error = -t3_load_fw(sc, fw_data, t->len); if (t3_get_fw_version(sc, &vers) == 0) { snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d", G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers)); } if (!error) sc->flags |= FW_UPTODATE; free(fw_data, M_DEVBUF); ADAPTER_UNLOCK(sc); break; } case CHELSIO_LOAD_BOOT: { uint8_t *boot_data; struct ch_mem_range *t = (struct ch_mem_range *)data; boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT); if (!boot_data) return ENOMEM; error = copyin(t->buf, boot_data, t->len); if (!error) error = -t3_load_boot(sc, boot_data, t->len); free(boot_data, M_DEVBUF); break; } case CHELSIO_GET_PM: { struct ch_pm *m = (struct ch_pm *)data; struct tp_params *p = &sc->params.tp; if (!is_offload(sc)) return (EOPNOTSUPP); m->tx_pg_sz = p->tx_pg_size; m->tx_num_pg = p->tx_num_pgs; m->rx_pg_sz = p->rx_pg_size; m->rx_num_pg = p->rx_num_pgs; m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan; break; } case CHELSIO_SET_PM: { struct ch_pm *m = (struct ch_pm *)data; struct tp_params *p = &sc->params.tp; if (!is_offload(sc)) return (EOPNOTSUPP); if (sc->flags & FULL_INIT_DONE) return (EBUSY); if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) || !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1))) return (EINVAL); /* not power of 2 */ if (!(m->rx_pg_sz & 0x14000)) return (EINVAL); /* not 16KB or 64KB */ if (!(m->tx_pg_sz & 0x1554000)) return (EINVAL); if (m->tx_num_pg == -1) m->tx_num_pg = p->tx_num_pgs; if (m->rx_num_pg == -1) m->rx_num_pg = p->rx_num_pgs; if (m->tx_num_pg % 24 || m->rx_num_pg % 24) return (EINVAL); if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size || m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size) return (EINVAL); p->rx_pg_size = m->rx_pg_sz; p->tx_pg_size = m->tx_pg_sz; p->rx_num_pgs = m->rx_num_pg; p->tx_num_pgs = m->tx_num_pg; break; } case CHELSIO_SETMTUTAB: { struct ch_mtus *m = (struct ch_mtus *)data; int i; if (!is_offload(sc)) return (EOPNOTSUPP); if (offload_running(sc)) return (EBUSY); if (m->nmtus != NMTUS) return (EINVAL); if (m->mtus[0] < 81) /* accommodate SACK */ return (EINVAL); /* * MTUs must be in ascending order */ for (i = 1; i < NMTUS; ++i) if (m->mtus[i] < m->mtus[i - 1]) return (EINVAL); memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus)); break; } case CHELSIO_GETMTUTAB: { struct ch_mtus *m = (struct ch_mtus *)data; if (!is_offload(sc)) return (EOPNOTSUPP); memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus)); m->nmtus = NMTUS; break; } case CHELSIO_GET_MEM: { struct ch_mem_range *t = (struct ch_mem_range *)data; struct mc7 *mem; uint8_t *useraddr; u64 buf[32]; /* * Use these to avoid modifying len/addr in the return * struct */ uint32_t len = t->len, addr = t->addr; if (!is_offload(sc)) return (EOPNOTSUPP); if (!(sc->flags & FULL_INIT_DONE)) return (EIO); /* need the memory controllers */ if ((addr & 0x7) || (len & 0x7)) return (EINVAL); if (t->mem_id == MEM_CM) mem = &sc->cm; else if (t->mem_id == MEM_PMRX) mem = &sc->pmrx; else if (t->mem_id == MEM_PMTX) mem = &sc->pmtx; else return (EINVAL); /* * Version scheme: * bits 0..9: chip version * bits 10..15: chip revision */ t->version = 3 | (sc->params.rev << 10); /* * Read 256 bytes at a time as len can be large and we don't * want to use huge intermediate buffers. */ useraddr = (uint8_t *)t->buf; while (len) { unsigned int chunk = min(len, sizeof(buf)); error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf); if (error) return (-error); if (copyout(buf, useraddr, chunk)) return (EFAULT); useraddr += chunk; addr += chunk; len -= chunk; } break; } case CHELSIO_READ_TCAM_WORD: { struct ch_tcam_word *t = (struct ch_tcam_word *)data; if (!is_offload(sc)) return (EOPNOTSUPP); if (!(sc->flags & FULL_INIT_DONE)) return (EIO); /* need MC5 */ return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf); break; } case CHELSIO_SET_TRACE_FILTER: { struct ch_trace *t = (struct ch_trace *)data; const struct trace_params *tp; tp = (const struct trace_params *)&t->sip; if (t->config_tx) t3_config_trace_filter(sc, tp, 0, t->invert_match, t->trace_tx); if (t->config_rx) t3_config_trace_filter(sc, tp, 1, t->invert_match, t->trace_rx); break; } case CHELSIO_SET_PKTSCHED: { struct ch_pktsched_params *p = (struct ch_pktsched_params *)data; if (sc->open_device_map == 0) return (EAGAIN); send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max, p->binding); break; } case CHELSIO_IFCONF_GETREGS: { struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data; int reglen = cxgb_get_regs_len(); uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT); if (buf == NULL) { return (ENOMEM); } if (regs->len > reglen) regs->len = reglen; else if (regs->len < reglen) error = ENOBUFS; if (!error) { cxgb_get_regs(sc, regs, buf); error = copyout(buf, regs->data, reglen); } free(buf, M_DEVBUF); break; } case CHELSIO_SET_HW_SCHED: { struct ch_hw_sched *t = (struct ch_hw_sched *)data; unsigned int ticks_per_usec = core_ticks_per_usec(sc); if ((sc->flags & FULL_INIT_DONE) == 0) return (EAGAIN); /* need TP to be initialized */ if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) || !in_range(t->channel, 0, 1) || !in_range(t->kbps, 0, 10000000) || !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) || !in_range(t->flow_ipg, 0, dack_ticks_to_usec(sc, 0x7ff))) return (EINVAL); if (t->kbps >= 0) { error = t3_config_sched(sc, t->kbps, t->sched); if (error < 0) return (-error); } if (t->class_ipg >= 0) t3_set_sched_ipg(sc, t->sched, t->class_ipg); if (t->flow_ipg >= 0) { t->flow_ipg *= 1000; /* us -> ns */ t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1); } if (t->mode >= 0) { int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched); t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, bit, t->mode ? bit : 0); } if (t->channel >= 0) t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP, 1 << t->sched, t->channel << t->sched); break; } case CHELSIO_GET_EEPROM: { int i; struct ch_eeprom *e = (struct ch_eeprom *)data; uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT); if (buf == NULL) { return (ENOMEM); } e->magic = EEPROM_MAGIC; for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4) error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]); if (!error) error = copyout(buf + e->offset, e->data, e->len); free(buf, M_DEVBUF); break; } case CHELSIO_CLEAR_STATS: { if (!(sc->flags & FULL_INIT_DONE)) return EAGAIN; PORT_LOCK(pi); t3_mac_update_stats(&pi->mac); memset(&pi->mac.stats, 0, sizeof(pi->mac.stats)); PORT_UNLOCK(pi); break; } case CHELSIO_GET_UP_LA: { struct ch_up_la *la = (struct ch_up_la *)data; uint8_t *buf = malloc(LA_BUFSIZE, M_DEVBUF, M_NOWAIT); if (buf == NULL) { return (ENOMEM); } if (la->bufsize < LA_BUFSIZE) error = ENOBUFS; if (!error) error = -t3_get_up_la(sc, &la->stopped, &la->idx, &la->bufsize, buf); if (!error) error = copyout(buf, la->data, la->bufsize); free(buf, M_DEVBUF); break; } case CHELSIO_GET_UP_IOQS: { struct ch_up_ioqs *ioqs = (struct ch_up_ioqs *)data; uint8_t *buf = malloc(IOQS_BUFSIZE, M_DEVBUF, M_NOWAIT); uint32_t *v; if (buf == NULL) { return (ENOMEM); } if (ioqs->bufsize < IOQS_BUFSIZE) error = ENOBUFS; if (!error) error = -t3_get_up_ioqs(sc, &ioqs->bufsize, buf); if (!error) { v = (uint32_t *)buf; ioqs->ioq_rx_enable = *v++; ioqs->ioq_tx_enable = *v++; ioqs->ioq_rx_status = *v++; ioqs->ioq_tx_status = *v++; error = copyout(v, ioqs->data, ioqs->bufsize); } free(buf, M_DEVBUF); break; } case CHELSIO_SET_FILTER: { struct ch_filter *f = (struct ch_filter *)data;; struct filter_info *p; unsigned int nfilters = sc->params.mc5.nfilters; if (!is_offload(sc)) return (EOPNOTSUPP); /* No TCAM */ if (!(sc->flags & FULL_INIT_DONE)) return (EAGAIN); /* mc5 not setup yet */ if (nfilters == 0) return (EBUSY); /* TOE will use TCAM */ /* sanity checks */ if (f->filter_id >= nfilters || (f->val.dip && f->mask.dip != 0xffffffff) || (f->val.sport && f->mask.sport != 0xffff) || (f->val.dport && f->mask.dport != 0xffff) || (f->val.vlan && f->mask.vlan != 0xfff) || (f->val.vlan_prio && f->mask.vlan_prio != FILTER_NO_VLAN_PRI) || (f->mac_addr_idx != 0xffff && f->mac_addr_idx > 15) || f->qset >= SGE_QSETS || sc->rrss_map[f->qset] >= RSS_TABLE_SIZE) return (EINVAL); /* Was allocated with M_WAITOK */ KASSERT(sc->filters, ("filter table NULL\n")); p = &sc->filters[f->filter_id]; if (p->locked) return (EPERM); bzero(p, sizeof(*p)); p->sip = f->val.sip; p->sip_mask = f->mask.sip; p->dip = f->val.dip; p->sport = f->val.sport; p->dport = f->val.dport; p->vlan = f->mask.vlan ? f->val.vlan : 0xfff; p->vlan_prio = f->mask.vlan_prio ? (f->val.vlan_prio & 6) : FILTER_NO_VLAN_PRI; p->mac_hit = f->mac_hit; p->mac_vld = f->mac_addr_idx != 0xffff; p->mac_idx = f->mac_addr_idx; p->pkt_type = f->proto; p->report_filter_id = f->want_filter_id; p->pass = f->pass; p->rss = f->rss; p->qset = f->qset; error = set_filter(sc, f->filter_id, p); if (error == 0) p->valid = 1; break; } case CHELSIO_DEL_FILTER: { struct ch_filter *f = (struct ch_filter *)data; struct filter_info *p; unsigned int nfilters = sc->params.mc5.nfilters; if (!is_offload(sc)) return (EOPNOTSUPP); if (!(sc->flags & FULL_INIT_DONE)) return (EAGAIN); if (nfilters == 0 || sc->filters == NULL) return (EINVAL); if (f->filter_id >= nfilters) return (EINVAL); p = &sc->filters[f->filter_id]; if (p->locked) return (EPERM); if (!p->valid) return (EFAULT); /* Read "Bad address" as "Bad index" */ bzero(p, sizeof(*p)); p->sip = p->sip_mask = 0xffffffff; p->vlan = 0xfff; p->vlan_prio = FILTER_NO_VLAN_PRI; p->pkt_type = 1; error = set_filter(sc, f->filter_id, p); break; } case CHELSIO_GET_FILTER: { struct ch_filter *f = (struct ch_filter *)data; struct filter_info *p; unsigned int i, nfilters = sc->params.mc5.nfilters; if (!is_offload(sc)) return (EOPNOTSUPP); if (!(sc->flags & FULL_INIT_DONE)) return (EAGAIN); if (nfilters == 0 || sc->filters == NULL) return (EINVAL); i = f->filter_id == 0xffffffff ? 0 : f->filter_id + 1; for (; i < nfilters; i++) { p = &sc->filters[i]; if (!p->valid) continue; bzero(f, sizeof(*f)); f->filter_id = i; f->val.sip = p->sip; f->mask.sip = p->sip_mask; f->val.dip = p->dip; f->mask.dip = p->dip ? 0xffffffff : 0; f->val.sport = p->sport; f->mask.sport = p->sport ? 0xffff : 0; f->val.dport = p->dport; f->mask.dport = p->dport ? 0xffff : 0; f->val.vlan = p->vlan == 0xfff ? 0 : p->vlan; f->mask.vlan = p->vlan == 0xfff ? 0 : 0xfff; f->val.vlan_prio = p->vlan_prio == FILTER_NO_VLAN_PRI ? 0 : p->vlan_prio; f->mask.vlan_prio = p->vlan_prio == FILTER_NO_VLAN_PRI ? 0 : FILTER_NO_VLAN_PRI; f->mac_hit = p->mac_hit; f->mac_addr_idx = p->mac_vld ? p->mac_idx : 0xffff; f->proto = p->pkt_type; f->want_filter_id = p->report_filter_id; f->pass = p->pass; f->rss = p->rss; f->qset = p->qset; break; } if (i == nfilters) f->filter_id = 0xffffffff; break; } default: return (EOPNOTSUPP); break; } return (error); } static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start, unsigned int end) { uint32_t *p = (uint32_t *)(buf + start); for ( ; start <= end; start += sizeof(uint32_t)) *p++ = t3_read_reg(ap, start); } #define T3_REGMAP_SIZE (3 * 1024) static int cxgb_get_regs_len(void) { return T3_REGMAP_SIZE; } static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf) { /* * Version scheme: * bits 0..9: chip version * bits 10..15: chip revision * bit 31: set for PCIe cards */ regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31); /* * We skip the MAC statistics registers because they are clear-on-read. * Also reading multi-register stats would need to synchronize with the * periodic mac stats accumulation. Hard to justify the complexity. */ memset(buf, 0, cxgb_get_regs_len()); reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN); reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT); reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE); reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA); reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3); reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0, XGM_REG(A_XGM_SERDES_STAT3, 1)); reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1), XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1)); } static int alloc_filters(struct adapter *sc) { struct filter_info *p; unsigned int nfilters = sc->params.mc5.nfilters; if (nfilters == 0) return (0); p = malloc(sizeof(*p) * nfilters, M_DEVBUF, M_WAITOK | M_ZERO); sc->filters = p; p = &sc->filters[nfilters - 1]; p->vlan = 0xfff; p->vlan_prio = FILTER_NO_VLAN_PRI; p->pass = p->rss = p->valid = p->locked = 1; return (0); } static int setup_hw_filters(struct adapter *sc) { int i, rc; unsigned int nfilters = sc->params.mc5.nfilters; if (!sc->filters) return (0); t3_enable_filters(sc); for (i = rc = 0; i < nfilters && !rc; i++) { if (sc->filters[i].locked) rc = set_filter(sc, i, &sc->filters[i]); } return (rc); } static int set_filter(struct adapter *sc, int id, const struct filter_info *f) { int len; struct mbuf *m; struct ulp_txpkt *txpkt; struct work_request_hdr *wr; struct cpl_pass_open_req *oreq; struct cpl_set_tcb_field *sreq; len = sizeof(*wr) + sizeof(*oreq) + 2 * sizeof(*sreq); KASSERT(len <= MHLEN, ("filter request too big for an mbuf")); id += t3_mc5_size(&sc->mc5) - sc->params.mc5.nroutes - sc->params.mc5.nfilters; m = m_gethdr(M_WAITOK, MT_DATA); m->m_len = m->m_pkthdr.len = len; bzero(mtod(m, char *), len); wr = mtod(m, struct work_request_hdr *); wr->wr_hi = htonl(V_WR_OP(FW_WROPCODE_BYPASS) | F_WR_ATOMIC); oreq = (struct cpl_pass_open_req *)(wr + 1); txpkt = (struct ulp_txpkt *)oreq; txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT)); txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*oreq) / 8)); OPCODE_TID(oreq) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, id)); oreq->local_port = htons(f->dport); oreq->peer_port = htons(f->sport); oreq->local_ip = htonl(f->dip); oreq->peer_ip = htonl(f->sip); oreq->peer_netmask = htonl(f->sip_mask); oreq->opt0h = 0; oreq->opt0l = htonl(F_NO_OFFLOAD); oreq->opt1 = htonl(V_MAC_MATCH_VALID(f->mac_vld) | V_CONN_POLICY(CPL_CONN_POLICY_FILTER) | V_VLAN_PRI(f->vlan_prio >> 1) | V_VLAN_PRI_VALID(f->vlan_prio != FILTER_NO_VLAN_PRI) | V_PKT_TYPE(f->pkt_type) | V_OPT1_VLAN(f->vlan) | V_MAC_MATCH(f->mac_idx | (f->mac_hit << 4))); sreq = (struct cpl_set_tcb_field *)(oreq + 1); set_tcb_field_ulp(sreq, id, 1, 0x1800808000ULL, (f->report_filter_id << 15) | (1 << 23) | ((u64)f->pass << 35) | ((u64)!f->rss << 36)); set_tcb_field_ulp(sreq + 1, id, 0, 0xffffffff, (2 << 19) | 1); t3_mgmt_tx(sc, m); if (f->pass && !f->rss) { len = sizeof(*sreq); m = m_gethdr(M_WAITOK, MT_DATA); m->m_len = m->m_pkthdr.len = len; bzero(mtod(m, char *), len); sreq = mtod(m, struct cpl_set_tcb_field *); sreq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD)); mk_set_tcb_field(sreq, id, 25, 0x3f80000, (u64)sc->rrss_map[f->qset] << 19); t3_mgmt_tx(sc, m); } return 0; } static inline void mk_set_tcb_field(struct cpl_set_tcb_field *req, unsigned int tid, unsigned int word, u64 mask, u64 val) { OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid)); req->reply = V_NO_REPLY(1); req->cpu_idx = 0; req->word = htons(word); req->mask = htobe64(mask); req->val = htobe64(val); } static inline void set_tcb_field_ulp(struct cpl_set_tcb_field *req, unsigned int tid, unsigned int word, u64 mask, u64 val) { struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req; txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT)); txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*req) / 8)); mk_set_tcb_field(req, tid, word, mask, val); } Index: stable/7/sys/dev/cxgb/cxgb_sge.c =================================================================== --- stable/7/sys/dev/cxgb/cxgb_sge.c (revision 220340) +++ stable/7/sys/dev/cxgb/cxgb_sge.c (revision 220341) @@ -1,3704 +1,3698 @@ /************************************************************************** Copyright (c) 2007-2009, Chelsio Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Neither the name of the Chelsio Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ***************************************************************************/ #define DEBUG_BUFRING #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef CONFIG_DEFINED #include #include #else #include #include #endif int txq_fills = 0; /* * XXX don't re-enable this until TOE stops assuming * we have an m_ext */ static int recycle_enable = 0; extern int cxgb_txq_buf_ring_size; int cxgb_cached_allocations; int cxgb_cached; int cxgb_ext_freed = 0; int cxgb_ext_inited = 0; int fl_q_size = 0; int jumbo_q_size = 0; extern int cxgb_use_16k_clusters; extern int cxgb_pcpu_cache_enable; extern int nmbjumbop; extern int nmbjumbo9; extern int nmbjumbo16; #define USE_GTS 0 #define SGE_RX_SM_BUF_SIZE 1536 #define SGE_RX_DROP_THRES 16 #define SGE_RX_COPY_THRES 128 /* * Period of the Tx buffer reclaim timer. This timer does not need to run * frequently as Tx buffers are usually reclaimed by new Tx packets. */ #define TX_RECLAIM_PERIOD (hz >> 1) /* * Values for sge_txq.flags */ enum { TXQ_RUNNING = 1 << 0, /* fetch engine is running */ TXQ_LAST_PKT_DB = 1 << 1, /* last packet rang the doorbell */ }; struct tx_desc { uint64_t flit[TX_DESC_FLITS]; } __packed; struct rx_desc { uint32_t addr_lo; uint32_t len_gen; uint32_t gen2; uint32_t addr_hi; } __packed;; struct rsp_desc { /* response queue descriptor */ struct rss_header rss_hdr; uint32_t flags; uint32_t len_cq; uint8_t imm_data[47]; uint8_t intr_gen; } __packed; #define RX_SW_DESC_MAP_CREATED (1 << 0) #define TX_SW_DESC_MAP_CREATED (1 << 1) #define RX_SW_DESC_INUSE (1 << 3) #define TX_SW_DESC_MAPPED (1 << 4) #define RSPQ_NSOP_NEOP G_RSPD_SOP_EOP(0) #define RSPQ_EOP G_RSPD_SOP_EOP(F_RSPD_EOP) #define RSPQ_SOP G_RSPD_SOP_EOP(F_RSPD_SOP) #define RSPQ_SOP_EOP G_RSPD_SOP_EOP(F_RSPD_SOP|F_RSPD_EOP) struct tx_sw_desc { /* SW state per Tx descriptor */ struct mbuf_iovec mi; bus_dmamap_t map; int flags; }; struct rx_sw_desc { /* SW state per Rx descriptor */ caddr_t rxsd_cl; caddr_t data; bus_dmamap_t map; int flags; }; struct txq_state { unsigned int compl; unsigned int gen; unsigned int pidx; }; struct refill_fl_cb_arg { int error; bus_dma_segment_t seg; int nseg; }; /* * Maps a number of flits to the number of Tx descriptors that can hold them. * The formula is * * desc = 1 + (flits - 2) / (WR_FLITS - 1). * * HW allows up to 4 descriptors to be combined into a WR. */ static uint8_t flit_desc_map[] = { 0, #if SGE_NUM_GENBITS == 1 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 #elif SGE_NUM_GENBITS == 2 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, #else # error "SGE_NUM_GENBITS must be 1 or 2" #endif }; int cxgb_debug = 0; static void sge_timer_cb(void *arg); static void sge_timer_reclaim(void *arg, int ncount); static void sge_txq_reclaim_handler(void *arg, int ncount); /** * reclaim_completed_tx - reclaims completed Tx descriptors * @adapter: the adapter * @q: the Tx queue to reclaim completed descriptors from * * Reclaims Tx descriptors that the SGE has indicated it has processed, * and frees the associated buffers if possible. Called with the Tx * queue's lock held. */ static __inline int reclaim_completed_tx_(struct sge_txq *q, int reclaim_min) { int reclaim = desc_reclaimable(q); if (reclaim < reclaim_min) return (0); mtx_assert(&q->lock, MA_OWNED); if (reclaim > 0) { t3_free_tx_desc(q, reclaim); q->cleaned += reclaim; q->in_use -= reclaim; } return (reclaim); } /** * should_restart_tx - are there enough resources to restart a Tx queue? * @q: the Tx queue * * Checks if there are enough descriptors to restart a suspended Tx queue. */ static __inline int should_restart_tx(const struct sge_txq *q) { unsigned int r = q->processed - q->cleaned; return q->in_use - r < (q->size >> 1); } /** * t3_sge_init - initialize SGE * @adap: the adapter * @p: the SGE parameters * * Performs SGE initialization needed every time after a chip reset. * We do not initialize any of the queue sets here, instead the driver * top-level must request those individually. We also do not enable DMA * here, that should be done after the queues have been set up. */ void t3_sge_init(adapter_t *adap, struct sge_params *p) { u_int ctrl, ups; ups = 0; /* = ffs(pci_resource_len(adap->pdev, 2) >> 12); */ ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL | F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN | V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS | V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING; #if SGE_NUM_GENBITS == 1 ctrl |= F_EGRGENCTRL; #endif if (adap->params.rev > 0) { if (!(adap->flags & (USING_MSIX | USING_MSI))) ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ; } t3_write_reg(adap, A_SG_CONTROL, ctrl); t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) | V_LORCQDRBTHRSH(512)); t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10); t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) | V_TIMEOUT(200 * core_ticks_per_usec(adap))); t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH, adap->params.rev < T3_REV_C ? 1000 : 500); t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256); t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000); t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256); t3_write_reg(adap, A_SG_OCO_BASE, V_BASE1(0xfff)); t3_write_reg(adap, A_SG_DRB_PRI_THRESH, 63 * 1024); } /** * sgl_len - calculates the size of an SGL of the given capacity * @n: the number of SGL entries * * Calculates the number of flits needed for a scatter/gather list that * can hold the given number of entries. */ static __inline unsigned int sgl_len(unsigned int n) { return ((3 * n) / 2 + (n & 1)); } /** * get_imm_packet - return the next ingress packet buffer from a response * @resp: the response descriptor containing the packet data * * Return a packet containing the immediate data of the given response. */ static int get_imm_packet(adapter_t *sc, const struct rsp_desc *resp, struct mbuf *m) { m->m_len = m->m_pkthdr.len = IMMED_PKT_SIZE; m->m_ext.ext_buf = NULL; m->m_ext.ext_type = 0; memcpy(mtod(m, uint8_t *), resp->imm_data, IMMED_PKT_SIZE); return (0); } static __inline u_int flits_to_desc(u_int n) { return (flit_desc_map[n]); } #define SGE_PARERR (F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \ F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \ V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \ F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \ F_HIRCQPARITYERROR) #define SGE_FRAMINGERR (F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR) #define SGE_FATALERR (SGE_PARERR | SGE_FRAMINGERR | F_RSPQCREDITOVERFOW | \ F_RSPQDISABLED) /** * t3_sge_err_intr_handler - SGE async event interrupt handler * @adapter: the adapter * * Interrupt handler for SGE asynchronous (non-data) events. */ void t3_sge_err_intr_handler(adapter_t *adapter) { unsigned int v, status; status = t3_read_reg(adapter, A_SG_INT_CAUSE); if (status & SGE_PARERR) CH_ALERT(adapter, "SGE parity error (0x%x)\n", status & SGE_PARERR); if (status & SGE_FRAMINGERR) CH_ALERT(adapter, "SGE framing error (0x%x)\n", status & SGE_FRAMINGERR); if (status & F_RSPQCREDITOVERFOW) CH_ALERT(adapter, "SGE response queue credit overflow\n"); if (status & F_RSPQDISABLED) { v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS); CH_ALERT(adapter, "packet delivered to disabled response queue (0x%x)\n", (v >> S_RSPQ0DISABLED) & 0xff); } t3_write_reg(adapter, A_SG_INT_CAUSE, status); if (status & SGE_FATALERR) t3_fatal_err(adapter); } void t3_sge_prep(adapter_t *adap, struct sge_params *p) { int i, nqsets; nqsets = min(SGE_QSETS, mp_ncpus*4); fl_q_size = min(nmbclusters/(3*nqsets), FL_Q_SIZE); while (!powerof2(fl_q_size)) fl_q_size--; #if __FreeBSD_version >= 700111 if (cxgb_use_16k_clusters) jumbo_q_size = min(nmbjumbo16/(3*nqsets), JUMBO_Q_SIZE); else jumbo_q_size = min(nmbjumbo9/(3*nqsets), JUMBO_Q_SIZE); #else jumbo_q_size = min(nmbjumbop/(3*nqsets), JUMBO_Q_SIZE); #endif while (!powerof2(jumbo_q_size)) jumbo_q_size--; if (fl_q_size < (FL_Q_SIZE / 4) || jumbo_q_size < (JUMBO_Q_SIZE / 2)) device_printf(adap->dev, "Insufficient clusters and/or jumbo buffers.\n"); /* XXX Does ETHER_ALIGN need to be accounted for here? */ p->max_pkt_size = adap->sge.qs[0].fl[1].buf_size - sizeof(struct cpl_rx_data); for (i = 0; i < SGE_QSETS; ++i) { struct qset_params *q = p->qset + i; if (adap->params.nports > 2) { q->coalesce_usecs = 50; } else { #ifdef INVARIANTS q->coalesce_usecs = 10; #else q->coalesce_usecs = 5; #endif } q->polling = 0; q->rspq_size = RSPQ_Q_SIZE; q->fl_size = fl_q_size; q->jumbo_size = jumbo_q_size; q->txq_size[TXQ_ETH] = TX_ETH_Q_SIZE; q->txq_size[TXQ_OFLD] = 1024; q->txq_size[TXQ_CTRL] = 256; q->cong_thres = 0; } } int t3_sge_alloc(adapter_t *sc) { /* The parent tag. */ if (bus_dma_tag_create( NULL, /* parent */ 1, 0, /* algnmnt, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ BUS_SPACE_UNRESTRICTED, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 0, /* flags */ NULL, NULL, /* lock, lockarg */ &sc->parent_dmat)) { device_printf(sc->dev, "Cannot allocate parent DMA tag\n"); return (ENOMEM); } /* * DMA tag for normal sized RX frames */ if (bus_dma_tag_create(sc->parent_dmat, MCLBYTES, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->rx_dmat)) { device_printf(sc->dev, "Cannot allocate RX DMA tag\n"); return (ENOMEM); } /* * DMA tag for jumbo sized RX frames. */ if (bus_dma_tag_create(sc->parent_dmat, MJUM16BYTES, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM16BYTES, 1, MJUM16BYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->rx_jumbo_dmat)) { device_printf(sc->dev, "Cannot allocate RX jumbo DMA tag\n"); return (ENOMEM); } /* * DMA tag for TX frames. */ if (bus_dma_tag_create(sc->parent_dmat, 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, TX_MAX_SIZE, TX_MAX_SEGS, TX_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->tx_dmat)) { device_printf(sc->dev, "Cannot allocate TX DMA tag\n"); return (ENOMEM); } return (0); } int t3_sge_free(struct adapter * sc) { if (sc->tx_dmat != NULL) bus_dma_tag_destroy(sc->tx_dmat); if (sc->rx_jumbo_dmat != NULL) bus_dma_tag_destroy(sc->rx_jumbo_dmat); if (sc->rx_dmat != NULL) bus_dma_tag_destroy(sc->rx_dmat); if (sc->parent_dmat != NULL) bus_dma_tag_destroy(sc->parent_dmat); return (0); } void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p) { qs->rspq.holdoff_tmr = max(p->coalesce_usecs * 10, 1U); qs->rspq.polling = 0 /* p->polling */; } #if !defined(__i386__) && !defined(__amd64__) static void refill_fl_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) { struct refill_fl_cb_arg *cb_arg = arg; cb_arg->error = error; cb_arg->seg = segs[0]; cb_arg->nseg = nseg; } #endif /** * refill_fl - refill an SGE free-buffer list * @sc: the controller softc * @q: the free-list to refill * @n: the number of new buffers to allocate * * (Re)populate an SGE free-buffer list with up to @n new packet buffers. * The caller must assure that @n does not exceed the queue's capacity. */ static void refill_fl(adapter_t *sc, struct sge_fl *q, int n) { struct rx_sw_desc *sd = &q->sdesc[q->pidx]; struct rx_desc *d = &q->desc[q->pidx]; struct refill_fl_cb_arg cb_arg; caddr_t cl; int err, count = 0; int header_size = sizeof(struct m_hdr) + sizeof(struct pkthdr) + sizeof(struct m_ext_) + sizeof(uint32_t); cb_arg.error = 0; while (n--) { /* * We only allocate a cluster, mbuf allocation happens after rx */ if ((cl = cxgb_cache_get(q->zone)) == NULL) { log(LOG_WARNING, "Failed to allocate cluster\n"); goto done; } if ((sd->flags & RX_SW_DESC_MAP_CREATED) == 0) { if ((err = bus_dmamap_create(q->entry_tag, 0, &sd->map))) { log(LOG_WARNING, "bus_dmamap_create failed %d\n", err); uma_zfree(q->zone, cl); goto done; } sd->flags |= RX_SW_DESC_MAP_CREATED; } #if !defined(__i386__) && !defined(__amd64__) err = bus_dmamap_load(q->entry_tag, sd->map, cl + header_size, q->buf_size, refill_fl_cb, &cb_arg, 0); if (err != 0 || cb_arg.error) { log(LOG_WARNING, "failure in refill_fl %d\n", cb_arg.error); /* * XXX free cluster */ return; } #else cb_arg.seg.ds_addr = pmap_kextract((vm_offset_t)(cl + header_size)); #endif sd->flags |= RX_SW_DESC_INUSE; sd->rxsd_cl = cl; sd->data = cl + header_size; d->addr_lo = htobe32(cb_arg.seg.ds_addr & 0xffffffff); d->addr_hi = htobe32(((uint64_t)cb_arg.seg.ds_addr >>32) & 0xffffffff); d->len_gen = htobe32(V_FLD_GEN1(q->gen)); d->gen2 = htobe32(V_FLD_GEN2(q->gen)); d++; sd++; if (++q->pidx == q->size) { q->pidx = 0; q->gen ^= 1; sd = q->sdesc; d = q->desc; } q->credits++; count++; } done: if (count) t3_write_reg(sc, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id)); } /** * free_rx_bufs - free the Rx buffers on an SGE free list * @sc: the controle softc * @q: the SGE free list to clean up * * Release the buffers on an SGE free-buffer Rx queue. HW fetching from * this queue should be stopped before calling this function. */ static void free_rx_bufs(adapter_t *sc, struct sge_fl *q) { u_int cidx = q->cidx; while (q->credits--) { struct rx_sw_desc *d = &q->sdesc[cidx]; if (d->flags & RX_SW_DESC_INUSE) { bus_dmamap_unload(q->entry_tag, d->map); bus_dmamap_destroy(q->entry_tag, d->map); uma_zfree(q->zone, d->rxsd_cl); } d->rxsd_cl = NULL; if (++cidx == q->size) cidx = 0; } } static __inline void __refill_fl(adapter_t *adap, struct sge_fl *fl) { refill_fl(adap, fl, min(16U, fl->size - fl->credits)); } static __inline void __refill_fl_lt(adapter_t *adap, struct sge_fl *fl, int max) { if ((fl->size - fl->credits) < max) refill_fl(adap, fl, min(max, fl->size - fl->credits)); } void refill_fl_service(adapter_t *adap, struct sge_fl *fl) { __refill_fl_lt(adap, fl, 512); } /** * recycle_rx_buf - recycle a receive buffer * @adapter: the adapter * @q: the SGE free list * @idx: index of buffer to recycle * * Recycles the specified buffer on the given free list by adding it at * the next available slot on the list. */ static void recycle_rx_buf(adapter_t *adap, struct sge_fl *q, unsigned int idx) { struct rx_desc *from = &q->desc[idx]; struct rx_desc *to = &q->desc[q->pidx]; q->sdesc[q->pidx] = q->sdesc[idx]; to->addr_lo = from->addr_lo; // already big endian to->addr_hi = from->addr_hi; // likewise wmb(); to->len_gen = htobe32(V_FLD_GEN1(q->gen)); to->gen2 = htobe32(V_FLD_GEN2(q->gen)); q->credits++; if (++q->pidx == q->size) { q->pidx = 0; q->gen ^= 1; } t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id)); } static void alloc_ring_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { uint32_t *addr; addr = arg; *addr = segs[0].ds_addr; } static int alloc_ring(adapter_t *sc, size_t nelem, size_t elem_size, size_t sw_size, bus_addr_t *phys, void *desc, void *sdesc, bus_dma_tag_t *tag, bus_dmamap_t *map, bus_dma_tag_t parent_entry_tag, bus_dma_tag_t *entry_tag) { size_t len = nelem * elem_size; void *s = NULL; void *p = NULL; int err; if ((err = bus_dma_tag_create(sc->parent_dmat, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag)) != 0) { device_printf(sc->dev, "Cannot allocate descriptor tag\n"); return (ENOMEM); } if ((err = bus_dmamem_alloc(*tag, (void **)&p, BUS_DMA_NOWAIT, map)) != 0) { device_printf(sc->dev, "Cannot allocate descriptor memory\n"); return (ENOMEM); } bus_dmamap_load(*tag, *map, p, len, alloc_ring_cb, phys, 0); bzero(p, len); *(void **)desc = p; if (sw_size) { len = nelem * sw_size; s = malloc(len, M_DEVBUF, M_WAITOK|M_ZERO); *(void **)sdesc = s; } if (parent_entry_tag == NULL) return (0); if ((err = bus_dma_tag_create(parent_entry_tag, 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, TX_MAX_SIZE, TX_MAX_SEGS, TX_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, entry_tag)) != 0) { device_printf(sc->dev, "Cannot allocate descriptor entry tag\n"); return (ENOMEM); } return (0); } static void sge_slow_intr_handler(void *arg, int ncount) { adapter_t *sc = arg; t3_slow_intr_handler(sc); t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask); (void) t3_read_reg(sc, A_PL_INT_ENABLE0); } /** * sge_timer_cb - perform periodic maintenance of an SGE qset * @data: the SGE queue set to maintain * * Runs periodically from a timer to perform maintenance of an SGE queue * set. It performs two tasks: * * a) Cleans up any completed Tx descriptors that may still be pending. * Normal descriptor cleanup happens when new packets are added to a Tx * queue so this timer is relatively infrequent and does any cleanup only * if the Tx queue has not seen any new packets in a while. We make a * best effort attempt to reclaim descriptors, in that we don't wait * around if we cannot get a queue's lock (which most likely is because * someone else is queueing new packets and so will also handle the clean * up). Since control queues use immediate data exclusively we don't * bother cleaning them up here. * * b) Replenishes Rx queues that have run out due to memory shortage. * Normally new Rx buffers are added when existing ones are consumed but * when out of memory a queue can become empty. We try to add only a few * buffers here, the queue will be replenished fully as these new buffers * are used up if memory shortage has subsided. * * c) Return coalesced response queue credits in case a response queue is * starved. * * d) Ring doorbells for T304 tunnel queues since we have seen doorbell * fifo overflows and the FW doesn't implement any recovery scheme yet. */ static void sge_timer_cb(void *arg) { adapter_t *sc = arg; #ifndef IFNET_MULTIQUEUE struct port_info *pi; struct sge_qset *qs; struct sge_txq *txq; int i, j; int reclaim_ofl, refill_rx; for (i = 0; i < sc->params.nports; i++) { pi = &sc->port[i]; for (j = 0; j < pi->nqsets; j++) { qs = &sc->sge.qs[pi->first_qset + j]; txq = &qs->txq[0]; reclaim_ofl = txq[TXQ_OFLD].processed - txq[TXQ_OFLD].cleaned; refill_rx = ((qs->fl[0].credits < qs->fl[0].size) || (qs->fl[1].credits < qs->fl[1].size)); if (reclaim_ofl || refill_rx) { taskqueue_enqueue(sc->tq, &pi->timer_reclaim_task); break; } } } #endif if (sc->params.nports > 2) { int i; for_each_port(sc, i) { struct port_info *pi = &sc->port[i]; t3_write_reg(sc, A_SG_KDOORBELL, F_SELEGRCNTX | (FW_TUNNEL_SGEEC_START + pi->first_qset)); } } if (sc->open_device_map != 0) callout_reset(&sc->sge_timer_ch, TX_RECLAIM_PERIOD, sge_timer_cb, sc); } /* * This is meant to be a catch-all function to keep sge state private * to sge.c * */ int t3_sge_init_adapter(adapter_t *sc) { callout_init(&sc->sge_timer_ch, CALLOUT_MPSAFE); callout_reset(&sc->sge_timer_ch, TX_RECLAIM_PERIOD, sge_timer_cb, sc); TASK_INIT(&sc->slow_intr_task, 0, sge_slow_intr_handler, sc); mi_init(); cxgb_cache_init(); return (0); } int t3_sge_reset_adapter(adapter_t *sc) { callout_reset(&sc->sge_timer_ch, TX_RECLAIM_PERIOD, sge_timer_cb, sc); return (0); } int t3_sge_init_port(struct port_info *pi) { TASK_INIT(&pi->timer_reclaim_task, 0, sge_timer_reclaim, pi); return (0); } void t3_sge_deinit_sw(adapter_t *sc) { mi_deinit(); } /** * refill_rspq - replenish an SGE response queue * @adapter: the adapter * @q: the response queue to replenish * @credits: how many new responses to make available * * Replenishes a response queue by making the supplied number of responses * available to HW. */ static __inline void refill_rspq(adapter_t *sc, const struct sge_rspq *q, u_int credits) { /* mbufs are allocated on demand when a rspq entry is processed. */ t3_write_reg(sc, A_SG_RSPQ_CREDIT_RETURN, V_RSPQ(q->cntxt_id) | V_CREDITS(credits)); } static __inline void sge_txq_reclaim_(struct sge_txq *txq, int force) { if (desc_reclaimable(txq) < 16) return; if (mtx_trylock(&txq->lock) == 0) return; reclaim_completed_tx_(txq, 16); mtx_unlock(&txq->lock); } static void sge_txq_reclaim_handler(void *arg, int ncount) { struct sge_txq *q = arg; sge_txq_reclaim_(q, TRUE); } static void sge_timer_reclaim(void *arg, int ncount) { struct port_info *pi = arg; int i, nqsets = pi->nqsets; adapter_t *sc = pi->adapter; struct sge_qset *qs; struct sge_txq *txq; struct mtx *lock; #ifdef IFNET_MULTIQUEUE panic("%s should not be called with multiqueue support\n", __FUNCTION__); #endif for (i = 0; i < nqsets; i++) { qs = &sc->sge.qs[pi->first_qset + i]; txq = &qs->txq[TXQ_OFLD]; sge_txq_reclaim_(txq, FALSE); lock = (sc->flags & USING_MSIX) ? &qs->rspq.lock : &sc->sge.qs[0].rspq.lock; if (mtx_trylock(lock)) { /* XXX currently assume that we are *NOT* polling */ uint32_t status = t3_read_reg(sc, A_SG_RSPQ_FL_STATUS); if (qs->fl[0].credits < qs->fl[0].size - 16) __refill_fl(sc, &qs->fl[0]); if (qs->fl[1].credits < qs->fl[1].size - 16) __refill_fl(sc, &qs->fl[1]); if (status & (1 << qs->rspq.cntxt_id)) { if (qs->rspq.credits) { refill_rspq(sc, &qs->rspq, 1); qs->rspq.credits--; t3_write_reg(sc, A_SG_RSPQ_FL_STATUS, 1 << qs->rspq.cntxt_id); } } mtx_unlock(lock); } } } /** * init_qset_cntxt - initialize an SGE queue set context info * @qs: the queue set * @id: the queue set id * * Initializes the TIDs and context ids for the queues of a queue set. */ static void init_qset_cntxt(struct sge_qset *qs, u_int id) { qs->rspq.cntxt_id = id; qs->fl[0].cntxt_id = 2 * id; qs->fl[1].cntxt_id = 2 * id + 1; qs->txq[TXQ_ETH].cntxt_id = FW_TUNNEL_SGEEC_START + id; qs->txq[TXQ_ETH].token = FW_TUNNEL_TID_START + id; qs->txq[TXQ_OFLD].cntxt_id = FW_OFLD_SGEEC_START + id; qs->txq[TXQ_CTRL].cntxt_id = FW_CTRL_SGEEC_START + id; qs->txq[TXQ_CTRL].token = FW_CTRL_TID_START + id; mbufq_init(&qs->txq[TXQ_ETH].sendq); mbufq_init(&qs->txq[TXQ_OFLD].sendq); mbufq_init(&qs->txq[TXQ_CTRL].sendq); } static void txq_prod(struct sge_txq *txq, unsigned int ndesc, struct txq_state *txqs) { txq->in_use += ndesc; /* * XXX we don't handle stopping of queue * presumably start handles this when we bump against the end */ txqs->gen = txq->gen; txq->unacked += ndesc; txqs->compl = (txq->unacked & 32) << (S_WR_COMPL - 5); txq->unacked &= 31; txqs->pidx = txq->pidx; txq->pidx += ndesc; #ifdef INVARIANTS if (((txqs->pidx > txq->cidx) && (txq->pidx < txqs->pidx) && (txq->pidx >= txq->cidx)) || ((txqs->pidx < txq->cidx) && (txq->pidx >= txq-> cidx)) || ((txqs->pidx < txq->cidx) && (txq->cidx < txqs->pidx))) panic("txqs->pidx=%d txq->pidx=%d txq->cidx=%d", txqs->pidx, txq->pidx, txq->cidx); #endif if (txq->pidx >= txq->size) { txq->pidx -= txq->size; txq->gen ^= 1; } } /** * calc_tx_descs - calculate the number of Tx descriptors for a packet * @m: the packet mbufs * @nsegs: the number of segments * * Returns the number of Tx descriptors needed for the given Ethernet * packet. Ethernet packets require addition of WR and CPL headers. */ static __inline unsigned int calc_tx_descs(const struct mbuf *m, int nsegs) { unsigned int flits; if (m->m_pkthdr.len <= WR_LEN - sizeof(struct cpl_tx_pkt)) return 1; flits = sgl_len(nsegs) + 2; #ifdef TSO_SUPPORTED if (m->m_pkthdr.csum_flags & CSUM_TSO) flits++; #endif return flits_to_desc(flits); } static unsigned int busdma_map_mbufs(struct mbuf **m, struct sge_txq *txq, struct tx_sw_desc *txsd, bus_dma_segment_t *segs, int *nsegs) { struct mbuf *m0; int err, pktlen, pass = 0; retry: err = 0; m0 = *m; pktlen = m0->m_pkthdr.len; #if defined(__i386__) || defined(__amd64__) if (busdma_map_sg_collapse(m, segs, nsegs) == 0) { goto done; } else #endif err = bus_dmamap_load_mbuf_sg(txq->entry_tag, txsd->map, m0, segs, nsegs, 0); if (err == 0) { goto done; } if (err == EFBIG && pass == 0) { pass = 1; /* Too many segments, try to defrag */ m0 = m_defrag(m0, M_DONTWAIT); if (m0 == NULL) { m_freem(*m); *m = NULL; return (ENOBUFS); } *m = m0; goto retry; } else if (err == ENOMEM) { return (err); } if (err) { if (cxgb_debug) printf("map failure err=%d pktlen=%d\n", err, pktlen); m_freem(m0); *m = NULL; return (err); } done: #if !defined(__i386__) && !defined(__amd64__) bus_dmamap_sync(txq->entry_tag, txsd->map, BUS_DMASYNC_PREWRITE); #endif txsd->flags |= TX_SW_DESC_MAPPED; return (0); } /** * make_sgl - populate a scatter/gather list for a packet * @sgp: the SGL to populate * @segs: the packet dma segments * @nsegs: the number of segments * * Generates a scatter/gather list for the buffers that make up a packet * and returns the SGL size in 8-byte words. The caller must size the SGL * appropriately. */ static __inline void make_sgl(struct sg_ent *sgp, bus_dma_segment_t *segs, int nsegs) { int i, idx; for (idx = 0, i = 0; i < nsegs; i++) { /* * firmware doesn't like empty segments */ if (segs[i].ds_len == 0) continue; if (i && idx == 0) ++sgp; sgp->len[idx] = htobe32(segs[i].ds_len); sgp->addr[idx] = htobe64(segs[i].ds_addr); idx ^= 1; } if (idx) { sgp->len[idx] = 0; sgp->addr[idx] = 0; } } /** * check_ring_tx_db - check and potentially ring a Tx queue's doorbell * @adap: the adapter * @q: the Tx queue * * Ring the doorbel if a Tx queue is asleep. There is a natural race, * where the HW is going to sleep just after we checked, however, * then the interrupt handler will detect the outstanding TX packet * and ring the doorbell for us. * * When GTS is disabled we unconditionally ring the doorbell. */ static __inline void check_ring_tx_db(adapter_t *adap, struct sge_txq *q) { #if USE_GTS clear_bit(TXQ_LAST_PKT_DB, &q->flags); if (test_and_set_bit(TXQ_RUNNING, &q->flags) == 0) { set_bit(TXQ_LAST_PKT_DB, &q->flags); #ifdef T3_TRACE T3_TRACE1(adap->tb[q->cntxt_id & 7], "doorbell Tx, cntxt %d", q->cntxt_id); #endif t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); } #else wmb(); /* write descriptors before telling HW */ t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); #endif } static __inline void wr_gen2(struct tx_desc *d, unsigned int gen) { #if SGE_NUM_GENBITS == 2 d->flit[TX_DESC_FLITS - 1] = htobe64(gen); #endif } /** * write_wr_hdr_sgl - write a WR header and, optionally, SGL * @ndesc: number of Tx descriptors spanned by the SGL * @txd: first Tx descriptor to be written * @txqs: txq state (generation and producer index) * @txq: the SGE Tx queue * @sgl: the SGL * @flits: number of flits to the start of the SGL in the first descriptor * @sgl_flits: the SGL size in flits * @wr_hi: top 32 bits of WR header based on WR type (big endian) * @wr_lo: low 32 bits of WR header based on WR type (big endian) * * Write a work request header and an associated SGL. If the SGL is * small enough to fit into one Tx descriptor it has already been written * and we just need to write the WR header. Otherwise we distribute the * SGL across the number of descriptors it spans. */ static void write_wr_hdr_sgl(unsigned int ndesc, struct tx_desc *txd, struct txq_state *txqs, const struct sge_txq *txq, const struct sg_ent *sgl, unsigned int flits, unsigned int sgl_flits, unsigned int wr_hi, unsigned int wr_lo) { struct work_request_hdr *wrp = (struct work_request_hdr *)txd; struct tx_sw_desc *txsd = &txq->sdesc[txqs->pidx]; if (__predict_true(ndesc == 1)) { wrp->wr_hi = htonl(F_WR_SOP | F_WR_EOP | V_WR_DATATYPE(1) | V_WR_SGLSFLT(flits)) | wr_hi; wmb(); wrp->wr_lo = htonl(V_WR_LEN(flits + sgl_flits) | V_WR_GEN(txqs->gen)) | wr_lo; /* XXX gen? */ wr_gen2(txd, txqs->gen); } else { unsigned int ogen = txqs->gen; const uint64_t *fp = (const uint64_t *)sgl; struct work_request_hdr *wp = wrp; wrp->wr_hi = htonl(F_WR_SOP | V_WR_DATATYPE(1) | V_WR_SGLSFLT(flits)) | wr_hi; while (sgl_flits) { unsigned int avail = WR_FLITS - flits; if (avail > sgl_flits) avail = sgl_flits; memcpy(&txd->flit[flits], fp, avail * sizeof(*fp)); sgl_flits -= avail; ndesc--; if (!sgl_flits) break; fp += avail; txd++; txsd++; if (++txqs->pidx == txq->size) { txqs->pidx = 0; txqs->gen ^= 1; txd = txq->desc; txsd = txq->sdesc; } /* * when the head of the mbuf chain * is freed all clusters will be freed * with it */ KASSERT(txsd->mi.mi_base == NULL, ("overwriting valid entry mi_base==%p", txsd->mi.mi_base)); wrp = (struct work_request_hdr *)txd; wrp->wr_hi = htonl(V_WR_DATATYPE(1) | V_WR_SGLSFLT(1)) | wr_hi; wrp->wr_lo = htonl(V_WR_LEN(min(WR_FLITS, sgl_flits + 1)) | V_WR_GEN(txqs->gen)) | wr_lo; wr_gen2(txd, txqs->gen); flits = 1; } wrp->wr_hi |= htonl(F_WR_EOP); wmb(); wp->wr_lo = htonl(V_WR_LEN(WR_FLITS) | V_WR_GEN(ogen)) | wr_lo; wr_gen2((struct tx_desc *)wp, ogen); } } /* sizeof(*eh) + sizeof(*ip) + sizeof(*tcp) */ #define TCPPKTHDRSIZE (ETHER_HDR_LEN + 20 + 20) #ifdef VLAN_SUPPORTED #define GET_VTAG(cntrl, m) \ do { \ if ((m)->m_flags & M_VLANTAG) \ cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN((m)->m_pkthdr.ether_vtag); \ } while (0) #define GET_VTAG_MI(cntrl, mi) \ do { \ if ((mi)->mi_flags & M_VLANTAG) \ cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN((mi)->mi_ether_vtag); \ } while (0) #else #define GET_VTAG(cntrl, m) #define GET_VTAG_MI(cntrl, m) #endif int t3_encap(struct sge_qset *qs, struct mbuf **m, int count) { adapter_t *sc; struct mbuf *m0; struct sge_txq *txq; struct txq_state txqs; struct port_info *pi; unsigned int ndesc, flits, cntrl, mlen; int err, nsegs, tso_info = 0; struct work_request_hdr *wrp; struct tx_sw_desc *txsd; struct sg_ent *sgp, *sgl; uint32_t wr_hi, wr_lo, sgl_flits; bus_dma_segment_t segs[TX_MAX_SEGS]; struct tx_desc *txd; struct mbuf_vec *mv; struct mbuf_iovec *mi; DPRINTF("t3_encap cpu=%d ", curcpu); mi = NULL; pi = qs->port; sc = pi->adapter; txq = &qs->txq[TXQ_ETH]; txd = &txq->desc[txq->pidx]; txsd = &txq->sdesc[txq->pidx]; sgl = txq->txq_sgl; m0 = *m; mtx_assert(&txq->lock, MA_OWNED); cntrl = V_TXPKT_INTF(pi->txpkt_intf); /* * XXX need to add VLAN support for 6.x */ #ifdef VLAN_SUPPORTED if (m0->m_pkthdr.csum_flags & (CSUM_TSO)) tso_info = V_LSO_MSS(m0->m_pkthdr.tso_segsz); #endif KASSERT(txsd->mi.mi_base == NULL, ("overwriting valid entry mi_base==%p", txsd->mi.mi_base)); if (count > 1) { panic("count > 1 not support in CVS\n"); if ((err = busdma_map_sg_vec(m, &m0, segs, count))) return (err); nsegs = count; } else if ((err = busdma_map_sg_collapse(&m0, segs, &nsegs))) { if (cxgb_debug) printf("failed ... err=%d\n", err); return (err); } KASSERT(m0->m_pkthdr.len, ("empty packet nsegs=%d count=%d", nsegs, count)); if (!(m0->m_pkthdr.len <= PIO_LEN)) { mi_collapse_mbuf(&txsd->mi, m0); mi = &txsd->mi; } if (count > 1) { struct cpl_tx_pkt_batch *cpl_batch = (struct cpl_tx_pkt_batch *)txd; int i, fidx; struct mbuf_iovec *batchmi; mv = mtomv(m0); batchmi = mv->mv_vec; wrp = (struct work_request_hdr *)txd; flits = count*2 + 1; txq_prod(txq, 1, &txqs); for (fidx = 1, i = 0; i < count; i++, batchmi++, fidx += 2) { struct cpl_tx_pkt_batch_entry *cbe = &cpl_batch->pkt_entry[i]; cntrl = V_TXPKT_INTF(pi->txpkt_intf); GET_VTAG_MI(cntrl, batchmi); cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT); if (__predict_false(!(m0->m_pkthdr.csum_flags & CSUM_IP))) cntrl |= F_TXPKT_IPCSUM_DIS; if (__predict_false(!(m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)))) cntrl |= F_TXPKT_L4CSUM_DIS; cbe->cntrl = htonl(cntrl); cbe->len = htonl(batchmi->mi_len | 0x80000000); cbe->addr = htobe64(segs[i].ds_addr); txd->flit[fidx] |= htobe64(1 << 24); } wrp->wr_hi = htonl(F_WR_SOP | F_WR_EOP | V_WR_DATATYPE(1) | V_WR_SGLSFLT(flits)) | htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | txqs.compl); wmb(); wrp->wr_lo = htonl(V_WR_LEN(flits) | V_WR_GEN(txqs.gen)) | htonl(V_WR_TID(txq->token)); /* XXX gen? */ wr_gen2(txd, txqs.gen); check_ring_tx_db(sc, txq); return (0); } else if (tso_info) { int eth_type; struct cpl_tx_pkt_lso *hdr = (struct cpl_tx_pkt_lso *)txd; struct ether_header *eh; struct ip *ip; struct tcphdr *tcp; txd->flit[2] = 0; GET_VTAG(cntrl, m0); cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT_LSO); hdr->cntrl = htonl(cntrl); mlen = m0->m_pkthdr.len; hdr->len = htonl(mlen | 0x80000000); if (__predict_false(mlen < TCPPKTHDRSIZE)) { printf("mbuf=%p,len=%d,tso_segsz=%d,csum_flags=%#x,flags=%#x", m0, mlen, m0->m_pkthdr.tso_segsz, m0->m_pkthdr.csum_flags, m0->m_flags); panic("tx tso packet too small"); } /* Make sure that ether, ip, tcp headers are all in m0 */ if (__predict_false(m0->m_len < TCPPKTHDRSIZE)) { m0 = m_pullup(m0, TCPPKTHDRSIZE); if (__predict_false(m0 == NULL)) { /* XXX panic probably an overreaction */ panic("couldn't fit header into mbuf"); } } eh = mtod(m0, struct ether_header *); if (eh->ether_type == htons(ETHERTYPE_VLAN)) { eth_type = CPL_ETH_II_VLAN; ip = (struct ip *)((struct ether_vlan_header *)eh + 1); } else { eth_type = CPL_ETH_II; ip = (struct ip *)(eh + 1); } tcp = (struct tcphdr *)(ip + 1); tso_info |= V_LSO_ETH_TYPE(eth_type) | V_LSO_IPHDR_WORDS(ip->ip_hl) | V_LSO_TCPHDR_WORDS(tcp->th_off); hdr->lso_info = htonl(tso_info); if (__predict_false(mlen <= PIO_LEN)) { /* * pkt not undersized but fits in PIO_LEN * Indicates a TSO bug at the higher levels. */ txq_prod(txq, 1, &txqs); m_copydata(m0, 0, mlen, (caddr_t)&txd->flit[3]); m_freem(m0); m0 = NULL; flits = (mlen + 7) / 8 + 3; hdr->wr.wr_hi = htonl(V_WR_BCNTLFLT(mlen & 7) | V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | F_WR_SOP | F_WR_EOP | txqs.compl); wmb(); hdr->wr.wr_lo = htonl(V_WR_LEN(flits) | V_WR_GEN(txqs.gen) | V_WR_TID(txq->token)); wr_gen2(txd, txqs.gen); check_ring_tx_db(sc, txq); return (0); } flits = 3; } else { struct cpl_tx_pkt *cpl = (struct cpl_tx_pkt *)txd; GET_VTAG(cntrl, m0); cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT); if (__predict_false(!(m0->m_pkthdr.csum_flags & CSUM_IP))) cntrl |= F_TXPKT_IPCSUM_DIS; if (__predict_false(!(m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)))) cntrl |= F_TXPKT_L4CSUM_DIS; cpl->cntrl = htonl(cntrl); mlen = m0->m_pkthdr.len; cpl->len = htonl(mlen | 0x80000000); if (mlen <= PIO_LEN) { txq_prod(txq, 1, &txqs); m_copydata(m0, 0, mlen, (caddr_t)&txd->flit[2]); m_freem(m0); m0 = NULL; flits = (mlen + 7) / 8 + 2; cpl->wr.wr_hi = htonl(V_WR_BCNTLFLT(mlen & 7) | V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | F_WR_SOP | F_WR_EOP | txqs.compl); wmb(); cpl->wr.wr_lo = htonl(V_WR_LEN(flits) | V_WR_GEN(txqs.gen) | V_WR_TID(txq->token)); wr_gen2(txd, txqs.gen); check_ring_tx_db(sc, txq); DPRINTF("pio buf\n"); return (0); } DPRINTF("regular buf\n"); flits = 2; } wrp = (struct work_request_hdr *)txd; #ifdef nomore /* * XXX need to move into one of the helper routines above * */ if ((err = busdma_map_mbufs(m, txq, txsd, segs, &nsegs)) != 0) return (err); m0 = *m; #endif ndesc = calc_tx_descs(m0, nsegs); sgp = (ndesc == 1) ? (struct sg_ent *)&txd->flit[flits] : sgl; make_sgl(sgp, segs, nsegs); sgl_flits = sgl_len(nsegs); DPRINTF("make_sgl success nsegs==%d ndesc==%d\n", nsegs, ndesc); txq_prod(txq, ndesc, &txqs); wr_hi = htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | txqs.compl); wr_lo = htonl(V_WR_TID(txq->token)); write_wr_hdr_sgl(ndesc, txd, &txqs, txq, sgl, flits, sgl_flits, wr_hi, wr_lo); check_ring_tx_db(pi->adapter, txq); if ((m0->m_type == MT_DATA) && ((m0->m_flags & (M_EXT|M_NOFREE)) == M_EXT) && (m0->m_ext.ext_type != EXT_PACKET)) { m0->m_flags &= ~M_EXT ; cxgb_mbufs_outstanding--; m_free(m0); } return (0); } /** * write_imm - write a packet into a Tx descriptor as immediate data * @d: the Tx descriptor to write * @m: the packet * @len: the length of packet data to write as immediate data * @gen: the generation bit value to write * * Writes a packet as immediate data into a Tx descriptor. The packet * contains a work request at its beginning. We must write the packet * carefully so the SGE doesn't read accidentally before it's written in * its entirety. */ static __inline void write_imm(struct tx_desc *d, struct mbuf *m, unsigned int len, unsigned int gen) { struct work_request_hdr *from = mtod(m, struct work_request_hdr *); struct work_request_hdr *to = (struct work_request_hdr *)d; if (len > WR_LEN) panic("len too big %d\n", len); if (len < sizeof(*from)) panic("len too small %d", len); memcpy(&to[1], &from[1], len - sizeof(*from)); to->wr_hi = from->wr_hi | htonl(F_WR_SOP | F_WR_EOP | V_WR_BCNTLFLT(len & 7)); wmb(); to->wr_lo = from->wr_lo | htonl(V_WR_GEN(gen) | V_WR_LEN((len + 7) / 8)); wr_gen2(d, gen); /* * This check is a hack we should really fix the logic so * that this can't happen */ if (m->m_type != MT_DONTFREE) m_freem(m); } /** * check_desc_avail - check descriptor availability on a send queue * @adap: the adapter * @q: the TX queue * @m: the packet needing the descriptors * @ndesc: the number of Tx descriptors needed * @qid: the Tx queue number in its queue set (TXQ_OFLD or TXQ_CTRL) * * Checks if the requested number of Tx descriptors is available on an * SGE send queue. If the queue is already suspended or not enough * descriptors are available the packet is queued for later transmission. * Must be called with the Tx queue locked. * * Returns 0 if enough descriptors are available, 1 if there aren't * enough descriptors and the packet has been queued, and 2 if the caller * needs to retry because there weren't enough descriptors at the * beginning of the call but some freed up in the mean time. */ static __inline int check_desc_avail(adapter_t *adap, struct sge_txq *q, struct mbuf *m, unsigned int ndesc, unsigned int qid) { /* * XXX We currently only use this for checking the control queue * the control queue is only used for binding qsets which happens * at init time so we are guaranteed enough descriptors */ if (__predict_false(!mbufq_empty(&q->sendq))) { addq_exit: mbufq_tail(&q->sendq, m); return 1; } if (__predict_false(q->size - q->in_use < ndesc)) { struct sge_qset *qs = txq_to_qset(q, qid); setbit(&qs->txq_stopped, qid); smp_mb(); if (should_restart_tx(q) && test_and_clear_bit(qid, &qs->txq_stopped)) return 2; q->stops++; goto addq_exit; } return 0; } /** * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs * @q: the SGE control Tx queue * * This is a variant of reclaim_completed_tx() that is used for Tx queues * that send only immediate data (presently just the control queues) and * thus do not have any mbufs */ static __inline void reclaim_completed_tx_imm(struct sge_txq *q) { unsigned int reclaim = q->processed - q->cleaned; mtx_assert(&q->lock, MA_OWNED); q->in_use -= reclaim; q->cleaned += reclaim; } static __inline int immediate(const struct mbuf *m) { return m->m_len <= WR_LEN && m->m_pkthdr.len <= WR_LEN ; } /** * ctrl_xmit - send a packet through an SGE control Tx queue * @adap: the adapter * @q: the control queue * @m: the packet * * Send a packet through an SGE control Tx queue. Packets sent through * a control queue must fit entirely as immediate data in a single Tx * descriptor and have no page fragments. */ static int ctrl_xmit(adapter_t *adap, struct sge_txq *q, struct mbuf *m) { int ret; struct work_request_hdr *wrp = mtod(m, struct work_request_hdr *); if (__predict_false(!immediate(m))) { m_freem(m); return 0; } wrp->wr_hi |= htonl(F_WR_SOP | F_WR_EOP); wrp->wr_lo = htonl(V_WR_TID(q->token)); mtx_lock(&q->lock); again: reclaim_completed_tx_imm(q); ret = check_desc_avail(adap, q, m, 1, TXQ_CTRL); if (__predict_false(ret)) { if (ret == 1) { mtx_unlock(&q->lock); return (ENOSPC); } goto again; } write_imm(&q->desc[q->pidx], m, m->m_len, q->gen); q->in_use++; if (++q->pidx >= q->size) { q->pidx = 0; q->gen ^= 1; } mtx_unlock(&q->lock); wmb(); wmb(); t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); return (0); } /** * restart_ctrlq - restart a suspended control queue * @qs: the queue set cotaining the control queue * * Resumes transmission on a suspended Tx control queue. */ static void restart_ctrlq(void *data, int npending) { struct mbuf *m; struct sge_qset *qs = (struct sge_qset *)data; struct sge_txq *q = &qs->txq[TXQ_CTRL]; adapter_t *adap = qs->port->adapter; mtx_lock(&q->lock); again: reclaim_completed_tx_imm(q); while (q->in_use < q->size && (m = mbufq_dequeue(&q->sendq)) != NULL) { write_imm(&q->desc[q->pidx], m, m->m_len, q->gen); if (++q->pidx >= q->size) { q->pidx = 0; q->gen ^= 1; } q->in_use++; } if (!mbufq_empty(&q->sendq)) { setbit(&qs->txq_stopped, TXQ_CTRL); smp_mb(); if (should_restart_tx(q) && test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped)) goto again; q->stops++; } mtx_unlock(&q->lock); wmb(); t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); } /* * Send a management message through control queue 0 */ int t3_mgmt_tx(struct adapter *adap, struct mbuf *m) { return ctrl_xmit(adap, &adap->sge.qs[0].txq[TXQ_CTRL], m); } /** * free_qset - free the resources of an SGE queue set * @sc: the controller owning the queue set * @q: the queue set * * Release the HW and SW resources associated with an SGE queue set, such * as HW contexts, packet buffers, and descriptor rings. Traffic to the * queue set must be quiesced prior to calling this. */ void t3_free_qset(adapter_t *sc, struct sge_qset *q) { int i; t3_free_tx_desc_all(&q->txq[TXQ_ETH]); for (i = 0; i < SGE_TXQ_PER_SET; i++) if (q->txq[i].txq_mr.br_ring != NULL) { free(q->txq[i].txq_mr.br_ring, M_DEVBUF); mtx_destroy(&q->txq[i].txq_mr.br_lock); } for (i = 0; i < SGE_RXQ_PER_SET; ++i) { if (q->fl[i].desc) { mtx_lock_spin(&sc->sge.reg_lock); t3_sge_disable_fl(sc, q->fl[i].cntxt_id); mtx_unlock_spin(&sc->sge.reg_lock); bus_dmamap_unload(q->fl[i].desc_tag, q->fl[i].desc_map); bus_dmamem_free(q->fl[i].desc_tag, q->fl[i].desc, q->fl[i].desc_map); bus_dma_tag_destroy(q->fl[i].desc_tag); bus_dma_tag_destroy(q->fl[i].entry_tag); } if (q->fl[i].sdesc) { free_rx_bufs(sc, &q->fl[i]); free(q->fl[i].sdesc, M_DEVBUF); } } for (i = 0; i < SGE_TXQ_PER_SET; i++) { if (q->txq[i].desc) { mtx_lock_spin(&sc->sge.reg_lock); t3_sge_enable_ecntxt(sc, q->txq[i].cntxt_id, 0); mtx_unlock_spin(&sc->sge.reg_lock); bus_dmamap_unload(q->txq[i].desc_tag, q->txq[i].desc_map); bus_dmamem_free(q->txq[i].desc_tag, q->txq[i].desc, q->txq[i].desc_map); bus_dma_tag_destroy(q->txq[i].desc_tag); bus_dma_tag_destroy(q->txq[i].entry_tag); MTX_DESTROY(&q->txq[i].lock); } if (q->txq[i].sdesc) { free(q->txq[i].sdesc, M_DEVBUF); } } if (q->rspq.desc) { mtx_lock_spin(&sc->sge.reg_lock); t3_sge_disable_rspcntxt(sc, q->rspq.cntxt_id); mtx_unlock_spin(&sc->sge.reg_lock); bus_dmamap_unload(q->rspq.desc_tag, q->rspq.desc_map); bus_dmamem_free(q->rspq.desc_tag, q->rspq.desc, q->rspq.desc_map); bus_dma_tag_destroy(q->rspq.desc_tag); MTX_DESTROY(&q->rspq.lock); } tcp_lro_free(&q->lro.ctrl); bzero(q, sizeof(*q)); } /** * t3_free_sge_resources - free SGE resources * @sc: the adapter softc * * Frees resources used by the SGE queue sets. */ void -t3_free_sge_resources(adapter_t *sc) +t3_free_sge_resources(adapter_t *sc, int nqsets) { - int i, nqsets; - -#ifdef IFNET_MULTIQUEUE - panic("%s should not be called when IFNET_MULTIQUEUE is defined", __FUNCTION__); -#endif - for (nqsets = i = 0; i < (sc)->params.nports; i++) - nqsets += sc->port[i].nqsets; + int i; for (i = 0; i < nqsets; ++i) t3_free_qset(sc, &sc->sge.qs[i]); } /** * t3_sge_start - enable SGE * @sc: the controller softc * * Enables the SGE for DMAs. This is the last step in starting packet * transfers. */ void t3_sge_start(adapter_t *sc) { t3_set_reg_field(sc, A_SG_CONTROL, F_GLOBALENABLE, F_GLOBALENABLE); } /** * t3_sge_stop - disable SGE operation * @sc: the adapter * * Disables the DMA engine. This can be called in emeregencies (e.g., * from error interrupts) or from normal process context. In the latter * case it also disables any pending queue restart tasklets. Note that * if it is called in interrupt context it cannot disable the restart * tasklets as it cannot wait, however the tasklets will have no effect * since the doorbells are disabled and the driver will call this again * later from process context, at which time the tasklets will be stopped * if they are still running. */ void t3_sge_stop(adapter_t *sc) { int i, nqsets; t3_set_reg_field(sc, A_SG_CONTROL, F_GLOBALENABLE, 0); if (sc->tq == NULL) return; for (nqsets = i = 0; i < (sc)->params.nports; i++) nqsets += sc->port[i].nqsets; #ifdef notyet /* * * XXX */ for (i = 0; i < nqsets; ++i) { struct sge_qset *qs = &sc->sge.qs[i]; taskqueue_drain(sc->tq, &qs->txq[TXQ_OFLD].qresume_task); taskqueue_drain(sc->tq, &qs->txq[TXQ_CTRL].qresume_task); } #endif } /** * t3_free_tx_desc - reclaims Tx descriptors and their buffers * @adapter: the adapter * @q: the Tx queue to reclaim descriptors from * @reclaimable: the number of descriptors to reclaim * @m_vec_size: maximum number of buffers to reclaim * @desc_reclaimed: returns the number of descriptors reclaimed * * Reclaims Tx descriptors from an SGE Tx queue and frees the associated * Tx buffers. Called with the Tx queue lock held. * * Returns number of buffers of reclaimed */ void t3_free_tx_desc(struct sge_txq *q, int reclaimable) { struct tx_sw_desc *txsd; unsigned int cidx; #ifdef T3_TRACE T3_TRACE2(sc->tb[q->cntxt_id & 7], "reclaiming %u Tx descriptors at cidx %u", reclaimable, cidx); #endif cidx = q->cidx; txsd = &q->sdesc[cidx]; DPRINTF("reclaiming %d WR\n", reclaimable); mtx_assert(&q->lock, MA_OWNED); while (reclaimable--) { DPRINTF("cidx=%d d=%p\n", cidx, txsd); if (txsd->mi.mi_base != NULL) { if (txsd->flags & TX_SW_DESC_MAPPED) { bus_dmamap_unload(q->entry_tag, txsd->map); txsd->flags &= ~TX_SW_DESC_MAPPED; } m_freem_iovec(&txsd->mi); buf_ring_scan(&q->txq_mr, txsd->mi.mi_base, __FILE__, __LINE__); txsd->mi.mi_base = NULL; #if defined(DIAGNOSTIC) && 0 if (m_get_priority(txsd->m[0]) != cidx) printf("pri=%d cidx=%d\n", (int)m_get_priority(txsd->m[0]), cidx); #endif } else q->txq_skipped++; ++txsd; if (++cidx == q->size) { cidx = 0; txsd = q->sdesc; } } q->cidx = cidx; } void t3_free_tx_desc_all(struct sge_txq *q) { int i; struct tx_sw_desc *txsd; for (i = 0; i < q->size; i++) { txsd = &q->sdesc[i]; if (txsd->mi.mi_base != NULL) { if (txsd->flags & TX_SW_DESC_MAPPED) { bus_dmamap_unload(q->entry_tag, txsd->map); txsd->flags &= ~TX_SW_DESC_MAPPED; } m_freem_iovec(&txsd->mi); bzero(&txsd->mi, sizeof(txsd->mi)); } } } /** * is_new_response - check if a response is newly written * @r: the response descriptor * @q: the response queue * * Returns true if a response descriptor contains a yet unprocessed * response. */ static __inline int is_new_response(const struct rsp_desc *r, const struct sge_rspq *q) { return (r->intr_gen & F_RSPD_GEN2) == q->gen; } #define RSPD_GTS_MASK (F_RSPD_TXQ0_GTS | F_RSPD_TXQ1_GTS) #define RSPD_CTRL_MASK (RSPD_GTS_MASK | \ V_RSPD_TXQ0_CR(M_RSPD_TXQ0_CR) | \ V_RSPD_TXQ1_CR(M_RSPD_TXQ1_CR) | \ V_RSPD_TXQ2_CR(M_RSPD_TXQ2_CR)) /* How long to delay the next interrupt in case of memory shortage, in 0.1us. */ #define NOMEM_INTR_DELAY 2500 /** * write_ofld_wr - write an offload work request * @adap: the adapter * @m: the packet to send * @q: the Tx queue * @pidx: index of the first Tx descriptor to write * @gen: the generation value to use * @ndesc: number of descriptors the packet will occupy * * Write an offload work request to send the supplied packet. The packet * data already carry the work request with most fields populated. */ static void write_ofld_wr(adapter_t *adap, struct mbuf *m, struct sge_txq *q, unsigned int pidx, unsigned int gen, unsigned int ndesc, bus_dma_segment_t *segs, unsigned int nsegs) { unsigned int sgl_flits, flits; struct work_request_hdr *from; struct sg_ent *sgp, sgl[TX_MAX_SEGS / 2 + 1]; struct tx_desc *d = &q->desc[pidx]; struct txq_state txqs; if (immediate(m) && nsegs == 0) { write_imm(d, m, m->m_len, gen); return; } /* Only TX_DATA builds SGLs */ from = mtod(m, struct work_request_hdr *); memcpy(&d->flit[1], &from[1], m->m_len - sizeof(*from)); flits = m->m_len / 8; sgp = (ndesc == 1) ? (struct sg_ent *)&d->flit[flits] : sgl; make_sgl(sgp, segs, nsegs); sgl_flits = sgl_len(nsegs); txqs.gen = gen; txqs.pidx = pidx; txqs.compl = 0; write_wr_hdr_sgl(ndesc, d, &txqs, q, sgl, flits, sgl_flits, from->wr_hi, from->wr_lo); } /** * calc_tx_descs_ofld - calculate # of Tx descriptors for an offload packet * @m: the packet * * Returns the number of Tx descriptors needed for the given offload * packet. These packets are already fully constructed. */ static __inline unsigned int calc_tx_descs_ofld(struct mbuf *m, unsigned int nsegs) { unsigned int flits, cnt = 0; int ndescs; if (m->m_len <= WR_LEN && nsegs == 0) return (1); /* packet fits as immediate data */ if (m->m_flags & M_IOVEC) cnt = mtomv(m)->mv_count; else cnt = nsegs; /* headers */ flits = m->m_len / 8; ndescs = flits_to_desc(flits + sgl_len(cnt)); CTR4(KTR_CXGB, "flits=%d sgl_len=%d nsegs=%d ndescs=%d", flits, sgl_len(cnt), nsegs, ndescs); return (ndescs); } /** * ofld_xmit - send a packet through an offload queue * @adap: the adapter * @q: the Tx offload queue * @m: the packet * * Send an offload packet through an SGE offload queue. */ static int ofld_xmit(adapter_t *adap, struct sge_txq *q, struct mbuf *m) { int ret, nsegs; unsigned int ndesc; unsigned int pidx, gen; bus_dma_segment_t segs[TX_MAX_SEGS], *vsegs; struct tx_sw_desc *stx; nsegs = m_get_sgllen(m); vsegs = m_get_sgl(m); ndesc = calc_tx_descs_ofld(m, nsegs); busdma_map_sgl(vsegs, segs, nsegs); stx = &q->sdesc[q->pidx]; KASSERT(stx->mi.mi_base == NULL, ("mi_base set")); mtx_lock(&q->lock); again: reclaim_completed_tx_(q, 16); ret = check_desc_avail(adap, q, m, ndesc, TXQ_OFLD); if (__predict_false(ret)) { if (ret == 1) { printf("no ofld desc avail\n"); m_set_priority(m, ndesc); /* save for restart */ mtx_unlock(&q->lock); return (EINTR); } goto again; } gen = q->gen; q->in_use += ndesc; pidx = q->pidx; q->pidx += ndesc; if (q->pidx >= q->size) { q->pidx -= q->size; q->gen ^= 1; } #ifdef T3_TRACE T3_TRACE5(adap->tb[q->cntxt_id & 7], "ofld_xmit: ndesc %u, pidx %u, len %u, main %u, frags %u", ndesc, pidx, skb->len, skb->len - skb->data_len, skb_shinfo(skb)->nr_frags); #endif mtx_unlock(&q->lock); write_ofld_wr(adap, m, q, pidx, gen, ndesc, segs, nsegs); check_ring_tx_db(adap, q); return (0); } /** * restart_offloadq - restart a suspended offload queue * @qs: the queue set cotaining the offload queue * * Resumes transmission on a suspended Tx offload queue. */ static void restart_offloadq(void *data, int npending) { struct mbuf *m; struct sge_qset *qs = data; struct sge_txq *q = &qs->txq[TXQ_OFLD]; adapter_t *adap = qs->port->adapter; bus_dma_segment_t segs[TX_MAX_SEGS]; struct tx_sw_desc *stx = &q->sdesc[q->pidx]; int nsegs, cleaned; mtx_lock(&q->lock); again: cleaned = reclaim_completed_tx_(q, 16); while ((m = mbufq_peek(&q->sendq)) != NULL) { unsigned int gen, pidx; unsigned int ndesc = m_get_priority(m); if (__predict_false(q->size - q->in_use < ndesc)) { setbit(&qs->txq_stopped, TXQ_OFLD); smp_mb(); if (should_restart_tx(q) && test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped)) goto again; q->stops++; break; } gen = q->gen; q->in_use += ndesc; pidx = q->pidx; q->pidx += ndesc; if (q->pidx >= q->size) { q->pidx -= q->size; q->gen ^= 1; } (void)mbufq_dequeue(&q->sendq); busdma_map_mbufs(&m, q, stx, segs, &nsegs); mtx_unlock(&q->lock); write_ofld_wr(adap, m, q, pidx, gen, ndesc, segs, nsegs); mtx_lock(&q->lock); } mtx_unlock(&q->lock); #if USE_GTS set_bit(TXQ_RUNNING, &q->flags); set_bit(TXQ_LAST_PKT_DB, &q->flags); #endif wmb(); t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id)); } /** * queue_set - return the queue set a packet should use * @m: the packet * * Maps a packet to the SGE queue set it should use. The desired queue * set is carried in bits 1-3 in the packet's priority. */ static __inline int queue_set(const struct mbuf *m) { return m_get_priority(m) >> 1; } /** * is_ctrl_pkt - return whether an offload packet is a control packet * @m: the packet * * Determines whether an offload packet should use an OFLD or a CTRL * Tx queue. This is indicated by bit 0 in the packet's priority. */ static __inline int is_ctrl_pkt(const struct mbuf *m) { return m_get_priority(m) & 1; } /** * t3_offload_tx - send an offload packet * @tdev: the offload device to send to * @m: the packet * * Sends an offload packet. We use the packet priority to select the * appropriate Tx queue as follows: bit 0 indicates whether the packet * should be sent as regular or control, bits 1-3 select the queue set. */ int t3_offload_tx(struct t3cdev *tdev, struct mbuf *m) { adapter_t *adap = tdev2adap(tdev); struct sge_qset *qs = &adap->sge.qs[queue_set(m)]; if (__predict_false(is_ctrl_pkt(m))) return ctrl_xmit(adap, &qs->txq[TXQ_CTRL], m); return ofld_xmit(adap, &qs->txq[TXQ_OFLD], m); } /** * deliver_partial_bundle - deliver a (partial) bundle of Rx offload pkts * @tdev: the offload device that will be receiving the packets * @q: the SGE response queue that assembled the bundle * @m: the partial bundle * @n: the number of packets in the bundle * * Delivers a (partial) bundle of Rx offload packets to an offload device. */ static __inline void deliver_partial_bundle(struct t3cdev *tdev, struct sge_rspq *q, struct mbuf *mbufs[], int n) { if (n) { q->offload_bundles++; cxgb_ofld_recv(tdev, mbufs, n); } } static __inline int rx_offload(struct t3cdev *tdev, struct sge_rspq *rq, struct mbuf *m, struct mbuf *rx_gather[], unsigned int gather_idx) { rq->offload_pkts++; m->m_pkthdr.header = mtod(m, void *); rx_gather[gather_idx++] = m; if (gather_idx == RX_BUNDLE_SIZE) { cxgb_ofld_recv(tdev, rx_gather, RX_BUNDLE_SIZE); gather_idx = 0; rq->offload_bundles++; } return (gather_idx); } static void restart_tx(struct sge_qset *qs) { struct adapter *sc = qs->port->adapter; if (isset(&qs->txq_stopped, TXQ_OFLD) && should_restart_tx(&qs->txq[TXQ_OFLD]) && test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped)) { qs->txq[TXQ_OFLD].restarts++; DPRINTF("restarting TXQ_OFLD\n"); taskqueue_enqueue(sc->tq, &qs->txq[TXQ_OFLD].qresume_task); } DPRINTF("stopped=0x%x restart=%d processed=%d cleaned=%d in_use=%d\n", qs->txq_stopped, should_restart_tx(&qs->txq[TXQ_CTRL]), qs->txq[TXQ_CTRL].processed, qs->txq[TXQ_CTRL].cleaned, qs->txq[TXQ_CTRL].in_use); if (isset(&qs->txq_stopped, TXQ_CTRL) && should_restart_tx(&qs->txq[TXQ_CTRL]) && test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped)) { qs->txq[TXQ_CTRL].restarts++; DPRINTF("restarting TXQ_CTRL\n"); taskqueue_enqueue(sc->tq, &qs->txq[TXQ_CTRL].qresume_task); } } /** * t3_sge_alloc_qset - initialize an SGE queue set * @sc: the controller softc * @id: the queue set id * @nports: how many Ethernet ports will be using this queue set * @irq_vec_idx: the IRQ vector index for response queue interrupts * @p: configuration parameters for this queue set * @ntxq: number of Tx queues for the queue set * @pi: port info for queue set * * Allocate resources and initialize an SGE queue set. A queue set * comprises a response queue, two Rx free-buffer queues, and up to 3 * Tx queues. The Tx queues are assigned roles in the order Ethernet * queue, offload queue, and control queue. */ int t3_sge_alloc_qset(adapter_t *sc, u_int id, int nports, int irq_vec_idx, const struct qset_params *p, int ntxq, struct port_info *pi) { struct sge_qset *q = &sc->sge.qs[id]; int i, header_size, ret = 0; for (i = 0; i < SGE_TXQ_PER_SET; i++) { if ((q->txq[i].txq_mr.br_ring = malloc(cxgb_txq_buf_ring_size*sizeof(struct mbuf *), M_DEVBUF, M_WAITOK|M_ZERO)) == NULL) { device_printf(sc->dev, "failed to allocate mbuf ring\n"); goto err; } q->txq[i].txq_mr.br_prod = q->txq[i].txq_mr.br_cons = 0; q->txq[i].txq_mr.br_size = cxgb_txq_buf_ring_size; mtx_init(&q->txq[i].txq_mr.br_lock, "txq mbuf ring", NULL, MTX_DEF); } init_qset_cntxt(q, id); q->idx = id; if ((ret = alloc_ring(sc, p->fl_size, sizeof(struct rx_desc), sizeof(struct rx_sw_desc), &q->fl[0].phys_addr, &q->fl[0].desc, &q->fl[0].sdesc, &q->fl[0].desc_tag, &q->fl[0].desc_map, sc->rx_dmat, &q->fl[0].entry_tag)) != 0) { printf("error %d from alloc ring fl0\n", ret); goto err; } if ((ret = alloc_ring(sc, p->jumbo_size, sizeof(struct rx_desc), sizeof(struct rx_sw_desc), &q->fl[1].phys_addr, &q->fl[1].desc, &q->fl[1].sdesc, &q->fl[1].desc_tag, &q->fl[1].desc_map, sc->rx_jumbo_dmat, &q->fl[1].entry_tag)) != 0) { printf("error %d from alloc ring fl1\n", ret); goto err; } if ((ret = alloc_ring(sc, p->rspq_size, sizeof(struct rsp_desc), 0, &q->rspq.phys_addr, &q->rspq.desc, NULL, &q->rspq.desc_tag, &q->rspq.desc_map, NULL, NULL)) != 0) { printf("error %d from alloc ring rspq\n", ret); goto err; } for (i = 0; i < ntxq; ++i) { /* * The control queue always uses immediate data so does not * need to keep track of any mbufs. * XXX Placeholder for future TOE support. */ size_t sz = i == TXQ_CTRL ? 0 : sizeof(struct tx_sw_desc); if ((ret = alloc_ring(sc, p->txq_size[i], sizeof(struct tx_desc), sz, &q->txq[i].phys_addr, &q->txq[i].desc, &q->txq[i].sdesc, &q->txq[i].desc_tag, &q->txq[i].desc_map, sc->tx_dmat, &q->txq[i].entry_tag)) != 0) { printf("error %d from alloc ring tx %i\n", ret, i); goto err; } mbufq_init(&q->txq[i].sendq); q->txq[i].gen = 1; q->txq[i].size = p->txq_size[i]; snprintf(q->txq[i].lockbuf, TXQ_NAME_LEN, "t3 txq lock %d:%d:%d", device_get_unit(sc->dev), irq_vec_idx, i); MTX_INIT(&q->txq[i].lock, q->txq[i].lockbuf, NULL, MTX_DEF); } q->txq[TXQ_ETH].port = pi; TASK_INIT(&q->txq[TXQ_OFLD].qresume_task, 0, restart_offloadq, q); TASK_INIT(&q->txq[TXQ_CTRL].qresume_task, 0, restart_ctrlq, q); TASK_INIT(&q->txq[TXQ_ETH].qreclaim_task, 0, sge_txq_reclaim_handler, &q->txq[TXQ_ETH]); TASK_INIT(&q->txq[TXQ_OFLD].qreclaim_task, 0, sge_txq_reclaim_handler, &q->txq[TXQ_OFLD]); q->fl[0].gen = q->fl[1].gen = 1; q->fl[0].size = p->fl_size; q->fl[1].size = p->jumbo_size; q->rspq.gen = 1; q->rspq.cidx = 0; q->rspq.size = p->rspq_size; header_size = sizeof(struct m_hdr) + sizeof(struct pkthdr) + sizeof(struct m_ext_) + sizeof(uint32_t); q->txq[TXQ_ETH].stop_thres = nports * flits_to_desc(sgl_len(TX_MAX_SEGS + 1) + 3); q->fl[0].buf_size = (MCLBYTES - header_size); q->fl[0].zone = zone_clust; q->fl[0].type = EXT_CLUSTER; #if __FreeBSD_version >= 700111 if (cxgb_use_16k_clusters) { q->fl[1].buf_size = MJUM16BYTES - header_size; q->fl[1].zone = zone_jumbo16; q->fl[1].type = EXT_JUMBO16; } else { q->fl[1].buf_size = MJUM9BYTES - header_size; q->fl[1].zone = zone_jumbo9; q->fl[1].type = EXT_JUMBO9; } #else q->fl[1].buf_size = MJUMPAGESIZE - header_size; q->fl[1].zone = zone_jumbop; q->fl[1].type = EXT_JUMBOP; #endif /* * We allocate and setup the lro_ctrl structure irrespective of whether * lro is available and/or enabled. */ q->lro.enabled = !!(pi->ifp->if_capenable & IFCAP_LRO); ret = tcp_lro_init(&q->lro.ctrl); if (ret) { printf("error %d from tcp_lro_init\n", ret); goto err; } q->lro.ctrl.ifp = pi->ifp; mtx_lock_spin(&sc->sge.reg_lock); ret = -t3_sge_init_rspcntxt(sc, q->rspq.cntxt_id, irq_vec_idx, q->rspq.phys_addr, q->rspq.size, q->fl[0].buf_size, 1, 0); if (ret) { printf("error %d from t3_sge_init_rspcntxt\n", ret); goto err_unlock; } for (i = 0; i < SGE_RXQ_PER_SET; ++i) { ret = -t3_sge_init_flcntxt(sc, q->fl[i].cntxt_id, 0, q->fl[i].phys_addr, q->fl[i].size, q->fl[i].buf_size, p->cong_thres, 1, 0); if (ret) { printf("error %d from t3_sge_init_flcntxt for index i=%d\n", ret, i); goto err_unlock; } } ret = -t3_sge_init_ecntxt(sc, q->txq[TXQ_ETH].cntxt_id, USE_GTS, SGE_CNTXT_ETH, id, q->txq[TXQ_ETH].phys_addr, q->txq[TXQ_ETH].size, q->txq[TXQ_ETH].token, 1, 0); if (ret) { printf("error %d from t3_sge_init_ecntxt\n", ret); goto err_unlock; } if (ntxq > 1) { ret = -t3_sge_init_ecntxt(sc, q->txq[TXQ_OFLD].cntxt_id, USE_GTS, SGE_CNTXT_OFLD, id, q->txq[TXQ_OFLD].phys_addr, q->txq[TXQ_OFLD].size, 0, 1, 0); if (ret) { printf("error %d from t3_sge_init_ecntxt\n", ret); goto err_unlock; } } if (ntxq > 2) { ret = -t3_sge_init_ecntxt(sc, q->txq[TXQ_CTRL].cntxt_id, 0, SGE_CNTXT_CTRL, id, q->txq[TXQ_CTRL].phys_addr, q->txq[TXQ_CTRL].size, q->txq[TXQ_CTRL].token, 1, 0); if (ret) { printf("error %d from t3_sge_init_ecntxt\n", ret); goto err_unlock; } } snprintf(q->rspq.lockbuf, RSPQ_NAME_LEN, "t3 rspq lock %d:%d", device_get_unit(sc->dev), irq_vec_idx); MTX_INIT(&q->rspq.lock, q->rspq.lockbuf, NULL, MTX_DEF); mtx_unlock_spin(&sc->sge.reg_lock); t3_update_qset_coalesce(q, p); q->port = pi; refill_fl(sc, &q->fl[0], q->fl[0].size); refill_fl(sc, &q->fl[1], q->fl[1].size); refill_rspq(sc, &q->rspq, q->rspq.size - 1); t3_write_reg(sc, A_SG_GTS, V_RSPQ(q->rspq.cntxt_id) | V_NEWTIMER(q->rspq.holdoff_tmr)); return (0); err_unlock: mtx_unlock_spin(&sc->sge.reg_lock); err: t3_free_qset(sc, q); return (ret); } /* * Remove CPL_RX_PKT headers from the mbuf and reduce it to a regular mbuf with * ethernet data. Hardware assistance with various checksums and any vlan tag * will also be taken into account here. */ void t3_rx_eth(struct adapter *adap, struct sge_rspq *rq, struct mbuf *m, int ethpad) { struct cpl_rx_pkt *cpl = (struct cpl_rx_pkt *)(mtod(m, uint8_t *) + ethpad); struct port_info *pi = &adap->port[adap->rxpkt_map[cpl->iff]]; struct ifnet *ifp = pi->ifp; DPRINTF("rx_eth m=%p m->m_data=%p p->iff=%d\n", m, mtod(m, uint8_t *), cpl->iff); if ((ifp->if_capenable & IFCAP_RXCSUM) && !cpl->fragment && cpl->csum_valid && cpl->csum == 0xffff) { m->m_pkthdr.csum_flags = (CSUM_IP_CHECKED|CSUM_IP_VALID); rspq_to_qset(rq)->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++; m->m_pkthdr.csum_flags = (CSUM_IP_CHECKED|CSUM_IP_VALID|CSUM_DATA_VALID|CSUM_PSEUDO_HDR); m->m_pkthdr.csum_data = 0xffff; } /* * XXX need to add VLAN support for 6.x */ #ifdef VLAN_SUPPORTED if (__predict_false(cpl->vlan_valid)) { m->m_pkthdr.ether_vtag = ntohs(cpl->vlan); m->m_flags |= M_VLANTAG; } #endif m->m_pkthdr.rcvif = ifp; m->m_pkthdr.header = mtod(m, uint8_t *) + sizeof(*cpl) + ethpad; #ifndef DISABLE_MBUF_IOVEC m_explode(m); #endif /* * adjust after conversion to mbuf chain */ m->m_pkthdr.len -= (sizeof(*cpl) + ethpad); m->m_len -= (sizeof(*cpl) + ethpad); m->m_data += (sizeof(*cpl) + ethpad); } static void ext_free_handler(void *buf, void * args) { uintptr_t type = (uintptr_t)args; uma_zone_t zone; struct mbuf *m; m = buf; zone = m_getzonefromtype(type); m->m_ext.ext_type = (int)type; cxgb_ext_freed++; cxgb_cache_put(zone, m); } static void init_cluster_mbuf(caddr_t cl, int flags, int type, uma_zone_t zone) { struct mbuf *m; int header_size; header_size = sizeof(struct m_hdr) + sizeof(struct pkthdr) + sizeof(struct m_ext_) + sizeof(uint32_t); bzero(cl, header_size); m = (struct mbuf *)cl; cxgb_ext_inited++; SLIST_INIT(&m->m_pkthdr.tags); m->m_type = MT_DATA; m->m_flags = flags | M_NOFREE | M_EXT; m->m_data = cl + header_size; m->m_ext.ext_buf = cl; m->m_ext.ref_cnt = (uint32_t *)(cl + header_size - sizeof(uint32_t)); m->m_ext.ext_size = m_getsizefromtype(type); m->m_ext.ext_free = ext_free_handler; m->m_ext.ext_args = (void *)(uintptr_t)type; m->m_ext.ext_type = EXT_EXTREF; *(m->m_ext.ref_cnt) = 1; DPRINTF("data=%p ref_cnt=%p\n", m->m_data, m->m_ext.ref_cnt); } /** * get_packet - return the next ingress packet buffer from a free list * @adap: the adapter that received the packet * @drop_thres: # of remaining buffers before we start dropping packets * @qs: the qset that the SGE free list holding the packet belongs to * @mh: the mbuf header, contains a pointer to the head and tail of the mbuf chain * @r: response descriptor * * Get the next packet from a free list and complete setup of the * sk_buff. If the packet is small we make a copy and recycle the * original buffer, otherwise we use the original buffer itself. If a * positive drop threshold is supplied packets are dropped and their * buffers recycled if (a) the number of remaining buffers is under the * threshold and the packet is too big to copy, or (b) the packet should * be copied but there is no memory for the copy. */ #ifdef DISABLE_MBUF_IOVEC static int get_packet(adapter_t *adap, unsigned int drop_thres, struct sge_qset *qs, struct t3_mbuf_hdr *mh, struct rsp_desc *r) { unsigned int len_cq = ntohl(r->len_cq); struct sge_fl *fl = (len_cq & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0]; struct rx_sw_desc *sd = &fl->sdesc[fl->cidx]; uint32_t len = G_RSPD_LEN(len_cq); uint32_t flags = ntohl(r->flags); uint8_t sopeop = G_RSPD_SOP_EOP(flags); caddr_t cl; struct mbuf *m, *m0; int ret = 0; prefetch(sd->rxsd_cl); fl->credits--; bus_dmamap_sync(fl->entry_tag, sd->map, BUS_DMASYNC_POSTREAD); if (recycle_enable && len <= SGE_RX_COPY_THRES && sopeop == RSPQ_SOP_EOP) { if ((m0 = m_gethdr(M_DONTWAIT, MT_DATA)) == NULL) goto skip_recycle; cl = mtod(m0, void *); memcpy(cl, sd->data, len); recycle_rx_buf(adap, fl, fl->cidx); m = m0; m0->m_len = len; } else { skip_recycle: bus_dmamap_unload(fl->entry_tag, sd->map); cl = sd->rxsd_cl; m = m0 = (struct mbuf *)cl; if ((sopeop == RSPQ_SOP_EOP) || (sopeop == RSPQ_SOP)) flags = M_PKTHDR; init_cluster_mbuf(cl, flags, fl->type, fl->zone); m0->m_len = len; } switch(sopeop) { case RSPQ_SOP_EOP: DBG(DBG_RX, ("get_packet: SOP-EOP m %p\n", m)); mh->mh_head = mh->mh_tail = m; m->m_pkthdr.len = len; ret = 1; break; case RSPQ_NSOP_NEOP: DBG(DBG_RX, ("get_packet: NO_SOP-NO_EOP m %p\n", m)); if (mh->mh_tail == NULL) { log(LOG_ERR, "discarding intermediate descriptor entry\n"); m_freem(m); break; } mh->mh_tail->m_next = m; mh->mh_tail = m; mh->mh_head->m_pkthdr.len += len; ret = 0; break; case RSPQ_SOP: DBG(DBG_RX, ("get_packet: SOP m %p\n", m)); m->m_pkthdr.len = len; mh->mh_head = mh->mh_tail = m; ret = 0; break; case RSPQ_EOP: DBG(DBG_RX, ("get_packet: EOP m %p\n", m)); mh->mh_head->m_pkthdr.len += len; mh->mh_tail->m_next = m; mh->mh_tail = m; ret = 1; break; } if (++fl->cidx == fl->size) fl->cidx = 0; return (ret); } #else static int get_packet(adapter_t *adap, unsigned int drop_thres, struct sge_qset *qs, struct mbuf **m, struct rsp_desc *r) { unsigned int len_cq = ntohl(r->len_cq); struct sge_fl *fl = (len_cq & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0]; struct rx_sw_desc *sd = &fl->sdesc[fl->cidx]; uint32_t len = G_RSPD_LEN(len_cq); uint32_t flags = ntohl(r->flags); uint8_t sopeop = G_RSPD_SOP_EOP(flags); void *cl; int ret = 0; struct mbuf *m0; #if 0 if ((sd + 1 )->rxsd_cl) prefetch((sd + 1)->rxsd_cl); if ((sd + 2)->rxsd_cl) prefetch((sd + 2)->rxsd_cl); #endif DPRINTF("rx cpu=%d\n", curcpu); fl->credits--; bus_dmamap_sync(fl->entry_tag, sd->map, BUS_DMASYNC_POSTREAD); if (recycle_enable && len <= SGE_RX_COPY_THRES && sopeop == RSPQ_SOP_EOP) { if ((m0 = m_gethdr(M_DONTWAIT, MT_DATA)) == NULL) goto skip_recycle; cl = mtod(m0, void *); memcpy(cl, sd->data, len); recycle_rx_buf(adap, fl, fl->cidx); *m = m0; } else { skip_recycle: bus_dmamap_unload(fl->entry_tag, sd->map); cl = sd->rxsd_cl; *m = m0 = (struct mbuf *)cl; } switch(sopeop) { case RSPQ_SOP_EOP: DBG(DBG_RX, ("get_packet: SOP-EOP m %p\n", m)); if (cl == sd->rxsd_cl) init_cluster_mbuf(cl, M_PKTHDR, fl->type, fl->zone); m0->m_len = m0->m_pkthdr.len = len; ret = 1; goto done; break; case RSPQ_NSOP_NEOP: DBG(DBG_RX, ("get_packet: NO_SOP-NO_EOP m %p\n", m)); panic("chaining unsupported"); ret = 0; break; case RSPQ_SOP: DBG(DBG_RX, ("get_packet: SOP m %p\n", m)); panic("chaining unsupported"); m_iovinit(m0); ret = 0; break; case RSPQ_EOP: DBG(DBG_RX, ("get_packet: EOP m %p\n", m)); panic("chaining unsupported"); ret = 1; break; } panic("append not supported"); #if 0 m_iovappend(m0, cl, fl->buf_size, len, sizeof(uint32_t), sd->rxsd_ref); #endif done: if (++fl->cidx == fl->size) fl->cidx = 0; return (ret); } #endif /** * handle_rsp_cntrl_info - handles control information in a response * @qs: the queue set corresponding to the response * @flags: the response control flags * * Handles the control information of an SGE response, such as GTS * indications and completion credits for the queue set's Tx queues. * HW coalesces credits, we don't do any extra SW coalescing. */ static __inline void handle_rsp_cntrl_info(struct sge_qset *qs, uint32_t flags) { unsigned int credits; #if USE_GTS if (flags & F_RSPD_TXQ0_GTS) clear_bit(TXQ_RUNNING, &qs->txq[TXQ_ETH].flags); #endif credits = G_RSPD_TXQ0_CR(flags); if (credits) qs->txq[TXQ_ETH].processed += credits; credits = G_RSPD_TXQ2_CR(flags); if (credits) qs->txq[TXQ_CTRL].processed += credits; # if USE_GTS if (flags & F_RSPD_TXQ1_GTS) clear_bit(TXQ_RUNNING, &qs->txq[TXQ_OFLD].flags); # endif credits = G_RSPD_TXQ1_CR(flags); if (credits) qs->txq[TXQ_OFLD].processed += credits; } static void check_ring_db(adapter_t *adap, struct sge_qset *qs, unsigned int sleeping) { ; } /** * process_responses - process responses from an SGE response queue * @adap: the adapter * @qs: the queue set to which the response queue belongs * @budget: how many responses can be processed in this round * * Process responses from an SGE response queue up to the supplied budget. * Responses include received packets as well as credits and other events * for the queues that belong to the response queue's queue set. * A negative budget is effectively unlimited. * * Additionally choose the interrupt holdoff time for the next interrupt * on this queue. If the system is under memory shortage use a fairly * long delay to help recovery. */ int process_responses(adapter_t *adap, struct sge_qset *qs, int budget) { struct sge_rspq *rspq = &qs->rspq; struct rsp_desc *r = &rspq->desc[rspq->cidx]; int budget_left = budget; unsigned int sleeping = 0; int lro_enabled = qs->lro.enabled; int skip_lro; struct lro_ctrl *lro_ctrl = &qs->lro.ctrl; struct mbuf *offload_mbufs[RX_BUNDLE_SIZE]; int ngathered = 0; #ifdef DEBUG static int last_holdoff = 0; if (cxgb_debug && rspq->holdoff_tmr != last_holdoff) { printf("next_holdoff=%d\n", rspq->holdoff_tmr); last_holdoff = rspq->holdoff_tmr; } #endif rspq->next_holdoff = rspq->holdoff_tmr; while (__predict_true(budget_left && is_new_response(r, rspq))) { int eth, eop = 0, ethpad = 0; uint32_t flags = ntohl(r->flags); uint32_t rss_csum = *(const uint32_t *)r; uint32_t rss_hash = be32toh(r->rss_hdr.rss_hash_val); eth = (r->rss_hdr.opcode == CPL_RX_PKT); if (__predict_false(flags & F_RSPD_ASYNC_NOTIF)) { struct mbuf *m; if (cxgb_debug) printf("async notification\n"); if (rspq->rspq_mh.mh_head == NULL) { rspq->rspq_mh.mh_head = m_gethdr(M_DONTWAIT, MT_DATA); m = rspq->rspq_mh.mh_head; } else { m = m_gethdr(M_DONTWAIT, MT_DATA); } /* XXX m is lost here if rspq->rspq_mbuf is not NULL */ if (m == NULL) goto no_mem; memcpy(mtod(m, char *), r, AN_PKT_SIZE); m->m_len = m->m_pkthdr.len = AN_PKT_SIZE; *mtod(m, char *) = CPL_ASYNC_NOTIF; rss_csum = htonl(CPL_ASYNC_NOTIF << 24); eop = 1; rspq->async_notif++; goto skip; } else if (flags & F_RSPD_IMM_DATA_VALID) { struct mbuf *m = NULL; DPRINTF("IMM DATA VALID opcode=0x%x rspq->cidx=%d\n", r->rss_hdr.opcode, rspq->cidx); if (rspq->rspq_mh.mh_head == NULL) rspq->rspq_mh.mh_head = m_gethdr(M_DONTWAIT, MT_DATA); else m = m_gethdr(M_DONTWAIT, MT_DATA); if (rspq->rspq_mh.mh_head == NULL && m == NULL) { no_mem: rspq->next_holdoff = NOMEM_INTR_DELAY; budget_left--; break; } get_imm_packet(adap, r, rspq->rspq_mh.mh_head); eop = 1; rspq->imm_data++; } else if (r->len_cq) { int drop_thresh = eth ? SGE_RX_DROP_THRES : 0; #ifdef DISABLE_MBUF_IOVEC eop = get_packet(adap, drop_thresh, qs, &rspq->rspq_mh, r); #else eop = get_packet(adap, drop_thresh, qs, &rspq->rspq_mbuf, r); #endif #ifdef IFNET_MULTIQUEUE rspq->rspq_mh.mh_head->m_pkthdr.rss_hash = rss_hash; #endif ethpad = 2; } else { DPRINTF("pure response\n"); rspq->pure_rsps++; } skip: if (flags & RSPD_CTRL_MASK) { sleeping |= flags & RSPD_GTS_MASK; handle_rsp_cntrl_info(qs, flags); } r++; if (__predict_false(++rspq->cidx == rspq->size)) { rspq->cidx = 0; rspq->gen ^= 1; r = rspq->desc; } prefetch(r); if (++rspq->credits >= (rspq->size / 4)) { refill_rspq(adap, rspq, rspq->credits); rspq->credits = 0; } DPRINTF("eth=%d eop=%d flags=0x%x\n", eth, eop, flags); if (!eth && eop) { rspq->rspq_mh.mh_head->m_pkthdr.csum_data = rss_csum; /* * XXX size mismatch */ m_set_priority(rspq->rspq_mh.mh_head, rss_hash); ngathered = rx_offload(&adap->tdev, rspq, rspq->rspq_mh.mh_head, offload_mbufs, ngathered); rspq->rspq_mh.mh_head = NULL; DPRINTF("received offload packet\n"); } else if (eth && eop) { struct mbuf *m = rspq->rspq_mh.mh_head; prefetch(mtod(m, uint8_t *)); prefetch(mtod(m, uint8_t *) + L1_CACHE_BYTES); t3_rx_eth(adap, rspq, m, ethpad); /* * The T304 sends incoming packets on any qset. If LRO * is also enabled, we could end up sending packet up * lro_ctrl->ifp's input. That is incorrect. * * The mbuf's rcvif was derived from the cpl header and * is accurate. Skip LRO and just use that. */ skip_lro = __predict_false(qs->port->ifp != m->m_pkthdr.rcvif); if (lro_enabled && lro_ctrl->lro_cnt && !skip_lro && (tcp_lro_rx(lro_ctrl, m, 0) == 0)) { /* successfully queue'd for LRO */ } else { /* * LRO not enabled, packet unsuitable for LRO, * or unable to queue. Pass it up right now in * either case. */ struct ifnet *ifp = m->m_pkthdr.rcvif; (*ifp->if_input)(ifp, m); } DPRINTF("received tunnel packet\n"); rspq->rspq_mh.mh_head = NULL; } __refill_fl_lt(adap, &qs->fl[0], 32); __refill_fl_lt(adap, &qs->fl[1], 32); --budget_left; } deliver_partial_bundle(&adap->tdev, rspq, offload_mbufs, ngathered); /* Flush LRO */ while (!SLIST_EMPTY(&lro_ctrl->lro_active)) { struct lro_entry *queued = SLIST_FIRST(&lro_ctrl->lro_active); SLIST_REMOVE_HEAD(&lro_ctrl->lro_active, next); tcp_lro_flush(lro_ctrl, queued); } if (sleeping) check_ring_db(adap, qs, sleeping); smp_mb(); /* commit Tx queue processed updates */ if (__predict_false(qs->txq_stopped > 1)) restart_tx(qs); __refill_fl_lt(adap, &qs->fl[0], 512); __refill_fl_lt(adap, &qs->fl[1], 512); budget -= budget_left; return (budget); } /* * A helper function that processes responses and issues GTS. */ static __inline int process_responses_gts(adapter_t *adap, struct sge_rspq *rq) { int work; static int last_holdoff = 0; work = process_responses(adap, rspq_to_qset(rq), -1); if (cxgb_debug && (rq->next_holdoff != last_holdoff)) { printf("next_holdoff=%d\n", rq->next_holdoff); last_holdoff = rq->next_holdoff; } t3_write_reg(adap, A_SG_GTS, V_RSPQ(rq->cntxt_id) | V_NEWTIMER(rq->next_holdoff) | V_NEWINDEX(rq->cidx)); return (work); } /* * Interrupt handler for legacy INTx interrupts for T3B-based cards. * Handles data events from SGE response queues as well as error and other * async events as they all use the same interrupt pin. We use one SGE * response queue per port in this mode and protect all response queues with * queue 0's lock. */ void t3b_intr(void *data) { uint32_t i, map; adapter_t *adap = data; struct sge_rspq *q0 = &adap->sge.qs[0].rspq; t3_write_reg(adap, A_PL_CLI, 0); map = t3_read_reg(adap, A_SG_DATA_INTR); if (!map) return; if (__predict_false(map & F_ERRINTR)) { t3_write_reg(adap, A_PL_INT_ENABLE0, 0); (void) t3_read_reg(adap, A_PL_INT_ENABLE0); taskqueue_enqueue(adap->tq, &adap->slow_intr_task); } mtx_lock(&q0->lock); for_each_port(adap, i) if (map & (1 << i)) process_responses_gts(adap, &adap->sge.qs[i].rspq); mtx_unlock(&q0->lock); } /* * The MSI interrupt handler. This needs to handle data events from SGE * response queues as well as error and other async events as they all use * the same MSI vector. We use one SGE response queue per port in this mode * and protect all response queues with queue 0's lock. */ void t3_intr_msi(void *data) { adapter_t *adap = data; struct sge_rspq *q0 = &adap->sge.qs[0].rspq; int i, new_packets = 0; mtx_lock(&q0->lock); for_each_port(adap, i) if (process_responses_gts(adap, &adap->sge.qs[i].rspq)) new_packets = 1; mtx_unlock(&q0->lock); if (new_packets == 0) { t3_write_reg(adap, A_PL_INT_ENABLE0, 0); (void) t3_read_reg(adap, A_PL_INT_ENABLE0); taskqueue_enqueue(adap->tq, &adap->slow_intr_task); } } void t3_intr_msix(void *data) { struct sge_qset *qs = data; adapter_t *adap = qs->port->adapter; struct sge_rspq *rspq = &qs->rspq; #ifndef IFNET_MULTIQUEUE mtx_lock(&rspq->lock); #else if (mtx_trylock(&rspq->lock)) #endif { if (process_responses_gts(adap, rspq) == 0) rspq->unhandled_irqs++; mtx_unlock(&rspq->lock); } } #define QDUMP_SBUF_SIZE 32 * 400 static int t3_dump_rspq(SYSCTL_HANDLER_ARGS) { struct sge_rspq *rspq; struct sge_qset *qs; int i, err, dump_end, idx; static int multiplier = 1; struct sbuf *sb; struct rsp_desc *rspd; uint32_t data[4]; rspq = arg1; qs = rspq_to_qset(rspq); if (rspq->rspq_dump_count == 0) return (0); if (rspq->rspq_dump_count > RSPQ_Q_SIZE) { log(LOG_WARNING, "dump count is too large %d\n", rspq->rspq_dump_count); rspq->rspq_dump_count = 0; return (EINVAL); } if (rspq->rspq_dump_start > (RSPQ_Q_SIZE-1)) { log(LOG_WARNING, "dump start of %d is greater than queue size\n", rspq->rspq_dump_start); rspq->rspq_dump_start = 0; return (EINVAL); } err = t3_sge_read_rspq(qs->port->adapter, rspq->cntxt_id, data); if (err) return (err); retry_sbufops: sb = sbuf_new(NULL, NULL, QDUMP_SBUF_SIZE*multiplier, SBUF_FIXEDLEN); sbuf_printf(sb, " \n index=%u size=%u MSI-X/RspQ=%u intr enable=%u intr armed=%u\n", (data[0] & 0xffff), data[0] >> 16, ((data[2] >> 20) & 0x3f), ((data[2] >> 26) & 1), ((data[2] >> 27) & 1)); sbuf_printf(sb, " generation=%u CQ mode=%u FL threshold=%u\n", ((data[2] >> 28) & 1), ((data[2] >> 31) & 1), data[3]); sbuf_printf(sb, " start=%d -> end=%d\n", rspq->rspq_dump_start, (rspq->rspq_dump_start + rspq->rspq_dump_count) & (RSPQ_Q_SIZE-1)); dump_end = rspq->rspq_dump_start + rspq->rspq_dump_count; for (i = rspq->rspq_dump_start; i < dump_end; i++) { idx = i & (RSPQ_Q_SIZE-1); rspd = &rspq->desc[idx]; sbuf_printf(sb, "\tidx=%04d opcode=%02x cpu_idx=%x hash_type=%x cq_idx=%x\n", idx, rspd->rss_hdr.opcode, rspd->rss_hdr.cpu_idx, rspd->rss_hdr.hash_type, be16toh(rspd->rss_hdr.cq_idx)); sbuf_printf(sb, "\trss_hash_val=%x flags=%08x len_cq=%x intr_gen=%x\n", rspd->rss_hdr.rss_hash_val, be32toh(rspd->flags), be32toh(rspd->len_cq), rspd->intr_gen); } if (sbuf_overflowed(sb)) { sbuf_delete(sb); multiplier++; goto retry_sbufops; } sbuf_finish(sb); err = SYSCTL_OUT(req, sbuf_data(sb), sbuf_len(sb) + 1); sbuf_delete(sb); return (err); } static int t3_dump_txq_eth(SYSCTL_HANDLER_ARGS) { struct sge_txq *txq; struct sge_qset *qs; int i, j, err, dump_end; static int multiplier = 1; struct sbuf *sb; struct tx_desc *txd; uint32_t *WR, wr_hi, wr_lo, gen; uint32_t data[4]; txq = arg1; qs = txq_to_qset(txq, TXQ_ETH); if (txq->txq_dump_count == 0) { return (0); } if (txq->txq_dump_count > TX_ETH_Q_SIZE) { log(LOG_WARNING, "dump count is too large %d\n", txq->txq_dump_count); txq->txq_dump_count = 1; return (EINVAL); } if (txq->txq_dump_start > (TX_ETH_Q_SIZE-1)) { log(LOG_WARNING, "dump start of %d is greater than queue size\n", txq->txq_dump_start); txq->txq_dump_start = 0; return (EINVAL); } err = t3_sge_read_ecntxt(qs->port->adapter, qs->rspq.cntxt_id, data); if (err) return (err); retry_sbufops: sb = sbuf_new(NULL, NULL, QDUMP_SBUF_SIZE*multiplier, SBUF_FIXEDLEN); sbuf_printf(sb, " \n credits=%u GTS=%u index=%u size=%u rspq#=%u cmdq#=%u\n", (data[0] & 0x7fff), ((data[0] >> 15) & 1), (data[0] >> 16), (data[1] & 0xffff), ((data[3] >> 4) & 7), ((data[3] >> 7) & 1)); sbuf_printf(sb, " TUN=%u TOE=%u generation%u uP token=%u valid=%u\n", ((data[3] >> 8) & 1), ((data[3] >> 9) & 1), ((data[3] >> 10) & 1), ((data[3] >> 11) & 0xfffff), ((data[3] >> 31) & 1)); sbuf_printf(sb, " qid=%d start=%d -> end=%d\n", qs->idx, txq->txq_dump_start, (txq->txq_dump_start + txq->txq_dump_count) & (TX_ETH_Q_SIZE-1)); dump_end = txq->txq_dump_start + txq->txq_dump_count; for (i = txq->txq_dump_start; i < dump_end; i++) { txd = &txq->desc[i & (TX_ETH_Q_SIZE-1)]; WR = (uint32_t *)txd->flit; wr_hi = ntohl(WR[0]); wr_lo = ntohl(WR[1]); gen = G_WR_GEN(wr_lo); sbuf_printf(sb," wr_hi %08x wr_lo %08x gen %d\n", wr_hi, wr_lo, gen); for (j = 2; j < 30; j += 4) sbuf_printf(sb, "\t%08x %08x %08x %08x \n", WR[j], WR[j + 1], WR[j + 2], WR[j + 3]); } if (sbuf_overflowed(sb)) { sbuf_delete(sb); multiplier++; goto retry_sbufops; } sbuf_finish(sb); err = SYSCTL_OUT(req, sbuf_data(sb), sbuf_len(sb) + 1); sbuf_delete(sb); return (err); } static int t3_dump_txq_ctrl(SYSCTL_HANDLER_ARGS) { struct sge_txq *txq; struct sge_qset *qs; int i, j, err, dump_end; static int multiplier = 1; struct sbuf *sb; struct tx_desc *txd; uint32_t *WR, wr_hi, wr_lo, gen; txq = arg1; qs = txq_to_qset(txq, TXQ_CTRL); if (txq->txq_dump_count == 0) { return (0); } if (txq->txq_dump_count > 256) { log(LOG_WARNING, "dump count is too large %d\n", txq->txq_dump_count); txq->txq_dump_count = 1; return (EINVAL); } if (txq->txq_dump_start > 255) { log(LOG_WARNING, "dump start of %d is greater than queue size\n", txq->txq_dump_start); txq->txq_dump_start = 0; return (EINVAL); } retry_sbufops: sb = sbuf_new(NULL, NULL, QDUMP_SBUF_SIZE*multiplier, SBUF_FIXEDLEN); sbuf_printf(sb, " qid=%d start=%d -> end=%d\n", qs->idx, txq->txq_dump_start, (txq->txq_dump_start + txq->txq_dump_count) & 255); dump_end = txq->txq_dump_start + txq->txq_dump_count; for (i = txq->txq_dump_start; i < dump_end; i++) { txd = &txq->desc[i & (255)]; WR = (uint32_t *)txd->flit; wr_hi = ntohl(WR[0]); wr_lo = ntohl(WR[1]); gen = G_WR_GEN(wr_lo); sbuf_printf(sb," wr_hi %08x wr_lo %08x gen %d\n", wr_hi, wr_lo, gen); for (j = 2; j < 30; j += 4) sbuf_printf(sb, "\t%08x %08x %08x %08x \n", WR[j], WR[j + 1], WR[j + 2], WR[j + 3]); } if (sbuf_overflowed(sb)) { sbuf_delete(sb); multiplier++; goto retry_sbufops; } sbuf_finish(sb); err = SYSCTL_OUT(req, sbuf_data(sb), sbuf_len(sb) + 1); sbuf_delete(sb); return (err); } static int t3_set_coalesce_usecs(SYSCTL_HANDLER_ARGS) { adapter_t *sc = arg1; struct qset_params *qsp = &sc->params.sge.qset[0]; int coalesce_usecs; struct sge_qset *qs; int i, j, err, nqsets = 0; struct mtx *lock; if ((sc->flags & FULL_INIT_DONE) == 0) return (ENXIO); coalesce_usecs = qsp->coalesce_usecs; err = sysctl_handle_int(oidp, &coalesce_usecs, arg2, req); if (err != 0) { return (err); } if (coalesce_usecs == qsp->coalesce_usecs) return (0); for (i = 0; i < sc->params.nports; i++) for (j = 0; j < sc->port[i].nqsets; j++) nqsets++; coalesce_usecs = max(1, coalesce_usecs); for (i = 0; i < nqsets; i++) { qs = &sc->sge.qs[i]; qsp = &sc->params.sge.qset[i]; qsp->coalesce_usecs = coalesce_usecs; lock = (sc->flags & USING_MSIX) ? &qs->rspq.lock : &sc->sge.qs[0].rspq.lock; mtx_lock(lock); t3_update_qset_coalesce(qs, qsp); t3_write_reg(sc, A_SG_GTS, V_RSPQ(qs->rspq.cntxt_id) | V_NEWTIMER(qs->rspq.holdoff_tmr)); mtx_unlock(lock); } return (0); } void t3_add_attach_sysctls(adapter_t *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid_list *children; ctx = device_get_sysctl_ctx(sc->dev); children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); /* random information */ SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", CTLFLAG_RD, &sc->fw_version, 0, "firmware version"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, &sc->params.rev, 0, "chip model"); SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "port_types", CTLFLAG_RD, &sc->port_types, 0, "type of ports"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "enable_debug", CTLFLAG_RW, &cxgb_debug, 0, "enable verbose debugging output"); SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tunq_coalesce", CTLFLAG_RD, &sc->tunq_coalesce, "#tunneled packets freed"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "txq_overrun", CTLFLAG_RD, &txq_fills, 0, "#times txq overrun"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcpu_cache_enable", CTLFLAG_RW, &cxgb_pcpu_cache_enable, 0, "#enable driver local pcpu caches"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cache_alloc", CTLFLAG_RD, &cxgb_cached_allocations, 0, "#times a cluster was allocated from cache"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cached", CTLFLAG_RD, &cxgb_cached, 0, "#times a cluster was cached"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ext_freed", CTLFLAG_RD, &cxgb_ext_freed, 0, "#times a cluster was freed through ext_free"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ext_inited", CTLFLAG_RD, &cxgb_ext_inited, 0, "#times a cluster was initialized for ext_free"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mbufs_outstanding", CTLFLAG_RD, &cxgb_mbufs_outstanding, 0, "#mbufs in flight in the driver"); SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pack_outstanding", CTLFLAG_RD, &cxgb_pack_outstanding, 0, "#packet in flight in the driver"); } static const char *rspq_name = "rspq"; static const char *txq_names[] = { "txq_eth", "txq_ofld", "txq_ctrl" }; static int sysctl_handle_macstat(SYSCTL_HANDLER_ARGS) { struct port_info *p = arg1; uint64_t *parg; if (!p) return (EINVAL); parg = (uint64_t *) ((uint8_t *)&p->mac.stats + arg2); PORT_LOCK(p); t3_mac_update_stats(&p->mac); PORT_UNLOCK(p); return (sysctl_handle_quad(oidp, parg, 0, req)); } void t3_add_configured_sysctls(adapter_t *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid_list *children; int i, j; ctx = device_get_sysctl_ctx(sc->dev); children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal", CTLTYPE_INT|CTLFLAG_RW, sc, 0, t3_set_coalesce_usecs, "I", "interrupt coalescing timer (us)"); for (i = 0; i < sc->params.nports; i++) { struct port_info *pi = &sc->port[i]; struct sysctl_oid *poid; struct sysctl_oid_list *poidlist; struct mac_stats *mstats = &pi->mac.stats; snprintf(pi->namebuf, PORT_NAME_LEN, "port%d", i); poid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, pi->namebuf, CTLFLAG_RD, NULL, "port statistics"); poidlist = SYSCTL_CHILDREN(poid); SYSCTL_ADD_INT(ctx, poidlist, OID_AUTO, "nqsets", CTLFLAG_RD, &pi->nqsets, 0, "#queue sets"); for (j = 0; j < pi->nqsets; j++) { struct sge_qset *qs = &sc->sge.qs[pi->first_qset + j]; struct sysctl_oid *qspoid, *rspqpoid, *txqpoid, *ctrlqpoid, *lropoid; struct sysctl_oid_list *qspoidlist, *rspqpoidlist, *txqpoidlist, *ctrlqpoidlist, *lropoidlist; struct sge_txq *txq = &qs->txq[TXQ_ETH]; snprintf(qs->namebuf, QS_NAME_LEN, "qs%d", j); qspoid = SYSCTL_ADD_NODE(ctx, poidlist, OID_AUTO, qs->namebuf, CTLFLAG_RD, NULL, "qset statistics"); qspoidlist = SYSCTL_CHILDREN(qspoid); SYSCTL_ADD_UINT(ctx, qspoidlist, OID_AUTO, "fl0_empty", CTLFLAG_RD, &qs->fl[0].empty, 0, "freelist #0 empty"); SYSCTL_ADD_UINT(ctx, qspoidlist, OID_AUTO, "fl1_empty", CTLFLAG_RD, &qs->fl[1].empty, 0, "freelist #1 empty"); rspqpoid = SYSCTL_ADD_NODE(ctx, qspoidlist, OID_AUTO, rspq_name, CTLFLAG_RD, NULL, "rspq statistics"); rspqpoidlist = SYSCTL_CHILDREN(rspqpoid); txqpoid = SYSCTL_ADD_NODE(ctx, qspoidlist, OID_AUTO, txq_names[0], CTLFLAG_RD, NULL, "txq statistics"); txqpoidlist = SYSCTL_CHILDREN(txqpoid); ctrlqpoid = SYSCTL_ADD_NODE(ctx, qspoidlist, OID_AUTO, txq_names[2], CTLFLAG_RD, NULL, "ctrlq statistics"); ctrlqpoidlist = SYSCTL_CHILDREN(ctrlqpoid); lropoid = SYSCTL_ADD_NODE(ctx, qspoidlist, OID_AUTO, "lro_stats", CTLFLAG_RD, NULL, "LRO statistics"); lropoidlist = SYSCTL_CHILDREN(lropoid); SYSCTL_ADD_UINT(ctx, rspqpoidlist, OID_AUTO, "size", CTLFLAG_RD, &qs->rspq.size, 0, "#entries in response queue"); SYSCTL_ADD_UINT(ctx, rspqpoidlist, OID_AUTO, "cidx", CTLFLAG_RD, &qs->rspq.cidx, 0, "consumer index"); SYSCTL_ADD_UINT(ctx, rspqpoidlist, OID_AUTO, "credits", CTLFLAG_RD, &qs->rspq.credits, 0, "#credits"); SYSCTL_ADD_UINT(ctx, rspqpoidlist, OID_AUTO, "starved", CTLFLAG_RD, &qs->rspq.starved, 0, "#times starved"); SYSCTL_ADD_XLONG(ctx, rspqpoidlist, OID_AUTO, "phys_addr", CTLFLAG_RD, &qs->rspq.phys_addr, "physical_address_of the queue"); SYSCTL_ADD_UINT(ctx, rspqpoidlist, OID_AUTO, "dump_start", CTLFLAG_RW, &qs->rspq.rspq_dump_start, 0, "start rspq dump entry"); SYSCTL_ADD_UINT(ctx, rspqpoidlist, OID_AUTO, "dump_count", CTLFLAG_RW, &qs->rspq.rspq_dump_count, 0, "#rspq entries to dump"); SYSCTL_ADD_PROC(ctx, rspqpoidlist, OID_AUTO, "qdump", CTLTYPE_STRING | CTLFLAG_RD, &qs->rspq, 0, t3_dump_rspq, "A", "dump of the response queue"); SYSCTL_ADD_INT(ctx, txqpoidlist, OID_AUTO, "dropped", CTLFLAG_RD, &qs->txq[TXQ_ETH].txq_drops, 0, "#tunneled packets dropped"); SYSCTL_ADD_INT(ctx, txqpoidlist, OID_AUTO, "sendqlen", CTLFLAG_RD, &qs->txq[TXQ_ETH].sendq.qlen, 0, "#tunneled packets waiting to be sent"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "queue_pidx", CTLFLAG_RD, (uint32_t *)(uintptr_t)&qs->txq[TXQ_ETH].txq_mr.br_prod, 0, "#tunneled packets queue producer index"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "queue_cidx", CTLFLAG_RD, (uint32_t *)(uintptr_t)&qs->txq[TXQ_ETH].txq_mr.br_cons, 0, "#tunneled packets queue consumer index"); SYSCTL_ADD_INT(ctx, txqpoidlist, OID_AUTO, "processed", CTLFLAG_RD, &qs->txq[TXQ_ETH].processed, 0, "#tunneled packets processed by the card"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "cleaned", CTLFLAG_RD, &txq->cleaned, 0, "#tunneled packets cleaned"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "in_use", CTLFLAG_RD, &txq->in_use, 0, "#tunneled packet slots in use"); SYSCTL_ADD_ULONG(ctx, txqpoidlist, OID_AUTO, "frees", CTLFLAG_RD, &txq->txq_frees, "#tunneled packets freed"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "skipped", CTLFLAG_RD, &txq->txq_skipped, 0, "#tunneled packet descriptors skipped"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "coalesced", CTLFLAG_RD, &txq->txq_coalesced, 0, "#tunneled packets coalesced"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "enqueued", CTLFLAG_RD, &txq->txq_enqueued, 0, "#tunneled packets enqueued to hardware"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "stopped_flags", CTLFLAG_RD, &qs->txq_stopped, 0, "tx queues stopped"); SYSCTL_ADD_XLONG(ctx, txqpoidlist, OID_AUTO, "phys_addr", CTLFLAG_RD, &txq->phys_addr, "physical_address_of the queue"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "qgen", CTLFLAG_RW, &qs->txq[TXQ_ETH].gen, 0, "txq generation"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "hw_cidx", CTLFLAG_RD, &txq->cidx, 0, "hardware queue cidx"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "hw_pidx", CTLFLAG_RD, &txq->pidx, 0, "hardware queue pidx"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "dump_start", CTLFLAG_RW, &qs->txq[TXQ_ETH].txq_dump_start, 0, "txq start idx for dump"); SYSCTL_ADD_UINT(ctx, txqpoidlist, OID_AUTO, "dump_count", CTLFLAG_RW, &qs->txq[TXQ_ETH].txq_dump_count, 0, "txq #entries to dump"); SYSCTL_ADD_PROC(ctx, txqpoidlist, OID_AUTO, "qdump", CTLTYPE_STRING | CTLFLAG_RD, &qs->txq[TXQ_ETH], 0, t3_dump_txq_eth, "A", "dump of the transmit queue"); SYSCTL_ADD_UINT(ctx, ctrlqpoidlist, OID_AUTO, "dump_start", CTLFLAG_RW, &qs->txq[TXQ_CTRL].txq_dump_start, 0, "ctrlq start idx for dump"); SYSCTL_ADD_UINT(ctx, ctrlqpoidlist, OID_AUTO, "dump_count", CTLFLAG_RW, &qs->txq[TXQ_CTRL].txq_dump_count, 0, "ctrl #entries to dump"); SYSCTL_ADD_PROC(ctx, ctrlqpoidlist, OID_AUTO, "qdump", CTLTYPE_STRING | CTLFLAG_RD, &qs->txq[TXQ_CTRL], 0, t3_dump_txq_ctrl, "A", "dump of the transmit queue"); SYSCTL_ADD_INT(ctx, lropoidlist, OID_AUTO, "lro_queued", CTLFLAG_RD, &qs->lro.ctrl.lro_queued, 0, NULL); SYSCTL_ADD_INT(ctx, lropoidlist, OID_AUTO, "lro_flushed", CTLFLAG_RD, &qs->lro.ctrl.lro_flushed, 0, NULL); SYSCTL_ADD_INT(ctx, lropoidlist, OID_AUTO, "lro_bad_csum", CTLFLAG_RD, &qs->lro.ctrl.lro_bad_csum, 0, NULL); SYSCTL_ADD_INT(ctx, lropoidlist, OID_AUTO, "lro_cnt", CTLFLAG_RD, &qs->lro.ctrl.lro_cnt, 0, NULL); } /* Now add a node for mac stats. */ poid = SYSCTL_ADD_NODE(ctx, poidlist, OID_AUTO, "mac_stats", CTLFLAG_RD, NULL, "MAC statistics"); poidlist = SYSCTL_CHILDREN(poid); /* * We (ab)use the length argument (arg2) to pass on the offset * of the data that we are interested in. This is only required * for the quad counters that are updated from the hardware (we * make sure that we return the latest value). * sysctl_handle_macstat first updates *all* the counters from * the hardware, and then returns the latest value of the * requested counter. Best would be to update only the * requested counter from hardware, but t3_mac_update_stats() * hides all the register details and we don't want to dive into * all that here. */ #define CXGB_SYSCTL_ADD_QUAD(a) SYSCTL_ADD_OID(ctx, poidlist, OID_AUTO, #a, \ (CTLTYPE_QUAD | CTLFLAG_RD), pi, offsetof(struct mac_stats, a), \ sysctl_handle_macstat, "QU", 0) CXGB_SYSCTL_ADD_QUAD(tx_octets); CXGB_SYSCTL_ADD_QUAD(tx_octets_bad); CXGB_SYSCTL_ADD_QUAD(tx_frames); CXGB_SYSCTL_ADD_QUAD(tx_mcast_frames); CXGB_SYSCTL_ADD_QUAD(tx_bcast_frames); CXGB_SYSCTL_ADD_QUAD(tx_pause); CXGB_SYSCTL_ADD_QUAD(tx_deferred); CXGB_SYSCTL_ADD_QUAD(tx_late_collisions); CXGB_SYSCTL_ADD_QUAD(tx_total_collisions); CXGB_SYSCTL_ADD_QUAD(tx_excess_collisions); CXGB_SYSCTL_ADD_QUAD(tx_underrun); CXGB_SYSCTL_ADD_QUAD(tx_len_errs); CXGB_SYSCTL_ADD_QUAD(tx_mac_internal_errs); CXGB_SYSCTL_ADD_QUAD(tx_excess_deferral); CXGB_SYSCTL_ADD_QUAD(tx_fcs_errs); CXGB_SYSCTL_ADD_QUAD(tx_frames_64); CXGB_SYSCTL_ADD_QUAD(tx_frames_65_127); CXGB_SYSCTL_ADD_QUAD(tx_frames_128_255); CXGB_SYSCTL_ADD_QUAD(tx_frames_256_511); CXGB_SYSCTL_ADD_QUAD(tx_frames_512_1023); CXGB_SYSCTL_ADD_QUAD(tx_frames_1024_1518); CXGB_SYSCTL_ADD_QUAD(tx_frames_1519_max); CXGB_SYSCTL_ADD_QUAD(rx_octets); CXGB_SYSCTL_ADD_QUAD(rx_octets_bad); CXGB_SYSCTL_ADD_QUAD(rx_frames); CXGB_SYSCTL_ADD_QUAD(rx_mcast_frames); CXGB_SYSCTL_ADD_QUAD(rx_bcast_frames); CXGB_SYSCTL_ADD_QUAD(rx_pause); CXGB_SYSCTL_ADD_QUAD(rx_fcs_errs); CXGB_SYSCTL_ADD_QUAD(rx_align_errs); CXGB_SYSCTL_ADD_QUAD(rx_symbol_errs); CXGB_SYSCTL_ADD_QUAD(rx_data_errs); CXGB_SYSCTL_ADD_QUAD(rx_sequence_errs); CXGB_SYSCTL_ADD_QUAD(rx_runt); CXGB_SYSCTL_ADD_QUAD(rx_jabber); CXGB_SYSCTL_ADD_QUAD(rx_short); CXGB_SYSCTL_ADD_QUAD(rx_too_long); CXGB_SYSCTL_ADD_QUAD(rx_mac_internal_errs); CXGB_SYSCTL_ADD_QUAD(rx_cong_drops); CXGB_SYSCTL_ADD_QUAD(rx_frames_64); CXGB_SYSCTL_ADD_QUAD(rx_frames_65_127); CXGB_SYSCTL_ADD_QUAD(rx_frames_128_255); CXGB_SYSCTL_ADD_QUAD(rx_frames_256_511); CXGB_SYSCTL_ADD_QUAD(rx_frames_512_1023); CXGB_SYSCTL_ADD_QUAD(rx_frames_1024_1518); CXGB_SYSCTL_ADD_QUAD(rx_frames_1519_max); #undef CXGB_SYSCTL_ADD_QUAD #define CXGB_SYSCTL_ADD_ULONG(a) SYSCTL_ADD_ULONG(ctx, poidlist, OID_AUTO, #a, \ CTLFLAG_RD, &mstats->a, 0) CXGB_SYSCTL_ADD_ULONG(tx_fifo_parity_err); CXGB_SYSCTL_ADD_ULONG(rx_fifo_parity_err); CXGB_SYSCTL_ADD_ULONG(tx_fifo_urun); CXGB_SYSCTL_ADD_ULONG(rx_fifo_ovfl); CXGB_SYSCTL_ADD_ULONG(serdes_signal_loss); CXGB_SYSCTL_ADD_ULONG(xaui_pcs_ctc_err); CXGB_SYSCTL_ADD_ULONG(xaui_pcs_align_change); CXGB_SYSCTL_ADD_ULONG(num_toggled); CXGB_SYSCTL_ADD_ULONG(num_resets); CXGB_SYSCTL_ADD_ULONG(link_faults); #undef CXGB_SYSCTL_ADD_ULONG } } /** * t3_get_desc - dump an SGE descriptor for debugging purposes * @qs: the queue set * @qnum: identifies the specific queue (0..2: Tx, 3:response, 4..5: Rx) * @idx: the descriptor index in the queue * @data: where to dump the descriptor contents * * Dumps the contents of a HW descriptor of an SGE queue. Returns the * size of the descriptor. */ int t3_get_desc(const struct sge_qset *qs, unsigned int qnum, unsigned int idx, unsigned char *data) { if (qnum >= 6) return (EINVAL); if (qnum < 3) { if (!qs->txq[qnum].desc || idx >= qs->txq[qnum].size) return -EINVAL; memcpy(data, &qs->txq[qnum].desc[idx], sizeof(struct tx_desc)); return sizeof(struct tx_desc); } if (qnum == 3) { if (!qs->rspq.desc || idx >= qs->rspq.size) return (EINVAL); memcpy(data, &qs->rspq.desc[idx], sizeof(struct rsp_desc)); return sizeof(struct rsp_desc); } qnum -= 4; if (!qs->fl[qnum].desc || idx >= qs->fl[qnum].size) return (EINVAL); memcpy(data, &qs->fl[qnum].desc[idx], sizeof(struct rx_desc)); return sizeof(struct rx_desc); } Index: stable/7/sys/dev/cxgb/cxgb_t3fw.h =================================================================== --- stable/7/sys/dev/cxgb/cxgb_t3fw.h (revision 220340) +++ stable/7/sys/dev/cxgb/cxgb_t3fw.h (revision 220341) @@ -1,7747 +1,7781 @@ /************************************************************************** Copyright (c) 2007-2009, Chelsio Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Neither the name of the Chelsio Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN22 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. $FreeBSD$ ***************************************************************************/ #define U (unsigned char) -static unsigned int t3fw_length = 30840; -static unsigned char t3fw[30840] = { +static unsigned int t3fw_length = 30976; +static unsigned char t3fw[30976] = { U 0x60, U 0x00, U 0x74, U 0x00, U 0x20, U 0x03, U 0x80, U 0x00, U 0x20, U 0x03, U 0x70, U 0x00, U 0x00, U 0x00, U 0x10, U 0x00, U 0x00, U 0x00, U 0x20, U 0x00, U 0xE1, U 0x00, U 0x02, U 0x84, U 0x00, U 0x07, U 0x00, U 0x00, U 0xE1, U 0x00, U 0x02, U 0x88, U 0x00, U 0x01, U 0x00, U 0x00, U 0xE0, U 0x00, U 0x00, U 0x00, U 0xE0, U 0x00, U 0x00, U 0xA0, U 0x01, U 0x00, U 0x00, U 0x00, U 0x44, U 0x44, U 0x44, U 0x40, U 0xE3, U 0x00, U 0x01, U 0x83, U 0x20, U 0x02, U 0x00, U 0x00, U 0x20, U 0x01, U 0xE0, U 0x00, U 0x20, U 0x01, U 0xFF, U 0x10, U 0x1F, U 0xFF, U 0xD0, U 0x00, U 0x1F, U 0xFF, U 0xC0, U 0x00, U 0xE3, U 0x00, U 0x04, U 0x3C, U 0x02, U 0x00, U 0x00, U 0x00, - U 0x20, U 0x00, U 0x6C, U 0x34, - U 0x1F, U 0xFF, U 0xC2, U 0x90, - U 0x20, U 0x00, U 0x6C, U 0x7C, - U 0x1F, U 0xFF, U 0xC2, U 0x94, - U 0x20, U 0x00, U 0x6C, U 0xBC, - U 0x1F, U 0xFF, U 0xC2, U 0x98, - U 0x20, U 0x00, U 0x6D, U 0x30, - U 0x1F, U 0xFF, U 0xC2, U 0x9C, + U 0x20, U 0x00, U 0x6C, U 0xB4, + U 0x1F, U 0xFF, U 0xC2, U 0xA0, + U 0x20, U 0x00, U 0x6C, U 0xFC, + U 0x1F, U 0xFF, U 0xC2, U 0xA4, + U 0x20, U 0x00, U 0x6D, U 0x3C, + U 0x1F, U 0xFF, U 0xC2, U 0xA8, + U 0x20, U 0x00, U 0x6D, U 0xB0, + U 0x1F, U 0xFF, U 0xC2, U 0xAC, U 0x20, U 0x00, U 0x03, U 0xC0, U 0xC0, U 0x00, U 0x00, U 0xE4, U 0x31, U 0x00, U 0xEA, U 0x31, U 0x00, U 0xA1, U 0x31, U 0x00, U 0xA0, U 0x31, U 0x03, U 0x02, U 0x00, U 0x02, U 0xED, U 0x30, U 0x6E, U 0x2A, U 0x05, U 0x00, U 0xED, U 0x31, U 0x00, U 0x02, U 0x00, U 0x02, U 0x16, U 0x00, U 0x12, U 0xFF, U 0xDB, U 0xC0, U 0x30, U 0x14, U 0xFF, U 0xDA, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x03, U 0x43, U 0x1F, U 0x24, U 0x4C, U 0x10, U 0x72, U 0x49, U 0xF0, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x12, U 0xFF, U 0xD5, U 0x23, U 0x0A, U 0x00, U 0x24, U 0x0A, U 0x00, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x03, U 0x43, U 0x1F, U 0x24, U 0x4C, U 0x10, U 0x72, U 0x49, U 0xF0, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x14, U 0xFF, U 0xCE, U 0x03, U 0x42, U 0x1F, U 0x14, U 0xFF, U 0xCB, U 0x03, U 0x42, U 0x1F, U 0x12, U 0xFF, U 0xCC, U 0xC0, U 0x30, U 0x2D, U 0x37, U 0x30, U 0x2D, U 0x37, U 0x34, U 0x2D, U 0x37, U 0x38, U 0x2D, U 0x37, U 0x3C, U 0x23, U 0x3D, U 0x01, U 0x72, U 0x33, U 0xED, U 0x00, U 0x02, U 0x00, U 0x12, U 0xFF, U 0xC4, U 0xC0, U 0x30, U 0x2F, U 0x37, U 0x00, U 0x2F, U 0x37, U 0x10, U 0x2F, U 0x37, U 0x20, U 0x2F, U 0x37, U 0x30, U 0x23, U 0x3D, U 0x01, U 0x72, U 0x33, U 0xED, U 0x00, U 0x02, U 0x00, U 0x12, U 0xFF, U 0xBE, U 0xC0, U 0x30, U 0x27, U 0x37, U 0x00, U 0x27, U 0x37, U 0x10, U 0x27, U 0x37, U 0x20, U 0x27, U 0x37, U 0x30, U 0x23, U 0x3D, U 0x01, U 0x72, U 0x33, U 0xED, U 0x03, U 0x02, U 0x00, U 0x12, U 0xFF, U 0xB9, U 0x13, U 0xFF, U 0xBA, U 0x0C, U 0x02, U 0x00, U 0x93, U 0x20, U 0x12, U 0xFF, U 0xB9, U 0x13, U 0xFF, U 0xB9, U 0x0C, U 0x02, U 0x00, U 0x93, U 0x20, U 0x12, U 0xFF, U 0xB8, U 0xC0, U 0x31, U 0x93, U 0x20, U 0x82, U 0x20, U 0x12, U 0xFF, U 0xB7, U 0x13, U 0xFF, U 0xB7, U 0x93, U 0x20, U 0x12, U 0xFF, U 0xB7, U 0x15, U 0xFF, U 0xB3, U 0x16, U 0xFF, U 0xB6, U 0xC0, U 0x30, U 0xD7, U 0x20, U 0x05, U 0x66, U 0x01, U 0x60, U 0x00, U 0x1B, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x04, U 0x36, U 0x05, U 0x00, U 0x02, U 0x00, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x05, U 0x33, U 0x0C, U 0x6E, U 0x3B, U 0x14, U 0x07, U 0x47, U 0x14, U 0x07, U 0x04, U 0x43, U 0x76, U 0x31, U 0xE6, U 0x04, U 0x36, U 0x05, U 0x05, U 0x33, U 0x0C, U 0x6F, U 0x3B, U 0xED, U 0x00, U 0x02, U 0x00, U 0x12, U 0xFF, U 0xA6, U 0x15, U 0xFF, U 0xA3, U 0x23, U 0x0A, U 0x00, U 0xD7, U 0x20, U 0x07, U 0x04, U 0x43, U 0x04, U 0x3E, U 0x05, U 0x05, U 0x33, U 0x0C, U 0x07, U 0x47, U 0x14, U 0x6F, U 0x3B, U 0xF0, U 0x03, U 0x02, U 0x00, U 0x12, U 0xFF, U 0xA1, U 0xC0, U 0x30, U 0x14, U 0xFF, U 0xA1, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x93, U 0x40, U 0xB4, U 0x44, U 0x72, U 0x49, U 0xF2, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x14, U 0xFF, U 0x9B, U 0x83, U 0x40, U 0x14, U 0xFF, U 0x9B, U 0x83, U 0x40, U 0x12, U 0xFF, U 0x9B, U 0x23, U 0x0A, U 0x00, U 0x14, U 0xFF, U 0x9A, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x93, U 0x40, U 0xB4, U 0x44, U 0x72, U 0x49, U 0xF2, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0xD3, U 0x0F, U 0x14, U 0xFF, U 0x95, U 0x83, U 0x40, U 0x12, U 0xFF, U 0x95, U 0xC9, U 0x2F, U 0x83, U 0x20, U 0x84, U 0x21, U 0x85, U 0x22, U 0xBC, U 0x22, U 0x74, U 0x3B, U 0x0F, U 0x86, U 0x50, U 0xB4, U 0x55, U 0x96, U 0x30, U 0xB4, U 0x33, U 0x74, U 0x33, U 0xF4, U 0x63, U 0xFF, U 0xE6, U 0x00, U 0x00, U 0x65, U 0x3F, U 0xE1, U 0x65, U 0x5F, U 0xDE, U 0x12, U 0xFF, U 0x7C, U 0x23, U 0x0A, U 0x00, U 0x28, U 0x37, U 0x40, U 0x28, U 0x37, U 0x44, U 0x28, U 0x37, U 0x48, U 0x28, U 0x37, U 0x4C, U 0x23, U 0x3D, U 0x01, U 0x72, U 0x33, U 0xED, U 0x03, U 0x02, U 0x00, U 0x00, U 0x02, U 0x00, U 0x12, U 0xFF, U 0x7A, U 0xC0, U 0x32, U 0x03, U 0x2E, U 0x05, U 0x03, U 0x02, U 0x00, U 0x12, U 0xFF, U 0x78, U 0x13, U 0xFF, U 0x81, U 0x93, U 0x20, U 0xC0, U 0x11, U 0x01, U 0x49, U 0x31, U 0x00, U 0x48, U 0x31, U 0x01, U 0x02, U 0x00, U 0xC0, U 0x00, U 0x14, U 0xFF, U 0x7E, U 0x04, U 0xD2, U 0x31, U 0x15, U 0xFF, U 0x7D, U 0x94, U 0x50, U 0x14, U 0xFF, U 0x7D, U 0x04, U 0xD3, U 0x31, U 0x15, U 0xFF, U 0x7C, U 0x94, U 0x50, U 0x14, U 0xFF, U 0x7C, U 0x04, U 0xD4, U 0x31, U 0x15, U 0xFF, U 0x7C, U 0x24, U 0x56, U 0x00, U 0x14, U 0xFF, U 0x7B, U 0x04, U 0xD5, U 0x31, U 0x15, U 0xFF, U 0x7B, U 0x24, U 0x56, U 0x00, U 0x10, U 0xFF, U 0x7A, U 0x03, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 0x00, U 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- U 0x61, U 0x2E, U 0x61, U 0x73, - U 0x69, U 0x63, U 0x64, U 0x65, - U 0x73, U 0x69, U 0x67, U 0x6E, - U 0x65, U 0x72, U 0x73, U 0x2E, - U 0x63, U 0x6F, U 0x6D, U 0x3A, - U 0x2F, U 0x68, U 0x6F, U 0x6D, - U 0x65, U 0x2F, U 0x66, U 0x65, - U 0x6C, U 0x69, U 0x78, U 0x2F, - U 0x77, U 0x2F, U 0x66, U 0x77, - U 0x5F, U 0x37, U 0x2E, U 0x37, + U 0x0A, U 0x00, U 0x00, U 0x00, + U 0x00, U 0x43, U 0x68, U 0x65, + U 0x6C, U 0x73, U 0x69, U 0x6F, + U 0x20, U 0x46, U 0x57, U 0x20, + U 0x44, U 0x45, U 0x42, U 0x55, + U 0x47, U 0x3D, U 0x30, U 0x20, + U 0x28, U 0x42, U 0x75, U 0x69, + U 0x6C, U 0x74, U 0x20, U 0x54, + U 0x68, U 0x75, U 0x20, U 0x4D, + U 0x61, U 0x79, U 0x20, U 0x32, + U 0x30, U 0x20, U 0x31, U 0x33, + U 0x3A, U 0x34, U 0x36, U 0x3A, + U 0x32, U 0x33, U 0x20, U 0x50, + U 0x44, U 0x54, U 0x20, U 0x32, + U 0x30, U 0x31, U 0x30, U 0x20, + U 0x6F, U 0x6E, U 0x20, U 0x63, + U 0x6C, U 0x65, U 0x6F, U 0x70, + U 0x61, U 0x74, U 0x72, U 0x61, + U 0x2E, U 0x61, U 0x73, U 0x69, + U 0x63, U 0x64, U 0x65, U 0x73, + U 0x69, U 0x67, U 0x6E, U 0x65, + U 0x72, U 0x73, U 0x2E, U 0x63, + U 0x6F, U 0x6D, U 0x3A, U 0x2F, + U 0x68, U 0x6F, U 0x6D, U 0x65, + U 0x2F, U 0x66, U 0x65, U 0x6C, + U 0x69, U 0x78, U 0x2F, U 0x77, + U 0x2F, U 0x66, U 0x77, U 0x2D, + U 0x37, U 0x2E, U 0x31, U 0x31, U 0x29, U 0x2C, U 0x20, U 0x56, U 0x65, U 0x72, U 0x73, U 0x69, U 0x6F, U 0x6E, U 0x20, U 0x54, U 0x33, U 0x78, U 0x78, U 0x20, U 0x30, U 0x30, U 0x37, U 0x2E, - U 0x30, U 0x38, U 0x2E, U 0x30, + U 0x30, U 0x62, U 0x2E, U 0x30, U 0x30, U 0x20, U 0x2D, U 0x20, U 0x31, U 0x30, U 0x30, U 0x37, - U 0x30, U 0x38, U 0x30, U 0x30, - U 0x10, U 0x07, U 0x08, U 0x00, - U 0x4F, U 0x43, U 0x3A, U 0x10, + U 0x30, U 0x62, U 0x30, U 0x30, + U 0x10, U 0x07, U 0x0B, U 0x00, + U 0x27, U 0x85, U 0x6A, U 0xC6, }; Index: stable/7/sys =================================================================== --- stable/7/sys (revision 220340) +++ stable/7/sys (revision 220341) Property changes on: stable/7/sys ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head/sys:r219945-219946,220009