Index: head/sys/dev/mii/miidevs =================================================================== --- head/sys/dev/mii/miidevs (revision 217909) +++ head/sys/dev/mii/miidevs (revision 217910) @@ -1,265 +1,266 @@ $FreeBSD$ /*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/ /*- * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, * NASA Ames Research Center. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * List of known MII OUIs. * For a complete list see http://standards.ieee.org/regauth/oui/ * * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped * to the 16 bits available in the id registers. The MII_OUI() macro * in "mii.h" reflects the most obvious way. If a vendor uses a * different mapping, an "xx" prefixed OUI is defined here which is * mangled accordingly to compensate. */ oui AGERE 0x00a0bc Agere Systems oui ALTIMA 0x0010a9 Altima Communications oui AMD 0x00001a Advanced Micro Devices oui ASIX 0x00602e Asix Semiconductor oui ATHEROS 0x001374 Atheros Communications oui BROADCOM 0x001018 Broadcom Corporation oui BROADCOM2 0x000af7 Broadcom Corporation oui CICADA 0x0003F1 Cicada Semiconductor oui DAVICOM 0x00606e Davicom Semiconductor oui ICPLUS 0x0090c3 IC Plus Corp. oui ICS 0x00a0be Integrated Circuit Systems oui INTEL 0x00aa00 Intel oui JATO 0x00e083 Jato Technologies oui JMICRON 0x001b8c JMicron Technologies oui LEVEL1 0x00207b Level 1 oui NATSEMI 0x080017 National Semiconductor oui QUALSEMI 0x006051 Quality Semiconductor oui RDC 0x000bb4 RDC Semiconductor oui REALTEK 0x000020 RealTek Semicondctor oui SEEQ 0x00a07d Seeq oui SIS 0x00e006 Silicon Integrated Systems oui SMSC 0x0005be SMSC oui TDK 0x00c039 TDK oui TI 0x080028 Texas Instruments oui VITESSE 0x0001c1 Vitesse Semiconductor oui XAQTI 0x00e0ae XaQti Corp. oui MARVELL 0x005043 Marvell Semiconductor oui xxMARVELL 0x000ac2 Marvell Semiconductor /* in the 79c873, AMD uses another OUI (which matches Davicom!) */ oui xxAMD 0x00606e Advanced Micro Devices /* Intel 82553 A/B steppings */ oui xxINTEL 0x00f800 Intel /* some vendors have the bits swapped within bytes (ie, ordered as on the wire) */ oui xxALTIMA 0x000895 Altima Communications oui xxBROADCOM 0x000818 Broadcom Corporation oui xxBROADCOM_ALT1 0x0050ef Broadcom Corporation oui xxBROADCOM_ALT2 0x00d897 Broadcom Corporation oui xxICS 0x00057d Integrated Circuit Systems oui xxSEEQ 0x0005be Seeq oui xxSIS 0x000760 Silicon Integrated Systems oui xxTI 0x100014 Texas Instruments oui xxXAQTI 0x350700 XaQti Corp. /* Level 1 is completely different - from right to left. (Two bits get lost in the third OUI byte.) */ oui xxLEVEL1 0x1e0400 Level 1 /* Don't know what's going on here. */ oui xxDAVICOM 0x006040 Davicom Semiconductor /* This is the OUI of the gigE PHY in the RealTek 8169S/8110S/8211B chips */ oui xxREALTEK 0x000732 /* * List of known models. Grouped by oui. */ /* Agere Systems PHYs */ model AGERE ET1011 0x0001 ET1011 10/100/1000baseT PHY model AGERE ET1011C 0x0004 ET1011C 10/100/1000baseT PHY /* Altima Communications PHYs */ model xxALTIMA AC101 0x0021 AC101 10/100 media interface model xxALTIMA AC101L 0x0012 AC101L 10/100 media interface model xxALTIMA ACXXX 0x0001 ACXXX 10/100 media interface /* Advanced Micro Devices PHYs */ model AMD 79c973phy 0x0036 Am79c973 internal PHY model AMD 79c978 0x0039 Am79c978 HomePNA PHY model xxAMD 79C873 0x0000 Am79C873/DM9101 10/100 media interface /* Asix semiconductor PHYs. */ model ASIX AX88X9X 0x0031 Ax88x9x internal PHY /* Atheros Communications/Attansic PHYs. */ model ATHEROS F1 0x0001 Atheros F1 10/100/1000 PHY model ATHEROS F2 0x0002 Atheros F2 10/100 PHY model ATHEROS F1_7 0x0007 Atheros F1 10/100/1000 PHY /* Broadcom Corp. PHYs. */ model BROADCOM 3C905B 0x0012 3c905B 10/100 internal PHY model BROADCOM 3C905C 0x0017 3c905C 10/100 internal PHY model BROADCOM BCM5201 0x0021 BCM5201 10/100baseTX PHY model BROADCOM BCM5214 0x0028 BCM5214 Quad 10/100 PHY model BROADCOM BCM5221 0x001e BCM5221 10/100baseTX PHY model BROADCOM BCM5222 0x0032 BCM5222 Dual 10/100 PHY model BROADCOM BCM4401 0x0036 BCM4401 10/100baseTX PHY model xxBROADCOM BCM5400 0x0004 Broadcom 1000baseTX PHY model xxBROADCOM BCM5401 0x0005 BCM5401 10/100/1000baseTX PHY model xxBROADCOM BCM5411 0x0007 BCM5411 10/100/1000baseTX PHY model xxBROADCOM BCM5754 0x000e BCM5754 10/100/1000baseTX PHY model xxBROADCOM BCM5752 0x0010 BCM5752 10/100/1000baseTX PHY model xxBROADCOM BCM5701 0x0011 BCM5701 10/100/1000baseTX PHY model xxBROADCOM BCM5706 0x0015 BCM5706 10/100/1000baseTX/SX PHY model xxBROADCOM BCM5703 0x0016 BCM5703 10/100/1000baseTX PHY model xxBROADCOM BCM5704 0x0019 BCM5704 10/100/1000baseTX PHY model xxBROADCOM BCM5705 0x001a BCM5705 10/100/1000baseTX PHY model xxBROADCOM BCM5750 0x0018 BCM5750 10/100/1000baseTX PHY model xxBROADCOM BCM54K2 0x002e BCM54K2 10/100/1000baseTX PHY model xxBROADCOM BCM5714 0x0034 BCM5714 10/100/1000baseTX PHY model xxBROADCOM BCM5780 0x0035 BCM5780 10/100/1000baseTX PHY model xxBROADCOM BCM5708C 0x0036 BCM5708C 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5482S 0x000b BCM5482S Dual-Port 10/100/1000baseX/FX PHY model xxBROADCOM_ALT1 BCM5755 0x000c BCM5755 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5787 0x000e BCM5787 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5708S 0x0015 BCM5708S 1000/2500BaseSX PHY model xxBROADCOM_ALT1 BCM5709CAX 0x002c BCM5709C(AX) 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5722 0x002d BCM5722 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5784 0x003a BCM5784 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5709C 0x003c BCM5709C 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5761 0x003d BCM5761 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5709S 0x003f BCM5709S 1000/2500baseSX PHY model xxBROADCOM_ALT2 BCM5717C 0x0020 BCM5717C 10/100/1000baseTX PHY model BROADCOM2 BCM5906 0x0004 BCM5906 10/100baseTX PHY /* Cicada Semiconductor PHYs (now owned by Vitesse?) */ model CICADA CS8201 0x0001 Cicada CS8201 10/100/1000TX PHY model CICADA CS8204 0x0004 Cicada CS8204 10/100/1000TX PHY model CICADA VSC8211 0x000b Cicada VSC8211 10/100/1000TX PHY model CICADA CS8201A 0x0020 Cicada CS8201 10/100/1000TX PHY model CICADA CS8201B 0x0021 Cicada CS8201 10/100/1000TX PHY model CICADA CS8244 0x002c Cicada CS8244 10/100/1000TX PHY model VITESSE VSC8601 0x0002 Vitesse VSC8601 10/100/1000TX PHY /* Davicom Semiconductor PHYs */ model DAVICOM DM9102 0x0004 DM9102 10/100 media interface model xxDAVICOM DM9101 0x0000 DM9101 10/100 media interface /* Integrated Circuit Systems PHYs */ model xxICS 1889 0x0001 ICS1889 10/100 media interface model xxICS 1890 0x0002 ICS1890 10/100 media interface model xxICS 1892 0x0003 ICS1892 10/100 media interface model xxICS 1893 0x0004 ICS1893 10/100 media interface /* IC Plus Corp. PHYs */ model ICPLUS IP101 0x0005 IC Plus 10/100 PHY model ICPLUS IP1000A 0x0008 IC Plus 10/100/1000 media interface model ICPLUS IP1001 0x0019 IC Plus IP1001 10/100/1000 media interface /* Intel PHYs */ model xxINTEL I82553AB 0x0000 i83553 10/100 media interface model INTEL I82555 0x0015 i82555 10/100 media interface model INTEL I82562EM 0x0032 i82562EM 10/100 media interface model INTEL I82562ET 0x0033 i82562ET 10/100 media interface model INTEL I82553C 0x0035 i82553 10/100 media interface /* Jato Technologies PHYs */ model JATO BASEX 0x0000 Jato 1000baseX media interface /* JMicron Technologies PHYs */ model JMICRON JMP211 0x0021 JMP211 10/100/1000 media interface model JMICRON JMP202 0x0022 JMP202 10/100 media interface /* Level 1 PHYs */ model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface /* National Semiconductor PHYs */ model NATSEMI DP83840 0x0000 DP83840 10/100 media interface model NATSEMI DP83843 0x0001 DP83843 10/100 media interface model NATSEMI DP83815 0x0002 DP83815 10/100 media interface model NATSEMI DP83847 0x0003 DP83847 10/100 media interface model NATSEMI DP83891 0x0005 DP83891 10/100/1000 media interface model NATSEMI DP83861 0x0006 DP83861 10/100/1000 media interface model NATSEMI DP83865 0x0007 DP83865 10/100/1000 media interface /* Quality Semiconductor PHYs */ model QUALSEMI QS6612 0x0000 QS6612 10/100 media interface /* RDC Semiconductor PHYs */ model RDC R6040 0x0003 R6040 10/100 media interface /* RealTek Semiconductor PHYs */ model REALTEK RTL8201L 0x0020 RTL8201L 10/100 media interface model xxREALTEK RTL8305SC 0x0005 RTL8305SC 10/100 802.1q switch +model xxREALTEK RTL8201E 0x0008 RTL8201E 10/100 media interface model xxREALTEK RTL8169S 0x0011 RTL8169S/8110S/8211B media interface /* Seeq PHYs */ model xxSEEQ 80220 0x0003 Seeq 80220 10/100 media interface model xxSEEQ 84220 0x0004 Seeq 84220 10/100 media interface /* Silicon Integrated Systems PHYs */ model xxSIS 900 0x0000 SiS 900 10/100 media interface /* SMSC PHYs */ model SMSC LAN83C183 0x0004 SMSC LAN83C183 10/100 media interface /* TDK */ model TDK 78Q2120 0x0014 TDK 78Q2120 media interface /* Texas Instruments PHYs */ model xxTI TLAN10T 0x0001 ThunderLAN 10baseT media interface model xxTI 100VGPMI 0x0002 ThunderLAN 100VG-AnyLan media interface /* XaQti Corp. PHYs. */ model XAQTI XMACII 0x0000 XaQti Corp. XMAC II gigabit interface /* Marvell Semiconductor PHYs */ model MARVELL E1000 0x0000 Marvell 88E1000 Gigabit PHY model MARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY model MARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY model MARVELL E1000S 0x0004 Marvell 88E1000S Gigabit PHY model MARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY model MARVELL E1101 0x0006 Marvell 88E1101 Gigabit PHY model MARVELL E3082 0x0008 Marvell 88E3082 10/100 Fast Ethernet PHY model MARVELL E1112 0x0009 Marvell 88E1112 Gigabit PHY model MARVELL E1149 0x000b Marvell 88E1149 Gigabit PHY model MARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY model MARVELL E1116 0x0021 Marvell 88E1116 Gigabit PHY model MARVELL E1116R 0x0024 Marvell 88E1116R Gigabit PHY model MARVELL E1118 0x0022 Marvell 88E1118 Gigabit PHY model MARVELL E3016 0x0026 Marvell 88E3016 10/100 Fast Ethernet PHY model MARVELL PHYG65G 0x0027 Marvell PHYG65G Gigabit PHY model xxMARVELL E1000 0x0005 Marvell 88E1000 Gigabit PHY model xxMARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY model xxMARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY model xxMARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY model xxMARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY Index: head/sys/dev/mii/rlphy.c =================================================================== --- head/sys/dev/mii/rlphy.c (revision 217909) +++ head/sys/dev/mii/rlphy.c (revision 217910) @@ -1,306 +1,307 @@ /*- * Copyright (c) 1997, 1998, 1999 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * driver for RealTek 8139 internal PHYs */ #include #include #include #include #include #include #include #include #include #include #include #include "miidevs.h" #include #include #include "miibus_if.h" struct rlphy_softc { struct mii_softc sc_mii; /* generic PHY */ int sc_is_RTL8201L; /* is an external RTL8201L PHY */ }; static int rlphy_probe(device_t); static int rlphy_attach(device_t); static device_method_t rlphy_methods[] = { /* device interface */ DEVMETHOD(device_probe, rlphy_probe), DEVMETHOD(device_attach, rlphy_attach), DEVMETHOD(device_detach, mii_phy_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), { 0, 0 } }; static devclass_t rlphy_devclass; static driver_t rlphy_driver = { "rlphy", rlphy_methods, sizeof(struct rlphy_softc) }; DRIVER_MODULE(rlphy, miibus, rlphy_driver, rlphy_devclass, 0, 0); static int rlphy_service(struct mii_softc *, struct mii_data *, int); static void rlphy_status(struct mii_softc *); /* * RealTek internal PHYs don't have vendor/device ID registers; * re(4) and rl(4) fake up a return value of all zeros. */ static const struct mii_phydesc rlintphys[] = { { 0, 0, "RealTek internal media interface" }, MII_PHY_END }; static const struct mii_phydesc rlphys[] = { MII_PHY_DESC(REALTEK, RTL8201L), + MII_PHY_DESC(xxREALTEK, RTL8201E), MII_PHY_DESC(ICPLUS, IP101), MII_PHY_END }; static int rlphy_probe(device_t dev) { const char *nic; int rv; rv = mii_phy_dev_probe(dev, rlphys, BUS_PROBE_DEFAULT); if (rv <= 0) return (rv); nic = device_get_name(device_get_parent(device_get_parent(dev))); if (strcmp(nic, "rl") == 0 || strcmp(nic, "re") == 0) return (mii_phy_dev_probe(dev, rlintphys, BUS_PROBE_DEFAULT)); return (ENXIO); } static int rlphy_attach(device_t dev) { struct mii_softc *sc; struct mii_attach_args *ma; struct mii_data *mii; struct rlphy_softc *rsc; sc = device_get_softc(dev); ma = device_get_ivars(dev); sc->mii_dev = device_get_parent(dev); mii = ma->mii_data; /* * Check whether we're the RTL8201L PHY and remember so the status * routine can query the proper register for speed detection. */ rsc = (struct rlphy_softc *)sc; if (mii_phy_dev_probe(dev, rlphys, 0) == 0) rsc->sc_is_RTL8201L++; LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); sc->mii_flags = miibus_get_flags(dev); sc->mii_inst = mii->mii_instance++; sc->mii_phy = ma->mii_phyno; sc->mii_service = rlphy_service; sc->mii_pdata = mii; /* * The RealTek PHY can never be isolated. */ sc->mii_flags |= MIIF_NOISOLATE; #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), MII_MEDIA_100_TX); mii_phy_reset(sc); sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; device_printf(dev, " "); mii_phy_add_media(sc); printf("\n"); #undef ADD MIIBUS_MEDIAINIT(sc->mii_dev); return (0); } static int rlphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { switch (cmd) { case MII_POLLSTAT: break; case MII_MEDIACHG: /* * If the interface is not up, don't do anything. */ if ((mii->mii_ifp->if_flags & IFF_UP) == 0) break; mii_phy_setmedia(sc); break; case MII_TICK: /* * Is the interface even up? */ if ((mii->mii_ifp->if_flags & IFF_UP) == 0) return (0); /* * The RealTek PHY's autonegotiation doesn't need to be * kicked; it continues in the background. */ break; } /* Update the media status. */ rlphy_status(sc); /* Callback if something changed. */ mii_phy_update(sc, cmd); return (0); } static void rlphy_status(struct mii_softc *phy) { struct rlphy_softc *rsc =(struct rlphy_softc *)phy; struct mii_data *mii = phy->mii_pdata; struct ifmedia_entry *ife = mii->mii_media.ifm_cur; int bmsr, bmcr, anlpar; mii->mii_media_status = IFM_AVALID; mii->mii_media_active = IFM_ETHER; bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR); if (bmsr & BMSR_LINK) mii->mii_media_status |= IFM_ACTIVE; bmcr = PHY_READ(phy, MII_BMCR); if (bmcr & BMCR_ISO) { mii->mii_media_active |= IFM_NONE; mii->mii_media_status = 0; return; } if (bmcr & BMCR_LOOP) mii->mii_media_active |= IFM_LOOP; if (bmcr & BMCR_AUTOEN) { /* * NWay autonegotiation takes the highest-order common * bit of the ANAR and ANLPAR (i.e. best media advertised * both by us and our link partner). */ if ((bmsr & BMSR_ACOMP) == 0) { /* Erg, still trying, I guess... */ mii->mii_media_active |= IFM_NONE; return; } if ((anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR))) { if (anlpar & ANLPAR_TX_FD) mii->mii_media_active |= IFM_100_TX|IFM_FDX; else if (anlpar & ANLPAR_T4) mii->mii_media_active |= IFM_100_T4|IFM_HDX; else if (anlpar & ANLPAR_TX) mii->mii_media_active |= IFM_100_TX|IFM_HDX; else if (anlpar & ANLPAR_10_FD) mii->mii_media_active |= IFM_10_T|IFM_FDX; else if (anlpar & ANLPAR_10) mii->mii_media_active |= IFM_10_T|IFM_HDX; else mii->mii_media_active |= IFM_NONE; return; } /* * If the other side doesn't support NWAY, then the * best we can do is determine if we have a 10Mbps or * 100Mbps link. There's no way to know if the link * is full or half duplex, so we default to half duplex * and hope that the user is clever enough to manually * change the media settings if we're wrong. */ /* * The RealTek PHY supports non-NWAY link speed * detection, however it does not report the link * detection results via the ANLPAR or BMSR registers. * (What? RealTek doesn't do things the way everyone * else does? I'm just shocked, shocked I tell you.) * To determine the link speed, we have to do one * of two things: * * - If this is a standalone RealTek RTL8201(L) PHY, * we can determine the link speed by testing bit 0 * in the magic, vendor-specific register at offset * 0x19. * * - If this is a RealTek MAC with integrated PHY, we * can test the 'SPEED10' bit of the MAC's media status * register. */ if (rsc->sc_is_RTL8201L) { if (PHY_READ(phy, 0x0019) & 0x01) mii->mii_media_active |= IFM_100_TX; else mii->mii_media_active |= IFM_10_T; } else { if (PHY_READ(phy, RL_MEDIASTAT) & RL_MEDIASTAT_SPEED10) mii->mii_media_active |= IFM_10_T; else mii->mii_media_active |= IFM_100_TX; } mii->mii_media_active |= IFM_HDX; } else mii->mii_media_active = ife->ifm_media; }