Index: head/sys/dev/sis/if_sis.c =================================================================== --- head/sys/dev/sis/if_sis.c (revision 212108) +++ head/sys/dev/sis/if_sis.c (revision 212109) @@ -1,2289 +1,2355 @@ /*- * Copyright (c) 2005 Poul-Henning Kamp * Copyright (c) 1997, 1998, 1999 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are * available from http://www.sis.com.tw. * * This driver also supports the NatSemi DP83815. Datasheets are * available from http://www.national.com. * * Written by Bill Paul * Electrical Engineering Department * Columbia University, New York City */ /* * The SiS 900 is a fairly simple chip. It uses bus master DMA with * simple TX and RX descriptors of 3 longwords in size. The receiver * has a single perfect filter entry for the station address and a * 128-bit multicast hash table. The SiS 900 has a built-in MII-based * transceiver while the 7016 requires an external transceiver chip. * Both chips offer the standard bit-bang MII interface as well as * an enchanced PHY interface which simplifies accessing MII registers. * * The only downside to this chipset is that RX descriptors must be * longword aligned. */ #ifdef HAVE_KERNEL_OPTION_HEADERS #include "opt_device_polling.h" #endif #include #include -#include -#include -#include +#include +#include #include +#include +#include +#include #include #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define SIS_USEIOSPACE #include MODULE_DEPEND(sis, pci, 1, 1, 1); MODULE_DEPEND(sis, ether, 1, 1, 1); MODULE_DEPEND(sis, miibus, 1, 1, 1); /* "device miibus" required. See GENERIC if you get errors here. */ #include "miibus_if.h" #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx) #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx) #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED) /* * register space access macros */ #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val) #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg) /* * Various supported device vendors/types and their names. */ static struct sis_type sis_devs[] = { { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, { 0, 0, NULL } }; static int sis_detach(device_t); +static __inline void sis_discard_rxbuf(struct sis_rxdesc *); +static int sis_dma_alloc(struct sis_softc *); +static void sis_dma_free(struct sis_softc *); +static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t, + bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); +static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int); +#ifndef __NO_STRICT_ALIGNMENT +static __inline void sis_fixup_rx(struct mbuf *); +#endif static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int sis_ifmedia_upd(struct ifnet *); static void sis_init(void *); static void sis_initl(struct sis_softc *); static void sis_intr(void *); static int sis_ioctl(struct ifnet *, u_long, caddr_t); -static int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *); +static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *); +static int sis_rxeof(struct sis_softc *); static void sis_start(struct ifnet *); static void sis_startl(struct ifnet *); static void sis_stop(struct sis_softc *); static void sis_watchdog(struct sis_softc *); static struct resource_spec sis_res_spec[] = { #ifdef SIS_USEIOSPACE { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE}, #else { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE}, #endif { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE}, { -1, 0 } }; #define SIS_SETBIT(sc, reg, x) \ CSR_WRITE_4(sc, reg, \ CSR_READ_4(sc, reg) | (x)) #define SIS_CLRBIT(sc, reg, x) \ CSR_WRITE_4(sc, reg, \ CSR_READ_4(sc, reg) & ~(x)) #define SIO_SET(x) \ CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) #define SIO_CLR(x) \ CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) -static void -sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error) -{ - struct sis_desc *r; - - r = arg; - r->sis_next = segs->ds_addr; -} - -static void -sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error) -{ - struct sis_desc *r; - - r = arg; - r->sis_ptr = segs->ds_addr; -} - -static void -sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error) -{ - u_int32_t *p; - - p = arg; - *p = segs->ds_addr; -} - /* * Routine to reverse the bits in a word. Stolen almost * verbatim from /usr/games/fortune. */ static uint16_t sis_reverse(uint16_t n) { n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); return (n); } static void sis_delay(struct sis_softc *sc) { int idx; for (idx = (300 / 33) + 1; idx > 0; idx--) CSR_READ_4(sc, SIS_CSR); } static void sis_eeprom_idle(struct sis_softc *sc) { int i; SIO_SET(SIS_EECTL_CSEL); sis_delay(sc); SIO_SET(SIS_EECTL_CLK); sis_delay(sc); for (i = 0; i < 25; i++) { SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); SIO_SET(SIS_EECTL_CLK); sis_delay(sc); } SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); SIO_CLR(SIS_EECTL_CSEL); sis_delay(sc); CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); } /* * Send a read command and address to the EEPROM, check for ACK. */ static void sis_eeprom_putbyte(struct sis_softc *sc, int addr) { int d, i; d = addr | SIS_EECMD_READ; /* * Feed in each bit and stobe the clock. */ for (i = 0x400; i; i >>= 1) { if (d & i) { SIO_SET(SIS_EECTL_DIN); } else { SIO_CLR(SIS_EECTL_DIN); } sis_delay(sc); SIO_SET(SIS_EECTL_CLK); sis_delay(sc); SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); } } /* * Read a word of data stored in the EEPROM at address 'addr.' */ static void sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest) { int i; u_int16_t word = 0; /* Force EEPROM to idle state. */ sis_eeprom_idle(sc); /* Enter EEPROM access mode. */ sis_delay(sc); SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); SIO_SET(SIS_EECTL_CSEL); sis_delay(sc); /* * Send address of word we want to read. */ sis_eeprom_putbyte(sc, addr); /* * Start reading bits from EEPROM. */ for (i = 0x8000; i; i >>= 1) { SIO_SET(SIS_EECTL_CLK); sis_delay(sc); if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) word |= i; sis_delay(sc); SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); } /* Turn off EEPROM access mode. */ sis_eeprom_idle(sc); *dest = word; } /* * Read a sequence of words from the EEPROM. */ static void sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap) { int i; u_int16_t word = 0, *ptr; for (i = 0; i < cnt; i++) { sis_eeprom_getword(sc, off + i, &word); ptr = (u_int16_t *)(dest + (i * 2)); if (swap) *ptr = ntohs(word); else *ptr = word; } } #if defined(__i386__) || defined(__amd64__) static device_t sis_find_bridge(device_t dev) { devclass_t pci_devclass; device_t *pci_devices; int pci_count = 0; device_t *pci_children; int pci_childcount = 0; device_t *busp, *childp; device_t child = NULL; int i, j; if ((pci_devclass = devclass_find("pci")) == NULL) return (NULL); devclass_get_devices(pci_devclass, &pci_devices, &pci_count); for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { if (device_get_children(*busp, &pci_children, &pci_childcount)) continue; for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { if (pci_get_vendor(*childp) == SIS_VENDORID && pci_get_device(*childp) == 0x0008) { child = *childp; free(pci_children, M_TEMP); goto done; } } free(pci_children, M_TEMP); } done: free(pci_devices, M_TEMP); return (child); } static void sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt) { device_t bridge; u_int8_t reg; int i; bus_space_tag_t btag; bridge = sis_find_bridge(dev); if (bridge == NULL) return; reg = pci_read_config(bridge, 0x48, 1); pci_write_config(bridge, 0x48, reg|0x40, 1); /* XXX */ #if defined(__i386__) btag = I386_BUS_SPACE_IO; #elif defined(__amd64__) btag = AMD64_BUS_SPACE_IO; #endif for (i = 0; i < cnt; i++) { bus_space_write_1(btag, 0x0, 0x70, i + off); *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); } pci_write_config(bridge, 0x48, reg & ~0x40, 1); } static void sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest) { u_int32_t filtsave, csrsave; filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); csrsave = CSR_READ_4(sc, SIS_CSR); CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); CSR_WRITE_4(sc, SIS_CSR, 0); CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); CSR_WRITE_4(sc, SIS_CSR, csrsave); } #endif /* * Sync the PHYs by setting data bit and strobing the clock 32 times. */ static void sis_mii_sync(struct sis_softc *sc) { int i; SIO_SET(SIS_MII_DIR|SIS_MII_DATA); for (i = 0; i < 32; i++) { SIO_SET(SIS_MII_CLK); DELAY(1); SIO_CLR(SIS_MII_CLK); DELAY(1); } } /* * Clock a series of bits through the MII. */ static void sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt) { int i; SIO_CLR(SIS_MII_CLK); for (i = (0x1 << (cnt - 1)); i; i >>= 1) { if (bits & i) { SIO_SET(SIS_MII_DATA); } else { SIO_CLR(SIS_MII_DATA); } DELAY(1); SIO_CLR(SIS_MII_CLK); DELAY(1); SIO_SET(SIS_MII_CLK); } } /* * Read an PHY register through the MII. */ static int sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) { int i, ack; /* * Set up frame for RX. */ frame->mii_stdelim = SIS_MII_STARTDELIM; frame->mii_opcode = SIS_MII_READOP; frame->mii_turnaround = 0; frame->mii_data = 0; /* * Turn on data xmit. */ SIO_SET(SIS_MII_DIR); sis_mii_sync(sc); /* * Send command/address info. */ sis_mii_send(sc, frame->mii_stdelim, 2); sis_mii_send(sc, frame->mii_opcode, 2); sis_mii_send(sc, frame->mii_phyaddr, 5); sis_mii_send(sc, frame->mii_regaddr, 5); /* Idle bit */ SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); DELAY(1); SIO_SET(SIS_MII_CLK); DELAY(1); /* Turn off xmit. */ SIO_CLR(SIS_MII_DIR); /* Check for ack */ SIO_CLR(SIS_MII_CLK); DELAY(1); ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; SIO_SET(SIS_MII_CLK); DELAY(1); /* * Now try reading data bits. If the ack failed, we still * need to clock through 16 cycles to keep the PHY(s) in sync. */ if (ack) { for (i = 0; i < 16; i++) { SIO_CLR(SIS_MII_CLK); DELAY(1); SIO_SET(SIS_MII_CLK); DELAY(1); } goto fail; } for (i = 0x8000; i; i >>= 1) { SIO_CLR(SIS_MII_CLK); DELAY(1); if (!ack) { if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) frame->mii_data |= i; DELAY(1); } SIO_SET(SIS_MII_CLK); DELAY(1); } fail: SIO_CLR(SIS_MII_CLK); DELAY(1); SIO_SET(SIS_MII_CLK); DELAY(1); if (ack) return (1); return (0); } /* * Write to a PHY register through the MII. */ static int sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) { /* * Set up frame for TX. */ frame->mii_stdelim = SIS_MII_STARTDELIM; frame->mii_opcode = SIS_MII_WRITEOP; frame->mii_turnaround = SIS_MII_TURNAROUND; /* * Turn on data output. */ SIO_SET(SIS_MII_DIR); sis_mii_sync(sc); sis_mii_send(sc, frame->mii_stdelim, 2); sis_mii_send(sc, frame->mii_opcode, 2); sis_mii_send(sc, frame->mii_phyaddr, 5); sis_mii_send(sc, frame->mii_regaddr, 5); sis_mii_send(sc, frame->mii_turnaround, 2); sis_mii_send(sc, frame->mii_data, 16); /* Idle bit. */ SIO_SET(SIS_MII_CLK); DELAY(1); SIO_CLR(SIS_MII_CLK); DELAY(1); /* * Turn off xmit. */ SIO_CLR(SIS_MII_DIR); return (0); } static int sis_miibus_readreg(device_t dev, int phy, int reg) { struct sis_softc *sc; struct sis_mii_frame frame; sc = device_get_softc(dev); if (sc->sis_type == SIS_TYPE_83815) { if (phy != 0) return (0); /* * The NatSemi chip can take a while after * a reset to come ready, during which the BMSR * returns a value of 0. This is *never* supposed * to happen: some of the BMSR bits are meant to * be hardwired in the on position, and this can * confuse the miibus code a bit during the probe * and attach phase. So we make an effort to check * for this condition and wait for it to clear. */ if (!CSR_READ_4(sc, NS_BMSR)) DELAY(1000); return CSR_READ_4(sc, NS_BMCR + (reg * 4)); } /* * Chipsets < SIS_635 seem not to be able to read/write * through mdio. Use the enhanced PHY access register * again for them. */ if (sc->sis_type == SIS_TYPE_900 && sc->sis_rev < SIS_REV_635) { int i, val = 0; if (phy != 0) return (0); CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); for (i = 0; i < SIS_TIMEOUT; i++) { if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) break; } if (i == SIS_TIMEOUT) { device_printf(sc->sis_dev, "PHY failed to come ready\n"); return (0); } val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; if (val == 0xFFFF) return (0); return (val); } else { bzero((char *)&frame, sizeof(frame)); frame.mii_phyaddr = phy; frame.mii_regaddr = reg; sis_mii_readreg(sc, &frame); return (frame.mii_data); } } static int sis_miibus_writereg(device_t dev, int phy, int reg, int data) { struct sis_softc *sc; struct sis_mii_frame frame; sc = device_get_softc(dev); if (sc->sis_type == SIS_TYPE_83815) { if (phy != 0) return (0); CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); return (0); } /* * Chipsets < SIS_635 seem not to be able to read/write * through mdio. Use the enhanced PHY access register * again for them. */ if (sc->sis_type == SIS_TYPE_900 && sc->sis_rev < SIS_REV_635) { int i; if (phy != 0) return (0); CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | (reg << 6) | SIS_PHYOP_WRITE); SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); for (i = 0; i < SIS_TIMEOUT; i++) { if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) break; } if (i == SIS_TIMEOUT) device_printf(sc->sis_dev, "PHY failed to come ready\n"); } else { bzero((char *)&frame, sizeof(frame)); frame.mii_phyaddr = phy; frame.mii_regaddr = reg; frame.mii_data = data; sis_mii_writereg(sc, &frame); } return (0); } static void sis_miibus_statchg(device_t dev) { struct sis_softc *sc; sc = device_get_softc(dev); SIS_LOCK_ASSERT(sc); sis_initl(sc); } static uint32_t sis_mchash(struct sis_softc *sc, const uint8_t *addr) { uint32_t crc; /* Compute CRC for the address value. */ crc = ether_crc32_be(addr, ETHER_ADDR_LEN); /* * return the filter bit position * * The NatSemi chip has a 512-bit filter, which is * different than the SiS, so we special-case it. */ if (sc->sis_type == SIS_TYPE_83815) return (crc >> 23); else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) return (crc >> 24); else return (crc >> 25); } static void sis_setmulti_ns(struct sis_softc *sc) { struct ifnet *ifp; struct ifmultiaddr *ifma; u_int32_t h = 0, i, filtsave; int bit, index; ifp = sc->sis_ifp; if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); return; } /* * We have to explicitly enable the multicast hash table * on the NatSemi chip if we want to use it, which we do. */ SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); /* first, zot all the existing hash bits */ for (i = 0; i < 32; i++) { CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); } if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = sis_mchash(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); index = h >> 3; bit = h & 0x1F; CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); if (bit > 0xF) bit -= 0x10; SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); } if_maddr_runlock(ifp); CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); } static void sis_setmulti_sis(struct sis_softc *sc) { struct ifnet *ifp; struct ifmultiaddr *ifma; u_int32_t h, i, n, ctl; u_int16_t hashes[16]; ifp = sc->sis_ifp; /* hash table size */ if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) n = 16; else n = 8; ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; if (ifp->if_flags & IFF_BROADCAST) ctl |= SIS_RXFILTCTL_BROAD; if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { ctl |= SIS_RXFILTCTL_ALLMULTI; if (ifp->if_flags & IFF_PROMISC) ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; for (i = 0; i < n; i++) hashes[i] = ~0; } else { for (i = 0; i < n; i++) hashes[i] = 0; i = 0; if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = sis_mchash(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); hashes[h >> 4] |= 1 << (h & 0xf); i++; } if_maddr_runlock(ifp); if (i > n) { ctl |= SIS_RXFILTCTL_ALLMULTI; for (i = 0; i < n; i++) hashes[i] = ~0; } } for (i = 0; i < n; i++) { CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); } CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); } static void sis_reset(struct sis_softc *sc) { int i; SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); for (i = 0; i < SIS_TIMEOUT; i++) { if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) break; } if (i == SIS_TIMEOUT) device_printf(sc->sis_dev, "reset never completed\n"); /* Wait a little while for the chip to get its brains in order. */ DELAY(1000); /* * If this is a NetSemi chip, make sure to clear * PME mode. */ if (sc->sis_type == SIS_TYPE_83815) { CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); CSR_WRITE_4(sc, NS_CLKRUN, 0); } } /* * Probe for an SiS chip. Check the PCI vendor and device * IDs against our list and return a device name if we find a match. */ static int sis_probe(device_t dev) { struct sis_type *t; t = sis_devs; while (t->sis_name != NULL) { if ((pci_get_vendor(dev) == t->sis_vid) && (pci_get_device(dev) == t->sis_did)) { device_set_desc(dev, t->sis_name); return (BUS_PROBE_DEFAULT); } t++; } return (ENXIO); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int sis_attach(device_t dev) { u_char eaddr[ETHER_ADDR_LEN]; struct sis_softc *sc; struct ifnet *ifp; int error = 0, waittime = 0; waittime = 0; sc = device_get_softc(dev); sc->sis_dev = dev; mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0); if (pci_get_device(dev) == SIS_DEVICEID_900) sc->sis_type = SIS_TYPE_900; if (pci_get_device(dev) == SIS_DEVICEID_7016) sc->sis_type = SIS_TYPE_7016; if (pci_get_vendor(dev) == NS_VENDORID) sc->sis_type = SIS_TYPE_83815; sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); /* * Map control/status registers. */ pci_enable_busmaster(dev); error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res); if (error) { device_printf(dev, "couldn't allocate resources\n"); goto fail; } /* Reset the adapter. */ sis_reset(sc); if (sc->sis_type == SIS_TYPE_900 && (sc->sis_rev == SIS_REV_635 || sc->sis_rev == SIS_REV_900B)) { SIO_SET(SIS_CFG_RND_CNT); SIO_SET(SIS_CFG_PERR_DETECT); } /* * Get station address from the EEPROM. */ switch (pci_get_vendor(dev)) { case NS_VENDORID: sc->sis_srr = CSR_READ_4(sc, NS_SRR); /* We can't update the device description, so spew */ if (sc->sis_srr == NS_SRR_15C) device_printf(dev, "Silicon Revision: DP83815C\n"); else if (sc->sis_srr == NS_SRR_15D) device_printf(dev, "Silicon Revision: DP83815D\n"); else if (sc->sis_srr == NS_SRR_16A) device_printf(dev, "Silicon Revision: DP83816A\n"); else device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); /* * Reading the MAC address out of the EEPROM on * the NatSemi chip takes a bit more work than * you'd expect. The address spans 4 16-bit words, * with the first word containing only a single bit. * You have to shift everything over one bit to * get it aligned properly. Also, the bits are * stored backwards (the LSB is really the MSB, * and so on) so you have to reverse them in order * to get the MAC address into the form we want. * Why? Who the hell knows. */ { u_int16_t tmp[4]; sis_read_eeprom(sc, (caddr_t)&tmp, NS_EE_NODEADDR, 4, 0); /* Shift everything over one bit. */ tmp[3] = tmp[3] >> 1; tmp[3] |= tmp[2] << 15; tmp[2] = tmp[2] >> 1; tmp[2] |= tmp[1] << 15; tmp[1] = tmp[1] >> 1; tmp[1] |= tmp[0] << 15; /* Now reverse all the bits. */ tmp[3] = sis_reverse(tmp[3]); tmp[2] = sis_reverse(tmp[2]); tmp[1] = sis_reverse(tmp[1]); bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); } break; case SIS_VENDORID: default: #if defined(__i386__) || defined(__amd64__) /* * If this is a SiS 630E chipset with an embedded * SiS 900 controller, we have to read the MAC address * from the APC CMOS RAM. Our method for doing this * is very ugly since we have to reach out and grab * ahold of hardware for which we cannot properly * allocate resources. This code is only compiled on * the i386 architecture since the SiS 630E chipset * is for x86 motherboards only. Note that there are * a lot of magic numbers in this hack. These are * taken from SiS's Linux driver. I'd like to replace * them with proper symbolic definitions, but that * requires some datasheets that I don't have access * to at the moment. */ if (sc->sis_rev == SIS_REV_630S || sc->sis_rev == SIS_REV_630E || sc->sis_rev == SIS_REV_630EA1) sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); else if (sc->sis_rev == SIS_REV_635 || sc->sis_rev == SIS_REV_630ET) sis_read_mac(sc, dev, (caddr_t)&eaddr); else if (sc->sis_rev == SIS_REV_96x) { /* Allow to read EEPROM from LAN. It is shared * between a 1394 controller and the NIC and each * time we access it, we need to set SIS_EECMD_REQ. */ SIO_SET(SIS_EECMD_REQ); for (waittime = 0; waittime < SIS_TIMEOUT; waittime++) { /* Force EEPROM to idle state. */ sis_eeprom_idle(sc); if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); break; } DELAY(1); } /* * Set SIS_EECTL_CLK to high, so a other master * can operate on the i2c bus. */ SIO_SET(SIS_EECTL_CLK); /* Refuse EEPROM access by LAN */ SIO_SET(SIS_EECMD_DONE); } else #endif sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); break; } - /* - * Allocate the parent bus DMA tag appropriate for PCI. - */ -#define SIS_NSEG_NEW 32 - error = bus_dma_tag_create(NULL, /* parent */ - 1, 0, /* alignment, boundary */ - BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ - BUS_DMA_ALLOCNOW, /* flags */ - NULL, NULL, /* lockfunc, lockarg */ - &sc->sis_parent_tag); - if (error) + /* Allocate DMA'able memory. */ + if ((error = sis_dma_alloc(sc)) != 0) goto fail; - /* - * Now allocate a tag for the DMA descriptor lists and a chunk - * of DMA-able memory based on the tag. Also obtain the physical - * addresses of the RX and TX ring, which we'll need later. - * All of our lists are allocated as a contiguous block - * of memory. - */ - error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ - 1, 0, /* alignment, boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ - 0, /* flags */ - busdma_lock_mutex, /* lockfunc */ - &Giant, /* lockarg */ - &sc->sis_rx_tag); - if (error) - goto fail; - - error = bus_dmamem_alloc(sc->sis_rx_tag, - (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, - &sc->sis_rx_dmamap); - - if (error) { - device_printf(dev, "no memory for rx list buffers!\n"); - bus_dma_tag_destroy(sc->sis_rx_tag); - sc->sis_rx_tag = NULL; - goto fail; - } - - error = bus_dmamap_load(sc->sis_rx_tag, - sc->sis_rx_dmamap, &(sc->sis_rx_list[0]), - sizeof(struct sis_desc), sis_dma_map_ring, - &sc->sis_rx_paddr, 0); - - if (error) { - device_printf(dev, "cannot get address of the rx ring!\n"); - bus_dmamem_free(sc->sis_rx_tag, - sc->sis_rx_list, sc->sis_rx_dmamap); - bus_dma_tag_destroy(sc->sis_rx_tag); - sc->sis_rx_tag = NULL; - goto fail; - } - - error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ - 1, 0, /* alignment, boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ - 0, /* flags */ - busdma_lock_mutex, /* lockfunc */ - &Giant, /* lockarg */ - &sc->sis_tx_tag); - if (error) - goto fail; - - error = bus_dmamem_alloc(sc->sis_tx_tag, - (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, - &sc->sis_tx_dmamap); - - if (error) { - device_printf(dev, "no memory for tx list buffers!\n"); - bus_dma_tag_destroy(sc->sis_tx_tag); - sc->sis_tx_tag = NULL; - goto fail; - } - - error = bus_dmamap_load(sc->sis_tx_tag, - sc->sis_tx_dmamap, &(sc->sis_tx_list[0]), - sizeof(struct sis_desc), sis_dma_map_ring, - &sc->sis_tx_paddr, 0); - - if (error) { - device_printf(dev, "cannot get address of the tx ring!\n"); - bus_dmamem_free(sc->sis_tx_tag, - sc->sis_tx_list, sc->sis_tx_dmamap); - bus_dma_tag_destroy(sc->sis_tx_tag); - sc->sis_tx_tag = NULL; - goto fail; - } - - error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ - 1, 0, /* alignment, boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - MCLBYTES, 1, /* maxsize,nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ - 0, /* flags */ - busdma_lock_mutex, /* lockfunc */ - &Giant, /* lockarg */ - &sc->sis_tag); - if (error) - goto fail; - - /* - * Obtain the physical addresses of the RX and TX - * rings which we'll need later in the init routine. - */ - ifp = sc->sis_ifp = if_alloc(IFT_ETHER); if (ifp == NULL) { device_printf(dev, "can not if_alloc()\n"); error = ENOSPC; goto fail; } ifp->if_softc = sc; if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_mtu = ETHERMTU; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = sis_ioctl; ifp->if_start = sis_start; ifp->if_init = sis_init; IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1); ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1; IFQ_SET_READY(&ifp->if_snd); /* * Do MII setup. */ if (mii_phy_probe(dev, &sc->sis_miibus, sis_ifmedia_upd, sis_ifmedia_sts)) { device_printf(dev, "MII without any PHY!\n"); error = ENXIO; goto fail; } /* * Call MI attach routine. */ ether_ifattach(ifp, eaddr); /* * Tell the upper layer(s) we support long frames. */ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); ifp->if_capabilities |= IFCAP_VLAN_MTU; ifp->if_capenable = ifp->if_capabilities; #ifdef DEVICE_POLLING ifp->if_capabilities |= IFCAP_POLLING; #endif /* Hook interrupt last to avoid having to lock softc */ error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE, NULL, sis_intr, sc, &sc->sis_intrhand); if (error) { device_printf(dev, "couldn't set up irq\n"); ether_ifdetach(ifp); goto fail; } fail: if (error) sis_detach(dev); return (error); } /* * Shutdown hardware and free up resources. This can be called any * time after the mutex has been initialized. It is called in both * the error case in attach and the normal detach case so it needs * to be careful about only freeing resources that have actually been * allocated. */ static int sis_detach(device_t dev) { struct sis_softc *sc; struct ifnet *ifp; sc = device_get_softc(dev); KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); ifp = sc->sis_ifp; #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) ether_poll_deregister(ifp); #endif /* These should only be active if attach succeeded. */ if (device_is_attached(dev)) { SIS_LOCK(sc); sis_reset(sc); sis_stop(sc); SIS_UNLOCK(sc); callout_drain(&sc->sis_stat_ch); ether_ifdetach(ifp); } if (sc->sis_miibus) device_delete_child(dev, sc->sis_miibus); bus_generic_detach(dev); if (sc->sis_intrhand) bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand); bus_release_resources(dev, sis_res_spec, sc->sis_res); if (ifp) if_free(ifp); - if (sc->sis_rx_tag) { - bus_dmamap_unload(sc->sis_rx_tag, - sc->sis_rx_dmamap); - bus_dmamem_free(sc->sis_rx_tag, - sc->sis_rx_list, sc->sis_rx_dmamap); - bus_dma_tag_destroy(sc->sis_rx_tag); + sis_dma_free(sc); + + mtx_destroy(&sc->sis_mtx); + + return (0); +} + +struct sis_dmamap_arg { + bus_addr_t sis_busaddr; +}; + +static void +sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + struct sis_dmamap_arg *ctx; + + if (error != 0) + return; + + KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); + + ctx = (struct sis_dmamap_arg *)arg; + ctx->sis_busaddr = segs[0].ds_addr; +} + +static int +sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment, + bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, + bus_addr_t *paddr, const char *msg) +{ + struct sis_dmamap_arg ctx; + int error; + + error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0, + BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, + maxsize, 0, NULL, NULL, tag); + if (error != 0) { + device_printf(sc->sis_dev, + "could not create %s dma tag\n", msg); + return (ENOMEM); } - if (sc->sis_tx_tag) { - bus_dmamap_unload(sc->sis_tx_tag, - sc->sis_tx_dmamap); - bus_dmamem_free(sc->sis_tx_tag, - sc->sis_tx_list, sc->sis_tx_dmamap); - bus_dma_tag_destroy(sc->sis_tx_tag); + /* Allocate DMA'able memory for ring. */ + error = bus_dmamem_alloc(*tag, (void **)ring, + BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); + if (error != 0) { + device_printf(sc->sis_dev, + "could not allocate DMA'able memory for %s\n", msg); + return (ENOMEM); } - if (sc->sis_parent_tag) - bus_dma_tag_destroy(sc->sis_parent_tag); - if (sc->sis_tag) - bus_dma_tag_destroy(sc->sis_tag); + /* Load the address of the ring. */ + ctx.sis_busaddr = 0; + error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb, + &ctx, BUS_DMA_NOWAIT); + if (error != 0) { + device_printf(sc->sis_dev, + "could not load DMA'able memory for %s\n", msg); + return (ENOMEM); + } + *paddr = ctx.sis_busaddr; + return (0); +} - mtx_destroy(&sc->sis_mtx); +static int +sis_dma_alloc(struct sis_softc *sc) +{ + struct sis_rxdesc *rxd; + struct sis_txdesc *txd; + int error, i; + /* Allocate the parent bus DMA tag appropriate for PCI. */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev), + 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, + NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, + 0, NULL, NULL, &sc->sis_parent_tag); + if (error != 0) { + device_printf(sc->sis_dev, + "could not allocate parent dma tag\n"); + return (ENOMEM); + } + + /* Create RX ring. */ + error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ, + &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list, + &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring"); + if (error) + return (error); + + /* Create TX ring. */ + error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ, + &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list, + &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring"); + if (error) + return (error); + + /* Create tag for RX mbufs. */ + error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0, + BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, + MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag); + if (error) { + device_printf(sc->sis_dev, "could not allocate RX dma tag\n"); + return (error); + } + + /* Create tag for TX mbufs. */ + error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0, + BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, + MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, + &sc->sis_tx_tag); + if (error) { + device_printf(sc->sis_dev, "could not allocate TX dma tag\n"); + return (error); + } + + /* Create DMA maps for RX buffers. */ + error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap); + if (error) { + device_printf(sc->sis_dev, + "can't create spare DMA map for RX\n"); + return (error); + } + for (i = 0; i < SIS_RX_LIST_CNT; i++) { + rxd = &sc->sis_rxdesc[i]; + rxd->rx_m = NULL; + error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap); + if (error) { + device_printf(sc->sis_dev, + "can't create DMA map for RX\n"); + return (error); + } + } + + /* Create DMA maps for TX buffers. */ + for (i = 0; i < SIS_TX_LIST_CNT; i++) { + txd = &sc->sis_txdesc[i]; + txd->tx_m = NULL; + error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap); + if (error) { + device_printf(sc->sis_dev, + "can't create DMA map for TX\n"); + return (error); + } + } + return (0); } +static void +sis_dma_free(struct sis_softc *sc) +{ + struct sis_rxdesc *rxd; + struct sis_txdesc *txd; + int i; + + /* Destroy DMA maps for RX buffers. */ + for (i = 0; i < SIS_RX_LIST_CNT; i++) { + rxd = &sc->sis_rxdesc[i]; + if (rxd->rx_dmamap) + bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap); + } + if (sc->sis_rx_sparemap) + bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap); + + /* Destroy DMA maps for TX buffers. */ + for (i = 0; i < SIS_TX_LIST_CNT; i++) { + txd = &sc->sis_txdesc[i]; + if (txd->tx_dmamap) + bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap); + } + + if (sc->sis_rx_tag) + bus_dma_tag_destroy(sc->sis_rx_tag); + if (sc->sis_tx_tag) + bus_dma_tag_destroy(sc->sis_tx_tag); + + /* Destroy RX ring. */ + if (sc->sis_rx_list_map) + bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map); + if (sc->sis_rx_list_map && sc->sis_rx_list) + bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list, + sc->sis_rx_list_map); + + if (sc->sis_rx_list_tag) + bus_dma_tag_destroy(sc->sis_rx_list_tag); + + /* Destroy TX ring. */ + if (sc->sis_tx_list_map) + bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map); + + if (sc->sis_tx_list_map && sc->sis_tx_list) + bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list, + sc->sis_tx_list_map); + + if (sc->sis_tx_list_tag) + bus_dma_tag_destroy(sc->sis_tx_list_tag); + + /* Destroy the parent tag. */ + if (sc->sis_parent_tag) + bus_dma_tag_destroy(sc->sis_parent_tag); +} + /* * Initialize the TX and RX descriptors and allocate mbufs for them. Note that * we arrange the descriptors in a closed ring, so that the last descriptor * points back to the first. */ static int sis_ring_init(struct sis_softc *sc) { - int i, error; - struct sis_desc *dp; + struct sis_rxdesc *rxd; + struct sis_txdesc *txd; + bus_addr_t next; + int error, i; - dp = &sc->sis_tx_list[0]; - for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { - if (i == (SIS_TX_LIST_CNT - 1)) - dp->sis_nextdesc = &sc->sis_tx_list[0]; + bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ); + for (i = 0; i < SIS_TX_LIST_CNT; i++) { + txd = &sc->sis_txdesc[i]; + txd->tx_m = NULL; + if (i == SIS_TX_LIST_CNT - 1) + next = SIS_TX_RING_ADDR(sc, 0); else - dp->sis_nextdesc = dp + 1; - bus_dmamap_load(sc->sis_tx_tag, - sc->sis_tx_dmamap, - dp->sis_nextdesc, sizeof(struct sis_desc), - sis_dma_map_desc_next, dp, 0); - dp->sis_mbuf = NULL; - dp->sis_ptr = 0; - dp->sis_ctl = 0; + next = SIS_TX_RING_ADDR(sc, i + 1); + sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next)); } - sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0; + bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - bus_dmamap_sync(sc->sis_tx_tag, - sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE); - - dp = &sc->sis_rx_list[0]; - for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { - error = sis_newbuf(sc, dp, NULL); + sc->sis_rx_cons = 0; + bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ); + for (i = 0; i < SIS_RX_LIST_CNT; i++) { + rxd = &sc->sis_rxdesc[i]; + rxd->rx_desc = &sc->sis_rx_list[i]; + if (i == SIS_RX_LIST_CNT - 1) + next = SIS_RX_RING_ADDR(sc, 0); + else + next = SIS_RX_RING_ADDR(sc, i + 1); + rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next)); + error = sis_newbuf(sc, rxd); if (error) return (error); - if (i == (SIS_RX_LIST_CNT - 1)) - dp->sis_nextdesc = &sc->sis_rx_list[0]; - else - dp->sis_nextdesc = dp + 1; - bus_dmamap_load(sc->sis_rx_tag, - sc->sis_rx_dmamap, - dp->sis_nextdesc, sizeof(struct sis_desc), - sis_dma_map_desc_next, dp, 0); - } + } + bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - bus_dmamap_sync(sc->sis_rx_tag, - sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE); - - sc->sis_rx_pdsc = &sc->sis_rx_list[0]; - return (0); } /* * Initialize an RX descriptor and attach an MBUF cluster. */ static int -sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m) +sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd) { + struct mbuf *m; + bus_dma_segment_t segs[1]; + bus_dmamap_t map; + int nsegs; - if (c == NULL) - return (EINVAL); + m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (m == NULL) + return (ENOBUFS); + m->m_len = m->m_pkthdr.len = SIS_RXLEN; +#ifndef __NO_STRICT_ALIGNMENT + m_adj(m, SIS_RX_BUF_ALIGN); +#endif - if (m == NULL) { - m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); - if (m == NULL) - return (ENOBUFS); - } else - m->m_data = m->m_ext.ext_buf; + if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m, + segs, &nsegs, 0) != 0) { + m_freem(m); + return (ENOBUFS); + } + KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); - c->sis_mbuf = m; - c->sis_ctl = SIS_RXLEN; + if (rxd->rx_m != NULL) { + bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); + } + map = rxd->rx_dmamap; + rxd->rx_dmamap = sc->sis_rx_sparemap; + sc->sis_rx_sparemap = map; + bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD); + rxd->rx_m = m; + rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); + rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr)); + return (0); +} - bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); - bus_dmamap_load(sc->sis_tag, c->sis_map, - mtod(m, void *), MCLBYTES, - sis_dma_map_desc_ptr, c, 0); - bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD); +static __inline void +sis_discard_rxbuf(struct sis_rxdesc *rxd) +{ - return (0); + rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN); } +#ifndef __NO_STRICT_ALIGNMENT +static __inline void +sis_fixup_rx(struct mbuf *m) +{ + uint16_t *src, *dst; + int i; + + src = mtod(m, uint16_t *); + dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src); + + for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) + *dst++ = *src++; + + m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN; +} +#endif + /* * A frame has been uploaded: pass the resulting mbuf chain up to * the higher level protocols. */ static int sis_rxeof(struct sis_softc *sc) { - struct mbuf *m, *m0; + struct mbuf *m; struct ifnet *ifp; + struct sis_rxdesc *rxd; struct sis_desc *cur_rx; - int total_len = 0, rx_npkts = 0; - u_int32_t rxstat; + int prog, rx_cons, rx_npkts = 0, total_len; + uint32_t rxstat; SIS_LOCK_ASSERT(sc); + bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + rx_cons = sc->sis_rx_cons; ifp = sc->sis_ifp; - for (cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx); - cur_rx = cur_rx->sis_nextdesc) { - + for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; + SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) { #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) { if (sc->rxcycles <= 0) break; sc->rxcycles--; } #endif - rxstat = cur_rx->sis_rxstat; - bus_dmamap_sync(sc->sis_tag, - cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); - bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); - m = cur_rx->sis_mbuf; - cur_rx->sis_mbuf = NULL; - total_len = SIS_RXBYTES(cur_rx); + cur_rx = &sc->sis_rx_list[rx_cons]; + rxstat = le32toh(cur_rx->sis_cmdsts); + if ((rxstat & SIS_CMDSTS_OWN) == 0) + break; + rxd = &sc->sis_rxdesc[rx_cons]; - /* - * If an error occurs, update stats, clear the - * status word and leave the mbuf cluster in place: - * it should simply get re-used next time this descriptor - * comes up in the ring. - */ + total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN; if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 && total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) rxstat &= ~SIS_RXSTAT_GIANT; if (SIS_RXSTAT_ERROR(rxstat) != 0) { ifp->if_ierrors++; if (rxstat & SIS_RXSTAT_COLL) ifp->if_collisions++; - sis_newbuf(sc, cur_rx, m); + sis_discard_rxbuf(rxd); continue; } + /* Add a new receive buffer to the ring. */ + m = rxd->rx_m; + if (sis_newbuf(sc, rxd) != 0) { + ifp->if_iqdrops++; + sis_discard_rxbuf(rxd); + continue; + } + /* No errors; receive the packet. */ -#ifdef __NO_STRICT_ALIGNMENT + m->m_pkthdr.len = m->m_len = total_len; +#ifndef __NO_STRICT_ALIGNMENT /* * On architectures without alignment problems we try to * allocate a new buffer for the receive ring, and pass up * the one where the packet is already, saving the expensive - * copy done in m_devget(). - * If we are on an architecture with alignment problems, or - * if the allocation fails, then use m_devget and leave the - * existing buffer in the receive ring. + * copy operation. */ - if (sis_newbuf(sc, cur_rx, NULL) == 0) - m->m_pkthdr.len = m->m_len = total_len; - else + sis_fixup_rx(m); #endif - { - m0 = m_devget(mtod(m, char *), total_len, - ETHER_ALIGN, ifp, NULL); - sis_newbuf(sc, cur_rx, m); - if (m0 == NULL) { - ifp->if_ierrors++; - continue; - } - m = m0; - } - ifp->if_ipackets++; m->m_pkthdr.rcvif = ifp; SIS_UNLOCK(sc); (*ifp->if_input)(ifp, m); SIS_LOCK(sc); rx_npkts++; } - sc->sis_rx_pdsc = cur_rx; + if (prog > 0) { + sc->sis_rx_cons = rx_cons; + bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + return (rx_npkts); } /* * A frame was downloaded to the chip. It's safe for us to clean up * the list buffers. */ static void sis_txeof(struct sis_softc *sc) { struct ifnet *ifp; - u_int32_t idx; + struct sis_desc *cur_tx; + struct sis_txdesc *txd; + uint32_t cons, txstat; SIS_LOCK_ASSERT(sc); + + cons = sc->sis_tx_cons; + if (cons == sc->sis_tx_prod) + return; + ifp = sc->sis_ifp; + bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); /* * Go through our tx list and free mbufs for those * frames that have been transmitted. */ - for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0; - sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { - struct sis_desc *cur_tx = &sc->sis_tx_list[idx]; - - if (SIS_OWNDESC(cur_tx)) + for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) { + cur_tx = &sc->sis_tx_list[cons]; + txstat = le32toh(cur_tx->sis_cmdsts); + if ((txstat & SIS_CMDSTS_OWN) != 0) break; - - if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) - continue; - - if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { - ifp->if_oerrors++; - if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) - ifp->if_collisions++; - if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) - ifp->if_collisions++; + txd = &sc->sis_txdesc[cons]; + if (txd->tx_m != NULL) { + bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); + m_freem(txd->tx_m); + txd->tx_m = NULL; + if ((txstat & SIS_CMDSTS_PKT_OK) != 0) { + ifp->if_opackets++; + ifp->if_collisions += + (txstat & SIS_TXSTAT_COLLCNT) >> 16; + } else { + ifp->if_oerrors++; + if (txstat & SIS_TXSTAT_EXCESSCOLLS) + ifp->if_collisions++; + if (txstat & SIS_TXSTAT_OUTOFWINCOLL) + ifp->if_collisions++; + } } - - ifp->if_collisions += - (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; - - ifp->if_opackets++; - if (cur_tx->sis_mbuf != NULL) { - m_freem(cur_tx->sis_mbuf); - cur_tx->sis_mbuf = NULL; - bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); - bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); - } - } - - if (idx != sc->sis_tx_cons) { - /* we freed up some buffers */ - sc->sis_tx_cons = idx; + sc->sis_tx_cnt--; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; } - - sc->sis_watchdog_timer = (sc->sis_tx_cnt == 0) ? 0 : 5; + sc->sis_tx_cons = cons; + if (sc->sis_tx_cnt == 0) + sc->sis_watchdog_timer = 0; } static void sis_tick(void *xsc) { struct sis_softc *sc; struct mii_data *mii; struct ifnet *ifp; sc = xsc; SIS_LOCK_ASSERT(sc); sc->in_tick = 1; ifp = sc->sis_ifp; mii = device_get_softc(sc->sis_miibus); mii_tick(mii); sis_watchdog(sc); if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { sc->sis_link++; if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) sis_startl(ifp); } callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); sc->in_tick = 0; } #ifdef DEVICE_POLLING static poll_handler_t sis_poll; static int sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct sis_softc *sc = ifp->if_softc; int rx_npkts = 0; SIS_LOCK(sc); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { SIS_UNLOCK(sc); return (rx_npkts); } /* * On the sis, reading the status register also clears it. * So before returning to intr mode we must make sure that all * possible pending sources of interrupts have been served. * In practice this means run to completion the *eof routines, * and then call the interrupt routine */ sc->rxcycles = count; rx_npkts = sis_rxeof(sc); sis_txeof(sc); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) sis_startl(ifp); if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { u_int32_t status; /* Reading the ISR register clears all interrupts. */ status = CSR_READ_4(sc, SIS_ISR); if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) ifp->if_ierrors++; if (status & (SIS_ISR_RX_IDLE)) SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); if (status & SIS_ISR_SYSERR) { sis_reset(sc); sis_initl(sc); } } SIS_UNLOCK(sc); return (rx_npkts); } #endif /* DEVICE_POLLING */ static void sis_intr(void *arg) { struct sis_softc *sc; struct ifnet *ifp; u_int32_t status; sc = arg; ifp = sc->sis_ifp; if (sc->sis_stopped) /* Most likely shared interrupt */ return; SIS_LOCK(sc); #ifdef DEVICE_POLLING if (ifp->if_capenable & IFCAP_POLLING) { SIS_UNLOCK(sc); return; } #endif /* Disable interrupts. */ CSR_WRITE_4(sc, SIS_IER, 0); for (;;) { SIS_LOCK_ASSERT(sc); /* Reading the ISR register clears all interrupts. */ status = CSR_READ_4(sc, SIS_ISR); if ((status & SIS_INTRS) == 0) break; if (status & (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) sis_txeof(sc); if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE)) sis_rxeof(sc); if (status & SIS_ISR_RX_OFLOW) ifp->if_ierrors++; if (status & (SIS_ISR_RX_IDLE)) SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); if (status & SIS_ISR_SYSERR) { sis_reset(sc); sis_initl(sc); } } /* Re-enable interrupts. */ CSR_WRITE_4(sc, SIS_IER, 1); if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) sis_startl(ifp); SIS_UNLOCK(sc); } /* * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data * pointers to the fragment pointers. */ static int -sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx) +sis_encap(struct sis_softc *sc, struct mbuf **m_head) { - struct sis_desc *f = NULL; struct mbuf *m; - int frag, cur, cnt = 0, chainlen = 0; + struct sis_txdesc *txd; + struct sis_desc *f; + bus_dma_segment_t segs[SIS_MAXTXSEGS]; + bus_dmamap_t map; + int error, i, frag, nsegs, prod; - /* - * If there's no way we can send any packets, return now. - */ - if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2) - return (ENOBUFS); - - /* - * Count the number of frags in this chain to see if - * we need to m_defrag. Since the descriptor list is shared - * by all packets, we'll m_defrag long chains so that they - * do not use up the entire list, even if they would fit. - */ - - for (m = *m_head; m != NULL; m = m->m_next) - chainlen++; - - if ((chainlen > SIS_TX_LIST_CNT / 4) || - ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) { - m = m_defrag(*m_head, M_DONTWAIT); - if (m == NULL) + prod = sc->sis_tx_prod; + txd = &sc->sis_txdesc[prod]; + error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, + *m_head, segs, &nsegs, 0); + if (error == EFBIG) { + m = m_collapse(*m_head, M_DONTWAIT, SIS_MAXTXSEGS); + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; return (ENOBUFS); + } *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap, + *m_head, segs, &nsegs, 0); + if (error != 0) { + m_freem(*m_head); + *m_head = NULL; + return (error); + } + } else if (error != 0) + return (error); + + /* Check for descriptor overruns. */ + if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) { + bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); + return (ENOBUFS); } - /* - * Start packing the mbufs in this chain into - * the fragment pointers. Stop when we run out - * of fragments or hit the end of the mbuf chain. - */ - cur = frag = *txidx; + bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE); - for (m = *m_head; m != NULL; m = m->m_next) { - if (m->m_len != 0) { - if ((SIS_TX_LIST_CNT - - (sc->sis_tx_cnt + cnt)) < 2) - return (ENOBUFS); - f = &sc->sis_tx_list[frag]; - f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; - bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); - bus_dmamap_load(sc->sis_tag, f->sis_map, - mtod(m, void *), m->m_len, - sis_dma_map_desc_ptr, f, 0); - bus_dmamap_sync(sc->sis_tag, - f->sis_map, BUS_DMASYNC_PREREAD); - if (cnt != 0) - f->sis_ctl |= SIS_CMDSTS_OWN; - cur = frag; - SIS_INC(frag, SIS_TX_LIST_CNT); - cnt++; - } + frag = prod; + for (i = 0; i < nsegs; i++) { + f = &sc->sis_tx_list[prod]; + if (i == 0) + f->sis_cmdsts = htole32(segs[i].ds_len | + SIS_CMDSTS_MORE); + else + f->sis_cmdsts = htole32(segs[i].ds_len | + SIS_CMDSTS_OWN | SIS_CMDSTS_MORE); + f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr)); + SIS_INC(prod, SIS_TX_LIST_CNT); + sc->sis_tx_cnt++; } - if (m != NULL) - return (ENOBUFS); + /* Update producer index. */ + sc->sis_tx_prod = prod; - sc->sis_tx_list[cur].sis_mbuf = *m_head; - sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; - sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; - sc->sis_tx_cnt += cnt; - *txidx = frag; + /* Remove MORE flag on the last descriptor. */ + prod = (prod - 1) & (SIS_TX_LIST_CNT - 1); + f = &sc->sis_tx_list[prod]; + f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE); + /* Lastly transfer ownership of packet to the controller. */ + f = &sc->sis_tx_list[frag]; + f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN); + + /* Swap the last and the first dmamaps. */ + map = txd->tx_dmamap; + txd->tx_dmamap = sc->sis_txdesc[frag].tx_dmamap; + sc->sis_txdesc[frag].tx_dmamap = map; + txd->tx_m = *m_head; + return (0); } -/* - * Main transmit routine. To avoid having to do mbuf copies, we put pointers - * to the mbuf data regions directly in the transmit lists. We also save a - * copy of the pointers since the transmit list fragment pointers are - * physical addresses. - */ - static void sis_start(struct ifnet *ifp) { struct sis_softc *sc; sc = ifp->if_softc; SIS_LOCK(sc); sis_startl(ifp); SIS_UNLOCK(sc); } static void sis_startl(struct ifnet *ifp) { struct sis_softc *sc; - struct mbuf *m_head = NULL; - u_int32_t idx, queued = 0; + struct mbuf *m_head; + int queued; sc = ifp->if_softc; SIS_LOCK_ASSERT(sc); - if (!sc->sis_link) + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING || sc->sis_link == 0) return; - idx = sc->sis_tx_prod; - - if (ifp->if_drv_flags & IFF_DRV_OACTIVE) - return; - - while (sc->sis_tx_list[idx].sis_mbuf == NULL) { + for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && + sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); if (m_head == NULL) break; - if (sis_encap(sc, &m_head, &idx)) { + if (sis_encap(sc, &m_head) != 0) { + if (m_head == NULL) + break; IFQ_DRV_PREPEND(&ifp->if_snd, m_head); ifp->if_drv_flags |= IFF_DRV_OACTIVE; break; } queued++; /* * If there's a BPF listener, bounce a copy of this frame * to him. */ BPF_MTAP(ifp, m_head); - } if (queued) { /* Transmit */ - sc->sis_tx_prod = idx; + bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); /* * Set a timeout in case the chip goes out to lunch. */ sc->sis_watchdog_timer = 5; } } static void sis_init(void *xsc) { struct sis_softc *sc = xsc; SIS_LOCK(sc); sis_initl(sc); SIS_UNLOCK(sc); } static void sis_initl(struct sis_softc *sc) { struct ifnet *ifp = sc->sis_ifp; struct mii_data *mii; SIS_LOCK_ASSERT(sc); /* * Cancel pending I/O and free all RX/TX buffers. */ sis_stop(sc); sc->sis_stopped = 0; #ifdef notyet if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { /* * Configure 400usec of interrupt holdoff. This is based * on emperical tests on a Soekris 4801. */ CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); } #endif mii = device_get_softc(sc->sis_miibus); /* Set MAC address */ if (sc->sis_type == SIS_TYPE_83815) { CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]); CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]); CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]); } else { CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]); } /* Init circular TX/RX lists. */ if (sis_ring_init(sc) != 0) { device_printf(sc->sis_dev, "initialization failed: no memory for rx buffers\n"); sis_stop(sc); return; } /* * Short Cable Receive Errors (MP21.E) * also: Page 78 of the DP83815 data sheet (september 2002 version) * recommends the following register settings "for optimum * performance." for rev 15C. Set this also for 15D parts as * they require it in practice. */ if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) { CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); /* set val for c2 */ CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); /* load/kill c2 */ CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); /* rais SD off, from 4 to c */ CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); CSR_WRITE_4(sc, NS_PHY_PAGE, 0); } /* * For the NatSemi chip, we have to explicitly enable the * reception of ARP frames, as well as turn on the 'perfect * match' filter where we store the station address, otherwise * we won't receive unicasts meant for this host. */ if (sc->sis_type == SIS_TYPE_83815) { SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); } /* If we want promiscuous mode, set the allframes bit. */ if (ifp->if_flags & IFF_PROMISC) { SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); } else { SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); } /* * Set the capture broadcast bit to capture broadcast frames. */ if (ifp->if_flags & IFF_BROADCAST) { SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); } else { SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); } /* * Load the multicast filter. */ if (sc->sis_type == SIS_TYPE_83815) sis_setmulti_ns(sc); else sis_setmulti_sis(sc); /* Turn the receive filter on */ SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); /* * Load the address of the RX and TX lists. */ - CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr); - CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr); + CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr)); + CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr)); /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of * the PCI bus. When this bit is set, the Max DMA Burst Size * for TX/RX DMA should be no larger than 16 double words. */ if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); } else { CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); } /* Accept Long Packets for VLAN support */ SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); /* Set TX configuration */ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); } else { CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); } /* Set full/half duplex mode. */ if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { SIS_SETBIT(sc, SIS_TX_CFG, (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); } else { SIS_CLRBIT(sc, SIS_TX_CFG, (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); } if (sc->sis_type == SIS_TYPE_83816) { /* * MPII03.D: Half Duplex Excessive Collisions. * Also page 49 in 83816 manual */ SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D); } if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && - IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { + IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { uint32_t reg; /* * Short Cable Receive Errors (MP21.E) */ CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); DELAY(100); reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { device_printf(sc->sis_dev, "Applying short cable fix (reg=%x)\n", reg); CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); } CSR_WRITE_4(sc, NS_PHY_PAGE, 0); } /* * Enable interrupts. */ CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); #ifdef DEVICE_POLLING /* * ... only enable interrupts if we are not polling, make sure * they are off otherwise. */ if (ifp->if_capenable & IFCAP_POLLING) CSR_WRITE_4(sc, SIS_IER, 0); else #endif CSR_WRITE_4(sc, SIS_IER, 1); /* Enable receiver and transmitter. */ SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); #ifdef notdef mii_mediachg(mii); #endif ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (!sc->in_tick) callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); } /* * Set media options. */ static int sis_ifmedia_upd(struct ifnet *ifp) { struct sis_softc *sc; struct mii_data *mii; sc = ifp->if_softc; SIS_LOCK(sc); mii = device_get_softc(sc->sis_miibus); sc->sis_link = 0; if (mii->mii_instance) { struct mii_softc *miisc; LIST_FOREACH(miisc, &mii->mii_phys, mii_list) mii_phy_reset(miisc); } mii_mediachg(mii); SIS_UNLOCK(sc); return (0); } /* * Report current media status. */ static void sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct sis_softc *sc; struct mii_data *mii; sc = ifp->if_softc; SIS_LOCK(sc); mii = device_get_softc(sc->sis_miibus); mii_pollstat(mii); SIS_UNLOCK(sc); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; } static int sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { struct sis_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *) data; struct mii_data *mii; int error = 0; switch (command) { case SIOCSIFFLAGS: SIS_LOCK(sc); if (ifp->if_flags & IFF_UP) { sis_initl(sc); } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { sis_stop(sc); } SIS_UNLOCK(sc); error = 0; break; case SIOCADDMULTI: case SIOCDELMULTI: SIS_LOCK(sc); if (sc->sis_type == SIS_TYPE_83815) sis_setmulti_ns(sc); else sis_setmulti_sis(sc); SIS_UNLOCK(sc); error = 0; break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: mii = device_get_softc(sc->sis_miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); break; case SIOCSIFCAP: /* ok, disable interrupts */ #ifdef DEVICE_POLLING if (ifr->ifr_reqcap & IFCAP_POLLING && !(ifp->if_capenable & IFCAP_POLLING)) { error = ether_poll_register(sis_poll, ifp); if (error) return (error); SIS_LOCK(sc); /* Disable interrupts */ CSR_WRITE_4(sc, SIS_IER, 0); ifp->if_capenable |= IFCAP_POLLING; SIS_UNLOCK(sc); return (error); } if (!(ifr->ifr_reqcap & IFCAP_POLLING) && ifp->if_capenable & IFCAP_POLLING) { error = ether_poll_deregister(ifp); /* Enable interrupts. */ SIS_LOCK(sc); CSR_WRITE_4(sc, SIS_IER, 1); ifp->if_capenable &= ~IFCAP_POLLING; SIS_UNLOCK(sc); return (error); } #endif /* DEVICE_POLLING */ break; default: error = ether_ioctl(ifp, command, data); break; } return (error); } static void sis_watchdog(struct sis_softc *sc) { SIS_LOCK_ASSERT(sc); if (sc->sis_stopped) { SIS_UNLOCK(sc); return; } if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0) return; device_printf(sc->sis_dev, "watchdog timeout\n"); sc->sis_ifp->if_oerrors++; sis_stop(sc); sis_reset(sc); sis_initl(sc); if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd)) sis_startl(sc->sis_ifp); } /* * Stop the adapter and free any mbufs allocated to the * RX and TX lists. */ static void sis_stop(struct sis_softc *sc) { - int i; struct ifnet *ifp; - struct sis_desc *dp; + struct sis_rxdesc *rxd; + struct sis_txdesc *txd; + int i; if (sc->sis_stopped) return; SIS_LOCK_ASSERT(sc); ifp = sc->sis_ifp; sc->sis_watchdog_timer = 0; callout_stop(&sc->sis_stat_ch); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); CSR_WRITE_4(sc, SIS_IER, 0); CSR_WRITE_4(sc, SIS_IMR, 0); CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */ SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); DELAY(1000); CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); sc->sis_link = 0; /* * Free data in the RX lists. */ - dp = &sc->sis_rx_list[0]; - for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) { - if (dp->sis_mbuf == NULL) - continue; - bus_dmamap_unload(sc->sis_tag, dp->sis_map); - bus_dmamap_destroy(sc->sis_tag, dp->sis_map); - m_freem(dp->sis_mbuf); - dp->sis_mbuf = NULL; + for (i = 0; i < SIS_RX_LIST_CNT; i++) { + rxd = &sc->sis_rxdesc[i]; + if (rxd->rx_m != NULL) { + bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap); + m_freem(rxd->rx_m); + rxd->rx_m = NULL; + } } - bzero(sc->sis_rx_list, SIS_RX_LIST_SZ); /* * Free the TX list buffers. */ - dp = &sc->sis_tx_list[0]; - for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) { - if (dp->sis_mbuf == NULL) - continue; - bus_dmamap_unload(sc->sis_tag, dp->sis_map); - bus_dmamap_destroy(sc->sis_tag, dp->sis_map); - m_freem(dp->sis_mbuf); - dp->sis_mbuf = NULL; + for (i = 0; i < SIS_TX_LIST_CNT; i++) { + txd = &sc->sis_txdesc[i]; + if (txd->tx_m != NULL) { + bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap); + m_freem(txd->tx_m); + txd->tx_m = NULL; + } } - - bzero(sc->sis_tx_list, SIS_TX_LIST_SZ); sc->sis_stopped = 1; } /* * Stop all chip I/O so that the kernel's probe routines don't * get confused by errant DMAs when rebooting. */ static int sis_shutdown(device_t dev) { struct sis_softc *sc; sc = device_get_softc(dev); SIS_LOCK(sc); sis_reset(sc); sis_stop(sc); SIS_UNLOCK(sc); return (0); } static device_method_t sis_methods[] = { /* Device interface */ DEVMETHOD(device_probe, sis_probe), DEVMETHOD(device_attach, sis_attach), DEVMETHOD(device_detach, sis_detach), DEVMETHOD(device_shutdown, sis_shutdown), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* MII interface */ DEVMETHOD(miibus_readreg, sis_miibus_readreg), DEVMETHOD(miibus_writereg, sis_miibus_writereg), DEVMETHOD(miibus_statchg, sis_miibus_statchg), { 0, 0 } }; static driver_t sis_driver = { "sis", sis_methods, sizeof(struct sis_softc) }; static devclass_t sis_devclass; DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); Index: head/sys/dev/sis/if_sisreg.h =================================================================== --- head/sys/dev/sis/if_sisreg.h (revision 212108) +++ head/sys/dev/sis/if_sisreg.h (revision 212109) @@ -1,512 +1,523 @@ /*- * Copyright (c) 1997, 1998, 1999 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* * Register definitions for the SiS 900 and SiS 7016 chipsets. The * 7016 is actually an older chip and some of its registers differ * from the 900, however the core operational registers are the same: * the differences lie in the OnNow/Wake on LAN stuff which we don't * use anyway. The 7016 needs an external MII compliant PHY while the * SiS 900 has one built in. All registers are 32-bits wide. */ /* Registers common to SiS 900 and SiS 7016 */ #define SIS_CSR 0x00 #define SIS_CFG 0x04 #define SIS_EECTL 0x08 #define SIS_PCICTL 0x0C #define SIS_ISR 0x10 #define SIS_IMR 0x14 #define SIS_IER 0x18 #define SIS_PHYCTL 0x1C #define SIS_TX_LISTPTR 0x20 #define SIS_TX_CFG 0x24 #define SIS_RX_LISTPTR 0x30 #define SIS_RX_CFG 0x34 #define SIS_FLOWCTL 0x38 #define SIS_RXFILT_CTL 0x48 #define SIS_RXFILT_DATA 0x4C #define SIS_PWRMAN_CTL 0xB0 #define SIS_PWERMAN_WKUP_EVENT 0xB4 #define SIS_WKUP_FRAME_CRC 0xBC #define SIS_WKUP_FRAME_MASK0 0xC0 #define SIS_WKUP_FRAME_MASKXX 0xEC /* SiS 7016 specific registers */ #define SIS_SILICON_REV 0x5C #define SIS_MIB_CTL0 0x60 #define SIS_MIB_CTL1 0x64 #define SIS_MIB_CTL2 0x68 #define SIS_MIB_CTL3 0x6C #define SIS_MIB 0x80 #define SIS_LINKSTS 0xA0 #define SIS_TIMEUNIT 0xA4 #define SIS_GPIO 0xB8 /* NS DP83815/6 registers */ #define NS_IHR 0x1C #define NS_CLKRUN 0x3C #define NS_SRR 0x58 #define NS_BMCR 0x80 #define NS_BMSR 0x84 #define NS_PHYIDR1 0x88 #define NS_PHYIDR2 0x8C #define NS_ANAR 0x90 #define NS_ANLPAR 0x94 #define NS_ANER 0x98 #define NS_ANNPTR 0x9C #define NS_PHY_CR 0xE4 #define NS_PHY_10BTSCR 0xE8 #define NS_PHY_PAGE 0xCC #define NS_PHY_EXTCFG 0xF0 #define NS_PHY_DSPCFG 0xF4 #define NS_PHY_SDCFG 0xF8 #define NS_PHY_TDATA 0xFC #define NS_CLKRUN_PMESTS 0x00008000 #define NS_CLKRUN_PMEENB 0x00000100 #define NS_CLNRUN_CLKRUN_ENB 0x00000001 /* NS silicon revisions */ #define NS_SRR_15C 0x302 #define NS_SRR_15D 0x403 #define NS_SRR_16A 0x505 #define SIS_CSR_TX_ENABLE 0x00000001 #define SIS_CSR_TX_DISABLE 0x00000002 #define SIS_CSR_RX_ENABLE 0x00000004 #define SIS_CSR_RX_DISABLE 0x00000008 #define SIS_CSR_TX_RESET 0x00000010 #define SIS_CSR_RX_RESET 0x00000020 #define SIS_CSR_SOFTINTR 0x00000080 #define SIS_CSR_RESET 0x00000100 #define SIS_CSR_ACCESS_MODE 0x00000200 #define SIS_CSR_RELOAD 0x00000400 #define SIS_CFG_BIGENDIAN 0x00000001 #define SIS_CFG_PERR_DETECT 0x00000008 #define SIS_CFG_DEFER_DISABLE 0x00000010 #define SIS_CFG_OUTOFWIN_TIMER 0x00000020 #define SIS_CFG_SINGLE_BACKOFF 0x00000040 #define SIS_CFG_PCIREQ_ALG 0x00000080 #define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */ #define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */ #define SIS_CFG_EDB_MASTER_EN 0x00002000 #define SIS_EECTL_DIN 0x00000001 #define SIS_EECTL_DOUT 0x00000002 #define SIS_EECTL_CLK 0x00000004 #define SIS_EECTL_CSEL 0x00000008 #define SIS_MII_CLK 0x00000040 #define SIS_MII_DIR 0x00000020 #define SIS_MII_DATA 0x00000010 #define SIS_EECMD_WRITE 0x140 #define SIS_EECMD_READ 0x180 #define SIS_EECMD_ERASE 0x1c0 /* * EEPROM Commands for SiS96x * chipsets. */ #define SIS_EECMD_REQ 0x00000400 #define SIS_EECMD_DONE 0x00000200 #define SIS_EECMD_GNT 0x00000100 #define SIS_EE_NODEADDR 0x8 #define NS_EE_NODEADDR 0x6 #define SIS_PCICTL_SRAMADDR 0x0000001F #define SIS_PCICTL_RAMTSTENB 0x00000020 #define SIS_PCICTL_TXTSTENB 0x00000040 #define SIS_PCICTL_RXTSTENB 0x00000080 #define SIS_PCICTL_BMTSTENB 0x00000200 #define SIS_PCICTL_RAMADDR 0x001F0000 #define SIS_PCICTL_ROMTIME 0x0F000000 #define SIS_PCICTL_DISCTEST 0x40000000 #define SIS_ISR_RX_OK 0x00000001 #define SIS_ISR_RX_DESC_OK 0x00000002 #define SIS_ISR_RX_ERR 0x00000004 #define SIS_ISR_RX_EARLY 0x00000008 #define SIS_ISR_RX_IDLE 0x00000010 #define SIS_ISR_RX_OFLOW 0x00000020 #define SIS_ISR_TX_OK 0x00000040 #define SIS_ISR_TX_DESC_OK 0x00000080 #define SIS_ISR_TX_ERR 0x00000100 #define SIS_ISR_TX_IDLE 0x00000200 #define SIS_ISR_TX_UFLOW 0x00000400 #define SIS_ISR_SOFTINTR 0x00000800 #define SIS_ISR_HIBITS 0x00008000 #define SIS_ISR_RX_FIFO_OFLOW 0x00010000 #define SIS_ISR_TGT_ABRT 0x00100000 #define SIS_ISR_BM_ABRT 0x00200000 #define SIS_ISR_SYSERR 0x00400000 #define SIS_ISR_PARITY_ERR 0x00800000 #define SIS_ISR_RX_RESET_DONE 0x01000000 #define SIS_ISR_TX_RESET_DONE 0x02000000 #define SIS_ISR_TX_PAUSE_START 0x04000000 #define SIS_ISR_TX_PAUSE_DONE 0x08000000 #define SIS_ISR_WAKE_EVENT 0x10000000 #define SIS_IMR_RX_OK 0x00000001 #define SIS_IMR_RX_DESC_OK 0x00000002 #define SIS_IMR_RX_ERR 0x00000004 #define SIS_IMR_RX_EARLY 0x00000008 #define SIS_IMR_RX_IDLE 0x00000010 #define SIS_IMR_RX_OFLOW 0x00000020 #define SIS_IMR_TX_OK 0x00000040 #define SIS_IMR_TX_DESC_OK 0x00000080 #define SIS_IMR_TX_ERR 0x00000100 #define SIS_IMR_TX_IDLE 0x00000200 #define SIS_IMR_TX_UFLOW 0x00000400 #define SIS_IMR_SOFTINTR 0x00000800 #define SIS_IMR_HIBITS 0x00008000 #define SIS_IMR_RX_FIFO_OFLOW 0x00010000 #define SIS_IMR_TGT_ABRT 0x00100000 #define SIS_IMR_BM_ABRT 0x00200000 #define SIS_IMR_SYSERR 0x00400000 #define SIS_IMR_PARITY_ERR 0x00800000 #define SIS_IMR_RX_RESET_DONE 0x01000000 #define SIS_IMR_TX_RESET_DONE 0x02000000 #define SIS_IMR_TX_PAUSE_START 0x04000000 #define SIS_IMR_TX_PAUSE_DONE 0x08000000 #define SIS_IMR_WAKE_EVENT 0x10000000 #define SIS_INTRS \ (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ SIS_IMR_RX_IDLE|\ SIS_IMR_SYSERR) #define SIS_IER_INTRENB 0x00000001 #define SIS_PHYCTL_ACCESS 0x00000010 #define SIS_PHYCTL_OP 0x00000020 #define SIS_PHYCTL_REGADDR 0x000007C0 #define SIS_PHYCTL_PHYADDR 0x0000F800 #define SIS_PHYCTL_PHYDATA 0xFFFF0000 #define SIS_PHYOP_READ 0x00000020 #define SIS_PHYOP_WRITE 0x00000000 #define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ #define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ #define SIS_TXCFG_DMABURST 0x00700000 #define SIS_TXCFG_AUTOPAD 0x10000000 #define SIS_TXCFG_LOOPBK 0x20000000 #define SIS_TXCFG_IGN_HBEAT 0x40000000 #define SIS_TXCFG_IGN_CARR 0x80000000 #define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) #define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) #define SIS_TXDMA_512BYTES 0x00000000 #define SIS_TXDMA_4BYTES 0x00100000 #define SIS_TXDMA_8BYTES 0x00200000 #define SIS_TXDMA_16BYTES 0x00300000 #define SIS_TXDMA_32BYTES 0x00400000 #define SIS_TXDMA_64BYTES 0x00500000 #define SIS_TXDMA_128BYTES 0x00600000 #define SIS_TXDMA_256BYTES 0x00700000 #define SIS_TXCFG_100 \ (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) #define SIS_TXCFG_10 \ (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\ SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) #define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ #define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */ #define SIS_RXCFG_DMABURST 0x00700000 #define SIS_RXCFG_RX_JABBER 0x08000000 #define SIS_RXCFG_RX_TXPKTS 0x10000000 #define SIS_RXCFG_RX_RUNTS 0x40000000 #define SIS_RXCFG_RX_GIANTS 0x80000000 #define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) #define SIS_RXDMA_512BYTES 0x00000000 #define SIS_RXDMA_4BYTES 0x00100000 #define SIS_RXDMA_8BYTES 0x00200000 #define SIS_RXDMA_16BYTES 0x00300000 #define SIS_RXDMA_32BYTES 0x00400000 #define SIS_RXDMA_64BYTES 0x00500000 #define SIS_RXDMA_128BYTES 0x00600000 #define SIS_RXDMA_256BYTES 0x00700000 #define SIS_RXCFG256 \ (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES) #define SIS_RXCFG64 \ (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES) #define SIS_RXFILTCTL_ADDR 0x000F0000 #define NS_RXFILTCTL_MCHASH 0x00200000 #define NS_RXFILTCTL_ARP 0x00400000 #define NS_RXFILTCTL_PERFECT 0x08000000 #define SIS_RXFILTCTL_ALLPHYS 0x10000000 #define SIS_RXFILTCTL_ALLMULTI 0x20000000 #define SIS_RXFILTCTL_BROAD 0x40000000 #define SIS_RXFILTCTL_ENABLE 0x80000000 #define SIS_FILTADDR_PAR0 0x00000000 #define SIS_FILTADDR_PAR1 0x00010000 #define SIS_FILTADDR_PAR2 0x00020000 #define SIS_FILTADDR_MAR0 0x00040000 #define SIS_FILTADDR_MAR1 0x00050000 #define SIS_FILTADDR_MAR2 0x00060000 #define SIS_FILTADDR_MAR3 0x00070000 #define SIS_FILTADDR_MAR4 0x00080000 #define SIS_FILTADDR_MAR5 0x00090000 #define SIS_FILTADDR_MAR6 0x000A0000 #define SIS_FILTADDR_MAR7 0x000B0000 #define NS_FILTADDR_PAR0 0x00000000 #define NS_FILTADDR_PAR1 0x00000002 #define NS_FILTADDR_PAR2 0x00000004 #define NS_FILTADDR_FMEM_LO 0x00000200 #define NS_FILTADDR_FMEM_HI 0x000003FE /* - * DMA descriptor structures. The first part of the descriptor - * is the hardware descriptor format, which is just three longwords. - * After this, we include some additional structure members for - * use by the driver. Note that for this structure will be a different - * size on the alpha, but that's okay as long as it's a multiple of 4 - * bytes in size. + * TX/RX DMA descriptor structures. */ struct sis_desc { /* SiS hardware descriptor section */ u_int32_t sis_next; u_int32_t sis_cmdsts; -#define sis_rxstat sis_cmdsts -#define sis_txstat sis_cmdsts -#define sis_ctl sis_cmdsts u_int32_t sis_ptr; - /* Driver software section */ - struct mbuf *sis_mbuf; - struct sis_desc *sis_nextdesc; - bus_dmamap_t sis_map; }; #define SIS_CMDSTS_BUFLEN 0x00000FFF #define SIS_CMDSTS_PKT_OK 0x08000000 #define SIS_CMDSTS_CRC 0x10000000 #define SIS_CMDSTS_INTR 0x20000000 #define SIS_CMDSTS_MORE 0x40000000 #define SIS_CMDSTS_OWN 0x80000000 -#define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE)) -#define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN) -#define SIS_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 -#define SIS_RXBYTES(x) (((x)->sis_ctl & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN) - #define SIS_RXSTAT_COLL 0x00010000 #define SIS_RXSTAT_LOOPBK 0x00020000 #define SIS_RXSTAT_ALIGNERR 0x00040000 #define SIS_RXSTAT_CRCERR 0x00080000 #define SIS_RXSTAT_SYMBOLERR 0x00100000 #define SIS_RXSTAT_RUNT 0x00200000 #define SIS_RXSTAT_GIANT 0x00400000 #define SIS_RXSTAT_DSTCLASS 0x01800000 #define SIS_RXSTAT_OVERRUN 0x02000000 #define SIS_RXSTAT_RX_ABORT 0x04000000 #define SIS_RXSTAT_ERROR(x) \ ((x) & (SIS_RXSTAT_RX_ABORT | SIS_RXSTAT_OVERRUN | \ SIS_RXSTAT_GIANT | SIS_RXSTAT_SYMBOLERR | SIS_RXSTAT_RUNT | \ SIS_RXSTAT_CRCERR | SIS_RXSTAT_ALIGNERR)) #define SIS_DSTCLASS_REJECT 0x00000000 #define SIS_DSTCLASS_UNICAST 0x00800000 #define SIS_DSTCLASS_MULTICAST 0x01000000 #define SIS_DSTCLASS_BROADCAST 0x02000000 #define SIS_TXSTAT_COLLCNT 0x000F0000 #define SIS_TXSTAT_EXCESSCOLLS 0x00100000 #define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 #define SIS_TXSTAT_EXCESS_DEFER 0x00400000 #define SIS_TXSTAT_DEFERED 0x00800000 #define SIS_TXSTAT_CARR_LOST 0x01000000 #define SIS_TXSTAT_UNDERRUN 0x02000000 #define SIS_TXSTAT_TX_ABORT 0x04000000 +#define SIS_DESC_ALIGN 16 +#define SIS_RX_BUF_ALIGN 4 +#define SIS_MAXTXSEGS 16 #define SIS_RX_LIST_CNT 64 #define SIS_TX_LIST_CNT 128 #define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc) #define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc) +#define SIS_ADDR_LO(x) ((uint64_t) (x) & 0xffffffff) +#define SIS_ADDR_HI(x) ((uint64_t) (x) >> 32) + +#define SIS_RX_RING_ADDR(sc, i) \ + ((sc)->sis_rx_paddr + sizeof(struct sis_desc) * (i)) +#define SIS_TX_RING_ADDR(sc, i) \ + ((sc)->sis_tx_paddr + sizeof(struct sis_desc) * (i)) + +#define SIS_INC(x, y) (x) = (x + 1) % (y) + /* * SiS PCI vendor ID. */ #define SIS_VENDORID 0x1039 /* * SiS PCI device IDs */ #define SIS_DEVICEID_900 0x0900 #define SIS_DEVICEID_7016 0x7016 /* * SiS 900 PCI revision codes. */ #define SIS_REV_900B 0x0003 #define SIS_REV_630A 0x0080 #define SIS_REV_630E 0x0081 #define SIS_REV_630S 0x0082 #define SIS_REV_630EA1 0x0083 #define SIS_REV_630ET 0x0084 #define SIS_REV_635 0x0090 #define SIS_REV_96x 0x0091 /* * NatSemi vendor ID */ #define NS_VENDORID 0x100B /* * DP83815 device ID */ #define NS_DEVICEID_DP83815 0x0020 struct sis_type { u_int16_t sis_vid; u_int16_t sis_did; char *sis_name; }; struct sis_mii_frame { u_int8_t mii_stdelim; u_int8_t mii_opcode; u_int8_t mii_phyaddr; u_int8_t mii_regaddr; u_int8_t mii_turnaround; u_int16_t mii_data; }; /* * MII constants */ #define SIS_MII_STARTDELIM 0x01 #define SIS_MII_READOP 0x02 #define SIS_MII_WRITEOP 0x01 #define SIS_MII_TURNAROUND 0x02 #define SIS_TYPE_900 1 #define SIS_TYPE_7016 2 #define SIS_TYPE_83815 3 #define SIS_TYPE_83816 4 +struct sis_txdesc { + struct mbuf *tx_m; + bus_dmamap_t tx_dmamap; +}; + +struct sis_rxdesc { + struct mbuf *rx_m; + bus_dmamap_t rx_dmamap; + struct sis_desc *rx_desc; +}; + struct sis_softc { struct ifnet *sis_ifp; /* interface info */ struct resource *sis_res[2]; void *sis_intrhand; device_t sis_dev; device_t sis_miibus; u_int8_t sis_type; u_int8_t sis_rev; u_int8_t sis_link; u_int sis_srr; struct sis_desc *sis_rx_list; struct sis_desc *sis_tx_list; + bus_dma_tag_t sis_rx_list_tag; + bus_dmamap_t sis_rx_list_map; + bus_dma_tag_t sis_tx_list_tag; + bus_dmamap_t sis_tx_list_map; + bus_dma_tag_t sis_parent_tag; bus_dma_tag_t sis_rx_tag; - bus_dmamap_t sis_rx_dmamap; + bus_dmamap_t sis_rx_sparemap; bus_dma_tag_t sis_tx_tag; - bus_dmamap_t sis_tx_dmamap; - bus_dma_tag_t sis_parent_tag; - bus_dma_tag_t sis_tag; - struct sis_desc *sis_rx_pdsc; + struct sis_rxdesc sis_rxdesc[SIS_RX_LIST_CNT]; + struct sis_txdesc sis_txdesc[SIS_TX_LIST_CNT]; int sis_tx_prod; int sis_tx_cons; int sis_tx_cnt; - u_int32_t sis_rx_paddr; - u_int32_t sis_tx_paddr; + int sis_rx_cons;; + bus_addr_t sis_rx_paddr; + bus_addr_t sis_tx_paddr; struct callout sis_stat_ch; int sis_watchdog_timer; int sis_stopped; #ifdef DEVICE_POLLING int rxcycles; #endif int in_tick; struct mtx sis_mtx; }; #define SIS_TIMEOUT 1000 #define ETHER_ALIGN 2 #define SIS_RXLEN 1536 #define SIS_MIN_FRAMELEN 60 /* * PCI low memory base and low I/O base register, and * other PCI registers. */ #define SIS_PCI_VENDOR_ID 0x00 #define SIS_PCI_DEVICE_ID 0x02 #define SIS_PCI_COMMAND 0x04 #define SIS_PCI_STATUS 0x06 #define SIS_PCI_REVID 0x08 #define SIS_PCI_CLASSCODE 0x09 #define SIS_PCI_CACHELEN 0x0C #define SIS_PCI_LATENCY_TIMER 0x0D #define SIS_PCI_HEADER_TYPE 0x0E #define SIS_PCI_LOIO 0x10 #define SIS_PCI_LOMEM 0x14 #define SIS_PCI_BIOSROM 0x30 #define SIS_PCI_INTLINE 0x3C #define SIS_PCI_INTPIN 0x3D #define SIS_PCI_MINGNT 0x3E #define SIS_PCI_MINLAT 0x0F #define SIS_PCI_RESETOPT 0x48 #define SIS_PCI_EEPROM_DATA 0x4C /* power management registers */ #define SIS_PCI_CAPID 0x50 /* 8 bits */ #define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ #define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ #define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ #define SIS_PSTATE_MASK 0x0003 #define SIS_PSTATE_D0 0x0000 #define SIS_PSTATE_D1 0x0001 #define SIS_PSTATE_D2 0x0002 #define SIS_PSTATE_D3 0x0003 #define SIS_PME_EN 0x0010 #define SIS_PME_STATUS 0x8000