Index: user/jmallett/octeon/sys/mips/cavium/asm_octeon.S =================================================================== --- user/jmallett/octeon/sys/mips/cavium/asm_octeon.S (revision 206643) +++ user/jmallett/octeon/sys/mips/cavium/asm_octeon.S (revision 206644) @@ -1,182 +1,39 @@ -/***********************license start*************** - * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights - * reserved. +/*- + * Copyright (c) 2004-2010 Juli Mallett + * All rights reserved. * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. - * - * * Neither the name of Cavium Networks nor the names of - * its contributors may be used to endorse or promote products - * derived from this software without specific prior written - * permission. - * - * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" - * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS - * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH - * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY - * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT - * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES - * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR - * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET - * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT - * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. - * - * - * For any questions regarding licensing please contact marketing@caviumnetworks.com - * - ***********************license end**************************************/ - -/* $FreeBSD$ */ - + * $FreeBSD$ + */ #include -#include -#include -#include -#include -#include "assym.s" - - - -#define CPU_DISABLE_INTERRUPTS(reg, reg2, reg3) \ - mfc0 reg, MIPS_COP_0_STATUS; \ - nop; \ - move reg3, reg; \ - li reg2, ~MIPS_SR_INT_IE; \ - and reg, reg2, reg; \ - mtc0 reg, MIPS_COP_0_STATUS; \ - COP0_SYNC - - - -#define CPU_ENABLE_INTERRUPTS(reg, reg3) \ - mfc0 reg, MIPS_COP_0_STATUS; \ - nop; \ - or reg, reg, reg3; \ - mtc0 reg, MIPS_COP_0_STATUS; \ - COP0_SYNC - - -#define PUSHR(reg) \ - addiu sp,sp,-16 ; \ - sd reg, 8(sp) ; \ - nop ; - -#define POPR(reg) \ - ld reg, 8(sp) ; \ - addiu sp,sp,16 ; \ - nop ; - - - - +#ifdef SMP /* - * octeon_ciu_get_interrupt_reg_addr - * - * Given Int-X, En-X combination, return the CIU Interrupt Enable Register addr - * a0 = ciu Int-X: 0/1 - * a1 = ciu EN-0: 0/1 + * This function must be implemented in assembly because it is called early + * in AP boot without a valid stack. */ -LEAF(octeon_ciu_get_interrupt_reg_addr) - .set noreorder - .set mips3 - - beqz a0, ciu_get_interrupt_reg_addr_Int_0 - nop - -ciu_get_interrupt_reg_addr_Int_1: - beqz a1, ciu_get_interrupt_reg_addr_Int_1_En_0 - nop - -ciu_get_interrupt_reg_addr_Int_1_En1: - li a0, OCTEON_CIU_ADDR_HI - dsll32 a0, a0, 0 - nop - ori a0, OCTEON_CIU_EN1_INT1_LO - j ciu_get_interrupt_reg_addr_ret - nop - -ciu_get_interrupt_reg_addr_Int_1_En_0: - li a0, OCTEON_CIU_ADDR_HI - dsll32 a0, a0, 0 - nop - ori a0, OCTEON_CIU_EN0_INT1_LO - j ciu_get_interrupt_reg_addr_ret - nop - -ciu_get_interrupt_reg_addr_Int_0: - beqz a1, ciu_get_interrupt_reg_addr_Int_0_En_0 - nop - -ciu_get_interrupt_reg_addr_Int_0_En_1: - li a0, OCTEON_CIU_ADDR_HI - dsll32 a0, a0, 0 - nop - ori a0, OCTEON_CIU_EN1_INT0_LO - j ciu_get_interrupt_reg_addr_ret - nop - -ciu_get_interrupt_reg_addr_Int_0_En_0: - li a0, OCTEON_CIU_ADDR_HI - dsll32 a0, a0, 0 - nop - ori a0, OCTEON_CIU_EN0_INT0_LO - - -ciu_get_interrupt_reg_addr_ret: - j ra - nop - - .set mips0 - .set reorder -END(octeon_ciu_get_interrupt_reg_addr) - - - -/* - * octeon_ciu_mask_all_interrupts - * - * a0 = ciu Interrupt-X: 0/1 - * a1 = ciu Enable-X: 0/1 - */ -LEAF(octeon_ciu_mask_all_interrupts) - .set noreorder - .set mips3 - - PUSHR(ra) - PUSHR(s0) - - move t0, a0 - move t1, a1 - li a0, MIPS_SR_INT_IE - CPU_DISABLE_INTERRUPTS(a2, a1, s0) - move a0, t0 - move t1, a1 - jal octeon_ciu_get_interrupt_reg_addr - nop - ld a2, 0(a0) # Dummy read - nop - move a2, zero # Clear all - sd a2, 0(a0) # Write new Enable bits - nop - CPU_ENABLE_INTERRUPTS(a2, s0) - - POPR(s0) - POPR(ra) - j ra # Return - nop # (bd slot) - - .set mips0 - .set reorder -END(octeon_ciu_mask_all_interrupts) - +LEAF(platform_processor_id) + li v0, 0 + jr ra +END(platform_processor_id) +#endif Index: user/jmallett/octeon/sys/mips/cavium/files.octeon1 =================================================================== --- user/jmallett/octeon/sys/mips/cavium/files.octeon1 (revision 206643) +++ user/jmallett/octeon/sys/mips/cavium/files.octeon1 (revision 206644) @@ -1,15 +1,17 @@ # $FreeBSD$ # Octeon Support Files # +mips/cavium/asm_octeon.S optional smp mips/cavium/dev/rgmii/octeon_fpa.c optional rgmii mips/cavium/dev/rgmii/octeon_ipd.c optional rgmii mips/cavium/dev/rgmii/octeon_pko.c optional rgmii mips/cavium/dev/rgmii/octeon_rgmx.c optional rgmii mips/cavium/obio.c optional uart mips/cavium/octeon_ebt3000_cf.c optional cf mips/cavium/octeon_machdep.c standard +mips/cavium/octeon_mp.c optional smp mips/cavium/uart_bus_octeonusart.c optional uart mips/cavium/uart_cpu_octeonusart.c optional uart mips/cavium/uart_dev_oct16550.c optional uart mips/mips/intr_machdep.c standard mips/mips/tick.c standard Index: user/jmallett/octeon/sys/mips/cavium/octeon_mp.c =================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_mp.c (nonexistent) +++ user/jmallett/octeon/sys/mips/cavium/octeon_mp.c (revision 206644) @@ -0,0 +1,75 @@ +/*- + * Copyright (c) 2004-2010 Juli Mallett + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include + +#include +#include + +void +platform_ipi_send(int cpuid) +{ + panic("%s: not yet implemented.", __func__); +} + +void +platform_ipi_clear(void) +{ + panic("%s: not yet implemented.", __func__); +} + +int +platform_ipi_intrnum(void) +{ + panic("%s: not yet implemented.", __func__); +} + +void +platform_init_ap(int cpuid) +{ + panic("%s: not yet implemented.", __func__); + + KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid)); +} + +int +platform_num_processors(void) +{ + panic("%s: not yet implemented.", __func__); +} + +int +platform_start_ap(int cpuid) +{ + panic("%s: not yet implemented.", __func__); +} Index: user/jmallett/octeon/sys/mips/mips/mpboot.S =================================================================== --- user/jmallett/octeon/sys/mips/mips/mpboot.S (revision 206643) +++ user/jmallett/octeon/sys/mips/mips/mpboot.S (revision 206644) @@ -1,72 +1,73 @@ /*- * Copyright (c) 2010 Neelkanth Natu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include #include #include #include "assym.s" .text .set noat .set noreorder GLOBAL(mpentry) + /* XXX On n64 this will be a problem. */ mtc0 zero, COP_0_STATUS_REG /* disable interrupts */ mtc0 zero, COP_0_CAUSE_REG /* clear soft interrupts */ li t0, CFG_K0_CACHED /* make sure kseg0 is cached */ mtc0 t0, MIPS_COP_0_CONFIG COP0_SYNC jal platform_processor_id /* get the processor number */ nop move s0, v0 /* * Initialize stack and call machine startup */ PTR_LA sp, _C_LABEL(pcpu_space) addiu sp, (PAGE_SIZE * 2) - CALLFRAME_SIZ sll t0, s0, PAGE_SHIFT + 1 addu sp, sp, t0 /* Zero out old ra and old fp for debugger */ sw zero, CALLFRAME_SIZ - 4(sp) sw zero, CALLFRAME_SIZ - 8(sp) PTR_LA gp, _C_LABEL(_gp) jal platform_init_ap move a0, s0 jal smp_init_secondary move a0, s0 PANIC("AP startup failed!")