Index: projects/mips/sys/mips/include/cpufunc.h =================================================================== --- projects/mips/sys/mips/include/cpufunc.h (revision 191576) +++ projects/mips/sys/mips/include/cpufunc.h (revision 191577) @@ -1,352 +1,366 @@ /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */ /* * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Per Fogelstrom. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta * $FreeBSD$ */ #ifndef _MACHINE_CPUFUNC_H_ #define _MACHINE_CPUFUNC_H_ #include #include /* * These functions are required by user-land atomi ops */ static __inline void mips_barrier(void) { __asm __volatile (".set noreorder\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" "nop\n\t" ".set reorder\n\t" : : : "memory"); } static __inline void mips_wbflush(void) { __asm __volatile ("sync" : : : "memory"); mips_barrier(); #if 0 __asm __volatile("mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */ : : "r" (flag)); #endif } static __inline void mips_read_membar(void) { /* Nil */ } static __inline void mips_write_membar(void) { mips_wbflush(); } #ifdef _KERNEL static __inline void mips_tlbp(void) { __asm __volatile ("tlbp"); mips_barrier(); #if 0 register_t ret; register_t tmp; __asm __volatile("mfc0 %0, $12\n" /* MIPS_COP_0_STATUS */ "and %1, %0, $~1\n" /* MIPS_SR_INT_IE */ "mtc0 %1, $12\n" /* MIPS_COP_0_STATUS */ : "=r" (ret), "=r" (tmp)); return (ret); #endif } static __inline void mips_tlbr(void) { __asm __volatile ("tlbr"); mips_barrier(); } static __inline void mips_tlbwi(void) { __asm __volatile ("tlbwi"); mips_barrier(); #if 0 __asm __volatile("mfc %0, $12\n" /* MIPS_COP_0_STATUS */ "or %0, %0, $1\n" /* MIPS_SR_INT_IE */ "mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */ : "=r" (tmp)); #endif } static __inline void mips_tlbwr(void) { __asm __volatile ("tlbwr"); mips_barrier(); } #if 0 /* XXX mips64 */ #define MIPS_RDRW64_COP0(n,r) \ static __inline uint64_t \ mips_rd_ ## n (void) \ { \ int v0; \ __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \ : [v0] "=&r"(v0)); \ mips_barrier(); \ return (v0); \ } \ static __inline void \ mips_wr_ ## n (uint64_t a0) \ { \ __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \ __XSTRING(COP0_SYNC)";" \ "nop;" \ "nop;" \ : \ : [a0] "r"(a0)); \ mips_barrier(); \ } struct __hack MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0); MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1); MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI); MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT); #undef MIPS_RDRW64_COP0 #endif #define MIPS_RDRW32_COP0(n,r) \ static __inline uint32_t \ mips_rd_ ## n (void) \ { \ int v0; \ __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \ : [v0] "=&r"(v0)); \ mips_barrier(); \ return (v0); \ } \ static __inline void \ mips_wr_ ## n (uint32_t a0) \ { \ __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \ __XSTRING(COP0_SYNC)";" \ "nop;" \ "nop;" \ : \ : [a0] "r"(a0)); \ mips_barrier(); \ } struct __hack +#define MIPS_RDRW32_COP0_SEL(n,r,s) \ +static __inline uint32_t \ +mips_rd_ ## n ## s(void) \ +{ \ + int v0; \ + __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ + : [v0] "=&r"(v0)); \ + mips_barrier(); \ + return (v0); \ +} \ +static __inline void \ +mips_wr_ ## n ## s(uint32_t a0) \ +{ \ + __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ + __XSTRING(COP0_SYNC)";" \ + "nop;" \ + "nop;" \ + : \ + : [a0] "r"(a0)); \ + mips_barrier(); \ +} struct __hack + #ifdef TARGET_OCTEON static __inline void mips_sync_icache (void) { __asm __volatile ( ".set mips64\n" ".word 0x041f0000\n" "nop\n" ".set mips0\n" : : ); } #endif MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); +MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 1); +MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 2); +MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 3); MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE); MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS); /* XXX: Some of these registers are specific to MIPS32. */ MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW); MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI); MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); +MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1); +MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2); +MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 3); MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); +MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1); +MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2); +MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3); #undef MIPS_RDRW32_COP0 - -#define MIPS_RD_CONFIG_SEL(sel) \ -static __inline uint32_t \ -mips_rd_config_sel##sel(void) \ -{ \ - int v0; \ - __asm __volatile("mfc0 %[v0], $16, " #sel " ;" \ - : [v0] "=&r" (v0)); \ - mips_barrier(); \ - return (v0); \ -} - - -MIPS_RD_CONFIG_SEL(1); -MIPS_RD_CONFIG_SEL(2); -MIPS_RD_CONFIG_SEL(3); -#undef MIPS_RD_CONFIG_SEL static __inline register_t intr_disable(void) { register_t s; s = mips_rd_status(); mips_wr_status(s & ~MIPS_SR_INT_IE); return (s); } static __inline register_t intr_enable(void) { register_t s; s = mips_rd_status(); mips_wr_status(s | MIPS_SR_INT_IE); return (s); } #define intr_restore(s) mips_wr_status((s)) static __inline void breakpoint(void) { __asm __volatile ("break"); } #endif /* _KERNEL */ #define readb(va) (*(volatile uint8_t *) (va)) #define readw(va) (*(volatile uint16_t *) (va)) #define readl(va) (*(volatile uint32_t *) (va)) #define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) #define writew(va, d) (*(volatile uint16_t *) (va) = (d)) #define writel(va, d) (*(volatile uint32_t *) (va) = (d)) /* * I/O macros. */ #define outb(a,v) (*(volatile unsigned char*)(a) = (v)) #define out8(a,v) (*(volatile unsigned char*)(a) = (v)) #define outw(a,v) (*(volatile unsigned short*)(a) = (v)) #define out16(a,v) outw(a,v) #define outl(a,v) (*(volatile unsigned int*)(a) = (v)) #define out32(a,v) outl(a,v) #define inb(a) (*(volatile unsigned char*)(a)) #define in8(a) (*(volatile unsigned char*)(a)) #define inw(a) (*(volatile unsigned short*)(a)) #define in16(a) inw(a) #define inl(a) (*(volatile unsigned int*)(a)) #define in32(a) inl(a) #define out8rb(a,v) (*(volatile unsigned char*)(a) = (v)) #define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v)) #define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v)) #define in8rb(a) (*(volatile unsigned char*)(a)) #define in16rb(a) (__in16rb((volatile uint16_t *)(a))) #define in32rb(a) (__in32rb((volatile uint32_t *)(a))) #define _swap_(x) (((x) >> 24) | ((x) << 24) | \ (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8)) static __inline void __out32rb(volatile uint32_t *, uint32_t); static __inline void __out16rb(volatile uint16_t *, uint16_t); static __inline uint32_t __in32rb(volatile uint32_t *); static __inline uint16_t __in16rb(volatile uint16_t *); static __inline void __out32rb(volatile uint32_t *a, uint32_t v) { uint32_t _v_ = v; _v_ = _swap_(_v_); out32(a, _v_); } static __inline void __out16rb(volatile uint16_t *a, uint16_t v) { uint16_t _v_; _v_ = ((v >> 8) & 0xff) | (v << 8); out16(a, _v_); } static __inline uint32_t __in32rb(volatile uint32_t *a) { uint32_t _v_; _v_ = in32(a); _v_ = _swap_(_v_); return _v_; } static __inline uint16_t __in16rb(volatile uint16_t *a) { uint16_t _v_; _v_ = in16(a); _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8); return _v_; } void insb(uint8_t *, uint8_t *,int); void insw(uint16_t *, uint16_t *,int); void insl(uint32_t *, uint32_t *,int); void outsb(uint8_t *, const uint8_t *,int); void outsw(uint16_t *, const uint16_t *,int); void outsl(uint32_t *, const uint32_t *,int); u_int loadandclear(volatile u_int *addr); #endif /* !_MACHINE_CPUFUNC_H_ */ Index: projects/mips/sys/mips/mips/cpu.c =================================================================== --- projects/mips/sys/mips/mips/cpu.c (revision 191576) +++ projects/mips/sys/mips/mips/cpu.c (revision 191577) @@ -1,367 +1,367 @@ /*- * Copyright (c) 2004 Juli Mallett. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static struct mips_cpuinfo cpuinfo; union cpuprid cpu_id; union cpuprid fpu_id; /* * Attempt to identify the MIPS CPU as much as possible. * * XXX: Assumes the CPU is MIPS32 compliant. * XXX: For now, skip config register selections 2 and 3 * as we don't currently use L2/L3 cache or additional * MIPS32 processor features. */ static void mips_get_identity(struct mips_cpuinfo *cpuinfo) { u_int32_t prid; u_int32_t cfg0; u_int32_t cfg1; u_int32_t tmp; memset(cpuinfo, 0, sizeof(struct mips_cpuinfo)); /* Read and store the PrID ID for CPU identification. */ prid = mips_rd_prid(); cpuinfo->cpu_vendor = MIPS_PRID_CID(prid); cpuinfo->cpu_rev = MIPS_PRID_REV(prid); cpuinfo->cpu_impl = MIPS_PRID_IMPL(prid); /* Read config register selection 0 to learn TLB type. */ cfg0 = mips_rd_config(); cpuinfo->tlb_type = ((cfg0 & MIPS_CONFIG0_MT_MASK) >> MIPS_CONFIG0_MT_SHIFT); cpuinfo->icache_virtual = cfg0 & MIPS_CONFIG0_VI; /* If config register selection 1 does not exist, exit. */ if (!(cfg0 & MIPS3_CONFIG_CM)) return; /* Learn TLB size and L1 cache geometry. */ - cfg1 = mips_rd_config_sel1(); + cfg1 = mips_rd_config1(); cpuinfo->tlb_nentries = ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; /* L1 instruction cache. */ tmp = 1 << (((cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT) + 1); if (tmp != 0) { cpuinfo->l1.ic_linesize = tmp; cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; cpuinfo->l1.ic_nsets = 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); cpuinfo->l1.ic_size = cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways; } /* L1 data cache. */ tmp = 1 << (((cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT) + 1); if (tmp != 0) { cpuinfo->l1.dc_linesize = tmp; cpuinfo->l1.dc_nways = (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; cpuinfo->l1.dc_nsets = 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); #ifdef TARGET_OCTEON /* * Octeon does 128 byte line-size. But Config-Sel1 doesn't show * 128 line-size, 1 Set, 64 ways. */ cpuinfo->l1.dc_linesize = 128; cpuinfo->l1.dc_nsets = 1; cpuinfo->l1.dc_nways = 64; #endif cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize * cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_nways; } } void mips_cpu_init(void) { mips_get_identity(&cpuinfo); num_tlbentries = cpuinfo.tlb_nentries; Mips_SetWIRED(0); Mips_TLBFlush(num_tlbentries); Mips_SetWIRED(VMWIRED_ENTRIES); mips_config_cache(&cpuinfo); mips_vector_init(); mips_icache_sync_all(); mips_dcache_wbinv_all(); /* Print some info about CPU */ cpu_identify(); } void cpu_identify(void) { uint32_t cfg0, cfg1, cfg2, cfg3; printf("cpu%d: ", 0); /* XXX per-cpu */ switch (cpuinfo.cpu_vendor) { case MIPS_PRID_CID_MTI: printf("MIPS Technologies"); break; case MIPS_PRID_CID_BROADCOM: case MIPS_PRID_CID_SIBYTE: printf("Broadcom"); break; case MIPS_PRID_CID_ALCHEMY: printf("AMD"); break; case MIPS_PRID_CID_SANDCRAFT: printf("Sandcraft"); break; case MIPS_PRID_CID_PHILIPS: printf("Philips"); break; case MIPS_PRID_CID_TOSHIBA: printf("Toshiba"); break; case MIPS_PRID_CID_LSI: printf("LSI"); break; case MIPS_PRID_CID_LEXRA: printf("Lexra"); break; case MIPS_PRID_CID_PREHISTORIC: default: printf("Unknown"); break; } printf(" processor v%d.%d\n", cpuinfo.cpu_rev, cpuinfo.cpu_impl); printf(" MMU: "); if (cpuinfo.tlb_type == MIPS_MMU_NONE) { printf("none present\n"); } else { if (cpuinfo.tlb_type == MIPS_MMU_TLB) { printf("Standard TLB"); } else if (cpuinfo.tlb_type == MIPS_MMU_BAT) { printf("Standard BAT"); } else if (cpuinfo.tlb_type == MIPS_MMU_FIXED) { printf("Fixed mapping"); } printf(", %d entries\n", cpuinfo.tlb_nentries); } printf(" L1 i-cache: "); if (cpuinfo.l1.ic_linesize == 0) { printf("disabled"); } else { if (cpuinfo.l1.ic_nways == 1) { printf("direct-mapped with"); } else { printf ("%d ways of", cpuinfo.l1.ic_nways); } printf(" %d sets, %d bytes per line\n", cpuinfo.l1.ic_nsets, cpuinfo.l1.ic_linesize); } printf(" L1 d-cache: "); if (cpuinfo.l1.dc_linesize == 0) { printf("disabled"); } else { if (cpuinfo.l1.dc_nways == 1) { printf("direct-mapped with"); } else { printf ("%d ways of", cpuinfo.l1.dc_nways); } printf(" %d sets, %d bytes per line\n", cpuinfo.l1.dc_nsets, cpuinfo.l1.dc_linesize); } cfg0 = mips_rd_config(); /* If config register selection 1 does not exist, exit. */ if (!(cfg0 & MIPS3_CONFIG_CM)) return; - cfg1 = mips_rd_config_sel1(); + cfg1 = mips_rd_config1(); printf(" Config1=0x%b\n", cfg1, "\20\7COP2\6MDMX\5PerfCount\4WatchRegs\3MIPS16\2EJTAG\1FPU"); /* If config register selection 2 does not exist, exit. */ if (!(cfg1 & MIPS3_CONFIG_CM)) return; - cfg2 = mips_rd_config_sel2(); + cfg2 = mips_rd_config2(); /* * Config2 contains no useful information other then Config3 * existence flag */ /* If config register selection 3 does not exist, exit. */ if (!(cfg2 & MIPS3_CONFIG_CM)) return; - cfg3 = mips_rd_config_sel3(); + cfg3 = mips_rd_config3(); /* Print Config3 if it contains any useful info */ if (cfg3 & ~(0x80000000)) printf(" Config3=0x%b\n", cfg3, "\20\2SmartMIPS\1TraceLogic"); } static struct rman cpu_hardirq_rman; static devclass_t cpu_devclass; /* * Device methods */ static int cpu_probe(device_t); static int cpu_attach(device_t); static struct resource *cpu_alloc_resource(device_t, device_t, int, int *, u_long, u_long, u_long, u_int); static int cpu_setup_intr(device_t, device_t, struct resource *, int, driver_filter_t *f, driver_intr_t *, void *, void **); static device_method_t cpu_methods[] = { /* Device interface */ DEVMETHOD(device_probe, cpu_probe), DEVMETHOD(device_attach, cpu_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), /* Bus interface */ DEVMETHOD(bus_alloc_resource, cpu_alloc_resource), DEVMETHOD(bus_setup_intr, cpu_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), { 0, 0 } }; static driver_t cpu_driver = { "cpu", cpu_methods, 1 }; static int cpu_probe(device_t dev) { return (0); } static int cpu_attach(device_t dev) { int error; #ifdef notyet device_t clock; #endif cpu_hardirq_rman.rm_start = 0; cpu_hardirq_rman.rm_end = 5; cpu_hardirq_rman.rm_type = RMAN_ARRAY; cpu_hardirq_rman.rm_descr = "CPU Hard Interrupts"; error = rman_init(&cpu_hardirq_rman); if (error != 0) { device_printf(dev, "failed to initialize irq resources\n"); return (error); } /* XXX rman_manage_all. */ error = rman_manage_region(&cpu_hardirq_rman, cpu_hardirq_rman.rm_start, cpu_hardirq_rman.rm_end); if (error != 0) { device_printf(dev, "failed to manage irq resources\n"); return (error); } if (device_get_unit(dev) != 0) panic("can't attach more cpus"); device_set_desc(dev, "MIPS32 processor"); #ifdef notyet clock = device_add_child(dev, "clock", device_get_unit(dev)); if (clock == NULL) device_printf(dev, "clock failed to attach"); #endif return (bus_generic_attach(dev)); } static struct resource * cpu_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct resource *res; if (type != SYS_RES_IRQ) return (NULL); res = rman_reserve_resource(&cpu_hardirq_rman, start, end, count, 0, child); return (res); } static int cpu_setup_intr(device_t dev, device_t child, struct resource *res, int flags, driver_filter_t *filt, driver_intr_t *handler, void *arg, void **cookiep) { int error; int intr; error = rman_activate_resource(res); if (error != 0) { device_printf(child, "could not activate irq\n"); return (error); } intr = rman_get_start(res); cpu_establish_hardintr(device_get_nameunit(child), filt, handler, arg, intr, flags, cookiep); device_printf(child, "established CPU interrupt %d\n", intr); return (0); } DRIVER_MODULE(cpu, root, cpu_driver, cpu_devclass, 0, 0);