Index: head/sys/powerpc/include/intr_machdep.h =================================================================== --- head/sys/powerpc/include/intr_machdep.h (revision 176207) +++ head/sys/powerpc/include/intr_machdep.h (revision 176208) @@ -1,45 +1,47 @@ /*- * Copyright (C) 2002 Benno Rice. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_INTR_MACHDEP_H_ #define _MACHINE_INTR_MACHDEP_H_ #define INTR_VECTORS 256 extern device_t pic; struct trapframe; -void powerpc_register_pic(device_t); +driver_filter_t powerpc_ipi_handler; + +void powerpc_register_pic(device_t, u_int); void powerpc_dispatch_intr(u_int, struct trapframe *); int powerpc_enable_intr(void); int powerpc_setup_intr(const char *, u_int, driver_filter_t, driver_intr_t, void *, enum intr_type, void **); int powerpc_teardown_intr(void *); #endif /* _MACHINE_INTR_MACHDEP_H_ */ Index: head/sys/powerpc/include/openpicreg.h =================================================================== --- head/sys/powerpc/include/openpicreg.h (revision 176207) +++ head/sys/powerpc/include/openpicreg.h (revision 176208) @@ -1,109 +1,140 @@ /*- * Copyright (c) 2000 Tsubai Masanari. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp * $FreeBSD$ */ /* * Size of OpenPIC register space */ #define OPENPIC_SIZE 0x40000 /* - * GLOBAL/TIMER register (IDU base + 0x1000) + * Per Processor Registers [private access] (0x00000 - 0x00fff) */ +/* IPI dispatch command reg */ +#define OPENPIC_IPI_DISPATCH(ipi) (0x40 + (ipi) * 0x10) + +/* current task priority reg */ +#define OPENPIC_TPR 0x80 +#define OPENPIC_TPR_MASK 0x0000000f + +#define OPENPIC_WHOAMI 0x90 + +/* interrupt acknowledge reg */ +#define OPENPIC_IACK 0xa0 + +/* end of interrupt reg */ +#define OPENPIC_EOI 0xb0 + +/* + * Global registers (0x01000-0x0ffff) + */ + /* feature reporting reg 0 */ #define OPENPIC_FEATURE 0x1000 -#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff -#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00 -#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8 -#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000 -#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16 +#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff +#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00 +#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8 +#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000 +#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16 /* global config reg 0 */ #define OPENPIC_CONFIG 0x1020 #define OPENPIC_CONFIG_RESET 0x80000000 #define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 /* interrupt configuration mode (direct or serial) */ #define OPENPIC_ICR 0x1030 -#define OPENPIC_ICR_SERIAL_MODE (1 << 27) -#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) -#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 +#define OPENPIC_ICR_SERIAL_MODE (1 << 27) +#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) +#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 /* vendor ID */ #define OPENPIC_VENDOR_ID 0x1080 /* processor initialization reg */ #define OPENPIC_PROC_INIT 0x1090 /* IPI vector/priority reg */ #define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) /* spurious intr. vector */ #define OPENPIC_SPURIOUS_VECTOR 0x10e0 +/* Timer registers */ +#define OPENPIC_TIMERS 4 +#define OPENPIC_TFREQ 0x10f0 +#define OPENPIC_TCNT(t) (0x1100 + (t) * 0x40) +#define OPENPIC_TBASE(t) (0x1110 + (t) * 0x40) +#define OPENPIC_TVEC(t) (0x1120 + (t) * 0x40) +#define OPENPIC_TDST(t) (0x1130 + (t) * 0x40) /* - * INTERRUPT SOURCE register (IDU base + 0x10000) + * Interrupt Source Configuration Registers (0x10000 - 0x1ffff) */ /* interrupt vector/priority reg */ #ifndef OPENPIC_SRC_VECTOR #define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) #endif #define OPENPIC_SENSE_LEVEL 0x00400000 #define OPENPIC_SENSE_EDGE 0x00000000 #define OPENPIC_POLARITY_POSITIVE 0x00800000 #define OPENPIC_POLARITY_NEGATIVE 0x00000000 #define OPENPIC_IMASK 0x80000000 #define OPENPIC_ACTIVITY 0x40000000 #define OPENPIC_PRIORITY_MASK 0x000f0000 #define OPENPIC_PRIORITY_SHIFT 16 #define OPENPIC_VECTOR_MASK 0x000000ff /* interrupt destination cpu */ #ifndef OPENPIC_IDEST #define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) #endif /* - * PROCESSOR register (IDU base + 0x20000) + * Per Processor Registers [global access] (0x20000 - 0x3ffff) */ -/* IPI command reg */ -#define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi)) +#define OPENPIC_PCPU_BASE(cpu) (0x20000 + (cpu) * 0x1000) -/* current task priority reg */ -#define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) -#define OPENPIC_CPU_PRIORITY_MASK 0x0000000f +#define OPENPIC_PCPU_IPI_DISPATCH(cpu, ipi) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IPI_DISPATCH(ipi)) -/* interrupt acknowledge reg */ -#define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) +#define OPENPIC_PCPU_TPR(cpu) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_TPR) -/* end of interrupt reg */ -#define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000) +#define OPENPIC_PCPU_WHOAMI(cpu) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_WHOAMI) + +#define OPENPIC_PCPU_IACK(cpu) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IACK) + +#define OPENPIC_PCPU_EOI(cpu) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_EOI) + Index: head/sys/powerpc/include/openpicvar.h =================================================================== --- head/sys/powerpc/include/openpicvar.h (revision 176207) +++ head/sys/powerpc/include/openpicvar.h (revision 176208) @@ -1,63 +1,64 @@ /*- * Copyright (C) 2002 Benno Rice. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _POWERPC_OPENPICVAR_H_ #define _POWERPC_OPENPICVAR_H_ #define OPENPIC_DEVSTR "OpenPIC Interrupt Controller" #define OPENPIC_IRQMAX 256 /* h/w allows more */ struct openpic_softc { device_t sc_dev; struct resource *sc_memr; bus_space_tag_t sc_bt; bus_space_handle_t sc_bh; char *sc_version; int sc_rid; u_int sc_ncpu; u_int sc_nirq; int sc_psim; }; extern devclass_t openpic_devclass; /* * Bus-independent attach i/f */ int openpic_attach(device_t); /* * PIC interface. */ void openpic_dispatch(device_t, struct trapframe *); void openpic_enable(device_t, u_int, u_int); void openpic_eoi(device_t, u_int); +void openpic_ipi(device_t, u_int); void openpic_mask(device_t, u_int); void openpic_unmask(device_t, u_int); #endif /* _POWERPC_OPENPICVAR_H_ */ Index: head/sys/powerpc/powermac/hrowpic.c =================================================================== --- head/sys/powerpc/powermac/hrowpic.c (revision 176207) +++ head/sys/powerpc/powermac/hrowpic.c (revision 176208) @@ -1,271 +1,279 @@ /*- * Copyright 2003 by Peter Grehan. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * A driver for the PIC found in the Heathrow/Paddington MacIO chips. * This was superseded by an OpenPIC in the Keylargo and beyond * MacIO versions. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pic_if.h" /* * MacIO interface */ static int hrowpic_probe(device_t); static int hrowpic_attach(device_t); static void hrowpic_dispatch(device_t, struct trapframe *); static void hrowpic_enable(device_t, u_int, u_int); static void hrowpic_eoi(device_t, u_int); +static void hrowpic_ipi(device_t, u_int); static void hrowpic_mask(device_t, u_int); static void hrowpic_unmask(device_t, u_int); static device_method_t hrowpic_methods[] = { /* Device interface */ DEVMETHOD(device_probe, hrowpic_probe), DEVMETHOD(device_attach, hrowpic_attach), /* PIC interface */ DEVMETHOD(pic_dispatch, hrowpic_dispatch), DEVMETHOD(pic_enable, hrowpic_enable), DEVMETHOD(pic_eoi, hrowpic_eoi), + DEVMETHOD(pic_ipi, hrowpic_ipi), DEVMETHOD(pic_mask, hrowpic_mask), DEVMETHOD(pic_unmask, hrowpic_unmask), { 0, 0 }, }; static driver_t hrowpic_driver = { "hrowpic", hrowpic_methods, sizeof(struct hrowpic_softc) }; static devclass_t hrowpic_devclass; DRIVER_MODULE(hrowpic, macio, hrowpic_driver, hrowpic_devclass, 0, 0); static uint32_t hrowpic_read_reg(struct hrowpic_softc *sc, u_int reg, u_int bank) { if (bank == HPIC_PRIMARY) reg += HPIC_1ST_OFFSET; return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg)); } static void hrowpic_write_reg(struct hrowpic_softc *sc, u_int reg, u_int bank, uint32_t val) { if (bank == HPIC_PRIMARY) reg += HPIC_1ST_OFFSET; bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val); /* XXX Issue a read to force the write to complete. */ bus_space_read_4(sc->sc_bt, sc->sc_bh, reg); } static int hrowpic_probe(device_t dev) { const char *type = ofw_bus_get_type(dev); /* * OpenPIC cells have a type of "open-pic", so this * is sufficient to identify a Heathrow cell */ if (strcmp(type, "interrupt-controller") != 0) return (ENXIO); /* * The description was already printed out in the nexus * probe, so don't do it again here */ device_set_desc(dev, "Heathrow MacIO interrupt controller"); return (0); } static int hrowpic_attach(device_t dev) { struct hrowpic_softc *sc; sc = device_get_softc(dev); sc->sc_dev = dev; sc->sc_rrid = 0; sc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rrid, RF_ACTIVE); if (sc->sc_rres == NULL) { device_printf(dev, "Could not alloc mem resource!\n"); return (ENXIO); } sc->sc_bt = rman_get_bustag(sc->sc_rres); sc->sc_bh = rman_get_bushandle(sc->sc_rres); /* * Disable all interrupt sources and clear outstanding interrupts */ hrowpic_write_reg(sc, HPIC_ENABLE, HPIC_PRIMARY, 0); hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_PRIMARY, 0xffffffff); hrowpic_write_reg(sc, HPIC_ENABLE, HPIC_SECONDARY, 0); hrowpic_write_reg(sc, HPIC_CLEAR, HPIC_SECONDARY, 0xffffffff); - powerpc_register_pic(dev); + powerpc_register_pic(dev, 64); return (0); } /* * Local routines */ static void hrowpic_toggle_irq(struct hrowpic_softc *sc, int irq, int enable) { u_int roffset; u_int rbit; KASSERT((irq > 0) && (irq < HROWPIC_IRQMAX), ("en irq out of range")); /* * Calculate prim/sec register bank for the IRQ, update soft copy, * and enable the IRQ as an interrupt source */ roffset = HPIC_INT_TO_BANK(irq); rbit = HPIC_INT_TO_REGBIT(irq); if (enable) sc->sc_softreg[roffset] |= (1 << rbit); else sc->sc_softreg[roffset] &= ~(1 << rbit); hrowpic_write_reg(sc, HPIC_ENABLE, roffset, sc->sc_softreg[roffset]); } /* * PIC I/F methods. */ static void hrowpic_dispatch(device_t dev, struct trapframe *tf) { struct hrowpic_softc *sc; uint64_t mask; uint32_t reg; u_int irq; sc = device_get_softc(dev); while (1) { mask = hrowpic_read_reg(sc, HPIC_STATUS, HPIC_SECONDARY); reg = hrowpic_read_reg(sc, HPIC_STATUS, HPIC_PRIMARY); mask = (mask << 32) | reg; if (mask == 0) break; irq = 0; while (irq < HROWPIC_IRQMAX) { if (mask & 1) powerpc_dispatch_intr(sc->sc_vector[irq], tf); mask >>= 1; irq++; } } } static void hrowpic_enable(device_t dev, u_int irq, u_int vector) { struct hrowpic_softc *sc; sc = device_get_softc(dev); sc->sc_vector[irq] = vector; hrowpic_toggle_irq(sc, irq, 1); } static void hrowpic_eoi(device_t dev __unused, u_int irq __unused) { struct hrowpic_softc *sc; int bank; sc = device_get_softc(dev); bank = (irq >= 32) ? HPIC_SECONDARY : HPIC_PRIMARY ; hrowpic_write_reg(sc, HPIC_CLEAR, bank, 1U << (irq & 0x1f)); +} + +static void +hrowpic_ipi(device_t dev, u_int irq) +{ + /* No SMP support. */ } static void hrowpic_mask(device_t dev, u_int irq) { struct hrowpic_softc *sc; int bank; sc = device_get_softc(dev); hrowpic_toggle_irq(sc, irq, 0); bank = (irq >= 32) ? HPIC_SECONDARY : HPIC_PRIMARY ; hrowpic_write_reg(sc, HPIC_CLEAR, bank, 1U << (irq & 0x1f)); } static void hrowpic_unmask(device_t dev, u_int irq) { struct hrowpic_softc *sc; sc = device_get_softc(dev); hrowpic_toggle_irq(sc, irq, 1); } Index: head/sys/powerpc/powermac/openpic_macio.c =================================================================== --- head/sys/powerpc/powermac/openpic_macio.c (revision 176207) +++ head/sys/powerpc/powermac/openpic_macio.c (revision 176208) @@ -1,97 +1,98 @@ /*- * Copyright 2003 by Peter Grehan. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pic_if.h" /* * MacIO interface */ static int openpic_macio_probe(device_t); static device_method_t openpic_macio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, openpic_macio_probe), DEVMETHOD(device_attach, openpic_attach), /* PIC interface */ DEVMETHOD(pic_dispatch, openpic_dispatch), DEVMETHOD(pic_enable, openpic_enable), DEVMETHOD(pic_eoi, openpic_eoi), + DEVMETHOD(pic_ipi, openpic_ipi), DEVMETHOD(pic_mask, openpic_mask), DEVMETHOD(pic_unmask, openpic_unmask), { 0, 0 }, }; static driver_t openpic_macio_driver = { "openpic", openpic_macio_methods, sizeof(struct openpic_softc), }; DRIVER_MODULE(openpic, macio, openpic_macio_driver, openpic_devclass, 0, 0); static int openpic_macio_probe(device_t dev) { const char *type = ofw_bus_get_type(dev); if (strcmp(type, "open-pic") != 0) return (ENXIO); device_set_desc(dev, OPENPIC_DEVSTR); return (0); } Index: head/sys/powerpc/powerpc/intr_machdep.c =================================================================== --- head/sys/powerpc/powerpc/intr_machdep.c (revision 176207) +++ head/sys/powerpc/powerpc/intr_machdep.c (revision 176208) @@ -1,306 +1,306 @@ /*- * Copyright (c) 1991 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /*- * Copyright (c) 2002 Benno Rice. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 * form: src/sys/i386/isa/intr_machdep.c,v 1.57 2001/07/20 * * $FreeBSD$ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pic_if.h" #define MAX_STRAY_LOG 5 MALLOC_DEFINE(M_INTR, "intr", "interrupt handler data"); struct powerpc_intr { struct intr_event *event; long *cntp; u_int irq; }; static struct powerpc_intr *powerpc_intrs[INTR_VECTORS]; static u_int nvectors; /* Allocated vectors */ static u_int stray_count; device_t pic; static void intrcnt_setname(const char *name, int index) { snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name); } #ifdef INTR_FILTER static void powerpc_intr_eoi(void *arg) { u_int irq = (uintptr_t)arg; PIC_EOI(pic, irq); } static void powerpc_intr_mask(void *arg) { u_int irq = (uintptr_t)arg; PIC_MASK(pic, irq); } #endif static void powerpc_intr_unmask(void *arg) { u_int irq = (uintptr_t)arg; PIC_UNMASK(pic, irq); } void -powerpc_register_pic(device_t dev) +powerpc_register_pic(device_t dev, u_int ipi) { pic = dev; } int powerpc_enable_intr(void) { struct powerpc_intr *i; int vector; for (vector = 0; vector < nvectors; vector++) { i = powerpc_intrs[vector]; if (i == NULL) continue; PIC_ENABLE(pic, i->irq, vector); } return (0); } int powerpc_setup_intr(const char *name, u_int irq, driver_filter_t filter, driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep) { struct powerpc_intr *i; u_int vector; int error; /* XXX lock */ i = NULL; for (vector = 0; vector < nvectors; vector++) { i = powerpc_intrs[vector]; if (i == NULL) continue; if (i->irq == irq) break; i = NULL; } if (i == NULL) { if (nvectors >= INTR_VECTORS) { /* XXX unlock */ return (ENOENT); } i = malloc(sizeof(*i), M_INTR, M_NOWAIT); if (i == NULL) { /* XXX unlock */ return (ENOMEM); } error = intr_event_create(&i->event, (void *)irq, 0, powerpc_intr_unmask, #ifdef INTR_FILTER powerpc_intr_eoi, powerpc_intr_mask, #endif "irq%u:", irq); if (error) { /* XXX unlock */ free(i, M_INTR); return (error); } vector = nvectors++; powerpc_intrs[vector] = i; i->irq = irq; /* XXX unlock */ i->cntp = &intrcnt[vector]; intrcnt_setname(i->event->ie_fullname, vector); if (!cold) PIC_ENABLE(pic, i->irq, vector); } else { /* XXX unlock */ } error = intr_event_add_handler(i->event, name, filter, handler, arg, intr_priority(flags), flags, cookiep); if (!error) intrcnt_setname(i->event->ie_fullname, vector); return (error); } int powerpc_teardown_intr(void *cookie) { return (intr_event_remove_handler(cookie)); } void powerpc_dispatch_intr(u_int vector, struct trapframe *tf) { struct powerpc_intr *i; struct intr_event *ie; #ifndef INTR_FILTER struct intr_handler *ih; int error, sched, ret; #endif i = powerpc_intrs[vector]; if (i == NULL) goto stray; (*i->cntp)++; ie = i->event; KASSERT(ie != NULL, ("%s: interrupt without an event", __func__)); #ifdef INTR_FILTER if (intr_event_handle(ie, tf) != 0) { PIC_MASK(pic, i->irq); log(LOG_ERR, "stray irq%u\n", i->irq); } #else if (TAILQ_EMPTY(&ie->ie_handlers)) goto stray; /* * Execute all fast interrupt handlers directly without Giant. Note * that this means that any fast interrupt handler must be MP safe. */ ret = 0; sched = 0; critical_enter(); TAILQ_FOREACH(ih, &ie->ie_handlers, ih_next) { if (ih->ih_filter == NULL) { sched = 1; continue; } CTR4(KTR_INTR, "%s: exec %p(%p) for %s", __func__, ih->ih_filter, ih->ih_argument, ih->ih_name); ret = ih->ih_filter(ih->ih_argument); /* * Wrapper handler special case: see * i386/intr_machdep.c::intr_execute_handlers() */ if (!sched) { if (ret == FILTER_SCHEDULE_THREAD) sched = 1; } } if (sched) { PIC_MASK(pic, i->irq); error = intr_event_schedule_thread(ie); KASSERT(error == 0, ("%s: impossible stray interrupt", __func__)); } else PIC_EOI(pic, i->irq); critical_exit(); #endif return; stray: stray_count++; if (stray_count <= MAX_STRAY_LOG) { printf("stray irq %d\n", i->irq); if (stray_count >= MAX_STRAY_LOG) { printf("got %d stray interrupts, not logging anymore\n", MAX_STRAY_LOG); } } if (i != NULL) PIC_MASK(pic, i->irq); } Index: head/sys/powerpc/powerpc/openpic.c =================================================================== --- head/sys/powerpc/powerpc/openpic.c (revision 176207) +++ head/sys/powerpc/powerpc/openpic.c (revision 176208) @@ -1,238 +1,273 @@ /*- * Copyright (C) 2002 Benno Rice. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pic_if.h" devclass_t openpic_devclass; /* * Local routines */ static __inline uint32_t openpic_read(struct openpic_softc *sc, u_int reg) { return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg)); } static __inline void openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val) { bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val); } static __inline void -openpic_set_priority(struct openpic_softc *sc, int cpu, int pri) +openpic_set_priority(struct openpic_softc *sc, int pri) { + u_int tpr; uint32_t x; - x = openpic_read(sc, OPENPIC_CPU_PRIORITY(cpu)); - x &= ~OPENPIC_CPU_PRIORITY_MASK; + tpr = OPENPIC_PCPU_TPR(PCPU_GET(cpuid)); + x = openpic_read(sc, tpr); + x &= ~OPENPIC_TPR_MASK; x |= pri; - openpic_write(sc, OPENPIC_CPU_PRIORITY(cpu), x); + openpic_write(sc, tpr, x); } int openpic_attach(device_t dev) { struct openpic_softc *sc; - u_int irq; + u_int ipi, irq; u_int32_t x; sc = device_get_softc(dev); sc->sc_dev = dev; sc->sc_rid = 0; sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, RF_ACTIVE); if (sc->sc_memr == NULL) { device_printf(dev, "Could not alloc mem resource!\n"); return (ENXIO); } sc->sc_bt = rman_get_bustag(sc->sc_memr); sc->sc_bh = rman_get_bushandle(sc->sc_memr); x = openpic_read(sc, OPENPIC_FEATURE); switch (x & OPENPIC_FEATURE_VERSION_MASK) { case 1: sc->sc_version = "1.0"; break; case 2: sc->sc_version = "1.2"; break; case 3: sc->sc_version = "1.3"; break; default: sc->sc_version = "unknown"; break; } sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >> OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1; sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >> OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1; /* * PSIM seems to report 1 too many IRQs */ if (sc->sc_psim) sc->sc_nirq--; if (bootverbose) device_printf(dev, "Version %s, supports %d CPUs and %d irqs\n", sc->sc_version, sc->sc_ncpu, sc->sc_nirq); - /* disable all interrupts */ - for (irq = 0; irq < sc->sc_nirq; irq++) - openpic_write(sc, OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK); + /* Reset and disable all interrupts. */ + for (irq = 0; irq < sc->sc_nirq; irq++) { + x = irq; /* irq == vector. */ + x |= OPENPIC_IMASK; + x |= OPENPIC_POLARITY_POSITIVE; + x |= OPENPIC_SENSE_LEVEL; + x |= 8 << OPENPIC_PRIORITY_SHIFT; + openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); + } - openpic_set_priority(sc, 0, 15); + /* Reset and disable all IPIs. */ + for (ipi = 0; ipi < 4; ipi++) { + x = sc->sc_nirq + ipi; + x |= OPENPIC_IMASK; + x |= 15 << OPENPIC_PRIORITY_SHIFT; + openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x); + } + openpic_set_priority(sc, 15); + /* we don't need 8259 passthrough mode */ x = openpic_read(sc, OPENPIC_CONFIG); x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; openpic_write(sc, OPENPIC_CONFIG, x); /* send all interrupts to cpu 0 */ for (irq = 0; irq < sc->sc_nirq; irq++) openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0); - for (irq = 0; irq < sc->sc_nirq; irq++) { - x = irq; /* irq == vector. */ - x |= OPENPIC_IMASK; - x |= OPENPIC_POLARITY_POSITIVE; - x |= OPENPIC_SENSE_LEVEL; - x |= 8 << OPENPIC_PRIORITY_SHIFT; - openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); - } - - /* XXX IPI */ /* XXX set spurious intr vector */ - openpic_set_priority(sc, 0, 0); + openpic_set_priority(sc, 0); /* clear all pending interrupts */ for (irq = 0; irq < sc->sc_nirq; irq++) { - (void)openpic_read(sc, OPENPIC_IACK(0)); - openpic_write(sc, OPENPIC_EOI(0), 0); + (void)openpic_read(sc, OPENPIC_PCPU_IACK(PCPU_GET(cpuid))); + openpic_write(sc, OPENPIC_PCPU_EOI(PCPU_GET(cpuid)), 0); } - powerpc_register_pic(dev); + powerpc_register_pic(dev, sc->sc_nirq); return (0); } /* * PIC I/F methods */ void openpic_dispatch(device_t dev, struct trapframe *tf) { struct openpic_softc *sc; u_int vector; sc = device_get_softc(dev); while (1) { - vector = openpic_read(sc, OPENPIC_IACK(0)); + vector = openpic_read(sc, OPENPIC_PCPU_IACK(PCPU_GET(cpuid))); vector &= OPENPIC_VECTOR_MASK; if (vector == 255) break; powerpc_dispatch_intr(vector, tf); } } void openpic_enable(device_t dev, u_int irq, u_int vector) { struct openpic_softc *sc; uint32_t x; sc = device_get_softc(dev); - x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); - x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK); - x |= vector; - openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); + if (irq < sc->sc_nirq) { + x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); + x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK); + x |= vector; + openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); + } else { + x = openpic_read(sc, OPENPIC_IPI_VECTOR(0)); + x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK); + x |= vector; + openpic_write(sc, OPENPIC_IPI_VECTOR(0), x); + } } void openpic_eoi(device_t dev, u_int irq __unused) { struct openpic_softc *sc; sc = device_get_softc(dev); - openpic_write(sc, OPENPIC_EOI(0), 0); + openpic_write(sc, OPENPIC_PCPU_EOI(PCPU_GET(cpuid)), 0); } void +openpic_ipi(device_t dev, u_int cpu) +{ + struct openpic_softc *sc; + + sc = device_get_softc(dev); + openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0), + 1u << cpu); +} + +void openpic_mask(device_t dev, u_int irq) { struct openpic_softc *sc; uint32_t x; sc = device_get_softc(dev); - x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); - x |= OPENPIC_IMASK; - openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); - openpic_write(sc, OPENPIC_EOI(0), 0); + if (irq < sc->sc_nirq) { + x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); + x |= OPENPIC_IMASK; + openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); + } else { + x = openpic_read(sc, OPENPIC_IPI_VECTOR(0)); + x |= OPENPIC_IMASK; + openpic_write(sc, OPENPIC_IPI_VECTOR(0), x); + } + openpic_write(sc, OPENPIC_PCPU_EOI(PCPU_GET(cpuid)), 0); } void openpic_unmask(device_t dev, u_int irq) { struct openpic_softc *sc; uint32_t x; sc = device_get_softc(dev); - x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); - x &= ~OPENPIC_IMASK; - openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); + if (irq < sc->sc_nirq) { + x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); + x &= ~OPENPIC_IMASK; + openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); + } else { + x = openpic_read(sc, OPENPIC_IPI_VECTOR(0)); + x &= ~OPENPIC_IMASK; + openpic_write(sc, OPENPIC_IPI_VECTOR(0), x); + } } Index: head/sys/powerpc/powerpc/pic_if.m =================================================================== --- head/sys/powerpc/powerpc/pic_if.m (revision 176207) +++ head/sys/powerpc/powerpc/pic_if.m (revision 176208) @@ -1,59 +1,64 @@ #- # Copyright (c) 1998 Doug Rabson # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions # are met: # 1. Redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer. # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. # # THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS # OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) # HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT # LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF # SUCH DAMAGE. # # from: src/sys/kern/bus_if.m,v 1.21 2002/04/21 11:16:10 markm Exp # $FreeBSD$ # #include #include INTERFACE pic; METHOD void dispatch { device_t dev; struct trapframe *tf; }; METHOD void enable { device_t dev; u_int irq; u_int vector; }; METHOD void eoi { device_t dev; u_int irq; }; +METHOD void ipi { + device_t dev; + u_int cpu; +}; + METHOD void mask { device_t dev; u_int irq; }; METHOD void unmask { device_t dev; u_int irq; }; Index: head/sys/powerpc/psim/openpic_iobus.c =================================================================== --- head/sys/powerpc/psim/openpic_iobus.c (revision 176207) +++ head/sys/powerpc/psim/openpic_iobus.c (revision 176208) @@ -1,106 +1,107 @@ /*- * Copyright 2003 by Peter Grehan. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ /* * The psim iobus attachment for the OpenPIC interrupt controller. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pic_if.h" /* * PSIM IOBus interface */ static int openpic_iobus_probe(device_t); static device_method_t openpic_iobus_methods[] = { /* Device interface */ DEVMETHOD(device_probe, openpic_iobus_probe), DEVMETHOD(device_attach, openpic_attach), /* PIC interface */ DEVMETHOD(pic_dispatch, openpic_dispatch), DEVMETHOD(pic_enable, openpic_enable), DEVMETHOD(pic_eoi, openpic_eoi), + DEVMETHOD(pic_ipi, openpic_ipi), DEVMETHOD(pic_mask, openpic_mask), DEVMETHOD(pic_unmask, openpic_unmask), { 0, 0 } }; static driver_t openpic_iobus_driver = { "openpic", openpic_iobus_methods, sizeof(struct openpic_softc) }; DRIVER_MODULE(openpic, iobus, openpic_iobus_driver, openpic_devclass, 0, 0); static int openpic_iobus_probe(device_t dev) { char *name; name = iobus_get_name(dev); if (strcmp(name, "interrupt-controller") != 0) return (ENXIO); /* * The description was already printed out in the nexus * probe, so don't do it again here */ device_set_desc(dev, OPENPIC_DEVSTR); return (0); }