Index: head/sys/dev/mii/brgphy.c =================================================================== --- head/sys/dev/mii/brgphy.c (revision 168600) +++ head/sys/dev/mii/brgphy.c (revision 168601) @@ -1,816 +1,817 @@ /*- * Copyright (c) 2000 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. */ #include #include #include #include #include #include #include #include #include #include #include #include "miidevs.h" #include #include #include #include #include #include #include #include "miibus_if.h" static int brgphy_probe(device_t); static int brgphy_attach(device_t); struct brgphy_softc { struct mii_softc mii_sc; int mii_model; int mii_rev; }; static device_method_t brgphy_methods[] = { /* device interface */ DEVMETHOD(device_probe, brgphy_probe), DEVMETHOD(device_attach, brgphy_attach), DEVMETHOD(device_detach, mii_phy_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), { 0, 0 } }; static devclass_t brgphy_devclass; static driver_t brgphy_driver = { "brgphy", brgphy_methods, sizeof(struct brgphy_softc) }; DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); static int brgphy_service(struct mii_softc *, struct mii_data *, int); static void brgphy_setmedia(struct mii_softc *, int, int); static void brgphy_status(struct mii_softc *); static int brgphy_mii_phy_auto(struct mii_softc *); static void brgphy_reset(struct mii_softc *); static void brgphy_loop(struct mii_softc *); static int bcm5706_is_tbi(device_t); static void bcm5401_load_dspcode(struct mii_softc *); static void bcm5411_load_dspcode(struct mii_softc *); static void brgphy_fixup_5704_a0_bug(struct mii_softc *); static void brgphy_fixup_adc_bug(struct mii_softc *); static void brgphy_fixup_adjust_trim(struct mii_softc *); static void brgphy_fixup_ber_bug(struct mii_softc *); static void brgphy_fixup_crc_bug(struct mii_softc *); static void brgphy_fixup_jitter_bug(struct mii_softc *); static void brgphy_ethernet_wirespeed(struct mii_softc *); static void brgphy_jumbo_settings(struct mii_softc *, u_long); static const struct mii_phydesc brgphys[] = { MII_PHY_DESC(xxBROADCOM, BCM5400), MII_PHY_DESC(xxBROADCOM, BCM5401), MII_PHY_DESC(xxBROADCOM, BCM5411), MII_PHY_DESC(xxBROADCOM, BCM5701), MII_PHY_DESC(xxBROADCOM, BCM5703), MII_PHY_DESC(xxBROADCOM, BCM5704), MII_PHY_DESC(xxBROADCOM, BCM5705), MII_PHY_DESC(xxBROADCOM, BCM5706C), MII_PHY_DESC(xxBROADCOM, BCM5714), MII_PHY_DESC(xxBROADCOM, BCM5750), MII_PHY_DESC(xxBROADCOM, BCM5752), MII_PHY_DESC(xxBROADCOM, BCM5754), MII_PHY_DESC(xxBROADCOM, BCM5780), MII_PHY_DESC(xxBROADCOM, BCM5708C), + MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755), MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787), MII_PHY_END }; static int brgphy_probe(device_t dev) { struct mii_attach_args *ma; int error; error = mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT); if (error != BUS_PROBE_DEFAULT) return (error); ma = device_get_ivars(dev); if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5706C) { /* * Broadcom uses the same MII model ID on two * different types of phys. The first is found on the * BCM 5706 and is supported by this driver. The * other is found on the BCM 5706S and 5708S and is * supported by the gentbi(4) driver, so we check to * see if this phy is supported by gentbi(4) and fail * the probe if so. */ if (bcm5706_is_tbi(dev)) return (ENXIO); } return (error); } static int brgphy_attach(device_t dev) { struct brgphy_softc *bsc; struct mii_softc *sc; struct mii_attach_args *ma; struct mii_data *mii; const char *sep = ""; struct bge_softc *bge_sc = NULL; struct bce_softc *bce_sc = NULL; int fast_ether_only = FALSE; bsc = device_get_softc(dev); sc = &bsc->mii_sc; ma = device_get_ivars(dev); sc->mii_dev = device_get_parent(dev); mii = device_get_softc(sc->mii_dev); LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); sc->mii_inst = mii->mii_instance; sc->mii_phy = ma->mii_phyno; sc->mii_service = brgphy_service; sc->mii_pdata = mii; sc->mii_flags |= MIIF_NOISOLATE; mii->mii_instance++; #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) #define PRINT(s) printf("%s%s", sep, s); sep = ", " ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), BMCR_ISO); #if 0 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), BMCR_LOOP | BMCR_S100); #endif bsc->mii_model = MII_MODEL(ma->mii_id2); bsc->mii_rev = MII_REV(ma->mii_id2); brgphy_reset(sc); sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; sc->mii_capabilities &= ~BMSR_ANEG; device_printf(dev, " "); mii_add_media(sc); /* Find the driver associated with this PHY. */ if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { bge_sc = mii->mii_ifp->if_softc; } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { bce_sc = mii->mii_ifp->if_softc; } /* The 590x chips are 10/100 only. */ if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) fast_ether_only = TRUE; if (fast_ether_only == FALSE) { ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), BRGPHY_BMCR_FDX); PRINT(", 1000baseTX"); ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); PRINT("1000baseTX-FDX"); sc->mii_anegticks = MII_ANEGTICKS_GIGE; } else sc->mii_anegticks = MII_ANEGTICKS; ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); PRINT("auto"); printf("\n"); #undef ADD #undef PRINT MIIBUS_MEDIAINIT(sc->mii_dev); return (0); } static int brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) { struct brgphy_softc *bsc = (struct brgphy_softc *)sc; struct ifmedia_entry *ife = mii->mii_media.ifm_cur; switch (cmd) { case MII_POLLSTAT: /* If we're not polling our PHY instance, just return. */ if (IFM_INST(ife->ifm_media) != sc->mii_inst) return (0); break; case MII_MEDIACHG: /* * If the media indicates a different PHY instance, * isolate ourselves. */ if (IFM_INST(ife->ifm_media) != sc->mii_inst) { PHY_WRITE(sc, MII_BMCR, PHY_READ(sc, MII_BMCR) | BMCR_ISO); return (0); } /* If the interface is not up, don't do anything. */ if ((mii->mii_ifp->if_flags & IFF_UP) == 0) break; brgphy_reset(sc); /* XXX hardware bug work-around */ switch (IFM_SUBTYPE(ife->ifm_media)) { case IFM_AUTO: #ifdef foo /* If we're already in auto mode, just return. */ if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) return (0); #endif (void)brgphy_mii_phy_auto(sc); break; case IFM_1000_T: case IFM_100_TX: case IFM_10_T: brgphy_setmedia(sc, ife->ifm_media, mii->mii_ifp->if_flags & IFF_LINK0); break; #ifdef foo case IFM_NONE: PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); break; #endif case IFM_100_T4: default: return (EINVAL); } break; case MII_TICK: /* If we're not currently selected, just return. */ if (IFM_INST(ife->ifm_media) != sc->mii_inst) return (0); /* Is the interface even up? */ if ((mii->mii_ifp->if_flags & IFF_UP) == 0) return (0); /* Only used for autonegotiation. */ if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { sc->mii_ticks = 0; /* Reset autoneg timer. */ break; } /* * Check to see if we have link. If we do, we don't * need to restart the autonegotiation process. */ if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) { sc->mii_ticks = 0; /* Reset autoneg timer. */ break; } /* Announce link loss right after it happens. */ if (sc->mii_ticks++ == 0) break; /* Only retry autonegotiation every mii_anegticks seconds. */ if (sc->mii_ticks <= sc->mii_anegticks) return (0); sc->mii_ticks = 0; (void)brgphy_mii_phy_auto(sc); break; } /* Update the media status. */ brgphy_status(sc); /* * Callback if something changed. Note that we need to poke * the DSP on the Broadcom PHYs if the media changes. */ if (sc->mii_media_active != mii->mii_media_active || sc->mii_media_status != mii->mii_media_status || cmd == MII_MEDIACHG) { switch (bsc->mii_model) { case MII_MODEL_xxBROADCOM_BCM5400: bcm5401_load_dspcode(sc); break; case MII_MODEL_xxBROADCOM_BCM5401: if (bsc->mii_rev == 1 || bsc->mii_rev == 3) bcm5401_load_dspcode(sc); break; case MII_MODEL_xxBROADCOM_BCM5411: bcm5411_load_dspcode(sc); break; } } mii_phy_update(sc, cmd); return (0); } static void brgphy_setmedia(struct mii_softc *sc, int media, int master) { struct brgphy_softc *bsc = (struct brgphy_softc *)sc; int bmcr, gig; switch (IFM_SUBTYPE(media)) { case IFM_1000_T: bmcr = BRGPHY_S1000; break; case IFM_100_TX: bmcr = BRGPHY_S100; break; case IFM_10_T: default: bmcr = BRGPHY_S10; break; } if ((media & IFM_GMASK) == IFM_FDX) { bmcr |= BRGPHY_BMCR_FDX; gig = BRGPHY_1000CTL_AFD; } else { gig = BRGPHY_1000CTL_AHD; } brgphy_loop(sc); PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); if (IFM_SUBTYPE(media) != IFM_1000_T) return; PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); if (bsc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) return; /* * When setting the link manually, one side must be the master and * the other the slave. However ifmedia doesn't give us a good way * to specify this, so we fake it by using one of the LINK flags. * If LINK0 is set, we program the PHY to be a master, otherwise * it's a slave. */ if (master) { PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig | BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC); } else { PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig | BRGPHY_1000CTL_MSE); } } static void brgphy_status(struct mii_softc *sc) { struct mii_data *mii = sc->mii_pdata; int aux, bmcr, bmsr; mii->mii_media_status = IFM_AVALID; mii->mii_media_active = IFM_ETHER; aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); if (aux & BRGPHY_AUXSTS_LINK) mii->mii_media_status |= IFM_ACTIVE; if (bmcr & BRGPHY_BMCR_LOOP) mii->mii_media_active |= IFM_LOOP; if ((bmcr & BRGPHY_BMCR_AUTOEN) && (bmsr & BRGPHY_BMSR_ACOMP) == 0) { /* Erg, still trying, I guess... */ mii->mii_media_active |= IFM_NONE; return; } if (aux & BRGPHY_AUXSTS_LINK) { switch (aux & BRGPHY_AUXSTS_AN_RES) { case BRGPHY_RES_1000FD: mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; case BRGPHY_RES_1000HD: mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; case BRGPHY_RES_100FD: mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; case BRGPHY_RES_100T4: mii->mii_media_active |= IFM_100_T4; break; case BRGPHY_RES_100HD: mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; case BRGPHY_RES_10FD: mii->mii_media_active |= IFM_10_T | IFM_FDX; break; case BRGPHY_RES_10HD: mii->mii_media_active |= IFM_10_T | IFM_HDX; break; default: mii->mii_media_active |= IFM_NONE; break; } } else mii->mii_media_active |= IFM_NONE; } static int brgphy_mii_phy_auto(struct mii_softc *sc) { struct brgphy_softc *bsc = (struct brgphy_softc *)sc; int ktcr = 0; brgphy_loop(sc); brgphy_reset(sc); ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); DELAY(1000); PHY_WRITE(sc, BRGPHY_MII_ANAR, BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); DELAY(1000); PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); return (EJUSTRETURN); } static void brgphy_loop(struct mii_softc *sc) { int i; PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); for (i = 0; i < 15000; i++) { if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) { #if 0 device_printf(sc->mii_dev, "looped %d\n", i); #endif break; } DELAY(10); } } /* * Check to see if a 5706 phy is really a SerDes phy. Copied from * gentbi_probe(). */ static int bcm5706_is_tbi(device_t dev) { device_t parent; struct mii_attach_args *ma; int bmsr, extsr; parent = device_get_parent(dev); ma = device_get_ivars(dev); bmsr = MIIBUS_READREG(parent, ma->mii_phyno, MII_BMSR); if ((bmsr & BMSR_EXTSTAT) == 0 || (bmsr & BMSR_MEDIAMASK) != 0) return (0); extsr = MIIBUS_READREG(parent, ma->mii_phyno, MII_EXTSR); if (extsr & (EXTSR_1000TFDX|EXTSR_1000THDX)) return (0); if (extsr & (EXTSR_1000XFDX|EXTSR_1000XHDX)) return (1); return (0); } /* Turn off tap power management on 5401. */ static void bcm5401_load_dspcode(struct mii_softc *sc) { static const struct { int reg; uint16_t val; } dspcode[] = { { BRGPHY_MII_AUXCTL, 0x0c20 }, { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, { 0, 0 }, }; int i; for (i = 0; dspcode[i].reg != 0; i++) PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); DELAY(40); } static void bcm5411_load_dspcode(struct mii_softc *sc) { static const struct { int reg; uint16_t val; } dspcode[] = { { 0x1c, 0x8c23 }, { 0x1c, 0x8ca3 }, { 0x1c, 0x8c23 }, { 0, 0 }, }; int i; for (i = 0; dspcode[i].reg != 0; i++) PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); } static void brgphy_fixup_5704_a0_bug(struct mii_softc *sc) { static const struct { int reg; uint16_t val; } dspcode[] = { { 0x1c, 0x8d68 }, { 0x1c, 0x8d68 }, { 0, 0 }, }; int i; for (i = 0; dspcode[i].reg != 0; i++) PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); } static void brgphy_fixup_adc_bug(struct mii_softc *sc) { static const struct { int reg; uint16_t val; } dspcode[] = { { BRGPHY_MII_AUXCTL, 0x0c00 }, { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, { 0, 0 }, }; int i; for (i = 0; dspcode[i].reg != 0; i++) PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); } static void brgphy_fixup_adjust_trim(struct mii_softc *sc) { static const struct { int reg; uint16_t val; } dspcode[] = { { BRGPHY_MII_AUXCTL, 0x0c00 }, { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, { BRGPHY_MII_DSP_RW_PORT, 0x110b }, { BRGPHY_MII_TEST1, 0x0014 }, { BRGPHY_MII_AUXCTL, 0x0400 }, { 0, 0 }, }; int i; for (i = 0; dspcode[i].reg != 0; i++) PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); } static void brgphy_fixup_ber_bug(struct mii_softc *sc) { static const struct { int reg; uint16_t val; } dspcode[] = { { BRGPHY_MII_AUXCTL, 0x0c00 }, { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, { BRGPHY_MII_DSP_RW_PORT, 0x310b }, { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, { BRGPHY_MII_AUXCTL, 0x0400 }, { 0, 0 }, }; int i; for (i = 0; dspcode[i].reg != 0; i++) PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); } static void brgphy_fixup_crc_bug(struct mii_softc *sc) { static const struct { int reg; uint16_t val; } dspcode[] = { { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, { 0x1c, 0x8c68 }, { 0x1c, 0x8d68 }, { 0x1c, 0x8c68 }, { 0, 0 }, }; int i; for (i = 0; dspcode[i].reg != 0; i++) PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); } static void brgphy_fixup_jitter_bug(struct mii_softc *sc) { static const struct { int reg; uint16_t val; } dspcode[] = { { BRGPHY_MII_AUXCTL, 0x0c00 }, { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, { BRGPHY_MII_DSP_RW_PORT, 0x010b }, { BRGPHY_MII_AUXCTL, 0x0400 }, { 0, 0 }, }; int i; for (i = 0; dspcode[i].reg != 0; i++) PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); } static void brgphy_ethernet_wirespeed(struct mii_softc *sc) { uint32_t val; /* Enable Ethernet@WireSpeed. */ PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); val = PHY_READ(sc, BRGPHY_MII_AUXCTL); PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); } static void brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) { struct brgphy_softc *bsc = (struct brgphy_softc *)sc; uint32_t val; /* Set or clear jumbo frame settings in the PHY. */ if (mtu > ETHER_MAX_LEN) { if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { /* BCM5401 PHY cannot read-modify-write. */ PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); } else { PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); val = PHY_READ(sc, BRGPHY_MII_AUXCTL); PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | BRGPHY_AUXCTL_LONG_PKT); } val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, val | BRGPHY_PHY_EXTCTL_HIGH_LA); } else { PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); val = PHY_READ(sc, BRGPHY_MII_AUXCTL); PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); } } static void brgphy_reset(struct mii_softc *sc) { struct brgphy_softc *bsc = (struct brgphy_softc *)sc; struct bge_softc *bge_sc = NULL; struct bce_softc *bce_sc = NULL; struct ifnet *ifp; mii_phy_reset(sc); switch (bsc->mii_model) { case MII_MODEL_xxBROADCOM_BCM5400: bcm5401_load_dspcode(sc); break; case MII_MODEL_xxBROADCOM_BCM5401: if (bsc->mii_rev == 1 || bsc->mii_rev == 3) bcm5401_load_dspcode(sc); break; case MII_MODEL_xxBROADCOM_BCM5411: bcm5411_load_dspcode(sc); break; } ifp = sc->mii_pdata->mii_ifp; /* Find the driver associated with this PHY. */ if (strcmp(ifp->if_dname, "bge") == 0) { bge_sc = ifp->if_softc; } else if (strcmp(ifp->if_dname, "bce") == 0) { bce_sc = ifp->if_softc; } /* Handle any NetXtreme/bge workarounds. */ if (bge_sc) { /* Fix up various bugs */ if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) brgphy_fixup_5704_a0_bug(sc); if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) brgphy_fixup_adc_bug(sc); if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) brgphy_fixup_adjust_trim(sc); if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) brgphy_fixup_ber_bug(sc); if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) brgphy_fixup_crc_bug(sc); if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) brgphy_fixup_jitter_bug(sc); brgphy_jumbo_settings(sc, ifp->if_mtu); /* * Don't enable Ethernet@WireSpeed for the 5700 or the * 5705 A1 and A2 chips. */ if (bge_sc->bge_asicrev != BGE_ASICREV_BCM5700 && bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A1 && bge_sc->bge_chipid != BGE_CHIPID_BCM5705_A2) brgphy_ethernet_wirespeed(sc); /* Enable Link LED on Dell boxes */ if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & ~BRGPHY_PHY_EXTCTL_3_LED); } } else if (bce_sc) { brgphy_fixup_ber_bug(sc); brgphy_jumbo_settings(sc, ifp->if_mtu); brgphy_ethernet_wirespeed(sc); } } Index: head/sys/dev/mii/miidevs =================================================================== --- head/sys/dev/mii/miidevs (revision 168600) +++ head/sys/dev/mii/miidevs (revision 168601) @@ -1,212 +1,213 @@ $FreeBSD$ /*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/ /*- * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, * NASA Ames Research Center. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the NetBSD * Foundation, Inc. and its contributors. * 4. Neither the name of The NetBSD Foundation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * List of known MII OUIs. * For a complete list see http://standards.ieee.org/regauth/oui/ * * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped * to the 16 bits available in the id registers. The MII_OUI() macro * in "mii.h" reflects the most obvious way. If a vendor uses a * different mapping, an "xx" prefixed OUI is defined here which is * mangled accordingly to compensate. */ oui ALTIMA 0x0010a9 Altima Communications oui AMD 0x00001a Advanced Micro Devices oui BROADCOM 0x001018 Broadcom Corporation oui CICADA 0x0003F1 Cicada Semiconductor oui DAVICOM 0x00606e Davicom Semiconductor oui ICPLUS 0x0090c3 IC Plus Corp. oui ICS 0x00a0be Integrated Circuit Systems oui INTEL 0x00aa00 Intel oui JATO 0x00e083 Jato Technologies oui LEVEL1 0x00207b Level 1 oui NATSEMI 0x080017 National Semiconductor oui QUALSEMI 0x006051 Quality Semiconductor oui REALTEK 0x000020 RealTek Semicondctor oui SEEQ 0x00a07d Seeq oui SIS 0x00e006 Silicon Integrated Systems oui TDK 0x00c039 TDK oui TI 0x080028 Texas Instruments oui XAQTI 0x00e0ae XaQti Corp. oui MARVELL 0x005043 Marvell Semiconductor oui xxMARVELL 0x000ac2 Marvell Semiconductor /* in the 79c873, AMD uses another OUI (which matches Davicom!) */ oui xxAMD 0x00606e Advanced Micro Devices /* Intel 82553 A/B steppings */ oui xxINTEL 0x00f800 Intel /* some vendors have the bits swapped within bytes (ie, ordered as on the wire) */ oui xxALTIMA 0x000895 Altima Communications oui xxBROADCOM 0x000818 Broadcom Corporation oui xxBROADCOM_ALT1 0x0050ef Broadcom Corporation oui xxICS 0x00057d Integrated Circuit Systems oui xxSEEQ 0x0005be Seeq oui xxSIS 0x000760 Silicon Integrated Systems oui xxTI 0x100014 Texas Instruments oui xxXAQTI 0x350700 XaQti Corp. /* Level 1 is completely different - from right to left. (Two bits get lost in the third OUI byte.) */ oui xxLEVEL1 0x1e0400 Level 1 /* Don't know what's going on here. */ oui xxDAVICOM 0x006040 Davicom Semiconductor /* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */ oui xxREALTEK 0x000732 /* * List of known models. Grouped by oui. */ /* Altima Communications PHYs */ model xxALTIMA AC101 0x0021 AC101 10/100 media interface model xxALTIMA AC101L 0x0012 AC101L 10/100 media interface model xxALTIMA ACXXX 0x0001 ACXXX 10/100 media interface /* Advanced Micro Devices PHYs */ model AMD 79c973phy 0x0036 Am79c973 internal PHY model AMD 79c978 0x0039 Am79c978 HomePNA PHY model xxAMD 79C873 0x0000 Am79C873/DM9101 10/100 media interface /* Broadcom Corp. PHYs. */ model BROADCOM 3C905B 0x0012 3c905B 10/100 internal PHY model BROADCOM 3C905C 0x0017 3c905C 10/100 internal PHY model BROADCOM BCM5201 0x0021 BCM5201 10/100baseTX PHY model BROADCOM BCM5221 0x001e BCM5221 10/100baseTX PHY model BROADCOM BCM4401 0x0036 BCM4401 10/100baseTX PHY model xxBROADCOM BCM5400 0x0004 Broadcom 1000baseTX PHY model xxBROADCOM BCM5401 0x0005 BCM5401 10/100/1000baseTX PHY model xxBROADCOM BCM5411 0x0007 BCM5411 10/100/1000baseTX PHY model xxBROADCOM BCM5754 0x000e BCM5754 10/100/1000baseTX PHY model xxBROADCOM BCM5752 0x0010 BCM5752 10/100/1000baseTX PHY model xxBROADCOM BCM5701 0x0011 BCM5701 10/100/1000baseTX PHY model xxBROADCOM BCM5706C 0x0015 BCM5706C 10/100/1000baseTX PHY model xxBROADCOM BCM5703 0x0016 BCM5703 10/100/1000baseTX PHY model xxBROADCOM BCM5704 0x0019 BCM5704 10/100/1000baseTX PHY model xxBROADCOM BCM5705 0x001a BCM5705 10/100/1000baseTX PHY model xxBROADCOM BCM5750 0x0018 BCM5750 10/100/1000baseTX PHY model xxBROADCOM BCM5714 0x0034 BCM5714 10/100/1000baseTX PHY model xxBROADCOM BCM5780 0x0035 BCM5780 10/100/1000baseTX PHY model xxBROADCOM BCM5708C 0x0036 BCM5708C 10/100/1000baseTX PHY +model xxBROADCOM_ALT1 BCM5755 0x000c BCM5755 10/100/1000baseTX PHY model xxBROADCOM_ALT1 BCM5787 0x000e BCM5787 10/100/1000baseTX PHY /* Cicada Semiconductor PHYs (now owned by Vitesse?) */ model CICADA CS8201 0x0001 Cicada CS8201 10/100/1000TX PHY model CICADA CS8201A 0x0020 Cicada CS8201 10/100/1000TX PHY model CICADA CS8201B 0x0021 Cicada CS8201 10/100/1000TX PHY /* Davicom Semiconductor PHYs */ model DAVICOM DM9102 0x0004 DM9102 10/100 media interface model xxDAVICOM DM9101 0x0000 DM9101 10/100 media interface /* Integrated Circuit Systems PHYs */ model xxICS 1890 0x0002 ICS1890 10/100 media interface /* IC Plus Corp. PHYs */ model ICPLUS IP1000A 0x0008 IC Plus 10/100/1000 media interface /* Intel PHYs */ model xxINTEL I82553AB 0x0000 i83553 10/100 media interface model INTEL I82555 0x0015 i82555 10/100 media interface model INTEL I82562EM 0x0032 i82562EM 10/100 media interface model INTEL I82562ET 0x0033 i82562ET 10/100 media interface model INTEL I82553C 0x0035 i82553 10/100 media interface /* Jato Technologies PHYs */ model JATO BASEX 0x0000 Jato 1000baseX media interface /* Level 1 PHYs */ model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface /* National Semiconductor PHYs */ model NATSEMI DP83840 0x0000 DP83840 10/100 media interface model NATSEMI DP83843 0x0001 DP83843 10/100 media interface model NATSEMI DP83891 0x0005 DP83891 10/100/1000 media interface model NATSEMI DP83861 0x0006 DP83861 10/100/1000 media interface /* Quality Semiconductor PHYs */ model QUALSEMI QS6612 0x0000 QS6612 10/100 media interface /* RealTek Semiconductor PHYs */ model REALTEK RTL8201L 0x0020 RTL8201L 10/100 media interface model xxREALTEK RTL8305SC 0x0005 RTL8305SC 10/100 802.1q switch model xxREALTEK RTL8169S 0x0011 RTL8169S/8110S media interface /* Seeq PHYs */ model xxSEEQ 80220 0x0003 Seeq 80220 10/100 media interface model xxSEEQ 84220 0x0004 Seeq 84220 10/100 media interface /* Silicon Integrated Systems PHYs */ model xxSIS 900 0x0000 SiS 900 10/100 media interface /* TDK */ model TDK 78Q2120 0x0014 TDK 78Q2120 media interface /* Texas Instruments PHYs */ model xxTI TLAN10T 0x0001 ThunderLAN 10baseT media interface model xxTI 100VGPMI 0x0002 ThunderLAN 100VG-AnyLan media interface /* XaQti Corp. PHYs. */ model XAQTI XMACII 0x0000 XaQti Corp. XMAC II gigabit interface /* Marvell Semiconductor PHYs */ model MARVELL E1000 0x0000 Marvell 88E1000 Gigabit PHY model MARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY model MARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY model MARVELL E1000S 0x0004 Marvell 88E1000S Gigabit PHY model MARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY model MARVELL E1000_6 0x0006 Marvell 88E1000 Gigabit PHY model MARVELL E3082 0x0008 Marvell 88E3082 10/100 Fast Ethernet PHY model MARVELL E1112 0x0009 Marvell 88E1112 Gigabit PHY model MARVELL E1149 0x000b Marvell 88E1149 Gigabit PHY model MARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY model MARVELL E1116 0x0021 Marvell 88E1116 Gigabit PHY model MARVELL E1118 0x0022 Marvell 88E1118 Gigabit PHY model xxMARVELL E1000 0x0005 Marvell 88E1000 Gigabit PHY model xxMARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY model xxMARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY model xxMARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY model xxMARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY