Index: head/sys/arm/arm/locore.S =================================================================== --- head/sys/arm/arm/locore.S (revision 137272) +++ head/sys/arm/arm/locore.S (revision 137273) @@ -1,338 +1,351 @@ /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */ /* * Copyright (C) 1994-1997 Mark Brinicombe * Copyright (C) 1994 Brini * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of Brini may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include "assym.s" #include #include #include #include __FBSDID("$FreeBSD$"); /* What size should this really be ? It is only used by init_arm() */ #define INIT_ARM_STACK_SIZE 2048 /* * This is for kvm_mkdb, and should be the address of the beginning * of the kernel text segment (not necessarily the same as kernbase). */ #define CPWAIT_BRANCH \ sub pc, pc, #4 #define CPWAIT(tmp) \ mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ CPWAIT_BRANCH /* branch to next insn */ .text .align 0 .globl kernbase .set kernbase,KERNBASE ENTRY_NP(btext) ASENTRY_NP(_start) /* Check if we are running on RAM, if not move ourself to RAM */ #if 0 cmp pc, #PHYSADDR bhi start_inram /* XXX: This is wrong */ #endif b start_inram /* * XXX: this is even more wrong, but RedBoot * use 0x00000000-0x100000000 as virtual * addresses for the RAM. */ /* move me to RAM * XXX: we can use memcpy if it is PIC */ ldr r1, Lcopy_size adr r0, _C_LABEL(_start) add r1, r1, #3 mov r1, r1, LSR #2 mov r2, #PHYSADDR add r2, r2, #0x00200000 mov r4, r2 5: ldr r3,[r0],#4 str r3,[r2],#4 subs r1,r1,#1 bhi 5b /* Jump to RAM */ ldr r0, Lstart_off add pc, r4, r0 Lcopy_size: .word _edata-_C_LABEL(_start) Lstart_off: .word start_inram-_C_LABEL(_start) start_inram: adr r7, Lunmapped bic r7, r7, #0xff000000 orr r7, r7, #PHYSADDR /* Disable MMU for a while */ mrc p15, 0, r2, c1, c0, 0 bic r2, r2, #CPU_CONTROL_MMU_ENABLE mcr p15, 0, r2, c1, c0, 0 nop nop nop mov pc, r7 Lunmapped: #ifdef STARTUP_PAGETABLE_ADDR /* build page table from scratch */ ldr r0, Lstartup_pagetable adr r4, mmu_init_table b 3f 2: str r3, [r0, r2] add r2, r2, #4 add r3, r3, #(L1_S_SIZE) adds r1, r1, #-1 bhi 2b 3: ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ cmp r1, #0 bne 2b mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #CPU_CONTROL_MMU_ENABLE mcr p15, 0, r0, c1, c0, 0 CPWAIT(r0) bl mmu_done mmu_done: #endif adr r1, .Lstart ldmia r1, {r1, r2, sp} /* Set initial stack and */ sub r2, r2, r1 /* get zero init data */ mov r3, #0 .L1: str r3, [r1], #0x0004 /* Zero the bss */ subs r2, r2, #4 bgt .L1 + ldr r4, =KERNVIRTADDR + cmp pc, r4 +#if KERNVIRTADDR > KERNPHYSADDR + ldrlt r4, =KERNVIRTADDR + ldrlt r5, =KERNPHYSADDR + sublt r4, r4, r5 + addlt pc, pc, r4 +#else + ldrgt r4, =KERNPHYSADDR + ldrgt r5, =KERNVIRTADDR + subgt r4, r4, r5 + sublt pc, pc, r4 +#endif ldr fp, =KERNVIRTADDR /* trace back starts here */ bl _C_LABEL(initarm) /* Off we go */ /* init arm will return the new stack pointer. */ mov sp, r0 bl _C_LABEL(mi_startup) /* call mi_startup()! */ adr r0, .Lmainreturned b _C_LABEL(panic) /* NOTEACHED */ #ifdef STARTUP_PAGETABLE_ADDR #define MMU_INIT(va,pa,n_sec,attr) \ .word n_sec ; \ .word 4*((va)>>L1_S_SHIFT) ; \ .word (pa)|(attr) ; Lstartup_pagetable: .word STARTUP_PAGETABLE_ADDR mmu_init_table: /* fill all table VA==PA */ MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) /* map SDRAM VA==PA, WT cacheable */ MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) /* map VA 0xc0000000..0xc3ffffff to PA */ MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) MMU_INIT(0xfe800000, 0xfe800000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) .word 0 /* end of table */ #endif .Lstart: .word _edata .word _end .word svcstk + INIT_ARM_STACK_SIZE .Lmainreturned: .asciz "main() returned" .align 0 .bss svcstk: .space INIT_ARM_STACK_SIZE .text .align 0 #ifndef OFW /* OFW based systems will used OF_boot() */ .Lcpufuncs: .word _C_LABEL(cpufuncs) ENTRY_NP(cpu_halt) mrs r2, cpsr bic r2, r2, #(PSR_MODE) orr r2, r2, #(PSR_SVC32_MODE) orr r2, r2, #(I32_bit | F32_bit) msr cpsr_all, r2 ldr r4, .Lcpu_reset_address ldr r4, [r4] ldr r0, .Lcpufuncs mov lr, pc ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] /* * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's * necessary. */ ldr r1, .Lcpu_reset_needs_v4_MMU_disable ldr r1, [r1] cmp r1, #0 mov r2, #0 /* * MMU & IDC off, 32 bit program & data space * Hurl ourselves into the ROM */ mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) mcr 15, 0, r0, c1, c0, 0 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ mov pc, r4 /* * _cpu_reset_address contains the address to branch to, to complete * the cpu reset after turning the MMU off * This variable is provided by the hardware specific code */ .Lcpu_reset_address: .word _C_LABEL(cpu_reset_address) /* * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the * v4 MMU disable instruction needs executing... it is an illegal instruction * on f.e. ARM6/7 that locks up the computer in an endless illegal * instruction / data-abort / reset loop. */ .Lcpu_reset_needs_v4_MMU_disable: .word _C_LABEL(cpu_reset_needs_v4_MMU_disable) #endif /* OFW */ #ifdef IPKDB /* * Execute(inst, psr, args, sp) * * Execute INSTruction with PSR and ARGS[0] - ARGS[3] making * available stack at SP for next undefined instruction trap. * * Move the instruction onto the stack and jump to it. */ ENTRY_NP(Execute) mov ip, sp stmfd sp!, {r2, r4-r7, fp, ip, lr, pc} sub fp, ip, #4 mov ip, r3 ldr r7, .Lreturn stmfd sp!, {r0, r7} adr r7, #.LExec mov r5, r1 mrs r4, cpsr ldmia r2, {r0-r3} mov r6, sp mov sp, ip msr cpsr_all, r5 mov pc, r6 .LExec: mrs r5, cpsr /* XXX Cannot switch thus easily back from user mode */ msr cpsr_all, r4 add sp, r6, #8 ldmfd sp!, {r6} stmia r6, {r0-r3} mov r0, r5 ldmdb fp, {r4-r7, fp, sp, pc} .Lreturn: mov pc, r7 #endif /* * setjump + longjmp */ ENTRY(setjmp) stmia r0, {r4-r14} mov r0, #0x00000000 mov pc, lr ENTRY(longjmp) ldmia r0, {r4-r14} mov r0, #0x00000001 mov pc, lr .data .global _C_LABEL(esym) _C_LABEL(esym): .word _C_LABEL(end) ENTRY_NP(abort) b _C_LABEL(abort) ENTRY_NP(sigcode) mov r0, sp swi SYS_sigreturn /* Well if that failed we better exit quick ! */ swi SYS_exit b . - 8 .align 0 .global _C_LABEL(esigcode) _C_LABEL(esigcode): .data .global szsigcode szsigcode: .long esigcode-sigcode /* End of locore.S */ Index: head/sys/arm/xscale/i80321/iq31244_machdep.c =================================================================== --- head/sys/arm/xscale/i80321/iq31244_machdep.c (revision 137272) +++ head/sys/arm/xscale/i80321/iq31244_machdep.c (revision 137273) @@ -1,460 +1,434 @@ /* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ /* * Copyright (c) 1994-1998 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * RiscBSD kernel project * * machdep.c * * Machine dependant functions for kernel setup * * This file needs a lot of work. * * Created : 17/09/94 */ #include "opt_msgbuf.h" #include __FBSDID("$FreeBSD$"); #define _ARM32_BUS_DMA_PRIVATE #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ #define KERNEL_PT_KERNEL 1 /* Page table for mapping kernel */ #define KERNEL_PT_KERNEL_NUM 4 /* L2 table for mapping i80321 */ #define KERNEL_PT_IOPXS (KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM) #define KERNEL_PT_VMDATA (KERNEL_PT_IOPXS + 1) #define KERNEL_PT_VMDATA_NUM 4 #define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM) /* Define various stack sizes in pages */ #define IRQ_STACK_SIZE 1 #define ABT_STACK_SIZE 1 #ifdef IPKDB #define UND_STACK_SIZE 2 #else #define UND_STACK_SIZE 1 #endif -#define KERNEL_VM_BASE (KERNBASE + 0x00c00000) -#define KERNEL_VM_SIZE 0x05000000 extern u_int data_abort_handler_address; extern u_int prefetch_abort_handler_address; extern u_int undefined_handler_address; struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; extern void *_end; extern vm_offset_t sa1_cache_clean_addr; extern int *end; struct pcpu __pcpu; struct pcpu *pcpup = &__pcpu; /* Physical and virtual addresses for some global pages */ vm_paddr_t phys_avail[10]; vm_paddr_t physical_start; vm_paddr_t physical_end; vm_offset_t physical_pages; vm_offset_t clean_sva, clean_eva; struct pv_addr systempage; struct pv_addr msgbufpv; struct pv_addr irqstack; struct pv_addr undstack; struct pv_addr abtstack; struct pv_addr kernelstack; struct pv_addr minidataclean; void enable_mmu(vm_offset_t); static struct trapframe proc0_tf; #define IQ80321_OBIO_BASE 0xfe800000UL #define IQ80321_OBIO_SIZE 0x00100000UL /* Static device mappings. */ static const struct pmap_devmap iq80321_devmap[] = { /* * Map the on-board devices VA == PA so that we can access them * with the MMU on or off. */ { IQ80321_OBIO_BASE, IQ80321_OBIO_BASE, IQ80321_OBIO_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, { IQ80321_IOW_VBASE, VERDE_OUT_XLATE_IO_WIN0_BASE, VERDE_OUT_XLATE_IO_WIN_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, { IQ80321_80321_VBASE, VERDE_PMMR_BASE, VERDE_PMMR_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, -#if 0 { - 0x80000000, - 0x80000000, - 0x08000000, - VM_PROT_READ|VM_PROT_WRITE, - PTE_NOCACHE, - }, -#endif - { 0, 0, 0, 0, 0, } }; #define SDRAM_START 0xa0000000 -void DO_corb(void); extern vm_offset_t xscale_cache_clean_addr; void * initarm(void *arg, void *arg2) { - struct pcpu *pc; struct pv_addr kernel_l1pt; struct pv_addr proc0_uarea; - struct pv_addr altkern[KERNEL_PT_KERNEL_NUM]; int loop; u_int kerneldatasize, symbolsize; u_int l1pagetable; vm_offset_t freemempos; vm_offset_t afterkern; int i = 0; uint32_t fake_preload[35]; uint32_t memsize, memstart; i80321_calibrate_delay(); cninit(); + i = 0; set_cpufuncs(); /* * Fetch the SDRAM start/size from the i80321 SDRAM configration * registers. */ i80321_sdram_bounds(&obio_bs_tag, VERDE_PMMR_BASE + VERDE_MCU_BASE, &memstart, &memsize); fake_preload[i++] = MODINFO_NAME; fake_preload[i++] = strlen("elf kernel") + 1; strcpy((char*)&fake_preload[i++], "elf kernel"); i += 2; fake_preload[i++] = MODINFO_TYPE; fake_preload[i++] = strlen("elf kernel") + 1; strcpy((char*)&fake_preload[i++], "elf kernel"); i += 2; fake_preload[i++] = MODINFO_ADDR; fake_preload[i++] = sizeof(vm_offset_t); - fake_preload[i++] = KERNBASE; + fake_preload[i++] = KERNBASE + 0x00200000; fake_preload[i++] = MODINFO_SIZE; fake_preload[i++] = sizeof(uint32_t); - fake_preload[i++] = (uint32_t)&end - KERNBASE; + fake_preload[i++] = (uint32_t)&end - KERNBASE - 0x00200000; fake_preload[i++] = 0; fake_preload[i] = 0; preload_metadata = (void *)fake_preload; physmem = memsize / PAGE_SIZE; - pc = &__pcpu; - pcpu_init(pc, 0, sizeof(struct pcpu)); + + pcpu_init(pcpup, 0, sizeof(struct pcpu)); PCPU_SET(curthread, &thread0); physical_start = (vm_offset_t) SDRAM_START; physical_end = (vm_offset_t) &end + SDRAM_START - 0xc0000000; afterkern = round_page((vm_offset_t)&end); #define KERNEL_TEXT_BASE (KERNBASE + 0x00200000) kerneldatasize = (u_int32_t)&end - (u_int32_t)KERNEL_TEXT_BASE; symbolsize = 0; freemempos = 0xa0200000; /* Define a macro to simplify memory allocation */ #define valloc_pages(var, np) \ alloc_pages((var).pv_pa, (np)); \ (var).pv_va = (var).pv_pa + 0x20000000; #define alloc_pages(var, np) \ freemempos -= (np * PAGE_SIZE); \ (var) = freemempos; \ memset((char *)(var), 0, ((np) * PAGE_SIZE)); while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) freemempos -= PAGE_SIZE; valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { valloc_pages(kernel_pt_table[loop], L2_TABLE_SIZE / PAGE_SIZE); } - for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++) { - valloc_pages(altkern[loop], L2_TABLE_SIZE / PAGE_SIZE); - } - /* * Allocate a page for the system page mapped to V0x00000000 * This page will just contain the system vectors and can be * shared by all processes. */ valloc_pages(systempage, 1); /* Allocate stacks for all modes */ valloc_pages(irqstack, IRQ_STACK_SIZE); valloc_pages(abtstack, ABT_STACK_SIZE); valloc_pages(undstack, UND_STACK_SIZE); valloc_pages(kernelstack, KSTACK_PAGES); valloc_pages(minidataclean, 1); valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE); /* * Allocate memory for the l1 and l2 page tables. The scheme to avoid * wasting memory by allocating the l1pt on the first 16k memory was * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for * this to work (which is supposed to be the case). */ /* Allocate pages for process 0 kernel stack and uarea */ valloc_pages(proc0_uarea, UAREA_PAGES); /* * Now we start construction of the L1 page table * We start by mapping the L2 page tables into the L1. * This means that we can replace L1 mappings later on if necessary */ - l1pagetable = kernel_l1pt.pv_pa; + l1pagetable = kernel_l1pt.pv_va; /* Map the L2 pages tables in the L1 page table */ pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00400000 - 1), &kernel_pt_table[KERNEL_PT_SYS]); for (i = 0; i < KERNEL_PT_KERNEL_NUM; i++) { pmap_link_l2pt(l1pagetable, KERNBASE + i * 0x00400000, &kernel_pt_table[KERNEL_PT_KERNEL + i]); - pmap_link_l2pt(l1pagetable, 0xa0000000 + i * 0x00400000, - &altkern[i]); } for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; ++loop) - pmap_link_l2pt(l1pagetable, KERNBASE + (KERNEL_PT_KERNEL_NUM + loop) * 0x00400000, + pmap_link_l2pt(l1pagetable, KERNBASE + (i + loop) * 0x00400000, &kernel_pt_table[KERNEL_PT_VMDATA + loop]); pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE, &kernel_pt_table[KERNEL_PT_IOPXS]); pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000, (((uint32_t)(&end) - KERNBASE - 0x200000) + PAGE_SHIFT) & ~PAGE_SHIFT, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - pmap_map_chunk(l1pagetable, KERNPHYSADDR, KERNPHYSADDR, - (((uint32_t)(&end) - KERNBASE - 0x200000) + PAGE_SHIFT) & ~PAGE_SHIFT, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); /* Map the stack pages */ pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa, IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa, ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa, UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa, KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, proc0_uarea.pv_va, proc0_uarea.pv_pa, UAREA_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa, MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va, kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE, - VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); - } - for (loop = 0; loop < 4; loop++) { - pmap_map_chunk(l1pagetable, altkern[loop].pv_va, - altkern[loop].pv_pa, L2_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); } /* Map the Mini-Data cache clean area. */ xscale_setup_minidata(l1pagetable, minidataclean.pv_va, minidataclean.pv_pa); /* Map the vector page. */ pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); pmap_devmap_bootstrap(l1pagetable, iq80321_devmap); /* * Give the XScale global cache clean code an appropriately * sized chunk of unmapped VA space starting at 0xff000000 * (our device mappings end before this address). */ xscale_cache_clean_addr = 0xff000000U; cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); setttb(kernel_l1pt.pv_pa); cpu_tlb_flushID(); cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); /* * Pages were allocated during the secondary bootstrap for the * stacks for different CPU modes. * We must now set the r13 registers in the different CPU modes to * point to these stacks. * Since the ARM stacks use STMFD etc. we must set r13 to the top end * of the stack memory. */ set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); /* * We must now clean the cache again.... * Cleaning may be done by reading new data to displace any * dirty data in the cache. This will have happened in setttb() * but since we are boot strapping the addresses used for the read * may have just been remapped and thus the cache could be out * of sync. A re-clean after the switch will cure this. * After booting there are no gross reloations of the kernel thus * this problem will not occur after initarm(). */ cpu_idcache_wbinv_all(); /* Set stack for exception handlers */ data_abort_handler_address = (u_int)data_abort_handler; prefetch_abort_handler_address = (u_int)prefetch_abort_handler; undefined_handler_address = (u_int)undefinedinstruction_bounce; undefined_init(); proc_linkup(&proc0, &ksegrp0, &thread0); proc0.p_uarea = (struct user *) proc0_uarea.pv_va; thread0.td_kstack = kernelstack.pv_va; thread0.td_pcb = (struct pcb *) (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; thread0.td_pcb->pcb_flags = 0; thread0.td_frame = &proc0_tf; pcpup->pc_curpcb = thread0.td_pcb; /* Enable MMU, I-cache, D-cache, write buffer. */ arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); pmap_curmaxkvaddr = afterkern; pmap_curmaxkvaddr &= 0xfff00000; pmap_curmaxkvaddr += 0x00100000; pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt); msgbufp = (void*)msgbufpv.pv_va; msgbufinit(msgbufp, MSGBUF_SIZE); mutex_init(); phys_avail[0] = SDRAM_START; phys_avail[1] = round_page(freemempos); phys_avail[2] = round_page(virtual_avail - KERNBASE + SDRAM_START); phys_avail[3] = trunc_page(0xa0000000 + memsize - 1); phys_avail[4] = 0; phys_avail[5] = 0; /* Do basic tuning, hz etc */ init_param1(); init_param2(physmem); avail_end = 0xa0000000 + memsize - 1; kdb_init(); return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP)); }