Index: head/sys/pc98/cbus/clock.c =================================================================== --- head/sys/pc98/cbus/clock.c (revision 130173) +++ head/sys/pc98/cbus/clock.c (revision 130174) @@ -1,1018 +1,1019 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz and Don Ahn. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 * $FreeBSD$ */ /* * Routines to handle clock hardware. */ /* * inittodr, settodr and support routines written * by Christoph Robitschko * * reintroduced and updated by Chris Stenton 8/10/94 */ /* * modified for PC98 by Kakefuda */ #include "opt_clock.h" #include "opt_isa.h" #include "opt_mca.h" #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(SMP) #include #endif #include #include #include #include #ifdef DEV_ISA #include #endif #include /* * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we * can use a simple formula for leap years. */ #define LEAPYEAR(y) (((u_int)(y) % 4 == 0) ? 1 : 0) #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) #ifndef BURN_BRIDGES /* * Time in timer cycles that it takes for microtime() to disable interrupts * and latch the count. microtime() currently uses "cli; outb ..." so it * normally takes less than 2 timer cycles. Add a few for cache misses. * Add a few more to allow for latency in bogus calls to microtime() with * interrupts already disabled. */ #define TIMER0_LATCH_COUNT 20 /* * Maximum frequency that we are willing to allow for timer0. Must be * low enough to guarantee that the timer interrupt handler returns * before the next timer interrupt. */ #define TIMER0_MAX_FREQ 20000 #endif int adjkerntz; /* local offset from GMT in seconds */ int clkintr_pending; int disable_rtc_set; /* disable resettodr() if != 0 */ int pscnt = 1; int psdiv = 1; int statclock_disable; #ifndef TIMER_FREQ #define TIMER_FREQ 2457600 #endif u_int timer_freq = TIMER_FREQ; int timer0_max_count; int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ struct mtx clock_lock; static int beeping = 0; static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; static u_int hardclock_max_count; static u_int32_t i8254_lastcount; static u_int32_t i8254_offset; static int i8254_ticked; static struct intsrc *i8254_intsrc; #ifndef BURN_BRIDGES /* * XXX new_function and timer_func should not handle clockframes, but * timer_func currently needs to hold hardclock to handle the * timer0_state == 0 case. We should use inthand_add()/inthand_remove() * to switch between clkintr() and a slightly different timerintr(). */ static void (*new_function)(struct clockframe *frame); static u_int new_rate; static u_int timer0_prescaler_count; static u_char timer0_state; #endif /* Values for timerX_state: */ #define RELEASED 0 #define RELEASE_PENDING 1 #define ACQUIRED 2 #define ACQUIRE_PENDING 3 static u_char timer1_state; static u_char timer2_state; static void (*timer_func)(struct clockframe *frame) = hardclock; static void rtc_serialcombit(int); static void rtc_serialcom(int); static int rtc_inb(void); static void rtc_outb(int); static unsigned i8254_get_timecount(struct timecounter *tc); static void set_timer_freq(u_int freq, int intr_freq); static struct timecounter i8254_timecounter = { i8254_get_timecount, /* get_timecount */ 0, /* no poll_pps */ ~0u, /* counter_mask */ 0, /* frequency */ "i8254", /* name */ 0 /* quality */ }; static void clkintr(struct clockframe *frame) { if (timecounter->tc_get_timecount == i8254_get_timecount) { mtx_lock_spin(&clock_lock); if (i8254_ticked) i8254_ticked = 0; else { i8254_offset += timer0_max_count; i8254_lastcount = 0; } clkintr_pending = 0; mtx_unlock_spin(&clock_lock); } timer_func(frame); #ifdef SMP if (timer_func == hardclock) forward_hardclock(); #endif #ifndef BURN_BRIDGES switch (timer0_state) { case RELEASED: break; case ACQUIRED: if ((timer0_prescaler_count += timer0_max_count) >= hardclock_max_count) { timer0_prescaler_count -= hardclock_max_count; hardclock(frame); #ifdef SMP forward_hardclock(); #endif } break; case ACQUIRE_PENDING: mtx_lock_spin(&clock_lock); i8254_offset = i8254_get_timecount(NULL); i8254_lastcount = 0; timer0_max_count = TIMER_DIV(new_rate); outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); timer_func = new_function; timer0_state = ACQUIRED; break; case RELEASE_PENDING: if ((timer0_prescaler_count += timer0_max_count) >= hardclock_max_count) { mtx_lock_spin(&clock_lock); i8254_offset = i8254_get_timecount(NULL); i8254_lastcount = 0; timer0_max_count = hardclock_max_count; outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); timer0_prescaler_count = 0; timer_func = hardclock; timer0_state = RELEASED; hardclock(frame); #ifdef SMP forward_hardclock(); #endif } break; } #endif } #ifndef BURN_BRIDGES /* * The acquire and release functions must be called at ipl >= splclock(). */ int acquire_timer0(int rate, void (*function)(struct clockframe *frame)) { static int old_rate; if (rate <= 0 || rate > TIMER0_MAX_FREQ) return (-1); switch (timer0_state) { case RELEASED: timer0_state = ACQUIRE_PENDING; break; case RELEASE_PENDING: if (rate != old_rate) return (-1); /* * The timer has been released recently, but is being * re-acquired before the release completed. In this * case, we simply reclaim it as if it had not been * released at all. */ timer0_state = ACQUIRED; break; default: return (-1); /* busy */ } new_function = function; old_rate = new_rate = rate; return (0); } #endif int acquire_timer1(int mode) { if (timer1_state != RELEASED) return (-1); timer1_state = ACQUIRED; /* * This access to the timer registers is as atomic as possible * because it is a single instruction. We could do better if we * knew the rate. Use of splclock() limits glitches to 10-100us, * and this is probably good enough for timer2, so we aren't as * careful with it as with timer0. */ outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); return (0); } int acquire_timer2(int mode) { if (timer2_state != RELEASED) return (-1); timer2_state = ACQUIRED; /* * This access to the timer registers is as atomic as possible * because it is a single instruction. We could do better if we * knew the rate. Use of splclock() limits glitches to 10-100us, * and this is probably good enough for timer2, so we aren't as * careful with it as with timer0. */ outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); return (0); } #ifndef BURN_BRIDGES int release_timer0() { switch (timer0_state) { case ACQUIRED: timer0_state = RELEASE_PENDING; break; case ACQUIRE_PENDING: /* Nothing happened yet, release quickly. */ timer0_state = RELEASED; break; default: return (-1); } return (0); } #endif int release_timer1() { if (timer1_state != ACQUIRED) return (-1); timer1_state = RELEASED; outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); return (0); } int release_timer2() { if (timer2_state != ACQUIRED) return (-1); timer2_state = RELEASED; outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); return (0); } static int getit(void) { int high, low; mtx_lock_spin(&clock_lock); /* Select timer0 and latch counter value. */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); low = inb(TIMER_CNTR0); high = inb(TIMER_CNTR0); mtx_unlock_spin(&clock_lock); return ((high << 8) | low); } /* * Wait "n" microseconds. * Relies on timer 1 counting down from (timer_freq / hz) * Note: timer had better have been programmed before this is first used! */ void DELAY(int n) { int delta, prev_tick, tick, ticks_left; #ifdef DELAYDEBUG int getit_calls = 1; int n1; static int state = 0; if (state == 0) { state = 1; for (n1 = 1; n1 <= 10000000; n1 *= 10) DELAY(n1); state = 2; } if (state == 1) printf("DELAY(%d)...", n); #endif /* * Guard against the timer being uninitialized if we are called * early for console i/o. */ if (timer0_max_count == 0) set_timer_freq(timer_freq, hz); /* * Read the counter first, so that the rest of the setup overhead is * counted. Guess the initial overhead is 20 usec (on most systems it * takes about 1.5 usec for each of the i/o's in getit(). The loop * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The * multiplications and divisions to scale the count take a while). * * However, if ddb is active then use a fake counter since reading * the i8254 counter involves acquiring a lock. ddb must not go * locking for many reasons, but it calls here for at least atkbd * input. */ #ifdef DDB if (db_active) prev_tick = 0; else #endif prev_tick = getit(); n -= 0; /* XXX actually guess no initial overhead */ /* * Calculate (n * (timer_freq / 1e6)) without using floating point * and without any avoidable overflows. */ if (n <= 0) ticks_left = 0; else if (n < 256) /* * Use fixed point to avoid a slow division by 1000000. * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. * 2^15 is the first power of 2 that gives exact results * for n between 0 and 256. */ ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; else /* * Don't bother using fixed point, although gcc-2.7.2 * generates particularly poor code for the long long * division, since even the slow way will complete long * before the delay is up (unless we're interrupted). */ ticks_left = ((u_int)n * (long long)timer_freq + 999999) / 1000000; while (ticks_left > 0) { #ifdef DDB if (db_active) { outb(0x5f, 0); tick = prev_tick + 1; } else #endif tick = getit(); #ifdef DELAYDEBUG ++getit_calls; #endif delta = prev_tick - tick; prev_tick = tick; if (delta < 0) { delta += timer0_max_count; /* * Guard against timer0_max_count being wrong. * This shouldn't happen in normal operation, * but it may happen if set_timer_freq() is * traced. */ if (delta < 0) delta = 0; } ticks_left -= delta; } #ifdef DELAYDEBUG if (state == 1) printf(" %d calls to getit() at %d usec each\n", getit_calls, (n + 5) / getit_calls); #endif } static void sysbeepstop(void *chan) { outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ release_timer1(); beeping = 0; } int sysbeep(int pitch, int period) { int x = splclock(); if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) if (!beeping) { /* Something else owns it. */ splx(x); return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ } disable_intr(); outb(0x3fdb, pitch); outb(0x3fdb, (pitch>>8)); enable_intr(); if (!beeping) { /* enable counter1 output to speaker */ outb(IO_PPI, (inb(IO_PPI) & 0xf7)); beeping = period; timeout(sysbeepstop, (void *)NULL, period); } splx(x); return (0); } unsigned int delaycount; #define FIRST_GUESS 0x2000 static void findcpuspeed(void) { int i; int remainder; /* Put counter in count down mode */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); outb(TIMER_CNTR0, 0xff); outb(TIMER_CNTR0, 0xff); for (i = FIRST_GUESS; i; i--) ; remainder = getit(); delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); } static u_int calibrate_clocks(void) { int timeout; u_int count, prev_count, tot_count; u_short sec, start_sec; if (bootverbose) printf("Calibrating clock(s) ... "); /* Check ARTIC. */ if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) goto fail; timeout = 100000000; /* Read the ARTIC. */ sec = inw(0x5e); /* Wait for the ARTIC to changes. */ start_sec = sec; for (;;) { sec = inw(0x5e); if (sec != start_sec) break; if (--timeout == 0) goto fail; } prev_count = getit(); if (prev_count == 0 || prev_count > timer0_max_count) goto fail; tot_count = 0; start_sec = sec; for (;;) { sec = inw(0x5e); count = getit(); if (count == 0 || count > timer0_max_count) goto fail; if (count > prev_count) tot_count += prev_count - (count - timer0_max_count); else tot_count += prev_count - count; prev_count = count; if ((sec == start_sec + 1200) || /* 1200 = 307.2KHz >> 8 */ (sec < start_sec && (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) break; if (--timeout == 0) goto fail; } if (bootverbose) { printf("i8254 clock: %u Hz\n", tot_count); } return (tot_count); fail: if (bootverbose) printf("failed, using default i8254 clock of %u Hz\n", timer_freq); return (timer_freq); } static void set_timer_freq(u_int freq, int intr_freq) { int new_timer0_max_count; mtx_lock_spin(&clock_lock); timer_freq = freq; new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); if (new_timer0_max_count != timer0_max_count) { timer0_max_count = new_timer0_max_count; outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); } mtx_unlock_spin(&clock_lock); } static void i8254_restore(void) { mtx_lock_spin(&clock_lock); outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); } /* * Restore all the timers non-atomically (XXX: should be atomically). * * This function is called from pmtimer_resume() to restore all the timers. * This should not be necessary, but there are broken laptops that do not * restore all the timers on resume. */ void timer_restore(void) { i8254_restore(); /* restore timer_freq and hz */ } /* * Initialize 8254 timer 0 early so that it can be used in DELAY(). * XXX initialization of other timers is unintentionally left blank. */ void startrtclock() { u_int delta, freq; findcpuspeed(); if (pc98_machine_type & M_8M) timer_freq = 1996800L; /* 1.9968 MHz */ else timer_freq = 2457600L; /* 2.4576 MHz */ set_timer_freq(timer_freq, hz); freq = calibrate_clocks(); #ifdef CLK_CALIBRATION_LOOP if (bootverbose) { printf( "Press a key on the console to abort clock calibration\n"); while (cncheckc() == -1) calibrate_clocks(); } #endif /* * Use the calibrated i8254 frequency if it seems reasonable. * Otherwise use the default, and don't use the calibrated i586 * frequency. */ delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; if (delta < timer_freq / 100) { #ifndef CLK_USE_I8254_CALIBRATION if (bootverbose) printf( "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); freq = timer_freq; #endif timer_freq = freq; } else { if (bootverbose) printf( "%d Hz differs from default of %d Hz by more than 1%%\n", freq, timer_freq); } set_timer_freq(timer_freq, hz); i8254_timecounter.tc_frequency = timer_freq; tc_init(&i8254_timecounter); init_TSC(); } static void rtc_serialcombit(int i) { outb(IO_RTC, ((i&0x01)<<5)|0x07); DELAY(1); outb(IO_RTC, ((i&0x01)<<5)|0x17); DELAY(1); outb(IO_RTC, ((i&0x01)<<5)|0x07); DELAY(1); } static void rtc_serialcom(int i) { rtc_serialcombit(i&0x01); rtc_serialcombit((i&0x02)>>1); rtc_serialcombit((i&0x04)>>2); rtc_serialcombit((i&0x08)>>3); outb(IO_RTC, 0x07); DELAY(1); outb(IO_RTC, 0x0f); DELAY(1); outb(IO_RTC, 0x07); DELAY(1); } static void rtc_outb(int val) { int s; int sa = 0; for (s=0;s<8;s++) { sa = ((val >> s) & 0x01) ? 0x27 : 0x07; outb(IO_RTC, sa); /* set DI & CLK 0 */ DELAY(1); outb(IO_RTC, sa | 0x10); /* CLK 1 */ DELAY(1); } outb(IO_RTC, sa & 0xef); /* CLK 0 */ } static int rtc_inb(void) { int s; int sa = 0; for (s=0;s<8;s++) { sa |= ((inb(0x33) & 0x01) << s); outb(IO_RTC, 0x17); /* CLK 1 */ DELAY(1); outb(IO_RTC, 0x07); /* CLK 0 */ DELAY(2); } return sa; } /* * Initialize the time of day register, based on the time base which is, e.g. * from a filesystem. */ void inittodr(time_t base) { unsigned long sec, days; int year, month; int y, m, s; struct timespec ts; int second, min, hour; if (base) { s = splclock(); ts.tv_sec = base; ts.tv_nsec = 0; tc_setclock(&ts); splx(s); } rtc_serialcom(0x03); /* Time Read */ rtc_serialcom(0x01); /* Register shift command. */ DELAY(20); second = bcd2bin(rtc_inb() & 0xff); /* sec */ min = bcd2bin(rtc_inb() & 0xff); /* min */ hour = bcd2bin(rtc_inb() & 0xff); /* hour */ days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ month = (rtc_inb() >> 4) & 0x0f; /* month */ for (m = 1; m < month; m++) days += daysinmonth[m-1]; year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ /* 2000 year problem */ if (year < 1995) year += 100; if (year < 1970) goto wrong_time; for (y = 1970; y < year; y++) days += DAYSPERYEAR + LEAPYEAR(y); if ((month > 2) && LEAPYEAR(year)) days ++; sec = ((( days * 24 + hour) * 60 + min) * 60 + second); /* sec now contains the number of seconds, since Jan 1 1970, in the local time zone */ s = splhigh(); sec += tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); y = time_second - sec; if (y <= -2 || y >= 2) { /* badly off, adjust it */ ts.tv_sec = sec; ts.tv_nsec = 0; tc_setclock(&ts); } splx(s); return; wrong_time: printf("Invalid time in real time clock.\n"); printf("Check and reset the date immediately!\n"); } /* * Write system time back to RTC */ void resettodr() { unsigned long tm; int y, m, s; int wd; if (disable_rtc_set) return; s = splclock(); tm = time_second; splx(s); rtc_serialcom(0x01); /* Register shift command. */ /* Calculate local time to put in RTC */ tm -= tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ /* We have now the days since 01-01-1970 in tm */ wd = (tm + 4) % 7 + 1; /* Write back Weekday */ for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); tm >= m; y++, m = DAYSPERYEAR + LEAPYEAR(y)) tm -= m; /* Now we have the years in y and the day-of-the-year in tm */ for (m = 0; ; m++) { int ml; ml = daysinmonth[m]; if (m == 1 && LEAPYEAR(y)) ml++; if (tm < ml) break; tm -= ml; } m++; rtc_outb(bin2bcd(tm+1)); /* Write back Day */ rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ rtc_outb(bin2bcd(y%100)); /* Write back Year */ rtc_serialcom(0x02); /* Time set & Counter hold command. */ rtc_serialcom(0x00); /* Register hold command. */ } /* * Start both clocks running. */ void cpu_initclocks() { /* Finish initializing 8254 timer 0. */ intr_add_handler("clk", 0, (driver_intr_t *)clkintr, NULL, INTR_TYPE_CLK | INTR_FAST, NULL); init_TSC_tc(); } void cpu_startprofclock(void) { } void cpu_stopprofclock(void) { } static int sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) { int error; u_int freq; /* * Use `i8254' instead of `timer' in external names because `timer' * is is too generic. Should use it everywhere. */ freq = timer_freq; error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); if (error == 0 && req->newptr != NULL) { #ifndef BURN_BRIDGES if (timer0_state != RELEASED) return (EBUSY); /* too much trouble to handle */ #endif set_timer_freq(freq, hz); i8254_timecounter.tc_frequency = freq; } return (error); } SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", ""); static unsigned i8254_get_timecount(struct timecounter *tc) { u_int count; u_int high, low; u_int eflags; eflags = read_eflags(); mtx_lock_spin(&clock_lock); /* Select timer0 and latch counter value. */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); low = inb(TIMER_CNTR0); high = inb(TIMER_CNTR0); count = timer0_max_count - ((high << 8) | low); if (count < i8254_lastcount || (!i8254_ticked && (clkintr_pending || ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) && i8254_intsrc != NULL && i8254_intsrc->is_pic->pic_source_pending(i8254_intsrc))))) { i8254_ticked = 1; i8254_offset += timer0_max_count; } i8254_lastcount = count; count += i8254_offset; mtx_unlock_spin(&clock_lock); return (count); } #ifdef DEV_ISA /* * Attach to the ISA PnP descriptors for the timer and realtime clock. */ static struct isa_pnp_id attimer_ids[] = { { 0x0001d041 /* PNP0100 */, "AT timer" }, { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, { 0 } }; static int attimer_probe(device_t dev) { int result; if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0) device_quiet(dev); return(result); } static int attimer_attach(device_t dev) { return(0); } static device_method_t attimer_methods[] = { /* Device interface */ DEVMETHOD(device_probe, attimer_probe), DEVMETHOD(device_attach, attimer_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */ DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */ { 0, 0 } }; static driver_t attimer_driver = { "attimer", attimer_methods, 1, /* no softc */ }; static devclass_t attimer_devclass; DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); #endif /* DEV_ISA */ Index: head/sys/pc98/cbus/gdc.c =================================================================== --- head/sys/pc98/cbus/gdc.c (revision 130173) +++ head/sys/pc98/cbus/gdc.c (revision 130174) @@ -1,1499 +1,1500 @@ /* * Copyright (c) 1999 FreeBSD(98) port team. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer as * the first lines of this file unmodified. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #include "opt_gdc.h" #include "opt_fb.h" #include "opt_syscons.h" #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef LINE30 #include #endif #include #include #define TEXT_GDC 0x60 #define GRAPHIC_GDC 0xa0 #define ROW 25 #define COL 80 #define DRIVER_NAME "gdc" /* cdev driver declaration */ #define GDC_UNIT(dev) minor(dev) #define GDC_MKMINOR(unit) (unit) typedef struct gdc_softc { video_adapter_t *adp; struct resource *res_tgdc, *res_ggdc; struct resource *res_egc, *res_pegc, *res_grcg, *res_kcg; struct resource *res_tmem, *res_gmem1, *res_gmem2; #ifdef FB_INSTALL_CDEV genfb_softc_t gensc; #endif } gdc_softc_t; #define GDC_SOFTC(unit) \ ((gdc_softc_t *)devclass_get_softc(gdc_devclass, unit)) static bus_addr_t gdc_iat[] = {0, 2, 4, 6, 8, 10, 12, 14}; static devclass_t gdc_devclass; static int gdc_probe_unit(int unit, gdc_softc_t *sc, int flags); static int gdc_attach_unit(int unit, gdc_softc_t *sc, int flags); static int gdc_alloc_resource(device_t dev); static int gdc_release_resource(device_t dev); #if FB_INSTALL_CDEV static d_open_t gdcopen; static d_close_t gdcclose; static d_read_t gdcread; static d_write_t gdcwrite; static d_ioctl_t gdcioctl; static d_mmap_t gdcmmap; static struct cdevsw gdc_cdevsw = { .d_version = D_VERSION, .d_flags = D_NEEDGIANT, .d_open = gdcopen, .d_close = gdcclose, .d_read = gdcread, .d_write = gdcwrite, .d_ioctl = gdcioctl, .d_mmap = gdcmmap, .d_name = DRIVER_NAME, .d_maj = -1, }; #endif /* FB_INSTALL_CDEV */ static void gdc_identify(driver_t *driver, device_t parent) { BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, DRIVER_NAME, 0); } static int gdcprobe(device_t dev) { int error; /* Check isapnp ids */ if (isa_get_vendorid(dev)) return (ENXIO); device_set_desc(dev, "Generic GDC"); error = gdc_alloc_resource(dev); if (error) return (error); error = gdc_probe_unit(device_get_unit(dev), device_get_softc(dev), device_get_flags(dev)); gdc_release_resource(dev); return (error); } static int gdc_attach(device_t dev) { gdc_softc_t *sc; int error; error = gdc_alloc_resource(dev); if (error) return (error); sc = device_get_softc(dev); error = gdc_attach_unit(device_get_unit(dev), sc, device_get_flags(dev)); if (error) { gdc_release_resource(dev); return error; } #ifdef FB_INSTALL_CDEV /* attach a virtual frame buffer device */ error = fb_attach(GDC_MKMINOR(device_get_unit(dev)), sc->adp, &gdc_cdevsw); if (error) { gdc_release_resource(dev); return error; } #endif /* FB_INSTALL_CDEV */ if (bootverbose) (*vidsw[sc->adp->va_index]->diag)(sc->adp, bootverbose); return 0; } static int gdc_probe_unit(int unit, gdc_softc_t *sc, int flags) { video_switch_t *sw; sw = vid_get_switch(DRIVER_NAME); if (sw == NULL) return ENXIO; return (*sw->probe)(unit, &sc->adp, NULL, flags); } static int gdc_attach_unit(int unit, gdc_softc_t *sc, int flags) { video_switch_t *sw; sw = vid_get_switch(DRIVER_NAME); if (sw == NULL) return ENXIO; return (*sw->init)(unit, sc->adp, flags); } static int gdc_alloc_resource(device_t dev) { int rid; gdc_softc_t *sc; sc = device_get_softc(dev); /* TEXT GDC */ rid = 0; bus_set_resource(dev, SYS_RES_IOPORT, rid, TEXT_GDC, 1); sc->res_tgdc = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_tgdc == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_tgdc, gdc_iat, 8); /* GRAPHIC GDC */ rid = 8; bus_set_resource(dev, SYS_RES_IOPORT, rid, GRAPHIC_GDC, 1); sc->res_ggdc = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_ggdc == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_ggdc, gdc_iat, 8); /* EGC */ rid = 16; bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x4a0, 1); sc->res_egc = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_egc == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_egc, gdc_iat, 8); /* PEGC */ rid = 24; bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x9a0, 1); sc->res_pegc = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_pegc == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_pegc, gdc_iat, 8); /* CRTC/GRCG */ rid = 32; bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x70, 1); sc->res_grcg = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_grcg == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_grcg, gdc_iat, 8); /* KCG */ rid = 40; bus_set_resource(dev, SYS_RES_IOPORT, rid, 0xa1, 1); sc->res_kcg = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_kcg == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_kcg, gdc_iat, 8); /* TEXT Memory */ rid = 0; sc->res_tmem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0xa0000, 0xa4fff, 0x5000, RF_ACTIVE); if (sc->res_tmem == NULL) { gdc_release_resource(dev); return (ENXIO); } /* GRAPHIC Memory */ rid = 1; sc->res_gmem1 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0xa8000, 0xbffff, 0x18000, RF_ACTIVE); if (sc->res_gmem1 == NULL) { gdc_release_resource(dev); return (ENXIO); } rid = 2; sc->res_gmem2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0xe0000, 0xe7fff, 0x8000, RF_ACTIVE); if (sc->res_gmem2 == NULL) { gdc_release_resource(dev); return (ENXIO); } return (0); } static int gdc_release_resource(device_t dev) { gdc_softc_t *sc; sc = device_get_softc(dev); if (sc->res_tgdc) bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->res_tgdc); if (sc->res_ggdc) bus_release_resource(dev, SYS_RES_IOPORT, 8, sc->res_ggdc); if (sc->res_egc) bus_release_resource(dev, SYS_RES_IOPORT, 16, sc->res_egc); if (sc->res_pegc) bus_release_resource(dev, SYS_RES_IOPORT, 24, sc->res_pegc); if (sc->res_grcg) bus_release_resource(dev, SYS_RES_IOPORT, 32, sc->res_grcg); if (sc->res_kcg) bus_release_resource(dev, SYS_RES_IOPORT, 40, sc->res_kcg); if (sc->res_tmem) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res_tmem); if (sc->res_gmem1) bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->res_gmem1); if (sc->res_gmem2) bus_release_resource(dev, SYS_RES_MEMORY, 2, sc->res_gmem2); return (0); } /* cdev driver functions */ #ifdef FB_INSTALL_CDEV static int gdcopen(dev_t dev, int flag, int mode, struct thread *td) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); if (sc == NULL) return ENXIO; if (mode & (O_CREAT | O_APPEND | O_TRUNC)) return ENODEV; return genfbopen(&sc->gensc, sc->adp, flag, mode, td); } static int gdcclose(dev_t dev, int flag, int mode, struct thread *td) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbclose(&sc->gensc, sc->adp, flag, mode, td); } static int gdcread(dev_t dev, struct uio *uio, int flag) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbread(&sc->gensc, sc->adp, uio, flag); } static int gdcwrite(dev_t dev, struct uio *uio, int flag) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbread(&sc->gensc, sc->adp, uio, flag); } static int gdcioctl(dev_t dev, u_long cmd, caddr_t arg, int flag, struct thread *td) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbioctl(&sc->gensc, sc->adp, cmd, arg, flag, td); } static int gdcmmap(dev_t dev, vm_offset_t offset, vm_paddr_t *paddr, int prot) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbmmap(&sc->gensc, sc->adp, offset, paddr, prot); } #endif /* FB_INSTALL_CDEV */ static device_method_t gdc_methods[] = { DEVMETHOD(device_identify, gdc_identify), DEVMETHOD(device_probe, gdcprobe), DEVMETHOD(device_attach, gdc_attach), { 0, 0 } }; static driver_t gdcdriver = { DRIVER_NAME, gdc_methods, sizeof(gdc_softc_t), }; DRIVER_MODULE(gdc, isa, gdcdriver, gdc_devclass, 0, 0); /* LOW-LEVEL */ #include #define TEXT_BUF_BASE 0x000a0000 #define TEXT_BUF_SIZE 0x00008000 #define GRAPHICS_BUF_BASE 0x000a8000 #define GRAPHICS_BUF_SIZE 0x00040000 #define VIDEO_BUF_BASE 0x000a0000 #define VIDEO_BUF_SIZE 0x00048000 #define probe_done(adp) ((adp)->va_flags & V_ADP_PROBED) #define init_done(adp) ((adp)->va_flags & V_ADP_INITIALIZED) #define config_done(adp) ((adp)->va_flags & V_ADP_REGISTERED) /* * NOTE: `va_window' should have a virtual address, but is initialized * with a physical address in the following table, they will be * converted at run-time. */ static video_adapter_t adapter_init_value[] = { { 0, KD_PC98, "gdc", /* va_type, va_name */ 0, 0, /* va_unit, va_minor */ V_ADP_COLOR | V_ADP_MODECHANGE | V_ADP_BORDER, TEXT_GDC, 16, TEXT_GDC, /* va_io*, XXX */ VIDEO_BUF_BASE, VIDEO_BUF_SIZE, /* va_mem* */ TEXT_BUF_BASE, TEXT_BUF_SIZE, TEXT_BUF_SIZE, 0, /* va_window* */ 0, 0, /* va_buffer, va_buffer_size */ 0, M_PC98_80x25, 0, /* va_*mode* */ }, }; static video_adapter_t biosadapter[1]; /* video driver declarations */ static int gdc_configure(int flags); static int gdc_err(video_adapter_t *adp, ...); static vi_probe_t gdc_probe; static vi_init_t gdc_init; static vi_get_info_t gdc_get_info; static vi_query_mode_t gdc_query_mode; static vi_set_mode_t gdc_set_mode; static vi_set_border_t gdc_set_border; static vi_save_state_t gdc_save_state; static vi_load_state_t gdc_load_state; static vi_read_hw_cursor_t gdc_read_hw_cursor; static vi_set_hw_cursor_t gdc_set_hw_cursor; static vi_set_hw_cursor_shape_t gdc_set_hw_cursor_shape; static vi_blank_display_t gdc_blank_display; static vi_mmap_t gdc_mmap_buf; static vi_ioctl_t gdc_dev_ioctl; static vi_clear_t gdc_clear; static vi_fill_rect_t gdc_fill_rect; static vi_bitblt_t gdc_bitblt; static vi_diag_t gdc_diag; static vi_save_palette_t gdc_save_palette; static vi_load_palette_t gdc_load_palette; static vi_set_win_org_t gdc_set_origin; static video_switch_t gdcvidsw = { gdc_probe, gdc_init, gdc_get_info, gdc_query_mode, gdc_set_mode, (vi_save_font_t *)gdc_err, (vi_load_font_t *)gdc_err, (vi_show_font_t *)gdc_err, gdc_save_palette, gdc_load_palette, gdc_set_border, gdc_save_state, gdc_load_state, gdc_set_origin, gdc_read_hw_cursor, gdc_set_hw_cursor, gdc_set_hw_cursor_shape, gdc_blank_display, gdc_mmap_buf, gdc_dev_ioctl, gdc_clear, gdc_fill_rect, gdc_bitblt, (int (*)(void))gdc_err, (int (*)(void))gdc_err, gdc_diag, }; VIDEO_DRIVER(gdc, gdcvidsw, gdc_configure); /* GDC BIOS standard video modes */ #define EOT (-1) #define NA (-2) static video_info_t bios_vmode[] = { { M_PC98_80x25, V_INFO_COLOR, 80, 25, 8, 16, 4, 1, TEXT_BUF_BASE, TEXT_BUF_SIZE, TEXT_BUF_SIZE, 0, 0, V_INFO_MM_TEXT }, #ifdef LINE30 { M_PC98_80x30, V_INFO_COLOR, 80, 30, 8, 16, 4, 1, TEXT_BUF_BASE, TEXT_BUF_SIZE, TEXT_BUF_SIZE, 0, 0, V_INFO_MM_TEXT }, #endif #ifndef GDC_NOGRAPHICS { M_PC98_EGC640x400, V_INFO_COLOR | V_INFO_GRAPHICS, 640, 400, 8, 16, 4, 4, GRAPHICS_BUF_BASE, GRAPHICS_BUF_SIZE, GRAPHICS_BUF_SIZE, 0, 0, V_INFO_MM_PLANAR }, { M_PC98_PEGC640x400, V_INFO_COLOR | V_INFO_GRAPHICS | V_INFO_VESA, 640, 400, 8, 16, 8, 1, GRAPHICS_BUF_BASE, 0x00008000, 0x00008000, 0, 0, V_INFO_MM_PACKED, 1 }, #ifdef LINE30 { M_PC98_PEGC640x480, V_INFO_COLOR | V_INFO_GRAPHICS | V_INFO_VESA, 640, 480, 8, 16, 8, 1, GRAPHICS_BUF_BASE, 0x00008000, 0x00008000, 0, 0, V_INFO_MM_PACKED, 1 }, #endif #endif { EOT }, }; static int gdc_init_done = FALSE; /* local functions */ static int map_gen_mode_num(int type, int color, int mode); static int probe_adapters(void); #define prologue(adp, flag, err) \ if (!gdc_init_done || !((adp)->va_flags & (flag))) \ return (err) /* a backdoor for the console driver */ static int gdc_configure(int flags) { probe_adapters(); biosadapter[0].va_flags |= V_ADP_INITIALIZED; if (!config_done(&biosadapter[0])) { if (vid_register(&biosadapter[0]) < 0) return 1; biosadapter[0].va_flags |= V_ADP_REGISTERED; } return 1; } /* local subroutines */ /* map a generic video mode to a known mode number */ static int map_gen_mode_num(int type, int color, int mode) { static struct { int from; int to; } mode_map[] = { { M_TEXT_80x25, M_PC98_80x25, }, #ifdef LINE30 { M_TEXT_80x30, M_PC98_80x30, }, #endif }; int i; for (i = 0; i < sizeof(mode_map)/sizeof(mode_map[0]); ++i) { if (mode_map[i].from == mode) return mode_map[i].to; } return mode; } static int verify_adapter(video_adapter_t *adp) { #ifndef GDC_NOGRAPHICS int i; if (PC98_SYSTEM_PARAMETER(0x45c) & 0x40) { /* PEGC exists */ adp->va_flags |= V_ADP_VESA; /* XXX */ } else { for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) { if (bios_vmode[i].vi_flags & V_INFO_VESA) bios_vmode[i].vi_mode = NA; } } #endif return 0; } /* probe video adapters and return the number of detected adapters */ static int probe_adapters(void) { video_info_t info; /* do this test only once */ if (gdc_init_done) return 1; gdc_init_done = TRUE; biosadapter[0] = adapter_init_value[0]; biosadapter[0].va_flags |= V_ADP_PROBED; biosadapter[0].va_mode = biosadapter[0].va_initial_mode = biosadapter[0].va_initial_bios_mode; if ((PC98_SYSTEM_PARAMETER(0x597) & 0x80) || (PC98_SYSTEM_PARAMETER(0x458) & 0x80)) { gdc_FH = (inb(0x9a8) & 1) ? _31KHZ : _24KHZ; } else { gdc_FH = _24KHZ; } gdc_get_info(&biosadapter[0], biosadapter[0].va_initial_mode, &info); initialize_gdc(T25_G400, info.vi_flags & V_INFO_GRAPHICS); biosadapter[0].va_window = BIOS_PADDRTOVADDR(info.vi_window); biosadapter[0].va_window_size = info.vi_window_size; biosadapter[0].va_window_gran = info.vi_window_gran; biosadapter[0].va_buffer = 0; biosadapter[0].va_buffer_size = 0; if (info.vi_flags & V_INFO_GRAPHICS) { switch (info.vi_depth/info.vi_planes) { case 1: biosadapter[0].va_line_width = info.vi_width/8; break; case 2: biosadapter[0].va_line_width = info.vi_width/4; break; case 4: biosadapter[0].va_line_width = info.vi_width/2; break; case 8: default: /* shouldn't happen */ biosadapter[0].va_line_width = info.vi_width; break; } } else { biosadapter[0].va_line_width = info.vi_width; } bcopy(&info, &biosadapter[0].va_info, sizeof(info)); verify_adapter(&biosadapter[0]); return 1; } static void master_gdc_cmd(unsigned int cmd) { while ( (inb(TEXT_GDC) & 2) != 0); outb(TEXT_GDC+2, cmd); } static void master_gdc_prm(unsigned int pmtr) { while ( (inb(TEXT_GDC) & 2) != 0); outb(TEXT_GDC, pmtr); } static void master_gdc_word_prm(unsigned int wpmtr) { master_gdc_prm(wpmtr & 0x00ff); master_gdc_prm((wpmtr >> 8) & 0x00ff); } #ifdef LINE30 static void master_gdc_fifo_empty(void) { while ( (inb(TEXT_GDC) & 4) == 0); } #endif static void master_gdc_wait_vsync(void) { while ( (inb(TEXT_GDC) & 0x20) != 0); while ( (inb(TEXT_GDC) & 0x20) == 0); } static void gdc_cmd(unsigned int cmd) { while ( (inb(GRAPHIC_GDC) & 2) != 0); outb( GRAPHIC_GDC+2, cmd); } #ifdef LINE30 static void gdc_prm(unsigned int pmtr) { while ( (inb(GRAPHIC_GDC) & 2) != 0); outb( GRAPHIC_GDC, pmtr); } static void gdc_word_prm(unsigned int wpmtr) { gdc_prm(wpmtr & 0x00ff); gdc_prm((wpmtr >> 8) & 0x00ff); } static void gdc_fifo_empty(void) { while ( (inb(GRAPHIC_GDC) & 0x04) == 0); } #endif static void gdc_wait_vsync(void) { while ( (inb(GRAPHIC_GDC) & 0x20) != 0); while ( (inb(GRAPHIC_GDC) & 0x20) == 0); } #ifdef LINE30 static int check_gdc_clock(void) { if ((inb(IO_SYSPORT) & 0x80) == 0){ return _5MHZ; } else { return _2_5MHZ; } } #endif static void initialize_gdc(unsigned int mode, int isGraph) { #ifdef LINE30 /* start 30line initialize */ int m_mode, s_mode, gdc_clock, hsync_clock; gdc_clock = check_gdc_clock(); m_mode = (mode == T25_G400) ? _25L : _30L; s_mode = 2*mode+gdc_clock; gdc_INFO = m_mode; master_gdc_wait_vsync(); if ((PC98_SYSTEM_PARAMETER(0x597) & 0x80) || (PC98_SYSTEM_PARAMETER(0x458) & 0x80)) { if (PC98_SYSTEM_PARAMETER(0x481) & 0x08) { hsync_clock = (m_mode == _25L) ? gdc_FH : _31KHZ; outb(0x9a8, (hsync_clock == _31KHZ) ? 1 : 0); } else { hsync_clock = gdc_FH; } } else { hsync_clock = _24KHZ; } if ((gdc_clock == _2_5MHZ) && (slave_param[hsync_clock][s_mode][GDC_LF] > 400)) { outb(0x6a, 0x83); outb(0x6a, 0x85); gdc_clock = _5MHZ; s_mode = 2*mode+gdc_clock; } master_gdc_cmd(_GDC_RESET); master_gdc_cmd(_GDC_MASTER); gdc_cmd(_GDC_RESET); gdc_cmd(_GDC_SLAVE); /* GDC Master */ master_gdc_cmd(_GDC_SYNC); master_gdc_prm(0x00); /* flush less */ /* text & graph */ master_gdc_prm(master_param[hsync_clock][m_mode][GDC_CR]); master_gdc_word_prm(((master_param[hsync_clock][m_mode][GDC_HFP] << 10) + (master_param[hsync_clock][m_mode][GDC_VS] << 5) + master_param[hsync_clock][m_mode][GDC_HS])); master_gdc_prm(master_param[hsync_clock][m_mode][GDC_HBP]); master_gdc_prm(master_param[hsync_clock][m_mode][GDC_VFP]); master_gdc_word_prm(((master_param[hsync_clock][m_mode][GDC_VBP] << 10) + (master_param[hsync_clock][m_mode][GDC_LF]))); master_gdc_fifo_empty(); master_gdc_cmd(_GDC_PITCH); master_gdc_prm(MasterPCH); master_gdc_fifo_empty(); /* GDC slave */ gdc_cmd(_GDC_SYNC); gdc_prm(0x06); gdc_prm(slave_param[hsync_clock][s_mode][GDC_CR]); gdc_word_prm((slave_param[hsync_clock][s_mode][GDC_HFP] << 10) + (slave_param[hsync_clock][s_mode][GDC_VS] << 5) + (slave_param[hsync_clock][s_mode][GDC_HS])); gdc_prm(slave_param[hsync_clock][s_mode][GDC_HBP]); gdc_prm(slave_param[hsync_clock][s_mode][GDC_VFP]); gdc_word_prm((slave_param[hsync_clock][s_mode][GDC_VBP] << 10) + (slave_param[hsync_clock][s_mode][GDC_LF])); gdc_fifo_empty(); gdc_cmd(_GDC_PITCH); gdc_prm(SlavePCH[gdc_clock]); gdc_fifo_empty(); /* set Master GDC scroll param */ master_gdc_wait_vsync(); master_gdc_wait_vsync(); master_gdc_wait_vsync(); master_gdc_cmd(_GDC_SCROLL); master_gdc_word_prm(0); master_gdc_word_prm((master_param[hsync_clock][m_mode][GDC_LF] << 4) | 0x0000); master_gdc_fifo_empty(); /* set Slave GDC scroll param */ gdc_wait_vsync(); gdc_cmd(_GDC_SCROLL); gdc_word_prm(0); if (gdc_clock == _5MHZ) { gdc_word_prm((SlaveScrlLF[mode] << 4) | 0x4000); } else { gdc_word_prm(SlaveScrlLF[mode] << 4); } gdc_fifo_empty(); gdc_word_prm(0); if (gdc_clock == _5MHZ) { gdc_word_prm((SlaveScrlLF[mode] << 4) | 0x4000); } else { gdc_word_prm(SlaveScrlLF[mode] << 4); } gdc_fifo_empty(); /* sync start */ gdc_cmd(isGraph ? _GDC_START : _GDC_STOP); gdc_wait_vsync(); gdc_wait_vsync(); gdc_wait_vsync(); master_gdc_cmd(isGraph ? _GDC_STOP : _GDC_START); #else master_gdc_wait_vsync(); master_gdc_cmd(isGraph ? _GDC_STOP : _GDC_START); /* text */ gdc_wait_vsync(); gdc_cmd(isGraph ? _GDC_START : _GDC_STOP); /* graphics */ #endif } #ifndef GDC_NOGRAPHICS static u_char b_palette[] = { /* R G B */ 0x00, 0x00, 0x00, /* 0 */ 0x00, 0x00, 0x7f, /* 1 */ 0x7f, 0x00, 0x00, /* 2 */ 0x7f, 0x00, 0x7f, /* 3 */ 0x00, 0x7f, 0x00, /* 4 */ 0x00, 0x7f, 0x7f, /* 5 */ 0x7f, 0x7f, 0x00, /* 6 */ 0x7f, 0x7f, 0x7f, /* 7 */ 0x40, 0x40, 0x40, /* 8 */ 0x00, 0x00, 0xff, /* 9 */ 0xff, 0x00, 0x00, /* 10 */ 0xff, 0x00, 0xff, /* 11 */ 0x00, 0xff, 0x00, /* 12 */ 0x00, 0xff, 0xff, /* 13 */ 0xff, 0xff, 0x00, /* 14 */ 0xff, 0xff, 0xff, /* 15 */ }; #endif static int gdc_load_palette(video_adapter_t *adp, u_char *palette) { #ifndef GDC_NOGRAPHICS int i; if (adp->va_info.vi_flags & V_INFO_VESA) { gdc_wait_vsync(); for (i = 0; i < 256; ++i) { outb(0xa8, i); outb(0xac, *palette++); /* R */ outb(0xaa, *palette++); /* G */ outb(0xae, *palette++); /* B */ } } else { /* * XXX - Even though PC-98 text color is independent of palette, * we should set palette in text mode. * Because the background color of text mode is palette 0's one. */ outb(0x6a, 1); /* 16 colors mode */ bcopy(palette, b_palette, sizeof(b_palette)); gdc_wait_vsync(); for (i = 0; i < 16; ++i) { outb(0xa8, i); outb(0xac, *palette++ >> 4); /* R */ outb(0xaa, *palette++ >> 4); /* G */ outb(0xae, *palette++ >> 4); /* B */ } } #endif return 0; } static int gdc_save_palette(video_adapter_t *adp, u_char *palette) { #ifndef GDC_NOGRAPHICS int i; if (adp->va_info.vi_flags & V_INFO_VESA) { for (i = 0; i < 256; ++i) { outb(0xa8, i); *palette++ = inb(0xac); /* R */ *palette++ = inb(0xaa); /* G */ *palette++ = inb(0xae); /* B */ } } else { bcopy(b_palette, palette, sizeof(b_palette)); } #endif return 0; } static int gdc_set_origin(video_adapter_t *adp, off_t offset) { #ifndef GDC_NOGRAPHICS if (adp->va_info.vi_flags & V_INFO_VESA) { writew(BIOS_PADDRTOVADDR(0x000e0004), offset >> 15); } #endif return 0; } /* entry points */ static int gdc_err(video_adapter_t *adp, ...) { return ENODEV; } static int gdc_probe(int unit, video_adapter_t **adpp, void *arg, int flags) { probe_adapters(); if (unit >= 1) return ENXIO; *adpp = &biosadapter[unit]; return 0; } static int gdc_init(int unit, video_adapter_t *adp, int flags) { if ((unit >= 1) || (adp == NULL) || !probe_done(adp)) return ENXIO; if (!init_done(adp)) { /* nothing to do really... */ adp->va_flags |= V_ADP_INITIALIZED; } if (!config_done(adp)) { if (vid_register(adp) < 0) return ENXIO; adp->va_flags |= V_ADP_REGISTERED; } return 0; } /* * get_info(): * Return the video_info structure of the requested video mode. */ static int gdc_get_info(video_adapter_t *adp, int mode, video_info_t *info) { int i; if (!gdc_init_done) return ENXIO; mode = map_gen_mode_num(adp->va_type, adp->va_flags & V_ADP_COLOR, mode); for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) { if (bios_vmode[i].vi_mode == NA) continue; if (mode == bios_vmode[i].vi_mode) { *info = bios_vmode[i]; info->vi_buffer_size = info->vi_window_size*info->vi_planes; return 0; } } return EINVAL; } /* * query_mode(): * Find a video mode matching the requested parameters. * Fields filled with 0 are considered "don't care" fields and * match any modes. */ static int gdc_query_mode(video_adapter_t *adp, video_info_t *info) { int i; if (!gdc_init_done) return ENXIO; for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) { if (bios_vmode[i].vi_mode == NA) continue; if ((info->vi_width != 0) && (info->vi_width != bios_vmode[i].vi_width)) continue; if ((info->vi_height != 0) && (info->vi_height != bios_vmode[i].vi_height)) continue; if ((info->vi_cwidth != 0) && (info->vi_cwidth != bios_vmode[i].vi_cwidth)) continue; if ((info->vi_cheight != 0) && (info->vi_cheight != bios_vmode[i].vi_cheight)) continue; if ((info->vi_depth != 0) && (info->vi_depth != bios_vmode[i].vi_depth)) continue; if ((info->vi_planes != 0) && (info->vi_planes != bios_vmode[i].vi_planes)) continue; /* XXX: should check pixel format, memory model */ if ((info->vi_flags != 0) && (info->vi_flags != bios_vmode[i].vi_flags)) continue; /* verify if this mode is supported on this adapter */ if (gdc_get_info(adp, bios_vmode[i].vi_mode, info)) continue; return 0; } return ENODEV; } /* * set_mode(): * Change the video mode. */ static int gdc_set_mode(video_adapter_t *adp, int mode) { video_info_t info; prologue(adp, V_ADP_MODECHANGE, ENODEV); mode = map_gen_mode_num(adp->va_type, adp->va_flags & V_ADP_COLOR, mode); if (gdc_get_info(adp, mode, &info)) return EINVAL; switch (info.vi_mode) { #ifndef GDC_NOGRAPHICS case M_PC98_PEGC640x480: /* PEGC 640x480 */ initialize_gdc(T30_G480, info.vi_flags & V_INFO_GRAPHICS); break; case M_PC98_PEGC640x400: /* PEGC 640x400 */ case M_PC98_EGC640x400: /* EGC GRAPHICS */ #endif case M_PC98_80x25: /* VGA TEXT */ initialize_gdc(T25_G400, info.vi_flags & V_INFO_GRAPHICS); break; case M_PC98_80x30: /* VGA TEXT */ initialize_gdc(T30_G400, info.vi_flags & V_INFO_GRAPHICS); break; default: break; } #ifndef GDC_NOGRAPHICS if (info.vi_flags & V_INFO_VESA) { outb(0x6a, 0x07); /* enable mode F/F change */ outb(0x6a, 0x21); /* enhanced graphics */ if (info.vi_height > 400) outb(0x6a, 0x69); /* 800 lines */ writeb(BIOS_PADDRTOVADDR(0x000e0100), 0); /* packed pixel */ } else { if (adp->va_flags & V_ADP_VESA) { outb(0x6a, 0x07); /* enable mode F/F change */ outb(0x6a, 0x20); /* normal graphics */ outb(0x6a, 0x68); /* 400 lines */ } outb(0x6a, 1); /* 16 colors */ } #endif adp->va_mode = mode; adp->va_flags &= ~V_ADP_COLOR; adp->va_flags |= (info.vi_flags & V_INFO_COLOR) ? V_ADP_COLOR : 0; #if 0 adp->va_crtc_addr = (adp->va_flags & V_ADP_COLOR) ? COLOR_CRTC : MONO_CRTC; #endif adp->va_window = BIOS_PADDRTOVADDR(info.vi_window); adp->va_window_size = info.vi_window_size; adp->va_window_gran = info.vi_window_gran; if (info.vi_buffer_size == 0) { adp->va_buffer = 0; adp->va_buffer_size = 0; } else { adp->va_buffer = BIOS_PADDRTOVADDR(info.vi_buffer); adp->va_buffer_size = info.vi_buffer_size; } if (info.vi_flags & V_INFO_GRAPHICS) { switch (info.vi_depth/info.vi_planes) { case 1: adp->va_line_width = info.vi_width/8; break; case 2: adp->va_line_width = info.vi_width/4; break; case 4: adp->va_line_width = info.vi_width/2; break; case 8: default: /* shouldn't happen */ adp->va_line_width = info.vi_width; break; } } else { adp->va_line_width = info.vi_width; } bcopy(&info, &adp->va_info, sizeof(info)); /* move hardware cursor out of the way */ (*vidsw[adp->va_index]->set_hw_cursor)(adp, -1, -1); return 0; } /* * set_border(): * Change the border color. */ static int gdc_set_border(video_adapter_t *adp, int color) { outb(0x6c, color << 4); return 0; } /* * save_state(): * Read video card register values. */ static int gdc_save_state(video_adapter_t *adp, void *p, size_t size) { return ENODEV; } /* * load_state(): * Set video card registers at once. */ static int gdc_load_state(video_adapter_t *adp, void *p) { return ENODEV; } /* * read_hw_cursor(): * Read the position of the hardware text cursor. */ static int gdc_read_hw_cursor(video_adapter_t *adp, int *col, int *row) { u_int16_t off; int s; if (!gdc_init_done) return ENXIO; if (adp->va_info.vi_flags & V_INFO_GRAPHICS) return ENODEV; s = spltty(); master_gdc_cmd(0xe0); /* _GDC_CSRR */ while((inb(TEXT_GDC + 0) & 0x1) == 0) {} /* GDC wait */ off = inb(TEXT_GDC + 2); /* EADl */ off |= (inb(TEXT_GDC + 2) << 8); /* EADh */ inb(TEXT_GDC + 2); /* dummy */ inb(TEXT_GDC + 2); /* dummy */ inb(TEXT_GDC + 2); /* dummy */ splx(s); if (off >= ROW*COL) off = 0; *row = off / adp->va_info.vi_width; *col = off % adp->va_info.vi_width; return 0; } /* * set_hw_cursor(): * Move the hardware text cursor. If col and row are both -1, * the cursor won't be shown. */ static int gdc_set_hw_cursor(video_adapter_t *adp, int col, int row) { u_int16_t off; int s; if (!gdc_init_done) return ENXIO; if ((col == -1) && (row == -1)) { off = -1; } else { if (adp->va_info.vi_flags & V_INFO_GRAPHICS) return ENODEV; off = row*adp->va_info.vi_width + col; } s = spltty(); master_gdc_cmd(0x49); /* _GDC_CSRW */ master_gdc_word_prm(off); splx(s); return 0; } /* * set_hw_cursor_shape(): * Change the shape of the hardware text cursor. If the height is zero * or negative, the cursor won't be shown. */ static int gdc_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, int celsize, int blink) { int start; int end; int s; if (!gdc_init_done) return ENXIO; start = celsize - (base + height); end = celsize - base - 1; #if 0 /* * muPD7220 GDC has anomaly that if end == celsize - 1 then start * must be 0, otherwise the cursor won't be correctly shown * in the first row in the screen. We shall set end to celsize - 2; * if end == celsize -1 && start > 0. XXX */ if ((end == celsize - 1) && (start > 0) && (start < end)) --end; #endif s = spltty(); master_gdc_cmd(0x4b); /* _GDC_CSRFORM */ master_gdc_prm(((height > 0) ? 0x80 : 0) /* cursor on/off */ | ((celsize - 1) & 0x1f)); /* cel size */ master_gdc_word_prm(((end & 0x1f) << 11) /* end line */ | (12 << 6) /* blink rate */ | (blink ? 0 : 0x20) /* blink on/off */ | (start & 0x1f)); /* start line */ splx(s); return 0; } /* * blank_display() * Put the display in power save/power off mode. */ static int gdc_blank_display(video_adapter_t *adp, int mode) { int s; static int standby = 0; if (!gdc_init_done) return ENXIO; s = splhigh(); switch (mode) { case V_DISPLAY_SUSPEND: case V_DISPLAY_STAND_BY: outb(0x09a2, 0x80 | 0x40); /* V/H-SYNC mask */ if (inb(0x09a2) == (0x80 | 0x40)) standby = 1; /* FALLTHROUGH */ case V_DISPLAY_BLANK: if (epson_machine_id == 0x20) { outb(0x43f, 0x42); outb(0xc17, inb(0xc17) & ~0x08); /* turn off side light */ outb(0xc16, inb(0xc16) & ~0x02); /* turn off back light */ outb(0x43f, 0x40); } else { while (!(inb(TEXT_GDC) & 0x20)) /* V-SYNC wait */ ; outb(TEXT_GDC + 8, 0x0e); /* DISP off */ } break; case V_DISPLAY_ON: if (epson_machine_id == 0x20) { outb(0x43f, 0x42); outb(0xc17, inb(0xc17) | 0x08); outb(0xc16, inb(0xc16) | 0x02); outb(0x43f, 0x40); } else { while (!(inb(TEXT_GDC) & 0x20)) /* V-SYNC wait */ ; outb(TEXT_GDC + 8, 0x0f); /* DISP on */ } if (standby) { outb(0x09a2, 0x00); /* V/H-SYNC unmask */ standby = 0; } break; } splx(s); return 0; } /* * mmap(): * Mmap frame buffer. */ static int gdc_mmap_buf(video_adapter_t *adp, vm_offset_t offset, vm_offset_t *paddr, int prot) { /* FIXME: is this correct? XXX */ if (offset > VIDEO_BUF_SIZE - PAGE_SIZE) return -1; *paddr = adp->va_info.vi_window + offset; return 0; } #ifndef GDC_NOGRAPHICS static void planar_fill(video_adapter_t *adp, int val) { outb(0x7c, 0x80); /* GRCG on & TDW mode */ outb(0x7e, 0); /* tile B */ outb(0x7e, 0); /* tile R */ outb(0x7e, 0); /* tile G */ outb(0x7e, 0); /* tile I */ fillw_io(0, adp->va_window, 0x8000 / 2); /* XXX */ outb(0x7c, 0); /* GRCG off */ } static void packed_fill(video_adapter_t *adp, int val) { int length; int at; /* position in the frame buffer */ int l; at = 0; length = adp->va_line_width*adp->va_info.vi_height; while (length > 0) { l = imin(length, adp->va_window_size); (*vidsw[adp->va_index]->set_win_org)(adp, at); bzero_io(adp->va_window, l); length -= l; at += l; } } static int gdc_clear(video_adapter_t *adp) { switch (adp->va_info.vi_mem_model) { case V_INFO_MM_TEXT: /* do nothing? XXX */ break; case V_INFO_MM_PLANAR: planar_fill(adp, 0); break; case V_INFO_MM_PACKED: packed_fill(adp, 0); break; } return 0; } #else /* GDC_NOGRAPHICS */ static int gdc_clear(video_adapter_t *adp) { return 0; } #endif /* GDC_NOGRAPHICS */ static int gdc_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) { return ENODEV; } static int gdc_bitblt(video_adapter_t *adp,...) { /* FIXME */ return ENODEV; } static int gdc_dev_ioctl(video_adapter_t *adp, u_long cmd, caddr_t arg) { switch (cmd) { case FBIO_GETWINORG: /* get frame buffer window origin */ *(u_int *)arg = 0; return 0; case FBIO_SETWINORG: /* set frame buffer window origin */ case FBIO_SETDISPSTART: /* set display start address */ case FBIO_SETLINEWIDTH: /* set scan line length in pixel */ case FBIO_GETPALETTE: /* get color palette */ case FBIO_SETPALETTE: /* set color palette */ case FBIOGETCMAP: /* get color palette */ case FBIOPUTCMAP: /* set color palette */ return ENODEV; case FBIOGTYPE: /* get frame buffer type info. */ ((struct fbtype *)arg)->fb_type = fb_type(adp->va_type); ((struct fbtype *)arg)->fb_height = adp->va_info.vi_height; ((struct fbtype *)arg)->fb_width = adp->va_info.vi_width; ((struct fbtype *)arg)->fb_depth = adp->va_info.vi_depth; if ((adp->va_info.vi_depth <= 1) || (adp->va_info.vi_depth > 8)) ((struct fbtype *)arg)->fb_cmsize = 0; else ((struct fbtype *)arg)->fb_cmsize = 1 << adp->va_info.vi_depth; ((struct fbtype *)arg)->fb_size = adp->va_buffer_size; return 0; default: return fb_commonioctl(adp, cmd, arg); } } /* * diag(): * Print some information about the video adapter and video modes, * with requested level of details. */ static int gdc_diag(video_adapter_t *adp, int level) { #if FB_DEBUG > 1 int i; #endif if (!gdc_init_done) return ENXIO; fb_dump_adp_info(DRIVER_NAME, adp, level); #if FB_DEBUG > 1 for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) { if (bios_vmode[i].vi_mode == NA) continue; if (get_mode_param(bios_vmode[i].vi_mode) == NULL) continue; fb_dump_mode_info(DRIVER_NAME, adp, &bios_vmode[i], level); } #endif return 0; } Index: head/sys/pc98/cbus/olpt.c =================================================================== --- head/sys/pc98/cbus/olpt.c (revision 130173) +++ head/sys/pc98/cbus/olpt.c (revision 130174) @@ -1,817 +1,818 @@ /* * Copyright (c) 1990 William F. Jolitz, TeleMuse * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This software is a component of "386BSD" developed by * William F. Jolitz, TeleMuse. * 4. Neither the name of the developer nor the name "386BSD" * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ * AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS * SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT. * THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT * NOT MAKE USE OF THIS WORK. * * FOR USERS WHO WISH TO UNDERSTAND THE 386BSD SYSTEM DEVELOPED * BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN * REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES * (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING * JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND * LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE * ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS * OF 386BSD ENTITLED "386BSD FROM THE INSIDE OUT" WILL BE AVAILABLE LATE 1992. * * THIS SOFTWARE IS PROVIDED BY THE DEVELOPER ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE DEVELOPER BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: unknown origin, 386BSD 0.1 * $FreeBSD$ */ /* * Device Driver for AT parallel printer port * Written by William Jolitz 12/18/90 */ /* * Parallel port TCP/IP interfaces added. I looked at the driver from * MACH but this is a complete rewrite, and btw. incompatible, and it * should perform better too. I have never run the MACH driver though. * * This driver sends two bytes (0x08, 0x00) in front of each packet, * to allow us to distinguish another format later. * * Now added a Linux/Crynwr compatibility mode which is enabled using * IF_LINK0 - Tim Wilkinson. * * TODO: * Make HDLC/PPP mode, use IF_LLC1 to enable. * * Connect the two computers using a Laplink parallel cable to use this * feature: * * +----------------------------------------+ * |A-name A-End B-End Descr. Port/Bit | * +----------------------------------------+ * |DATA0 2 15 Data 0/0x01 | * |-ERROR 15 2 1/0x08 | * +----------------------------------------+ * |DATA1 3 13 Data 0/0x02 | * |+SLCT 13 3 1/0x10 | * +----------------------------------------+ * |DATA2 4 12 Data 0/0x04 | * |+PE 12 4 1/0x20 | * +----------------------------------------+ * |DATA3 5 10 Strobe 0/0x08 | * |-ACK 10 5 1/0x40 | * +----------------------------------------+ * |DATA4 6 11 Data 0/0x10 | * |BUSY 11 6 1/~0x80 | * +----------------------------------------+ * |GND 18-25 18-25 GND - | * +----------------------------------------+ * * Expect transfer-rates up to 75 kbyte/sec. * * If GCC could correctly grok * register int port asm("edx") * the code would be cleaner * * Poul-Henning Kamp */ #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #define LPINITRDY 4 /* wait up to 4 seconds for a ready */ #define LPTOUTINITIAL 10 /* initial timeout to wait for ready 1/10 s */ #define LPTOUTMAX 1 /* maximal timeout 1 s */ #define LPPRI (PZERO+8) #define BUFSIZE 1024 #ifndef PC98 /* BIOS printer list - used by BIOS probe*/ #define BIOS_LPT_PORTS 0x408 #define BIOS_PORTS (short *)(KERNBASE+BIOS_LPT_PORTS) #define BIOS_MAX_LPT 4 #endif #ifndef DEBUG #define lprintf(args) #else #define lprintf(args) do { \ if (lptflag) \ printf args; \ } while (0) static int volatile lptflag = 1; #endif #define LPTUNIT(s) ((s)&0x03) #define LPTFLAGS(s) ((s)&0xfc) struct lpt_softc { struct resource *res_port; struct resource *res_irq; void *sc_ih; int sc_port; short sc_state; /* default case: negative prime, negative ack, handshake strobe, prime once */ u_char sc_control; char sc_flags; #define LP_POS_INIT 0x04 /* if we are a postive init signal */ #define LP_POS_ACK 0x08 /* if we are a positive going ack */ #define LP_NO_PRIME 0x10 /* don't prime the printer at all */ #define LP_PRIMEOPEN 0x20 /* prime on every open */ #define LP_AUTOLF 0x40 /* tell printer to do an automatic lf */ #define LP_BYPASS 0x80 /* bypass printer ready checks */ void *sc_inbuf; short sc_xfercnt ; char sc_primed; char *sc_cp ; u_char sc_irq ; /* IRQ status of port */ #define LP_HAS_IRQ 0x01 /* we have an irq available */ #define LP_USE_IRQ 0x02 /* we are using our irq */ #define LP_ENABLE_IRQ 0x04 /* enable IRQ on open */ u_char sc_backoff ; /* time to call lptout() again */ }; /* bits for state */ #define OPEN (1<<0) /* device is open */ #define ASLP (1<<1) /* awaiting draining of printer */ #define ERROR (1<<2) /* error was received from printer */ #define OBUSY (1<<3) /* printer is busy doing output */ #define LPTOUT (1<<4) /* timeout while not selected */ #define TOUT (1<<5) /* timeout while not selected */ #define INIT (1<<6) /* waiting to initialize for open */ #define INTERRUPTED (1<<7) /* write call was interrupted */ /* status masks to interrogate printer status */ #define RDY_MASK (LPS_SEL|LPS_OUT|LPS_NBSY|LPS_NERR) /* ready ? */ #define LP_READY (LPS_SEL|LPS_NBSY|LPS_NERR) /* Printer Ready condition - from lpa.c */ /* Only used in polling code */ #ifdef PC98 #define NOT_READY(x) ((inb(x) & LPS_NBSY) != LPS_NBSY) #else /* IBM-PC */ #define LPS_INVERT (LPS_NBSY | LPS_NACK | LPS_SEL | LPS_NERR) #define LPS_MASK (LPS_NBSY | LPS_NACK | LPS_OUT | LPS_SEL | LPS_NERR) #define NOT_READY(x) ((inb(x)^LPS_INVERT)&LPS_MASK) #endif #define MAX_SLEEP (hz*5) /* Timeout while waiting for device ready */ #define MAX_SPIN 20 /* Max delay for device ready in usecs */ static timeout_t lptout; static int lpt_probe(device_t); static int lpt_attach(device_t); static void lpt_intr(void *); static devclass_t olpt_devclass; static device_method_t olpt_methods[] = { DEVMETHOD(device_probe, lpt_probe), DEVMETHOD(device_attach, lpt_attach), { 0, 0 } }; static driver_t olpt_driver = { "olpt", olpt_methods, sizeof (struct lpt_softc), }; DRIVER_MODULE(olpt, isa, olpt_driver, olpt_devclass, 0, 0); static d_open_t lptopen; static d_close_t lptclose; static d_write_t lptwrite; static d_ioctl_t lptioctl; static struct cdevsw lpt_cdevsw = { .d_version = D_VERSION, .d_flags = D_NEEDGIANT, .d_open = lptopen, .d_close = lptclose, .d_write = lptwrite, .d_ioctl = lptioctl, .d_name = "lpt", }; static bus_addr_t lpt_iat[] = {0, 2, 4, 6}; #ifndef PC98 /* * Internal routine to lptprobe to do port tests of one byte value */ static int lpt_port_test (int port, u_char data, u_char mask) { int temp, timeout; data = data & mask; outb(port, data); timeout = 10000; do { DELAY(10); temp = inb(port) & mask; } while (temp != data && --timeout); lprintf(("Port 0x%x\tout=%x\tin=%x\ttout=%d\n", port, data, temp, timeout)); return (temp == data); } #endif /* PC98 */ /* * New lpt port probe Geoff Rehmet - Rhodes University - 14/2/94 * Based partially on Rod Grimes' printer probe * * Logic: * 1) If no port address was given, use the bios detected ports * and autodetect what ports the printers are on. * 2) Otherwise, probe the data port at the address given, * using the method in Rod Grimes' port probe. * (Much code ripped off directly from Rod's probe.) * * Comments from Rod's probe: * Logic: * 1) You should be able to write to and read back the same value * to the data port. Do an alternating zeros, alternating ones, * walking zero, and walking one test to check for stuck bits. * * 2) You should be able to write to and read back the same value * to the control port lower 5 bits, the upper 3 bits are reserved * per the IBM PC technical reference manauls and different boards * do different things with them. Do an alternating zeros, alternating * ones, walking zero, and walking one test to check for stuck bits. * * Some printers drag the strobe line down when the are powered off * so this bit has been masked out of the control port test. * * XXX Some printers may not like a fast pulse on init or strobe, I * don't know at this point, if that becomes a problem these bits * should be turned off in the mask byte for the control port test. * * We are finally left with a mask of 0x14, due to some printers * being adamant about holding other bits high ........ * * Before probing the control port, we write a 0 to the data port - * If not, some printers chuck out garbage when the strobe line * gets toggled. * * 3) Set the data and control ports to a value of 0 * * This probe routine has been tested on Epson Lx-800, HP LJ3P, * Epson FX-1170 and C.Itoh 8510RM * printers. * Quick exit on fail added. */ int lpt_probe(device_t dev) { #ifdef PC98 #define PC98_OLD_LPT 0x40 #define PC98_IEEE_1284_FUNCTION 0x149 int rid; struct resource *res; /* Check isapnp ids */ if (isa_get_vendorid(dev)) return ENXIO; rid = 0; res = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, lpt_iat, 4, RF_ACTIVE); if (res == NULL) return ENXIO; isa_load_resourcev(res, lpt_iat, 4); if (isa_get_port(dev) == PC98_OLD_LPT) { unsigned int pc98_ieee_mode, tmp; tmp = inb(PC98_IEEE_1284_FUNCTION); pc98_ieee_mode = tmp; if ((tmp & 0x10) == 0x10) { outb(PC98_IEEE_1284_FUNCTION, tmp & ~0x10); tmp = inb(PC98_IEEE_1284_FUNCTION); if ((tmp & 0x10) != 0x10) { outb(PC98_IEEE_1284_FUNCTION, pc98_ieee_mode); bus_release_resource(dev, SYS_RES_IOPORT, rid, res); return ENXIO; } } } bus_release_resource(dev, SYS_RES_IOPORT, rid, res); return 0; #else int port; static short next_bios_lpt = 0; int status; static u_char testbyte[18] = { 0x55, /* alternating zeros */ 0xaa, /* alternating ones */ 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f, /* walking zero */ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 /* walking one */ }; int i; /* * Make sure there is some way for lptopen to see that * the port is not configured * This 0 will remain if the port isn't attached */ (lpt_sc + dvp->id_unit)->sc_port = 0; status = IO_LPTSIZE; /* If port not specified, use bios list */ if(dvp->id_iobase < 0) { /* port? */ if((next_bios_lpt < BIOS_MAX_LPT) && (*(BIOS_PORTS+next_bios_lpt) != 0) ) { dvp->id_iobase = *(BIOS_PORTS+next_bios_lpt++); goto end_probe; } else return (0); } /* Port was explicitly specified */ /* This allows probing of ports unknown to the BIOS */ port = dvp->id_iobase + lpt_data; for (i = 0; i < 18; i++) { if (!lpt_port_test(port, testbyte[i], 0xff)) { status = 0; goto end_probe; } } end_probe: /* write 0's to control and data ports */ outb(dvp->id_iobase+lpt_data, 0); outb(dvp->id_iobase+lpt_control, 0); return (status); #endif } /* XXX Todo - try and detect if interrupt is working */ int lpt_attach(device_t dev) { int rid, unit; struct lpt_softc *sc; unit = device_get_unit(dev); sc = device_get_softc(dev); rid = 0; sc->res_port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, lpt_iat, 4, RF_ACTIVE); if (sc->res_port == NULL) return ENXIO; isa_load_resourcev(sc->res_port, lpt_iat, 4); sc->sc_port = rman_get_start(sc->res_port); sc->sc_primed = 0; /* not primed yet */ #ifdef PC98 outb(sc->sc_port+lpt_pstb_ctrl, LPC_DIS_PSTB); /* PSTB disable */ outb(sc->sc_port+lpt_control, LPC_MODE8255); /* 8255 mode set */ outb(sc->sc_port+lpt_control, LPC_NIRQ8); /* IRQ8 inactive */ outb(sc->sc_port+lpt_control, LPC_NPSTB); /* PSTB inactive */ outb(sc->sc_port+lpt_pstb_ctrl, LPC_EN_PSTB); /* PSTB enable */ #else outb(sc->sc_port+lpt_control, LPC_NINIT); #endif sc->sc_irq = 0; if (isa_get_irq(dev) != -1) { rid = 0; sc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->res_irq == NULL) { bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->res_port); return ENXIO; } if (bus_setup_intr(dev, sc->res_irq, INTR_TYPE_TTY, lpt_intr, sc, &sc->sc_ih)) { bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->res_port); bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_irq); return ENXIO; } sc->sc_irq = LP_HAS_IRQ | LP_USE_IRQ | LP_ENABLE_IRQ; device_printf(dev, "Interrupt-driven port"); } /* XXX what to do about the flags in the minor number? */ make_dev(&lpt_cdevsw, unit, UID_ROOT, GID_WHEEL, 0600, "lpt%d", unit); make_dev(&lpt_cdevsw, unit | LP_BYPASS, UID_ROOT, GID_WHEEL, 0600, "lpctl%d", unit); return 0; } /* * lptopen -- reset the printer, then wait until it's selected and not busy. * If LP_BYPASS flag is selected, then we do not try to select the * printer -- this is just used for passing ioctls. */ static int lptopen (dev_t dev, int flags, int fmt, struct thread *td) { struct lpt_softc *sc; int s; #ifdef PC98 int port; #else int trys, port; #endif sc = devclass_get_softc(olpt_devclass, LPTUNIT(minor(dev))); if (sc->sc_port == 0) return (ENXIO); if (sc->sc_state) { lprintf(("lp: still open %x\n", sc->sc_state)); return(EBUSY); } else sc->sc_state |= INIT; sc->sc_flags = LPTFLAGS(minor(dev)); /* Check for open with BYPASS flag set. */ if (sc->sc_flags & LP_BYPASS) { sc->sc_state = OPEN; return(0); } s = spltty(); lprintf(("lp flags 0x%x\n", sc->sc_flags)); port = sc->sc_port; /* set IRQ status according to ENABLE_IRQ flag */ if (sc->sc_irq & LP_ENABLE_IRQ) sc->sc_irq |= LP_USE_IRQ; else sc->sc_irq &= ~LP_USE_IRQ; /* init printer */ #ifndef PC98 if ((sc->sc_flags & LP_NO_PRIME) == 0) { if((sc->sc_flags & LP_PRIMEOPEN) || sc->sc_primed == 0) { outb(port+lpt_control, 0); sc->sc_primed++; DELAY(500); } } outb (port+lpt_control, LPC_SEL|LPC_NINIT); /* wait till ready (printer running diagnostics) */ trys = 0; do { /* ran out of waiting for the printer */ if (trys++ >= LPINITRDY*4) { splx(s); sc->sc_state = 0; lprintf(("status %x\n", inb(port+lpt_status))); return (EBUSY); } /* wait 1/4 second, give up if we get a signal */ if (tsleep (sc, LPPRI|PCATCH, "lptinit", hz/4) != EWOULDBLOCK) { sc->sc_state = 0; splx(s); return (EBUSY); } /* is printer online and ready for output */ } while ((inb(port+lpt_status) & (LPS_SEL|LPS_OUT|LPS_NBSY|LPS_NERR)) != (LPS_SEL|LPS_NBSY|LPS_NERR)); sc->sc_control = LPC_SEL|LPC_NINIT; if (sc->sc_flags & LP_AUTOLF) sc->sc_control |= LPC_AUTOL; /* enable interrupt if interrupt-driven */ if (sc->sc_irq & LP_USE_IRQ) sc->sc_control |= LPC_ENA; outb(port+lpt_control, sc->sc_control); #endif sc->sc_state = OPEN; sc->sc_inbuf = malloc(BUFSIZE, M_DEVBUF, M_WAITOK); sc->sc_xfercnt = 0; splx(s); /* only use timeout if using interrupt */ lprintf(("irq %x\n", sc->sc_irq)); if (sc->sc_irq & LP_USE_IRQ) { sc->sc_state |= TOUT; timeout (lptout, (caddr_t)sc, (sc->sc_backoff = hz/LPTOUTINITIAL)); } lprintf(("opened.\n")); return(0); } static void lptout (void *arg) { struct lpt_softc *sc = arg; int pl; lprintf(("T %x ", inb(sc->sc_port+lpt_status))); if (sc->sc_state & OPEN) { sc->sc_backoff++; if (sc->sc_backoff > hz/LPTOUTMAX) sc->sc_backoff = sc->sc_backoff > hz/LPTOUTMAX; timeout (lptout, (caddr_t)sc, sc->sc_backoff); } else sc->sc_state &= ~TOUT; if (sc->sc_state & ERROR) sc->sc_state &= ~ERROR; /* * Avoid possible hangs do to missed interrupts */ if (sc->sc_xfercnt) { pl = spltty(); lpt_intr(sc); splx(pl); } else { sc->sc_state &= ~OBUSY; wakeup(sc); } } /* * lptclose -- close the device, free the local line buffer. * * Check for interrupted write call added. */ static int lptclose(dev_t dev, int flags, int fmt, struct thread *td) { struct lpt_softc *sc; #ifndef PC98 int port; #endif sc = devclass_get_softc(olpt_devclass, LPTUNIT(minor(dev))); if(sc->sc_flags & LP_BYPASS) goto end_close; #ifndef PC98 port = sc->sc_port; #endif sc->sc_state &= ~OPEN; #ifndef PC98 /* if the last write was interrupted, don't complete it */ if((!(sc->sc_state & INTERRUPTED)) && (sc->sc_irq & LP_USE_IRQ)) while ((inb(port+lpt_status) & (LPS_SEL|LPS_OUT|LPS_NBSY|LPS_NERR)) != (LPS_SEL|LPS_NBSY|LPS_NERR) || sc->sc_xfercnt) /* wait 1/4 second, give up if we get a signal */ if (tsleep (sc, LPPRI|PCATCH, "lpclose", hz) != EWOULDBLOCK) break; outb(sc->sc_port+lpt_control, LPC_NINIT); #endif free(sc->sc_inbuf, M_DEVBUF); end_close: sc->sc_state = 0; sc->sc_xfercnt = 0; lprintf(("closed.\n")); return(0); } /* * pushbytes() * Workhorse for actually spinning and writing bytes to printer * Derived from lpa.c * Originally by ? * * This code is only used when we are polling the port */ static int pushbytes(struct lpt_softc * sc) { int spin, err, tic; char ch; int port = sc->sc_port; lprintf(("p")); /* loop for every character .. */ while (sc->sc_xfercnt > 0) { /* printer data */ ch = *(sc->sc_cp); sc->sc_cp++; sc->sc_xfercnt--; /* * Wait for printer ready. * Loop 20 usecs testing BUSY bit, then sleep * for exponentially increasing timeout. (vak) */ for (spin=0; NOT_READY(port+lpt_status) && spin= MAX_SPIN) { tic = 0; while (NOT_READY(port+lpt_status)) { /* * Now sleep, every cycle a * little longer .. */ tic = tic + tic + 1; /* * But no more than 10 seconds. (vak) */ if (tic > MAX_SLEEP) tic = MAX_SLEEP; err = tsleep(sc, LPPRI, "lptpoll", tic); if (err != EWOULDBLOCK) { return (err); } } } /* output data */ outb(port+lpt_data, ch); #ifdef PC98 DELAY(1); outb(port+lpt_control, LPC_PSTB); DELAY(1); outb(port+lpt_control, LPC_NPSTB); #else /* strobe */ outb(port+lpt_control, sc->sc_control|LPC_STB); outb(port+lpt_control, sc->sc_control); #endif } return(0); } /* * lptwrite --copy a line from user space to a local buffer, then call * putc to get the chars moved to the output queue. * * Flagging of interrupted write added. */ static int lptwrite(dev_t dev, struct uio * uio, int ioflag) { register unsigned n; int pl, err; struct lpt_softc *sc; sc = devclass_get_softc(olpt_devclass, LPTUNIT(minor(dev))); if(sc->sc_flags & LP_BYPASS) { /* we can't do writes in bypass mode */ return(EPERM); } sc->sc_state &= ~INTERRUPTED; while ((n = min(BUFSIZE, uio->uio_resid)) != 0) { sc->sc_cp = sc->sc_inbuf; uiomove(sc->sc_cp, n, uio); sc->sc_xfercnt = n ; while ((sc->sc_xfercnt > 0)&&(sc->sc_irq & LP_USE_IRQ)) { lprintf(("i")); /* if the printer is ready for a char, */ /* give it one */ if ((sc->sc_state & OBUSY) == 0){ lprintf(("\nC %d. ", sc->sc_xfercnt)); pl = spltty(); lpt_intr(sc); (void) splx(pl); } lprintf(("W ")); if (sc->sc_state & OBUSY) if ((err = tsleep (sc, LPPRI|PCATCH, "lpwrite", 0))) { sc->sc_state |= INTERRUPTED; return(err); } } /* check to see if we must do a polled write */ if(!(sc->sc_irq & LP_USE_IRQ) && (sc->sc_xfercnt)) { lprintf(("p")); if((err = pushbytes(sc))) return(err); } } return(0); } /* * lptintr -- handle printer interrupts which occur when the printer is * ready to accept another char. * * do checking for interrupted write call. */ static void lpt_intr(void *arg) { } static int lptioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct thread *td) { int error = 0; struct lpt_softc *sc; u_int unit = LPTUNIT(minor(dev)); u_char old_sc_irq; /* old printer IRQ status */ sc = devclass_get_softc(olpt_devclass, unit); switch (cmd) { case LPT_IRQ : if(sc->sc_irq & LP_HAS_IRQ) { /* * NOTE: * If the IRQ status is changed, * this will only be visible on the * next open. * * If interrupt status changes, * this gets syslog'd. */ old_sc_irq = sc->sc_irq; if(*(int*)data == 0) sc->sc_irq &= (~LP_ENABLE_IRQ); else sc->sc_irq |= LP_ENABLE_IRQ; if (old_sc_irq != sc->sc_irq ) log(LOG_NOTICE, "lpt%c switched to %s mode\n", (char)unit+'0', (sc->sc_irq & LP_ENABLE_IRQ)? "interrupt-driven":"polled"); } else /* polled port */ error = EOPNOTSUPP; break; default: error = ENODEV; } return(error); } Index: head/sys/pc98/cbus/pcrtc.c =================================================================== --- head/sys/pc98/cbus/pcrtc.c (revision 130173) +++ head/sys/pc98/cbus/pcrtc.c (revision 130174) @@ -1,1018 +1,1019 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz and Don Ahn. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 * $FreeBSD$ */ /* * Routines to handle clock hardware. */ /* * inittodr, settodr and support routines written * by Christoph Robitschko * * reintroduced and updated by Chris Stenton 8/10/94 */ /* * modified for PC98 by Kakefuda */ #include "opt_clock.h" #include "opt_isa.h" #include "opt_mca.h" #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(SMP) #include #endif #include #include #include #include #ifdef DEV_ISA #include #endif #include /* * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we * can use a simple formula for leap years. */ #define LEAPYEAR(y) (((u_int)(y) % 4 == 0) ? 1 : 0) #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) #ifndef BURN_BRIDGES /* * Time in timer cycles that it takes for microtime() to disable interrupts * and latch the count. microtime() currently uses "cli; outb ..." so it * normally takes less than 2 timer cycles. Add a few for cache misses. * Add a few more to allow for latency in bogus calls to microtime() with * interrupts already disabled. */ #define TIMER0_LATCH_COUNT 20 /* * Maximum frequency that we are willing to allow for timer0. Must be * low enough to guarantee that the timer interrupt handler returns * before the next timer interrupt. */ #define TIMER0_MAX_FREQ 20000 #endif int adjkerntz; /* local offset from GMT in seconds */ int clkintr_pending; int disable_rtc_set; /* disable resettodr() if != 0 */ int pscnt = 1; int psdiv = 1; int statclock_disable; #ifndef TIMER_FREQ #define TIMER_FREQ 2457600 #endif u_int timer_freq = TIMER_FREQ; int timer0_max_count; int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ struct mtx clock_lock; static int beeping = 0; static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; static u_int hardclock_max_count; static u_int32_t i8254_lastcount; static u_int32_t i8254_offset; static int i8254_ticked; static struct intsrc *i8254_intsrc; #ifndef BURN_BRIDGES /* * XXX new_function and timer_func should not handle clockframes, but * timer_func currently needs to hold hardclock to handle the * timer0_state == 0 case. We should use inthand_add()/inthand_remove() * to switch between clkintr() and a slightly different timerintr(). */ static void (*new_function)(struct clockframe *frame); static u_int new_rate; static u_int timer0_prescaler_count; static u_char timer0_state; #endif /* Values for timerX_state: */ #define RELEASED 0 #define RELEASE_PENDING 1 #define ACQUIRED 2 #define ACQUIRE_PENDING 3 static u_char timer1_state; static u_char timer2_state; static void (*timer_func)(struct clockframe *frame) = hardclock; static void rtc_serialcombit(int); static void rtc_serialcom(int); static int rtc_inb(void); static void rtc_outb(int); static unsigned i8254_get_timecount(struct timecounter *tc); static void set_timer_freq(u_int freq, int intr_freq); static struct timecounter i8254_timecounter = { i8254_get_timecount, /* get_timecount */ 0, /* no poll_pps */ ~0u, /* counter_mask */ 0, /* frequency */ "i8254", /* name */ 0 /* quality */ }; static void clkintr(struct clockframe *frame) { if (timecounter->tc_get_timecount == i8254_get_timecount) { mtx_lock_spin(&clock_lock); if (i8254_ticked) i8254_ticked = 0; else { i8254_offset += timer0_max_count; i8254_lastcount = 0; } clkintr_pending = 0; mtx_unlock_spin(&clock_lock); } timer_func(frame); #ifdef SMP if (timer_func == hardclock) forward_hardclock(); #endif #ifndef BURN_BRIDGES switch (timer0_state) { case RELEASED: break; case ACQUIRED: if ((timer0_prescaler_count += timer0_max_count) >= hardclock_max_count) { timer0_prescaler_count -= hardclock_max_count; hardclock(frame); #ifdef SMP forward_hardclock(); #endif } break; case ACQUIRE_PENDING: mtx_lock_spin(&clock_lock); i8254_offset = i8254_get_timecount(NULL); i8254_lastcount = 0; timer0_max_count = TIMER_DIV(new_rate); outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); timer_func = new_function; timer0_state = ACQUIRED; break; case RELEASE_PENDING: if ((timer0_prescaler_count += timer0_max_count) >= hardclock_max_count) { mtx_lock_spin(&clock_lock); i8254_offset = i8254_get_timecount(NULL); i8254_lastcount = 0; timer0_max_count = hardclock_max_count; outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); timer0_prescaler_count = 0; timer_func = hardclock; timer0_state = RELEASED; hardclock(frame); #ifdef SMP forward_hardclock(); #endif } break; } #endif } #ifndef BURN_BRIDGES /* * The acquire and release functions must be called at ipl >= splclock(). */ int acquire_timer0(int rate, void (*function)(struct clockframe *frame)) { static int old_rate; if (rate <= 0 || rate > TIMER0_MAX_FREQ) return (-1); switch (timer0_state) { case RELEASED: timer0_state = ACQUIRE_PENDING; break; case RELEASE_PENDING: if (rate != old_rate) return (-1); /* * The timer has been released recently, but is being * re-acquired before the release completed. In this * case, we simply reclaim it as if it had not been * released at all. */ timer0_state = ACQUIRED; break; default: return (-1); /* busy */ } new_function = function; old_rate = new_rate = rate; return (0); } #endif int acquire_timer1(int mode) { if (timer1_state != RELEASED) return (-1); timer1_state = ACQUIRED; /* * This access to the timer registers is as atomic as possible * because it is a single instruction. We could do better if we * knew the rate. Use of splclock() limits glitches to 10-100us, * and this is probably good enough for timer2, so we aren't as * careful with it as with timer0. */ outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); return (0); } int acquire_timer2(int mode) { if (timer2_state != RELEASED) return (-1); timer2_state = ACQUIRED; /* * This access to the timer registers is as atomic as possible * because it is a single instruction. We could do better if we * knew the rate. Use of splclock() limits glitches to 10-100us, * and this is probably good enough for timer2, so we aren't as * careful with it as with timer0. */ outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); return (0); } #ifndef BURN_BRIDGES int release_timer0() { switch (timer0_state) { case ACQUIRED: timer0_state = RELEASE_PENDING; break; case ACQUIRE_PENDING: /* Nothing happened yet, release quickly. */ timer0_state = RELEASED; break; default: return (-1); } return (0); } #endif int release_timer1() { if (timer1_state != ACQUIRED) return (-1); timer1_state = RELEASED; outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); return (0); } int release_timer2() { if (timer2_state != ACQUIRED) return (-1); timer2_state = RELEASED; outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); return (0); } static int getit(void) { int high, low; mtx_lock_spin(&clock_lock); /* Select timer0 and latch counter value. */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); low = inb(TIMER_CNTR0); high = inb(TIMER_CNTR0); mtx_unlock_spin(&clock_lock); return ((high << 8) | low); } /* * Wait "n" microseconds. * Relies on timer 1 counting down from (timer_freq / hz) * Note: timer had better have been programmed before this is first used! */ void DELAY(int n) { int delta, prev_tick, tick, ticks_left; #ifdef DELAYDEBUG int getit_calls = 1; int n1; static int state = 0; if (state == 0) { state = 1; for (n1 = 1; n1 <= 10000000; n1 *= 10) DELAY(n1); state = 2; } if (state == 1) printf("DELAY(%d)...", n); #endif /* * Guard against the timer being uninitialized if we are called * early for console i/o. */ if (timer0_max_count == 0) set_timer_freq(timer_freq, hz); /* * Read the counter first, so that the rest of the setup overhead is * counted. Guess the initial overhead is 20 usec (on most systems it * takes about 1.5 usec for each of the i/o's in getit(). The loop * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The * multiplications and divisions to scale the count take a while). * * However, if ddb is active then use a fake counter since reading * the i8254 counter involves acquiring a lock. ddb must not go * locking for many reasons, but it calls here for at least atkbd * input. */ #ifdef DDB if (db_active) prev_tick = 0; else #endif prev_tick = getit(); n -= 0; /* XXX actually guess no initial overhead */ /* * Calculate (n * (timer_freq / 1e6)) without using floating point * and without any avoidable overflows. */ if (n <= 0) ticks_left = 0; else if (n < 256) /* * Use fixed point to avoid a slow division by 1000000. * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. * 2^15 is the first power of 2 that gives exact results * for n between 0 and 256. */ ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; else /* * Don't bother using fixed point, although gcc-2.7.2 * generates particularly poor code for the long long * division, since even the slow way will complete long * before the delay is up (unless we're interrupted). */ ticks_left = ((u_int)n * (long long)timer_freq + 999999) / 1000000; while (ticks_left > 0) { #ifdef DDB if (db_active) { outb(0x5f, 0); tick = prev_tick + 1; } else #endif tick = getit(); #ifdef DELAYDEBUG ++getit_calls; #endif delta = prev_tick - tick; prev_tick = tick; if (delta < 0) { delta += timer0_max_count; /* * Guard against timer0_max_count being wrong. * This shouldn't happen in normal operation, * but it may happen if set_timer_freq() is * traced. */ if (delta < 0) delta = 0; } ticks_left -= delta; } #ifdef DELAYDEBUG if (state == 1) printf(" %d calls to getit() at %d usec each\n", getit_calls, (n + 5) / getit_calls); #endif } static void sysbeepstop(void *chan) { outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ release_timer1(); beeping = 0; } int sysbeep(int pitch, int period) { int x = splclock(); if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) if (!beeping) { /* Something else owns it. */ splx(x); return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ } disable_intr(); outb(0x3fdb, pitch); outb(0x3fdb, (pitch>>8)); enable_intr(); if (!beeping) { /* enable counter1 output to speaker */ outb(IO_PPI, (inb(IO_PPI) & 0xf7)); beeping = period; timeout(sysbeepstop, (void *)NULL, period); } splx(x); return (0); } unsigned int delaycount; #define FIRST_GUESS 0x2000 static void findcpuspeed(void) { int i; int remainder; /* Put counter in count down mode */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); outb(TIMER_CNTR0, 0xff); outb(TIMER_CNTR0, 0xff); for (i = FIRST_GUESS; i; i--) ; remainder = getit(); delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); } static u_int calibrate_clocks(void) { int timeout; u_int count, prev_count, tot_count; u_short sec, start_sec; if (bootverbose) printf("Calibrating clock(s) ... "); /* Check ARTIC. */ if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) goto fail; timeout = 100000000; /* Read the ARTIC. */ sec = inw(0x5e); /* Wait for the ARTIC to changes. */ start_sec = sec; for (;;) { sec = inw(0x5e); if (sec != start_sec) break; if (--timeout == 0) goto fail; } prev_count = getit(); if (prev_count == 0 || prev_count > timer0_max_count) goto fail; tot_count = 0; start_sec = sec; for (;;) { sec = inw(0x5e); count = getit(); if (count == 0 || count > timer0_max_count) goto fail; if (count > prev_count) tot_count += prev_count - (count - timer0_max_count); else tot_count += prev_count - count; prev_count = count; if ((sec == start_sec + 1200) || /* 1200 = 307.2KHz >> 8 */ (sec < start_sec && (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) break; if (--timeout == 0) goto fail; } if (bootverbose) { printf("i8254 clock: %u Hz\n", tot_count); } return (tot_count); fail: if (bootverbose) printf("failed, using default i8254 clock of %u Hz\n", timer_freq); return (timer_freq); } static void set_timer_freq(u_int freq, int intr_freq) { int new_timer0_max_count; mtx_lock_spin(&clock_lock); timer_freq = freq; new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); if (new_timer0_max_count != timer0_max_count) { timer0_max_count = new_timer0_max_count; outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); } mtx_unlock_spin(&clock_lock); } static void i8254_restore(void) { mtx_lock_spin(&clock_lock); outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); } /* * Restore all the timers non-atomically (XXX: should be atomically). * * This function is called from pmtimer_resume() to restore all the timers. * This should not be necessary, but there are broken laptops that do not * restore all the timers on resume. */ void timer_restore(void) { i8254_restore(); /* restore timer_freq and hz */ } /* * Initialize 8254 timer 0 early so that it can be used in DELAY(). * XXX initialization of other timers is unintentionally left blank. */ void startrtclock() { u_int delta, freq; findcpuspeed(); if (pc98_machine_type & M_8M) timer_freq = 1996800L; /* 1.9968 MHz */ else timer_freq = 2457600L; /* 2.4576 MHz */ set_timer_freq(timer_freq, hz); freq = calibrate_clocks(); #ifdef CLK_CALIBRATION_LOOP if (bootverbose) { printf( "Press a key on the console to abort clock calibration\n"); while (cncheckc() == -1) calibrate_clocks(); } #endif /* * Use the calibrated i8254 frequency if it seems reasonable. * Otherwise use the default, and don't use the calibrated i586 * frequency. */ delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; if (delta < timer_freq / 100) { #ifndef CLK_USE_I8254_CALIBRATION if (bootverbose) printf( "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); freq = timer_freq; #endif timer_freq = freq; } else { if (bootverbose) printf( "%d Hz differs from default of %d Hz by more than 1%%\n", freq, timer_freq); } set_timer_freq(timer_freq, hz); i8254_timecounter.tc_frequency = timer_freq; tc_init(&i8254_timecounter); init_TSC(); } static void rtc_serialcombit(int i) { outb(IO_RTC, ((i&0x01)<<5)|0x07); DELAY(1); outb(IO_RTC, ((i&0x01)<<5)|0x17); DELAY(1); outb(IO_RTC, ((i&0x01)<<5)|0x07); DELAY(1); } static void rtc_serialcom(int i) { rtc_serialcombit(i&0x01); rtc_serialcombit((i&0x02)>>1); rtc_serialcombit((i&0x04)>>2); rtc_serialcombit((i&0x08)>>3); outb(IO_RTC, 0x07); DELAY(1); outb(IO_RTC, 0x0f); DELAY(1); outb(IO_RTC, 0x07); DELAY(1); } static void rtc_outb(int val) { int s; int sa = 0; for (s=0;s<8;s++) { sa = ((val >> s) & 0x01) ? 0x27 : 0x07; outb(IO_RTC, sa); /* set DI & CLK 0 */ DELAY(1); outb(IO_RTC, sa | 0x10); /* CLK 1 */ DELAY(1); } outb(IO_RTC, sa & 0xef); /* CLK 0 */ } static int rtc_inb(void) { int s; int sa = 0; for (s=0;s<8;s++) { sa |= ((inb(0x33) & 0x01) << s); outb(IO_RTC, 0x17); /* CLK 1 */ DELAY(1); outb(IO_RTC, 0x07); /* CLK 0 */ DELAY(2); } return sa; } /* * Initialize the time of day register, based on the time base which is, e.g. * from a filesystem. */ void inittodr(time_t base) { unsigned long sec, days; int year, month; int y, m, s; struct timespec ts; int second, min, hour; if (base) { s = splclock(); ts.tv_sec = base; ts.tv_nsec = 0; tc_setclock(&ts); splx(s); } rtc_serialcom(0x03); /* Time Read */ rtc_serialcom(0x01); /* Register shift command. */ DELAY(20); second = bcd2bin(rtc_inb() & 0xff); /* sec */ min = bcd2bin(rtc_inb() & 0xff); /* min */ hour = bcd2bin(rtc_inb() & 0xff); /* hour */ days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ month = (rtc_inb() >> 4) & 0x0f; /* month */ for (m = 1; m < month; m++) days += daysinmonth[m-1]; year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ /* 2000 year problem */ if (year < 1995) year += 100; if (year < 1970) goto wrong_time; for (y = 1970; y < year; y++) days += DAYSPERYEAR + LEAPYEAR(y); if ((month > 2) && LEAPYEAR(year)) days ++; sec = ((( days * 24 + hour) * 60 + min) * 60 + second); /* sec now contains the number of seconds, since Jan 1 1970, in the local time zone */ s = splhigh(); sec += tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); y = time_second - sec; if (y <= -2 || y >= 2) { /* badly off, adjust it */ ts.tv_sec = sec; ts.tv_nsec = 0; tc_setclock(&ts); } splx(s); return; wrong_time: printf("Invalid time in real time clock.\n"); printf("Check and reset the date immediately!\n"); } /* * Write system time back to RTC */ void resettodr() { unsigned long tm; int y, m, s; int wd; if (disable_rtc_set) return; s = splclock(); tm = time_second; splx(s); rtc_serialcom(0x01); /* Register shift command. */ /* Calculate local time to put in RTC */ tm -= tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ /* We have now the days since 01-01-1970 in tm */ wd = (tm + 4) % 7 + 1; /* Write back Weekday */ for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); tm >= m; y++, m = DAYSPERYEAR + LEAPYEAR(y)) tm -= m; /* Now we have the years in y and the day-of-the-year in tm */ for (m = 0; ; m++) { int ml; ml = daysinmonth[m]; if (m == 1 && LEAPYEAR(y)) ml++; if (tm < ml) break; tm -= ml; } m++; rtc_outb(bin2bcd(tm+1)); /* Write back Day */ rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ rtc_outb(bin2bcd(y%100)); /* Write back Year */ rtc_serialcom(0x02); /* Time set & Counter hold command. */ rtc_serialcom(0x00); /* Register hold command. */ } /* * Start both clocks running. */ void cpu_initclocks() { /* Finish initializing 8254 timer 0. */ intr_add_handler("clk", 0, (driver_intr_t *)clkintr, NULL, INTR_TYPE_CLK | INTR_FAST, NULL); init_TSC_tc(); } void cpu_startprofclock(void) { } void cpu_stopprofclock(void) { } static int sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) { int error; u_int freq; /* * Use `i8254' instead of `timer' in external names because `timer' * is is too generic. Should use it everywhere. */ freq = timer_freq; error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); if (error == 0 && req->newptr != NULL) { #ifndef BURN_BRIDGES if (timer0_state != RELEASED) return (EBUSY); /* too much trouble to handle */ #endif set_timer_freq(freq, hz); i8254_timecounter.tc_frequency = freq; } return (error); } SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", ""); static unsigned i8254_get_timecount(struct timecounter *tc) { u_int count; u_int high, low; u_int eflags; eflags = read_eflags(); mtx_lock_spin(&clock_lock); /* Select timer0 and latch counter value. */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); low = inb(TIMER_CNTR0); high = inb(TIMER_CNTR0); count = timer0_max_count - ((high << 8) | low); if (count < i8254_lastcount || (!i8254_ticked && (clkintr_pending || ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) && i8254_intsrc != NULL && i8254_intsrc->is_pic->pic_source_pending(i8254_intsrc))))) { i8254_ticked = 1; i8254_offset += timer0_max_count; } i8254_lastcount = count; count += i8254_offset; mtx_unlock_spin(&clock_lock); return (count); } #ifdef DEV_ISA /* * Attach to the ISA PnP descriptors for the timer and realtime clock. */ static struct isa_pnp_id attimer_ids[] = { { 0x0001d041 /* PNP0100 */, "AT timer" }, { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, { 0 } }; static int attimer_probe(device_t dev) { int result; if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0) device_quiet(dev); return(result); } static int attimer_attach(device_t dev) { return(0); } static device_method_t attimer_methods[] = { /* Device interface */ DEVMETHOD(device_probe, attimer_probe), DEVMETHOD(device_attach, attimer_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */ DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */ { 0, 0 } }; static driver_t attimer_driver = { "attimer", attimer_methods, 1, /* no softc */ }; static devclass_t attimer_devclass; DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); #endif /* DEV_ISA */ Index: head/sys/pc98/cbus/ppc.c =================================================================== --- head/sys/pc98/cbus/ppc.c (revision 130173) +++ head/sys/pc98/cbus/ppc.c (revision 130174) @@ -1,2210 +1,2211 @@ /*- * Copyright (c) 2001 Alcove - Nicolas Souchu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include "opt_ppc.h" #include #include #include +#include #include #include #include #include #include #include #include #ifdef PC98 #include #else #include #endif #include #include #include #include #ifdef PC98 #include #else #include #endif #include "ppbus_if.h" static int ppc_cbus_probe(device_t dev); static void ppcintr(void *arg); #define LOG_PPC(function, ppc, string) \ if (bootverbose) printf("%s: %s\n", function, string) #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) devclass_t ppc_devclass; static device_method_t ppc_methods[] = { /* device interface */ DEVMETHOD(device_probe, ppc_cbus_probe), DEVMETHOD(device_attach, ppc_attach), /* bus interface */ DEVMETHOD(bus_read_ivar, ppc_read_ivar), DEVMETHOD(bus_setup_intr, ppc_setup_intr), DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), /* ppbus interface */ DEVMETHOD(ppbus_io, ppc_io), DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), DEVMETHOD(ppbus_setmode, ppc_setmode), DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), DEVMETHOD(ppbus_read, ppc_read), DEVMETHOD(ppbus_write, ppc_write), { 0, 0 } }; static driver_t ppc_driver = { "ppc", ppc_methods, sizeof(struct ppc_data), }; static char *ppc_models[] = { "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", "SMC FDC37C935", "PC87303", 0 }; /* list of available modes */ static char *ppc_avms[] = { "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 }; /* list of current executing modes * Note that few modes do not actually exist. */ static char *ppc_modes[] = { "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", "EPP", "EPP", "EPP", "ECP", "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 }; static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; #ifdef __i386__ /* * BIOS printer list - used by BIOS probe. */ #define BIOS_PPC_PORTS 0x408 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) #define BIOS_MAX_PPC 4 #endif /* * ppc_ecp_sync() XXX */ void ppc_ecp_sync(device_t dev) { int i, r; struct ppc_data *ppc = DEVTOSOFTC(dev); if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) return; r = r_ecr(ppc); if ((r & 0xe0) != PPC_ECR_EPP) return; for (i = 0; i < 100; i++) { r = r_ecr(ppc); if (r & 0x1) return; DELAY(100); } printf("ppc%d: ECP sync failed as data still " \ "present in FIFO.\n", ppc->ppc_unit); return; } /* * ppc_detect_fifo() * * Detect parallel port FIFO */ static int ppc_detect_fifo(struct ppc_data *ppc) { char ecr_sav; char ctr_sav, ctr, cc; short i; /* save registers */ ecr_sav = r_ecr(ppc); ctr_sav = r_ctr(ppc); /* enter ECP configuration mode, no interrupt, no DMA */ w_ecr(ppc, 0xf4); /* read PWord size - transfers in FIFO mode must be PWord aligned */ ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); /* XXX 16 and 32 bits implementations not supported */ if (ppc->ppc_pword != PPC_PWORD_8) { LOG_PPC(__func__, ppc, "PWord not supported"); goto error; } w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ ctr = r_ctr(ppc); w_ctr(ppc, ctr | PCD); /* set direction to 1 */ /* enter ECP test mode, no interrupt, no DMA */ w_ecr(ppc, 0xd4); /* flush the FIFO */ for (i=0; i<1024; i++) { if (r_ecr(ppc) & PPC_FIFO_EMPTY) break; cc = r_fifo(ppc); } if (i >= 1024) { LOG_PPC(__func__, ppc, "can't flush FIFO"); goto error; } /* enable interrupts, no DMA */ w_ecr(ppc, 0xd0); /* determine readIntrThreshold * fill the FIFO until serviceIntr is set */ for (i=0; i<1024; i++) { w_fifo(ppc, (char)i); if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { /* readThreshold reached */ ppc->ppc_rthr = i+1; } if (r_ecr(ppc) & PPC_FIFO_FULL) { ppc->ppc_fifo = i+1; break; } } if (i >= 1024) { LOG_PPC(__func__, ppc, "can't fill FIFO"); goto error; } w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ w_ecr(ppc, 0xd0); /* enable interrupts */ /* determine writeIntrThreshold * empty the FIFO until serviceIntr is set */ for (i=ppc->ppc_fifo; i>0; i--) { if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { LOG_PPC(__func__, ppc, "invalid data in FIFO"); goto error; } if (r_ecr(ppc) & PPC_SERVICE_INTR) { /* writeIntrThreshold reached */ ppc->ppc_wthr = ppc->ppc_fifo - i+1; } /* if FIFO empty before the last byte, error */ if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { LOG_PPC(__func__, ppc, "data lost in FIFO"); goto error; } } /* FIFO must be empty after the last byte */ if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { LOG_PPC(__func__, ppc, "can't empty the FIFO"); goto error; } w_ctr(ppc, ctr_sav); w_ecr(ppc, ecr_sav); return (0); error: w_ctr(ppc, ctr_sav); w_ecr(ppc, ecr_sav); return (EINVAL); } static int ppc_detect_port(struct ppc_data *ppc) { w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ w_dtr(ppc, 0xaa); if (r_dtr(ppc) != 0xaa) return (0); return (1); } /* * EPP timeout, according to the PC87332 manual * Semantics of clearing EPP timeout bit. * PC87332 - reading SPP_STR does it... * SMC - write 1 to EPP timeout bit XXX * Others - (?) write 0 to EPP timeout bit */ static void ppc_reset_epp_timeout(struct ppc_data *ppc) { register char r; r = r_str(ppc); w_str(ppc, r | 0x1); w_str(ppc, r & 0xfe); return; } static int ppc_check_epp_timeout(struct ppc_data *ppc) { ppc_reset_epp_timeout(ppc); return (!(r_str(ppc) & TIMEOUT)); } /* * Configure current operating mode */ static int ppc_generic_setmode(struct ppc_data *ppc, int mode) { u_char ecr = 0; /* check if mode is available */ if (mode && !(ppc->ppc_avm & mode)) return (EINVAL); /* if ECP mode, configure ecr register */ if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { /* return to byte mode (keeping direction bit), * no interrupt, no DMA to be able to change to * ECP */ w_ecr(ppc, PPC_ECR_RESET); ecr = PPC_DISABLE_INTR; if (mode & PPB_EPP) return (EINVAL); else if (mode & PPB_ECP) /* select ECP mode */ ecr |= PPC_ECR_ECP; else if (mode & PPB_PS2) /* select PS2 mode with ECP */ ecr |= PPC_ECR_PS2; else /* select COMPATIBLE/NIBBLE mode */ ecr |= PPC_ECR_STD; w_ecr(ppc, ecr); } ppc->ppc_mode = mode; return (0); } /* * The ppc driver is free to choose options like FIFO or DMA * if ECP mode is available. * * The 'RAW' option allows the upper drivers to force the ppc mode * even with FIFO, DMA available. */ static int ppc_smclike_setmode(struct ppc_data *ppc, int mode) { u_char ecr = 0; /* check if mode is available */ if (mode && !(ppc->ppc_avm & mode)) return (EINVAL); /* if ECP mode, configure ecr register */ if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { /* return to byte mode (keeping direction bit), * no interrupt, no DMA to be able to change to * ECP or EPP mode */ w_ecr(ppc, PPC_ECR_RESET); ecr = PPC_DISABLE_INTR; if (mode & PPB_EPP) /* select EPP mode */ ecr |= PPC_ECR_EPP; else if (mode & PPB_ECP) /* select ECP mode */ ecr |= PPC_ECR_ECP; else if (mode & PPB_PS2) /* select PS2 mode with ECP */ ecr |= PPC_ECR_PS2; else /* select COMPATIBLE/NIBBLE mode */ ecr |= PPC_ECR_STD; w_ecr(ppc, ecr); } ppc->ppc_mode = mode; return (0); } #ifdef PPC_PROBE_CHIPSET /* * ppc_pc873xx_detect * * Probe for a Natsemi PC873xx-family part. * * References in this function are to the National Semiconductor * PC87332 datasheet TL/C/11930, May 1995 revision. */ static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; static int pc873xx_irqtab[] = {5, 7, 5, 0}; static int pc873xx_regstab[] = { PC873_FER, PC873_FAR, PC873_PTR, PC873_FCR, PC873_PCR, PC873_PMC, PC873_TUP, PC873_SID, PC873_PNP0, PC873_PNP1, PC873_LPTBA, -1 }; static char *pc873xx_rnametab[] = { "FER", "FAR", "PTR", "FCR", "PCR", "PMC", "TUP", "SID", "PNP0", "PNP1", "LPTBA", NULL }; static int ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ { static int index = 0; int idport, irq; int ptr, pcr, val, i; while ((idport = pc873xx_basetab[index++])) { /* XXX should check first to see if this location is already claimed */ /* * Pull the 873xx through the power-on ID cycle (2.2,1.). * We can't use this to locate the chip as it may already have * been used by the BIOS. */ (void)inb(idport); (void)inb(idport); (void)inb(idport); (void)inb(idport); /* * Read the SID byte. Possible values are : * * 01010xxx PC87334 * 0001xxxx PC87332 * 01110xxx PC87306 * 00110xxx PC87303 */ outb(idport, PC873_SID); val = inb(idport + 1); if ((val & 0xf0) == 0x10) { ppc->ppc_model = NS_PC87332; } else if ((val & 0xf8) == 0x70) { ppc->ppc_model = NS_PC87306; } else if ((val & 0xf8) == 0x50) { ppc->ppc_model = NS_PC87334; } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the documentation, but probing yielded 0x40... */ ppc->ppc_model = NS_PC87303; } else { if (bootverbose && (val != 0xff)) printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); continue ; /* not recognised */ } /* print registers */ if (bootverbose) { printf("PC873xx"); for (i=0; pc873xx_regstab[i] != -1; i++) { outb(idport, pc873xx_regstab[i]); printf(" %s=0x%x", pc873xx_rnametab[i], inb(idport + 1) & 0xff); } printf("\n"); } /* * We think we have one. Is it enabled and where we want it to be? */ outb(idport, PC873_FER); val = inb(idport + 1); if (!(val & PC873_PPENABLE)) { if (bootverbose) printf("PC873xx parallel port disabled\n"); continue; } outb(idport, PC873_FAR); val = inb(idport + 1); /* XXX we should create a driver instance for every port found */ if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { /* First try to change the port address to that requested... */ switch(ppc->ppc_base) { case 0x378: val &= 0xfc; break; case 0x3bc: val &= 0xfd; break; case 0x278: val &= 0xfe; break; default: val &= 0xfd; break; } outb(idport, PC873_FAR); outb(idport + 1, val); outb(idport + 1, val); /* Check for success by reading back the value we supposedly wrote and comparing...*/ outb(idport, PC873_FAR); val = inb(idport + 1) & 0x3; /* If we fail, report the failure... */ if (pc873xx_porttab[val] != ppc->ppc_base) { if (bootverbose) printf("PC873xx at 0x%x not for driver at port 0x%x\n", pc873xx_porttab[val], ppc->ppc_base); } continue; } outb(idport, PC873_PTR); ptr = inb(idport + 1); /* get irq settings */ if (ppc->ppc_base == 0x378) irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; else irq = pc873xx_irqtab[val]; if (bootverbose) printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); /* * Check if irq settings are correct */ if (irq != ppc->ppc_irq) { /* * If the chipset is not locked and base address is 0x378, * we have another chance */ if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { if (ppc->ppc_irq == 7) { outb(idport + 1, (ptr | PC873_LPTBIRQ7)); outb(idport + 1, (ptr | PC873_LPTBIRQ7)); } else { outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); } if (bootverbose) printf("PC873xx irq set to %d\n", ppc->ppc_irq); } else { if (bootverbose) printf("PC873xx sorry, can't change irq setting\n"); } } else { if (bootverbose) printf("PC873xx irq settings are correct\n"); } outb(idport, PC873_PCR); pcr = inb(idport + 1); if ((ptr & PC873_CFGLOCK) || !chipset_mode) { if (bootverbose) printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); ppc->ppc_avm |= PPB_NIBBLE; if (bootverbose) printf(", NIBBLE"); if (pcr & PC873_EPPEN) { ppc->ppc_avm |= PPB_EPP; if (bootverbose) printf(", EPP"); if (pcr & PC873_EPP19) ppc->ppc_epp = EPP_1_9; else ppc->ppc_epp = EPP_1_7; if ((ppc->ppc_model == NS_PC87332) && bootverbose) { outb(idport, PC873_PTR); ptr = inb(idport + 1); if (ptr & PC873_EPPRDIR) printf(", Regular mode"); else printf(", Automatic mode"); } } else if (pcr & PC873_ECPEN) { ppc->ppc_avm |= PPB_ECP; if (bootverbose) printf(", ECP"); if (pcr & PC873_ECPCLK) { /* XXX */ ppc->ppc_avm |= PPB_PS2; if (bootverbose) printf(", PS/2"); } } else { outb(idport, PC873_PTR); ptr = inb(idport + 1); if (ptr & PC873_EXTENDED) { ppc->ppc_avm |= PPB_SPP; if (bootverbose) printf(", SPP"); } } } else { if (bootverbose) printf("PC873xx unlocked"); if (chipset_mode & PPB_ECP) { if ((chipset_mode & PPB_EPP) && bootverbose) printf(", ECP+EPP not supported"); pcr &= ~PC873_EPPEN; pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ outb(idport + 1, pcr); outb(idport + 1, pcr); if (bootverbose) printf(", ECP"); } else if (chipset_mode & PPB_EPP) { pcr &= ~(PC873_ECPEN | PC873_ECPCLK); pcr |= (PC873_EPPEN | PC873_EPP19); outb(idport + 1, pcr); outb(idport + 1, pcr); ppc->ppc_epp = EPP_1_9; /* XXX */ if (bootverbose) printf(", EPP1.9"); /* enable automatic direction turnover */ if (ppc->ppc_model == NS_PC87332) { outb(idport, PC873_PTR); ptr = inb(idport + 1); ptr &= ~PC873_EPPRDIR; outb(idport + 1, ptr); outb(idport + 1, ptr); if (bootverbose) printf(", Automatic mode"); } } else { pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); outb(idport + 1, pcr); outb(idport + 1, pcr); /* configure extended bit in PTR */ outb(idport, PC873_PTR); ptr = inb(idport + 1); if (chipset_mode & PPB_PS2) { ptr |= PC873_EXTENDED; if (bootverbose) printf(", PS/2"); } else { /* default to NIBBLE mode */ ptr &= ~PC873_EXTENDED; if (bootverbose) printf(", NIBBLE"); } outb(idport + 1, ptr); outb(idport + 1, ptr); } ppc->ppc_avm = chipset_mode; } if (bootverbose) printf("\n"); ppc->ppc_type = PPC_TYPE_GENERIC; ppc_generic_setmode(ppc, chipset_mode); return(chipset_mode); } return(-1); } /* * ppc_smc37c66xgt_detect * * SMC FDC37C66xGT configuration. */ static int ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) { int s, i; u_char r; int type = -1; int csr = SMC66x_CSR; /* initial value is 0x3F0 */ int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ /* * Detection: enter configuration mode and read CRD register. */ s = splhigh(); outb(csr, SMC665_iCODE); outb(csr, SMC665_iCODE); splx(s); outb(csr, 0xd); if (inb(cio) == 0x65) { type = SMC_37C665GT; goto config; } for (i = 0; i < 2; i++) { s = splhigh(); outb(csr, SMC666_iCODE); outb(csr, SMC666_iCODE); splx(s); outb(csr, 0xd); if (inb(cio) == 0x66) { type = SMC_37C666GT; break; } /* Another chance, CSR may be hard-configured to be at 0x370 */ csr = SMC666_CSR; } config: /* * If chipset not found, do not continue. */ if (type == -1) return (-1); /* select CR1 */ outb(csr, 0x1); /* read the port's address: bits 0 and 1 of CR1 */ r = inb(cio) & SMC_CR1_ADDR; if (port_address[(int)r] != ppc->ppc_base) return (-1); ppc->ppc_model = type; /* * CR1 and CR4 registers bits 3 and 0/1 for mode configuration * If SPP mode is detected, try to set ECP+EPP mode */ if (bootverbose) { outb(csr, 0x1); printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, inb(cio) & 0xff); outb(csr, 0x4); printf(" CR4=0x%x", inb(cio) & 0xff); } /* select CR1 */ outb(csr, 0x1); if (!chipset_mode) { /* autodetect mode */ /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ if (type == SMC_37C666GT) { ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; if (bootverbose) printf(" configuration hardwired, supposing " \ "ECP+EPP SPP"); } else if ((inb(cio) & SMC_CR1_MODE) == 0) { /* already in extended parallel port mode, read CR4 */ outb(csr, 0x4); r = (inb(cio) & SMC_CR4_EMODE); switch (r) { case SMC_SPP: ppc->ppc_avm |= PPB_SPP; if (bootverbose) printf(" SPP"); break; case SMC_EPPSPP: ppc->ppc_avm |= PPB_EPP | PPB_SPP; if (bootverbose) printf(" EPP SPP"); break; case SMC_ECP: ppc->ppc_avm |= PPB_ECP | PPB_SPP; if (bootverbose) printf(" ECP SPP"); break; case SMC_ECPEPP: ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; if (bootverbose) printf(" ECP+EPP SPP"); break; } } else { /* not an extended port mode */ ppc->ppc_avm |= PPB_SPP; if (bootverbose) printf(" SPP"); } } else { /* mode forced */ ppc->ppc_avm = chipset_mode; /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ if (type == SMC_37C666GT) goto end_detect; r = inb(cio); if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { /* do not use ECP when the mode is not forced to */ outb(cio, r | SMC_CR1_MODE); if (bootverbose) printf(" SPP"); } else { /* an extended mode is selected */ outb(cio, r & ~SMC_CR1_MODE); /* read CR4 register and reset mode field */ outb(csr, 0x4); r = inb(cio) & ~SMC_CR4_EMODE; if (chipset_mode & PPB_ECP) { if (chipset_mode & PPB_EPP) { outb(cio, r | SMC_ECPEPP); if (bootverbose) printf(" ECP+EPP"); } else { outb(cio, r | SMC_ECP); if (bootverbose) printf(" ECP"); } } else { /* PPB_EPP is set */ outb(cio, r | SMC_EPPSPP); if (bootverbose) printf(" EPP SPP"); } } ppc->ppc_avm = chipset_mode; } /* set FIFO threshold to 16 */ if (ppc->ppc_avm & PPB_ECP) { /* select CRA */ outb(csr, 0xa); outb(cio, 16); } end_detect: if (bootverbose) printf ("\n"); if (ppc->ppc_avm & PPB_EPP) { /* select CR4 */ outb(csr, 0x4); r = inb(cio); /* * Set the EPP protocol... * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 */ if (ppc->ppc_epp == EPP_1_9) outb(cio, (r & ~SMC_CR4_EPPTYPE)); else outb(cio, (r | SMC_CR4_EPPTYPE)); } /* end config mode */ outb(csr, 0xaa); ppc->ppc_type = PPC_TYPE_SMCLIKE; ppc_smclike_setmode(ppc, chipset_mode); return (chipset_mode); } /* * SMC FDC37C935 configuration * Found on many Alpha machines */ static int ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) { int s; int type = -1; s = splhigh(); outb(SMC935_CFG, 0x55); /* enter config mode */ outb(SMC935_CFG, 0x55); splx(s); outb(SMC935_IND, SMC935_ID); /* check device id */ if (inb(SMC935_DAT) == 0x2) type = SMC_37C935; if (type == -1) { outb(SMC935_CFG, 0xaa); /* exit config mode */ return (-1); } ppc->ppc_model = type; outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ outb(SMC935_DAT, 3); /* which is logical device 3 */ /* set io port base */ outb(SMC935_IND, SMC935_PORTHI); outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); outb(SMC935_IND, SMC935_PORTLO); outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); if (!chipset_mode) ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ else { ppc->ppc_avm = chipset_mode; outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ /* SPP + EPP or just plain SPP */ if (chipset_mode & (PPB_SPP)) { if (chipset_mode & PPB_EPP) { if (ppc->ppc_epp == EPP_1_9) { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_EPP19SPP); } if (ppc->ppc_epp == EPP_1_7) { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_EPP17SPP); } } else { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_SPP); } } /* ECP + EPP or just plain ECP */ if (chipset_mode & PPB_ECP) { if (chipset_mode & PPB_EPP) { if (ppc->ppc_epp == EPP_1_9) { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_ECPEPP19); } if (ppc->ppc_epp == EPP_1_7) { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_ECPEPP17); } } else { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_ECP); } } } outb(SMC935_CFG, 0xaa); /* exit config mode */ ppc->ppc_type = PPC_TYPE_SMCLIKE; ppc_smclike_setmode(ppc, chipset_mode); return (chipset_mode); } /* * Winbond W83877F stuff * * EFER: extended function enable register * EFIR: extended function index register * EFDR: extended function data register */ #define efir ((efer == 0x250) ? 0x251 : 0x3f0) #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; static int w83877f_keyiter[] = { 1, 2, 2, 1 }; static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; static int ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) { int i, j, efer; unsigned char r, hefere, hefras; for (i = 0; i < 4; i ++) { /* first try to enable configuration registers */ efer = w83877f_efers[i]; /* write the key to the EFER */ for (j = 0; j < w83877f_keyiter[i]; j ++) outb (efer, w83877f_keys[i]); /* then check HEFERE and HEFRAS bits */ outb (efir, 0x0c); hefere = inb(efdr) & WINB_HEFERE; outb (efir, 0x16); hefras = inb(efdr) & WINB_HEFRAS; /* * HEFRAS HEFERE * 0 1 write 89h to 250h (power-on default) * 1 0 write 86h twice to 3f0h * 1 1 write 87h twice to 3f0h * 0 0 write 88h to 250h */ if ((hefere | hefras) == w83877f_hefs[i]) goto found; } return (-1); /* failed */ found: /* check base port address - read from CR23 */ outb(efir, 0x23); if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ return (-1); /* read CHIP ID from CR9/bits0-3 */ outb(efir, 0x9); switch (inb(efdr) & WINB_CHIPID) { case WINB_W83877F_ID: ppc->ppc_model = WINB_W83877F; break; case WINB_W83877AF_ID: ppc->ppc_model = WINB_W83877AF; break; default: ppc->ppc_model = WINB_UNKNOWN; } if (bootverbose) { /* dump of registers */ printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); for (i = 0; i <= 0xd; i ++) { outb(efir, i); printf("0x%x ", inb(efdr)); } for (i = 0x10; i <= 0x17; i ++) { outb(efir, i); printf("0x%x ", inb(efdr)); } outb(efir, 0x1e); printf("0x%x ", inb(efdr)); for (i = 0x20; i <= 0x29; i ++) { outb(efir, i); printf("0x%x ", inb(efdr)); } printf("\n"); printf("ppc%d:", ppc->ppc_unit); } ppc->ppc_type = PPC_TYPE_GENERIC; if (!chipset_mode) { /* autodetect mode */ /* select CR0 */ outb(efir, 0x0); r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); /* select CR9 */ outb(efir, 0x9); r |= (inb(efdr) & WINB_PRTMODS2); switch (r) { case WINB_W83757: if (bootverbose) printf("ppc%d: W83757 compatible mode\n", ppc->ppc_unit); return (-1); /* generic or SMC-like */ case WINB_EXTFDC: case WINB_EXTADP: case WINB_EXT2FDD: case WINB_JOYSTICK: if (bootverbose) printf(" not in parallel port mode\n"); return (-1); case (WINB_PARALLEL | WINB_EPP_SPP): ppc->ppc_avm |= PPB_EPP | PPB_SPP; if (bootverbose) printf(" EPP SPP"); break; case (WINB_PARALLEL | WINB_ECP): ppc->ppc_avm |= PPB_ECP | PPB_SPP; if (bootverbose) printf(" ECP SPP"); break; case (WINB_PARALLEL | WINB_ECP_EPP): ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; ppc->ppc_type = PPC_TYPE_SMCLIKE; if (bootverbose) printf(" ECP+EPP SPP"); break; default: printf("%s: unknown case (0x%x)!\n", __func__, r); } } else { /* mode forced */ /* select CR9 and set PRTMODS2 bit */ outb(efir, 0x9); outb(efdr, inb(efdr) & ~WINB_PRTMODS2); /* select CR0 and reset PRTMODSx bits */ outb(efir, 0x0); outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); if (chipset_mode & PPB_ECP) { if (chipset_mode & PPB_EPP) { outb(efdr, inb(efdr) | WINB_ECP_EPP); if (bootverbose) printf(" ECP+EPP"); ppc->ppc_type = PPC_TYPE_SMCLIKE; } else { outb(efdr, inb(efdr) | WINB_ECP); if (bootverbose) printf(" ECP"); } } else { /* select EPP_SPP otherwise */ outb(efdr, inb(efdr) | WINB_EPP_SPP); if (bootverbose) printf(" EPP SPP"); } ppc->ppc_avm = chipset_mode; } if (bootverbose) printf("\n"); /* exit configuration mode */ outb(efer, 0xaa); switch (ppc->ppc_type) { case PPC_TYPE_SMCLIKE: ppc_smclike_setmode(ppc, chipset_mode); break; default: ppc_generic_setmode(ppc, chipset_mode); break; } return (chipset_mode); } #endif /* * ppc_generic_detect */ static int ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) { /* default to generic */ ppc->ppc_type = PPC_TYPE_GENERIC; if (bootverbose) printf("ppc%d:", ppc->ppc_unit); /* first, check for ECP */ w_ecr(ppc, PPC_ECR_PS2); if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { ppc->ppc_dtm |= PPB_ECP | PPB_SPP; if (bootverbose) printf(" ECP SPP"); /* search for SMC style ECP+EPP mode */ w_ecr(ppc, PPC_ECR_EPP); } /* try to reset EPP timeout bit */ if (ppc_check_epp_timeout(ppc)) { ppc->ppc_dtm |= PPB_EPP; if (ppc->ppc_dtm & PPB_ECP) { /* SMC like chipset found */ ppc->ppc_model = SMC_LIKE; ppc->ppc_type = PPC_TYPE_SMCLIKE; if (bootverbose) printf(" ECP+EPP"); } else { if (bootverbose) printf(" EPP"); } } else { /* restore to standard mode */ w_ecr(ppc, PPC_ECR_STD); } /* XXX try to detect NIBBLE and PS2 modes */ ppc->ppc_dtm |= PPB_NIBBLE; if (bootverbose) printf(" SPP"); if (chipset_mode) ppc->ppc_avm = chipset_mode; else ppc->ppc_avm = ppc->ppc_dtm; if (bootverbose) printf("\n"); switch (ppc->ppc_type) { case PPC_TYPE_SMCLIKE: ppc_smclike_setmode(ppc, chipset_mode); break; default: ppc_generic_setmode(ppc, chipset_mode); break; } return (chipset_mode); } /* * ppc_detect() * * mode is the mode suggested at boot */ static int ppc_detect(struct ppc_data *ppc, int chipset_mode) { #ifdef PPC_PROBE_CHIPSET int i, mode; /* list of supported chipsets */ int (*chipset_detect[])(struct ppc_data *, int) = { ppc_pc873xx_detect, ppc_smc37c66xgt_detect, ppc_w83877f_detect, ppc_smc37c935_detect, ppc_generic_detect, NULL }; #endif /* if can't find the port and mode not forced return error */ if (!ppc_detect_port(ppc) && chipset_mode == 0) return (EIO); /* failed, port not present */ /* assume centronics compatible mode is supported */ ppc->ppc_avm = PPB_COMPATIBLE; #ifdef PPC_PROBE_CHIPSET /* we have to differenciate available chipset modes, * chipset running modes and IEEE-1284 operating modes * * after detection, the port must support running in compatible mode */ if (ppc->ppc_flags & 0x40) { if (bootverbose) printf("ppc: chipset forced to generic\n"); #endif ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); #ifdef PPC_PROBE_CHIPSET } else { for (i=0; chipset_detect[i] != NULL; i++) { if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { ppc->ppc_mode = mode; break; } } } #endif /* configure/detect ECP FIFO */ if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) ppc_detect_fifo(ppc); return (0); } /* * ppc_exec_microseq() * * Execute a microsequence. * Microsequence mechanism is supposed to handle fast I/O operations. */ int ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) { struct ppc_data *ppc = DEVTOSOFTC(dev); struct ppb_microseq *mi; char cc, *p; int i, iter, len; int error; register int reg; register char mask; register int accum = 0; register char *ptr = 0; struct ppb_microseq *stack = 0; /* microsequence registers are equivalent to PC-like port registers */ #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register)) #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte)) #define INCR_PC (mi ++) /* increment program counter */ mi = *p_msq; for (;;) { switch (mi->opcode) { case MS_OP_RSET: cc = r_reg(mi->arg[0].i, ppc); cc &= (char)mi->arg[2].i; /* clear mask */ cc |= (char)mi->arg[1].i; /* assert mask */ w_reg(mi->arg[0].i, ppc, cc); INCR_PC; break; case MS_OP_RASSERT_P: reg = mi->arg[1].i; ptr = ppc->ppc_ptr; if ((len = mi->arg[0].i) == MS_ACCUM) { accum = ppc->ppc_accum; for (; accum; accum--) w_reg(reg, ppc, *ptr++); ppc->ppc_accum = accum; } else for (i=0; ippc_ptr = ptr; INCR_PC; break; case MS_OP_RFETCH_P: reg = mi->arg[1].i; mask = (char)mi->arg[2].i; ptr = ppc->ppc_ptr; if ((len = mi->arg[0].i) == MS_ACCUM) { accum = ppc->ppc_accum; for (; accum; accum--) *ptr++ = r_reg(reg, ppc) & mask; ppc->ppc_accum = accum; } else for (i=0; ippc_ptr = ptr; INCR_PC; break; case MS_OP_RFETCH: *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & (char)mi->arg[1].i; INCR_PC; break; case MS_OP_RASSERT: case MS_OP_DELAY: /* let's suppose the next instr. is the same */ prefetch: for (;mi->opcode == MS_OP_RASSERT; INCR_PC) w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); if (mi->opcode == MS_OP_DELAY) { DELAY(mi->arg[0].i); INCR_PC; goto prefetch; } break; case MS_OP_ADELAY: if (mi->arg[0].i) tsleep(NULL, PPBPRI, "ppbdelay", mi->arg[0].i * (hz/1000)); INCR_PC; break; case MS_OP_TRIG: reg = mi->arg[0].i; iter = mi->arg[1].i; p = (char *)mi->arg[2].p; /* XXX delay limited to 255 us */ for (i=0; ippc_accum = mi->arg[0].i; INCR_PC; break; case MS_OP_DBRA: if (--ppc->ppc_accum > 0) mi += mi->arg[0].i; INCR_PC; break; case MS_OP_BRSET: cc = r_str(ppc); if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) mi += mi->arg[1].i; INCR_PC; break; case MS_OP_BRCLEAR: cc = r_str(ppc); if ((cc & (char)mi->arg[0].i) == 0) mi += mi->arg[1].i; INCR_PC; break; case MS_OP_BRSTAT: cc = r_str(ppc); if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == (char)mi->arg[0].i) mi += mi->arg[2].i; INCR_PC; break; case MS_OP_C_CALL: /* * If the C call returns !0 then end the microseq. * The current state of ptr is passed to the C function */ if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) return (error); INCR_PC; break; case MS_OP_PTR: ppc->ppc_ptr = (char *)mi->arg[0].p; INCR_PC; break; case MS_OP_CALL: if (stack) panic("%s: too much calls", __func__); if (mi->arg[0].p) { /* store the state of the actual * microsequence */ stack = mi; /* jump to the new microsequence */ mi = (struct ppb_microseq *)mi->arg[0].p; } else INCR_PC; break; case MS_OP_SUBRET: /* retrieve microseq and pc state before the call */ mi = stack; /* reset the stack */ stack = 0; /* XXX return code */ INCR_PC; break; case MS_OP_PUT: case MS_OP_GET: case MS_OP_RET: /* can't return to ppb level during the execution * of a submicrosequence */ if (stack) panic("%s: can't return to ppb level", __func__); /* update pc for ppb level of execution */ *p_msq = mi; /* return to ppb level of execution */ return (0); default: panic("%s: unknown microsequence opcode 0x%x", __func__, mi->opcode); } } /* unreached */ } static void ppcintr(void *arg) { device_t dev = (device_t)arg; struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); u_char ctr, ecr, str; str = r_str(ppc); ctr = r_ctr(ppc); ecr = r_ecr(ppc); #if PPC_DEBUG > 1 printf("![%x/%x/%x]", ctr, ecr, str); #endif /* don't use ecp mode with IRQENABLE set */ if (ctr & IRQENABLE) { return; } /* interrupts are generated by nFault signal * only in ECP mode */ if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { /* check if ppc driver has programmed the * nFault interrupt */ if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { w_ecr(ppc, ecr | PPC_nFAULT_INTR); ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; } else { /* shall be handled by underlying layers XXX */ return; } } if (ppc->ppc_irqstat & PPC_IRQ_DMA) { /* disable interrupts (should be done by hardware though) */ w_ecr(ppc, ecr | PPC_SERVICE_INTR); ppc->ppc_irqstat &= ~PPC_IRQ_DMA; ecr = r_ecr(ppc); /* check if DMA completed */ if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { #ifdef PPC_DEBUG printf("a"); #endif /* stop DMA */ w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); ecr = r_ecr(ppc); if (ppc->ppc_dmastat == PPC_DMA_STARTED) { #ifdef PPC_DEBUG printf("d"); #endif isa_dmadone( ppc->ppc_dmaflags, ppc->ppc_dmaddr, ppc->ppc_dmacnt, ppc->ppc_dmachan); ppc->ppc_dmastat = PPC_DMA_COMPLETE; /* wakeup the waiting process */ wakeup(ppc); } } } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { /* classic interrupt I/O */ ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; } return; } int ppc_read(device_t dev, char *buf, int len, int mode) { return (EINVAL); } /* * Call this function if you want to send data in any advanced mode * of your parallel port: FIFO, DMA * * If what you want is not possible (no ECP, no DMA...), * EINVAL is returned */ int ppc_write(device_t dev, char *buf, int len, int how) { struct ppc_data *ppc = DEVTOSOFTC(dev); char ecr, ecr_sav, ctr, ctr_sav; int s, error = 0; int spin; #ifdef PPC_DEBUG printf("w"); #endif ecr_sav = r_ecr(ppc); ctr_sav = r_ctr(ppc); /* * Send buffer with DMA, FIFO and interrupts */ if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { if (ppc->ppc_dmachan > 0) { /* byte mode, no intr, no DMA, dir=0, flush fifo */ ecr = PPC_ECR_STD | PPC_DISABLE_INTR; w_ecr(ppc, ecr); /* disable nAck interrupts */ ctr = r_ctr(ppc); ctr &= ~IRQENABLE; w_ctr(ppc, ctr); ppc->ppc_dmaflags = 0; ppc->ppc_dmaddr = (caddr_t)buf; ppc->ppc_dmacnt = (u_int)len; switch (ppc->ppc_mode) { case PPB_COMPATIBLE: /* compatible mode with FIFO, no intr, DMA, dir=0 */ ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; break; case PPB_ECP: ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; break; default: error = EINVAL; goto error; } w_ecr(ppc, ecr); ecr = r_ecr(ppc); /* enter splhigh() not to be preempted * by the dma interrupt, we may miss * the wakeup otherwise */ s = splhigh(); ppc->ppc_dmastat = PPC_DMA_INIT; /* enable interrupts */ ecr &= ~PPC_SERVICE_INTR; ppc->ppc_irqstat = PPC_IRQ_DMA; w_ecr(ppc, ecr); isa_dmastart( ppc->ppc_dmaflags, ppc->ppc_dmaddr, ppc->ppc_dmacnt, ppc->ppc_dmachan); #ifdef PPC_DEBUG printf("s%d", ppc->ppc_dmacnt); #endif ppc->ppc_dmastat = PPC_DMA_STARTED; /* Wait for the DMA completed interrupt. We hope we won't * miss it, otherwise a signal will be necessary to unlock the * process. */ do { /* release CPU */ error = tsleep(ppc, PPBPRI | PCATCH, "ppcdma", 0); } while (error == EWOULDBLOCK); splx(s); if (error) { #ifdef PPC_DEBUG printf("i"); #endif /* stop DMA */ isa_dmadone( ppc->ppc_dmaflags, ppc->ppc_dmaddr, ppc->ppc_dmacnt, ppc->ppc_dmachan); /* no dma, no interrupt, flush the fifo */ w_ecr(ppc, PPC_ECR_RESET); ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; goto error; } /* wait for an empty fifo */ while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { for (spin=100; spin; spin--) if (r_ecr(ppc) & PPC_FIFO_EMPTY) goto fifo_empty; #ifdef PPC_DEBUG printf("Z"); #endif error = tsleep(ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); if (error != EWOULDBLOCK) { #ifdef PPC_DEBUG printf("I"); #endif /* no dma, no interrupt, flush the fifo */ w_ecr(ppc, PPC_ECR_RESET); ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; error = EINTR; goto error; } } fifo_empty: /* no dma, no interrupt, flush the fifo */ w_ecr(ppc, PPC_ECR_RESET); } else error = EINVAL; /* XXX we should FIFO and * interrupts */ } else error = EINVAL; error: /* PDRQ must be kept unasserted until nPDACK is * deasserted for a minimum of 350ns (SMC datasheet) * * Consequence may be a FIFO that never empty */ DELAY(1); w_ecr(ppc, ecr_sav); w_ctr(ppc, ctr_sav); return (error); } void ppc_reset_epp(device_t dev) { struct ppc_data *ppc = DEVTOSOFTC(dev); ppc_reset_epp_timeout(ppc); return; } int ppc_setmode(device_t dev, int mode) { struct ppc_data *ppc = DEVTOSOFTC(dev); switch (ppc->ppc_type) { case PPC_TYPE_SMCLIKE: return (ppc_smclike_setmode(ppc, mode)); break; case PPC_TYPE_GENERIC: default: return (ppc_generic_setmode(ppc, mode)); break; } /* not reached */ return (ENXIO); } static struct isa_pnp_id lpc_ids[] = { { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */ { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */ { 0 } }; static int ppc_cbus_probe(device_t dev) { device_t parent; int error; parent = device_get_parent(dev); error = ISA_PNP_PROBE(parent, dev, lpc_ids); if (error == ENXIO) return (ENXIO); else if (error != 0) /* XXX shall be set after detection */ device_set_desc(dev, "Parallel port"); return(ppc_probe(dev)); } int ppc_probe(device_t dev) { #ifdef __i386__ static short next_bios_ppc = 0; #endif struct ppc_data *ppc; int error; u_long port; #ifdef PC98 #define PC98_IEEE_1284_DISABLE 0x100 #define PC98_IEEE_1284_PORT 0x140 unsigned int pc98_ieee_mode = 0x00; unsigned int tmp; #endif /* * Allocate the ppc_data structure. */ ppc = DEVTOSOFTC(dev); bzero(ppc, sizeof(struct ppc_data)); ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; /* retrieve ISA parameters */ error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL); #ifdef __i386__ /* * If port not specified, use bios list. */ if (error) { #ifndef PC98 if((next_bios_ppc < BIOS_MAX_PPC) && (*(BIOS_PORTS+next_bios_ppc) != 0) ) { port = *(BIOS_PORTS+next_bios_ppc++); if (bootverbose) device_printf(dev, "parallel port found at 0x%x\n", (int) port); } else { device_printf(dev, "parallel port not found.\n"); return ENXIO; } #else if (next_bios_ppc == 0) { /* Use default IEEE-1284 port of NEC PC-98x1 */ port = PC98_IEEE_1284_PORT; next_bios_ppc += 1; if (bootverbose) device_printf(dev, "parallel port found at 0x%x\n", (int) port); } #endif bus_set_resource(dev, SYS_RES_IOPORT, 0, port, IO_LPTSIZE_EXTENDED); } #endif #ifdef __alpha__ /* * There isn't a bios list on alpha. Put it in the usual place. */ if (error) { bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc, IO_LPTSIZE_NORMAL); } #endif /* IO port is mandatory */ /* Try "extended" IO port range...*/ ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, &ppc->rid_ioport, 0, ~0, IO_LPTSIZE_EXTENDED, RF_ACTIVE); if (ppc->res_ioport != 0) { if (bootverbose) device_printf(dev, "using extended I/O port range\n"); } else { /* Failed? If so, then try the "normal" IO port range... */ ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, &ppc->rid_ioport, 0, ~0, IO_LPTSIZE_NORMAL, RF_ACTIVE); if (ppc->res_ioport != 0) { if (bootverbose) device_printf(dev, "using normal I/O port range\n"); } else { device_printf(dev, "cannot reserve I/O port range\n"); goto error; } } ppc->ppc_base = rman_get_start(ppc->res_ioport); ppc->bsh = rman_get_bushandle(ppc->res_ioport); ppc->bst = rman_get_bustag(ppc->res_ioport); ppc->ppc_flags = device_get_flags(dev); if (!(ppc->ppc_flags & 0x20)) { ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &ppc->rid_irq, RF_SHAREABLE); ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, &ppc->rid_drq, RF_ACTIVE); } if (ppc->res_irq) ppc->ppc_irq = rman_get_start(ppc->res_irq); if (ppc->res_drq) ppc->ppc_dmachan = rman_get_start(ppc->res_drq); ppc->ppc_unit = device_get_unit(dev); ppc->ppc_model = GENERIC; ppc->ppc_mode = PPB_COMPATIBLE; ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; ppc->ppc_type = PPC_TYPE_GENERIC; #ifdef PC98 /* * IEEE STD 1284 Function Check and Enable * for default IEEE-1284 port of NEC PC-98x1 */ if ((ppc->ppc_base == PC98_IEEE_1284_PORT) && !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); pc98_ieee_mode = tmp; if ((tmp & 0x10) == 0x10) { outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10); tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); if ((tmp & 0x10) == 0x10) goto error; } else { outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10); tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); if ((tmp & 0x10) != 0x10) goto error; } outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10); } #endif /* * Try to detect the chipset and its mode. */ if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) goto error; return (0); error: #ifdef PC98 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) && !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode); } #endif if (ppc->res_irq != 0) { bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, ppc->res_irq); } if (ppc->res_ioport != 0) { bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, ppc->res_ioport); bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, ppc->res_ioport); } if (ppc->res_drq != 0) { bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, ppc->res_drq); bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, ppc->res_drq); } return (ENXIO); } int ppc_attach(device_t dev) { struct ppc_data *ppc = DEVTOSOFTC(dev); device_t ppbus; device_t parent = device_get_parent(dev); device_printf(dev, "%s chipset (%s) in %s mode%s\n", ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? ppc_epp_protocol[ppc->ppc_epp] : ""); if (ppc->ppc_fifo) device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { /* acquire the DMA channel forever */ /* XXX */ isa_dma_acquire(ppc->ppc_dmachan); isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ } /* add ppbus as a child of this isa to parallel bridge */ ppbus = device_add_child(dev, "ppbus", -1); /* * Probe the ppbus and attach devices found. */ device_probe_and_attach(ppbus); /* register the ppc interrupt handler as default */ if (ppc->res_irq) { /* default to the tty mask for registration */ /* XXX */ if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, ppcintr, dev, &ppc->intr_cookie) == 0) { /* remember the ppcintr is registered */ ppc->ppc_registered = 1; } } return (0); } u_char ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) { struct ppc_data *ppc = DEVTOSOFTC(ppcdev); switch (iop) { case PPB_OUTSB_EPP: bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); break; case PPB_OUTSW_EPP: bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); break; case PPB_OUTSL_EPP: bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); break; case PPB_INSB_EPP: bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); break; case PPB_INSW_EPP: bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); break; case PPB_INSL_EPP: bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); break; case PPB_RDTR: return (r_dtr(ppc)); case PPB_RSTR: return (r_str(ppc)); case PPB_RCTR: return (r_ctr(ppc)); case PPB_REPP_A: return (r_epp_A(ppc)); case PPB_REPP_D: return (r_epp_D(ppc)); case PPB_RECR: return (r_ecr(ppc)); case PPB_RFIFO: return (r_fifo(ppc)); case PPB_WDTR: w_dtr(ppc, byte); break; case PPB_WSTR: w_str(ppc, byte); break; case PPB_WCTR: w_ctr(ppc, byte); break; case PPB_WEPP_A: w_epp_A(ppc, byte); break; case PPB_WEPP_D: w_epp_D(ppc, byte); break; case PPB_WECR: w_ecr(ppc, byte); break; case PPB_WFIFO: w_fifo(ppc, byte); break; default: panic("%s: unknown I/O operation", __func__); break; } return (0); /* not significative */ } int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) { struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); switch (index) { case PPC_IVAR_EPP_PROTO: *val = (u_long)ppc->ppc_epp; break; case PPC_IVAR_IRQ: *val = (u_long)ppc->ppc_irq; break; default: return (ENOENT); } return (0); } /* * Resource is useless here since ppbus devices' interrupt handlers are * multiplexed to the same resource initially allocated by ppc */ int ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, void (*ihand)(void *), void *arg, void **cookiep) { int error; struct ppc_data *ppc = DEVTOSOFTC(bus); if (ppc->ppc_registered) { /* XXX refuse registration if DMA is in progress */ /* first, unregister the default interrupt handler */ if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), bus, ppc->res_irq, ppc->intr_cookie))) return (error); /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ /* ppc->res_irq); */ /* DMA/FIFO operation won't be possible anymore */ ppc->ppc_registered = 0; } /* pass registration to the upper layer, ignore the incoming resource */ return (BUS_SETUP_INTR(device_get_parent(bus), child, r, flags, ihand, arg, cookiep)); } /* * When no underlying device has a registered interrupt, register the ppc * layer one */ int ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) { int error; struct ppc_data *ppc = DEVTOSOFTC(bus); device_t parent = device_get_parent(bus); /* pass unregistration to the upper layer */ if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) return (error); /* default to the tty mask for registration */ /* XXX */ if (ppc->ppc_irq && !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) { /* remember the ppcintr is registered */ ppc->ppc_registered = 1; } return (error); } DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); #ifndef PC98 DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, 0, 0); #endif Index: head/sys/pc98/pc98/clock.c =================================================================== --- head/sys/pc98/pc98/clock.c (revision 130173) +++ head/sys/pc98/pc98/clock.c (revision 130174) @@ -1,1018 +1,1019 @@ /*- * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. * * This code is derived from software contributed to Berkeley by * William Jolitz and Don Ahn. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 * $FreeBSD$ */ /* * Routines to handle clock hardware. */ /* * inittodr, settodr and support routines written * by Christoph Robitschko * * reintroduced and updated by Chris Stenton 8/10/94 */ /* * modified for PC98 by Kakefuda */ #include "opt_clock.h" #include "opt_isa.h" #include "opt_mca.h" #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(SMP) #include #endif #include #include #include #include #ifdef DEV_ISA #include #endif #include /* * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we * can use a simple formula for leap years. */ #define LEAPYEAR(y) (((u_int)(y) % 4 == 0) ? 1 : 0) #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) #ifndef BURN_BRIDGES /* * Time in timer cycles that it takes for microtime() to disable interrupts * and latch the count. microtime() currently uses "cli; outb ..." so it * normally takes less than 2 timer cycles. Add a few for cache misses. * Add a few more to allow for latency in bogus calls to microtime() with * interrupts already disabled. */ #define TIMER0_LATCH_COUNT 20 /* * Maximum frequency that we are willing to allow for timer0. Must be * low enough to guarantee that the timer interrupt handler returns * before the next timer interrupt. */ #define TIMER0_MAX_FREQ 20000 #endif int adjkerntz; /* local offset from GMT in seconds */ int clkintr_pending; int disable_rtc_set; /* disable resettodr() if != 0 */ int pscnt = 1; int psdiv = 1; int statclock_disable; #ifndef TIMER_FREQ #define TIMER_FREQ 2457600 #endif u_int timer_freq = TIMER_FREQ; int timer0_max_count; int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ struct mtx clock_lock; static int beeping = 0; static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; static u_int hardclock_max_count; static u_int32_t i8254_lastcount; static u_int32_t i8254_offset; static int i8254_ticked; static struct intsrc *i8254_intsrc; #ifndef BURN_BRIDGES /* * XXX new_function and timer_func should not handle clockframes, but * timer_func currently needs to hold hardclock to handle the * timer0_state == 0 case. We should use inthand_add()/inthand_remove() * to switch between clkintr() and a slightly different timerintr(). */ static void (*new_function)(struct clockframe *frame); static u_int new_rate; static u_int timer0_prescaler_count; static u_char timer0_state; #endif /* Values for timerX_state: */ #define RELEASED 0 #define RELEASE_PENDING 1 #define ACQUIRED 2 #define ACQUIRE_PENDING 3 static u_char timer1_state; static u_char timer2_state; static void (*timer_func)(struct clockframe *frame) = hardclock; static void rtc_serialcombit(int); static void rtc_serialcom(int); static int rtc_inb(void); static void rtc_outb(int); static unsigned i8254_get_timecount(struct timecounter *tc); static void set_timer_freq(u_int freq, int intr_freq); static struct timecounter i8254_timecounter = { i8254_get_timecount, /* get_timecount */ 0, /* no poll_pps */ ~0u, /* counter_mask */ 0, /* frequency */ "i8254", /* name */ 0 /* quality */ }; static void clkintr(struct clockframe *frame) { if (timecounter->tc_get_timecount == i8254_get_timecount) { mtx_lock_spin(&clock_lock); if (i8254_ticked) i8254_ticked = 0; else { i8254_offset += timer0_max_count; i8254_lastcount = 0; } clkintr_pending = 0; mtx_unlock_spin(&clock_lock); } timer_func(frame); #ifdef SMP if (timer_func == hardclock) forward_hardclock(); #endif #ifndef BURN_BRIDGES switch (timer0_state) { case RELEASED: break; case ACQUIRED: if ((timer0_prescaler_count += timer0_max_count) >= hardclock_max_count) { timer0_prescaler_count -= hardclock_max_count; hardclock(frame); #ifdef SMP forward_hardclock(); #endif } break; case ACQUIRE_PENDING: mtx_lock_spin(&clock_lock); i8254_offset = i8254_get_timecount(NULL); i8254_lastcount = 0; timer0_max_count = TIMER_DIV(new_rate); outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); timer_func = new_function; timer0_state = ACQUIRED; break; case RELEASE_PENDING: if ((timer0_prescaler_count += timer0_max_count) >= hardclock_max_count) { mtx_lock_spin(&clock_lock); i8254_offset = i8254_get_timecount(NULL); i8254_lastcount = 0; timer0_max_count = hardclock_max_count; outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); timer0_prescaler_count = 0; timer_func = hardclock; timer0_state = RELEASED; hardclock(frame); #ifdef SMP forward_hardclock(); #endif } break; } #endif } #ifndef BURN_BRIDGES /* * The acquire and release functions must be called at ipl >= splclock(). */ int acquire_timer0(int rate, void (*function)(struct clockframe *frame)) { static int old_rate; if (rate <= 0 || rate > TIMER0_MAX_FREQ) return (-1); switch (timer0_state) { case RELEASED: timer0_state = ACQUIRE_PENDING; break; case RELEASE_PENDING: if (rate != old_rate) return (-1); /* * The timer has been released recently, but is being * re-acquired before the release completed. In this * case, we simply reclaim it as if it had not been * released at all. */ timer0_state = ACQUIRED; break; default: return (-1); /* busy */ } new_function = function; old_rate = new_rate = rate; return (0); } #endif int acquire_timer1(int mode) { if (timer1_state != RELEASED) return (-1); timer1_state = ACQUIRED; /* * This access to the timer registers is as atomic as possible * because it is a single instruction. We could do better if we * knew the rate. Use of splclock() limits glitches to 10-100us, * and this is probably good enough for timer2, so we aren't as * careful with it as with timer0. */ outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); return (0); } int acquire_timer2(int mode) { if (timer2_state != RELEASED) return (-1); timer2_state = ACQUIRED; /* * This access to the timer registers is as atomic as possible * because it is a single instruction. We could do better if we * knew the rate. Use of splclock() limits glitches to 10-100us, * and this is probably good enough for timer2, so we aren't as * careful with it as with timer0. */ outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); return (0); } #ifndef BURN_BRIDGES int release_timer0() { switch (timer0_state) { case ACQUIRED: timer0_state = RELEASE_PENDING; break; case ACQUIRE_PENDING: /* Nothing happened yet, release quickly. */ timer0_state = RELEASED; break; default: return (-1); } return (0); } #endif int release_timer1() { if (timer1_state != ACQUIRED) return (-1); timer1_state = RELEASED; outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); return (0); } int release_timer2() { if (timer2_state != ACQUIRED) return (-1); timer2_state = RELEASED; outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); return (0); } static int getit(void) { int high, low; mtx_lock_spin(&clock_lock); /* Select timer0 and latch counter value. */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); low = inb(TIMER_CNTR0); high = inb(TIMER_CNTR0); mtx_unlock_spin(&clock_lock); return ((high << 8) | low); } /* * Wait "n" microseconds. * Relies on timer 1 counting down from (timer_freq / hz) * Note: timer had better have been programmed before this is first used! */ void DELAY(int n) { int delta, prev_tick, tick, ticks_left; #ifdef DELAYDEBUG int getit_calls = 1; int n1; static int state = 0; if (state == 0) { state = 1; for (n1 = 1; n1 <= 10000000; n1 *= 10) DELAY(n1); state = 2; } if (state == 1) printf("DELAY(%d)...", n); #endif /* * Guard against the timer being uninitialized if we are called * early for console i/o. */ if (timer0_max_count == 0) set_timer_freq(timer_freq, hz); /* * Read the counter first, so that the rest of the setup overhead is * counted. Guess the initial overhead is 20 usec (on most systems it * takes about 1.5 usec for each of the i/o's in getit(). The loop * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The * multiplications and divisions to scale the count take a while). * * However, if ddb is active then use a fake counter since reading * the i8254 counter involves acquiring a lock. ddb must not go * locking for many reasons, but it calls here for at least atkbd * input. */ #ifdef DDB if (db_active) prev_tick = 0; else #endif prev_tick = getit(); n -= 0; /* XXX actually guess no initial overhead */ /* * Calculate (n * (timer_freq / 1e6)) without using floating point * and without any avoidable overflows. */ if (n <= 0) ticks_left = 0; else if (n < 256) /* * Use fixed point to avoid a slow division by 1000000. * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. * 2^15 is the first power of 2 that gives exact results * for n between 0 and 256. */ ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; else /* * Don't bother using fixed point, although gcc-2.7.2 * generates particularly poor code for the long long * division, since even the slow way will complete long * before the delay is up (unless we're interrupted). */ ticks_left = ((u_int)n * (long long)timer_freq + 999999) / 1000000; while (ticks_left > 0) { #ifdef DDB if (db_active) { outb(0x5f, 0); tick = prev_tick + 1; } else #endif tick = getit(); #ifdef DELAYDEBUG ++getit_calls; #endif delta = prev_tick - tick; prev_tick = tick; if (delta < 0) { delta += timer0_max_count; /* * Guard against timer0_max_count being wrong. * This shouldn't happen in normal operation, * but it may happen if set_timer_freq() is * traced. */ if (delta < 0) delta = 0; } ticks_left -= delta; } #ifdef DELAYDEBUG if (state == 1) printf(" %d calls to getit() at %d usec each\n", getit_calls, (n + 5) / getit_calls); #endif } static void sysbeepstop(void *chan) { outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ release_timer1(); beeping = 0; } int sysbeep(int pitch, int period) { int x = splclock(); if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) if (!beeping) { /* Something else owns it. */ splx(x); return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ } disable_intr(); outb(0x3fdb, pitch); outb(0x3fdb, (pitch>>8)); enable_intr(); if (!beeping) { /* enable counter1 output to speaker */ outb(IO_PPI, (inb(IO_PPI) & 0xf7)); beeping = period; timeout(sysbeepstop, (void *)NULL, period); } splx(x); return (0); } unsigned int delaycount; #define FIRST_GUESS 0x2000 static void findcpuspeed(void) { int i; int remainder; /* Put counter in count down mode */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); outb(TIMER_CNTR0, 0xff); outb(TIMER_CNTR0, 0xff); for (i = FIRST_GUESS; i; i--) ; remainder = getit(); delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); } static u_int calibrate_clocks(void) { int timeout; u_int count, prev_count, tot_count; u_short sec, start_sec; if (bootverbose) printf("Calibrating clock(s) ... "); /* Check ARTIC. */ if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) goto fail; timeout = 100000000; /* Read the ARTIC. */ sec = inw(0x5e); /* Wait for the ARTIC to changes. */ start_sec = sec; for (;;) { sec = inw(0x5e); if (sec != start_sec) break; if (--timeout == 0) goto fail; } prev_count = getit(); if (prev_count == 0 || prev_count > timer0_max_count) goto fail; tot_count = 0; start_sec = sec; for (;;) { sec = inw(0x5e); count = getit(); if (count == 0 || count > timer0_max_count) goto fail; if (count > prev_count) tot_count += prev_count - (count - timer0_max_count); else tot_count += prev_count - count; prev_count = count; if ((sec == start_sec + 1200) || /* 1200 = 307.2KHz >> 8 */ (sec < start_sec && (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) break; if (--timeout == 0) goto fail; } if (bootverbose) { printf("i8254 clock: %u Hz\n", tot_count); } return (tot_count); fail: if (bootverbose) printf("failed, using default i8254 clock of %u Hz\n", timer_freq); return (timer_freq); } static void set_timer_freq(u_int freq, int intr_freq) { int new_timer0_max_count; mtx_lock_spin(&clock_lock); timer_freq = freq; new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); if (new_timer0_max_count != timer0_max_count) { timer0_max_count = new_timer0_max_count; outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); } mtx_unlock_spin(&clock_lock); } static void i8254_restore(void) { mtx_lock_spin(&clock_lock); outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb(TIMER_CNTR0, timer0_max_count & 0xff); outb(TIMER_CNTR0, timer0_max_count >> 8); mtx_unlock_spin(&clock_lock); } /* * Restore all the timers non-atomically (XXX: should be atomically). * * This function is called from pmtimer_resume() to restore all the timers. * This should not be necessary, but there are broken laptops that do not * restore all the timers on resume. */ void timer_restore(void) { i8254_restore(); /* restore timer_freq and hz */ } /* * Initialize 8254 timer 0 early so that it can be used in DELAY(). * XXX initialization of other timers is unintentionally left blank. */ void startrtclock() { u_int delta, freq; findcpuspeed(); if (pc98_machine_type & M_8M) timer_freq = 1996800L; /* 1.9968 MHz */ else timer_freq = 2457600L; /* 2.4576 MHz */ set_timer_freq(timer_freq, hz); freq = calibrate_clocks(); #ifdef CLK_CALIBRATION_LOOP if (bootverbose) { printf( "Press a key on the console to abort clock calibration\n"); while (cncheckc() == -1) calibrate_clocks(); } #endif /* * Use the calibrated i8254 frequency if it seems reasonable. * Otherwise use the default, and don't use the calibrated i586 * frequency. */ delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; if (delta < timer_freq / 100) { #ifndef CLK_USE_I8254_CALIBRATION if (bootverbose) printf( "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); freq = timer_freq; #endif timer_freq = freq; } else { if (bootverbose) printf( "%d Hz differs from default of %d Hz by more than 1%%\n", freq, timer_freq); } set_timer_freq(timer_freq, hz); i8254_timecounter.tc_frequency = timer_freq; tc_init(&i8254_timecounter); init_TSC(); } static void rtc_serialcombit(int i) { outb(IO_RTC, ((i&0x01)<<5)|0x07); DELAY(1); outb(IO_RTC, ((i&0x01)<<5)|0x17); DELAY(1); outb(IO_RTC, ((i&0x01)<<5)|0x07); DELAY(1); } static void rtc_serialcom(int i) { rtc_serialcombit(i&0x01); rtc_serialcombit((i&0x02)>>1); rtc_serialcombit((i&0x04)>>2); rtc_serialcombit((i&0x08)>>3); outb(IO_RTC, 0x07); DELAY(1); outb(IO_RTC, 0x0f); DELAY(1); outb(IO_RTC, 0x07); DELAY(1); } static void rtc_outb(int val) { int s; int sa = 0; for (s=0;s<8;s++) { sa = ((val >> s) & 0x01) ? 0x27 : 0x07; outb(IO_RTC, sa); /* set DI & CLK 0 */ DELAY(1); outb(IO_RTC, sa | 0x10); /* CLK 1 */ DELAY(1); } outb(IO_RTC, sa & 0xef); /* CLK 0 */ } static int rtc_inb(void) { int s; int sa = 0; for (s=0;s<8;s++) { sa |= ((inb(0x33) & 0x01) << s); outb(IO_RTC, 0x17); /* CLK 1 */ DELAY(1); outb(IO_RTC, 0x07); /* CLK 0 */ DELAY(2); } return sa; } /* * Initialize the time of day register, based on the time base which is, e.g. * from a filesystem. */ void inittodr(time_t base) { unsigned long sec, days; int year, month; int y, m, s; struct timespec ts; int second, min, hour; if (base) { s = splclock(); ts.tv_sec = base; ts.tv_nsec = 0; tc_setclock(&ts); splx(s); } rtc_serialcom(0x03); /* Time Read */ rtc_serialcom(0x01); /* Register shift command. */ DELAY(20); second = bcd2bin(rtc_inb() & 0xff); /* sec */ min = bcd2bin(rtc_inb() & 0xff); /* min */ hour = bcd2bin(rtc_inb() & 0xff); /* hour */ days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ month = (rtc_inb() >> 4) & 0x0f; /* month */ for (m = 1; m < month; m++) days += daysinmonth[m-1]; year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ /* 2000 year problem */ if (year < 1995) year += 100; if (year < 1970) goto wrong_time; for (y = 1970; y < year; y++) days += DAYSPERYEAR + LEAPYEAR(y); if ((month > 2) && LEAPYEAR(year)) days ++; sec = ((( days * 24 + hour) * 60 + min) * 60 + second); /* sec now contains the number of seconds, since Jan 1 1970, in the local time zone */ s = splhigh(); sec += tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); y = time_second - sec; if (y <= -2 || y >= 2) { /* badly off, adjust it */ ts.tv_sec = sec; ts.tv_nsec = 0; tc_setclock(&ts); } splx(s); return; wrong_time: printf("Invalid time in real time clock.\n"); printf("Check and reset the date immediately!\n"); } /* * Write system time back to RTC */ void resettodr() { unsigned long tm; int y, m, s; int wd; if (disable_rtc_set) return; s = splclock(); tm = time_second; splx(s); rtc_serialcom(0x01); /* Register shift command. */ /* Calculate local time to put in RTC */ tm -= tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ /* We have now the days since 01-01-1970 in tm */ wd = (tm + 4) % 7 + 1; /* Write back Weekday */ for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); tm >= m; y++, m = DAYSPERYEAR + LEAPYEAR(y)) tm -= m; /* Now we have the years in y and the day-of-the-year in tm */ for (m = 0; ; m++) { int ml; ml = daysinmonth[m]; if (m == 1 && LEAPYEAR(y)) ml++; if (tm < ml) break; tm -= ml; } m++; rtc_outb(bin2bcd(tm+1)); /* Write back Day */ rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ rtc_outb(bin2bcd(y%100)); /* Write back Year */ rtc_serialcom(0x02); /* Time set & Counter hold command. */ rtc_serialcom(0x00); /* Register hold command. */ } /* * Start both clocks running. */ void cpu_initclocks() { /* Finish initializing 8254 timer 0. */ intr_add_handler("clk", 0, (driver_intr_t *)clkintr, NULL, INTR_TYPE_CLK | INTR_FAST, NULL); init_TSC_tc(); } void cpu_startprofclock(void) { } void cpu_stopprofclock(void) { } static int sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) { int error; u_int freq; /* * Use `i8254' instead of `timer' in external names because `timer' * is is too generic. Should use it everywhere. */ freq = timer_freq; error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); if (error == 0 && req->newptr != NULL) { #ifndef BURN_BRIDGES if (timer0_state != RELEASED) return (EBUSY); /* too much trouble to handle */ #endif set_timer_freq(freq, hz); i8254_timecounter.tc_frequency = freq; } return (error); } SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", ""); static unsigned i8254_get_timecount(struct timecounter *tc) { u_int count; u_int high, low; u_int eflags; eflags = read_eflags(); mtx_lock_spin(&clock_lock); /* Select timer0 and latch counter value. */ outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); low = inb(TIMER_CNTR0); high = inb(TIMER_CNTR0); count = timer0_max_count - ((high << 8) | low); if (count < i8254_lastcount || (!i8254_ticked && (clkintr_pending || ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) && i8254_intsrc != NULL && i8254_intsrc->is_pic->pic_source_pending(i8254_intsrc))))) { i8254_ticked = 1; i8254_offset += timer0_max_count; } i8254_lastcount = count; count += i8254_offset; mtx_unlock_spin(&clock_lock); return (count); } #ifdef DEV_ISA /* * Attach to the ISA PnP descriptors for the timer and realtime clock. */ static struct isa_pnp_id attimer_ids[] = { { 0x0001d041 /* PNP0100 */, "AT timer" }, { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, { 0 } }; static int attimer_probe(device_t dev) { int result; if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0) device_quiet(dev); return(result); } static int attimer_attach(device_t dev) { return(0); } static device_method_t attimer_methods[] = { /* Device interface */ DEVMETHOD(device_probe, attimer_probe), DEVMETHOD(device_attach, attimer_attach), DEVMETHOD(device_detach, bus_generic_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */ DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */ { 0, 0 } }; static driver_t attimer_driver = { "attimer", attimer_methods, 1, /* no softc */ }; static devclass_t attimer_devclass; DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); #endif /* DEV_ISA */ Index: head/sys/pc98/pc98/mse.c =================================================================== --- head/sys/pc98/pc98/mse.c (revision 130173) +++ head/sys/pc98/pc98/mse.c (revision 130174) @@ -1,1074 +1,1075 @@ /* * Copyright 1992 by the University of Guelph * * Permission to use, copy and modify this * software and its documentation for any purpose and without * fee is hereby granted, provided that the above copyright * notice appear in all copies and that both that copyright * notice and this permission notice appear in supporting * documentation. * University of Guelph makes no representations about the suitability of * this software for any purpose. It is provided "as is" * without express or implied warranty. * * $FreeBSD$ */ /* * Driver for the Logitech and ATI Inport Bus mice for use with 386bsd and * the X386 port, courtesy of * Rick Macklem, rick@snowhite.cis.uoguelph.ca * Caveats: The driver currently uses spltty(), but doesn't use any * generic tty code. It could use splmse() (that only masks off the * bus mouse interrupt, but that would require hacking in i386/isa/icu.s. * (This may be worth the effort, since the Logitech generates 30/60 * interrupts/sec continuously while it is open.) * NB: The ATI has NOT been tested yet! */ /* * Modification history: * Sep 6, 1994 -- Lars Fredriksen(fredriks@mcs.com) * improved probe based on input from Logitech. * * Oct 19, 1992 -- E. Stark (stark@cs.sunysb.edu) * fixes to make it work with Microsoft InPort busmouse * * Jan, 1993 -- E. Stark (stark@cs.sunysb.edu) * added patches for new "select" interface * * May 4, 1993 -- E. Stark (stark@cs.sunysb.edu) * changed position of some spl()'s in mseread * * October 8, 1993 -- E. Stark (stark@cs.sunysb.edu) * limit maximum negative x/y value to -127 to work around XFree problem * that causes spurious button pushes. */ #include #include #include #include +#include #include #include #include #include #include #include #include #include #include #include /* driver configuration flags (config) */ #define MSE_CONFIG_ACCEL 0x00f0 /* acceleration factor */ #define MSE_CONFIG_FLAGS (MSE_CONFIG_ACCEL) /* * Software control structure for mouse. The sc_enablemouse(), * sc_disablemouse() and sc_getmouse() routines must be called spl'd(). */ typedef struct mse_softc { int sc_flags; int sc_mousetype; struct selinfo sc_selp; struct resource *sc_port; struct resource *sc_intr; bus_space_tag_t sc_iot; bus_space_handle_t sc_ioh; void *sc_ih; void (*sc_enablemouse)(bus_space_tag_t t, bus_space_handle_t h); void (*sc_disablemouse)(bus_space_tag_t t, bus_space_handle_t h); void (*sc_getmouse)(bus_space_tag_t t, bus_space_handle_t h, int *dx, int *dy, int *but); int sc_deltax; int sc_deltay; int sc_obuttons; int sc_buttons; int sc_bytesread; u_char sc_bytes[MOUSE_SYS_PACKETSIZE]; struct callout_handle sc_callout; int sc_watchdog; dev_t sc_dev; dev_t sc_ndev; mousehw_t hw; mousemode_t mode; mousestatus_t status; } mse_softc_t; static devclass_t mse_devclass; static int mse_probe(device_t dev); static int mse_attach(device_t dev); static int mse_detach(device_t dev); static device_method_t mse_methods[] = { DEVMETHOD(device_probe, mse_probe), DEVMETHOD(device_attach, mse_attach), DEVMETHOD(device_detach, mse_detach), { 0, 0 } }; static driver_t mse_driver = { "mse", mse_methods, sizeof(mse_softc_t), }; DRIVER_MODULE(mse, isa, mse_driver, mse_devclass, 0, 0); static struct isa_pnp_id mse_ids[] = { { 0x000fd041, "Bus mouse" }, /* PNP0F00 */ { 0x020fd041, "InPort mouse" }, /* PNP0F02 */ { 0x0d0fd041, "InPort mouse compatible" }, /* PNP0F0D */ { 0x110fd041, "Bus mouse compatible" }, /* PNP0F11 */ { 0x150fd041, "Logitech bus mouse" }, /* PNP0F15 */ { 0x180fd041, "Logitech bus mouse compatible" },/* PNP0F18 */ { 0 } }; static d_open_t mseopen; static d_close_t mseclose; static d_read_t mseread; static d_ioctl_t mseioctl; static d_poll_t msepoll; static struct cdevsw mse_cdevsw = { .d_version = D_VERSION, .d_flags = D_NEEDGIANT, .d_open = mseopen, .d_close = mseclose, .d_read = mseread, .d_ioctl = mseioctl, .d_poll = msepoll, .d_name = "mse", }; static void mseintr(void *); static timeout_t msetimeout; /* Flags */ #define MSESC_OPEN 0x1 #define MSESC_WANT 0x2 /* and Mouse Types */ #define MSE_NONE 0 /* don't move this! */ #ifdef PC98 #define MSE_98BUSMOUSE 0x1 #else #define MSE_LOGITECH 0x1 #define MSE_ATIINPORT 0x2 #define MSE_LOGI_SIG 0xA5 #endif #define MSE_PORTA 0 #define MSE_PORTB 1 #define MSE_PORTC 2 #define MSE_PORTD 3 #define MSE_IOSIZE 4 #define MSE_UNIT(dev) (minor(dev) >> 1) #define MSE_NBLOCKIO(dev) (minor(dev) & 0x1) #ifdef PC98 /* * PC-9801 Bus mouse definitions */ #define MODE MSE_PORTD #define HC MSE_PORTD #define INT MSE_PORTD #define XL 0x00 #define XH 0x20 #define YL 0x40 #define YH 0x60 #define INT_ENABLE 0x8 #define INT_DISABLE 0x9 #define HC_NO_CLEAR 0xe #define HC_CLEAR 0xf static bus_addr_t mse_port[] = {0, 2, 4, 6}; static int mse_probe98m(device_t dev, mse_softc_t *sc); static void mse_disable98m(bus_space_tag_t t, bus_space_handle_t h); static void mse_get98m(bus_space_tag_t t, bus_space_handle_t h, int *dx, int *dy, int *but); static void mse_enable98m(bus_space_tag_t t, bus_space_handle_t h); #else /* * Logitech bus mouse definitions */ #define MSE_SETUP 0x91 /* What does this mean? */ /* The definition for the control port */ /* is as follows: */ /* D7 = Mode set flag (1 = active) */ /* D6,D5 = Mode selection (port A) */ /* 00 = Mode 0 = Basic I/O */ /* 01 = Mode 1 = Strobed I/O */ /* 10 = Mode 2 = Bi-dir bus */ /* D4 = Port A direction (1 = input)*/ /* D3 = Port C (upper 4 bits) */ /* direction. (1 = input) */ /* D2 = Mode selection (port B & C) */ /* 0 = Mode 0 = Basic I/O */ /* 1 = Mode 1 = Strobed I/O */ /* D1 = Port B direction (1 = input)*/ /* D0 = Port C (lower 4 bits) */ /* direction. (1 = input) */ /* So 91 means Basic I/O on all 3 ports,*/ /* Port A is an input port, B is an */ /* output port, C is split with upper */ /* 4 bits being an output port and lower*/ /* 4 bits an input port, and enable the */ /* sucker. */ /* Courtesy Intel 8255 databook. Lars */ #define MSE_HOLD 0x80 #define MSE_RXLOW 0x00 #define MSE_RXHIGH 0x20 #define MSE_RYLOW 0x40 #define MSE_RYHIGH 0x60 #define MSE_DISINTR 0x10 #define MSE_INTREN 0x00 static int mse_probelogi(device_t dev, mse_softc_t *sc); static void mse_disablelogi(bus_space_tag_t t, bus_space_handle_t h); static void mse_getlogi(bus_space_tag_t t, bus_space_handle_t h, int *dx, int *dy, int *but); static void mse_enablelogi(bus_space_tag_t t, bus_space_handle_t h); /* * ATI Inport mouse definitions */ #define MSE_INPORT_RESET 0x80 #define MSE_INPORT_STATUS 0x00 #define MSE_INPORT_DX 0x01 #define MSE_INPORT_DY 0x02 #define MSE_INPORT_MODE 0x07 #define MSE_INPORT_HOLD 0x20 #define MSE_INPORT_INTREN 0x09 static int mse_probeati(device_t dev, mse_softc_t *sc); static void mse_enableati(bus_space_tag_t t, bus_space_handle_t h); static void mse_disableati(bus_space_tag_t t, bus_space_handle_t h); static void mse_getati(bus_space_tag_t t, bus_space_handle_t h, int *dx, int *dy, int *but); #endif #define MSEPRI (PZERO + 3) /* * Table of mouse types. * Keep the Logitech last, since I haven't figured out how to probe it * properly yet. (Someday I'll have the documentation.) */ static struct mse_types { int m_type; /* Type of bus mouse */ int (*m_probe)(device_t dev, mse_softc_t *sc); /* Probe routine to test for it */ void (*m_enable)(bus_space_tag_t t, bus_space_handle_t h); /* Start routine */ void (*m_disable)(bus_space_tag_t t, bus_space_handle_t h); /* Disable interrupts routine */ void (*m_get)(bus_space_tag_t t, bus_space_handle_t h, int *dx, int *dy, int *but); /* and get mouse status */ mousehw_t m_hw; /* buttons iftype type model hwid */ mousemode_t m_mode; /* proto rate res accel level size mask */ } mse_types[] = { #ifdef PC98 { MSE_98BUSMOUSE, mse_probe98m, mse_enable98m, mse_disable98m, mse_get98m, { 2, MOUSE_IF_BUS, MOUSE_MOUSE, MOUSE_MODEL_GENERIC, 0, }, { MOUSE_PROTO_BUS, -1, -1, 0, 0, MOUSE_MSC_PACKETSIZE, { MOUSE_MSC_SYNCMASK, MOUSE_MSC_SYNC, }, }, }, #else { MSE_ATIINPORT, mse_probeati, mse_enableati, mse_disableati, mse_getati, { 2, MOUSE_IF_INPORT, MOUSE_MOUSE, MOUSE_MODEL_GENERIC, 0, }, { MOUSE_PROTO_INPORT, -1, -1, 0, 0, MOUSE_MSC_PACKETSIZE, { MOUSE_MSC_SYNCMASK, MOUSE_MSC_SYNC, }, }, }, { MSE_LOGITECH, mse_probelogi, mse_enablelogi, mse_disablelogi, mse_getlogi, { 2, MOUSE_IF_BUS, MOUSE_MOUSE, MOUSE_MODEL_GENERIC, 0, }, { MOUSE_PROTO_BUS, -1, -1, 0, 0, MOUSE_MSC_PACKETSIZE, { MOUSE_MSC_SYNCMASK, MOUSE_MSC_SYNC, }, }, }, #endif { 0, }, }; static int mse_probe(dev) device_t dev; { mse_softc_t *sc; int error; int rid; int i; /* check PnP IDs */ error = ISA_PNP_PROBE(device_get_parent(dev), dev, mse_ids); if (error == ENXIO) return error; sc = device_get_softc(dev); rid = 0; #ifdef PC98 sc->sc_port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, mse_port, MSE_IOSIZE, RF_ACTIVE); #else sc->sc_port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, MSE_IOSIZE, RF_ACTIVE); #endif if (sc->sc_port == NULL) return ENXIO; #ifdef PC98 if (isa_load_resourcev(sc->sc_port, mse_port, MSE_IOSIZE)) { bus_release_resource(dev, SYS_RES_IOPORT, rid, sc->sc_port); return ENXIO; } #endif sc->sc_iot = rman_get_bustag(sc->sc_port); sc->sc_ioh = rman_get_bushandle(sc->sc_port); /* * Check for each mouse type in the table. */ i = 0; while (mse_types[i].m_type) { if ((*mse_types[i].m_probe)(dev, sc)) { sc->sc_mousetype = mse_types[i].m_type; sc->sc_enablemouse = mse_types[i].m_enable; sc->sc_disablemouse = mse_types[i].m_disable; sc->sc_getmouse = mse_types[i].m_get; sc->hw = mse_types[i].m_hw; sc->mode = mse_types[i].m_mode; bus_release_resource(dev, SYS_RES_IOPORT, rid, sc->sc_port); device_set_desc(dev, "Bus/InPort Mouse"); return 0; } i++; } bus_release_resource(dev, SYS_RES_IOPORT, rid, sc->sc_port); return ENXIO; } static int mse_attach(dev) device_t dev; { mse_softc_t *sc; int flags; int unit; int rid; sc = device_get_softc(dev); unit = device_get_unit(dev); rid = 0; #ifdef PC98 sc->sc_port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, mse_port, MSE_IOSIZE, RF_ACTIVE); #else sc->sc_port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, MSE_IOSIZE, RF_ACTIVE); #endif if (sc->sc_port == NULL) return ENXIO; #ifdef PC98 if (isa_load_resourcev(sc->sc_port, mse_port, MSE_IOSIZE)) { bus_release_resource(dev, SYS_RES_IOPORT, rid, sc->sc_port); return ENXIO; } #endif sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->sc_intr == NULL) { bus_release_resource(dev, SYS_RES_IOPORT, rid, sc->sc_port); return ENXIO; } sc->sc_iot = rman_get_bustag(sc->sc_port); sc->sc_ioh = rman_get_bushandle(sc->sc_port); if (BUS_SETUP_INTR(device_get_parent(dev), dev, sc->sc_intr, INTR_TYPE_TTY, mseintr, sc, &sc->sc_ih)) { bus_release_resource(dev, SYS_RES_IOPORT, rid, sc->sc_port); bus_release_resource(dev, SYS_RES_IRQ, rid, sc->sc_intr); return ENXIO; } flags = device_get_flags(dev); sc->mode.accelfactor = (flags & MSE_CONFIG_ACCEL) >> 4; callout_handle_init(&sc->sc_callout); sc->sc_dev = make_dev(&mse_cdevsw, unit << 1, 0, 0, 0600, "mse%d", unit); sc->sc_ndev = make_dev(&mse_cdevsw, (unit<<1)+1, 0, 0, 0600, "nmse%d", unit); return 0; } static int mse_detach(dev) device_t dev; { mse_softc_t *sc; int rid; sc = device_get_softc(dev); if (sc->sc_flags & MSESC_OPEN) return EBUSY; rid = 0; BUS_TEARDOWN_INTR(device_get_parent(dev), dev, sc->sc_intr, sc->sc_ih); bus_release_resource(dev, SYS_RES_IRQ, rid, sc->sc_intr); bus_release_resource(dev, SYS_RES_IOPORT, rid, sc->sc_port); destroy_dev(sc->sc_dev); destroy_dev(sc->sc_ndev); return 0; } /* * Exclusive open the mouse, initialize it and enable interrupts. */ static int mseopen(dev, flags, fmt, td) dev_t dev; int flags; int fmt; struct thread *td; { mse_softc_t *sc; int s; sc = devclass_get_softc(mse_devclass, MSE_UNIT(dev)); if (sc == NULL) return (ENXIO); if (sc->sc_mousetype == MSE_NONE) return (ENXIO); if (sc->sc_flags & MSESC_OPEN) return (EBUSY); sc->sc_flags |= MSESC_OPEN; sc->sc_obuttons = sc->sc_buttons = MOUSE_MSC_BUTTONS; sc->sc_deltax = sc->sc_deltay = 0; sc->sc_bytesread = sc->mode.packetsize = MOUSE_MSC_PACKETSIZE; sc->sc_watchdog = FALSE; sc->sc_callout = timeout(msetimeout, dev, hz*2); sc->mode.level = 0; sc->status.flags = 0; sc->status.button = sc->status.obutton = 0; sc->status.dx = sc->status.dy = sc->status.dz = 0; /* * Initialize mouse interface and enable interrupts. */ s = spltty(); (*sc->sc_enablemouse)(sc->sc_iot, sc->sc_ioh); splx(s); return (0); } /* * mseclose: just turn off mouse innterrupts. */ static int mseclose(dev, flags, fmt, td) dev_t dev; int flags; int fmt; struct thread *td; { mse_softc_t *sc = devclass_get_softc(mse_devclass, MSE_UNIT(dev)); int s; untimeout(msetimeout, dev, sc->sc_callout); callout_handle_init(&sc->sc_callout); s = spltty(); (*sc->sc_disablemouse)(sc->sc_iot, sc->sc_ioh); sc->sc_flags &= ~MSESC_OPEN; splx(s); return(0); } /* * mseread: return mouse info using the MSC serial protocol, but without * using bytes 4 and 5. * (Yes this is cheesy, but it makes the X386 server happy, so...) */ static int mseread(dev, uio, ioflag) dev_t dev; struct uio *uio; int ioflag; { mse_softc_t *sc = devclass_get_softc(mse_devclass, MSE_UNIT(dev)); int xfer, s, error; /* * If there are no protocol bytes to be read, set up a new protocol * packet. */ s = spltty(); /* XXX Should be its own spl, but where is imlXX() */ if (sc->sc_bytesread >= sc->mode.packetsize) { while (sc->sc_deltax == 0 && sc->sc_deltay == 0 && (sc->sc_obuttons ^ sc->sc_buttons) == 0) { if (MSE_NBLOCKIO(dev)) { splx(s); return (0); } sc->sc_flags |= MSESC_WANT; error = tsleep(sc, MSEPRI | PCATCH, "mseread", 0); if (error) { splx(s); return (error); } } /* * Generate protocol bytes. * For some reason X386 expects 5 bytes but never uses * the fourth or fifth? */ sc->sc_bytes[0] = sc->mode.syncmask[1] | (sc->sc_buttons & ~sc->mode.syncmask[0]); if (sc->sc_deltax > 127) sc->sc_deltax = 127; if (sc->sc_deltax < -127) sc->sc_deltax = -127; sc->sc_deltay = -sc->sc_deltay; /* Otherwise mousey goes wrong way */ if (sc->sc_deltay > 127) sc->sc_deltay = 127; if (sc->sc_deltay < -127) sc->sc_deltay = -127; sc->sc_bytes[1] = sc->sc_deltax; sc->sc_bytes[2] = sc->sc_deltay; sc->sc_bytes[3] = sc->sc_bytes[4] = 0; sc->sc_bytes[5] = sc->sc_bytes[6] = 0; sc->sc_bytes[7] = MOUSE_SYS_EXTBUTTONS; sc->sc_obuttons = sc->sc_buttons; sc->sc_deltax = sc->sc_deltay = 0; sc->sc_bytesread = 0; } splx(s); xfer = min(uio->uio_resid, sc->mode.packetsize - sc->sc_bytesread); error = uiomove(&sc->sc_bytes[sc->sc_bytesread], xfer, uio); if (error) return (error); sc->sc_bytesread += xfer; return(0); } /* * mseioctl: process ioctl commands. */ static int mseioctl(dev, cmd, addr, flag, td) dev_t dev; u_long cmd; caddr_t addr; int flag; struct thread *td; { mse_softc_t *sc = devclass_get_softc(mse_devclass, MSE_UNIT(dev)); mousestatus_t status; int err = 0; int s; switch (cmd) { case MOUSE_GETHWINFO: s = spltty(); *(mousehw_t *)addr = sc->hw; if (sc->mode.level == 0) ((mousehw_t *)addr)->model = MOUSE_MODEL_GENERIC; splx(s); break; case MOUSE_GETMODE: s = spltty(); *(mousemode_t *)addr = sc->mode; switch (sc->mode.level) { case 0: break; case 1: ((mousemode_t *)addr)->protocol = MOUSE_PROTO_SYSMOUSE; ((mousemode_t *)addr)->syncmask[0] = MOUSE_SYS_SYNCMASK; ((mousemode_t *)addr)->syncmask[1] = MOUSE_SYS_SYNC; break; } splx(s); break; case MOUSE_SETMODE: switch (((mousemode_t *)addr)->level) { case 0: case 1: break; default: return (EINVAL); } if (((mousemode_t *)addr)->accelfactor < -1) return (EINVAL); else if (((mousemode_t *)addr)->accelfactor >= 0) sc->mode.accelfactor = ((mousemode_t *)addr)->accelfactor; sc->mode.level = ((mousemode_t *)addr)->level; switch (sc->mode.level) { case 0: sc->sc_bytesread = sc->mode.packetsize = MOUSE_MSC_PACKETSIZE; break; case 1: sc->sc_bytesread = sc->mode.packetsize = MOUSE_SYS_PACKETSIZE; break; } break; case MOUSE_GETLEVEL: *(int *)addr = sc->mode.level; break; case MOUSE_SETLEVEL: switch (*(int *)addr) { case 0: sc->mode.level = *(int *)addr; sc->sc_bytesread = sc->mode.packetsize = MOUSE_MSC_PACKETSIZE; break; case 1: sc->mode.level = *(int *)addr; sc->sc_bytesread = sc->mode.packetsize = MOUSE_SYS_PACKETSIZE; break; default: return (EINVAL); } break; case MOUSE_GETSTATUS: s = spltty(); status = sc->status; sc->status.flags = 0; sc->status.obutton = sc->status.button; sc->status.button = 0; sc->status.dx = 0; sc->status.dy = 0; sc->status.dz = 0; splx(s); *(mousestatus_t *)addr = status; break; case MOUSE_READSTATE: case MOUSE_READDATA: return (ENODEV); #if (defined(MOUSE_GETVARS)) case MOUSE_GETVARS: case MOUSE_SETVARS: return (ENODEV); #endif default: return (ENOTTY); } return (err); } /* * msepoll: check for mouse input to be processed. */ static int msepoll(dev, events, td) dev_t dev; int events; struct thread *td; { mse_softc_t *sc = devclass_get_softc(mse_devclass, MSE_UNIT(dev)); int s; int revents = 0; s = spltty(); if (events & (POLLIN | POLLRDNORM)) { if (sc->sc_bytesread != sc->mode.packetsize || sc->sc_deltax != 0 || sc->sc_deltay != 0 || (sc->sc_obuttons ^ sc->sc_buttons) != 0) revents |= events & (POLLIN | POLLRDNORM); else { /* * Since this is an exclusive open device, any previous * proc pointer is trash now, so we can just assign it. */ selrecord(td, &sc->sc_selp); } } splx(s); return (revents); } /* * msetimeout: watchdog timer routine. */ static void msetimeout(arg) void *arg; { dev_t dev; mse_softc_t *sc; dev = (dev_t)arg; sc = devclass_get_softc(mse_devclass, MSE_UNIT(dev)); if (sc->sc_watchdog) { if (bootverbose) printf("mse%d: lost interrupt?\n", MSE_UNIT(dev)); mseintr(sc); } sc->sc_watchdog = TRUE; sc->sc_callout = timeout(msetimeout, dev, hz); } /* * mseintr: update mouse status. sc_deltax and sc_deltay are accumulative. */ static void mseintr(arg) void *arg; { /* * the table to turn MouseSystem button bits (MOUSE_MSC_BUTTON?UP) * into `mousestatus' button bits (MOUSE_BUTTON?DOWN). */ static int butmap[8] = { 0, MOUSE_BUTTON3DOWN, MOUSE_BUTTON2DOWN, MOUSE_BUTTON2DOWN | MOUSE_BUTTON3DOWN, MOUSE_BUTTON1DOWN, MOUSE_BUTTON1DOWN | MOUSE_BUTTON3DOWN, MOUSE_BUTTON1DOWN | MOUSE_BUTTON2DOWN, MOUSE_BUTTON1DOWN | MOUSE_BUTTON2DOWN | MOUSE_BUTTON3DOWN }; mse_softc_t *sc = arg; int dx, dy, but; int sign; #ifdef DEBUG static int mse_intrcnt = 0; if((mse_intrcnt++ % 10000) == 0) printf("mseintr\n"); #endif /* DEBUG */ if ((sc->sc_flags & MSESC_OPEN) == 0) return; (*sc->sc_getmouse)(sc->sc_iot, sc->sc_ioh, &dx, &dy, &but); if (sc->mode.accelfactor > 0) { sign = (dx < 0); dx = dx * dx / sc->mode.accelfactor; if (dx == 0) dx = 1; if (sign) dx = -dx; sign = (dy < 0); dy = dy * dy / sc->mode.accelfactor; if (dy == 0) dy = 1; if (sign) dy = -dy; } sc->sc_deltax += dx; sc->sc_deltay += dy; sc->sc_buttons = but; but = butmap[~but & MOUSE_MSC_BUTTONS]; sc->status.dx += dx; sc->status.dy += dy; sc->status.flags |= ((dx || dy) ? MOUSE_POSCHANGED : 0) | (sc->status.button ^ but); sc->status.button = but; sc->sc_watchdog = FALSE; /* * If mouse state has changed, wake up anyone wanting to know. */ if (sc->sc_deltax != 0 || sc->sc_deltay != 0 || (sc->sc_obuttons ^ sc->sc_buttons) != 0) { if (sc->sc_flags & MSESC_WANT) { sc->sc_flags &= ~MSESC_WANT; wakeup(sc); } selwakeuppri(&sc->sc_selp, MSEPRI); } } #ifndef PC98 /* * Routines for the Logitech mouse. */ /* * Test for a Logitech bus mouse and return 1 if it is. * (until I know how to use the signature port properly, just disable * interrupts and return 1) */ static int mse_probelogi(dev, sc) device_t dev; mse_softc_t *sc; { int sig; bus_space_write_1(sc->sc_iot, sc->sc_ioh, MSE_PORTD, MSE_SETUP); /* set the signature port */ bus_space_write_1(sc->sc_iot, sc->sc_ioh, MSE_PORTB, MSE_LOGI_SIG); DELAY(30000); /* 30 ms delay */ sig = bus_space_read_1(sc->sc_iot, sc->sc_ioh, MSE_PORTB) & 0xFF; if (sig == MSE_LOGI_SIG) { bus_space_write_1(sc->sc_iot, sc->sc_ioh, MSE_PORTC, MSE_DISINTR); return(1); } else { if (bootverbose) device_printf(dev, "wrong signature %x\n", sig); return(0); } } /* * Initialize Logitech mouse and enable interrupts. */ static void mse_enablelogi(tag, handle) bus_space_tag_t tag; bus_space_handle_t handle; { int dx, dy, but; bus_space_write_1(tag, handle, MSE_PORTD, MSE_SETUP); mse_getlogi(tag, handle, &dx, &dy, &but); } /* * Disable interrupts for Logitech mouse. */ static void mse_disablelogi(tag, handle) bus_space_tag_t tag; bus_space_handle_t handle; { bus_space_write_1(tag, handle, MSE_PORTC, MSE_DISINTR); } /* * Get the current dx, dy and button up/down state. */ static void mse_getlogi(tag, handle, dx, dy, but) bus_space_tag_t tag; bus_space_handle_t handle; int *dx; int *dy; int *but; { register char x, y; bus_space_write_1(tag, handle, MSE_PORTC, MSE_HOLD | MSE_RXLOW); x = bus_space_read_1(tag, handle, MSE_PORTA); *but = (x >> 5) & MOUSE_MSC_BUTTONS; x &= 0xf; bus_space_write_1(tag, handle, MSE_PORTC, MSE_HOLD | MSE_RXHIGH); x |= (bus_space_read_1(tag, handle, MSE_PORTA) << 4); bus_space_write_1(tag, handle, MSE_PORTC, MSE_HOLD | MSE_RYLOW); y = (bus_space_read_1(tag, handle, MSE_PORTA) & 0xf); bus_space_write_1(tag, handle, MSE_PORTC, MSE_HOLD | MSE_RYHIGH); y |= (bus_space_read_1(tag, handle, MSE_PORTA) << 4); *dx = x; *dy = y; bus_space_write_1(tag, handle, MSE_PORTC, MSE_INTREN); } /* * Routines for the ATI Inport bus mouse. */ /* * Test for an ATI Inport bus mouse and return 1 if it is. * (do not enable interrupts) */ static int mse_probeati(dev, sc) device_t dev; mse_softc_t *sc; { int i; for (i = 0; i < 2; i++) if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, MSE_PORTC) == 0xde) return (1); return (0); } /* * Initialize ATI Inport mouse and enable interrupts. */ static void mse_enableati(tag, handle) bus_space_tag_t tag; bus_space_handle_t handle; { bus_space_write_1(tag, handle, MSE_PORTA, MSE_INPORT_RESET); bus_space_write_1(tag, handle, MSE_PORTA, MSE_INPORT_MODE); bus_space_write_1(tag, handle, MSE_PORTB, MSE_INPORT_INTREN); } /* * Disable interrupts for ATI Inport mouse. */ static void mse_disableati(tag, handle) bus_space_tag_t tag; bus_space_handle_t handle; { bus_space_write_1(tag, handle, MSE_PORTA, MSE_INPORT_MODE); bus_space_write_1(tag, handle, MSE_PORTB, 0); } /* * Get current dx, dy and up/down button state. */ static void mse_getati(tag, handle, dx, dy, but) bus_space_tag_t tag; bus_space_handle_t handle; int *dx; int *dy; int *but; { register char byte; bus_space_write_1(tag, handle, MSE_PORTA, MSE_INPORT_MODE); bus_space_write_1(tag, handle, MSE_PORTB, MSE_INPORT_HOLD); bus_space_write_1(tag, handle, MSE_PORTA, MSE_INPORT_STATUS); *but = ~bus_space_read_1(tag, handle, MSE_PORTB) & MOUSE_MSC_BUTTONS; bus_space_write_1(tag, handle, MSE_PORTA, MSE_INPORT_DX); byte = bus_space_read_1(tag, handle, MSE_PORTB); *dx = byte; bus_space_write_1(tag, handle, MSE_PORTA, MSE_INPORT_DY); byte = bus_space_read_1(tag, handle, MSE_PORTB); *dy = byte; bus_space_write_1(tag, handle, MSE_PORTA, MSE_INPORT_MODE); bus_space_write_1(tag, handle, MSE_PORTB, MSE_INPORT_INTREN); } #endif #ifdef PC98 /* * Routines for the PC98 bus mouse. */ /* * Test for a PC98 bus mouse and return 1 if it is. * (do not enable interrupts) */ static int mse_probe98m(dev, sc) device_t dev; mse_softc_t *sc; { /* mode set */ bus_space_write_1(sc->sc_iot, sc->sc_ioh, MODE, 0x93); /* initialize */ /* INT disable */ bus_space_write_1(sc->sc_iot, sc->sc_ioh, INT, INT_DISABLE); /* HC = 0 */ bus_space_write_1(sc->sc_iot, sc->sc_ioh, HC, HC_NO_CLEAR); /* HC = 1 */ bus_space_write_1(sc->sc_iot, sc->sc_ioh, HC, HC_CLEAR); return (1); } /* * Initialize PC98 bus mouse and enable interrupts. */ static void mse_enable98m(tag, handle) bus_space_tag_t tag; bus_space_handle_t handle; { bus_space_write_1(tag, handle, INT, INT_ENABLE); /* INT enable */ bus_space_write_1(tag, handle, HC, HC_NO_CLEAR); /* HC = 0 */ bus_space_write_1(tag, handle, HC, HC_CLEAR); /* HC = 1 */ } /* * Disable interrupts for PC98 Bus mouse. */ static void mse_disable98m(tag, handle) bus_space_tag_t tag; bus_space_handle_t handle; { bus_space_write_1(tag, handle, INT, INT_DISABLE); /* INT disable */ bus_space_write_1(tag, handle, HC, HC_NO_CLEAR); /* HC = 0 */ bus_space_write_1(tag, handle, HC, HC_CLEAR); /* HC = 1 */ } /* * Get current dx, dy and up/down button state. */ static void mse_get98m(tag, handle, dx, dy, but) bus_space_tag_t tag; bus_space_handle_t handle; int *dx; int *dy; int *but; { register char x, y; bus_space_write_1(tag, handle, INT, INT_DISABLE); /* INT disable */ bus_space_write_1(tag, handle, HC, HC_CLEAR); /* HC = 1 */ /* X low */ bus_space_write_1(tag, handle, MSE_PORTC, 0x90 | XL); x = bus_space_read_1(tag, handle, MSE_PORTA) & 0x0f; /* X high */ bus_space_write_1(tag, handle, MSE_PORTC, 0x90 | XH); x |= ((bus_space_read_1(tag, handle, MSE_PORTA) & 0x0f) << 4); /* Y low */ bus_space_write_1(tag, handle, MSE_PORTC, 0x90 | YL); y = (bus_space_read_1(tag, handle, MSE_PORTA) & 0x0f); /* Y high */ bus_space_write_1(tag, handle, MSE_PORTC, 0x90 | YH); y |= ((bus_space_read_1(tag, handle, MSE_PORTA) & 0x0f) << 4); *but = (bus_space_read_1(tag, handle, MSE_PORTA) >> 5) & 7; *dx = x; *dy = y; bus_space_write_1(tag, handle, HC, HC_NO_CLEAR); /* HC = 0 */ bus_space_write_1(tag, handle, INT, INT_ENABLE); /* INT enable */ } #endif Index: head/sys/pc98/pc98/olpt.c =================================================================== --- head/sys/pc98/pc98/olpt.c (revision 130173) +++ head/sys/pc98/pc98/olpt.c (revision 130174) @@ -1,817 +1,818 @@ /* * Copyright (c) 1990 William F. Jolitz, TeleMuse * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This software is a component of "386BSD" developed by * William F. Jolitz, TeleMuse. * 4. Neither the name of the developer nor the name "386BSD" * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ * AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS * SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT. * THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT * NOT MAKE USE OF THIS WORK. * * FOR USERS WHO WISH TO UNDERSTAND THE 386BSD SYSTEM DEVELOPED * BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN * REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES * (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING * JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND * LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE * ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS * OF 386BSD ENTITLED "386BSD FROM THE INSIDE OUT" WILL BE AVAILABLE LATE 1992. * * THIS SOFTWARE IS PROVIDED BY THE DEVELOPER ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE DEVELOPER BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: unknown origin, 386BSD 0.1 * $FreeBSD$ */ /* * Device Driver for AT parallel printer port * Written by William Jolitz 12/18/90 */ /* * Parallel port TCP/IP interfaces added. I looked at the driver from * MACH but this is a complete rewrite, and btw. incompatible, and it * should perform better too. I have never run the MACH driver though. * * This driver sends two bytes (0x08, 0x00) in front of each packet, * to allow us to distinguish another format later. * * Now added a Linux/Crynwr compatibility mode which is enabled using * IF_LINK0 - Tim Wilkinson. * * TODO: * Make HDLC/PPP mode, use IF_LLC1 to enable. * * Connect the two computers using a Laplink parallel cable to use this * feature: * * +----------------------------------------+ * |A-name A-End B-End Descr. Port/Bit | * +----------------------------------------+ * |DATA0 2 15 Data 0/0x01 | * |-ERROR 15 2 1/0x08 | * +----------------------------------------+ * |DATA1 3 13 Data 0/0x02 | * |+SLCT 13 3 1/0x10 | * +----------------------------------------+ * |DATA2 4 12 Data 0/0x04 | * |+PE 12 4 1/0x20 | * +----------------------------------------+ * |DATA3 5 10 Strobe 0/0x08 | * |-ACK 10 5 1/0x40 | * +----------------------------------------+ * |DATA4 6 11 Data 0/0x10 | * |BUSY 11 6 1/~0x80 | * +----------------------------------------+ * |GND 18-25 18-25 GND - | * +----------------------------------------+ * * Expect transfer-rates up to 75 kbyte/sec. * * If GCC could correctly grok * register int port asm("edx") * the code would be cleaner * * Poul-Henning Kamp */ #include #include #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #define LPINITRDY 4 /* wait up to 4 seconds for a ready */ #define LPTOUTINITIAL 10 /* initial timeout to wait for ready 1/10 s */ #define LPTOUTMAX 1 /* maximal timeout 1 s */ #define LPPRI (PZERO+8) #define BUFSIZE 1024 #ifndef PC98 /* BIOS printer list - used by BIOS probe*/ #define BIOS_LPT_PORTS 0x408 #define BIOS_PORTS (short *)(KERNBASE+BIOS_LPT_PORTS) #define BIOS_MAX_LPT 4 #endif #ifndef DEBUG #define lprintf(args) #else #define lprintf(args) do { \ if (lptflag) \ printf args; \ } while (0) static int volatile lptflag = 1; #endif #define LPTUNIT(s) ((s)&0x03) #define LPTFLAGS(s) ((s)&0xfc) struct lpt_softc { struct resource *res_port; struct resource *res_irq; void *sc_ih; int sc_port; short sc_state; /* default case: negative prime, negative ack, handshake strobe, prime once */ u_char sc_control; char sc_flags; #define LP_POS_INIT 0x04 /* if we are a postive init signal */ #define LP_POS_ACK 0x08 /* if we are a positive going ack */ #define LP_NO_PRIME 0x10 /* don't prime the printer at all */ #define LP_PRIMEOPEN 0x20 /* prime on every open */ #define LP_AUTOLF 0x40 /* tell printer to do an automatic lf */ #define LP_BYPASS 0x80 /* bypass printer ready checks */ void *sc_inbuf; short sc_xfercnt ; char sc_primed; char *sc_cp ; u_char sc_irq ; /* IRQ status of port */ #define LP_HAS_IRQ 0x01 /* we have an irq available */ #define LP_USE_IRQ 0x02 /* we are using our irq */ #define LP_ENABLE_IRQ 0x04 /* enable IRQ on open */ u_char sc_backoff ; /* time to call lptout() again */ }; /* bits for state */ #define OPEN (1<<0) /* device is open */ #define ASLP (1<<1) /* awaiting draining of printer */ #define ERROR (1<<2) /* error was received from printer */ #define OBUSY (1<<3) /* printer is busy doing output */ #define LPTOUT (1<<4) /* timeout while not selected */ #define TOUT (1<<5) /* timeout while not selected */ #define INIT (1<<6) /* waiting to initialize for open */ #define INTERRUPTED (1<<7) /* write call was interrupted */ /* status masks to interrogate printer status */ #define RDY_MASK (LPS_SEL|LPS_OUT|LPS_NBSY|LPS_NERR) /* ready ? */ #define LP_READY (LPS_SEL|LPS_NBSY|LPS_NERR) /* Printer Ready condition - from lpa.c */ /* Only used in polling code */ #ifdef PC98 #define NOT_READY(x) ((inb(x) & LPS_NBSY) != LPS_NBSY) #else /* IBM-PC */ #define LPS_INVERT (LPS_NBSY | LPS_NACK | LPS_SEL | LPS_NERR) #define LPS_MASK (LPS_NBSY | LPS_NACK | LPS_OUT | LPS_SEL | LPS_NERR) #define NOT_READY(x) ((inb(x)^LPS_INVERT)&LPS_MASK) #endif #define MAX_SLEEP (hz*5) /* Timeout while waiting for device ready */ #define MAX_SPIN 20 /* Max delay for device ready in usecs */ static timeout_t lptout; static int lpt_probe(device_t); static int lpt_attach(device_t); static void lpt_intr(void *); static devclass_t olpt_devclass; static device_method_t olpt_methods[] = { DEVMETHOD(device_probe, lpt_probe), DEVMETHOD(device_attach, lpt_attach), { 0, 0 } }; static driver_t olpt_driver = { "olpt", olpt_methods, sizeof (struct lpt_softc), }; DRIVER_MODULE(olpt, isa, olpt_driver, olpt_devclass, 0, 0); static d_open_t lptopen; static d_close_t lptclose; static d_write_t lptwrite; static d_ioctl_t lptioctl; static struct cdevsw lpt_cdevsw = { .d_version = D_VERSION, .d_flags = D_NEEDGIANT, .d_open = lptopen, .d_close = lptclose, .d_write = lptwrite, .d_ioctl = lptioctl, .d_name = "lpt", }; static bus_addr_t lpt_iat[] = {0, 2, 4, 6}; #ifndef PC98 /* * Internal routine to lptprobe to do port tests of one byte value */ static int lpt_port_test (int port, u_char data, u_char mask) { int temp, timeout; data = data & mask; outb(port, data); timeout = 10000; do { DELAY(10); temp = inb(port) & mask; } while (temp != data && --timeout); lprintf(("Port 0x%x\tout=%x\tin=%x\ttout=%d\n", port, data, temp, timeout)); return (temp == data); } #endif /* PC98 */ /* * New lpt port probe Geoff Rehmet - Rhodes University - 14/2/94 * Based partially on Rod Grimes' printer probe * * Logic: * 1) If no port address was given, use the bios detected ports * and autodetect what ports the printers are on. * 2) Otherwise, probe the data port at the address given, * using the method in Rod Grimes' port probe. * (Much code ripped off directly from Rod's probe.) * * Comments from Rod's probe: * Logic: * 1) You should be able to write to and read back the same value * to the data port. Do an alternating zeros, alternating ones, * walking zero, and walking one test to check for stuck bits. * * 2) You should be able to write to and read back the same value * to the control port lower 5 bits, the upper 3 bits are reserved * per the IBM PC technical reference manauls and different boards * do different things with them. Do an alternating zeros, alternating * ones, walking zero, and walking one test to check for stuck bits. * * Some printers drag the strobe line down when the are powered off * so this bit has been masked out of the control port test. * * XXX Some printers may not like a fast pulse on init or strobe, I * don't know at this point, if that becomes a problem these bits * should be turned off in the mask byte for the control port test. * * We are finally left with a mask of 0x14, due to some printers * being adamant about holding other bits high ........ * * Before probing the control port, we write a 0 to the data port - * If not, some printers chuck out garbage when the strobe line * gets toggled. * * 3) Set the data and control ports to a value of 0 * * This probe routine has been tested on Epson Lx-800, HP LJ3P, * Epson FX-1170 and C.Itoh 8510RM * printers. * Quick exit on fail added. */ int lpt_probe(device_t dev) { #ifdef PC98 #define PC98_OLD_LPT 0x40 #define PC98_IEEE_1284_FUNCTION 0x149 int rid; struct resource *res; /* Check isapnp ids */ if (isa_get_vendorid(dev)) return ENXIO; rid = 0; res = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, lpt_iat, 4, RF_ACTIVE); if (res == NULL) return ENXIO; isa_load_resourcev(res, lpt_iat, 4); if (isa_get_port(dev) == PC98_OLD_LPT) { unsigned int pc98_ieee_mode, tmp; tmp = inb(PC98_IEEE_1284_FUNCTION); pc98_ieee_mode = tmp; if ((tmp & 0x10) == 0x10) { outb(PC98_IEEE_1284_FUNCTION, tmp & ~0x10); tmp = inb(PC98_IEEE_1284_FUNCTION); if ((tmp & 0x10) != 0x10) { outb(PC98_IEEE_1284_FUNCTION, pc98_ieee_mode); bus_release_resource(dev, SYS_RES_IOPORT, rid, res); return ENXIO; } } } bus_release_resource(dev, SYS_RES_IOPORT, rid, res); return 0; #else int port; static short next_bios_lpt = 0; int status; static u_char testbyte[18] = { 0x55, /* alternating zeros */ 0xaa, /* alternating ones */ 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f, /* walking zero */ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 /* walking one */ }; int i; /* * Make sure there is some way for lptopen to see that * the port is not configured * This 0 will remain if the port isn't attached */ (lpt_sc + dvp->id_unit)->sc_port = 0; status = IO_LPTSIZE; /* If port not specified, use bios list */ if(dvp->id_iobase < 0) { /* port? */ if((next_bios_lpt < BIOS_MAX_LPT) && (*(BIOS_PORTS+next_bios_lpt) != 0) ) { dvp->id_iobase = *(BIOS_PORTS+next_bios_lpt++); goto end_probe; } else return (0); } /* Port was explicitly specified */ /* This allows probing of ports unknown to the BIOS */ port = dvp->id_iobase + lpt_data; for (i = 0; i < 18; i++) { if (!lpt_port_test(port, testbyte[i], 0xff)) { status = 0; goto end_probe; } } end_probe: /* write 0's to control and data ports */ outb(dvp->id_iobase+lpt_data, 0); outb(dvp->id_iobase+lpt_control, 0); return (status); #endif } /* XXX Todo - try and detect if interrupt is working */ int lpt_attach(device_t dev) { int rid, unit; struct lpt_softc *sc; unit = device_get_unit(dev); sc = device_get_softc(dev); rid = 0; sc->res_port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, lpt_iat, 4, RF_ACTIVE); if (sc->res_port == NULL) return ENXIO; isa_load_resourcev(sc->res_port, lpt_iat, 4); sc->sc_port = rman_get_start(sc->res_port); sc->sc_primed = 0; /* not primed yet */ #ifdef PC98 outb(sc->sc_port+lpt_pstb_ctrl, LPC_DIS_PSTB); /* PSTB disable */ outb(sc->sc_port+lpt_control, LPC_MODE8255); /* 8255 mode set */ outb(sc->sc_port+lpt_control, LPC_NIRQ8); /* IRQ8 inactive */ outb(sc->sc_port+lpt_control, LPC_NPSTB); /* PSTB inactive */ outb(sc->sc_port+lpt_pstb_ctrl, LPC_EN_PSTB); /* PSTB enable */ #else outb(sc->sc_port+lpt_control, LPC_NINIT); #endif sc->sc_irq = 0; if (isa_get_irq(dev) != -1) { rid = 0; sc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->res_irq == NULL) { bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->res_port); return ENXIO; } if (bus_setup_intr(dev, sc->res_irq, INTR_TYPE_TTY, lpt_intr, sc, &sc->sc_ih)) { bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->res_port); bus_release_resource(dev, SYS_RES_IRQ, 0, sc->res_irq); return ENXIO; } sc->sc_irq = LP_HAS_IRQ | LP_USE_IRQ | LP_ENABLE_IRQ; device_printf(dev, "Interrupt-driven port"); } /* XXX what to do about the flags in the minor number? */ make_dev(&lpt_cdevsw, unit, UID_ROOT, GID_WHEEL, 0600, "lpt%d", unit); make_dev(&lpt_cdevsw, unit | LP_BYPASS, UID_ROOT, GID_WHEEL, 0600, "lpctl%d", unit); return 0; } /* * lptopen -- reset the printer, then wait until it's selected and not busy. * If LP_BYPASS flag is selected, then we do not try to select the * printer -- this is just used for passing ioctls. */ static int lptopen (dev_t dev, int flags, int fmt, struct thread *td) { struct lpt_softc *sc; int s; #ifdef PC98 int port; #else int trys, port; #endif sc = devclass_get_softc(olpt_devclass, LPTUNIT(minor(dev))); if (sc->sc_port == 0) return (ENXIO); if (sc->sc_state) { lprintf(("lp: still open %x\n", sc->sc_state)); return(EBUSY); } else sc->sc_state |= INIT; sc->sc_flags = LPTFLAGS(minor(dev)); /* Check for open with BYPASS flag set. */ if (sc->sc_flags & LP_BYPASS) { sc->sc_state = OPEN; return(0); } s = spltty(); lprintf(("lp flags 0x%x\n", sc->sc_flags)); port = sc->sc_port; /* set IRQ status according to ENABLE_IRQ flag */ if (sc->sc_irq & LP_ENABLE_IRQ) sc->sc_irq |= LP_USE_IRQ; else sc->sc_irq &= ~LP_USE_IRQ; /* init printer */ #ifndef PC98 if ((sc->sc_flags & LP_NO_PRIME) == 0) { if((sc->sc_flags & LP_PRIMEOPEN) || sc->sc_primed == 0) { outb(port+lpt_control, 0); sc->sc_primed++; DELAY(500); } } outb (port+lpt_control, LPC_SEL|LPC_NINIT); /* wait till ready (printer running diagnostics) */ trys = 0; do { /* ran out of waiting for the printer */ if (trys++ >= LPINITRDY*4) { splx(s); sc->sc_state = 0; lprintf(("status %x\n", inb(port+lpt_status))); return (EBUSY); } /* wait 1/4 second, give up if we get a signal */ if (tsleep (sc, LPPRI|PCATCH, "lptinit", hz/4) != EWOULDBLOCK) { sc->sc_state = 0; splx(s); return (EBUSY); } /* is printer online and ready for output */ } while ((inb(port+lpt_status) & (LPS_SEL|LPS_OUT|LPS_NBSY|LPS_NERR)) != (LPS_SEL|LPS_NBSY|LPS_NERR)); sc->sc_control = LPC_SEL|LPC_NINIT; if (sc->sc_flags & LP_AUTOLF) sc->sc_control |= LPC_AUTOL; /* enable interrupt if interrupt-driven */ if (sc->sc_irq & LP_USE_IRQ) sc->sc_control |= LPC_ENA; outb(port+lpt_control, sc->sc_control); #endif sc->sc_state = OPEN; sc->sc_inbuf = malloc(BUFSIZE, M_DEVBUF, M_WAITOK); sc->sc_xfercnt = 0; splx(s); /* only use timeout if using interrupt */ lprintf(("irq %x\n", sc->sc_irq)); if (sc->sc_irq & LP_USE_IRQ) { sc->sc_state |= TOUT; timeout (lptout, (caddr_t)sc, (sc->sc_backoff = hz/LPTOUTINITIAL)); } lprintf(("opened.\n")); return(0); } static void lptout (void *arg) { struct lpt_softc *sc = arg; int pl; lprintf(("T %x ", inb(sc->sc_port+lpt_status))); if (sc->sc_state & OPEN) { sc->sc_backoff++; if (sc->sc_backoff > hz/LPTOUTMAX) sc->sc_backoff = sc->sc_backoff > hz/LPTOUTMAX; timeout (lptout, (caddr_t)sc, sc->sc_backoff); } else sc->sc_state &= ~TOUT; if (sc->sc_state & ERROR) sc->sc_state &= ~ERROR; /* * Avoid possible hangs do to missed interrupts */ if (sc->sc_xfercnt) { pl = spltty(); lpt_intr(sc); splx(pl); } else { sc->sc_state &= ~OBUSY; wakeup(sc); } } /* * lptclose -- close the device, free the local line buffer. * * Check for interrupted write call added. */ static int lptclose(dev_t dev, int flags, int fmt, struct thread *td) { struct lpt_softc *sc; #ifndef PC98 int port; #endif sc = devclass_get_softc(olpt_devclass, LPTUNIT(minor(dev))); if(sc->sc_flags & LP_BYPASS) goto end_close; #ifndef PC98 port = sc->sc_port; #endif sc->sc_state &= ~OPEN; #ifndef PC98 /* if the last write was interrupted, don't complete it */ if((!(sc->sc_state & INTERRUPTED)) && (sc->sc_irq & LP_USE_IRQ)) while ((inb(port+lpt_status) & (LPS_SEL|LPS_OUT|LPS_NBSY|LPS_NERR)) != (LPS_SEL|LPS_NBSY|LPS_NERR) || sc->sc_xfercnt) /* wait 1/4 second, give up if we get a signal */ if (tsleep (sc, LPPRI|PCATCH, "lpclose", hz) != EWOULDBLOCK) break; outb(sc->sc_port+lpt_control, LPC_NINIT); #endif free(sc->sc_inbuf, M_DEVBUF); end_close: sc->sc_state = 0; sc->sc_xfercnt = 0; lprintf(("closed.\n")); return(0); } /* * pushbytes() * Workhorse for actually spinning and writing bytes to printer * Derived from lpa.c * Originally by ? * * This code is only used when we are polling the port */ static int pushbytes(struct lpt_softc * sc) { int spin, err, tic; char ch; int port = sc->sc_port; lprintf(("p")); /* loop for every character .. */ while (sc->sc_xfercnt > 0) { /* printer data */ ch = *(sc->sc_cp); sc->sc_cp++; sc->sc_xfercnt--; /* * Wait for printer ready. * Loop 20 usecs testing BUSY bit, then sleep * for exponentially increasing timeout. (vak) */ for (spin=0; NOT_READY(port+lpt_status) && spin= MAX_SPIN) { tic = 0; while (NOT_READY(port+lpt_status)) { /* * Now sleep, every cycle a * little longer .. */ tic = tic + tic + 1; /* * But no more than 10 seconds. (vak) */ if (tic > MAX_SLEEP) tic = MAX_SLEEP; err = tsleep(sc, LPPRI, "lptpoll", tic); if (err != EWOULDBLOCK) { return (err); } } } /* output data */ outb(port+lpt_data, ch); #ifdef PC98 DELAY(1); outb(port+lpt_control, LPC_PSTB); DELAY(1); outb(port+lpt_control, LPC_NPSTB); #else /* strobe */ outb(port+lpt_control, sc->sc_control|LPC_STB); outb(port+lpt_control, sc->sc_control); #endif } return(0); } /* * lptwrite --copy a line from user space to a local buffer, then call * putc to get the chars moved to the output queue. * * Flagging of interrupted write added. */ static int lptwrite(dev_t dev, struct uio * uio, int ioflag) { register unsigned n; int pl, err; struct lpt_softc *sc; sc = devclass_get_softc(olpt_devclass, LPTUNIT(minor(dev))); if(sc->sc_flags & LP_BYPASS) { /* we can't do writes in bypass mode */ return(EPERM); } sc->sc_state &= ~INTERRUPTED; while ((n = min(BUFSIZE, uio->uio_resid)) != 0) { sc->sc_cp = sc->sc_inbuf; uiomove(sc->sc_cp, n, uio); sc->sc_xfercnt = n ; while ((sc->sc_xfercnt > 0)&&(sc->sc_irq & LP_USE_IRQ)) { lprintf(("i")); /* if the printer is ready for a char, */ /* give it one */ if ((sc->sc_state & OBUSY) == 0){ lprintf(("\nC %d. ", sc->sc_xfercnt)); pl = spltty(); lpt_intr(sc); (void) splx(pl); } lprintf(("W ")); if (sc->sc_state & OBUSY) if ((err = tsleep (sc, LPPRI|PCATCH, "lpwrite", 0))) { sc->sc_state |= INTERRUPTED; return(err); } } /* check to see if we must do a polled write */ if(!(sc->sc_irq & LP_USE_IRQ) && (sc->sc_xfercnt)) { lprintf(("p")); if((err = pushbytes(sc))) return(err); } } return(0); } /* * lptintr -- handle printer interrupts which occur when the printer is * ready to accept another char. * * do checking for interrupted write call. */ static void lpt_intr(void *arg) { } static int lptioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct thread *td) { int error = 0; struct lpt_softc *sc; u_int unit = LPTUNIT(minor(dev)); u_char old_sc_irq; /* old printer IRQ status */ sc = devclass_get_softc(olpt_devclass, unit); switch (cmd) { case LPT_IRQ : if(sc->sc_irq & LP_HAS_IRQ) { /* * NOTE: * If the IRQ status is changed, * this will only be visible on the * next open. * * If interrupt status changes, * this gets syslog'd. */ old_sc_irq = sc->sc_irq; if(*(int*)data == 0) sc->sc_irq &= (~LP_ENABLE_IRQ); else sc->sc_irq |= LP_ENABLE_IRQ; if (old_sc_irq != sc->sc_irq ) log(LOG_NOTICE, "lpt%c switched to %s mode\n", (char)unit+'0', (sc->sc_irq & LP_ENABLE_IRQ)? "interrupt-driven":"polled"); } else /* polled port */ error = EOPNOTSUPP; break; default: error = ENODEV; } return(error); } Index: head/sys/pc98/pc98/pc98gdc.c =================================================================== --- head/sys/pc98/pc98/pc98gdc.c (revision 130173) +++ head/sys/pc98/pc98/pc98gdc.c (revision 130174) @@ -1,1499 +1,1500 @@ /* * Copyright (c) 1999 FreeBSD(98) port team. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer as * the first lines of this file unmodified. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #include "opt_gdc.h" #include "opt_fb.h" #include "opt_syscons.h" #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef LINE30 #include #endif #include #include #define TEXT_GDC 0x60 #define GRAPHIC_GDC 0xa0 #define ROW 25 #define COL 80 #define DRIVER_NAME "gdc" /* cdev driver declaration */ #define GDC_UNIT(dev) minor(dev) #define GDC_MKMINOR(unit) (unit) typedef struct gdc_softc { video_adapter_t *adp; struct resource *res_tgdc, *res_ggdc; struct resource *res_egc, *res_pegc, *res_grcg, *res_kcg; struct resource *res_tmem, *res_gmem1, *res_gmem2; #ifdef FB_INSTALL_CDEV genfb_softc_t gensc; #endif } gdc_softc_t; #define GDC_SOFTC(unit) \ ((gdc_softc_t *)devclass_get_softc(gdc_devclass, unit)) static bus_addr_t gdc_iat[] = {0, 2, 4, 6, 8, 10, 12, 14}; static devclass_t gdc_devclass; static int gdc_probe_unit(int unit, gdc_softc_t *sc, int flags); static int gdc_attach_unit(int unit, gdc_softc_t *sc, int flags); static int gdc_alloc_resource(device_t dev); static int gdc_release_resource(device_t dev); #if FB_INSTALL_CDEV static d_open_t gdcopen; static d_close_t gdcclose; static d_read_t gdcread; static d_write_t gdcwrite; static d_ioctl_t gdcioctl; static d_mmap_t gdcmmap; static struct cdevsw gdc_cdevsw = { .d_version = D_VERSION, .d_flags = D_NEEDGIANT, .d_open = gdcopen, .d_close = gdcclose, .d_read = gdcread, .d_write = gdcwrite, .d_ioctl = gdcioctl, .d_mmap = gdcmmap, .d_name = DRIVER_NAME, .d_maj = -1, }; #endif /* FB_INSTALL_CDEV */ static void gdc_identify(driver_t *driver, device_t parent) { BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, DRIVER_NAME, 0); } static int gdcprobe(device_t dev) { int error; /* Check isapnp ids */ if (isa_get_vendorid(dev)) return (ENXIO); device_set_desc(dev, "Generic GDC"); error = gdc_alloc_resource(dev); if (error) return (error); error = gdc_probe_unit(device_get_unit(dev), device_get_softc(dev), device_get_flags(dev)); gdc_release_resource(dev); return (error); } static int gdc_attach(device_t dev) { gdc_softc_t *sc; int error; error = gdc_alloc_resource(dev); if (error) return (error); sc = device_get_softc(dev); error = gdc_attach_unit(device_get_unit(dev), sc, device_get_flags(dev)); if (error) { gdc_release_resource(dev); return error; } #ifdef FB_INSTALL_CDEV /* attach a virtual frame buffer device */ error = fb_attach(GDC_MKMINOR(device_get_unit(dev)), sc->adp, &gdc_cdevsw); if (error) { gdc_release_resource(dev); return error; } #endif /* FB_INSTALL_CDEV */ if (bootverbose) (*vidsw[sc->adp->va_index]->diag)(sc->adp, bootverbose); return 0; } static int gdc_probe_unit(int unit, gdc_softc_t *sc, int flags) { video_switch_t *sw; sw = vid_get_switch(DRIVER_NAME); if (sw == NULL) return ENXIO; return (*sw->probe)(unit, &sc->adp, NULL, flags); } static int gdc_attach_unit(int unit, gdc_softc_t *sc, int flags) { video_switch_t *sw; sw = vid_get_switch(DRIVER_NAME); if (sw == NULL) return ENXIO; return (*sw->init)(unit, sc->adp, flags); } static int gdc_alloc_resource(device_t dev) { int rid; gdc_softc_t *sc; sc = device_get_softc(dev); /* TEXT GDC */ rid = 0; bus_set_resource(dev, SYS_RES_IOPORT, rid, TEXT_GDC, 1); sc->res_tgdc = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_tgdc == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_tgdc, gdc_iat, 8); /* GRAPHIC GDC */ rid = 8; bus_set_resource(dev, SYS_RES_IOPORT, rid, GRAPHIC_GDC, 1); sc->res_ggdc = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_ggdc == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_ggdc, gdc_iat, 8); /* EGC */ rid = 16; bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x4a0, 1); sc->res_egc = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_egc == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_egc, gdc_iat, 8); /* PEGC */ rid = 24; bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x9a0, 1); sc->res_pegc = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_pegc == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_pegc, gdc_iat, 8); /* CRTC/GRCG */ rid = 32; bus_set_resource(dev, SYS_RES_IOPORT, rid, 0x70, 1); sc->res_grcg = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_grcg == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_grcg, gdc_iat, 8); /* KCG */ rid = 40; bus_set_resource(dev, SYS_RES_IOPORT, rid, 0xa1, 1); sc->res_kcg = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, gdc_iat, 8, RF_ACTIVE); if (sc->res_kcg == NULL) { gdc_release_resource(dev); return (ENXIO); } isa_load_resourcev(sc->res_kcg, gdc_iat, 8); /* TEXT Memory */ rid = 0; sc->res_tmem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0xa0000, 0xa4fff, 0x5000, RF_ACTIVE); if (sc->res_tmem == NULL) { gdc_release_resource(dev); return (ENXIO); } /* GRAPHIC Memory */ rid = 1; sc->res_gmem1 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0xa8000, 0xbffff, 0x18000, RF_ACTIVE); if (sc->res_gmem1 == NULL) { gdc_release_resource(dev); return (ENXIO); } rid = 2; sc->res_gmem2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0xe0000, 0xe7fff, 0x8000, RF_ACTIVE); if (sc->res_gmem2 == NULL) { gdc_release_resource(dev); return (ENXIO); } return (0); } static int gdc_release_resource(device_t dev) { gdc_softc_t *sc; sc = device_get_softc(dev); if (sc->res_tgdc) bus_release_resource(dev, SYS_RES_IOPORT, 0, sc->res_tgdc); if (sc->res_ggdc) bus_release_resource(dev, SYS_RES_IOPORT, 8, sc->res_ggdc); if (sc->res_egc) bus_release_resource(dev, SYS_RES_IOPORT, 16, sc->res_egc); if (sc->res_pegc) bus_release_resource(dev, SYS_RES_IOPORT, 24, sc->res_pegc); if (sc->res_grcg) bus_release_resource(dev, SYS_RES_IOPORT, 32, sc->res_grcg); if (sc->res_kcg) bus_release_resource(dev, SYS_RES_IOPORT, 40, sc->res_kcg); if (sc->res_tmem) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res_tmem); if (sc->res_gmem1) bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->res_gmem1); if (sc->res_gmem2) bus_release_resource(dev, SYS_RES_MEMORY, 2, sc->res_gmem2); return (0); } /* cdev driver functions */ #ifdef FB_INSTALL_CDEV static int gdcopen(dev_t dev, int flag, int mode, struct thread *td) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); if (sc == NULL) return ENXIO; if (mode & (O_CREAT | O_APPEND | O_TRUNC)) return ENODEV; return genfbopen(&sc->gensc, sc->adp, flag, mode, td); } static int gdcclose(dev_t dev, int flag, int mode, struct thread *td) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbclose(&sc->gensc, sc->adp, flag, mode, td); } static int gdcread(dev_t dev, struct uio *uio, int flag) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbread(&sc->gensc, sc->adp, uio, flag); } static int gdcwrite(dev_t dev, struct uio *uio, int flag) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbread(&sc->gensc, sc->adp, uio, flag); } static int gdcioctl(dev_t dev, u_long cmd, caddr_t arg, int flag, struct thread *td) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbioctl(&sc->gensc, sc->adp, cmd, arg, flag, td); } static int gdcmmap(dev_t dev, vm_offset_t offset, vm_paddr_t *paddr, int prot) { gdc_softc_t *sc; sc = GDC_SOFTC(GDC_UNIT(dev)); return genfbmmap(&sc->gensc, sc->adp, offset, paddr, prot); } #endif /* FB_INSTALL_CDEV */ static device_method_t gdc_methods[] = { DEVMETHOD(device_identify, gdc_identify), DEVMETHOD(device_probe, gdcprobe), DEVMETHOD(device_attach, gdc_attach), { 0, 0 } }; static driver_t gdcdriver = { DRIVER_NAME, gdc_methods, sizeof(gdc_softc_t), }; DRIVER_MODULE(gdc, isa, gdcdriver, gdc_devclass, 0, 0); /* LOW-LEVEL */ #include #define TEXT_BUF_BASE 0x000a0000 #define TEXT_BUF_SIZE 0x00008000 #define GRAPHICS_BUF_BASE 0x000a8000 #define GRAPHICS_BUF_SIZE 0x00040000 #define VIDEO_BUF_BASE 0x000a0000 #define VIDEO_BUF_SIZE 0x00048000 #define probe_done(adp) ((adp)->va_flags & V_ADP_PROBED) #define init_done(adp) ((adp)->va_flags & V_ADP_INITIALIZED) #define config_done(adp) ((adp)->va_flags & V_ADP_REGISTERED) /* * NOTE: `va_window' should have a virtual address, but is initialized * with a physical address in the following table, they will be * converted at run-time. */ static video_adapter_t adapter_init_value[] = { { 0, KD_PC98, "gdc", /* va_type, va_name */ 0, 0, /* va_unit, va_minor */ V_ADP_COLOR | V_ADP_MODECHANGE | V_ADP_BORDER, TEXT_GDC, 16, TEXT_GDC, /* va_io*, XXX */ VIDEO_BUF_BASE, VIDEO_BUF_SIZE, /* va_mem* */ TEXT_BUF_BASE, TEXT_BUF_SIZE, TEXT_BUF_SIZE, 0, /* va_window* */ 0, 0, /* va_buffer, va_buffer_size */ 0, M_PC98_80x25, 0, /* va_*mode* */ }, }; static video_adapter_t biosadapter[1]; /* video driver declarations */ static int gdc_configure(int flags); static int gdc_err(video_adapter_t *adp, ...); static vi_probe_t gdc_probe; static vi_init_t gdc_init; static vi_get_info_t gdc_get_info; static vi_query_mode_t gdc_query_mode; static vi_set_mode_t gdc_set_mode; static vi_set_border_t gdc_set_border; static vi_save_state_t gdc_save_state; static vi_load_state_t gdc_load_state; static vi_read_hw_cursor_t gdc_read_hw_cursor; static vi_set_hw_cursor_t gdc_set_hw_cursor; static vi_set_hw_cursor_shape_t gdc_set_hw_cursor_shape; static vi_blank_display_t gdc_blank_display; static vi_mmap_t gdc_mmap_buf; static vi_ioctl_t gdc_dev_ioctl; static vi_clear_t gdc_clear; static vi_fill_rect_t gdc_fill_rect; static vi_bitblt_t gdc_bitblt; static vi_diag_t gdc_diag; static vi_save_palette_t gdc_save_palette; static vi_load_palette_t gdc_load_palette; static vi_set_win_org_t gdc_set_origin; static video_switch_t gdcvidsw = { gdc_probe, gdc_init, gdc_get_info, gdc_query_mode, gdc_set_mode, (vi_save_font_t *)gdc_err, (vi_load_font_t *)gdc_err, (vi_show_font_t *)gdc_err, gdc_save_palette, gdc_load_palette, gdc_set_border, gdc_save_state, gdc_load_state, gdc_set_origin, gdc_read_hw_cursor, gdc_set_hw_cursor, gdc_set_hw_cursor_shape, gdc_blank_display, gdc_mmap_buf, gdc_dev_ioctl, gdc_clear, gdc_fill_rect, gdc_bitblt, (int (*)(void))gdc_err, (int (*)(void))gdc_err, gdc_diag, }; VIDEO_DRIVER(gdc, gdcvidsw, gdc_configure); /* GDC BIOS standard video modes */ #define EOT (-1) #define NA (-2) static video_info_t bios_vmode[] = { { M_PC98_80x25, V_INFO_COLOR, 80, 25, 8, 16, 4, 1, TEXT_BUF_BASE, TEXT_BUF_SIZE, TEXT_BUF_SIZE, 0, 0, V_INFO_MM_TEXT }, #ifdef LINE30 { M_PC98_80x30, V_INFO_COLOR, 80, 30, 8, 16, 4, 1, TEXT_BUF_BASE, TEXT_BUF_SIZE, TEXT_BUF_SIZE, 0, 0, V_INFO_MM_TEXT }, #endif #ifndef GDC_NOGRAPHICS { M_PC98_EGC640x400, V_INFO_COLOR | V_INFO_GRAPHICS, 640, 400, 8, 16, 4, 4, GRAPHICS_BUF_BASE, GRAPHICS_BUF_SIZE, GRAPHICS_BUF_SIZE, 0, 0, V_INFO_MM_PLANAR }, { M_PC98_PEGC640x400, V_INFO_COLOR | V_INFO_GRAPHICS | V_INFO_VESA, 640, 400, 8, 16, 8, 1, GRAPHICS_BUF_BASE, 0x00008000, 0x00008000, 0, 0, V_INFO_MM_PACKED, 1 }, #ifdef LINE30 { M_PC98_PEGC640x480, V_INFO_COLOR | V_INFO_GRAPHICS | V_INFO_VESA, 640, 480, 8, 16, 8, 1, GRAPHICS_BUF_BASE, 0x00008000, 0x00008000, 0, 0, V_INFO_MM_PACKED, 1 }, #endif #endif { EOT }, }; static int gdc_init_done = FALSE; /* local functions */ static int map_gen_mode_num(int type, int color, int mode); static int probe_adapters(void); #define prologue(adp, flag, err) \ if (!gdc_init_done || !((adp)->va_flags & (flag))) \ return (err) /* a backdoor for the console driver */ static int gdc_configure(int flags) { probe_adapters(); biosadapter[0].va_flags |= V_ADP_INITIALIZED; if (!config_done(&biosadapter[0])) { if (vid_register(&biosadapter[0]) < 0) return 1; biosadapter[0].va_flags |= V_ADP_REGISTERED; } return 1; } /* local subroutines */ /* map a generic video mode to a known mode number */ static int map_gen_mode_num(int type, int color, int mode) { static struct { int from; int to; } mode_map[] = { { M_TEXT_80x25, M_PC98_80x25, }, #ifdef LINE30 { M_TEXT_80x30, M_PC98_80x30, }, #endif }; int i; for (i = 0; i < sizeof(mode_map)/sizeof(mode_map[0]); ++i) { if (mode_map[i].from == mode) return mode_map[i].to; } return mode; } static int verify_adapter(video_adapter_t *adp) { #ifndef GDC_NOGRAPHICS int i; if (PC98_SYSTEM_PARAMETER(0x45c) & 0x40) { /* PEGC exists */ adp->va_flags |= V_ADP_VESA; /* XXX */ } else { for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) { if (bios_vmode[i].vi_flags & V_INFO_VESA) bios_vmode[i].vi_mode = NA; } } #endif return 0; } /* probe video adapters and return the number of detected adapters */ static int probe_adapters(void) { video_info_t info; /* do this test only once */ if (gdc_init_done) return 1; gdc_init_done = TRUE; biosadapter[0] = adapter_init_value[0]; biosadapter[0].va_flags |= V_ADP_PROBED; biosadapter[0].va_mode = biosadapter[0].va_initial_mode = biosadapter[0].va_initial_bios_mode; if ((PC98_SYSTEM_PARAMETER(0x597) & 0x80) || (PC98_SYSTEM_PARAMETER(0x458) & 0x80)) { gdc_FH = (inb(0x9a8) & 1) ? _31KHZ : _24KHZ; } else { gdc_FH = _24KHZ; } gdc_get_info(&biosadapter[0], biosadapter[0].va_initial_mode, &info); initialize_gdc(T25_G400, info.vi_flags & V_INFO_GRAPHICS); biosadapter[0].va_window = BIOS_PADDRTOVADDR(info.vi_window); biosadapter[0].va_window_size = info.vi_window_size; biosadapter[0].va_window_gran = info.vi_window_gran; biosadapter[0].va_buffer = 0; biosadapter[0].va_buffer_size = 0; if (info.vi_flags & V_INFO_GRAPHICS) { switch (info.vi_depth/info.vi_planes) { case 1: biosadapter[0].va_line_width = info.vi_width/8; break; case 2: biosadapter[0].va_line_width = info.vi_width/4; break; case 4: biosadapter[0].va_line_width = info.vi_width/2; break; case 8: default: /* shouldn't happen */ biosadapter[0].va_line_width = info.vi_width; break; } } else { biosadapter[0].va_line_width = info.vi_width; } bcopy(&info, &biosadapter[0].va_info, sizeof(info)); verify_adapter(&biosadapter[0]); return 1; } static void master_gdc_cmd(unsigned int cmd) { while ( (inb(TEXT_GDC) & 2) != 0); outb(TEXT_GDC+2, cmd); } static void master_gdc_prm(unsigned int pmtr) { while ( (inb(TEXT_GDC) & 2) != 0); outb(TEXT_GDC, pmtr); } static void master_gdc_word_prm(unsigned int wpmtr) { master_gdc_prm(wpmtr & 0x00ff); master_gdc_prm((wpmtr >> 8) & 0x00ff); } #ifdef LINE30 static void master_gdc_fifo_empty(void) { while ( (inb(TEXT_GDC) & 4) == 0); } #endif static void master_gdc_wait_vsync(void) { while ( (inb(TEXT_GDC) & 0x20) != 0); while ( (inb(TEXT_GDC) & 0x20) == 0); } static void gdc_cmd(unsigned int cmd) { while ( (inb(GRAPHIC_GDC) & 2) != 0); outb( GRAPHIC_GDC+2, cmd); } #ifdef LINE30 static void gdc_prm(unsigned int pmtr) { while ( (inb(GRAPHIC_GDC) & 2) != 0); outb( GRAPHIC_GDC, pmtr); } static void gdc_word_prm(unsigned int wpmtr) { gdc_prm(wpmtr & 0x00ff); gdc_prm((wpmtr >> 8) & 0x00ff); } static void gdc_fifo_empty(void) { while ( (inb(GRAPHIC_GDC) & 0x04) == 0); } #endif static void gdc_wait_vsync(void) { while ( (inb(GRAPHIC_GDC) & 0x20) != 0); while ( (inb(GRAPHIC_GDC) & 0x20) == 0); } #ifdef LINE30 static int check_gdc_clock(void) { if ((inb(IO_SYSPORT) & 0x80) == 0){ return _5MHZ; } else { return _2_5MHZ; } } #endif static void initialize_gdc(unsigned int mode, int isGraph) { #ifdef LINE30 /* start 30line initialize */ int m_mode, s_mode, gdc_clock, hsync_clock; gdc_clock = check_gdc_clock(); m_mode = (mode == T25_G400) ? _25L : _30L; s_mode = 2*mode+gdc_clock; gdc_INFO = m_mode; master_gdc_wait_vsync(); if ((PC98_SYSTEM_PARAMETER(0x597) & 0x80) || (PC98_SYSTEM_PARAMETER(0x458) & 0x80)) { if (PC98_SYSTEM_PARAMETER(0x481) & 0x08) { hsync_clock = (m_mode == _25L) ? gdc_FH : _31KHZ; outb(0x9a8, (hsync_clock == _31KHZ) ? 1 : 0); } else { hsync_clock = gdc_FH; } } else { hsync_clock = _24KHZ; } if ((gdc_clock == _2_5MHZ) && (slave_param[hsync_clock][s_mode][GDC_LF] > 400)) { outb(0x6a, 0x83); outb(0x6a, 0x85); gdc_clock = _5MHZ; s_mode = 2*mode+gdc_clock; } master_gdc_cmd(_GDC_RESET); master_gdc_cmd(_GDC_MASTER); gdc_cmd(_GDC_RESET); gdc_cmd(_GDC_SLAVE); /* GDC Master */ master_gdc_cmd(_GDC_SYNC); master_gdc_prm(0x00); /* flush less */ /* text & graph */ master_gdc_prm(master_param[hsync_clock][m_mode][GDC_CR]); master_gdc_word_prm(((master_param[hsync_clock][m_mode][GDC_HFP] << 10) + (master_param[hsync_clock][m_mode][GDC_VS] << 5) + master_param[hsync_clock][m_mode][GDC_HS])); master_gdc_prm(master_param[hsync_clock][m_mode][GDC_HBP]); master_gdc_prm(master_param[hsync_clock][m_mode][GDC_VFP]); master_gdc_word_prm(((master_param[hsync_clock][m_mode][GDC_VBP] << 10) + (master_param[hsync_clock][m_mode][GDC_LF]))); master_gdc_fifo_empty(); master_gdc_cmd(_GDC_PITCH); master_gdc_prm(MasterPCH); master_gdc_fifo_empty(); /* GDC slave */ gdc_cmd(_GDC_SYNC); gdc_prm(0x06); gdc_prm(slave_param[hsync_clock][s_mode][GDC_CR]); gdc_word_prm((slave_param[hsync_clock][s_mode][GDC_HFP] << 10) + (slave_param[hsync_clock][s_mode][GDC_VS] << 5) + (slave_param[hsync_clock][s_mode][GDC_HS])); gdc_prm(slave_param[hsync_clock][s_mode][GDC_HBP]); gdc_prm(slave_param[hsync_clock][s_mode][GDC_VFP]); gdc_word_prm((slave_param[hsync_clock][s_mode][GDC_VBP] << 10) + (slave_param[hsync_clock][s_mode][GDC_LF])); gdc_fifo_empty(); gdc_cmd(_GDC_PITCH); gdc_prm(SlavePCH[gdc_clock]); gdc_fifo_empty(); /* set Master GDC scroll param */ master_gdc_wait_vsync(); master_gdc_wait_vsync(); master_gdc_wait_vsync(); master_gdc_cmd(_GDC_SCROLL); master_gdc_word_prm(0); master_gdc_word_prm((master_param[hsync_clock][m_mode][GDC_LF] << 4) | 0x0000); master_gdc_fifo_empty(); /* set Slave GDC scroll param */ gdc_wait_vsync(); gdc_cmd(_GDC_SCROLL); gdc_word_prm(0); if (gdc_clock == _5MHZ) { gdc_word_prm((SlaveScrlLF[mode] << 4) | 0x4000); } else { gdc_word_prm(SlaveScrlLF[mode] << 4); } gdc_fifo_empty(); gdc_word_prm(0); if (gdc_clock == _5MHZ) { gdc_word_prm((SlaveScrlLF[mode] << 4) | 0x4000); } else { gdc_word_prm(SlaveScrlLF[mode] << 4); } gdc_fifo_empty(); /* sync start */ gdc_cmd(isGraph ? _GDC_START : _GDC_STOP); gdc_wait_vsync(); gdc_wait_vsync(); gdc_wait_vsync(); master_gdc_cmd(isGraph ? _GDC_STOP : _GDC_START); #else master_gdc_wait_vsync(); master_gdc_cmd(isGraph ? _GDC_STOP : _GDC_START); /* text */ gdc_wait_vsync(); gdc_cmd(isGraph ? _GDC_START : _GDC_STOP); /* graphics */ #endif } #ifndef GDC_NOGRAPHICS static u_char b_palette[] = { /* R G B */ 0x00, 0x00, 0x00, /* 0 */ 0x00, 0x00, 0x7f, /* 1 */ 0x7f, 0x00, 0x00, /* 2 */ 0x7f, 0x00, 0x7f, /* 3 */ 0x00, 0x7f, 0x00, /* 4 */ 0x00, 0x7f, 0x7f, /* 5 */ 0x7f, 0x7f, 0x00, /* 6 */ 0x7f, 0x7f, 0x7f, /* 7 */ 0x40, 0x40, 0x40, /* 8 */ 0x00, 0x00, 0xff, /* 9 */ 0xff, 0x00, 0x00, /* 10 */ 0xff, 0x00, 0xff, /* 11 */ 0x00, 0xff, 0x00, /* 12 */ 0x00, 0xff, 0xff, /* 13 */ 0xff, 0xff, 0x00, /* 14 */ 0xff, 0xff, 0xff, /* 15 */ }; #endif static int gdc_load_palette(video_adapter_t *adp, u_char *palette) { #ifndef GDC_NOGRAPHICS int i; if (adp->va_info.vi_flags & V_INFO_VESA) { gdc_wait_vsync(); for (i = 0; i < 256; ++i) { outb(0xa8, i); outb(0xac, *palette++); /* R */ outb(0xaa, *palette++); /* G */ outb(0xae, *palette++); /* B */ } } else { /* * XXX - Even though PC-98 text color is independent of palette, * we should set palette in text mode. * Because the background color of text mode is palette 0's one. */ outb(0x6a, 1); /* 16 colors mode */ bcopy(palette, b_palette, sizeof(b_palette)); gdc_wait_vsync(); for (i = 0; i < 16; ++i) { outb(0xa8, i); outb(0xac, *palette++ >> 4); /* R */ outb(0xaa, *palette++ >> 4); /* G */ outb(0xae, *palette++ >> 4); /* B */ } } #endif return 0; } static int gdc_save_palette(video_adapter_t *adp, u_char *palette) { #ifndef GDC_NOGRAPHICS int i; if (adp->va_info.vi_flags & V_INFO_VESA) { for (i = 0; i < 256; ++i) { outb(0xa8, i); *palette++ = inb(0xac); /* R */ *palette++ = inb(0xaa); /* G */ *palette++ = inb(0xae); /* B */ } } else { bcopy(b_palette, palette, sizeof(b_palette)); } #endif return 0; } static int gdc_set_origin(video_adapter_t *adp, off_t offset) { #ifndef GDC_NOGRAPHICS if (adp->va_info.vi_flags & V_INFO_VESA) { writew(BIOS_PADDRTOVADDR(0x000e0004), offset >> 15); } #endif return 0; } /* entry points */ static int gdc_err(video_adapter_t *adp, ...) { return ENODEV; } static int gdc_probe(int unit, video_adapter_t **adpp, void *arg, int flags) { probe_adapters(); if (unit >= 1) return ENXIO; *adpp = &biosadapter[unit]; return 0; } static int gdc_init(int unit, video_adapter_t *adp, int flags) { if ((unit >= 1) || (adp == NULL) || !probe_done(adp)) return ENXIO; if (!init_done(adp)) { /* nothing to do really... */ adp->va_flags |= V_ADP_INITIALIZED; } if (!config_done(adp)) { if (vid_register(adp) < 0) return ENXIO; adp->va_flags |= V_ADP_REGISTERED; } return 0; } /* * get_info(): * Return the video_info structure of the requested video mode. */ static int gdc_get_info(video_adapter_t *adp, int mode, video_info_t *info) { int i; if (!gdc_init_done) return ENXIO; mode = map_gen_mode_num(adp->va_type, adp->va_flags & V_ADP_COLOR, mode); for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) { if (bios_vmode[i].vi_mode == NA) continue; if (mode == bios_vmode[i].vi_mode) { *info = bios_vmode[i]; info->vi_buffer_size = info->vi_window_size*info->vi_planes; return 0; } } return EINVAL; } /* * query_mode(): * Find a video mode matching the requested parameters. * Fields filled with 0 are considered "don't care" fields and * match any modes. */ static int gdc_query_mode(video_adapter_t *adp, video_info_t *info) { int i; if (!gdc_init_done) return ENXIO; for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) { if (bios_vmode[i].vi_mode == NA) continue; if ((info->vi_width != 0) && (info->vi_width != bios_vmode[i].vi_width)) continue; if ((info->vi_height != 0) && (info->vi_height != bios_vmode[i].vi_height)) continue; if ((info->vi_cwidth != 0) && (info->vi_cwidth != bios_vmode[i].vi_cwidth)) continue; if ((info->vi_cheight != 0) && (info->vi_cheight != bios_vmode[i].vi_cheight)) continue; if ((info->vi_depth != 0) && (info->vi_depth != bios_vmode[i].vi_depth)) continue; if ((info->vi_planes != 0) && (info->vi_planes != bios_vmode[i].vi_planes)) continue; /* XXX: should check pixel format, memory model */ if ((info->vi_flags != 0) && (info->vi_flags != bios_vmode[i].vi_flags)) continue; /* verify if this mode is supported on this adapter */ if (gdc_get_info(adp, bios_vmode[i].vi_mode, info)) continue; return 0; } return ENODEV; } /* * set_mode(): * Change the video mode. */ static int gdc_set_mode(video_adapter_t *adp, int mode) { video_info_t info; prologue(adp, V_ADP_MODECHANGE, ENODEV); mode = map_gen_mode_num(adp->va_type, adp->va_flags & V_ADP_COLOR, mode); if (gdc_get_info(adp, mode, &info)) return EINVAL; switch (info.vi_mode) { #ifndef GDC_NOGRAPHICS case M_PC98_PEGC640x480: /* PEGC 640x480 */ initialize_gdc(T30_G480, info.vi_flags & V_INFO_GRAPHICS); break; case M_PC98_PEGC640x400: /* PEGC 640x400 */ case M_PC98_EGC640x400: /* EGC GRAPHICS */ #endif case M_PC98_80x25: /* VGA TEXT */ initialize_gdc(T25_G400, info.vi_flags & V_INFO_GRAPHICS); break; case M_PC98_80x30: /* VGA TEXT */ initialize_gdc(T30_G400, info.vi_flags & V_INFO_GRAPHICS); break; default: break; } #ifndef GDC_NOGRAPHICS if (info.vi_flags & V_INFO_VESA) { outb(0x6a, 0x07); /* enable mode F/F change */ outb(0x6a, 0x21); /* enhanced graphics */ if (info.vi_height > 400) outb(0x6a, 0x69); /* 800 lines */ writeb(BIOS_PADDRTOVADDR(0x000e0100), 0); /* packed pixel */ } else { if (adp->va_flags & V_ADP_VESA) { outb(0x6a, 0x07); /* enable mode F/F change */ outb(0x6a, 0x20); /* normal graphics */ outb(0x6a, 0x68); /* 400 lines */ } outb(0x6a, 1); /* 16 colors */ } #endif adp->va_mode = mode; adp->va_flags &= ~V_ADP_COLOR; adp->va_flags |= (info.vi_flags & V_INFO_COLOR) ? V_ADP_COLOR : 0; #if 0 adp->va_crtc_addr = (adp->va_flags & V_ADP_COLOR) ? COLOR_CRTC : MONO_CRTC; #endif adp->va_window = BIOS_PADDRTOVADDR(info.vi_window); adp->va_window_size = info.vi_window_size; adp->va_window_gran = info.vi_window_gran; if (info.vi_buffer_size == 0) { adp->va_buffer = 0; adp->va_buffer_size = 0; } else { adp->va_buffer = BIOS_PADDRTOVADDR(info.vi_buffer); adp->va_buffer_size = info.vi_buffer_size; } if (info.vi_flags & V_INFO_GRAPHICS) { switch (info.vi_depth/info.vi_planes) { case 1: adp->va_line_width = info.vi_width/8; break; case 2: adp->va_line_width = info.vi_width/4; break; case 4: adp->va_line_width = info.vi_width/2; break; case 8: default: /* shouldn't happen */ adp->va_line_width = info.vi_width; break; } } else { adp->va_line_width = info.vi_width; } bcopy(&info, &adp->va_info, sizeof(info)); /* move hardware cursor out of the way */ (*vidsw[adp->va_index]->set_hw_cursor)(adp, -1, -1); return 0; } /* * set_border(): * Change the border color. */ static int gdc_set_border(video_adapter_t *adp, int color) { outb(0x6c, color << 4); return 0; } /* * save_state(): * Read video card register values. */ static int gdc_save_state(video_adapter_t *adp, void *p, size_t size) { return ENODEV; } /* * load_state(): * Set video card registers at once. */ static int gdc_load_state(video_adapter_t *adp, void *p) { return ENODEV; } /* * read_hw_cursor(): * Read the position of the hardware text cursor. */ static int gdc_read_hw_cursor(video_adapter_t *adp, int *col, int *row) { u_int16_t off; int s; if (!gdc_init_done) return ENXIO; if (adp->va_info.vi_flags & V_INFO_GRAPHICS) return ENODEV; s = spltty(); master_gdc_cmd(0xe0); /* _GDC_CSRR */ while((inb(TEXT_GDC + 0) & 0x1) == 0) {} /* GDC wait */ off = inb(TEXT_GDC + 2); /* EADl */ off |= (inb(TEXT_GDC + 2) << 8); /* EADh */ inb(TEXT_GDC + 2); /* dummy */ inb(TEXT_GDC + 2); /* dummy */ inb(TEXT_GDC + 2); /* dummy */ splx(s); if (off >= ROW*COL) off = 0; *row = off / adp->va_info.vi_width; *col = off % adp->va_info.vi_width; return 0; } /* * set_hw_cursor(): * Move the hardware text cursor. If col and row are both -1, * the cursor won't be shown. */ static int gdc_set_hw_cursor(video_adapter_t *adp, int col, int row) { u_int16_t off; int s; if (!gdc_init_done) return ENXIO; if ((col == -1) && (row == -1)) { off = -1; } else { if (adp->va_info.vi_flags & V_INFO_GRAPHICS) return ENODEV; off = row*adp->va_info.vi_width + col; } s = spltty(); master_gdc_cmd(0x49); /* _GDC_CSRW */ master_gdc_word_prm(off); splx(s); return 0; } /* * set_hw_cursor_shape(): * Change the shape of the hardware text cursor. If the height is zero * or negative, the cursor won't be shown. */ static int gdc_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, int celsize, int blink) { int start; int end; int s; if (!gdc_init_done) return ENXIO; start = celsize - (base + height); end = celsize - base - 1; #if 0 /* * muPD7220 GDC has anomaly that if end == celsize - 1 then start * must be 0, otherwise the cursor won't be correctly shown * in the first row in the screen. We shall set end to celsize - 2; * if end == celsize -1 && start > 0. XXX */ if ((end == celsize - 1) && (start > 0) && (start < end)) --end; #endif s = spltty(); master_gdc_cmd(0x4b); /* _GDC_CSRFORM */ master_gdc_prm(((height > 0) ? 0x80 : 0) /* cursor on/off */ | ((celsize - 1) & 0x1f)); /* cel size */ master_gdc_word_prm(((end & 0x1f) << 11) /* end line */ | (12 << 6) /* blink rate */ | (blink ? 0 : 0x20) /* blink on/off */ | (start & 0x1f)); /* start line */ splx(s); return 0; } /* * blank_display() * Put the display in power save/power off mode. */ static int gdc_blank_display(video_adapter_t *adp, int mode) { int s; static int standby = 0; if (!gdc_init_done) return ENXIO; s = splhigh(); switch (mode) { case V_DISPLAY_SUSPEND: case V_DISPLAY_STAND_BY: outb(0x09a2, 0x80 | 0x40); /* V/H-SYNC mask */ if (inb(0x09a2) == (0x80 | 0x40)) standby = 1; /* FALLTHROUGH */ case V_DISPLAY_BLANK: if (epson_machine_id == 0x20) { outb(0x43f, 0x42); outb(0xc17, inb(0xc17) & ~0x08); /* turn off side light */ outb(0xc16, inb(0xc16) & ~0x02); /* turn off back light */ outb(0x43f, 0x40); } else { while (!(inb(TEXT_GDC) & 0x20)) /* V-SYNC wait */ ; outb(TEXT_GDC + 8, 0x0e); /* DISP off */ } break; case V_DISPLAY_ON: if (epson_machine_id == 0x20) { outb(0x43f, 0x42); outb(0xc17, inb(0xc17) | 0x08); outb(0xc16, inb(0xc16) | 0x02); outb(0x43f, 0x40); } else { while (!(inb(TEXT_GDC) & 0x20)) /* V-SYNC wait */ ; outb(TEXT_GDC + 8, 0x0f); /* DISP on */ } if (standby) { outb(0x09a2, 0x00); /* V/H-SYNC unmask */ standby = 0; } break; } splx(s); return 0; } /* * mmap(): * Mmap frame buffer. */ static int gdc_mmap_buf(video_adapter_t *adp, vm_offset_t offset, vm_offset_t *paddr, int prot) { /* FIXME: is this correct? XXX */ if (offset > VIDEO_BUF_SIZE - PAGE_SIZE) return -1; *paddr = adp->va_info.vi_window + offset; return 0; } #ifndef GDC_NOGRAPHICS static void planar_fill(video_adapter_t *adp, int val) { outb(0x7c, 0x80); /* GRCG on & TDW mode */ outb(0x7e, 0); /* tile B */ outb(0x7e, 0); /* tile R */ outb(0x7e, 0); /* tile G */ outb(0x7e, 0); /* tile I */ fillw_io(0, adp->va_window, 0x8000 / 2); /* XXX */ outb(0x7c, 0); /* GRCG off */ } static void packed_fill(video_adapter_t *adp, int val) { int length; int at; /* position in the frame buffer */ int l; at = 0; length = adp->va_line_width*adp->va_info.vi_height; while (length > 0) { l = imin(length, adp->va_window_size); (*vidsw[adp->va_index]->set_win_org)(adp, at); bzero_io(adp->va_window, l); length -= l; at += l; } } static int gdc_clear(video_adapter_t *adp) { switch (adp->va_info.vi_mem_model) { case V_INFO_MM_TEXT: /* do nothing? XXX */ break; case V_INFO_MM_PLANAR: planar_fill(adp, 0); break; case V_INFO_MM_PACKED: packed_fill(adp, 0); break; } return 0; } #else /* GDC_NOGRAPHICS */ static int gdc_clear(video_adapter_t *adp) { return 0; } #endif /* GDC_NOGRAPHICS */ static int gdc_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) { return ENODEV; } static int gdc_bitblt(video_adapter_t *adp,...) { /* FIXME */ return ENODEV; } static int gdc_dev_ioctl(video_adapter_t *adp, u_long cmd, caddr_t arg) { switch (cmd) { case FBIO_GETWINORG: /* get frame buffer window origin */ *(u_int *)arg = 0; return 0; case FBIO_SETWINORG: /* set frame buffer window origin */ case FBIO_SETDISPSTART: /* set display start address */ case FBIO_SETLINEWIDTH: /* set scan line length in pixel */ case FBIO_GETPALETTE: /* get color palette */ case FBIO_SETPALETTE: /* set color palette */ case FBIOGETCMAP: /* get color palette */ case FBIOPUTCMAP: /* set color palette */ return ENODEV; case FBIOGTYPE: /* get frame buffer type info. */ ((struct fbtype *)arg)->fb_type = fb_type(adp->va_type); ((struct fbtype *)arg)->fb_height = adp->va_info.vi_height; ((struct fbtype *)arg)->fb_width = adp->va_info.vi_width; ((struct fbtype *)arg)->fb_depth = adp->va_info.vi_depth; if ((adp->va_info.vi_depth <= 1) || (adp->va_info.vi_depth > 8)) ((struct fbtype *)arg)->fb_cmsize = 0; else ((struct fbtype *)arg)->fb_cmsize = 1 << adp->va_info.vi_depth; ((struct fbtype *)arg)->fb_size = adp->va_buffer_size; return 0; default: return fb_commonioctl(adp, cmd, arg); } } /* * diag(): * Print some information about the video adapter and video modes, * with requested level of details. */ static int gdc_diag(video_adapter_t *adp, int level) { #if FB_DEBUG > 1 int i; #endif if (!gdc_init_done) return ENXIO; fb_dump_adp_info(DRIVER_NAME, adp, level); #if FB_DEBUG > 1 for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) { if (bios_vmode[i].vi_mode == NA) continue; if (get_mode_param(bios_vmode[i].vi_mode) == NULL) continue; fb_dump_mode_info(DRIVER_NAME, adp, &bios_vmode[i], level); } #endif return 0; } Index: head/sys/pc98/pc98/ppc.c =================================================================== --- head/sys/pc98/pc98/ppc.c (revision 130173) +++ head/sys/pc98/pc98/ppc.c (revision 130174) @@ -1,2210 +1,2211 @@ /*- * Copyright (c) 2001 Alcove - Nicolas Souchu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include "opt_ppc.h" #include #include #include +#include #include #include #include #include #include #include #include #ifdef PC98 #include #else #include #endif #include #include #include #include #ifdef PC98 #include #else #include #endif #include "ppbus_if.h" static int ppc_cbus_probe(device_t dev); static void ppcintr(void *arg); #define LOG_PPC(function, ppc, string) \ if (bootverbose) printf("%s: %s\n", function, string) #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) devclass_t ppc_devclass; static device_method_t ppc_methods[] = { /* device interface */ DEVMETHOD(device_probe, ppc_cbus_probe), DEVMETHOD(device_attach, ppc_attach), /* bus interface */ DEVMETHOD(bus_read_ivar, ppc_read_ivar), DEVMETHOD(bus_setup_intr, ppc_setup_intr), DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), /* ppbus interface */ DEVMETHOD(ppbus_io, ppc_io), DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), DEVMETHOD(ppbus_setmode, ppc_setmode), DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), DEVMETHOD(ppbus_read, ppc_read), DEVMETHOD(ppbus_write, ppc_write), { 0, 0 } }; static driver_t ppc_driver = { "ppc", ppc_methods, sizeof(struct ppc_data), }; static char *ppc_models[] = { "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", "SMC FDC37C935", "PC87303", 0 }; /* list of available modes */ static char *ppc_avms[] = { "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 }; /* list of current executing modes * Note that few modes do not actually exist. */ static char *ppc_modes[] = { "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", "EPP", "EPP", "EPP", "ECP", "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 }; static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; #ifdef __i386__ /* * BIOS printer list - used by BIOS probe. */ #define BIOS_PPC_PORTS 0x408 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) #define BIOS_MAX_PPC 4 #endif /* * ppc_ecp_sync() XXX */ void ppc_ecp_sync(device_t dev) { int i, r; struct ppc_data *ppc = DEVTOSOFTC(dev); if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) return; r = r_ecr(ppc); if ((r & 0xe0) != PPC_ECR_EPP) return; for (i = 0; i < 100; i++) { r = r_ecr(ppc); if (r & 0x1) return; DELAY(100); } printf("ppc%d: ECP sync failed as data still " \ "present in FIFO.\n", ppc->ppc_unit); return; } /* * ppc_detect_fifo() * * Detect parallel port FIFO */ static int ppc_detect_fifo(struct ppc_data *ppc) { char ecr_sav; char ctr_sav, ctr, cc; short i; /* save registers */ ecr_sav = r_ecr(ppc); ctr_sav = r_ctr(ppc); /* enter ECP configuration mode, no interrupt, no DMA */ w_ecr(ppc, 0xf4); /* read PWord size - transfers in FIFO mode must be PWord aligned */ ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); /* XXX 16 and 32 bits implementations not supported */ if (ppc->ppc_pword != PPC_PWORD_8) { LOG_PPC(__func__, ppc, "PWord not supported"); goto error; } w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ ctr = r_ctr(ppc); w_ctr(ppc, ctr | PCD); /* set direction to 1 */ /* enter ECP test mode, no interrupt, no DMA */ w_ecr(ppc, 0xd4); /* flush the FIFO */ for (i=0; i<1024; i++) { if (r_ecr(ppc) & PPC_FIFO_EMPTY) break; cc = r_fifo(ppc); } if (i >= 1024) { LOG_PPC(__func__, ppc, "can't flush FIFO"); goto error; } /* enable interrupts, no DMA */ w_ecr(ppc, 0xd0); /* determine readIntrThreshold * fill the FIFO until serviceIntr is set */ for (i=0; i<1024; i++) { w_fifo(ppc, (char)i); if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { /* readThreshold reached */ ppc->ppc_rthr = i+1; } if (r_ecr(ppc) & PPC_FIFO_FULL) { ppc->ppc_fifo = i+1; break; } } if (i >= 1024) { LOG_PPC(__func__, ppc, "can't fill FIFO"); goto error; } w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ w_ecr(ppc, 0xd0); /* enable interrupts */ /* determine writeIntrThreshold * empty the FIFO until serviceIntr is set */ for (i=ppc->ppc_fifo; i>0; i--) { if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { LOG_PPC(__func__, ppc, "invalid data in FIFO"); goto error; } if (r_ecr(ppc) & PPC_SERVICE_INTR) { /* writeIntrThreshold reached */ ppc->ppc_wthr = ppc->ppc_fifo - i+1; } /* if FIFO empty before the last byte, error */ if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { LOG_PPC(__func__, ppc, "data lost in FIFO"); goto error; } } /* FIFO must be empty after the last byte */ if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { LOG_PPC(__func__, ppc, "can't empty the FIFO"); goto error; } w_ctr(ppc, ctr_sav); w_ecr(ppc, ecr_sav); return (0); error: w_ctr(ppc, ctr_sav); w_ecr(ppc, ecr_sav); return (EINVAL); } static int ppc_detect_port(struct ppc_data *ppc) { w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ w_dtr(ppc, 0xaa); if (r_dtr(ppc) != 0xaa) return (0); return (1); } /* * EPP timeout, according to the PC87332 manual * Semantics of clearing EPP timeout bit. * PC87332 - reading SPP_STR does it... * SMC - write 1 to EPP timeout bit XXX * Others - (?) write 0 to EPP timeout bit */ static void ppc_reset_epp_timeout(struct ppc_data *ppc) { register char r; r = r_str(ppc); w_str(ppc, r | 0x1); w_str(ppc, r & 0xfe); return; } static int ppc_check_epp_timeout(struct ppc_data *ppc) { ppc_reset_epp_timeout(ppc); return (!(r_str(ppc) & TIMEOUT)); } /* * Configure current operating mode */ static int ppc_generic_setmode(struct ppc_data *ppc, int mode) { u_char ecr = 0; /* check if mode is available */ if (mode && !(ppc->ppc_avm & mode)) return (EINVAL); /* if ECP mode, configure ecr register */ if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { /* return to byte mode (keeping direction bit), * no interrupt, no DMA to be able to change to * ECP */ w_ecr(ppc, PPC_ECR_RESET); ecr = PPC_DISABLE_INTR; if (mode & PPB_EPP) return (EINVAL); else if (mode & PPB_ECP) /* select ECP mode */ ecr |= PPC_ECR_ECP; else if (mode & PPB_PS2) /* select PS2 mode with ECP */ ecr |= PPC_ECR_PS2; else /* select COMPATIBLE/NIBBLE mode */ ecr |= PPC_ECR_STD; w_ecr(ppc, ecr); } ppc->ppc_mode = mode; return (0); } /* * The ppc driver is free to choose options like FIFO or DMA * if ECP mode is available. * * The 'RAW' option allows the upper drivers to force the ppc mode * even with FIFO, DMA available. */ static int ppc_smclike_setmode(struct ppc_data *ppc, int mode) { u_char ecr = 0; /* check if mode is available */ if (mode && !(ppc->ppc_avm & mode)) return (EINVAL); /* if ECP mode, configure ecr register */ if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { /* return to byte mode (keeping direction bit), * no interrupt, no DMA to be able to change to * ECP or EPP mode */ w_ecr(ppc, PPC_ECR_RESET); ecr = PPC_DISABLE_INTR; if (mode & PPB_EPP) /* select EPP mode */ ecr |= PPC_ECR_EPP; else if (mode & PPB_ECP) /* select ECP mode */ ecr |= PPC_ECR_ECP; else if (mode & PPB_PS2) /* select PS2 mode with ECP */ ecr |= PPC_ECR_PS2; else /* select COMPATIBLE/NIBBLE mode */ ecr |= PPC_ECR_STD; w_ecr(ppc, ecr); } ppc->ppc_mode = mode; return (0); } #ifdef PPC_PROBE_CHIPSET /* * ppc_pc873xx_detect * * Probe for a Natsemi PC873xx-family part. * * References in this function are to the National Semiconductor * PC87332 datasheet TL/C/11930, May 1995 revision. */ static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; static int pc873xx_irqtab[] = {5, 7, 5, 0}; static int pc873xx_regstab[] = { PC873_FER, PC873_FAR, PC873_PTR, PC873_FCR, PC873_PCR, PC873_PMC, PC873_TUP, PC873_SID, PC873_PNP0, PC873_PNP1, PC873_LPTBA, -1 }; static char *pc873xx_rnametab[] = { "FER", "FAR", "PTR", "FCR", "PCR", "PMC", "TUP", "SID", "PNP0", "PNP1", "LPTBA", NULL }; static int ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ { static int index = 0; int idport, irq; int ptr, pcr, val, i; while ((idport = pc873xx_basetab[index++])) { /* XXX should check first to see if this location is already claimed */ /* * Pull the 873xx through the power-on ID cycle (2.2,1.). * We can't use this to locate the chip as it may already have * been used by the BIOS. */ (void)inb(idport); (void)inb(idport); (void)inb(idport); (void)inb(idport); /* * Read the SID byte. Possible values are : * * 01010xxx PC87334 * 0001xxxx PC87332 * 01110xxx PC87306 * 00110xxx PC87303 */ outb(idport, PC873_SID); val = inb(idport + 1); if ((val & 0xf0) == 0x10) { ppc->ppc_model = NS_PC87332; } else if ((val & 0xf8) == 0x70) { ppc->ppc_model = NS_PC87306; } else if ((val & 0xf8) == 0x50) { ppc->ppc_model = NS_PC87334; } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the documentation, but probing yielded 0x40... */ ppc->ppc_model = NS_PC87303; } else { if (bootverbose && (val != 0xff)) printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); continue ; /* not recognised */ } /* print registers */ if (bootverbose) { printf("PC873xx"); for (i=0; pc873xx_regstab[i] != -1; i++) { outb(idport, pc873xx_regstab[i]); printf(" %s=0x%x", pc873xx_rnametab[i], inb(idport + 1) & 0xff); } printf("\n"); } /* * We think we have one. Is it enabled and where we want it to be? */ outb(idport, PC873_FER); val = inb(idport + 1); if (!(val & PC873_PPENABLE)) { if (bootverbose) printf("PC873xx parallel port disabled\n"); continue; } outb(idport, PC873_FAR); val = inb(idport + 1); /* XXX we should create a driver instance for every port found */ if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { /* First try to change the port address to that requested... */ switch(ppc->ppc_base) { case 0x378: val &= 0xfc; break; case 0x3bc: val &= 0xfd; break; case 0x278: val &= 0xfe; break; default: val &= 0xfd; break; } outb(idport, PC873_FAR); outb(idport + 1, val); outb(idport + 1, val); /* Check for success by reading back the value we supposedly wrote and comparing...*/ outb(idport, PC873_FAR); val = inb(idport + 1) & 0x3; /* If we fail, report the failure... */ if (pc873xx_porttab[val] != ppc->ppc_base) { if (bootverbose) printf("PC873xx at 0x%x not for driver at port 0x%x\n", pc873xx_porttab[val], ppc->ppc_base); } continue; } outb(idport, PC873_PTR); ptr = inb(idport + 1); /* get irq settings */ if (ppc->ppc_base == 0x378) irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; else irq = pc873xx_irqtab[val]; if (bootverbose) printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); /* * Check if irq settings are correct */ if (irq != ppc->ppc_irq) { /* * If the chipset is not locked and base address is 0x378, * we have another chance */ if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { if (ppc->ppc_irq == 7) { outb(idport + 1, (ptr | PC873_LPTBIRQ7)); outb(idport + 1, (ptr | PC873_LPTBIRQ7)); } else { outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); } if (bootverbose) printf("PC873xx irq set to %d\n", ppc->ppc_irq); } else { if (bootverbose) printf("PC873xx sorry, can't change irq setting\n"); } } else { if (bootverbose) printf("PC873xx irq settings are correct\n"); } outb(idport, PC873_PCR); pcr = inb(idport + 1); if ((ptr & PC873_CFGLOCK) || !chipset_mode) { if (bootverbose) printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); ppc->ppc_avm |= PPB_NIBBLE; if (bootverbose) printf(", NIBBLE"); if (pcr & PC873_EPPEN) { ppc->ppc_avm |= PPB_EPP; if (bootverbose) printf(", EPP"); if (pcr & PC873_EPP19) ppc->ppc_epp = EPP_1_9; else ppc->ppc_epp = EPP_1_7; if ((ppc->ppc_model == NS_PC87332) && bootverbose) { outb(idport, PC873_PTR); ptr = inb(idport + 1); if (ptr & PC873_EPPRDIR) printf(", Regular mode"); else printf(", Automatic mode"); } } else if (pcr & PC873_ECPEN) { ppc->ppc_avm |= PPB_ECP; if (bootverbose) printf(", ECP"); if (pcr & PC873_ECPCLK) { /* XXX */ ppc->ppc_avm |= PPB_PS2; if (bootverbose) printf(", PS/2"); } } else { outb(idport, PC873_PTR); ptr = inb(idport + 1); if (ptr & PC873_EXTENDED) { ppc->ppc_avm |= PPB_SPP; if (bootverbose) printf(", SPP"); } } } else { if (bootverbose) printf("PC873xx unlocked"); if (chipset_mode & PPB_ECP) { if ((chipset_mode & PPB_EPP) && bootverbose) printf(", ECP+EPP not supported"); pcr &= ~PC873_EPPEN; pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ outb(idport + 1, pcr); outb(idport + 1, pcr); if (bootverbose) printf(", ECP"); } else if (chipset_mode & PPB_EPP) { pcr &= ~(PC873_ECPEN | PC873_ECPCLK); pcr |= (PC873_EPPEN | PC873_EPP19); outb(idport + 1, pcr); outb(idport + 1, pcr); ppc->ppc_epp = EPP_1_9; /* XXX */ if (bootverbose) printf(", EPP1.9"); /* enable automatic direction turnover */ if (ppc->ppc_model == NS_PC87332) { outb(idport, PC873_PTR); ptr = inb(idport + 1); ptr &= ~PC873_EPPRDIR; outb(idport + 1, ptr); outb(idport + 1, ptr); if (bootverbose) printf(", Automatic mode"); } } else { pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); outb(idport + 1, pcr); outb(idport + 1, pcr); /* configure extended bit in PTR */ outb(idport, PC873_PTR); ptr = inb(idport + 1); if (chipset_mode & PPB_PS2) { ptr |= PC873_EXTENDED; if (bootverbose) printf(", PS/2"); } else { /* default to NIBBLE mode */ ptr &= ~PC873_EXTENDED; if (bootverbose) printf(", NIBBLE"); } outb(idport + 1, ptr); outb(idport + 1, ptr); } ppc->ppc_avm = chipset_mode; } if (bootverbose) printf("\n"); ppc->ppc_type = PPC_TYPE_GENERIC; ppc_generic_setmode(ppc, chipset_mode); return(chipset_mode); } return(-1); } /* * ppc_smc37c66xgt_detect * * SMC FDC37C66xGT configuration. */ static int ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) { int s, i; u_char r; int type = -1; int csr = SMC66x_CSR; /* initial value is 0x3F0 */ int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ /* * Detection: enter configuration mode and read CRD register. */ s = splhigh(); outb(csr, SMC665_iCODE); outb(csr, SMC665_iCODE); splx(s); outb(csr, 0xd); if (inb(cio) == 0x65) { type = SMC_37C665GT; goto config; } for (i = 0; i < 2; i++) { s = splhigh(); outb(csr, SMC666_iCODE); outb(csr, SMC666_iCODE); splx(s); outb(csr, 0xd); if (inb(cio) == 0x66) { type = SMC_37C666GT; break; } /* Another chance, CSR may be hard-configured to be at 0x370 */ csr = SMC666_CSR; } config: /* * If chipset not found, do not continue. */ if (type == -1) return (-1); /* select CR1 */ outb(csr, 0x1); /* read the port's address: bits 0 and 1 of CR1 */ r = inb(cio) & SMC_CR1_ADDR; if (port_address[(int)r] != ppc->ppc_base) return (-1); ppc->ppc_model = type; /* * CR1 and CR4 registers bits 3 and 0/1 for mode configuration * If SPP mode is detected, try to set ECP+EPP mode */ if (bootverbose) { outb(csr, 0x1); printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, inb(cio) & 0xff); outb(csr, 0x4); printf(" CR4=0x%x", inb(cio) & 0xff); } /* select CR1 */ outb(csr, 0x1); if (!chipset_mode) { /* autodetect mode */ /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ if (type == SMC_37C666GT) { ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; if (bootverbose) printf(" configuration hardwired, supposing " \ "ECP+EPP SPP"); } else if ((inb(cio) & SMC_CR1_MODE) == 0) { /* already in extended parallel port mode, read CR4 */ outb(csr, 0x4); r = (inb(cio) & SMC_CR4_EMODE); switch (r) { case SMC_SPP: ppc->ppc_avm |= PPB_SPP; if (bootverbose) printf(" SPP"); break; case SMC_EPPSPP: ppc->ppc_avm |= PPB_EPP | PPB_SPP; if (bootverbose) printf(" EPP SPP"); break; case SMC_ECP: ppc->ppc_avm |= PPB_ECP | PPB_SPP; if (bootverbose) printf(" ECP SPP"); break; case SMC_ECPEPP: ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; if (bootverbose) printf(" ECP+EPP SPP"); break; } } else { /* not an extended port mode */ ppc->ppc_avm |= PPB_SPP; if (bootverbose) printf(" SPP"); } } else { /* mode forced */ ppc->ppc_avm = chipset_mode; /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ if (type == SMC_37C666GT) goto end_detect; r = inb(cio); if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { /* do not use ECP when the mode is not forced to */ outb(cio, r | SMC_CR1_MODE); if (bootverbose) printf(" SPP"); } else { /* an extended mode is selected */ outb(cio, r & ~SMC_CR1_MODE); /* read CR4 register and reset mode field */ outb(csr, 0x4); r = inb(cio) & ~SMC_CR4_EMODE; if (chipset_mode & PPB_ECP) { if (chipset_mode & PPB_EPP) { outb(cio, r | SMC_ECPEPP); if (bootverbose) printf(" ECP+EPP"); } else { outb(cio, r | SMC_ECP); if (bootverbose) printf(" ECP"); } } else { /* PPB_EPP is set */ outb(cio, r | SMC_EPPSPP); if (bootverbose) printf(" EPP SPP"); } } ppc->ppc_avm = chipset_mode; } /* set FIFO threshold to 16 */ if (ppc->ppc_avm & PPB_ECP) { /* select CRA */ outb(csr, 0xa); outb(cio, 16); } end_detect: if (bootverbose) printf ("\n"); if (ppc->ppc_avm & PPB_EPP) { /* select CR4 */ outb(csr, 0x4); r = inb(cio); /* * Set the EPP protocol... * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 */ if (ppc->ppc_epp == EPP_1_9) outb(cio, (r & ~SMC_CR4_EPPTYPE)); else outb(cio, (r | SMC_CR4_EPPTYPE)); } /* end config mode */ outb(csr, 0xaa); ppc->ppc_type = PPC_TYPE_SMCLIKE; ppc_smclike_setmode(ppc, chipset_mode); return (chipset_mode); } /* * SMC FDC37C935 configuration * Found on many Alpha machines */ static int ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) { int s; int type = -1; s = splhigh(); outb(SMC935_CFG, 0x55); /* enter config mode */ outb(SMC935_CFG, 0x55); splx(s); outb(SMC935_IND, SMC935_ID); /* check device id */ if (inb(SMC935_DAT) == 0x2) type = SMC_37C935; if (type == -1) { outb(SMC935_CFG, 0xaa); /* exit config mode */ return (-1); } ppc->ppc_model = type; outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ outb(SMC935_DAT, 3); /* which is logical device 3 */ /* set io port base */ outb(SMC935_IND, SMC935_PORTHI); outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); outb(SMC935_IND, SMC935_PORTLO); outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); if (!chipset_mode) ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ else { ppc->ppc_avm = chipset_mode; outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ /* SPP + EPP or just plain SPP */ if (chipset_mode & (PPB_SPP)) { if (chipset_mode & PPB_EPP) { if (ppc->ppc_epp == EPP_1_9) { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_EPP19SPP); } if (ppc->ppc_epp == EPP_1_7) { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_EPP17SPP); } } else { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_SPP); } } /* ECP + EPP or just plain ECP */ if (chipset_mode & PPB_ECP) { if (chipset_mode & PPB_EPP) { if (ppc->ppc_epp == EPP_1_9) { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_ECPEPP19); } if (ppc->ppc_epp == EPP_1_7) { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_ECPEPP17); } } else { outb(SMC935_IND, SMC935_PPMODE); outb(SMC935_DAT, SMC935_ECP); } } } outb(SMC935_CFG, 0xaa); /* exit config mode */ ppc->ppc_type = PPC_TYPE_SMCLIKE; ppc_smclike_setmode(ppc, chipset_mode); return (chipset_mode); } /* * Winbond W83877F stuff * * EFER: extended function enable register * EFIR: extended function index register * EFDR: extended function data register */ #define efir ((efer == 0x250) ? 0x251 : 0x3f0) #define efdr ((efer == 0x250) ? 0x252 : 0x3f1) static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; static int w83877f_keyiter[] = { 1, 2, 2, 1 }; static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; static int ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) { int i, j, efer; unsigned char r, hefere, hefras; for (i = 0; i < 4; i ++) { /* first try to enable configuration registers */ efer = w83877f_efers[i]; /* write the key to the EFER */ for (j = 0; j < w83877f_keyiter[i]; j ++) outb (efer, w83877f_keys[i]); /* then check HEFERE and HEFRAS bits */ outb (efir, 0x0c); hefere = inb(efdr) & WINB_HEFERE; outb (efir, 0x16); hefras = inb(efdr) & WINB_HEFRAS; /* * HEFRAS HEFERE * 0 1 write 89h to 250h (power-on default) * 1 0 write 86h twice to 3f0h * 1 1 write 87h twice to 3f0h * 0 0 write 88h to 250h */ if ((hefere | hefras) == w83877f_hefs[i]) goto found; } return (-1); /* failed */ found: /* check base port address - read from CR23 */ outb(efir, 0x23); if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ return (-1); /* read CHIP ID from CR9/bits0-3 */ outb(efir, 0x9); switch (inb(efdr) & WINB_CHIPID) { case WINB_W83877F_ID: ppc->ppc_model = WINB_W83877F; break; case WINB_W83877AF_ID: ppc->ppc_model = WINB_W83877AF; break; default: ppc->ppc_model = WINB_UNKNOWN; } if (bootverbose) { /* dump of registers */ printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); for (i = 0; i <= 0xd; i ++) { outb(efir, i); printf("0x%x ", inb(efdr)); } for (i = 0x10; i <= 0x17; i ++) { outb(efir, i); printf("0x%x ", inb(efdr)); } outb(efir, 0x1e); printf("0x%x ", inb(efdr)); for (i = 0x20; i <= 0x29; i ++) { outb(efir, i); printf("0x%x ", inb(efdr)); } printf("\n"); printf("ppc%d:", ppc->ppc_unit); } ppc->ppc_type = PPC_TYPE_GENERIC; if (!chipset_mode) { /* autodetect mode */ /* select CR0 */ outb(efir, 0x0); r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); /* select CR9 */ outb(efir, 0x9); r |= (inb(efdr) & WINB_PRTMODS2); switch (r) { case WINB_W83757: if (bootverbose) printf("ppc%d: W83757 compatible mode\n", ppc->ppc_unit); return (-1); /* generic or SMC-like */ case WINB_EXTFDC: case WINB_EXTADP: case WINB_EXT2FDD: case WINB_JOYSTICK: if (bootverbose) printf(" not in parallel port mode\n"); return (-1); case (WINB_PARALLEL | WINB_EPP_SPP): ppc->ppc_avm |= PPB_EPP | PPB_SPP; if (bootverbose) printf(" EPP SPP"); break; case (WINB_PARALLEL | WINB_ECP): ppc->ppc_avm |= PPB_ECP | PPB_SPP; if (bootverbose) printf(" ECP SPP"); break; case (WINB_PARALLEL | WINB_ECP_EPP): ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; ppc->ppc_type = PPC_TYPE_SMCLIKE; if (bootverbose) printf(" ECP+EPP SPP"); break; default: printf("%s: unknown case (0x%x)!\n", __func__, r); } } else { /* mode forced */ /* select CR9 and set PRTMODS2 bit */ outb(efir, 0x9); outb(efdr, inb(efdr) & ~WINB_PRTMODS2); /* select CR0 and reset PRTMODSx bits */ outb(efir, 0x0); outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); if (chipset_mode & PPB_ECP) { if (chipset_mode & PPB_EPP) { outb(efdr, inb(efdr) | WINB_ECP_EPP); if (bootverbose) printf(" ECP+EPP"); ppc->ppc_type = PPC_TYPE_SMCLIKE; } else { outb(efdr, inb(efdr) | WINB_ECP); if (bootverbose) printf(" ECP"); } } else { /* select EPP_SPP otherwise */ outb(efdr, inb(efdr) | WINB_EPP_SPP); if (bootverbose) printf(" EPP SPP"); } ppc->ppc_avm = chipset_mode; } if (bootverbose) printf("\n"); /* exit configuration mode */ outb(efer, 0xaa); switch (ppc->ppc_type) { case PPC_TYPE_SMCLIKE: ppc_smclike_setmode(ppc, chipset_mode); break; default: ppc_generic_setmode(ppc, chipset_mode); break; } return (chipset_mode); } #endif /* * ppc_generic_detect */ static int ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) { /* default to generic */ ppc->ppc_type = PPC_TYPE_GENERIC; if (bootverbose) printf("ppc%d:", ppc->ppc_unit); /* first, check for ECP */ w_ecr(ppc, PPC_ECR_PS2); if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { ppc->ppc_dtm |= PPB_ECP | PPB_SPP; if (bootverbose) printf(" ECP SPP"); /* search for SMC style ECP+EPP mode */ w_ecr(ppc, PPC_ECR_EPP); } /* try to reset EPP timeout bit */ if (ppc_check_epp_timeout(ppc)) { ppc->ppc_dtm |= PPB_EPP; if (ppc->ppc_dtm & PPB_ECP) { /* SMC like chipset found */ ppc->ppc_model = SMC_LIKE; ppc->ppc_type = PPC_TYPE_SMCLIKE; if (bootverbose) printf(" ECP+EPP"); } else { if (bootverbose) printf(" EPP"); } } else { /* restore to standard mode */ w_ecr(ppc, PPC_ECR_STD); } /* XXX try to detect NIBBLE and PS2 modes */ ppc->ppc_dtm |= PPB_NIBBLE; if (bootverbose) printf(" SPP"); if (chipset_mode) ppc->ppc_avm = chipset_mode; else ppc->ppc_avm = ppc->ppc_dtm; if (bootverbose) printf("\n"); switch (ppc->ppc_type) { case PPC_TYPE_SMCLIKE: ppc_smclike_setmode(ppc, chipset_mode); break; default: ppc_generic_setmode(ppc, chipset_mode); break; } return (chipset_mode); } /* * ppc_detect() * * mode is the mode suggested at boot */ static int ppc_detect(struct ppc_data *ppc, int chipset_mode) { #ifdef PPC_PROBE_CHIPSET int i, mode; /* list of supported chipsets */ int (*chipset_detect[])(struct ppc_data *, int) = { ppc_pc873xx_detect, ppc_smc37c66xgt_detect, ppc_w83877f_detect, ppc_smc37c935_detect, ppc_generic_detect, NULL }; #endif /* if can't find the port and mode not forced return error */ if (!ppc_detect_port(ppc) && chipset_mode == 0) return (EIO); /* failed, port not present */ /* assume centronics compatible mode is supported */ ppc->ppc_avm = PPB_COMPATIBLE; #ifdef PPC_PROBE_CHIPSET /* we have to differenciate available chipset modes, * chipset running modes and IEEE-1284 operating modes * * after detection, the port must support running in compatible mode */ if (ppc->ppc_flags & 0x40) { if (bootverbose) printf("ppc: chipset forced to generic\n"); #endif ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); #ifdef PPC_PROBE_CHIPSET } else { for (i=0; chipset_detect[i] != NULL; i++) { if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { ppc->ppc_mode = mode; break; } } } #endif /* configure/detect ECP FIFO */ if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) ppc_detect_fifo(ppc); return (0); } /* * ppc_exec_microseq() * * Execute a microsequence. * Microsequence mechanism is supposed to handle fast I/O operations. */ int ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) { struct ppc_data *ppc = DEVTOSOFTC(dev); struct ppb_microseq *mi; char cc, *p; int i, iter, len; int error; register int reg; register char mask; register int accum = 0; register char *ptr = 0; struct ppb_microseq *stack = 0; /* microsequence registers are equivalent to PC-like port registers */ #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register)) #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte)) #define INCR_PC (mi ++) /* increment program counter */ mi = *p_msq; for (;;) { switch (mi->opcode) { case MS_OP_RSET: cc = r_reg(mi->arg[0].i, ppc); cc &= (char)mi->arg[2].i; /* clear mask */ cc |= (char)mi->arg[1].i; /* assert mask */ w_reg(mi->arg[0].i, ppc, cc); INCR_PC; break; case MS_OP_RASSERT_P: reg = mi->arg[1].i; ptr = ppc->ppc_ptr; if ((len = mi->arg[0].i) == MS_ACCUM) { accum = ppc->ppc_accum; for (; accum; accum--) w_reg(reg, ppc, *ptr++); ppc->ppc_accum = accum; } else for (i=0; ippc_ptr = ptr; INCR_PC; break; case MS_OP_RFETCH_P: reg = mi->arg[1].i; mask = (char)mi->arg[2].i; ptr = ppc->ppc_ptr; if ((len = mi->arg[0].i) == MS_ACCUM) { accum = ppc->ppc_accum; for (; accum; accum--) *ptr++ = r_reg(reg, ppc) & mask; ppc->ppc_accum = accum; } else for (i=0; ippc_ptr = ptr; INCR_PC; break; case MS_OP_RFETCH: *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & (char)mi->arg[1].i; INCR_PC; break; case MS_OP_RASSERT: case MS_OP_DELAY: /* let's suppose the next instr. is the same */ prefetch: for (;mi->opcode == MS_OP_RASSERT; INCR_PC) w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); if (mi->opcode == MS_OP_DELAY) { DELAY(mi->arg[0].i); INCR_PC; goto prefetch; } break; case MS_OP_ADELAY: if (mi->arg[0].i) tsleep(NULL, PPBPRI, "ppbdelay", mi->arg[0].i * (hz/1000)); INCR_PC; break; case MS_OP_TRIG: reg = mi->arg[0].i; iter = mi->arg[1].i; p = (char *)mi->arg[2].p; /* XXX delay limited to 255 us */ for (i=0; ippc_accum = mi->arg[0].i; INCR_PC; break; case MS_OP_DBRA: if (--ppc->ppc_accum > 0) mi += mi->arg[0].i; INCR_PC; break; case MS_OP_BRSET: cc = r_str(ppc); if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) mi += mi->arg[1].i; INCR_PC; break; case MS_OP_BRCLEAR: cc = r_str(ppc); if ((cc & (char)mi->arg[0].i) == 0) mi += mi->arg[1].i; INCR_PC; break; case MS_OP_BRSTAT: cc = r_str(ppc); if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == (char)mi->arg[0].i) mi += mi->arg[2].i; INCR_PC; break; case MS_OP_C_CALL: /* * If the C call returns !0 then end the microseq. * The current state of ptr is passed to the C function */ if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) return (error); INCR_PC; break; case MS_OP_PTR: ppc->ppc_ptr = (char *)mi->arg[0].p; INCR_PC; break; case MS_OP_CALL: if (stack) panic("%s: too much calls", __func__); if (mi->arg[0].p) { /* store the state of the actual * microsequence */ stack = mi; /* jump to the new microsequence */ mi = (struct ppb_microseq *)mi->arg[0].p; } else INCR_PC; break; case MS_OP_SUBRET: /* retrieve microseq and pc state before the call */ mi = stack; /* reset the stack */ stack = 0; /* XXX return code */ INCR_PC; break; case MS_OP_PUT: case MS_OP_GET: case MS_OP_RET: /* can't return to ppb level during the execution * of a submicrosequence */ if (stack) panic("%s: can't return to ppb level", __func__); /* update pc for ppb level of execution */ *p_msq = mi; /* return to ppb level of execution */ return (0); default: panic("%s: unknown microsequence opcode 0x%x", __func__, mi->opcode); } } /* unreached */ } static void ppcintr(void *arg) { device_t dev = (device_t)arg; struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); u_char ctr, ecr, str; str = r_str(ppc); ctr = r_ctr(ppc); ecr = r_ecr(ppc); #if PPC_DEBUG > 1 printf("![%x/%x/%x]", ctr, ecr, str); #endif /* don't use ecp mode with IRQENABLE set */ if (ctr & IRQENABLE) { return; } /* interrupts are generated by nFault signal * only in ECP mode */ if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { /* check if ppc driver has programmed the * nFault interrupt */ if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { w_ecr(ppc, ecr | PPC_nFAULT_INTR); ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; } else { /* shall be handled by underlying layers XXX */ return; } } if (ppc->ppc_irqstat & PPC_IRQ_DMA) { /* disable interrupts (should be done by hardware though) */ w_ecr(ppc, ecr | PPC_SERVICE_INTR); ppc->ppc_irqstat &= ~PPC_IRQ_DMA; ecr = r_ecr(ppc); /* check if DMA completed */ if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { #ifdef PPC_DEBUG printf("a"); #endif /* stop DMA */ w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); ecr = r_ecr(ppc); if (ppc->ppc_dmastat == PPC_DMA_STARTED) { #ifdef PPC_DEBUG printf("d"); #endif isa_dmadone( ppc->ppc_dmaflags, ppc->ppc_dmaddr, ppc->ppc_dmacnt, ppc->ppc_dmachan); ppc->ppc_dmastat = PPC_DMA_COMPLETE; /* wakeup the waiting process */ wakeup(ppc); } } } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { /* classic interrupt I/O */ ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; } return; } int ppc_read(device_t dev, char *buf, int len, int mode) { return (EINVAL); } /* * Call this function if you want to send data in any advanced mode * of your parallel port: FIFO, DMA * * If what you want is not possible (no ECP, no DMA...), * EINVAL is returned */ int ppc_write(device_t dev, char *buf, int len, int how) { struct ppc_data *ppc = DEVTOSOFTC(dev); char ecr, ecr_sav, ctr, ctr_sav; int s, error = 0; int spin; #ifdef PPC_DEBUG printf("w"); #endif ecr_sav = r_ecr(ppc); ctr_sav = r_ctr(ppc); /* * Send buffer with DMA, FIFO and interrupts */ if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { if (ppc->ppc_dmachan > 0) { /* byte mode, no intr, no DMA, dir=0, flush fifo */ ecr = PPC_ECR_STD | PPC_DISABLE_INTR; w_ecr(ppc, ecr); /* disable nAck interrupts */ ctr = r_ctr(ppc); ctr &= ~IRQENABLE; w_ctr(ppc, ctr); ppc->ppc_dmaflags = 0; ppc->ppc_dmaddr = (caddr_t)buf; ppc->ppc_dmacnt = (u_int)len; switch (ppc->ppc_mode) { case PPB_COMPATIBLE: /* compatible mode with FIFO, no intr, DMA, dir=0 */ ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; break; case PPB_ECP: ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; break; default: error = EINVAL; goto error; } w_ecr(ppc, ecr); ecr = r_ecr(ppc); /* enter splhigh() not to be preempted * by the dma interrupt, we may miss * the wakeup otherwise */ s = splhigh(); ppc->ppc_dmastat = PPC_DMA_INIT; /* enable interrupts */ ecr &= ~PPC_SERVICE_INTR; ppc->ppc_irqstat = PPC_IRQ_DMA; w_ecr(ppc, ecr); isa_dmastart( ppc->ppc_dmaflags, ppc->ppc_dmaddr, ppc->ppc_dmacnt, ppc->ppc_dmachan); #ifdef PPC_DEBUG printf("s%d", ppc->ppc_dmacnt); #endif ppc->ppc_dmastat = PPC_DMA_STARTED; /* Wait for the DMA completed interrupt. We hope we won't * miss it, otherwise a signal will be necessary to unlock the * process. */ do { /* release CPU */ error = tsleep(ppc, PPBPRI | PCATCH, "ppcdma", 0); } while (error == EWOULDBLOCK); splx(s); if (error) { #ifdef PPC_DEBUG printf("i"); #endif /* stop DMA */ isa_dmadone( ppc->ppc_dmaflags, ppc->ppc_dmaddr, ppc->ppc_dmacnt, ppc->ppc_dmachan); /* no dma, no interrupt, flush the fifo */ w_ecr(ppc, PPC_ECR_RESET); ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; goto error; } /* wait for an empty fifo */ while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { for (spin=100; spin; spin--) if (r_ecr(ppc) & PPC_FIFO_EMPTY) goto fifo_empty; #ifdef PPC_DEBUG printf("Z"); #endif error = tsleep(ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); if (error != EWOULDBLOCK) { #ifdef PPC_DEBUG printf("I"); #endif /* no dma, no interrupt, flush the fifo */ w_ecr(ppc, PPC_ECR_RESET); ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; error = EINTR; goto error; } } fifo_empty: /* no dma, no interrupt, flush the fifo */ w_ecr(ppc, PPC_ECR_RESET); } else error = EINVAL; /* XXX we should FIFO and * interrupts */ } else error = EINVAL; error: /* PDRQ must be kept unasserted until nPDACK is * deasserted for a minimum of 350ns (SMC datasheet) * * Consequence may be a FIFO that never empty */ DELAY(1); w_ecr(ppc, ecr_sav); w_ctr(ppc, ctr_sav); return (error); } void ppc_reset_epp(device_t dev) { struct ppc_data *ppc = DEVTOSOFTC(dev); ppc_reset_epp_timeout(ppc); return; } int ppc_setmode(device_t dev, int mode) { struct ppc_data *ppc = DEVTOSOFTC(dev); switch (ppc->ppc_type) { case PPC_TYPE_SMCLIKE: return (ppc_smclike_setmode(ppc, mode)); break; case PPC_TYPE_GENERIC: default: return (ppc_generic_setmode(ppc, mode)); break; } /* not reached */ return (ENXIO); } static struct isa_pnp_id lpc_ids[] = { { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */ { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */ { 0 } }; static int ppc_cbus_probe(device_t dev) { device_t parent; int error; parent = device_get_parent(dev); error = ISA_PNP_PROBE(parent, dev, lpc_ids); if (error == ENXIO) return (ENXIO); else if (error != 0) /* XXX shall be set after detection */ device_set_desc(dev, "Parallel port"); return(ppc_probe(dev)); } int ppc_probe(device_t dev) { #ifdef __i386__ static short next_bios_ppc = 0; #endif struct ppc_data *ppc; int error; u_long port; #ifdef PC98 #define PC98_IEEE_1284_DISABLE 0x100 #define PC98_IEEE_1284_PORT 0x140 unsigned int pc98_ieee_mode = 0x00; unsigned int tmp; #endif /* * Allocate the ppc_data structure. */ ppc = DEVTOSOFTC(dev); bzero(ppc, sizeof(struct ppc_data)); ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; /* retrieve ISA parameters */ error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL); #ifdef __i386__ /* * If port not specified, use bios list. */ if (error) { #ifndef PC98 if((next_bios_ppc < BIOS_MAX_PPC) && (*(BIOS_PORTS+next_bios_ppc) != 0) ) { port = *(BIOS_PORTS+next_bios_ppc++); if (bootverbose) device_printf(dev, "parallel port found at 0x%x\n", (int) port); } else { device_printf(dev, "parallel port not found.\n"); return ENXIO; } #else if (next_bios_ppc == 0) { /* Use default IEEE-1284 port of NEC PC-98x1 */ port = PC98_IEEE_1284_PORT; next_bios_ppc += 1; if (bootverbose) device_printf(dev, "parallel port found at 0x%x\n", (int) port); } #endif bus_set_resource(dev, SYS_RES_IOPORT, 0, port, IO_LPTSIZE_EXTENDED); } #endif #ifdef __alpha__ /* * There isn't a bios list on alpha. Put it in the usual place. */ if (error) { bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc, IO_LPTSIZE_NORMAL); } #endif /* IO port is mandatory */ /* Try "extended" IO port range...*/ ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, &ppc->rid_ioport, 0, ~0, IO_LPTSIZE_EXTENDED, RF_ACTIVE); if (ppc->res_ioport != 0) { if (bootverbose) device_printf(dev, "using extended I/O port range\n"); } else { /* Failed? If so, then try the "normal" IO port range... */ ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, &ppc->rid_ioport, 0, ~0, IO_LPTSIZE_NORMAL, RF_ACTIVE); if (ppc->res_ioport != 0) { if (bootverbose) device_printf(dev, "using normal I/O port range\n"); } else { device_printf(dev, "cannot reserve I/O port range\n"); goto error; } } ppc->ppc_base = rman_get_start(ppc->res_ioport); ppc->bsh = rman_get_bushandle(ppc->res_ioport); ppc->bst = rman_get_bustag(ppc->res_ioport); ppc->ppc_flags = device_get_flags(dev); if (!(ppc->ppc_flags & 0x20)) { ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &ppc->rid_irq, RF_SHAREABLE); ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, &ppc->rid_drq, RF_ACTIVE); } if (ppc->res_irq) ppc->ppc_irq = rman_get_start(ppc->res_irq); if (ppc->res_drq) ppc->ppc_dmachan = rman_get_start(ppc->res_drq); ppc->ppc_unit = device_get_unit(dev); ppc->ppc_model = GENERIC; ppc->ppc_mode = PPB_COMPATIBLE; ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; ppc->ppc_type = PPC_TYPE_GENERIC; #ifdef PC98 /* * IEEE STD 1284 Function Check and Enable * for default IEEE-1284 port of NEC PC-98x1 */ if ((ppc->ppc_base == PC98_IEEE_1284_PORT) && !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); pc98_ieee_mode = tmp; if ((tmp & 0x10) == 0x10) { outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10); tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); if ((tmp & 0x10) == 0x10) goto error; } else { outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10); tmp = inb(ppc->ppc_base + PPC_1284_ENABLE); if ((tmp & 0x10) != 0x10) goto error; } outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10); } #endif /* * Try to detect the chipset and its mode. */ if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) goto error; return (0); error: #ifdef PC98 if ((ppc->ppc_base == PC98_IEEE_1284_PORT) && !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) { outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode); } #endif if (ppc->res_irq != 0) { bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, ppc->res_irq); } if (ppc->res_ioport != 0) { bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, ppc->res_ioport); bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, ppc->res_ioport); } if (ppc->res_drq != 0) { bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, ppc->res_drq); bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, ppc->res_drq); } return (ENXIO); } int ppc_attach(device_t dev) { struct ppc_data *ppc = DEVTOSOFTC(dev); device_t ppbus; device_t parent = device_get_parent(dev); device_printf(dev, "%s chipset (%s) in %s mode%s\n", ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? ppc_epp_protocol[ppc->ppc_epp] : ""); if (ppc->ppc_fifo) device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { /* acquire the DMA channel forever */ /* XXX */ isa_dma_acquire(ppc->ppc_dmachan); isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ } /* add ppbus as a child of this isa to parallel bridge */ ppbus = device_add_child(dev, "ppbus", -1); /* * Probe the ppbus and attach devices found. */ device_probe_and_attach(ppbus); /* register the ppc interrupt handler as default */ if (ppc->res_irq) { /* default to the tty mask for registration */ /* XXX */ if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, ppcintr, dev, &ppc->intr_cookie) == 0) { /* remember the ppcintr is registered */ ppc->ppc_registered = 1; } } return (0); } u_char ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) { struct ppc_data *ppc = DEVTOSOFTC(ppcdev); switch (iop) { case PPB_OUTSB_EPP: bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); break; case PPB_OUTSW_EPP: bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); break; case PPB_OUTSL_EPP: bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); break; case PPB_INSB_EPP: bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); break; case PPB_INSW_EPP: bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); break; case PPB_INSL_EPP: bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); break; case PPB_RDTR: return (r_dtr(ppc)); case PPB_RSTR: return (r_str(ppc)); case PPB_RCTR: return (r_ctr(ppc)); case PPB_REPP_A: return (r_epp_A(ppc)); case PPB_REPP_D: return (r_epp_D(ppc)); case PPB_RECR: return (r_ecr(ppc)); case PPB_RFIFO: return (r_fifo(ppc)); case PPB_WDTR: w_dtr(ppc, byte); break; case PPB_WSTR: w_str(ppc, byte); break; case PPB_WCTR: w_ctr(ppc, byte); break; case PPB_WEPP_A: w_epp_A(ppc, byte); break; case PPB_WEPP_D: w_epp_D(ppc, byte); break; case PPB_WECR: w_ecr(ppc, byte); break; case PPB_WFIFO: w_fifo(ppc, byte); break; default: panic("%s: unknown I/O operation", __func__); break; } return (0); /* not significative */ } int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) { struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); switch (index) { case PPC_IVAR_EPP_PROTO: *val = (u_long)ppc->ppc_epp; break; case PPC_IVAR_IRQ: *val = (u_long)ppc->ppc_irq; break; default: return (ENOENT); } return (0); } /* * Resource is useless here since ppbus devices' interrupt handlers are * multiplexed to the same resource initially allocated by ppc */ int ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, void (*ihand)(void *), void *arg, void **cookiep) { int error; struct ppc_data *ppc = DEVTOSOFTC(bus); if (ppc->ppc_registered) { /* XXX refuse registration if DMA is in progress */ /* first, unregister the default interrupt handler */ if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), bus, ppc->res_irq, ppc->intr_cookie))) return (error); /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ /* ppc->res_irq); */ /* DMA/FIFO operation won't be possible anymore */ ppc->ppc_registered = 0; } /* pass registration to the upper layer, ignore the incoming resource */ return (BUS_SETUP_INTR(device_get_parent(bus), child, r, flags, ihand, arg, cookiep)); } /* * When no underlying device has a registered interrupt, register the ppc * layer one */ int ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) { int error; struct ppc_data *ppc = DEVTOSOFTC(bus); device_t parent = device_get_parent(bus); /* pass unregistration to the upper layer */ if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) return (error); /* default to the tty mask for registration */ /* XXX */ if (ppc->ppc_irq && !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) { /* remember the ppcintr is registered */ ppc->ppc_registered = 1; } return (error); } DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); #ifndef PC98 DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, 0, 0); #endif