Index: head/sys/dev/firewire/firewire.c =================================================================== --- head/sys/dev/firewire/firewire.c (revision 129540) +++ head/sys/dev/firewire/firewire.c (revision 129541) @@ -1,2283 +1,2283 @@ /* * Copyright (c) 2003 Hidetoshi Shimokawa * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the acknowledgement as bellow: * * This product includes software developed by K. Kobayashi and H. Shimokawa * * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #include #include #include #include #include #include #include #if defined(__DragonFly__) || __FreeBSD_version < 500000 #include /* for DELAY() */ #endif #include /* used by smbus and newbus */ #include #ifdef __DragonFly__ #include "firewire.h" #include "firewirereg.h" #include "fwmem.h" #include "iec13213.h" #include "iec68113.h" #else #include #include #include #include #include #endif struct crom_src_buf { struct crom_src src; struct crom_chunk root; struct crom_chunk vendor; struct crom_chunk hw; }; int firewire_debug=0, try_bmr=1, hold_count=3; SYSCTL_INT(_debug, OID_AUTO, firewire_debug, CTLFLAG_RW, &firewire_debug, 0, "FireWire driver debug flag"); SYSCTL_NODE(_hw, OID_AUTO, firewire, CTLFLAG_RD, 0, "FireWire Subsystem"); SYSCTL_INT(_hw_firewire, OID_AUTO, try_bmr, CTLFLAG_RW, &try_bmr, 0, "Try to be a bus manager"); SYSCTL_INT(_hw_firewire, OID_AUTO, hold_count, CTLFLAG_RW, &hold_count, 0, "Number of count of bus resets for removing lost device information"); MALLOC_DEFINE(M_FW, "firewire", "FireWire"); MALLOC_DEFINE(M_FWXFER, "fw_xfer", "XFER/FireWire"); #define FW_MAXASYRTY 4 devclass_t firewire_devclass; static void firewire_identify (driver_t *, device_t); static int firewire_probe (device_t); static int firewire_attach (device_t); static int firewire_detach (device_t); static int firewire_resume (device_t); #if 0 static int firewire_shutdown (device_t); #endif static device_t firewire_add_child (device_t, int, const char *, int); static void fw_try_bmr (void *); static void fw_try_bmr_callback (struct fw_xfer *); static void fw_asystart (struct fw_xfer *); static int fw_get_tlabel (struct firewire_comm *, struct fw_xfer *); static void fw_bus_probe (struct firewire_comm *); static void fw_bus_explore (struct firewire_comm *); static void fw_bus_explore_callback (struct fw_xfer *); static void fw_attach_dev (struct firewire_comm *); #ifdef FW_VMACCESS static void fw_vmaccess (struct fw_xfer *); #endif struct fw_xfer *asyreqq (struct firewire_comm *, u_int8_t, u_int8_t, u_int8_t, u_int32_t, u_int32_t, void (*)(struct fw_xfer *)); static int fw_bmr (struct firewire_comm *); static device_method_t firewire_methods[] = { /* Device interface */ DEVMETHOD(device_identify, firewire_identify), DEVMETHOD(device_probe, firewire_probe), DEVMETHOD(device_attach, firewire_attach), DEVMETHOD(device_detach, firewire_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, firewire_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), /* Bus interface */ DEVMETHOD(bus_add_child, firewire_add_child), DEVMETHOD(bus_print_child, bus_generic_print_child), { 0, 0 } }; char *linkspeed[] = { "S100", "S200", "S400", "S800", "S1600", "S3200", "undef", "undef" }; static char *tcode_str[] = { "WREQQ", "WREQB", "WRES", "undef", "RREQQ", "RREQB", "RRESQ", "RRESB", "CYCS", "LREQ", "STREAM", "LRES", "undef", "undef", "PHY", "undef" }; /* IEEE-1394a Table C-2 Gap count as a function of hops*/ #define MAX_GAPHOP 15 u_int gap_cnt[] = { 5, 5, 7, 8, 10, 13, 16, 18, 21, 24, 26, 29, 32, 35, 37, 40}; static driver_t firewire_driver = { "firewire", firewire_methods, sizeof(struct firewire_softc), }; /* * Lookup fwdev by node id. */ struct fw_device * fw_noderesolve_nodeid(struct firewire_comm *fc, int dst) { struct fw_device *fwdev; int s; s = splfw(); STAILQ_FOREACH(fwdev, &fc->devices, link) if (fwdev->dst == dst && fwdev->status != FWDEVINVAL) break; splx(s); return fwdev; } /* * Lookup fwdev by EUI64. */ struct fw_device * fw_noderesolve_eui64(struct firewire_comm *fc, struct fw_eui64 *eui) { struct fw_device *fwdev; int s; s = splfw(); STAILQ_FOREACH(fwdev, &fc->devices, link) if (FW_EUI64_EQUAL(fwdev->eui, *eui)) break; splx(s); if(fwdev == NULL) return NULL; if(fwdev->status == FWDEVINVAL) return NULL; return fwdev; } /* * Async. request procedure for userland application. */ int fw_asyreq(struct firewire_comm *fc, int sub, struct fw_xfer *xfer) { int err = 0; struct fw_xferq *xferq; int tl = 0, len; struct fw_pkt *fp; int tcode; struct tcode_info *info; if(xfer == NULL) return EINVAL; if(xfer->act.hand == NULL){ printf("act.hand == NULL\n"); return EINVAL; } fp = &xfer->send.hdr; tcode = fp->mode.common.tcode & 0xf; info = &fc->tcode[tcode]; if (info->flag == 0) { printf("invalid tcode=%x\n", tcode); return EINVAL; } if (info->flag & FWTI_REQ) xferq = fc->atq; else xferq = fc->ats; len = info->hdr_len; if (xfer->send.pay_len > MAXREC(fc->maxrec)) { printf("send.pay_len > maxrec\n"); return EINVAL; } if (info->flag & FWTI_BLOCK_STR) len = fp->mode.stream.len; else if (info->flag & FWTI_BLOCK_ASY) len = fp->mode.rresb.len; else len = 0; if (len != xfer->send.pay_len){ printf("len(%d) != send.pay_len(%d) %s(%x)\n", len, xfer->send.pay_len, tcode_str[tcode], tcode); return EINVAL; } if(xferq->start == NULL){ printf("xferq->start == NULL\n"); return EINVAL; } if(!(xferq->queued < xferq->maxq)){ device_printf(fc->bdev, "Discard a packet (queued=%d)\n", xferq->queued); return EINVAL; } if (info->flag & FWTI_TLABEL) { if((tl = fw_get_tlabel(fc, xfer)) == -1 ) return EIO; fp->mode.hdr.tlrt = tl << 2; } xfer->tl = tl; xfer->resp = 0; xfer->fc = fc; xfer->q = xferq; xfer->retry_req = fw_asybusy; fw_asystart(xfer); return err; } /* * Wakeup blocked process. */ void fw_asy_callback(struct fw_xfer *xfer){ wakeup(xfer); return; } /* * Postpone to later retry. */ void fw_asybusy(struct fw_xfer *xfer){ printf("fw_asybusy\n"); /* xfer->ch = timeout((timeout_t *)fw_asystart, (void *)xfer, 20000); */ #if 0 DELAY(20000); #endif fw_asystart(xfer); return; } /* * Async. request with given xfer structure. */ static void fw_asystart(struct fw_xfer *xfer) { struct firewire_comm *fc = xfer->fc; int s; if(xfer->retry++ >= fc->max_asyretry){ device_printf(fc->bdev, "max_asyretry exceeded\n"); xfer->resp = EBUSY; xfer->state = FWXF_BUSY; xfer->act.hand(xfer); return; } #if 0 /* XXX allow bus explore packets only after bus rest */ if (fc->status < FWBUSEXPLORE) { xfer->resp = EAGAIN; xfer->state = FWXF_BUSY; if (xfer->act.hand != NULL) xfer->act.hand(xfer); return; } #endif microtime(&xfer->tv); s = splfw(); xfer->state = FWXF_INQ; STAILQ_INSERT_TAIL(&xfer->q->q, xfer, link); xfer->q->queued ++; splx(s); /* XXX just queue for mbuf */ if (xfer->mbuf == NULL) xfer->q->start(fc); return; } static void firewire_identify(driver_t *driver, device_t parent) { BUS_ADD_CHILD(parent, 0, "firewire", -1); } static int firewire_probe(device_t dev) { device_set_desc(dev, "IEEE1394(FireWire) bus"); return (0); } static void firewire_xfer_timeout(struct firewire_comm *fc) { struct fw_xfer *xfer; struct tlabel *tl; struct timeval tv; struct timeval split_timeout; int i, s; split_timeout.tv_sec = 0; split_timeout.tv_usec = 200 * 1000; /* 200 msec */ microtime(&tv); timevalsub(&tv, &split_timeout); s = splfw(); for (i = 0; i < 0x40; i ++) { while ((tl = STAILQ_FIRST(&fc->tlabels[i])) != NULL) { xfer = tl->xfer; if (timevalcmp(&xfer->tv, &tv, >)) /* the rests are newer than this */ break; if (xfer->state == FWXF_START) /* not sent yet */ break; device_printf(fc->bdev, "split transaction timeout dst=0x%x tl=0x%x state=%d\n", xfer->send.hdr.mode.hdr.dst, i, xfer->state); xfer->resp = ETIMEDOUT; STAILQ_REMOVE_HEAD(&fc->tlabels[i], link); fw_xfer_done(xfer); } } splx(s); } #define WATCHDOC_HZ 10 static void firewire_watchdog(void *arg) { struct firewire_comm *fc; static int watchdoc_clock = 0; fc = (struct firewire_comm *)arg; /* * At boot stage, the device interrupt is disabled and * We encounter a timeout easily. To avoid this, * ignore clock interrupt for a while. */ if (watchdoc_clock > WATCHDOC_HZ * 15) { firewire_xfer_timeout(fc); fc->timeout(fc); } else watchdoc_clock ++; callout_reset(&fc->timeout_callout, hz / WATCHDOC_HZ, (void *)firewire_watchdog, (void *)fc); } /* * The attach routine. */ static int firewire_attach(device_t dev) { int unit; struct firewire_softc *sc = device_get_softc(dev); device_t pa = device_get_parent(dev); struct firewire_comm *fc; fc = (struct firewire_comm *)device_get_softc(pa); sc->fc = fc; fc->status = FWBUSNOTREADY; unit = device_get_unit(dev); if( fc->nisodma > FWMAXNDMA) fc->nisodma = FWMAXNDMA; fwdev_makedev(sc); CALLOUT_INIT(&sc->fc->timeout_callout); CALLOUT_INIT(&sc->fc->bmr_callout); CALLOUT_INIT(&sc->fc->retry_probe_callout); CALLOUT_INIT(&sc->fc->busprobe_callout); callout_reset(&sc->fc->timeout_callout, hz, (void *)firewire_watchdog, (void *)sc->fc); /* Locate our children */ bus_generic_probe(dev); /* launch attachement of the added children */ bus_generic_attach(dev); /* bus_reset */ fw_busreset(fc); fc->ibr(fc); return 0; } /* * Attach it as child. */ static device_t firewire_add_child(device_t dev, int order, const char *name, int unit) { device_t child; struct firewire_softc *sc; sc = (struct firewire_softc *)device_get_softc(dev); child = device_add_child(dev, name, unit); if (child) { device_set_ivars(child, sc->fc); device_probe_and_attach(child); } return child; } static int firewire_resume(device_t dev) { struct firewire_softc *sc; sc = (struct firewire_softc *)device_get_softc(dev); sc->fc->status = FWBUSNOTREADY; bus_generic_resume(dev); return(0); } /* * Dettach it. */ static int firewire_detach(device_t dev) { struct firewire_softc *sc; struct csrdir *csrd, *next; struct fw_device *fwdev, *fwdev_next; int err; sc = (struct firewire_softc *)device_get_softc(dev); if ((err = fwdev_destroydev(sc)) != 0) return err; if ((err = bus_generic_detach(dev)) != 0) return err; callout_stop(&sc->fc->timeout_callout); callout_stop(&sc->fc->bmr_callout); callout_stop(&sc->fc->retry_probe_callout); callout_stop(&sc->fc->busprobe_callout); /* XXX xfree_free and untimeout on all xfers */ for (fwdev = STAILQ_FIRST(&sc->fc->devices); fwdev != NULL; fwdev = fwdev_next) { fwdev_next = STAILQ_NEXT(fwdev, link); free(fwdev, M_FW); } for (csrd = SLIST_FIRST(&sc->fc->csrfree); csrd != NULL; csrd = next) { next = SLIST_NEXT(csrd, link); free(csrd, M_FW); } free(sc->fc->topology_map, M_FW); free(sc->fc->speed_map, M_FW); free(sc->fc->crom_src_buf, M_FW); return(0); } #if 0 static int firewire_shutdown( device_t dev ) { return 0; } #endif static void fw_xferq_drain(struct fw_xferq *xferq) { struct fw_xfer *xfer; while ((xfer = STAILQ_FIRST(&xferq->q)) != NULL) { STAILQ_REMOVE_HEAD(&xferq->q, link); xferq->queued --; xfer->resp = EAGAIN; fw_xfer_done(xfer); } } void fw_drain_txq(struct firewire_comm *fc) { int i; fw_xferq_drain(fc->atq); fw_xferq_drain(fc->ats); for(i = 0; i < fc->nisodma; i++) fw_xferq_drain(fc->it[i]); } static void fw_reset_csr(struct firewire_comm *fc) { int i; CSRARC(fc, STATE_CLEAR) = 1 << 23 | 0 << 17 | 1 << 16 | 1 << 15 | 1 << 14 ; CSRARC(fc, STATE_SET) = CSRARC(fc, STATE_CLEAR); CSRARC(fc, NODE_IDS) = 0x3f; CSRARC(fc, TOPO_MAP + 8) = 0; fc->irm = -1; fc->max_node = -1; for(i = 2; i < 0x100/4 - 2 ; i++){ CSRARC(fc, SPED_MAP + i * 4) = 0; } CSRARC(fc, STATE_CLEAR) = 1 << 23 | 0 << 17 | 1 << 16 | 1 << 15 | 1 << 14 ; CSRARC(fc, STATE_SET) = CSRARC(fc, STATE_CLEAR); CSRARC(fc, RESET_START) = 0; CSRARC(fc, SPLIT_TIMEOUT_HI) = 0; CSRARC(fc, SPLIT_TIMEOUT_LO) = 800 << 19; CSRARC(fc, CYCLE_TIME) = 0x0; CSRARC(fc, BUS_TIME) = 0x0; CSRARC(fc, BUS_MGR_ID) = 0x3f; CSRARC(fc, BANDWIDTH_AV) = 4915; CSRARC(fc, CHANNELS_AV_HI) = 0xffffffff; CSRARC(fc, CHANNELS_AV_LO) = 0xffffffff; CSRARC(fc, IP_CHANNELS) = (1 << 31); CSRARC(fc, CONF_ROM) = 0x04 << 24; CSRARC(fc, CONF_ROM + 4) = 0x31333934; /* means strings 1394 */ CSRARC(fc, CONF_ROM + 8) = 1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 | 0xff << 16 | 0x09 << 8; CSRARC(fc, CONF_ROM + 0xc) = 0; /* DV depend CSRs see blue book */ CSRARC(fc, oPCR) &= ~DV_BROADCAST_ON; CSRARC(fc, iPCR) &= ~DV_BROADCAST_ON; CSRARC(fc, STATE_CLEAR) &= ~(1 << 23 | 1 << 15 | 1 << 14 ); CSRARC(fc, STATE_SET) = CSRARC(fc, STATE_CLEAR); } static void fw_init_crom(struct firewire_comm *fc) { struct crom_src *src; fc->crom_src_buf = (struct crom_src_buf *) malloc(sizeof(struct crom_src_buf), M_FW, M_WAITOK | M_ZERO); if (fc->crom_src_buf == NULL) return; src = &fc->crom_src_buf->src; bzero(src, sizeof(struct crom_src)); /* BUS info sample */ src->hdr.info_len = 4; src->businfo.bus_name = CSR_BUS_NAME_IEEE1394; src->businfo.irmc = 1; src->businfo.cmc = 1; src->businfo.isc = 1; src->businfo.bmc = 1; src->businfo.pmc = 0; src->businfo.cyc_clk_acc = 100; src->businfo.max_rec = fc->maxrec; src->businfo.max_rom = MAXROM_4; src->businfo.generation = 1; src->businfo.link_spd = fc->speed; src->businfo.eui64.hi = fc->eui.hi; src->businfo.eui64.lo = fc->eui.lo; STAILQ_INIT(&src->chunk_list); fc->crom_src = src; fc->crom_root = &fc->crom_src_buf->root; } static void fw_reset_crom(struct firewire_comm *fc) { struct crom_src_buf *buf; struct crom_src *src; struct crom_chunk *root; if (fc->crom_src_buf == NULL) fw_init_crom(fc); buf = fc->crom_src_buf; src = fc->crom_src; root = fc->crom_root; STAILQ_INIT(&src->chunk_list); bzero(root, sizeof(struct crom_chunk)); crom_add_chunk(src, NULL, root, 0); crom_add_entry(root, CSRKEY_NCAP, 0x0083c0); /* XXX */ /* private company_id */ crom_add_entry(root, CSRKEY_VENDOR, CSRVAL_VENDOR_PRIVATE); #ifdef __DragonFly__ crom_add_simple_text(src, root, &buf->vendor, "DragonFly Project"); crom_add_entry(root, CSRKEY_HW, __DragonFly_cc_version); #else crom_add_simple_text(src, root, &buf->vendor, "FreeBSD Project"); crom_add_entry(root, CSRKEY_HW, __FreeBSD_version); #endif crom_add_simple_text(src, root, &buf->hw, hostname); } /* * Called after bus reset. */ void fw_busreset(struct firewire_comm *fc) { struct firewire_dev_comm *fdc; struct crom_src *src; device_t *devlistp; void *newrom; int i, devcnt; switch(fc->status){ case FWBUSMGRELECT: callout_stop(&fc->bmr_callout); break; default: break; } fc->status = FWBUSRESET; fw_reset_csr(fc); fw_reset_crom(fc); if (device_get_children(fc->bdev, &devlistp, &devcnt) == 0) { for( i = 0 ; i < devcnt ; i++) if (device_get_state(devlistp[i]) >= DS_ATTACHED) { fdc = device_get_softc(devlistp[i]); if (fdc->post_busreset != NULL) fdc->post_busreset(fdc); } free(devlistp, M_TEMP); } newrom = malloc(CROMSIZE, M_FW, M_NOWAIT | M_ZERO); src = &fc->crom_src_buf->src; crom_load(src, (u_int32_t *)newrom, CROMSIZE); if (bcmp(newrom, fc->config_rom, CROMSIZE) != 0) { /* bump generation and reload */ src->businfo.generation ++; /* generation must be between 0x2 and 0xF */ if (src->businfo.generation < 2) src->businfo.generation ++; crom_load(src, (u_int32_t *)newrom, CROMSIZE); bcopy(newrom, (void *)fc->config_rom, CROMSIZE); } free(newrom, M_FW); } /* Call once after reboot */ void fw_init(struct firewire_comm *fc) { int i; struct csrdir *csrd; #ifdef FW_VMACCESS struct fw_xfer *xfer; struct fw_bind *fwb; #endif fc->max_asyretry = FW_MAXASYRTY; fc->arq->queued = 0; fc->ars->queued = 0; fc->atq->queued = 0; fc->ats->queued = 0; fc->arq->buf = NULL; fc->ars->buf = NULL; fc->atq->buf = NULL; fc->ats->buf = NULL; fc->arq->flag = 0; fc->ars->flag = 0; fc->atq->flag = 0; fc->ats->flag = 0; STAILQ_INIT(&fc->atq->q); STAILQ_INIT(&fc->ats->q); for( i = 0 ; i < fc->nisodma ; i ++ ){ fc->it[i]->queued = 0; fc->ir[i]->queued = 0; fc->it[i]->start = NULL; fc->ir[i]->start = NULL; fc->it[i]->buf = NULL; fc->ir[i]->buf = NULL; fc->it[i]->flag = FWXFERQ_STREAM; fc->ir[i]->flag = FWXFERQ_STREAM; STAILQ_INIT(&fc->it[i]->q); STAILQ_INIT(&fc->ir[i]->q); STAILQ_INIT(&fc->it[i]->binds); STAILQ_INIT(&fc->ir[i]->binds); } fc->arq->maxq = FWMAXQUEUE; fc->ars->maxq = FWMAXQUEUE; fc->atq->maxq = FWMAXQUEUE; fc->ats->maxq = FWMAXQUEUE; for( i = 0 ; i < fc->nisodma ; i++){ fc->ir[i]->maxq = FWMAXQUEUE; fc->it[i]->maxq = FWMAXQUEUE; } /* Initialize csr registers */ fc->topology_map = (struct fw_topology_map *)malloc( sizeof(struct fw_topology_map), M_FW, M_NOWAIT | M_ZERO); fc->speed_map = (struct fw_speed_map *)malloc( sizeof(struct fw_speed_map), M_FW, M_NOWAIT | M_ZERO); CSRARC(fc, TOPO_MAP) = 0x3f1 << 16; CSRARC(fc, TOPO_MAP + 4) = 1; CSRARC(fc, SPED_MAP) = 0x3f1 << 16; CSRARC(fc, SPED_MAP + 4) = 1; STAILQ_INIT(&fc->devices); /* Initialize csr ROM work space */ SLIST_INIT(&fc->ongocsr); SLIST_INIT(&fc->csrfree); for( i = 0 ; i < FWMAXCSRDIR ; i++){ csrd = (struct csrdir *) malloc(sizeof(struct csrdir), M_FW,M_NOWAIT); if(csrd == NULL) break; SLIST_INSERT_HEAD(&fc->csrfree, csrd, link); } /* Initialize Async handlers */ STAILQ_INIT(&fc->binds); for( i = 0 ; i < 0x40 ; i++){ STAILQ_INIT(&fc->tlabels[i]); } /* DV depend CSRs see blue book */ #if 0 CSRARC(fc, oMPR) = 0x3fff0001; /* # output channel = 1 */ CSRARC(fc, oPCR) = 0x8000007a; for(i = 4 ; i < 0x7c/4 ; i+=4){ CSRARC(fc, i + oPCR) = 0x8000007a; } CSRARC(fc, iMPR) = 0x00ff0001; /* # input channel = 1 */ CSRARC(fc, iPCR) = 0x803f0000; for(i = 4 ; i < 0x7c/4 ; i+=4){ CSRARC(fc, i + iPCR) = 0x0; } #endif fc->crom_src_buf = NULL; #ifdef FW_VMACCESS xfer = fw_xfer_alloc(); if(xfer == NULL) return; fwb = (struct fw_bind *)malloc(sizeof (struct fw_bind), M_FW, M_NOWAIT); if(fwb == NULL){ fw_xfer_free(xfer); } xfer->act.hand = fw_vmaccess; xfer->fc = fc; xfer->sc = NULL; fwb->start_hi = 0x2; fwb->start_lo = 0; fwb->addrlen = 0xffffffff; fwb->xfer = xfer; fw_bindadd(fc, fwb); #endif } #define BIND_CMP(addr, fwb) (((addr) < (fwb)->start)?-1:\ ((fwb)->end < (addr))?1:0) /* - * To lookup binded process from IEEE1394 address. + * To lookup bound process from IEEE1394 address. */ struct fw_bind * fw_bindlookup(struct firewire_comm *fc, u_int16_t dest_hi, u_int32_t dest_lo) { u_int64_t addr; struct fw_bind *tfw; addr = ((u_int64_t)dest_hi << 32) | dest_lo; STAILQ_FOREACH(tfw, &fc->binds, fclist) if (tfw->act_type != FWACT_NULL && BIND_CMP(addr, tfw) == 0) return(tfw); return(NULL); } /* * To bind IEEE1394 address block to process. */ int fw_bindadd(struct firewire_comm *fc, struct fw_bind *fwb) { struct fw_bind *tfw, *prev = NULL; if (fwb->start > fwb->end) { printf("%s: invalid range\n", __func__); return EINVAL; } STAILQ_FOREACH(tfw, &fc->binds, fclist) { if (fwb->end < tfw->start) break; prev = tfw; } if (prev == NULL) { STAILQ_INSERT_HEAD(&fc->binds, fwb, fclist); goto out; } if (prev->end < fwb->start) { STAILQ_INSERT_AFTER(&fc->binds, prev, fwb, fclist); goto out; } printf("%s: bind failed\n", __func__); return (EBUSY); out: if (fwb->act_type == FWACT_CH) STAILQ_INSERT_HEAD(&fc->ir[fwb->sub]->binds, fwb, chlist); return (0); } /* * To free IEEE1394 address block. */ int fw_bindremove(struct firewire_comm *fc, struct fw_bind *fwb) { #if 0 struct fw_xfer *xfer, *next; #endif struct fw_bind *tfw; int s; s = splfw(); STAILQ_FOREACH(tfw, &fc->binds, fclist) if (tfw == fwb) { STAILQ_REMOVE(&fc->binds, fwb, fw_bind, fclist); goto found; } - printf("%s: no such bind\n", __func__); + printf("%s: no such binding\n", __func__); splx(s); return (1); found: #if 0 /* shall we do this? */ for (xfer = STAILQ_FIRST(&fwb->xferlist); xfer != NULL; xfer = next) { next = STAILQ_NEXT(xfer, link); fw_xfer_free(xfer); } STAILQ_INIT(&fwb->xferlist); #endif splx(s); return 0; } /* * To free transaction label. */ static void fw_tl_free(struct firewire_comm *fc, struct fw_xfer *xfer) { struct tlabel *tl; int s = splfw(); for( tl = STAILQ_FIRST(&fc->tlabels[xfer->tl]); tl != NULL; tl = STAILQ_NEXT(tl, link)){ if(tl->xfer == xfer){ STAILQ_REMOVE(&fc->tlabels[xfer->tl], tl, tlabel, link); free(tl, M_FW); splx(s); return; } } splx(s); return; } /* * To obtain XFER structure by transaction label. */ static struct fw_xfer * fw_tl2xfer(struct firewire_comm *fc, int node, int tlabel) { struct fw_xfer *xfer; struct tlabel *tl; int s = splfw(); for( tl = STAILQ_FIRST(&fc->tlabels[tlabel]); tl != NULL; tl = STAILQ_NEXT(tl, link)){ if(tl->xfer->send.hdr.mode.hdr.dst == node){ xfer = tl->xfer; splx(s); if (firewire_debug > 2) printf("fw_tl2xfer: found tl=%d\n", tlabel); return(xfer); } } if (firewire_debug > 1) printf("fw_tl2xfer: not found tl=%d\n", tlabel); splx(s); return(NULL); } /* * To allocate IEEE1394 XFER structure. */ struct fw_xfer * fw_xfer_alloc(struct malloc_type *type) { struct fw_xfer *xfer; xfer = malloc(sizeof(struct fw_xfer), type, M_NOWAIT | M_ZERO); if (xfer == NULL) return xfer; xfer->malloc = type; return xfer; } struct fw_xfer * fw_xfer_alloc_buf(struct malloc_type *type, int send_len, int recv_len) { struct fw_xfer *xfer; xfer = fw_xfer_alloc(type); if (xfer == NULL) return(NULL); xfer->send.pay_len = send_len; xfer->recv.pay_len = recv_len; if (send_len > 0) { xfer->send.payload = malloc(send_len, type, M_NOWAIT | M_ZERO); if (xfer->send.payload == NULL) { fw_xfer_free(xfer); return(NULL); } } if (recv_len > 0) { xfer->recv.payload = malloc(recv_len, type, M_NOWAIT); if (xfer->recv.payload == NULL) { if (xfer->send.payload != NULL) free(xfer->send.payload, type); fw_xfer_free(xfer); return(NULL); } } return(xfer); } /* * IEEE1394 XFER post process. */ void fw_xfer_done(struct fw_xfer *xfer) { if (xfer->act.hand == NULL) { printf("act.hand == NULL\n"); return; } if (xfer->fc == NULL) panic("fw_xfer_done: why xfer->fc is NULL?"); xfer->act.hand(xfer); } void fw_xfer_unload(struct fw_xfer* xfer) { int s; if(xfer == NULL ) return; if(xfer->state == FWXF_INQ){ printf("fw_xfer_free FWXF_INQ\n"); s = splfw(); STAILQ_REMOVE(&xfer->q->q, xfer, fw_xfer, link); xfer->q->queued --; splx(s); } if (xfer->fc != NULL) { #if 1 if(xfer->state == FWXF_START) /* * This could happen if: * 1. We call fwohci_arcv() before fwohci_txd(). * 2. firewire_watch() is called. */ printf("fw_xfer_free FWXF_START\n"); #endif fw_tl_free(xfer->fc, xfer); } xfer->state = FWXF_INIT; xfer->resp = 0; xfer->retry = 0; } /* * To free IEEE1394 XFER structure. */ void fw_xfer_free_buf( struct fw_xfer* xfer) { if (xfer == NULL) { printf("%s: xfer == NULL\n", __func__); return; } fw_xfer_unload(xfer); if(xfer->send.payload != NULL){ free(xfer->send.payload, xfer->malloc); } if(xfer->recv.payload != NULL){ free(xfer->recv.payload, xfer->malloc); } free(xfer, xfer->malloc); } void fw_xfer_free( struct fw_xfer* xfer) { if (xfer == NULL) { printf("%s: xfer == NULL\n", __func__); return; } fw_xfer_unload(xfer); free(xfer, xfer->malloc); } void fw_asy_callback_free(struct fw_xfer *xfer) { #if 0 printf("asyreq done state=%d resp=%d\n", xfer->state, xfer->resp); #endif fw_xfer_free(xfer); } /* * To configure PHY. */ static void fw_phy_config(struct firewire_comm *fc, int root_node, int gap_count) { struct fw_xfer *xfer; struct fw_pkt *fp; fc->status = FWBUSPHYCONF; xfer = fw_xfer_alloc(M_FWXFER); if (xfer == NULL) return; xfer->fc = fc; xfer->retry_req = fw_asybusy; xfer->act.hand = fw_asy_callback_free; fp = &xfer->send.hdr; fp->mode.ld[1] = 0; if (root_node >= 0) fp->mode.ld[1] |= (root_node & 0x3f) << 24 | 1 << 23; if (gap_count >= 0) fp->mode.ld[1] |= 1 << 22 | (gap_count & 0x3f) << 16; fp->mode.ld[2] = ~fp->mode.ld[1]; /* XXX Dangerous, how to pass PHY packet to device driver */ fp->mode.common.tcode |= FWTCODE_PHY; if (firewire_debug) printf("send phy_config root_node=%d gap_count=%d\n", root_node, gap_count); fw_asyreq(fc, -1, xfer); } #if 0 /* * Dump self ID. */ static void fw_print_sid(u_int32_t sid) { union fw_self_id *s; s = (union fw_self_id *) &sid; printf("node:%d link:%d gap:%d spd:%d del:%d con:%d pwr:%d" " p0:%d p1:%d p2:%d i:%d m:%d\n", s->p0.phy_id, s->p0.link_active, s->p0.gap_count, s->p0.phy_speed, s->p0.phy_delay, s->p0.contender, s->p0.power_class, s->p0.port0, s->p0.port1, s->p0.port2, s->p0.initiated_reset, s->p0.more_packets); } #endif /* * To receive self ID. */ void fw_sidrcv(struct firewire_comm* fc, u_int32_t *sid, u_int len) { u_int32_t *p; union fw_self_id *self_id; u_int i, j, node, c_port = 0, i_branch = 0; fc->sid_cnt = len /(sizeof(u_int32_t) * 2); fc->status = FWBUSINIT; fc->max_node = fc->nodeid & 0x3f; CSRARC(fc, NODE_IDS) = ((u_int32_t)fc->nodeid) << 16; fc->status = FWBUSCYMELECT; fc->topology_map->crc_len = 2; fc->topology_map->generation ++; fc->topology_map->self_id_count = 0; fc->topology_map->node_count = 0; fc->speed_map->generation ++; fc->speed_map->crc_len = 1 + (64*64 + 3) / 4; self_id = &fc->topology_map->self_id[0]; for(i = 0; i < fc->sid_cnt; i ++){ if (sid[1] != ~sid[0]) { printf("fw_sidrcv: invalid self-id packet\n"); sid += 2; continue; } *self_id = *((union fw_self_id *)sid); fc->topology_map->crc_len++; if(self_id->p0.sequel == 0){ fc->topology_map->node_count ++; c_port = 0; #if 0 fw_print_sid(sid[0]); #endif node = self_id->p0.phy_id; if(fc->max_node < node){ fc->max_node = self_id->p0.phy_id; } /* XXX I'm not sure this is the right speed_map */ fc->speed_map->speed[node][node] = self_id->p0.phy_speed; for (j = 0; j < node; j ++) { fc->speed_map->speed[j][node] = fc->speed_map->speed[node][j] = min(fc->speed_map->speed[j][j], self_id->p0.phy_speed); } if ((fc->irm == -1 || self_id->p0.phy_id > fc->irm) && (self_id->p0.link_active && self_id->p0.contender)) { fc->irm = self_id->p0.phy_id; } if(self_id->p0.port0 >= 0x2){ c_port++; } if(self_id->p0.port1 >= 0x2){ c_port++; } if(self_id->p0.port2 >= 0x2){ c_port++; } } if(c_port > 2){ i_branch += (c_port - 2); } sid += 2; self_id++; fc->topology_map->self_id_count ++; } device_printf(fc->bdev, "%d nodes", fc->max_node + 1); /* CRC */ fc->topology_map->crc = fw_crc16( (u_int32_t *)&fc->topology_map->generation, fc->topology_map->crc_len * 4); fc->speed_map->crc = fw_crc16( (u_int32_t *)&fc->speed_map->generation, fc->speed_map->crc_len * 4); /* byteswap and copy to CSR */ p = (u_int32_t *)fc->topology_map; for (i = 0; i <= fc->topology_map->crc_len; i++) CSRARC(fc, TOPO_MAP + i * 4) = htonl(*p++); p = (u_int32_t *)fc->speed_map; CSRARC(fc, SPED_MAP) = htonl(*p++); CSRARC(fc, SPED_MAP + 4) = htonl(*p++); /* don't byte-swap u_int8_t array */ bcopy(p, &CSRARC(fc, SPED_MAP + 8), (fc->speed_map->crc_len - 1)*4); fc->max_hop = fc->max_node - i_branch; printf(", maxhop <= %d", fc->max_hop); if(fc->irm == -1 ){ printf(", Not found IRM capable node"); }else{ printf(", cable IRM = %d", fc->irm); if (fc->irm == fc->nodeid) printf(" (me)"); } printf("\n"); if (try_bmr && (fc->irm != -1) && (CSRARC(fc, BUS_MGR_ID) == 0x3f)) { if (fc->irm == fc->nodeid) { fc->status = FWBUSMGRDONE; CSRARC(fc, BUS_MGR_ID) = fc->set_bmr(fc, fc->irm); fw_bmr(fc); } else { fc->status = FWBUSMGRELECT; callout_reset(&fc->bmr_callout, hz/8, (void *)fw_try_bmr, (void *)fc); } } else fc->status = FWBUSMGRDONE; callout_reset(&fc->busprobe_callout, hz/4, (void *)fw_bus_probe, (void *)fc); } /* * To probe devices on the IEEE1394 bus. */ static void fw_bus_probe(struct firewire_comm *fc) { int s; struct fw_device *fwdev; s = splfw(); fc->status = FWBUSEXPLORE; fc->retry_count = 0; /* Invalidate all devices, just after bus reset. */ STAILQ_FOREACH(fwdev, &fc->devices, link) if (fwdev->status != FWDEVINVAL) { fwdev->status = FWDEVINVAL; fwdev->rcnt = 0; } fc->ongonode = 0; fc->ongoaddr = CSRROMOFF; fc->ongodev = NULL; fc->ongoeui.hi = 0xffffffff; fc->ongoeui.lo = 0xffffffff; fw_bus_explore(fc); splx(s); } /* * Find the self_id packet for a node, ignoring sequels. */ static union fw_self_id * fw_find_self_id(struct firewire_comm *fc, int node) { uint32_t i; union fw_self_id *s; for (i = 0; i < fc->topology_map->self_id_count; i++) { s = &fc->topology_map->self_id[i]; if (s->p0.sequel) continue; if (s->p0.phy_id == node) return s; } return 0; } /* * To collect device informations on the IEEE1394 bus. */ static void fw_bus_explore(struct firewire_comm *fc ) { int err = 0; struct fw_device *fwdev, *pfwdev, *tfwdev; u_int32_t addr; struct fw_xfer *xfer; struct fw_pkt *fp; if(fc->status != FWBUSEXPLORE) return; loop: if(fc->ongonode == fc->nodeid) fc->ongonode++; if(fc->ongonode > fc->max_node) goto done; if(fc->ongonode >= 0x3f) goto done; /* check link */ /* XXX we need to check phy_id first */ if (!fw_find_self_id(fc, fc->ongonode)->p0.link_active) { if (firewire_debug) printf("node%d: link down\n", fc->ongonode); fc->ongonode++; goto loop; } if(fc->ongoaddr <= CSRROMOFF && fc->ongoeui.hi == 0xffffffff && fc->ongoeui.lo == 0xffffffff ){ fc->ongoaddr = CSRROMOFF; addr = 0xf0000000 | fc->ongoaddr; }else if(fc->ongoeui.hi == 0xffffffff ){ fc->ongoaddr = CSRROMOFF + 0xc; addr = 0xf0000000 | fc->ongoaddr; }else if(fc->ongoeui.lo == 0xffffffff ){ fc->ongoaddr = CSRROMOFF + 0x10; addr = 0xf0000000 | fc->ongoaddr; }else if(fc->ongodev == NULL){ STAILQ_FOREACH(fwdev, &fc->devices, link) if (FW_EUI64_EQUAL(fwdev->eui, fc->ongoeui)) break; if(fwdev != NULL){ fwdev->dst = fc->ongonode; fwdev->status = FWDEVINIT; fc->ongodev = fwdev; fc->ongoaddr = CSRROMOFF; addr = 0xf0000000 | fc->ongoaddr; goto dorequest; } fwdev = malloc(sizeof(struct fw_device), M_FW, M_NOWAIT | M_ZERO); if(fwdev == NULL) return; fwdev->fc = fc; fwdev->rommax = 0; fwdev->dst = fc->ongonode; fwdev->eui.hi = fc->ongoeui.hi; fwdev->eui.lo = fc->ongoeui.lo; fwdev->status = FWDEVINIT; fwdev->speed = fc->speed_map->speed[fc->nodeid][fc->ongonode]; pfwdev = NULL; STAILQ_FOREACH(tfwdev, &fc->devices, link) { if (tfwdev->eui.hi > fwdev->eui.hi || (tfwdev->eui.hi == fwdev->eui.hi && tfwdev->eui.lo > fwdev->eui.lo)) break; pfwdev = tfwdev; } if (pfwdev == NULL) STAILQ_INSERT_HEAD(&fc->devices, fwdev, link); else STAILQ_INSERT_AFTER(&fc->devices, pfwdev, fwdev, link); device_printf(fc->bdev, "New %s device ID:%08x%08x\n", linkspeed[fwdev->speed], fc->ongoeui.hi, fc->ongoeui.lo); fc->ongodev = fwdev; fc->ongoaddr = CSRROMOFF; addr = 0xf0000000 | fc->ongoaddr; }else{ addr = 0xf0000000 | fc->ongoaddr; } dorequest: #if 0 xfer = asyreqq(fc, FWSPD_S100, 0, 0, ((FWLOCALBUS | fc->ongonode) << 16) | 0xffff , addr, fw_bus_explore_callback); if(xfer == NULL) goto done; #else xfer = fw_xfer_alloc(M_FWXFER); if(xfer == NULL){ goto done; } xfer->send.spd = 0; fp = &xfer->send.hdr; fp->mode.rreqq.dest_hi = 0xffff; fp->mode.rreqq.tlrt = 0; fp->mode.rreqq.tcode = FWTCODE_RREQQ; fp->mode.rreqq.pri = 0; fp->mode.rreqq.src = 0; fp->mode.rreqq.dst = FWLOCALBUS | fc->ongonode; fp->mode.rreqq.dest_lo = addr; xfer->act.hand = fw_bus_explore_callback; if (firewire_debug) printf("node%d: explore addr=0x%x\n", fc->ongonode, fc->ongoaddr); err = fw_asyreq(fc, -1, xfer); if(err){ fw_xfer_free( xfer); return; } #endif return; done: /* fw_attach_devs */ fc->status = FWBUSEXPDONE; if (firewire_debug) printf("bus_explore done\n"); fw_attach_dev(fc); return; } /* Portable Async. request read quad */ struct fw_xfer * asyreqq(struct firewire_comm *fc, u_int8_t spd, u_int8_t tl, u_int8_t rt, u_int32_t addr_hi, u_int32_t addr_lo, void (*hand) (struct fw_xfer*)) { struct fw_xfer *xfer; struct fw_pkt *fp; int err; xfer = fw_xfer_alloc(M_FWXFER); if (xfer == NULL) return NULL; xfer->send.spd = spd; /* XXX:min(spd, fc->spd) */ fp = &xfer->send.hdr; fp->mode.rreqq.dest_hi = addr_hi & 0xffff; if(tl & FWP_TL_VALID){ fp->mode.rreqq.tlrt = (tl & 0x3f) << 2; }else{ fp->mode.rreqq.tlrt = 0; } fp->mode.rreqq.tlrt |= rt & 0x3; fp->mode.rreqq.tcode = FWTCODE_RREQQ; fp->mode.rreqq.pri = 0; fp->mode.rreqq.src = 0; fp->mode.rreqq.dst = addr_hi >> 16; fp->mode.rreqq.dest_lo = addr_lo; xfer->act.hand = hand; err = fw_asyreq(fc, -1, xfer); if(err){ fw_xfer_free( xfer); return NULL; } return xfer; } /* * Callback for the IEEE1394 bus information collection. */ static void fw_bus_explore_callback(struct fw_xfer *xfer) { struct firewire_comm *fc; struct fw_pkt *sfp,*rfp; struct csrhdr *chdr; struct csrdir *csrd; struct csrreg *csrreg; u_int32_t offset; if(xfer == NULL) { printf("xfer == NULL\n"); return; } fc = xfer->fc; if (firewire_debug) printf("node%d: callback addr=0x%x\n", fc->ongonode, fc->ongoaddr); if(xfer->resp != 0){ device_printf(fc->bdev, "bus_explore node=%d addr=0x%x resp=%d retry=%d\n", fc->ongonode, fc->ongoaddr, xfer->resp, xfer->retry); if (xfer->retry < fc->max_asyretry) { fw_asystart(xfer); return; } goto errnode; } sfp = &xfer->send.hdr; rfp = &xfer->recv.hdr; #if 0 { u_int32_t *qld; int i; qld = (u_int32_t *)xfer->recv.buf; printf("len:%d\n", xfer->recv.len); for( i = 0 ; i <= xfer->recv.len && i < 32; i+= 4){ printf("0x%08x ", rfp->mode.ld[i/4]); if((i % 16) == 15) printf("\n"); } if((i % 16) != 15) printf("\n"); } #endif if(fc->ongodev == NULL){ if(sfp->mode.rreqq.dest_lo == (0xf0000000 | CSRROMOFF)){ rfp->mode.rresq.data = ntohl(rfp->mode.rresq.data); chdr = (struct csrhdr *)(&rfp->mode.rresq.data); -/* If CSR is minimal confinguration, more investgation is not needed. */ +/* If CSR is minimal confinguration, more investigation is not needed. */ if(chdr->info_len == 1){ if (firewire_debug) printf("node%d: minimal config\n", fc->ongonode); goto nextnode; }else{ fc->ongoaddr = CSRROMOFF + 0xc; } }else if(sfp->mode.rreqq.dest_lo == (0xf0000000 |(CSRROMOFF + 0xc))){ fc->ongoeui.hi = ntohl(rfp->mode.rresq.data); fc->ongoaddr = CSRROMOFF + 0x10; }else if(sfp->mode.rreqq.dest_lo == (0xf0000000 |(CSRROMOFF + 0x10))){ fc->ongoeui.lo = ntohl(rfp->mode.rresq.data); if (fc->ongoeui.hi == 0 && fc->ongoeui.lo == 0) { if (firewire_debug) printf("node%d: eui64 is zero.\n", fc->ongonode); goto nextnode; } fc->ongoaddr = CSRROMOFF; } }else{ if (fc->ongoaddr == CSRROMOFF && fc->ongodev->csrrom[0] == ntohl(rfp->mode.rresq.data)) { fc->ongodev->status = FWDEVATTACHED; goto nextnode; } fc->ongodev->csrrom[(fc->ongoaddr - CSRROMOFF)/4] = ntohl(rfp->mode.rresq.data); if(fc->ongoaddr > fc->ongodev->rommax){ fc->ongodev->rommax = fc->ongoaddr; } csrd = SLIST_FIRST(&fc->ongocsr); if((csrd = SLIST_FIRST(&fc->ongocsr)) == NULL){ chdr = (struct csrhdr *)(fc->ongodev->csrrom); offset = CSRROMOFF; }else{ chdr = (struct csrhdr *)&fc->ongodev->csrrom[(csrd->off - CSRROMOFF)/4]; offset = csrd->off; } if(fc->ongoaddr > (CSRROMOFF + 0x14) && fc->ongoaddr != offset){ csrreg = (struct csrreg *)&fc->ongodev->csrrom[(fc->ongoaddr - CSRROMOFF)/4]; if( csrreg->key == 0x81 || csrreg->key == 0xd1){ csrd = SLIST_FIRST(&fc->csrfree); if(csrd == NULL){ goto nextnode; }else{ csrd->ongoaddr = fc->ongoaddr; fc->ongoaddr += csrreg->val * 4; csrd->off = fc->ongoaddr; SLIST_REMOVE_HEAD(&fc->csrfree, link); SLIST_INSERT_HEAD(&fc->ongocsr, csrd, link); goto nextaddr; } } } fc->ongoaddr += 4; if(((fc->ongoaddr - offset)/4 > chdr->crc_len) && (fc->ongodev->rommax < 0x414)){ if(fc->ongodev->rommax <= 0x414){ csrd = SLIST_FIRST(&fc->csrfree); if(csrd == NULL) goto nextnode; csrd->off = fc->ongoaddr; csrd->ongoaddr = fc->ongoaddr; SLIST_REMOVE_HEAD(&fc->csrfree, link); SLIST_INSERT_HEAD(&fc->ongocsr, csrd, link); } goto nextaddr; } while(((fc->ongoaddr - offset)/4 > chdr->crc_len)){ if(csrd == NULL){ goto nextnode; }; fc->ongoaddr = csrd->ongoaddr + 4; SLIST_REMOVE_HEAD(&fc->ongocsr, link); SLIST_INSERT_HEAD(&fc->csrfree, csrd, link); csrd = SLIST_FIRST(&fc->ongocsr); if((csrd = SLIST_FIRST(&fc->ongocsr)) == NULL){ chdr = (struct csrhdr *)(fc->ongodev->csrrom); offset = CSRROMOFF; }else{ chdr = (struct csrhdr *)&(fc->ongodev->csrrom[(csrd->off - CSRROMOFF)/4]); offset = csrd->off; } } if((fc->ongoaddr - CSRROMOFF) > CSRROMSIZE){ goto nextnode; } } nextaddr: fw_xfer_free( xfer); fw_bus_explore(fc); return; errnode: fc->retry_count++; if (fc->ongodev != NULL) { fc->ongodev->status = FWDEVINVAL; /* Invalidate ROM */ fc->ongodev->csrrom[0] = 0; } nextnode: fw_xfer_free( xfer); fc->ongonode++; /* housekeeping work space */ fc->ongoaddr = CSRROMOFF; fc->ongodev = NULL; fc->ongoeui.hi = 0xffffffff; fc->ongoeui.lo = 0xffffffff; while((csrd = SLIST_FIRST(&fc->ongocsr)) != NULL){ SLIST_REMOVE_HEAD(&fc->ongocsr, link); SLIST_INSERT_HEAD(&fc->csrfree, csrd, link); } fw_bus_explore(fc); return; } /* * To attach sub-devices layer onto IEEE1394 bus. */ static void fw_attach_dev(struct firewire_comm *fc) { struct fw_device *fwdev, *next; int i, err; device_t *devlistp; int devcnt; struct firewire_dev_comm *fdc; for (fwdev = STAILQ_FIRST(&fc->devices); fwdev != NULL; fwdev = next) { next = STAILQ_NEXT(fwdev, link); if (fwdev->status == FWDEVINIT) { fwdev->status = FWDEVATTACHED; } else if (fwdev->status == FWDEVINVAL) { fwdev->rcnt ++; if (fwdev->rcnt > hold_count) { /* * Remove devices which have not been seen * for a while. */ STAILQ_REMOVE(&fc->devices, fwdev, fw_device, link); free(fwdev, M_FW); } } } err = device_get_children(fc->bdev, &devlistp, &devcnt); if( err != 0 ) return; for( i = 0 ; i < devcnt ; i++){ if (device_get_state(devlistp[i]) >= DS_ATTACHED) { fdc = device_get_softc(devlistp[i]); if (fdc->post_explore != NULL) fdc->post_explore(fdc); } } free(devlistp, M_TEMP); if (fc->retry_count > 0) { device_printf(fc->bdev, "bus_explore failed for %d nodes\n", fc->retry_count); #if 0 callout_reset(&fc->retry_probe_callout, hz*2, (void *)fc->ibr, (void *)fc); #endif } return; } /* - * To allocate uniq transaction label. + * To allocate unique transaction label. */ static int fw_get_tlabel(struct firewire_comm *fc, struct fw_xfer *xfer) { u_int i; struct tlabel *tl, *tmptl; int s; static u_int32_t label = 0; s = splfw(); for( i = 0 ; i < 0x40 ; i ++){ label = (label + 1) & 0x3f; for(tmptl = STAILQ_FIRST(&fc->tlabels[label]); tmptl != NULL; tmptl = STAILQ_NEXT(tmptl, link)){ if (tmptl->xfer->send.hdr.mode.hdr.dst == xfer->send.hdr.mode.hdr.dst) break; } if(tmptl == NULL) { tl = malloc(sizeof(struct tlabel),M_FW,M_NOWAIT); if (tl == NULL) { splx(s); return (-1); } tl->xfer = xfer; STAILQ_INSERT_TAIL(&fc->tlabels[label], tl, link); splx(s); if (firewire_debug > 1) printf("fw_get_tlabel: dst=%d tl=%d\n", xfer->send.hdr.mode.hdr.dst, label); return(label); } } splx(s); printf("fw_get_tlabel: no free tlabel\n"); return(-1); } static void fw_rcv_copy(struct fw_rcv_buf *rb) { struct fw_pkt *pkt; u_char *p; struct tcode_info *tinfo; u_int res, i, len, plen; rb->xfer->recv.spd -= rb->spd; pkt = (struct fw_pkt *)rb->vec->iov_base; tinfo = &rb->fc->tcode[pkt->mode.hdr.tcode]; /* Copy header */ p = (u_char *)&rb->xfer->recv.hdr; bcopy(rb->vec->iov_base, p, tinfo->hdr_len); (u_char *)rb->vec->iov_base += tinfo->hdr_len; rb->vec->iov_len -= tinfo->hdr_len; /* Copy payload */ p = (u_char *)rb->xfer->recv.payload; res = rb->xfer->recv.pay_len; /* special handling for RRESQ */ if (pkt->mode.hdr.tcode == FWTCODE_RRESQ && p != NULL && res >= sizeof(u_int32_t)) { *(u_int32_t *)p = pkt->mode.rresq.data; rb->xfer->recv.pay_len = sizeof(u_int32_t); return; } if ((tinfo->flag & FWTI_BLOCK_ASY) == 0) return; plen = pkt->mode.rresb.len; for (i = 0; i < rb->nvec; i++, rb->vec++) { len = MIN(rb->vec->iov_len, plen); if (res < len) { printf("rcv buffer(%d) is %d bytes short.\n", rb->xfer->recv.pay_len, len - res); len = res; } bcopy(rb->vec->iov_base, p, len); p += len; res -= len; plen -= len; if (res == 0 || plen == 0) break; } rb->xfer->recv.pay_len -= res; } /* - * Generic packet receving process. + * Generic packet receiving process. */ void fw_rcv(struct fw_rcv_buf *rb) { struct fw_pkt *fp, *resfp; struct fw_bind *bind; int tcode, s; int i, len, oldstate; #if 0 { u_int32_t *qld; int i; qld = (u_int32_t *)buf; printf("spd %d len:%d\n", spd, len); for( i = 0 ; i <= len && i < 32; i+= 4){ printf("0x%08x ", ntohl(qld[i/4])); if((i % 16) == 15) printf("\n"); } if((i % 16) != 15) printf("\n"); } #endif fp = (struct fw_pkt *)rb->vec[0].iov_base; tcode = fp->mode.common.tcode; switch (tcode) { case FWTCODE_WRES: case FWTCODE_RRESQ: case FWTCODE_RRESB: case FWTCODE_LRES: rb->xfer = fw_tl2xfer(rb->fc, fp->mode.hdr.src, fp->mode.hdr.tlrt >> 2); if(rb->xfer == NULL) { printf("fw_rcv: unknown response " "%s(%x) src=0x%x tl=0x%x rt=%d data=0x%x\n", tcode_str[tcode], tcode, fp->mode.hdr.src, fp->mode.hdr.tlrt >> 2, fp->mode.hdr.tlrt & 3, fp->mode.rresq.data); #if 1 printf("try ad-hoc work around!!\n"); rb->xfer = fw_tl2xfer(rb->fc, fp->mode.hdr.src, (fp->mode.hdr.tlrt >> 2)^3); if (rb->xfer == NULL) { printf("no use...\n"); goto err; } #else goto err; #endif } fw_rcv_copy(rb); if (rb->xfer->recv.hdr.mode.wres.rtcode != RESP_CMP) rb->xfer->resp = EIO; else rb->xfer->resp = 0; /* make sure the packet is drained in AT queue */ oldstate = rb->xfer->state; rb->xfer->state = FWXF_RCVD; switch (oldstate) { case FWXF_SENT: fw_xfer_done(rb->xfer); break; case FWXF_START: #if 0 if (firewire_debug) printf("not sent yet tl=%x\n", rb->xfer->tl); #endif break; default: printf("unexpected state %d\n", rb->xfer->state); } return; case FWTCODE_WREQQ: case FWTCODE_WREQB: case FWTCODE_RREQQ: case FWTCODE_RREQB: case FWTCODE_LREQ: bind = fw_bindlookup(rb->fc, fp->mode.rreqq.dest_hi, fp->mode.rreqq.dest_lo); if(bind == NULL){ printf("Unknown service addr 0x%04x:0x%08x %s(%x)" #if defined(__DragonFly__) || __FreeBSD_version < 500000 " src=0x%x data=%lx\n", #else " src=0x%x data=%x\n", #endif fp->mode.wreqq.dest_hi, fp->mode.wreqq.dest_lo, tcode_str[tcode], tcode, fp->mode.hdr.src, ntohl(fp->mode.wreqq.data)); if (rb->fc->status == FWBUSRESET) { printf("fw_rcv: cannot respond(bus reset)!\n"); goto err; } rb->xfer = fw_xfer_alloc(M_FWXFER); if(rb->xfer == NULL){ return; } rb->xfer->send.spd = rb->spd; rb->xfer->send.pay_len = 0; resfp = &rb->xfer->send.hdr; switch (tcode) { case FWTCODE_WREQQ: case FWTCODE_WREQB: resfp->mode.hdr.tcode = FWTCODE_WRES; break; case FWTCODE_RREQQ: resfp->mode.hdr.tcode = FWTCODE_RRESQ; break; case FWTCODE_RREQB: resfp->mode.hdr.tcode = FWTCODE_RRESB; break; case FWTCODE_LREQ: resfp->mode.hdr.tcode = FWTCODE_LRES; break; } resfp->mode.hdr.dst = fp->mode.hdr.src; resfp->mode.hdr.tlrt = fp->mode.hdr.tlrt; resfp->mode.hdr.pri = fp->mode.hdr.pri; resfp->mode.rresb.rtcode = RESP_ADDRESS_ERROR; resfp->mode.rresb.extcode = 0; resfp->mode.rresb.len = 0; /* rb->xfer->act.hand = fw_asy_callback; */ rb->xfer->act.hand = fw_xfer_free; if(fw_asyreq(rb->fc, -1, rb->xfer)){ fw_xfer_free(rb->xfer); return; } goto err; } len = 0; for (i = 0; i < rb->nvec; i ++) len += rb->vec[i].iov_len; switch(bind->act_type){ case FWACT_XFER: /* splfw()?? */ rb->xfer = STAILQ_FIRST(&bind->xferlist); if (rb->xfer == NULL) { printf("Discard a packet for this bind.\n"); goto err; } STAILQ_REMOVE_HEAD(&bind->xferlist, link); fw_rcv_copy(rb); rb->xfer->act.hand(rb->xfer); return; break; case FWACT_CH: if(rb->fc->ir[bind->sub]->queued >= rb->fc->ir[bind->sub]->maxq){ device_printf(rb->fc->bdev, "Discard a packet %x %d\n", bind->sub, rb->fc->ir[bind->sub]->queued); goto err; } rb->xfer = STAILQ_FIRST(&bind->xferlist); if (rb->xfer == NULL) { printf("Discard packet for this bind\n"); goto err; } STAILQ_REMOVE_HEAD(&bind->xferlist, link); fw_rcv_copy(rb); s = splfw(); rb->fc->ir[bind->sub]->queued++; STAILQ_INSERT_TAIL(&rb->fc->ir[bind->sub]->q, rb->xfer, link); splx(s); wakeup((caddr_t)rb->fc->ir[bind->sub]); return; break; default: goto err; break; } break; #if 0 /* shouldn't happen ?? or for GASP */ case FWTCODE_STREAM: { struct fw_xferq *xferq; xferq = rb->fc->ir[sub]; #if 0 printf("stream rcv dma %d len %d off %d spd %d\n", sub, len, off, spd); #endif if(xferq->queued >= xferq->maxq) { printf("receive queue is full\n"); goto err; } /* XXX get xfer from xfer queue, we don't need copy for per packet mode */ rb->xfer = fw_xfer_alloc_buf(M_FWXFER, 0, /* XXX */ vec[0].iov_len); if (rb->xfer == NULL) goto err; fw_rcv_copy(rb) s = splfw(); xferq->queued++; STAILQ_INSERT_TAIL(&xferq->q, rb->xfer, link); splx(s); sc = device_get_softc(rb->fc->bdev); #if defined(__DragonFly__) || __FreeBSD_version < 500000 if (&xferq->rsel.si_pid != 0) #else if (SEL_WAITING(&xferq->rsel)) #endif selwakeuppri(&xferq->rsel, FWPRI); if (xferq->flag & FWXFERQ_WAKEUP) { xferq->flag &= ~FWXFERQ_WAKEUP; wakeup((caddr_t)xferq); } if (xferq->flag & FWXFERQ_HANDLER) { xferq->hand(xferq); } return; break; } #endif default: printf("fw_rcv: unknow tcode %d\n", tcode); break; } err: return; } /* * Post process for Bus Manager election process. */ static void fw_try_bmr_callback(struct fw_xfer *xfer) { struct firewire_comm *fc; int bmr; if (xfer == NULL) return; fc = xfer->fc; if (xfer->resp != 0) goto error; if (xfer->recv.payload == NULL) goto error; if (xfer->recv.hdr.mode.lres.rtcode != FWRCODE_COMPLETE) goto error; bmr = ntohl(xfer->recv.payload[0]); if (bmr == 0x3f) bmr = fc->nodeid; CSRARC(fc, BUS_MGR_ID) = fc->set_bmr(fc, bmr & 0x3f); fw_xfer_free_buf(xfer); fw_bmr(fc); return; error: device_printf(fc->bdev, "bus manager election failed\n"); fw_xfer_free_buf(xfer); } /* * To candidate Bus Manager election process. */ static void fw_try_bmr(void *arg) { struct fw_xfer *xfer; struct firewire_comm *fc = (struct firewire_comm *)arg; struct fw_pkt *fp; int err = 0; xfer = fw_xfer_alloc_buf(M_FWXFER, 8, 4); if(xfer == NULL){ return; } xfer->send.spd = 0; fc->status = FWBUSMGRELECT; fp = &xfer->send.hdr; fp->mode.lreq.dest_hi = 0xffff; fp->mode.lreq.tlrt = 0; fp->mode.lreq.tcode = FWTCODE_LREQ; fp->mode.lreq.pri = 0; fp->mode.lreq.src = 0; fp->mode.lreq.len = 8; fp->mode.lreq.extcode = EXTCODE_CMP_SWAP; fp->mode.lreq.dst = FWLOCALBUS | fc->irm; fp->mode.lreq.dest_lo = 0xf0000000 | BUS_MGR_ID; xfer->send.payload[0] = htonl(0x3f); xfer->send.payload[1] = htonl(fc->nodeid); xfer->act.hand = fw_try_bmr_callback; err = fw_asyreq(fc, -1, xfer); if(err){ fw_xfer_free_buf(xfer); return; } return; } #ifdef FW_VMACCESS /* * Software implementation for physical memory block access. * XXX:Too slow, usef for debug purpose only. */ static void fw_vmaccess(struct fw_xfer *xfer){ struct fw_pkt *rfp, *sfp = NULL; u_int32_t *ld = (u_int32_t *)xfer->recv.buf; printf("vmaccess spd:%2x len:%03x data:%08x %08x %08x %08x\n", xfer->spd, xfer->recv.len, ntohl(ld[0]), ntohl(ld[1]), ntohl(ld[2]), ntohl(ld[3])); printf("vmaccess data:%08x %08x %08x %08x\n", ntohl(ld[4]), ntohl(ld[5]), ntohl(ld[6]), ntohl(ld[7])); if(xfer->resp != 0){ fw_xfer_free( xfer); return; } if(xfer->recv.buf == NULL){ fw_xfer_free( xfer); return; } rfp = (struct fw_pkt *)xfer->recv.buf; switch(rfp->mode.hdr.tcode){ /* XXX need fix for 64bit arch */ case FWTCODE_WREQB: xfer->send.buf = malloc(12, M_FW, M_NOWAIT); xfer->send.len = 12; sfp = (struct fw_pkt *)xfer->send.buf; bcopy(rfp->mode.wreqb.payload, (caddr_t)ntohl(rfp->mode.wreqb.dest_lo), ntohs(rfp->mode.wreqb.len)); sfp->mode.wres.tcode = FWTCODE_WRES; sfp->mode.wres.rtcode = 0; break; case FWTCODE_WREQQ: xfer->send.buf = malloc(12, M_FW, M_NOWAIT); xfer->send.len = 12; sfp->mode.wres.tcode = FWTCODE_WRES; *((u_int32_t *)(ntohl(rfp->mode.wreqb.dest_lo))) = rfp->mode.wreqq.data; sfp->mode.wres.rtcode = 0; break; case FWTCODE_RREQB: xfer->send.buf = malloc(16 + rfp->mode.rreqb.len, M_FW, M_NOWAIT); xfer->send.len = 16 + ntohs(rfp->mode.rreqb.len); sfp = (struct fw_pkt *)xfer->send.buf; bcopy((caddr_t)ntohl(rfp->mode.rreqb.dest_lo), sfp->mode.rresb.payload, (u_int16_t)ntohs(rfp->mode.rreqb.len)); sfp->mode.rresb.tcode = FWTCODE_RRESB; sfp->mode.rresb.len = rfp->mode.rreqb.len; sfp->mode.rresb.rtcode = 0; sfp->mode.rresb.extcode = 0; break; case FWTCODE_RREQQ: xfer->send.buf = malloc(16, M_FW, M_NOWAIT); xfer->send.len = 16; sfp = (struct fw_pkt *)xfer->send.buf; sfp->mode.rresq.data = *(u_int32_t *)(ntohl(rfp->mode.rreqq.dest_lo)); sfp->mode.wres.tcode = FWTCODE_RRESQ; sfp->mode.rresb.rtcode = 0; break; default: fw_xfer_free( xfer); return; } sfp->mode.hdr.dst = rfp->mode.hdr.src; xfer->dst = ntohs(rfp->mode.hdr.src); xfer->act.hand = fw_xfer_free; xfer->retry_req = fw_asybusy; sfp->mode.hdr.tlrt = rfp->mode.hdr.tlrt; sfp->mode.hdr.pri = 0; fw_asyreq(xfer->fc, -1, xfer); /**/ return; } #endif /* * CRC16 check-sum for IEEE1394 register blocks. */ u_int16_t fw_crc16(u_int32_t *ptr, u_int32_t len){ u_int32_t i, sum, crc = 0; int shift; len = (len + 3) & ~3; for(i = 0 ; i < len ; i+= 4){ for( shift = 28 ; shift >= 0 ; shift -= 4){ sum = ((crc >> 12) ^ (ptr[i/4] >> shift)) & 0xf; crc = (crc << 4) ^ ( sum << 12 ) ^ ( sum << 5) ^ sum; } crc &= 0xffff; } return((u_int16_t) crc); } static int fw_bmr(struct firewire_comm *fc) { struct fw_device fwdev; union fw_self_id *self_id; int cmstr; u_int32_t quad; /* Check to see if the current root node is cycle master capable */ self_id = fw_find_self_id(fc, fc->max_node); if (fc->max_node > 0) { /* XXX check cmc bit of businfo block rather than contender */ if (self_id->p0.link_active && self_id->p0.contender) cmstr = fc->max_node; else { device_printf(fc->bdev, "root node is not cycle master capable\n"); /* XXX shall we be the cycle master? */ cmstr = fc->nodeid; /* XXX need bus reset */ } } else cmstr = -1; device_printf(fc->bdev, "bus manager %d ", CSRARC(fc, BUS_MGR_ID)); if(CSRARC(fc, BUS_MGR_ID) != fc->nodeid) { /* We are not the bus manager */ printf("\n"); return(0); } printf("(me)\n"); /* Optimize gapcount */ if(fc->max_hop <= MAX_GAPHOP ) fw_phy_config(fc, cmstr, gap_cnt[fc->max_hop]); /* If we are the cycle master, nothing to do */ if (cmstr == fc->nodeid || cmstr == -1) return 0; /* Bus probe has not finished, make dummy fwdev for cmstr */ bzero(&fwdev, sizeof(fwdev)); fwdev.fc = fc; fwdev.dst = cmstr; fwdev.speed = 0; fwdev.maxrec = 8; /* 512 */ fwdev.status = FWDEVINIT; /* Set cmstr bit on the cycle master */ quad = htonl(1 << 8); fwmem_write_quad(&fwdev, NULL, 0/*spd*/, 0xffff, 0xf0000000 | STATE_SET, &quad, fw_asy_callback_free); return 0; } static int fw_modevent(module_t mode, int type, void *data) { int err = 0; #if defined(__FreeBSD__) && __FreeBSD_version >= 500000 static eventhandler_tag fwdev_ehtag = NULL; #endif switch (type) { case MOD_LOAD: #if defined(__FreeBSD__) && __FreeBSD_version >= 500000 fwdev_ehtag = EVENTHANDLER_REGISTER(dev_clone, fwdev_clone, 0, 1000); #endif break; case MOD_UNLOAD: #if defined(__FreeBSD__) && __FreeBSD_version >= 500000 if (fwdev_ehtag != NULL) EVENTHANDLER_DEREGISTER(dev_clone, fwdev_ehtag); #endif break; case MOD_SHUTDOWN: break; } return (err); } #ifdef __DragonFly__ DECLARE_DUMMY_MODULE(firewire); #endif DRIVER_MODULE(firewire,fwohci,firewire_driver,firewire_devclass,fw_modevent,0); MODULE_VERSION(firewire, 1); Index: head/sys/dev/firewire/fwohci.c =================================================================== --- head/sys/dev/firewire/fwohci.c (revision 129540) +++ head/sys/dev/firewire/fwohci.c (revision 129541) @@ -1,2899 +1,2899 @@ /* * Copyright (c) 2003 Hidetoshi Shimokawa * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the acknowledgement as bellow: * * This product includes software developed by K. Kobayashi and H. Shimokawa * * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #define ATRQ_CH 0 #define ATRS_CH 1 #define ARRQ_CH 2 #define ARRS_CH 3 #define ITX_CH 4 #define IRX_CH 0x24 #include #include #include #include #include #include #include #include #include #include #if defined(__DragonFly__) || __FreeBSD_version < 500000 #include /* for DELAY() */ #endif #ifdef __DragonFly__ #include "firewire.h" #include "firewirereg.h" #include "fwdma.h" #include "fwohcireg.h" #include "fwohcivar.h" #include "firewire_phy.h" #else #include #include #include #include #include #include #endif #undef OHCI_DEBUG static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", "STOR","LOAD","NOP ","STOP",}; static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", "UNDEF","REG","SYS","DEV"}; static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; char fwohcicode[32][0x20]={ "No stat","Undef","long","miss Ack err", "underrun","overrun","desc err", "data read err", "data write err","bus reset","timeout","tcode err", "Undef","Undef","unknown event","flushed", "Undef","ack complete","ack pend","Undef", "ack busy_X","ack busy_A","ack busy_B","Undef", "Undef","Undef","Undef","ack tardy", "Undef","ack data_err","ack type_err",""}; #define MAX_SPEED 3 extern char *linkspeed[]; u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; static struct tcode_info tinfo[] = { /* hdr_len block flag*/ /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, /* 2 WRES */ {12, FWTI_RES}, /* 3 XXX */ { 0, 0}, /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, /* 6 RRESQ */ {16, FWTI_RES}, /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, /* 8 CYCS */ { 0, 0}, /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, /* c XXX */ { 0, 0}, /* d XXX */ { 0, 0}, /* e PHY */ {12, FWTI_REQ}, /* f XXX */ { 0, 0} }; #define OHCI_WRITE_SIGMASK 0xffff0000 #define OHCI_READ_SIGMASK 0xffff0000 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) static void fwohci_ibr (struct firewire_comm *); static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *); static void fwohci_db_free (struct fwohci_dbch *); static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int); static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *); static void fwohci_start_atq (struct firewire_comm *); static void fwohci_start_ats (struct firewire_comm *); static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *); static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t); static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t); static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *); static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *); static int fwohci_irx_enable (struct firewire_comm *, int); static int fwohci_irx_disable (struct firewire_comm *, int); #if BYTE_ORDER == BIG_ENDIAN static void fwohci_irx_post (struct firewire_comm *, u_int32_t *); #endif static int fwohci_itxbuf_enable (struct firewire_comm *, int); static int fwohci_itx_disable (struct firewire_comm *, int); static void fwohci_timeout (void *); static void fwohci_set_intr (struct firewire_comm *, int); static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *); static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int); static void dump_db (struct fwohci_softc *, u_int32_t); static void print_db (struct fwohcidb_tr *, struct fwohcidb *, u_int32_t , u_int32_t); static void dump_dma (struct fwohci_softc *, u_int32_t); static u_int32_t fwohci_cyctimer (struct firewire_comm *); static void fwohci_rbuf_update (struct fwohci_softc *, int); static void fwohci_tbuf_update (struct fwohci_softc *, int); void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *); #if FWOHCI_TASKQUEUE static void fwohci_complete(void *, int); #endif /* * memory allocated for DMA programs */ #define DMA_PROG_ALLOC (8 * PAGE_SIZE) #define NDB FWMAXQUEUE #define OHCI_VERSION 0x00 #define OHCI_ATRETRY 0x08 #define OHCI_CROMHDR 0x18 #define OHCI_BUS_OPT 0x20 #define OHCI_BUSIRMC (1 << 31) #define OHCI_BUSCMC (1 << 30) #define OHCI_BUSISC (1 << 29) #define OHCI_BUSBMC (1 << 28) #define OHCI_BUSPMC (1 << 27) #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ OHCI_BUSBMC | OHCI_BUSPMC #define OHCI_EUID_HI 0x24 #define OHCI_EUID_LO 0x28 #define OHCI_CROMPTR 0x34 #define OHCI_HCCCTL 0x50 #define OHCI_HCCCTLCLR 0x54 #define OHCI_AREQHI 0x100 #define OHCI_AREQHICLR 0x104 #define OHCI_AREQLO 0x108 #define OHCI_AREQLOCLR 0x10c #define OHCI_PREQHI 0x110 #define OHCI_PREQHICLR 0x114 #define OHCI_PREQLO 0x118 #define OHCI_PREQLOCLR 0x11c #define OHCI_PREQUPPER 0x120 #define OHCI_SID_BUF 0x64 #define OHCI_SID_CNT 0x68 #define OHCI_SID_ERR (1 << 31) #define OHCI_SID_CNT_MASK 0xffc #define OHCI_IT_STAT 0x90 #define OHCI_IT_STATCLR 0x94 #define OHCI_IT_MASK 0x98 #define OHCI_IT_MASKCLR 0x9c #define OHCI_IR_STAT 0xa0 #define OHCI_IR_STATCLR 0xa4 #define OHCI_IR_MASK 0xa8 #define OHCI_IR_MASKCLR 0xac #define OHCI_LNKCTL 0xe0 #define OHCI_LNKCTLCLR 0xe4 #define OHCI_PHYACCESS 0xec #define OHCI_CYCLETIMER 0xf0 #define OHCI_DMACTL(off) (off) #define OHCI_DMACTLCLR(off) (off + 4) #define OHCI_DMACMD(off) (off + 0xc) #define OHCI_DMAMATCH(off) (off + 0x10) #define OHCI_ATQOFF 0x180 #define OHCI_ATQCTL OHCI_ATQOFF #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) #define OHCI_ATSOFF 0x1a0 #define OHCI_ATSCTL OHCI_ATSOFF #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) #define OHCI_ARQOFF 0x1c0 #define OHCI_ARQCTL OHCI_ARQOFF #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) #define OHCI_ARSOFF 0x1e0 #define OHCI_ARSCTL OHCI_ARSOFF #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) #define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) d_ioctl_t fwohci_ioctl; /* * Communication with PHY device */ static u_int32_t fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) { u_int32_t fun; addr &= 0xf; data &= 0xff; fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); OWRITE(sc, OHCI_PHYACCESS, fun); DELAY(100); return(fwphy_rddata( sc, addr)); } static u_int32_t fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) { struct fwohci_softc *sc = (struct fwohci_softc *)fc; int i; u_int32_t bm; #define OHCI_CSR_DATA 0x0c #define OHCI_CSR_COMP 0x10 #define OHCI_CSR_CONT 0x14 #define OHCI_BUS_MANAGER_ID 0 OWRITE(sc, OHCI_CSR_DATA, node); OWRITE(sc, OHCI_CSR_COMP, 0x3f); OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) DELAY(10); bm = OREAD(sc, OHCI_CSR_DATA); if((bm & 0x3f) == 0x3f) bm = node; if (bootverbose) device_printf(sc->fc.dev, "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); return(bm); } static u_int32_t fwphy_rddata(struct fwohci_softc *sc, u_int addr) { u_int32_t fun, stat; u_int i, retry = 0; addr &= 0xf; #define MAX_RETRY 100 again: OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); OWRITE(sc, OHCI_PHYACCESS, fun); for ( i = 0 ; i < MAX_RETRY ; i ++ ){ fun = OREAD(sc, OHCI_PHYACCESS); if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) break; DELAY(100); } if(i >= MAX_RETRY) { if (bootverbose) device_printf(sc->fc.dev, "phy read failed(1).\n"); if (++retry < MAX_RETRY) { DELAY(100); goto again; } } /* Make sure that SCLK is started */ stat = OREAD(sc, FWOHCI_INTSTAT); if ((stat & OHCI_INT_REG_FAIL) != 0 || ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { if (bootverbose) device_printf(sc->fc.dev, "phy read failed(2).\n"); if (++retry < MAX_RETRY) { DELAY(100); goto again; } } if (bootverbose || retry >= MAX_RETRY) device_printf(sc->fc.dev, "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry); #undef MAX_RETRY return((fun >> PHYDEV_RDDATA )& 0xff); } /* Device specific ioctl. */ int fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) { struct firewire_softc *sc; struct fwohci_softc *fc; int unit = DEV2UNIT(dev); int err = 0; struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; u_int32_t *dmach = (u_int32_t *) data; sc = devclass_get_softc(firewire_devclass, unit); if(sc == NULL){ return(EINVAL); } fc = (struct fwohci_softc *)sc->fc; if (!data) return(EINVAL); switch (cmd) { case FWOHCI_WRREG: #define OHCI_MAX_REG 0x800 if(reg->addr <= OHCI_MAX_REG){ OWRITE(fc, reg->addr, reg->data); reg->data = OREAD(fc, reg->addr); }else{ err = EINVAL; } break; case FWOHCI_RDREG: if(reg->addr <= OHCI_MAX_REG){ reg->data = OREAD(fc, reg->addr); }else{ err = EINVAL; } break; /* Read DMA descriptors for debug */ case DUMPDMA: if(*dmach <= OHCI_MAX_DMA_CH ){ dump_dma(fc, *dmach); dump_db(fc, *dmach); }else{ err = EINVAL; } break; /* Read/Write Phy registers */ #define OHCI_MAX_PHY_REG 0xf case FWOHCI_RDPHYREG: if (reg->addr <= OHCI_MAX_PHY_REG) reg->data = fwphy_rddata(fc, reg->addr); else err = EINVAL; break; case FWOHCI_WRPHYREG: if (reg->addr <= OHCI_MAX_PHY_REG) reg->data = fwphy_wrdata(fc, reg->addr, reg->data); else err = EINVAL; break; default: err = EINVAL; break; } return err; } static int fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) { u_int32_t reg, reg2; int e1394a = 1; /* * probe PHY parameters * 0. to prove PHY version, whether compliance of 1394a. * 1. to probe maximum speed supported by the PHY and * number of port supported by core-logic. * It is not actually available port on your PC . */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); reg = fwphy_rddata(sc, FW_PHY_SPD_REG); if((reg >> 5) != 7 ){ sc->fc.mode &= ~FWPHYASYST; sc->fc.nport = reg & FW_PHY_NP; sc->fc.speed = reg & FW_PHY_SPD >> 6; if (sc->fc.speed > MAX_SPEED) { device_printf(dev, "invalid speed %d (fixed to %d).\n", sc->fc.speed, MAX_SPEED); sc->fc.speed = MAX_SPEED; } device_printf(dev, "Phy 1394 only %s, %d ports.\n", linkspeed[sc->fc.speed], sc->fc.nport); }else{ reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); sc->fc.mode |= FWPHYASYST; sc->fc.nport = reg & FW_PHY_NP; sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; if (sc->fc.speed > MAX_SPEED) { device_printf(dev, "invalid speed %d (fixed to %d).\n", sc->fc.speed, MAX_SPEED); sc->fc.speed = MAX_SPEED; } device_printf(dev, "Phy 1394a available %s, %d ports.\n", linkspeed[sc->fc.speed], sc->fc.nport); /* check programPhyEnable */ reg2 = fwphy_rddata(sc, 5); #if 0 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { #else /* XXX force to enable 1394a */ if (e1394a) { #endif if (bootverbose) device_printf(dev, "Enable 1394a Enhancements\n"); /* enable EAA EMC */ reg2 |= 0x03; /* set aPhyEnhanceEnable */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); } else { /* for safe */ reg2 &= ~0x83; } reg2 = fwphy_wrdata(sc, 5, reg2); } reg = fwphy_rddata(sc, FW_PHY_SPD_REG); if((reg >> 5) == 7 ){ reg = fwphy_rddata(sc, 4); reg |= 1 << 6; fwphy_wrdata(sc, 4, reg); reg = fwphy_rddata(sc, 4); } return 0; } void fwohci_reset(struct fwohci_softc *sc, device_t dev) { int i, max_rec, speed; u_int32_t reg, reg2; struct fwohcidb_tr *db_tr; - /* Disable interrupt */ + /* Disable interrupts */ OWRITE(sc, FWOHCI_INTMASKCLR, ~0); - /* Now stopping all DMA channel */ + /* Now stopping all DMA channels */ OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_IR_MASKCLR, ~0); for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); } /* FLUSH FIFO and reset Transmitter/Reciever */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); if (bootverbose) device_printf(dev, "resetting OHCI..."); i = 0; while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { if (i++ > 100) break; DELAY(1000); } if (bootverbose) printf("done (loop=%d)\n", i); /* Probe phy */ fwohci_probe_phy(sc, dev); /* Probe link */ reg = OREAD(sc, OHCI_BUS_OPT); reg2 = reg | OHCI_BUSFNC; max_rec = (reg & 0x0000f000) >> 12; speed = (reg & 0x00000007); device_printf(dev, "Link %s, max_rec %d bytes.\n", linkspeed[speed], MAXREC(max_rec)); /* XXX fix max_rec */ sc->fc.maxrec = sc->fc.speed + 8; if (max_rec != sc->fc.maxrec) { reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12); device_printf(dev, "max_rec %d -> %d\n", MAXREC(max_rec), MAXREC(sc->fc.maxrec)); } if (bootverbose) device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); OWRITE(sc, OHCI_BUS_OPT, reg2); /* Initialize registers */ OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr); OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr); OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); /* Enable link */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); /* Force to start async RX DMA */ sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; fwohci_rx_enable(sc, &sc->arrq); fwohci_rx_enable(sc, &sc->arrs); /* Initialize async TX */ OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); /* AT Retries */ OWRITE(sc, FWOHCI_RETRY, /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */ (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ; sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq); sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq); sc->atrq.bottom = sc->atrq.top; sc->atrs.bottom = sc->atrs.top; for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; i ++, db_tr = STAILQ_NEXT(db_tr, link)){ db_tr->xfer = NULL; } for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; i ++, db_tr = STAILQ_NEXT(db_tr, link)){ db_tr->xfer = NULL; } - /* Enable interrupt */ + /* Enable interrupts */ OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_ERR | OHCI_INT_PHY_SID | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); fwohci_set_intr(&sc->fc, 1); } int fwohci_init(struct fwohci_softc *sc, device_t dev) { int i, mver; u_int32_t reg; u_int8_t ui[8]; #if FWOHCI_TASKQUEUE TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc); #endif /* OHCI version */ reg = OREAD(sc, OHCI_VERSION); mver = (reg >> 16) & 0xff; device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", mver, reg & 0xff, (reg>>24) & 1); if (mver < 1 || mver > 9) { device_printf(dev, "invalid OHCI version\n"); return (ENXIO); } -/* Available Isochrounous DMA channel probe */ +/* Available Isochronous DMA channel probe */ OWRITE(sc, OHCI_IT_MASK, 0xffffffff); OWRITE(sc, OHCI_IR_MASK, 0xffffffff); reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK); OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff); OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff); for (i = 0; i < 0x20; i++) if ((reg & (1 << i)) == 0) break; sc->fc.nisodma = i; - device_printf(dev, "No. of Isochronous channel is %d.\n", i); + device_printf(dev, "No. of Isochronous channels is %d.\n", i); if (i == 0) return (ENXIO); sc->fc.arq = &sc->arrq.xferq; sc->fc.ars = &sc->arrs.xferq; sc->fc.atq = &sc->atrq.xferq; sc->fc.ats = &sc->atrs.xferq; sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE); sc->arrq.xferq.start = NULL; sc->arrs.xferq.start = NULL; sc->atrq.xferq.start = fwohci_start_atq; sc->atrs.xferq.start = fwohci_start_ats; sc->arrq.xferq.buf = NULL; sc->arrs.xferq.buf = NULL; sc->atrq.xferq.buf = NULL; sc->atrs.xferq.buf = NULL; sc->arrq.xferq.dmach = -1; sc->arrs.xferq.dmach = -1; sc->atrq.xferq.dmach = -1; sc->atrs.xferq.dmach = -1; sc->arrq.ndesc = 1; sc->arrs.ndesc = 1; sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */ sc->atrs.ndesc = 2; sc->arrq.ndb = NDB; sc->arrs.ndb = NDB / 2; sc->atrq.ndb = NDB; sc->atrs.ndb = NDB / 2; for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ sc->fc.it[i] = &sc->it[i].xferq; sc->fc.ir[i] = &sc->ir[i].xferq; sc->it[i].xferq.dmach = i; sc->ir[i].xferq.dmach = i; sc->it[i].ndb = 0; sc->ir[i].ndb = 0; } sc->fc.tcode = tinfo; sc->fc.dev = dev; sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE, &sc->crom_dma, BUS_DMA_WAITOK); if(sc->fc.config_rom == NULL){ device_printf(dev, "config_rom alloc failed."); return ENOMEM; } #if 0 bzero(&sc->fc.config_rom[0], CROMSIZE); sc->fc.config_rom[1] = 0x31333934; sc->fc.config_rom[2] = 0xf000a002; sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); sc->fc.config_rom[5] = 0; sc->fc.config_rom[0] = (4 << 24) | (5 << 16); sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); #endif -/* SID recieve buffer must allign 2^11 */ +/* SID recieve buffer must align 2^11 */ #define OHCI_SIDSIZE (1 << 11) sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE, &sc->sid_dma, BUS_DMA_WAITOK); if (sc->sid_buf == NULL) { device_printf(dev, "sid_buf alloc failed."); return ENOMEM; } fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t), &sc->dummy_dma, BUS_DMA_WAITOK); if (sc->dummy_dma.v_addr == NULL) { device_printf(dev, "dummy_dma alloc failed."); return ENOMEM; } fwohci_db_init(sc, &sc->arrq); if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) return ENOMEM; fwohci_db_init(sc, &sc->arrs); if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) return ENOMEM; fwohci_db_init(sc, &sc->atrq); if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) return ENOMEM; fwohci_db_init(sc, &sc->atrs); if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) return ENOMEM; sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H); sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L); for( i = 0 ; i < 8 ; i ++) ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i); device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]); sc->fc.ioctl = fwohci_ioctl; sc->fc.cyctimer = fwohci_cyctimer; sc->fc.set_bmr = fwohci_set_bus_manager; sc->fc.ibr = fwohci_ibr; sc->fc.irx_enable = fwohci_irx_enable; sc->fc.irx_disable = fwohci_irx_disable; sc->fc.itx_enable = fwohci_itxbuf_enable; sc->fc.itx_disable = fwohci_itx_disable; #if BYTE_ORDER == BIG_ENDIAN sc->fc.irx_post = fwohci_irx_post; #else sc->fc.irx_post = NULL; #endif sc->fc.itx_post = NULL; sc->fc.timeout = fwohci_timeout; sc->fc.poll = fwohci_poll; sc->fc.set_intr = fwohci_set_intr; sc->intmask = sc->irstat = sc->itstat = 0; fw_init(&sc->fc); fwohci_reset(sc, dev); return 0; } void fwohci_timeout(void *arg) { struct fwohci_softc *sc; sc = (struct fwohci_softc *)arg; } u_int32_t fwohci_cyctimer(struct firewire_comm *fc) { struct fwohci_softc *sc = (struct fwohci_softc *)fc; return(OREAD(sc, OHCI_CYCLETIMER)); } int fwohci_detach(struct fwohci_softc *sc, device_t dev) { int i; if (sc->sid_buf != NULL) fwdma_free(&sc->fc, &sc->sid_dma); if (sc->fc.config_rom != NULL) fwdma_free(&sc->fc, &sc->crom_dma); fwohci_db_free(&sc->arrq); fwohci_db_free(&sc->arrs); fwohci_db_free(&sc->atrq); fwohci_db_free(&sc->atrs); for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ fwohci_db_free(&sc->it[i]); fwohci_db_free(&sc->ir[i]); } return 0; } #define LAST_DB(dbtr, db) do { \ struct fwohcidb_tr *_dbtr = (dbtr); \ int _cnt = _dbtr->dbcnt; \ db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ } while (0) static void fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error) { struct fwohcidb_tr *db_tr; struct fwohcidb *db; bus_dma_segment_t *s; int i; db_tr = (struct fwohcidb_tr *)arg; db = &db_tr->db[db_tr->dbcnt]; if (error) { if (firewire_debug || error != EFBIG) printf("fwohci_execute_db: error=%d\n", error); return; } for (i = 0; i < nseg; i++) { s = &segs[i]; FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr); FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len); FWOHCI_DMA_WRITE(db->db.desc.res, 0); db++; db_tr->dbcnt++; } } static void fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg, bus_size_t size, int error) { fwohci_execute_db(arg, segs, nseg, error); } static void fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) { int i, s; int tcode, hdr_len, pl_off; int fsegment = -1; u_int32_t off; struct fw_xfer *xfer; struct fw_pkt *fp; struct fwohci_txpkthdr *ohcifp; struct fwohcidb_tr *db_tr; struct fwohcidb *db; u_int32_t *ld; struct tcode_info *info; static int maxdesc=0; if(&sc->atrq == dbch){ off = OHCI_ATQOFF; }else if(&sc->atrs == dbch){ off = OHCI_ATSOFF; }else{ return; } if (dbch->flags & FWOHCI_DBCH_FULL) return; s = splfw(); db_tr = dbch->top; txloop: xfer = STAILQ_FIRST(&dbch->xferq.q); if(xfer == NULL){ goto kick; } if(dbch->xferq.queued == 0 ){ device_printf(sc->fc.dev, "TX queue empty\n"); } STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); db_tr->xfer = xfer; xfer->state = FWXF_START; fp = &xfer->send.hdr; tcode = fp->mode.common.tcode; ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed; info = &tinfo[tcode]; hdr_len = pl_off = info->hdr_len; ld = &ohcifp->mode.ld[0]; ld[0] = ld[1] = ld[2] = ld[3] = 0; for( i = 0 ; i < pl_off ; i+= 4) ld[i/4] = fp->mode.ld[i/4]; ohcifp->mode.common.spd = xfer->send.spd & 0x7; if (tcode == FWTCODE_STREAM ){ hdr_len = 8; ohcifp->mode.stream.len = fp->mode.stream.len; } else if (tcode == FWTCODE_PHY) { hdr_len = 12; ld[1] = fp->mode.ld[1]; ld[2] = fp->mode.ld[2]; ohcifp->mode.common.spd = 0; ohcifp->mode.common.tcode = FWOHCITCODE_PHY; } else { ohcifp->mode.asycomm.dst = fp->mode.hdr.dst; ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; ohcifp->mode.asycomm.tlrt |= FWRETRY_X; } db = &db_tr->db[0]; FWOHCI_DMA_WRITE(db->db.desc.cmd, OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len); FWOHCI_DMA_WRITE(db->db.desc.addr, 0); FWOHCI_DMA_WRITE(db->db.desc.res, 0); /* Specify bound timer of asy. responce */ if(&sc->atrs == dbch){ FWOHCI_DMA_WRITE(db->db.desc.res, (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13)); } #if BYTE_ORDER == BIG_ENDIAN if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ) hdr_len = 12; for (i = 0; i < hdr_len/4; i ++) FWOHCI_DMA_WRITE(ld[i], ld[i]); #endif again: db_tr->dbcnt = 2; db = &db_tr->db[db_tr->dbcnt]; if (xfer->send.pay_len > 0) { int err; /* handle payload */ if (xfer->mbuf == NULL) { err = bus_dmamap_load(dbch->dmat, db_tr->dma_map, &xfer->send.payload[0], xfer->send.pay_len, fwohci_execute_db, db_tr, /*flags*/0); } else { /* XXX we can handle only 6 (=8-2) mbuf chains */ err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, xfer->mbuf, fwohci_execute_db2, db_tr, /* flags */0); if (err == EFBIG) { struct mbuf *m0; if (firewire_debug) device_printf(sc->fc.dev, "EFBIG.\n"); m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); if (m0 != NULL) { m_copydata(xfer->mbuf, 0, xfer->mbuf->m_pkthdr.len, mtod(m0, caddr_t)); m0->m_len = m0->m_pkthdr.len = xfer->mbuf->m_pkthdr.len; m_freem(xfer->mbuf); xfer->mbuf = m0; goto again; } device_printf(sc->fc.dev, "m_getcl failed.\n"); } } if (err) printf("dmamap_load: err=%d\n", err); bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREWRITE); #if 0 /* OHCI_OUTPUT_MODE == 0 */ for (i = 2; i < db_tr->dbcnt; i++) FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd, OHCI_OUTPUT_MORE); #endif } if (maxdesc < db_tr->dbcnt) { maxdesc = db_tr->dbcnt; if (bootverbose) device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc); } /* last db */ LAST_DB(db_tr, db); FWOHCI_DMA_SET(db->db.desc.cmd, OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); FWOHCI_DMA_WRITE(db->db.desc.depend, STAILQ_NEXT(db_tr, link)->bus_addr); if(fsegment == -1 ) fsegment = db_tr->dbcnt; if (dbch->pdb_tr != NULL) { LAST_DB(dbch->pdb_tr, db); FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt); } dbch->pdb_tr = db_tr; db_tr = STAILQ_NEXT(db_tr, link); if(db_tr != dbch->bottom){ goto txloop; } else { device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); dbch->flags |= FWOHCI_DBCH_FULL; } kick: /* kick asy q */ fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); if(dbch->xferq.flag & FWXFERQ_RUNNING) { OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); } else { if (bootverbose) device_printf(sc->fc.dev, "start AT DMA status=%x\n", OREAD(sc, OHCI_DMACTL(off))); OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment); OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); dbch->xferq.flag |= FWXFERQ_RUNNING; } dbch->top = db_tr; splx(s); return; } static void fwohci_start_atq(struct firewire_comm *fc) { struct fwohci_softc *sc = (struct fwohci_softc *)fc; fwohci_start( sc, &(sc->atrq)); return; } static void fwohci_start_ats(struct firewire_comm *fc) { struct fwohci_softc *sc = (struct fwohci_softc *)fc; fwohci_start( sc, &(sc->atrs)); return; } void fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) { int s, ch, err = 0; struct fwohcidb_tr *tr; struct fwohcidb *db; struct fw_xfer *xfer; u_int32_t off; u_int stat, status; int packets; struct firewire_comm *fc = (struct firewire_comm *)sc; if(&sc->atrq == dbch){ off = OHCI_ATQOFF; ch = ATRQ_CH; }else if(&sc->atrs == dbch){ off = OHCI_ATSOFF; ch = ATRS_CH; }else{ return; } s = splfw(); tr = dbch->bottom; packets = 0; fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); while(dbch->xferq.queued > 0){ LAST_DB(tr, db); status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT; if(!(status & OHCI_CNTL_DMA_ACTIVE)){ if (fc->status != FWBUSRESET) /* maybe out of order?? */ goto out; } bus_dmamap_sync(dbch->dmat, tr->dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(dbch->dmat, tr->dma_map); #if 1 if (firewire_debug) dump_db(sc, ch); #endif if(status & OHCI_CNTL_DMA_DEAD) { /* Stop DMA */ OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); device_printf(sc->fc.dev, "force reset AT FIFO\n"); OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); } stat = status & FWOHCIEV_MASK; switch(stat){ case FWOHCIEV_ACKPEND: case FWOHCIEV_ACKCOMPL: err = 0; break; case FWOHCIEV_ACKBSA: case FWOHCIEV_ACKBSB: case FWOHCIEV_ACKBSX: device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); err = EBUSY; break; case FWOHCIEV_FLUSHED: case FWOHCIEV_ACKTARD: device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); err = EAGAIN; break; case FWOHCIEV_MISSACK: case FWOHCIEV_UNDRRUN: case FWOHCIEV_OVRRUN: case FWOHCIEV_DESCERR: case FWOHCIEV_DTRDERR: case FWOHCIEV_TIMEOUT: case FWOHCIEV_TCODERR: case FWOHCIEV_UNKNOWN: case FWOHCIEV_ACKDERR: case FWOHCIEV_ACKTERR: default: device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); err = EINVAL; break; } if (tr->xfer != NULL) { xfer = tr->xfer; if (xfer->state == FWXF_RCVD) { #if 0 if (firewire_debug) printf("already rcvd\n"); #endif fw_xfer_done(xfer); } else { xfer->state = FWXF_SENT; if (err == EBUSY && fc->status != FWBUSRESET) { xfer->state = FWXF_BUSY; xfer->resp = err; if (xfer->retry_req != NULL) xfer->retry_req(xfer); else { xfer->recv.pay_len = 0; fw_xfer_done(xfer); } } else if (stat != FWOHCIEV_ACKPEND) { if (stat != FWOHCIEV_ACKCOMPL) xfer->state = FWXF_SENTERR; xfer->resp = err; xfer->recv.pay_len = 0; fw_xfer_done(xfer); } } /* * The watchdog timer takes care of split * transcation timeout for ACKPEND case. */ } else { printf("this shouldn't happen\n"); } dbch->xferq.queued --; tr->xfer = NULL; packets ++; tr = STAILQ_NEXT(tr, link); dbch->bottom = tr; if (dbch->bottom == dbch->top) { /* we reaches the end of context program */ if (firewire_debug && dbch->xferq.queued > 0) printf("queued > 0\n"); break; } } out: if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { printf("make free slot\n"); dbch->flags &= ~FWOHCI_DBCH_FULL; fwohci_start(sc, dbch); } splx(s); } static void fwohci_db_free(struct fwohci_dbch *dbch) { struct fwohcidb_tr *db_tr; int idb; if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) return; for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb; db_tr = STAILQ_NEXT(db_tr, link), idb++){ if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 && db_tr->buf != NULL) { fwdma_free_size(dbch->dmat, db_tr->dma_map, db_tr->buf, dbch->xferq.psize); db_tr->buf = NULL; } else if (db_tr->dma_map != NULL) bus_dmamap_destroy(dbch->dmat, db_tr->dma_map); } dbch->ndb = 0; db_tr = STAILQ_FIRST(&dbch->db_trq); fwdma_free_multiseg(dbch->am); free(db_tr, M_FW); STAILQ_INIT(&dbch->db_trq); dbch->flags &= ~FWOHCI_DBCH_INIT; } static void fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch) { int idb; struct fwohcidb_tr *db_tr; if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) goto out; /* create dma_tag for buffers */ #define MAX_REQCOUNT 0xffff if (bus_dma_tag_create(/*parent*/ sc->fc.dmat, /*alignment*/ 1, /*boundary*/ 0, /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, /*highaddr*/ BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL, /*maxsize*/ dbch->xferq.psize, /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, /*maxsegsz*/ MAX_REQCOUNT, /*flags*/ 0, #if defined(__FreeBSD__) && __FreeBSD_version >= 501102 /*lockfunc*/busdma_lock_mutex, /*lockarg*/&Giant, #endif &dbch->dmat)) return; /* allocate DB entries and attach one to each DMA channels */ /* DB entry must start at 16 bytes bounary. */ STAILQ_INIT(&dbch->db_trq); db_tr = (struct fwohcidb_tr *) malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, M_FW, M_WAITOK | M_ZERO); if(db_tr == NULL){ printf("fwohci_db_init: malloc(1) failed\n"); return; } #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc) dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch), DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK); if (dbch->am == NULL) { printf("fwohci_db_init: fwdma_malloc_multiseg failed\n"); free(db_tr, M_FW); return; } /* Attach DB to DMA ch. */ for(idb = 0 ; idb < dbch->ndb ; idb++){ db_tr->dbcnt = 0; db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb); db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb); /* create dmamap for buffers */ /* XXX do we need 4bytes alignment tag? */ /* XXX don't alloc dma_map for AR */ if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) { printf("bus_dmamap_create failed\n"); dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */ fwohci_db_free(dbch); return; } STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); if (dbch->xferq.flag & FWXFERQ_EXTBUF) { if (idb % dbch->xferq.bnpacket == 0) dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket ].start = (caddr_t)db_tr; if ((idb + 1) % dbch->xferq.bnpacket == 0) dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket ].end = (caddr_t)db_tr; } db_tr++; } STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next = STAILQ_FIRST(&dbch->db_trq); out: dbch->xferq.queued = 0; dbch->pdb_tr = NULL; dbch->top = STAILQ_FIRST(&dbch->db_trq); dbch->bottom = dbch->top; dbch->flags = FWOHCI_DBCH_INIT; } static int fwohci_itx_disable(struct firewire_comm *fc, int dmach) { struct fwohci_softc *sc = (struct fwohci_softc *)fc; int sleepch; OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S); OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); /* XXX we cannot free buffers until the DMA really stops */ tsleep((void *)&sleepch, FWPRI, "fwitxd", hz); fwohci_db_free(&sc->it[dmach]); sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; return 0; } static int fwohci_irx_disable(struct firewire_comm *fc, int dmach) { struct fwohci_softc *sc = (struct fwohci_softc *)fc; int sleepch; OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); /* XXX we cannot free buffers until the DMA really stops */ tsleep((void *)&sleepch, FWPRI, "fwirxd", hz); fwohci_db_free(&sc->ir[dmach]); sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; return 0; } #if BYTE_ORDER == BIG_ENDIAN static void fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) { qld[0] = FWOHCI_DMA_READ(qld[0]); return; } #endif static int fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) { int err = 0; int idb, z, i, dmach = 0, ldesc; u_int32_t off = 0; struct fwohcidb_tr *db_tr; struct fwohcidb *db; if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ err = EINVAL; return err; } z = dbch->ndesc; for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ if( &sc->it[dmach] == dbch){ off = OHCI_ITOFF(dmach); break; } } if(off == 0){ err = EINVAL; return err; } if(dbch->xferq.flag & FWXFERQ_RUNNING) return err; dbch->xferq.flag |= FWXFERQ_RUNNING; for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ dbch->bottom = STAILQ_NEXT(dbch->bottom, link); } db_tr = dbch->top; for (idb = 0; idb < dbch->ndb; idb ++) { fwohci_add_tx_buf(dbch, db_tr, idb); if(STAILQ_NEXT(db_tr, link) == NULL){ break; } db = db_tr->db; ldesc = db_tr->dbcnt - 1; FWOHCI_DMA_WRITE(db[0].db.desc.depend, STAILQ_NEXT(db_tr, link)->bus_addr | z); db[ldesc].db.desc.depend = db[0].db.desc.depend; if(dbch->xferq.flag & FWXFERQ_EXTBUF){ if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ FWOHCI_DMA_SET( db[ldesc].db.desc.cmd, OHCI_INTERRUPT_ALWAYS); /* OHCI 1.1 and above */ FWOHCI_DMA_SET( db[0].db.desc.cmd, OHCI_INTERRUPT_ALWAYS); } } db_tr = STAILQ_NEXT(db_tr, link); } FWOHCI_DMA_CLEAR( dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf); return err; } static int fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) { int err = 0; int idb, z, i, dmach = 0, ldesc; u_int32_t off = 0; struct fwohcidb_tr *db_tr; struct fwohcidb *db; z = dbch->ndesc; if(&sc->arrq == dbch){ off = OHCI_ARQOFF; }else if(&sc->arrs == dbch){ off = OHCI_ARSOFF; }else{ for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ if( &sc->ir[dmach] == dbch){ off = OHCI_IROFF(dmach); break; } } } if(off == 0){ err = EINVAL; return err; } if(dbch->xferq.flag & FWXFERQ_STREAM){ if(dbch->xferq.flag & FWXFERQ_RUNNING) return err; }else{ if(dbch->xferq.flag & FWXFERQ_RUNNING){ err = EBUSY; return err; } } dbch->xferq.flag |= FWXFERQ_RUNNING; dbch->top = STAILQ_FIRST(&dbch->db_trq); for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ dbch->bottom = STAILQ_NEXT(dbch->bottom, link); } db_tr = dbch->top; for (idb = 0; idb < dbch->ndb; idb ++) { fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma); if (STAILQ_NEXT(db_tr, link) == NULL) break; db = db_tr->db; ldesc = db_tr->dbcnt - 1; FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend, STAILQ_NEXT(db_tr, link)->bus_addr | z); if(dbch->xferq.flag & FWXFERQ_EXTBUF){ if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ FWOHCI_DMA_SET( db[ldesc].db.desc.cmd, OHCI_INTERRUPT_ALWAYS); FWOHCI_DMA_CLEAR( db[ldesc].db.desc.depend, 0xf); } } db_tr = STAILQ_NEXT(db_tr, link); } FWOHCI_DMA_CLEAR( dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf); dbch->buf_offset = 0; fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); if(dbch->xferq.flag & FWXFERQ_STREAM){ return err; }else{ OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z); } OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); return err; } static int fwohci_next_cycle(struct firewire_comm *fc, int cycle_now) { int sec, cycle, cycle_match; cycle = cycle_now & 0x1fff; sec = cycle_now >> 13; #define CYCLE_MOD 0x10 #if 1 #define CYCLE_DELAY 8 /* min delay to start DMA */ #else #define CYCLE_DELAY 7000 /* min delay to start DMA */ #endif cycle = cycle + CYCLE_DELAY; if (cycle >= 8000) { sec ++; cycle -= 8000; } cycle = roundup2(cycle, CYCLE_MOD); if (cycle >= 8000) { sec ++; if (cycle == 8000) cycle = 0; else cycle = CYCLE_MOD; } cycle_match = ((sec << 13) | cycle) & 0x7ffff; return(cycle_match); } static int fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) { struct fwohci_softc *sc = (struct fwohci_softc *)fc; int err = 0; unsigned short tag, ich; struct fwohci_dbch *dbch; int cycle_match, cycle_now, s, ldesc; u_int32_t stat; struct fw_bulkxfer *first, *chunk, *prev; struct fw_xferq *it; dbch = &sc->it[dmach]; it = &dbch->xferq; tag = (it->flag >> 6) & 3; ich = it->flag & 0x3f; if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) { dbch->ndb = it->bnpacket * it->bnchunk; dbch->ndesc = 3; fwohci_db_init(sc, dbch); if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) return ENOMEM; err = fwohci_tx_enable(sc, dbch); } if(err) return err; ldesc = dbch->ndesc - 1; s = splfw(); prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link); while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) { struct fwohcidb *db; fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket, BUS_DMASYNC_PREWRITE); fwohci_txbufdb(sc, dmach, chunk); if (prev != NULL) { db = ((struct fwohcidb_tr *)(prev->end))->db; #if 0 /* XXX necessary? */ FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); #endif #if 0 /* if bulkxfer->npacket changes */ db[ldesc].db.desc.depend = db[0].db.desc.depend = ((struct fwohcidb_tr *) (chunk->start))->bus_addr | dbch->ndesc; #else FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); #endif } STAILQ_REMOVE_HEAD(&it->stvalid, link); STAILQ_INSERT_TAIL(&it->stdma, chunk, link); prev = chunk; } fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); splx(s); stat = OREAD(sc, OHCI_ITCTL(dmach)); if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S)) printf("stat 0x%x\n", stat); if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S)) return 0; #if 0 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); #endif OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); OWRITE(sc, OHCI_IT_MASK, 1 << dmach); OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); first = STAILQ_FIRST(&it->stdma); OWRITE(sc, OHCI_ITCMD(dmach), ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); if (firewire_debug) { printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat); #if 1 dump_dma(sc, ITX_CH + dmach); #endif } if ((stat & OHCI_CNTL_DMA_RUN) == 0) { #if 1 /* Don't start until all chunks are buffered */ if (STAILQ_FIRST(&it->stfree) != NULL) goto out; #endif #if 1 /* Clear cycle match counter bits */ OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000); /* 2bit second + 13bit cycle */ cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff; cycle_match = fwohci_next_cycle(fc, cycle_now); OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_CYCMATCH_S | (cycle_match << 16) | OHCI_CNTL_DMA_RUN); #else OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); #endif if (firewire_debug) { printf("cycle_match: 0x%04x->0x%04x\n", cycle_now, cycle_match); dump_dma(sc, ITX_CH + dmach); dump_db(sc, ITX_CH + dmach); } } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) { device_printf(sc->fc.dev, "IT DMA underrun (0x%08x)\n", stat); OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE); } out: return err; } static int fwohci_irx_enable(struct firewire_comm *fc, int dmach) { struct fwohci_softc *sc = (struct fwohci_softc *)fc; int err = 0, s, ldesc; unsigned short tag, ich; u_int32_t stat; struct fwohci_dbch *dbch; struct fwohcidb_tr *db_tr; struct fw_bulkxfer *first, *prev, *chunk; struct fw_xferq *ir; dbch = &sc->ir[dmach]; ir = &dbch->xferq; if ((ir->flag & FWXFERQ_RUNNING) == 0) { tag = (ir->flag >> 6) & 3; ich = ir->flag & 0x3f; OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); ir->queued = 0; dbch->ndb = ir->bnpacket * ir->bnchunk; dbch->ndesc = 2; fwohci_db_init(sc, dbch); if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) return ENOMEM; err = fwohci_rx_enable(sc, dbch); } if(err) return err; first = STAILQ_FIRST(&ir->stfree); if (first == NULL) { device_printf(fc->dev, "IR DMA no free chunk\n"); return 0; } ldesc = dbch->ndesc - 1; s = splfw(); prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link); while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) { struct fwohcidb *db; #if 1 /* XXX for if_fwe */ if (chunk->mbuf != NULL) { db_tr = (struct fwohcidb_tr *)(chunk->start); db_tr->dbcnt = 1; err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map, chunk->mbuf, fwohci_execute_db2, db_tr, /* flags */0); FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd, OHCI_UPDATE | OHCI_INPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS); } #endif db = ((struct fwohcidb_tr *)(chunk->end))->db; FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0); FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf); if (prev != NULL) { db = ((struct fwohcidb_tr *)(prev->end))->db; FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc); } STAILQ_REMOVE_HEAD(&ir->stfree, link); STAILQ_INSERT_TAIL(&ir->stdma, chunk, link); prev = chunk; } fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD); splx(s); stat = OREAD(sc, OHCI_IRCTL(dmach)); if (stat & OHCI_CNTL_DMA_ACTIVE) return 0; if (stat & OHCI_CNTL_DMA_RUN) { OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat); } if (firewire_debug) printf("start IR DMA 0x%x\n", stat); OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); OWRITE(sc, OHCI_IR_MASK, 1 << dmach); OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); OWRITE(sc, OHCI_IRCMD(dmach), ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc); OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); #if 0 dump_db(sc, IRX_CH + dmach); #endif return err; } int fwohci_stop(struct fwohci_softc *sc, device_t dev) { u_int i; /* Now stopping all DMA channel */ OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); } /* FLUSH FIFO and reset Transmitter/Reciever */ OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); /* Stop interrupt */ OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID | OHCI_INT_PHY_INT | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS | OHCI_INT_PHY_BUS_R); if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0) fw_drain_txq(&sc->fc); /* XXX Link down? Bus reset? */ return 0; } int fwohci_resume(struct fwohci_softc *sc, device_t dev) { int i; struct fw_xferq *ir; struct fw_bulkxfer *chunk; fwohci_reset(sc, dev); - /* XXX resume isochronus receive automatically. (how about TX?) */ + /* XXX resume isochronous receive automatically. (how about TX?) */ for(i = 0; i < sc->fc.nisodma; i ++) { ir = &sc->ir[i].xferq; if((ir->flag & FWXFERQ_RUNNING) != 0) { device_printf(sc->fc.dev, "resume iso receive ch: %d\n", i); ir->flag &= ~FWXFERQ_RUNNING; /* requeue stdma to stfree */ while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { STAILQ_REMOVE_HEAD(&ir->stdma, link); STAILQ_INSERT_TAIL(&ir->stfree, chunk, link); } sc->fc.irx_enable(&sc->fc, i); } } bus_generic_resume(dev); sc->fc.ibr(&sc->fc); return 0; } #define ACK_ALL static void fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) { u_int32_t irstat, itstat; u_int i; struct firewire_comm *fc = (struct firewire_comm *)sc; #ifdef OHCI_DEBUG if(stat & OREAD(sc, FWOHCI_INTMASK)) device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", stat & OHCI_INT_EN ? "DMA_EN ":"", stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", stat & OHCI_INT_ERR ? "INT_ERR ":"", stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", stat & OHCI_INT_CYC_START ? "CYC_START ":"", stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", stat & OHCI_INT_PHY_SID ? "SID ":"", stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", stat, OREAD(sc, FWOHCI_INTMASK) ); #endif /* Bus reset */ if(stat & OHCI_INT_PHY_BUS_R ){ if (fc->status == FWBUSRESET) goto busresetout; /* Disable bus reset interrupt until sid recv. */ OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R); device_printf(fc->dev, "BUS reset\n"); OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); #endif fw_busreset(fc); OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0])); OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2])); } busresetout: if((stat & OHCI_INT_DMA_IR )){ #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); #endif #if defined(__DragonFly__) || __FreeBSD_version < 500000 irstat = sc->irstat; sc->irstat = 0; #else irstat = atomic_readandclear_int(&sc->irstat); #endif for(i = 0; i < fc->nisodma ; i++){ struct fwohci_dbch *dbch; if((irstat & (1 << i)) != 0){ dbch = &sc->ir[i]; if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) { device_printf(sc->fc.dev, "dma(%d) not active\n", i); continue; } fwohci_rbuf_update(sc, i); } } } if((stat & OHCI_INT_DMA_IT )){ #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); #endif #if defined(__DragonFly__) || __FreeBSD_version < 500000 itstat = sc->itstat; sc->itstat = 0; #else itstat = atomic_readandclear_int(&sc->itstat); #endif for(i = 0; i < fc->nisodma ; i++){ if((itstat & (1 << i)) != 0){ fwohci_tbuf_update(sc, i); } } } if((stat & OHCI_INT_DMA_PRRS )){ #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); #endif #if 0 dump_dma(sc, ARRS_CH); dump_db(sc, ARRS_CH); #endif fwohci_arcv(sc, &sc->arrs, count); } if((stat & OHCI_INT_DMA_PRRQ )){ #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); #endif #if 0 dump_dma(sc, ARRQ_CH); dump_db(sc, ARRQ_CH); #endif fwohci_arcv(sc, &sc->arrq, count); } if(stat & OHCI_INT_PHY_SID){ u_int32_t *buf, node_id; int plen; #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); #endif /* Enable bus reset interrupt */ OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); /* Allow async. request to us */ OWRITE(sc, OHCI_AREQHI, 1 << 31); /* XXX insecure ?? */ OWRITE(sc, OHCI_PREQHI, 0x7fffffff); OWRITE(sc, OHCI_PREQLO, 0xffffffff); OWRITE(sc, OHCI_PREQUPPER, 0x10000); /* Set ATRetries register */ OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff); /* ** Checking whether the node is root or not. If root, turn on ** cycle master. */ node_id = OREAD(sc, FWOHCI_NODEID); plen = OREAD(sc, OHCI_SID_CNT); device_printf(fc->dev, "node_id=0x%08x, gen=%d, ", node_id, (plen >> 16) & 0xff); if (!(node_id & OHCI_NODE_VALID)) { printf("Bus reset failure\n"); goto sidout; } if (node_id & OHCI_NODE_ROOT) { printf("CYCLEMASTER mode\n"); OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); } else { printf("non CYCLEMASTER mode\n"); OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); } fc->nodeid = node_id & 0x3f; if (plen & OHCI_SID_ERR) { device_printf(fc->dev, "SID Error\n"); goto sidout; } plen &= OHCI_SID_CNT_MASK; if (plen < 4 || plen > OHCI_SIDSIZE) { device_printf(fc->dev, "invalid SID len = %d\n", plen); goto sidout; } plen -= 4; /* chop control info */ buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT); if (buf == NULL) { device_printf(fc->dev, "malloc failed\n"); goto sidout; } for (i = 0; i < plen / 4; i ++) buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]); #if 1 /* XXX needed?? */ /* pending all pre-bus_reset packets */ fwohci_txd(sc, &sc->atrq); fwohci_txd(sc, &sc->atrs); fwohci_arcv(sc, &sc->arrs, -1); fwohci_arcv(sc, &sc->arrq, -1); fw_drain_txq(fc); #endif fw_sidrcv(fc, buf, plen); free(buf, M_FW); } sidout: if((stat & OHCI_INT_DMA_ATRQ )){ #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); #endif fwohci_txd(sc, &(sc->atrq)); } if((stat & OHCI_INT_DMA_ATRS )){ #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); #endif fwohci_txd(sc, &(sc->atrs)); } if((stat & OHCI_INT_PW_ERR )){ #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); #endif device_printf(fc->dev, "posted write error\n"); } if((stat & OHCI_INT_ERR )){ #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); #endif device_printf(fc->dev, "unrecoverable error\n"); } if((stat & OHCI_INT_PHY_INT)) { #ifndef ACK_ALL OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); #endif device_printf(fc->dev, "phy int\n"); } return; } #if FWOHCI_TASKQUEUE static void fwohci_complete(void *arg, int pending) { struct fwohci_softc *sc = (struct fwohci_softc *)arg; u_int32_t stat; again: stat = atomic_readandclear_int(&sc->intstat); if (stat) fwohci_intr_body(sc, stat, -1); else return; goto again; } #endif static u_int32_t fwochi_check_stat(struct fwohci_softc *sc) { u_int32_t stat, irstat, itstat; stat = OREAD(sc, FWOHCI_INTSTAT); if (stat == 0xffffffff) { device_printf(sc->fc.dev, "device physically ejected?\n"); return(stat); } #ifdef ACK_ALL if (stat) OWRITE(sc, FWOHCI_INTSTATCLR, stat); #endif if (stat & OHCI_INT_DMA_IR) { irstat = OREAD(sc, OHCI_IR_STAT); OWRITE(sc, OHCI_IR_STATCLR, irstat); atomic_set_int(&sc->irstat, irstat); } if (stat & OHCI_INT_DMA_IT) { itstat = OREAD(sc, OHCI_IT_STAT); OWRITE(sc, OHCI_IT_STATCLR, itstat); atomic_set_int(&sc->itstat, itstat); } return(stat); } void fwohci_intr(void *arg) { struct fwohci_softc *sc = (struct fwohci_softc *)arg; u_int32_t stat; #if !FWOHCI_TASKQUEUE u_int32_t bus_reset = 0; #endif if (!(sc->intmask & OHCI_INT_EN)) { /* polling mode */ return; } #if !FWOHCI_TASKQUEUE again: #endif stat = fwochi_check_stat(sc); if (stat == 0 || stat == 0xffffffff) return; #if FWOHCI_TASKQUEUE atomic_set_int(&sc->intstat, stat); /* XXX mask bus reset intr. during bus reset phase */ if (stat) taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete); #else /* We cannot clear bus reset event during bus reset phase */ if ((stat & ~bus_reset) == 0) return; bus_reset = stat & OHCI_INT_PHY_BUS_R; fwohci_intr_body(sc, stat, -1); goto again; #endif } void fwohci_poll(struct firewire_comm *fc, int quick, int count) { int s; u_int32_t stat; struct fwohci_softc *sc; sc = (struct fwohci_softc *)fc; stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; #if 0 if (!quick) { #else if (1) { #endif stat = fwochi_check_stat(sc); if (stat == 0 || stat == 0xffffffff) return; } s = splfw(); fwohci_intr_body(sc, stat, count); splx(s); } static void fwohci_set_intr(struct firewire_comm *fc, int enable) { struct fwohci_softc *sc; sc = (struct fwohci_softc *)fc; if (bootverbose) device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); if (enable) { sc->intmask |= OHCI_INT_EN; OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); } else { sc->intmask &= ~OHCI_INT_EN; OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); } } static void fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) { struct firewire_comm *fc = &sc->fc; struct fwohcidb *db; struct fw_bulkxfer *chunk; struct fw_xferq *it; u_int32_t stat, count; int s, w=0, ldesc; it = fc->it[dmach]; ldesc = sc->it[dmach].ndesc - 1; s = splfw(); /* unnecessary ? */ fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD); if (firewire_debug) dump_db(sc, ITX_CH + dmach); while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) { db = ((struct fwohcidb_tr *)(chunk->end))->db; stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res) >> OHCI_STATUS_SHIFT; db = ((struct fwohcidb_tr *)(chunk->start))->db; /* timestamp */ count = FWOHCI_DMA_READ(db[ldesc].db.desc.res) & OHCI_COUNT_MASK; if (stat == 0) break; STAILQ_REMOVE_HEAD(&it->stdma, link); switch (stat & FWOHCIEV_MASK){ case FWOHCIEV_ACKCOMPL: #if 0 device_printf(fc->dev, "0x%08x\n", count); #endif break; default: device_printf(fc->dev, "Isochronous transmit err %02x(%s)\n", stat, fwohcicode[stat & 0x1f]); } STAILQ_INSERT_TAIL(&it->stfree, chunk, link); w++; } splx(s); if (w) wakeup(it); } static void fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) { struct firewire_comm *fc = &sc->fc; struct fwohcidb_tr *db_tr; struct fw_bulkxfer *chunk; struct fw_xferq *ir; u_int32_t stat; int s, w=0, ldesc; ir = fc->ir[dmach]; ldesc = sc->ir[dmach].ndesc - 1; #if 0 dump_db(sc, dmach); #endif s = splfw(); fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD); while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) { db_tr = (struct fwohcidb_tr *)chunk->end; stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res) >> OHCI_STATUS_SHIFT; if (stat == 0) break; if (chunk->mbuf != NULL) { bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map); } else if (ir->buf != NULL) { fwdma_sync_multiseg(ir->buf, chunk->poffset, ir->bnpacket, BUS_DMASYNC_POSTREAD); } else { /* XXX */ printf("fwohci_rbuf_update: this shouldn't happend\n"); } STAILQ_REMOVE_HEAD(&ir->stdma, link); STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link); switch (stat & FWOHCIEV_MASK) { case FWOHCIEV_ACKCOMPL: chunk->resp = 0; break; default: chunk->resp = EINVAL; device_printf(fc->dev, "Isochronous receive err %02x(%s)\n", stat, fwohcicode[stat & 0x1f]); } w++; } splx(s); if (w) { if (ir->flag & FWXFERQ_HANDLER) ir->hand(ir); else wakeup(ir); } } void dump_dma(struct fwohci_softc *sc, u_int32_t ch) { u_int32_t off, cntl, stat, cmd, match; if(ch == 0){ off = OHCI_ATQOFF; }else if(ch == 1){ off = OHCI_ATSOFF; }else if(ch == 2){ off = OHCI_ARQOFF; }else if(ch == 3){ off = OHCI_ARSOFF; }else if(ch < IRX_CH){ off = OHCI_ITCTL(ch - ITX_CH); }else{ off = OHCI_IRCTL(ch - IRX_CH); } cntl = stat = OREAD(sc, off); cmd = OREAD(sc, off + 0xc); match = OREAD(sc, off + 0x10); device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n", ch, cntl, cmd, match); stat &= 0xffff ; if (stat) { device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", ch, stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", fwohcicode[stat & 0x1f], stat & 0x1f ); }else{ device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); } } void dump_db(struct fwohci_softc *sc, u_int32_t ch) { struct fwohci_dbch *dbch; struct fwohcidb_tr *cp = NULL, *pp, *np = NULL; struct fwohcidb *curr = NULL, *prev, *next = NULL; int idb, jdb; u_int32_t cmd, off; if(ch == 0){ off = OHCI_ATQOFF; dbch = &sc->atrq; }else if(ch == 1){ off = OHCI_ATSOFF; dbch = &sc->atrs; }else if(ch == 2){ off = OHCI_ARQOFF; dbch = &sc->arrq; }else if(ch == 3){ off = OHCI_ARSOFF; dbch = &sc->arrs; }else if(ch < IRX_CH){ off = OHCI_ITCTL(ch - ITX_CH); dbch = &sc->it[ch - ITX_CH]; }else { off = OHCI_IRCTL(ch - IRX_CH); dbch = &sc->ir[ch - IRX_CH]; } cmd = OREAD(sc, off + 0xc); if( dbch->ndb == 0 ){ device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); return; } pp = dbch->top; prev = pp->db; for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ if(pp == NULL){ curr = NULL; goto outdb; } cp = STAILQ_NEXT(pp, link); if(cp == NULL){ curr = NULL; goto outdb; } np = STAILQ_NEXT(cp, link); for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ if ((cmd & 0xfffffff0) == cp->bus_addr) { curr = cp->db; if(np != NULL){ next = np->db; }else{ next = NULL; } goto outdb; } } pp = STAILQ_NEXT(pp, link); prev = pp->db; } outdb: if( curr != NULL){ #if 0 printf("Prev DB %d\n", ch); print_db(pp, prev, ch, dbch->ndesc); #endif printf("Current DB %d\n", ch); print_db(cp, curr, ch, dbch->ndesc); #if 0 printf("Next DB %d\n", ch); print_db(np, next, ch, dbch->ndesc); #endif }else{ printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); } return; } void print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db, u_int32_t ch, u_int32_t max) { fwohcireg_t stat; int i, key; u_int32_t cmd, res; if(db == NULL){ printf("No Descriptor is found\n"); return; } printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", ch, "Current", "OP ", "KEY", "INT", "BR ", "len", "Addr", "Depend", "Stat", "Cnt"); for( i = 0 ; i <= max ; i ++){ cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd); res = FWOHCI_DMA_READ(db[i].db.desc.res); key = cmd & OHCI_KEY_MASK; stat = res >> OHCI_STATUS_SHIFT; #if defined(__DragonFly__) || __FreeBSD_version < 500000 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x", db_tr->bus_addr, #else printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x", (uintmax_t)db_tr->bus_addr, #endif dbcode[(cmd >> 28) & 0xf], dbkey[(cmd >> 24) & 0x7], dbcond[(cmd >> 20) & 0x3], dbcond[(cmd >> 18) & 0x3], cmd & OHCI_COUNT_MASK, FWOHCI_DMA_READ(db[i].db.desc.addr), FWOHCI_DMA_READ(db[i].db.desc.depend), stat, res & OHCI_COUNT_MASK); if(stat & 0xff00){ printf(" %s%s%s%s%s%s %s(%x)\n", stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", fwohcicode[stat & 0x1f], stat & 0x1f ); }else{ printf(" Nostat\n"); } if(key == OHCI_KEY_ST2 ){ printf("0x%08x 0x%08x 0x%08x 0x%08x\n", FWOHCI_DMA_READ(db[i+1].db.immed[0]), FWOHCI_DMA_READ(db[i+1].db.immed[1]), FWOHCI_DMA_READ(db[i+1].db.immed[2]), FWOHCI_DMA_READ(db[i+1].db.immed[3])); } if(key == OHCI_KEY_DEVICE){ return; } if((cmd & OHCI_BRANCH_MASK) == OHCI_BRANCH_ALWAYS){ return; } if((cmd & OHCI_CMD_MASK) == OHCI_OUTPUT_LAST){ return; } if((cmd & OHCI_CMD_MASK) == OHCI_INPUT_LAST){ return; } if(key == OHCI_KEY_ST2 ){ i++; } } return; } void fwohci_ibr(struct firewire_comm *fc) { struct fwohci_softc *sc; u_int32_t fun; device_printf(fc->dev, "Initiate bus reset\n"); sc = (struct fwohci_softc *)fc; /* * Set root hold-off bit so that non cyclemaster capable node * shouldn't became the root node. */ #if 1 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); fun |= FW_PHY_IBR | FW_PHY_RHB; fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); #else /* Short bus reset */ fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); fun |= FW_PHY_ISBR | FW_PHY_RHB; fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); #endif } void fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) { struct fwohcidb_tr *db_tr, *fdb_tr; struct fwohci_dbch *dbch; struct fwohcidb *db; struct fw_pkt *fp; struct fwohci_txpkthdr *ohcifp; unsigned short chtag; int idb; dbch = &sc->it[dmach]; chtag = sc->it[dmach].xferq.flag & 0xff; db_tr = (struct fwohcidb_tr *)(bulkxfer->start); fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); /* device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr); */ for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) { db = db_tr->db; fp = (struct fw_pkt *)db_tr->buf; ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed; ohcifp->mode.ld[0] = fp->mode.ld[0]; ohcifp->mode.common.spd = 0 & 0x7; ohcifp->mode.stream.len = fp->mode.stream.len; ohcifp->mode.stream.chtag = chtag; ohcifp->mode.stream.tcode = 0xa; #if BYTE_ORDER == BIG_ENDIAN FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]); FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]); #endif FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK); FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len); FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); #if 0 /* if bulkxfer->npackets changes */ db[2].db.desc.cmd = OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS; db[0].db.desc.depend = = db[dbch->ndesc - 1].db.desc.depend = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc; #else FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc); FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc); #endif bulkxfer->end = (caddr_t)db_tr; db_tr = STAILQ_NEXT(db_tr, link); } db = ((struct fwohcidb_tr *)bulkxfer->end)->db; FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf); FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf); #if 0 /* if bulkxfer->npackets changes */ db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS; /* OHCI 1.1 and above */ db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS; #endif /* db_tr = (struct fwohcidb_tr *)bulkxfer->start; fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr); */ return; } static int fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, int poffset) { struct fwohcidb *db = db_tr->db; struct fw_xferq *it; int err = 0; it = &dbch->xferq; if(it->buf == 0){ err = EINVAL; return err; } db_tr->buf = fwdma_v_addr(it->buf, poffset); db_tr->dbcnt = 3; FWOHCI_DMA_WRITE(db[0].db.desc.cmd, OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8); FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0); bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed)); FWOHCI_DMA_WRITE(db[2].db.desc.addr, fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t)); FWOHCI_DMA_WRITE(db[2].db.desc.cmd, OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS); #if 1 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0); FWOHCI_DMA_WRITE(db[2].db.desc.res, 0); #endif return 0; } int fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr, int poffset, struct fwdma_alloc *dummy_dma) { struct fwohcidb *db = db_tr->db; struct fw_xferq *ir; int i, ldesc; bus_addr_t dbuf[2]; int dsiz[2]; ir = &dbch->xferq; if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) { db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map, ir->psize, &dbuf[0], BUS_DMA_NOWAIT); if (db_tr->buf == NULL) return(ENOMEM); db_tr->dbcnt = 1; dsiz[0] = ir->psize; bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD); } else { db_tr->dbcnt = 0; if (dummy_dma != NULL) { dsiz[db_tr->dbcnt] = sizeof(u_int32_t); dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr; } dsiz[db_tr->dbcnt] = ir->psize; if (ir->buf != NULL) { db_tr->buf = fwdma_v_addr(ir->buf, poffset); dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset); } db_tr->dbcnt++; } for(i = 0 ; i < db_tr->dbcnt ; i++){ FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]); FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]); if (ir->flag & FWXFERQ_STREAM) { FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE); } FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]); } ldesc = db_tr->dbcnt - 1; if (ir->flag & FWXFERQ_STREAM) { FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST); } FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS); return 0; } static int fwohci_arcv_swap(struct fw_pkt *fp, int len) { struct fw_pkt *fp0; u_int32_t ld0; int slen, hlen; #if BYTE_ORDER == BIG_ENDIAN int i; #endif ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]); #if 0 printf("ld0: x%08x\n", ld0); #endif fp0 = (struct fw_pkt *)&ld0; /* determine length to swap */ switch (fp0->mode.common.tcode) { case FWTCODE_RREQQ: case FWTCODE_WRES: case FWTCODE_WREQQ: case FWTCODE_RRESQ: case FWOHCITCODE_PHY: slen = 12; break; case FWTCODE_RREQB: case FWTCODE_WREQB: case FWTCODE_LREQ: case FWTCODE_RRESB: case FWTCODE_LRES: slen = 16; break; default: printf("Unknown tcode %d\n", fp0->mode.common.tcode); return(0); } hlen = tinfo[fp0->mode.common.tcode].hdr_len; if (hlen > len) { if (firewire_debug) printf("splitted header\n"); return(-hlen); } #if BYTE_ORDER == BIG_ENDIAN for(i = 0; i < slen/4; i ++) fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]); #endif return(hlen); } static int fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp) { struct tcode_info *info; int r; info = &tinfo[fp->mode.common.tcode]; r = info->hdr_len + sizeof(u_int32_t); if ((info->flag & FWTI_BLOCK_ASY) != 0) r += roundup2(fp->mode.wreqb.len, sizeof(u_int32_t)); if (r == sizeof(u_int32_t)) /* XXX */ device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); if (r > dbch->xferq.psize) { device_printf(sc->fc.dev, "Invalid packet length %d\n", r); /* panic ? */ } return r; } static void fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr) { struct fwohcidb *db = &db_tr->db[0]; FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf); FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize); FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1); fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE); dbch->bottom = db_tr; } static void fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) { struct fwohcidb_tr *db_tr; struct iovec vec[2]; struct fw_pkt pktbuf; int nvec; struct fw_pkt *fp; u_int8_t *ld; u_int32_t stat, off, status; u_int spd; int len, plen, hlen, pcnt, offset; int s; caddr_t buf; int resCount; if(&sc->arrq == dbch){ off = OHCI_ARQOFF; }else if(&sc->arrs == dbch){ off = OHCI_ARSOFF; }else{ return; } s = splfw(); db_tr = dbch->top; pcnt = 0; /* XXX we cannot handle a packet which lies in more than two buf */ fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD); fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE); status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; #if 0 printf("status 0x%04x, resCount 0x%04x\n", status, resCount); #endif while (status & OHCI_CNTL_DMA_ACTIVE) { len = dbch->xferq.psize - resCount; ld = (u_int8_t *)db_tr->buf; if (dbch->pdb_tr == NULL) { len -= dbch->buf_offset; ld += dbch->buf_offset; } if (len > 0) bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_POSTREAD); while (len > 0 ) { if (count >= 0 && count-- == 0) goto out; if(dbch->pdb_tr != NULL){ /* we have a fragment in previous buffer */ int rlen; offset = dbch->buf_offset; if (offset < 0) offset = - offset; buf = dbch->pdb_tr->buf + offset; rlen = dbch->xferq.psize - offset; if (firewire_debug) printf("rlen=%d, offset=%d\n", rlen, dbch->buf_offset); if (dbch->buf_offset < 0) { /* splitted in header, pull up */ char *p; p = (char *)&pktbuf; bcopy(buf, p, rlen); p += rlen; /* this must be too long but harmless */ rlen = sizeof(pktbuf) - rlen; if (rlen < 0) printf("why rlen < 0\n"); bcopy(db_tr->buf, p, rlen); ld += rlen; len -= rlen; hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf)); if (hlen < 0) { printf("hlen < 0 shouldn't happen"); } offset = sizeof(pktbuf); vec[0].iov_base = (char *)&pktbuf; vec[0].iov_len = offset; } else { /* splitted in payload */ offset = rlen; vec[0].iov_base = buf; vec[0].iov_len = rlen; } fp=(struct fw_pkt *)vec[0].iov_base; nvec = 1; } else { /* no fragment in previous buffer */ fp=(struct fw_pkt *)ld; hlen = fwohci_arcv_swap(fp, len); if (hlen == 0) /* XXX need reset */ goto out; if (hlen < 0) { dbch->pdb_tr = db_tr; dbch->buf_offset = - dbch->buf_offset; /* sanity check */ if (resCount != 0) printf("resCount = %d !?\n", resCount); /* XXX clear pdb_tr */ goto out; } offset = 0; nvec = 0; } plen = fwohci_get_plen(sc, dbch, fp) - offset; if (plen < 0) { /* minimum header size + trailer = sizeof(fw_pkt) so this shouldn't happens */ printf("plen(%d) is negative! offset=%d\n", plen, offset); /* XXX clear pdb_tr */ goto out; } if (plen > 0) { len -= plen; if (len < 0) { dbch->pdb_tr = db_tr; if (firewire_debug) printf("splitted payload\n"); /* sanity check */ if (resCount != 0) printf("resCount = %d !?\n", resCount); /* XXX clear pdb_tr */ goto out; } vec[nvec].iov_base = ld; vec[nvec].iov_len = plen; nvec ++; ld += plen; } dbch->buf_offset = ld - (u_int8_t *)db_tr->buf; if (nvec == 0) printf("nvec == 0\n"); /* DMA result-code will be written at the tail of packet */ #if BYTE_ORDER == BIG_ENDIAN stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16; #else stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; #endif #if 0 printf("plen: %d, stat %x\n", plen ,stat); #endif spd = (stat >> 5) & 0x3; stat &= 0x1f; switch(stat){ case FWOHCIEV_ACKPEND: #if 0 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode); #endif /* fall through */ case FWOHCIEV_ACKCOMPL: { struct fw_rcv_buf rb; if ((vec[nvec-1].iov_len -= sizeof(struct fwohci_trailer)) == 0) nvec--; rb.fc = &sc->fc; rb.vec = vec; rb.nvec = nvec; rb.spd = spd; fw_rcv(&rb); break; } case FWOHCIEV_BUSRST: if (sc->fc.status != FWBUSRESET) printf("got BUSRST packet!?\n"); break; default: device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); #if 0 /* XXX */ goto out; #endif break; } pcnt ++; if (dbch->pdb_tr != NULL) { fwohci_arcv_free_buf(dbch, dbch->pdb_tr); dbch->pdb_tr = NULL; } } out: if (resCount == 0) { /* done on this buffer */ if (dbch->pdb_tr == NULL) { fwohci_arcv_free_buf(dbch, db_tr); dbch->buf_offset = 0; } else if (dbch->pdb_tr != db_tr) printf("pdb_tr != db_tr\n"); db_tr = STAILQ_NEXT(db_tr, link); status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT; resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK; /* XXX check buffer overrun */ dbch->top = db_tr; } else { dbch->buf_offset = dbch->xferq.psize - resCount; break; } /* XXX make sure DMA is not dead */ } #if 0 if (pcnt < 1) printf("fwohci_arcv: no packets\n"); #endif splx(s); } Index: head/sys/dev/firewire/iec13213.h =================================================================== --- head/sys/dev/firewire/iec13213.h (revision 129540) +++ head/sys/dev/firewire/iec13213.h (revision 129541) @@ -1,251 +1,251 @@ /* * Copyright (c) 2003 Hidetoshi Shimokawa * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the acknowledgement as bellow: * * This product includes software developed by K. Kobayashi and H. Shimokawa * * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #define STATE_CLEAR 0x0000 #define STATE_SET 0x0004 #define NODE_IDS 0x0008 #define RESET_START 0x000c #define SPLIT_TIMEOUT_HI 0x0018 #define SPLIT_TIMEOUT_LO 0x001c #define CYCLE_TIME 0x0200 #define BUS_TIME 0x0204 #define BUSY_TIMEOUT 0x0210 #define PRIORITY_BUDGET 0x0218 #define BUS_MGR_ID 0x021c #define BANDWIDTH_AV 0x0220 #define CHANNELS_AV_HI 0x0224 #define CHANNELS_AV_LO 0x0228 #define IP_CHANNELS 0x0234 #define CONF_ROM 0x0400 #define TOPO_MAP 0x1000 #define SPED_MAP 0x2000 #define CSRTYPE_SHIFT 6 #define CSRTYPE_MASK (3 << CSRTYPE_SHIFT) #define CSRTYPE_I (0 << CSRTYPE_SHIFT) /* Immediate */ #define CSRTYPE_C (1 << CSRTYPE_SHIFT) /* CSR offset */ #define CSRTYPE_L (2 << CSRTYPE_SHIFT) /* Leaf */ #define CSRTYPE_D (3 << CSRTYPE_SHIFT) /* Directory */ /* * CSR keys * 00 - 2F: defined by CSR architecture standards. * 30 - 37: defined by BUS starndards * 38 - 3F: defined by Vendor/Specifier */ #define CSRKEY_MASK 0x3f #define CSRKEY_DESC 0x01 /* Descriptor */ #define CSRKEY_BDINFO 0x02 /* Bus_Dependent_Info */ #define CSRKEY_VENDOR 0x03 /* Vendor */ #define CSRKEY_HW 0x04 /* Hardware_Version */ #define CSRKEY_MODULE 0x07 /* Module */ #define CSRKEY_NCAP 0x0c /* Node_Capabilities */ #define CSRKEY_EUI64 0x0d /* EUI_64 */ #define CSRKEY_UNIT 0x11 /* Unit */ #define CSRKEY_SPEC 0x12 /* Specifier_ID */ #define CSRKEY_VER 0x13 /* Version */ #define CSRKEY_DINFO 0x14 /* Dependent_Info */ #define CSRKEY_ULOC 0x15 /* Unit_Location */ #define CSRKEY_MODEL 0x17 /* Model */ #define CSRKEY_INST 0x18 /* Instance */ #define CSRKEY_KEYW 0x19 /* Keyword */ #define CSRKEY_FEAT 0x1a /* Feature */ #define CSRKEY_EROM 0x1b /* Extended_ROM */ #define CSRKEY_EKSID 0x1c /* Extended_Key_Specifier_ID */ #define CSRKEY_EKEY 0x1d /* Extended_Key */ #define CSRKEY_EDATA 0x1e /* Extended_Data */ #define CSRKEY_MDESC 0x1f /* Modifiable_Descriptor */ #define CSRKEY_DID 0x20 /* Directory_ID */ #define CSRKEY_REV 0x21 /* Revision */ -#define CSRKEY_FIRM_VER 0x3c /* Firemware version */ +#define CSRKEY_FIRM_VER 0x3c /* Firmware version */ #define CSRKEY_UNIT_CH 0x3a /* Unit characteristics */ #define CSRKEY_COM_SPEC 0x38 /* Command set revision */ #define CSRKEY_COM_SET 0x39 /* Command set */ #define CROM_UDIR (CSRTYPE_D | CSRKEY_UNIT) /* 0x81 Unit directory */ #define CROM_TEXTLEAF (CSRTYPE_L | CSRKEY_DESC) /* 0x81 Text leaf */ #define CROM_LUN (CSRTYPE_I | CSRKEY_DINFO) /* 0x14 Logical unit num. */ #define CROM_MGM (CSRTYPE_C | CSRKEY_DINFO) /* 0x54 Management agent */ #define CSRVAL_VENDOR_PRIVATE 0xacde48 #define CSRVAL_1394TA 0x00a02d #define CSRVAL_ANSIT10 0x00609e #define CSRVAL_IETF 0x00005e #define CSR_PROTAVC 0x010001 #define CSR_PROTCAL 0x010002 #define CSR_PROTEHS 0x010004 #define CSR_PROTHAVI 0x010008 #define CSR_PROTCAM104 0x000100 #define CSR_PROTCAM120 0x000101 #define CSR_PROTCAM130 0x000102 #define CSR_PROTDPP 0x0a6be2 #define CSR_PROTIICP 0x4b661f #define CSRVAL_T10SBP2 0x010483 #define CSRVAL_SCSI 0x0104d8 struct csrreg { #if BYTE_ORDER == BIG_ENDIAN u_int32_t key:8, val:24; #else u_int32_t val:24, key:8; #endif }; struct csrhdr { #if BYTE_ORDER == BIG_ENDIAN u_int32_t info_len:8, crc_len:8, crc:16; #else u_int32_t crc:16, crc_len:8, info_len:8; #endif }; struct csrdirectory { BIT16x2(crc_len, crc); struct csrreg entry[0]; }; struct csrtext { BIT16x2(crc_len, crc); #if BYTE_ORDER == BIG_ENDIAN u_int32_t spec_type:8, spec_id:24; #else u_int32_t spec_id:24, spec_type:8; #endif u_int32_t lang_id; u_int32_t text[0]; }; struct bus_info { #define CSR_BUS_NAME_IEEE1394 0x31333934 u_int32_t bus_name; #if BYTE_ORDER == BIG_ENDIAN u_int32_t irmc:1, /* iso. resource manager capable */ cmc:1, /* cycle master capable */ isc:1, /* iso. operation support */ bmc:1, /* bus manager capable */ pmc:1, /* power manager capable */ :3, cyc_clk_acc:8, /* 0 <= ppm <= 100 */ max_rec:4, /* (2 << max_rec) bytes */ :2, max_rom:2, generation:4, :1, link_spd:3; #else u_int32_t link_spd:3, :1, generation:4, max_rom:2, :2, max_rec:4, /* (2 << max_rec) bytes */ cyc_clk_acc:8, /* 0 <= ppm <= 100 */ :3, pmc:1, /* power manager capable */ bmc:1, /* bus manager capable */ isc:1, /* iso. operation support */ cmc:1, /* cycle master capable */ irmc:1; /* iso. resource manager capable */ #endif struct fw_eui64 eui64; }; /* max_rom */ #define MAXROM_4 0 #define MAXROM_64 1 #define MAXROM_1024 2 #define CROM_MAX_DEPTH 10 struct crom_ptr { struct csrdirectory *dir; int index; }; struct crom_context { int depth; struct crom_ptr stack[CROM_MAX_DEPTH]; }; void crom_init_context(struct crom_context *, u_int32_t *); struct csrreg *crom_get(struct crom_context *); void crom_next(struct crom_context *); void crom_parse_text(struct crom_context *, char *, int); u_int16_t crom_crc(u_int32_t *r, int); struct csrreg *crom_search_key(struct crom_context *, u_int8_t); int crom_has_specver(u_int32_t *, u_int32_t, u_int32_t); #ifndef _KERNEL char *crom_desc(struct crom_context *, char *, int); #endif /* For CROM build */ #if defined(_KERNEL) || defined(TEST) #define CROM_MAX_CHUNK_LEN 20 struct crom_src { struct csrhdr hdr; struct bus_info businfo; STAILQ_HEAD(, crom_chunk) chunk_list; }; struct crom_chunk { STAILQ_ENTRY(crom_chunk) link; struct crom_chunk *ref_chunk; int ref_index; int offset; struct { BIT16x2(crc_len, crc); u_int32_t buf[CROM_MAX_CHUNK_LEN]; } data; }; extern int crom_add_quad(struct crom_chunk *, u_int32_t); extern int crom_add_entry(struct crom_chunk *, int, int); extern int crom_add_chunk(struct crom_src *src, struct crom_chunk *, struct crom_chunk *, int); extern int crom_add_simple_text(struct crom_src *src, struct crom_chunk *, struct crom_chunk *, char *); extern int crom_load(struct crom_src *, u_int32_t *, int); #endif