Index: head/sys/dev/fxp/if_fxp.c =================================================================== --- head/sys/dev/fxp/if_fxp.c (revision 121696) +++ head/sys/dev/fxp/if_fxp.c (revision 121697) @@ -1,2745 +1,2745 @@ /*- * Copyright (c) 1995, David Greenman * Copyright (c) 2001 Jonathan Lemon * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); /* * Intel EtherExpress Pro/100B PCI Fast Ethernet driver */ #include __FBSDID("$FreeBSD$"); #include #include #include #include /* #include */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* for DELAY */ #include #include #ifdef FXP_IP_CSUM_WAR #include #include #include #include #endif #include #include /* for PCIM_CMD_xxx */ #include #include #include #include #include MODULE_DEPEND(fxp, pci, 1, 1, 1); MODULE_DEPEND(fxp, ether, 1, 1, 1); MODULE_DEPEND(fxp, miibus, 1, 1, 1); #include "miibus_if.h" /* * NOTE! On the Alpha, we have an alignment constraint. The * card DMAs the packet immediately following the RFA. However, * the first thing in the packet is a 14-byte Ethernet header. * This means that the packet is misaligned. To compensate, * we actually offset the RFA 2 bytes into the cluster. This * alignes the packet after the Ethernet header at a 32-bit * boundary. HOWEVER! This means that the RFA is misaligned! */ #define RFA_ALIGNMENT_FUDGE 2 /* * Set initial transmit threshold at 64 (512 bytes). This is * increased by 64 (512 bytes) at a time, to maximum of 192 * (1536 bytes), if an underrun occurs. */ static int tx_threshold = 64; /* * The configuration byte map has several undefined fields which * must be one or must be zero. Set up a template for these bits * only, (assuming a 82557 chip) leaving the actual configuration * to fxp_init. * * See struct fxp_cb_config for the bit definitions. */ static u_char fxp_cb_config_template[] = { 0x0, 0x0, /* cb_status */ 0x0, 0x0, /* cb_command */ 0x0, 0x0, 0x0, 0x0, /* link_addr */ 0x0, /* 0 */ 0x0, /* 1 */ 0x0, /* 2 */ 0x0, /* 3 */ 0x0, /* 4 */ 0x0, /* 5 */ 0x32, /* 6 */ 0x0, /* 7 */ 0x0, /* 8 */ 0x0, /* 9 */ 0x6, /* 10 */ 0x0, /* 11 */ 0x0, /* 12 */ 0x0, /* 13 */ 0xf2, /* 14 */ 0x48, /* 15 */ 0x0, /* 16 */ 0x40, /* 17 */ 0xf0, /* 18 */ 0x0, /* 19 */ 0x3f, /* 20 */ 0x5 /* 21 */ }; struct fxp_ident { u_int16_t devid; int16_t revid; /* -1 matches anything */ char *name; }; /* * Claim various Intel PCI device identifiers for this driver. The * sub-vendor and sub-device field are extensively used to identify * particular variants, but we don't currently differentiate between * them. */ static struct fxp_ident fxp_ident_table[] = { { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" }, { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" }, { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" }, { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" }, { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" }, { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" }, { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" }, { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" }, { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" }, { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" }, { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" }, { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" }, { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" }, { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" }, { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" }, { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" }, { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" }, { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" }, { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" }, { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" }, { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" }, { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" }, { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" }, { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" }, { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" }, { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" }, { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" }, { 0, -1, NULL }, }; #ifdef FXP_IP_CSUM_WAR #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) #else #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) #endif static int fxp_probe(device_t dev); static int fxp_attach(device_t dev); static int fxp_detach(device_t dev); static int fxp_shutdown(device_t dev); static int fxp_suspend(device_t dev); static int fxp_resume(device_t dev); static void fxp_intr(void *xsc); static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, int count); static void fxp_init(void *xsc); static void fxp_init_body(struct fxp_softc *sc); static void fxp_tick(void *xsc); #ifndef BURN_BRIDGES static void fxp_powerstate_d0(device_t dev); #endif static void fxp_start(struct ifnet *ifp); static void fxp_start_body(struct ifnet *ifp); static void fxp_stop(struct fxp_softc *sc); static void fxp_release(struct fxp_softc *sc); static int fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data); static void fxp_watchdog(struct ifnet *ifp); static int fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp); static int fxp_mc_addrs(struct fxp_softc *sc); static void fxp_mc_setup(struct fxp_softc *sc); static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize); static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data); static void fxp_autosize_eeprom(struct fxp_softc *sc); static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words); static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words); static int fxp_ifmedia_upd(struct ifnet *ifp); static void fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); static int fxp_serial_ifmedia_upd(struct ifnet *ifp); static void fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); static void fxp_miibus_writereg(device_t dev, int phy, int reg, int value); static void fxp_load_ucode(struct fxp_softc *sc); static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high); static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); static void fxp_scb_wait(struct fxp_softc *sc); static void fxp_scb_cmd(struct fxp_softc *sc, int cmd); static void fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, bus_dma_tag_t dmat, bus_dmamap_t map); static device_method_t fxp_methods[] = { /* Device interface */ DEVMETHOD(device_probe, fxp_probe), DEVMETHOD(device_attach, fxp_attach), DEVMETHOD(device_detach, fxp_detach), DEVMETHOD(device_shutdown, fxp_shutdown), DEVMETHOD(device_suspend, fxp_suspend), DEVMETHOD(device_resume, fxp_resume), /* MII interface */ DEVMETHOD(miibus_readreg, fxp_miibus_readreg), DEVMETHOD(miibus_writereg, fxp_miibus_writereg), { 0, 0 } }; static driver_t fxp_driver = { "fxp", fxp_methods, sizeof(struct fxp_softc), }; static devclass_t fxp_devclass; DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0); DRIVER_MODULE(fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); static int fxp_rnr; SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); static int fxp_noflow; SYSCTL_INT(_hw, OID_AUTO, fxp_noflow, CTLFLAG_RW, &fxp_noflow, 0, "fxp flow control disabled"); TUNABLE_INT("hw.fxp_noflow", &fxp_noflow); /* * Wait for the previous command to be accepted (but not necessarily * completed). */ static void fxp_scb_wait(struct fxp_softc *sc) { int i = 10000; while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) DELAY(2); if (i == 0) device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), CSR_READ_1(sc, FXP_CSR_SCB_STATACK), CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); } static void fxp_scb_cmd(struct fxp_softc *sc, int cmd) { if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); fxp_scb_wait(sc); } CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); } static void fxp_dma_wait(struct fxp_softc *sc, volatile u_int16_t *status, bus_dma_tag_t dmat, bus_dmamap_t map) { int i = 10000; bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); while (!(le16toh(*status) & FXP_CB_STATUS_C) && --i) { DELAY(2); bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTREAD); } if (i == 0) device_printf(sc->dev, "DMA timeout\n"); } /* * Return identification string if this device is ours. */ static int fxp_probe(device_t dev) { u_int16_t devid; u_int8_t revid; struct fxp_ident *ident; if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { devid = pci_get_device(dev); revid = pci_get_revid(dev); for (ident = fxp_ident_table; ident->name != NULL; ident++) { if (ident->devid == devid && (ident->revid == revid || ident->revid == -1)) { device_set_desc(dev, ident->name); return (0); } } } return (ENXIO); } #ifndef BURN_BRIDGES static void fxp_powerstate_d0(device_t dev) { #if __FreeBSD_version >= 430002 u_int32_t iobase, membase, irq; if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { /* Save important PCI config data. */ iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); membase = pci_read_config(dev, FXP_PCI_MMBA, 4); irq = pci_read_config(dev, PCIR_INTLINE, 4); /* Reset the power state. */ device_printf(dev, "chip is in D%d power mode " "-- setting to D0\n", pci_get_powerstate(dev)); pci_set_powerstate(dev, PCI_POWERSTATE_D0); /* Restore PCI config data. */ pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); pci_write_config(dev, FXP_PCI_MMBA, membase, 4); pci_write_config(dev, PCIR_INTLINE, irq, 4); } #endif } #endif static void fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) { u_int32_t *addr; if (error) return; KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); addr = arg; *addr = segs->ds_addr; } static int fxp_attach(device_t dev) { int error = 0; struct fxp_softc *sc = device_get_softc(dev); struct ifnet *ifp; struct fxp_rx *rxp; u_int32_t val; u_int16_t data, myea[ETHER_ADDR_LEN / 2]; int i, rid, m1, m2, prefer_iomap, maxtxseg; int s, ipcbxmit_disable; sc->dev = dev; callout_init(&sc->stat_ch, CALLOUT_MPSAFE); sysctl_ctx_init(&sc->sysctl_ctx); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, fxp_serial_ifmedia_sts); s = splimp(); /* * Enable bus mastering. */ pci_enable_busmaster(dev); val = pci_read_config(dev, PCIR_COMMAND, 2); #ifndef BURN_BRIDGES fxp_powerstate_d0(dev); #endif /* * Figure out which we should try first - memory mapping or i/o mapping? * We default to memory mapping. Then we accept an override from the * command line. Then we check to see which one is enabled. */ m1 = PCIM_CMD_MEMEN; m2 = PCIM_CMD_PORTEN; prefer_iomap = 0; if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { m1 = PCIM_CMD_PORTEN; m2 = PCIM_CMD_MEMEN; } sc->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 0, ~0, 1, RF_ACTIVE); if (sc->mem == NULL) { sc->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 0, ~0, 1, RF_ACTIVE); } if (!sc->mem) { error = ENXIO; goto fail; } if (bootverbose) { device_printf(dev, "using %s space register mapping\n", sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); } sc->sc_st = rman_get_bustag(sc->mem); sc->sc_sh = rman_get_bushandle(sc->mem); /* * Allocate our interrupt. */ rid = 0; sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); if (sc->irq == NULL) { device_printf(dev, "could not map interrupt\n"); error = ENXIO; goto fail; } /* * Reset to a stable state. */ CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); DELAY(10); /* * Find out how large of an SEEPROM we have. */ fxp_autosize_eeprom(sc); /* * Determine whether we must use the 503 serial interface. */ fxp_read_eeprom(sc, &data, 6, 1); if ((data & FXP_PHY_DEVICE_MASK) != 0 && (data & FXP_PHY_SERIAL_ONLY)) sc->flags |= FXP_FLAG_SERIAL_MEDIA; /* * Create the sysctl tree */ sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, device_get_nameunit(dev), CTLFLAG_RD, 0, ""); if (sc->sysctl_tree == NULL) { error = ENXIO; goto fail; } SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", "FXP driver receive interrupt microcode bundling delay"); SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", "FXP driver receive interrupt microcode bundle size limit"); /* * Pull in device tunables. */ sc->tunable_int_delay = TUNABLE_INT_DELAY; sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "int_delay", &sc->tunable_int_delay); (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "bundle_max", &sc->tunable_bundle_max); /* * Find out the chip revision; lump all 82557 revs together. */ fxp_read_eeprom(sc, &data, 5, 1); if ((data >> 8) == 1) sc->revision = FXP_REV_82557; else sc->revision = pci_get_revid(dev); /* * Enable workarounds for certain chip revision deficiencies. * * Systems based on the ICH2/ICH2-M chip from Intel, and possibly * some systems based a normal 82559 design, have a defect where * the chip can cause a PCI protocol violation if it receives * a CU_RESUME command when it is entering the IDLE state. The * workaround is to disable Dynamic Standby Mode, so the chip never * deasserts CLKRUN#, and always remains in an active state. * * See Intel 82801BA/82801BAM Specification Update, Errata #30. */ i = pci_get_device(dev); if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || sc->revision >= FXP_REV_82559_A0) { fxp_read_eeprom(sc, &data, 10, 1); if (data & 0x02) { /* STB enable */ u_int16_t cksum; int i; device_printf(dev, "Disabling dynamic standby mode in EEPROM\n"); data &= ~0x02; fxp_write_eeprom(sc, &data, 10, 1); device_printf(dev, "New EEPROM ID: 0x%x\n", data); cksum = 0; for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { fxp_read_eeprom(sc, &data, i, 1); cksum += data; } i = (1 << sc->eeprom_size) - 1; cksum = 0xBABA - cksum; fxp_read_eeprom(sc, &data, i, 1); fxp_write_eeprom(sc, &cksum, i, 1); device_printf(dev, "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", i, data, cksum); #if 1 /* * If the user elects to continue, try the software * workaround, as it is better than nothing. */ sc->flags |= FXP_FLAG_CU_RESUME_BUG; #endif } } /* * If we are not a 82557 chip, we can enable extended features. */ if (sc->revision != FXP_REV_82557) { /* * If MWI is enabled in the PCI configuration, and there * is a valid cacheline size (8 or 16 dwords), then tell * the board to turn on MWI. */ if (val & PCIM_CMD_MWRICEN && pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) sc->flags |= FXP_FLAG_MWI_ENABLE; /* turn on the extended TxCB feature */ sc->flags |= FXP_FLAG_EXT_TXCB; /* enable reception of long frames for VLAN */ sc->flags |= FXP_FLAG_LONG_PKT_EN; } /* * Enable use of extended RFDs and TCBs for 82550 * and later chips. Note: we need extended TXCB support * too, but that's already enabled by the code above. * Be careful to do this only on the right devices. * * At least some 82550 cards probed as "chip=0x12298086 rev=0x0d" * truncate packets that end with an mbuf containing 1 to 3 bytes * when used with this feature enabled in the previous version of the * driver. This problem appears to be fixed now that the driver * always sets the hardware parse bit in the IPCB structure, which * the "Intel 8255x 10/100 Mbps Ethernet Controller Family Open * Source Software Developer Manual" says is necessary in the * cases where packet truncation was observed. * * The device hint "hint.fxp.UNIT_NUMBER.ipcbxmit_disable" * allows this feature to be disabled at boot time. * * If fxp is not compiled into the kernel, this feature may also * be disabled at run time: * # kldunload fxp * # kenv hint.fxp.0.ipcbxmit_disable=1 * # kldload fxp */ if (resource_int_value("fxp", device_get_unit(dev), "ipcbxmit_disable", &ipcbxmit_disable) != 0) ipcbxmit_disable = 0; if (ipcbxmit_disable == 0 && (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C)) { sc->rfa_size = sizeof (struct fxp_rfa); sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT; sc->flags |= FXP_FLAG_EXT_RFA; } else { sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN; sc->tx_cmd = FXP_CB_COMMAND_XMIT; } /* * Allocate DMA tags and DMA safe memory. */ maxtxseg = sc->flags & FXP_FLAG_EXT_RFA ? FXP_NTXSEG - 1 : FXP_NTXSEG; error = bus_dma_tag_create(NULL, 2, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * maxtxseg, maxtxseg, MCLBYTES, 0, busdma_lock_mutex, &Giant, &sc->fxp_mtag); if (error) { device_printf(dev, "could not allocate dma tag\n"); goto fail; } error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0, busdma_lock_mutex, &Giant, &sc->fxp_stag); if (error) { device_printf(dev, "could not allocate dma tag\n"); goto fail; } error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->fxp_smap); if (error) goto fail; error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats, sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0); if (error) { device_printf(dev, "could not map the stats buffer\n"); goto fail; } error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, busdma_lock_mutex, &Giant, &sc->cbl_tag); if (error) { device_printf(dev, "could not allocate dma tag\n"); goto fail; } error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->cbl_map); if (error) goto fail; error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map, sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr, &sc->fxp_desc.cbl_addr, 0); if (error) { device_printf(dev, "could not map DMA memory\n"); goto fail; } error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0, busdma_lock_mutex, &Giant, &sc->mcs_tag); if (error) { device_printf(dev, "could not allocate dma tag\n"); goto fail; } error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp, BUS_DMA_NOWAIT, &sc->mcs_map); if (error) goto fail; error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp, sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0); if (error) { device_printf(dev, "can't map the multicast setup command\n"); goto fail; } /* * Pre-allocate the TX DMA maps. */ for (i = 0; i < FXP_NTXCB; i++) { error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->fxp_desc.tx_list[i].tx_map); if (error) { device_printf(dev, "can't create DMA map for TX\n"); goto fail; } } error = bus_dmamap_create(sc->fxp_mtag, 0, &sc->spare_map); if (error) { device_printf(dev, "can't create spare DMA map\n"); goto fail; } /* * Pre-allocate our receive buffers. */ sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL; for (i = 0; i < FXP_NRFABUFS; i++) { rxp = &sc->fxp_desc.rx_list[i]; error = bus_dmamap_create(sc->fxp_mtag, 0, &rxp->rx_map); if (error) { device_printf(dev, "can't create DMA map for RX\n"); goto fail; } if (fxp_add_rfabuf(sc, rxp) != 0) { error = ENOMEM; goto fail; } } /* * Read MAC address. */ fxp_read_eeprom(sc, myea, 0, 3); sc->arpcom.ac_enaddr[0] = myea[0] & 0xff; sc->arpcom.ac_enaddr[1] = myea[0] >> 8; sc->arpcom.ac_enaddr[2] = myea[1] & 0xff; sc->arpcom.ac_enaddr[3] = myea[1] >> 8; sc->arpcom.ac_enaddr[4] = myea[2] & 0xff; sc->arpcom.ac_enaddr[5] = myea[2] >> 8; device_printf(dev, "Ethernet address %6D%s\n", sc->arpcom.ac_enaddr, ":", sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); if (bootverbose) { device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", pci_get_vendor(dev), pci_get_device(dev), pci_get_subvendor(dev), pci_get_subdevice(dev), pci_get_revid(dev)); fxp_read_eeprom(sc, &data, 10, 1); device_printf(dev, "Dynamic Standby mode is %s\n", data & 0x02 ? "enabled" : "disabled"); } /* * If this is only a 10Mbps device, then there is no MII, and * the PHY will use a serial interface instead. * * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter * doesn't have a programming interface of any sort. The * media is sensed automatically based on how the link partner * is configured. This is, in essence, manual configuration. */ if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); } else { if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, fxp_ifmedia_sts)) { device_printf(dev, "MII without any PHY!\n"); error = ENXIO; goto fail; } } ifp = &sc->arpcom.ac_if; ifp->if_unit = device_get_unit(dev); ifp->if_name = "fxp"; ifp->if_output = ether_output; ifp->if_baudrate = 100000000; ifp->if_init = fxp_init; ifp->if_softc = sc; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = fxp_ioctl; ifp->if_start = fxp_start; ifp->if_watchdog = fxp_watchdog; /* Enable checksum offload for 82550 or better chips */ if (sc->flags & FXP_FLAG_EXT_RFA) { ifp->if_hwassist = FXP_CSUM_FEATURES; ifp->if_capabilities = IFCAP_HWCSUM; ifp->if_capenable = ifp->if_capabilities; } /* * Attach the interface. */ ether_ifattach(ifp, sc->arpcom.ac_enaddr); /* * Tell the upper layer(s) we support long frames. */ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); ifp->if_capabilities |= IFCAP_VLAN_MTU; /* * Let the system queue as many packets as we have available * TX descriptors. */ ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; /* * Hook our interrupt after all initialization is complete. * XXX This driver has been tested with the INTR_MPSAFFE flag set * however, ifp and its functions are not fully locked so MPSAFE * should not be used unless you can handle potential data loss. */ - error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET /*|INTR_MPSAFE*/, + error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, fxp_intr, sc, &sc->ih); if (error) { device_printf(dev, "could not setup irq\n"); ether_ifdetach(&sc->arpcom.ac_if); goto fail; } fail: splx(s); if (error) fxp_release(sc); return (error); } /* * Release all resources. The softc lock should not be held and the * interrupt should already be torn down. */ static void fxp_release(struct fxp_softc *sc) { struct fxp_rx *rxp; struct fxp_tx *txp; int i; mtx_assert(&sc->sc_mtx, MA_NOTOWNED); if (sc->ih) panic("fxp_release() called with intr handle still active"); if (sc->miibus) device_delete_child(sc->dev, sc->miibus); bus_generic_detach(sc->dev); ifmedia_removeall(&sc->sc_media); if (sc->fxp_desc.cbl_list) { bus_dmamap_unload(sc->cbl_tag, sc->cbl_map); bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list, sc->cbl_map); } if (sc->fxp_stats) { bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap); bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap); } if (sc->mcsp) { bus_dmamap_unload(sc->mcs_tag, sc->mcs_map); bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map); } if (sc->irq) bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); if (sc->mem) bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); if (sc->fxp_mtag) { for (i = 0; i < FXP_NRFABUFS; i++) { rxp = &sc->fxp_desc.rx_list[i]; if (rxp->rx_mbuf != NULL) { bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); m_freem(rxp->rx_mbuf); } bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); } bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); bus_dma_tag_destroy(sc->fxp_mtag); } if (sc->fxp_stag) { for (i = 0; i < FXP_NTXCB; i++) { txp = &sc->fxp_desc.tx_list[i]; if (txp->tx_mbuf != NULL) { bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); m_freem(txp->tx_mbuf); } bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); } bus_dma_tag_destroy(sc->fxp_stag); } if (sc->cbl_tag) bus_dma_tag_destroy(sc->cbl_tag); if (sc->mcs_tag) bus_dma_tag_destroy(sc->mcs_tag); sysctl_ctx_free(&sc->sysctl_ctx); mtx_destroy(&sc->sc_mtx); } /* * Detach interface. */ static int fxp_detach(device_t dev) { struct fxp_softc *sc = device_get_softc(dev); int s; FXP_LOCK(sc); s = splimp(); sc->suspended = 1; /* Do same thing as we do for suspend */ /* * Close down routes etc. */ ether_ifdetach(&sc->arpcom.ac_if); /* * Stop DMA and drop transmit queue, but disable interrupts first. */ CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); fxp_stop(sc); FXP_UNLOCK(sc); /* * Unhook interrupt before dropping lock. This is to prevent * races with fxp_intr(). */ bus_teardown_intr(sc->dev, sc->irq, sc->ih); sc->ih = NULL; splx(s); /* Release our allocated resources. */ fxp_release(sc); return (0); } /* * Device shutdown routine. Called at system shutdown after sync. The * main purpose of this routine is to shut off receiver DMA so that * kernel memory doesn't get clobbered during warmboot. */ static int fxp_shutdown(device_t dev) { /* * Make sure that DMA is disabled prior to reboot. Not doing * do could allow DMA to corrupt kernel memory during the * reboot before the driver initializes. */ fxp_stop((struct fxp_softc *) device_get_softc(dev)); return (0); } /* * Device suspend routine. Stop the interface and save some PCI * settings in case the BIOS doesn't restore them properly on * resume. */ static int fxp_suspend(device_t dev) { struct fxp_softc *sc = device_get_softc(dev); int i, s; FXP_LOCK(sc); s = splimp(); fxp_stop(sc); for (i = 0; i < 5; i++) sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); sc->suspended = 1; FXP_UNLOCK(sc); splx(s); return (0); } /* * Device resume routine. Restore some PCI settings in case the BIOS * doesn't, re-enable busmastering, and restart the interface if * appropriate. */ static int fxp_resume(device_t dev) { struct fxp_softc *sc = device_get_softc(dev); struct ifnet *ifp = &sc->sc_if; u_int16_t pci_command; int i, s; FXP_LOCK(sc); s = splimp(); #ifndef BURN_BRIDGES fxp_powerstate_d0(dev); #endif /* better way to do this? */ for (i = 0; i < 5; i++) pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); /* reenable busmastering */ pci_command = pci_read_config(dev, PCIR_COMMAND, 2); pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); pci_write_config(dev, PCIR_COMMAND, pci_command, 2); CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); DELAY(10); /* reinitialize interface if necessary */ if (ifp->if_flags & IFF_UP) fxp_init_body(sc); sc->suspended = 0; FXP_UNLOCK(sc); splx(s); return (0); } static void fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) { u_int16_t reg; int x; /* * Shift in data. */ for (x = 1 << (length - 1); x; x >>= 1) { if (data & x) reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; else reg = FXP_EEPROM_EECS; CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); DELAY(1); CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); DELAY(1); CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); DELAY(1); } } /* * Read from the serial EEPROM. Basically, you manually shift in * the read opcode (one bit at a time) and then shift in the address, * and then you shift out the data (all of this one bit at a time). * The word size is 16 bits, so you have to provide the address for * every 16 bits of data. */ static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) { u_int16_t reg, data; int x; CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); /* * Shift in read opcode. */ fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); /* * Shift in address. */ data = 0; for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { if (offset & x) reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; else reg = FXP_EEPROM_EECS; CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); DELAY(1); CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); DELAY(1); CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); DELAY(1); reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; data++; if (autosize && reg == 0) { sc->eeprom_size = data; break; } } /* * Shift out data. */ data = 0; reg = FXP_EEPROM_EECS; for (x = 1 << 15; x; x >>= 1) { CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); DELAY(1); if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) data |= x; CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); DELAY(1); } CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); DELAY(1); return (data); } static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) { int i; /* * Erase/write enable. */ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); fxp_eeprom_shiftin(sc, 0x4, 3); fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); DELAY(1); /* * Shift in write opcode, address, data. */ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); fxp_eeprom_shiftin(sc, data, 16); CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); DELAY(1); /* * Wait for EEPROM to finish up. */ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); DELAY(1); for (i = 0; i < 1000; i++) { if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) break; DELAY(50); } CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); DELAY(1); /* * Erase/write disable. */ CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); fxp_eeprom_shiftin(sc, 0x4, 3); fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); DELAY(1); } /* * From NetBSD: * * Figure out EEPROM size. * * 559's can have either 64-word or 256-word EEPROMs, the 558 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet * talks about the existance of 16 to 256 word EEPROMs. * * The only known sizes are 64 and 256, where the 256 version is used * by CardBus cards to store CIS information. * * The address is shifted in msb-to-lsb, and after the last * address-bit the EEPROM is supposed to output a `dummy zero' bit, * after which follows the actual data. We try to detect this zero, by * probing the data-out bit in the EEPROM control register just after * having shifted in a bit. If the bit is zero, we assume we've * shifted enough address bits. The data-out should be tri-state, * before this, which should translate to a logical one. */ static void fxp_autosize_eeprom(struct fxp_softc *sc) { /* guess maximum size of 256 words */ sc->eeprom_size = 8; /* autosize */ (void) fxp_eeprom_getword(sc, 0, 1); } static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) { int i; for (i = 0; i < words; i++) data[i] = fxp_eeprom_getword(sc, offset + i, 0); } static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) { int i; for (i = 0; i < words; i++) fxp_eeprom_putword(sc, offset + i, data[i]); } static void fxp_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, bus_size_t mapsize, int error) { struct fxp_softc *sc; struct fxp_cb_tx *txp; int i; if (error) return; KASSERT(nseg <= FXP_NTXSEG, ("too many DMA segments")); sc = arg; txp = sc->fxp_desc.tx_last->tx_next->tx_cb; for (i = 0; i < nseg; i++) { KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large")); /* * If this is an 82550/82551, then we're using extended * TxCBs _and_ we're using checksum offload. This means * that the TxCB is really an IPCB. One major difference * between the two is that with plain extended TxCBs, * the bottom half of the TxCB contains two entries from * the TBD array, whereas IPCBs contain just one entry: * one entry (8 bytes) has been sacrificed for the TCP/IP * checksum offload control bits. So to make things work * right, we have to start filling in the TBD array * starting from a different place depending on whether * the chip is an 82550/82551 or not. */ if (sc->flags & FXP_FLAG_EXT_RFA) { txp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr); txp->tbd[i + 1].tb_size = htole32(segs[i].ds_len); } else { txp->tbd[i].tb_addr = htole32(segs[i].ds_addr); txp->tbd[i].tb_size = htole32(segs[i].ds_len); } } txp->tbd_number = nseg; } /* * Grab the softc lock and call the real fxp_start_body() routine */ static void fxp_start(struct ifnet *ifp) { struct fxp_softc *sc = ifp->if_softc; FXP_LOCK(sc); fxp_start_body(ifp); FXP_UNLOCK(sc); } /* * Start packet transmission on the interface. * This routine must be called with the softc lock held, and is an * internal entry point only. */ static void fxp_start_body(struct ifnet *ifp) { struct fxp_softc *sc = ifp->if_softc; struct fxp_tx *txp; struct mbuf *mb_head; int error; mtx_assert(&sc->sc_mtx, MA_OWNED); /* * See if we need to suspend xmit until the multicast filter * has been reprogrammed (which can only be done at the head * of the command chain). */ if (sc->need_mcsetup) { return; } txp = NULL; /* * We're finished if there is nothing more to add to the list or if * we're all filled up with buffers to transmit. * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add * a NOP command when needed. */ while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { /* * Grab a packet to transmit. */ IF_DEQUEUE(&ifp->if_snd, mb_head); /* * Get pointer to next available tx desc. */ txp = sc->fxp_desc.tx_last->tx_next; /* * A note in Appendix B of the Intel 8255x 10/100 Mbps * Ethernet Controller Family Open Source Software * Developer Manual says: * Using software parsing is only allowed with legal * TCP/IP or UDP/IP packets. * ... * For all other datagrams, hardware parsing must * be used. * Software parsing appears to truncate ICMP and * fragmented UDP packets that contain one to three * bytes in the second (and final) mbuf of the packet. */ if (sc->flags & FXP_FLAG_EXT_RFA) txp->tx_cb->ipcb_ip_activation_high = FXP_IPCB_HARDWAREPARSING_ENABLE; /* * Deal with TCP/IP checksum offload. Note that * in order for TCP checksum offload to work, * the pseudo header checksum must have already * been computed and stored in the checksum field * in the TCP header. The stack should have * already done this for us. */ if (mb_head->m_pkthdr.csum_flags) { if (mb_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE; if (mb_head->m_pkthdr.csum_flags & CSUM_TCP) txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET; } #ifdef FXP_IP_CSUM_WAR /* * XXX The 82550 chip appears to have trouble * dealing with IP header checksums in very small * datagrams, namely fragments from 1 to 3 bytes * in size. For example, say you want to transmit * a UDP packet of 1473 bytes. The packet will be * fragmented over two IP datagrams, the latter * containing only one byte of data. The 82550 will * botch the header checksum on the 1-byte fragment. * As long as the datagram contains 4 or more bytes * of data, you're ok. * * The following code attempts to work around this * problem: if the datagram is less than 38 bytes * in size (14 bytes ether header, 20 bytes IP header, * plus 4 bytes of data), we punt and compute the IP * header checksum by hand. This workaround doesn't * work very well, however, since it can be fooled * by things like VLAN tags and IP options that make * the header sizes/offsets vary. */ if (mb_head->m_pkthdr.csum_flags & CSUM_IP) { if (mb_head->m_pkthdr.len < 38) { struct ip *ip; mb_head->m_data += ETHER_HDR_LEN; ip = mtod(mb_head, struct ip *); ip->ip_sum = in_cksum(mb_head, ip->ip_hl << 2); mb_head->m_data -= ETHER_HDR_LEN; } else { txp->tx_cb->ipcb_ip_activation_high = FXP_IPCB_HARDWAREPARSING_ENABLE; txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_IP_CHECKSUM_ENABLE; } } #endif } /* * Go through each of the mbufs in the chain and initialize * the transmit buffer descriptors with the physical address * and size of the mbuf. */ error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, mb_head, fxp_dma_map_txbuf, sc, 0); if (error && error != EFBIG) { device_printf(sc->dev, "can't map mbuf (error %d)\n", error); m_freem(mb_head); break; } if (error) { struct mbuf *mn; /* * We ran out of segments. We have to recopy this * mbuf chain first. Bail out if we can't get the * new buffers. */ mn = m_defrag(mb_head, M_DONTWAIT); if (mn == NULL) { m_freem(mb_head); break; } else { mb_head = mn; } error = bus_dmamap_load_mbuf(sc->fxp_mtag, txp->tx_map, mb_head, fxp_dma_map_txbuf, sc, 0); if (error) { device_printf(sc->dev, "can't map mbuf (error %d)\n", error); m_freem(mb_head); break; } } bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_PREWRITE); txp->tx_mbuf = mb_head; txp->tx_cb->cb_status = 0; txp->tx_cb->byte_count = 0; if (sc->tx_queued != FXP_CXINT_THRESH - 1) { txp->tx_cb->cb_command = htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S); } else { txp->tx_cb->cb_command = htole16(sc->tx_cmd | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); /* * Set a 5 second timer just in case we don't hear * from the card again. */ ifp->if_timer = 5; } txp->tx_cb->tx_threshold = tx_threshold; /* * Advance the end of list forward. */ #ifdef __alpha__ /* * On platforms which can't access memory in 16-bit * granularities, we must prevent the card from DMA'ing * up the status while we update the command field. * This could cause us to overwrite the completion status. * XXX This is probably bogus and we're _not_ looking * for atomicity here. */ atomic_clear_16(&sc->fxp_desc.tx_last->tx_cb->cb_command, htole16(FXP_CB_COMMAND_S)); #else sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); #endif /*__alpha__*/ sc->fxp_desc.tx_last = txp; /* * Advance the beginning of the list forward if there are * no other packets queued (when nothing is queued, tx_first * sits on the last TxCB that was sent out). */ if (sc->tx_queued == 0) sc->fxp_desc.tx_first = txp; sc->tx_queued++; /* * Pass packet to bpf if there is a listener. */ BPF_MTAP(ifp, mb_head); } bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); /* * We're finished. If we added to the list, issue a RESUME to get DMA * going again if suspended. */ if (txp != NULL) { fxp_scb_wait(sc); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); } } #ifdef DEVICE_POLLING static poll_handler_t fxp_poll; static void fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct fxp_softc *sc = ifp->if_softc; u_int8_t statack; FXP_LOCK(sc); if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); FXP_UNLOCK(sc); return; } statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | FXP_SCB_STATACK_FR; if (cmd == POLL_AND_CHECK_STATUS) { u_int8_t tmp; tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); if (tmp == 0xff || tmp == 0) { FXP_UNLOCK(sc); return; /* nothing to do */ } tmp &= ~statack; /* ack what we can */ if (tmp != 0) CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); statack |= tmp; } fxp_intr_body(sc, ifp, statack, count); FXP_UNLOCK(sc); } #endif /* DEVICE_POLLING */ /* * Process interface interrupts. */ static void fxp_intr(void *xsc) { struct fxp_softc *sc = xsc; struct ifnet *ifp = &sc->sc_if; u_int8_t statack; FXP_LOCK(sc); if (sc->suspended) { FXP_UNLOCK(sc); return; } #ifdef DEVICE_POLLING if (ifp->if_flags & IFF_POLLING) { FXP_UNLOCK(sc); return; } if (ether_poll_register(fxp_poll, ifp)) { /* disable interrupts */ CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); FXP_UNLOCK(sc); fxp_poll(ifp, 0, 1); return; } #endif while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { /* * It should not be possible to have all bits set; the * FXP_SCB_INTR_SWI bit always returns 0 on a read. If * all bits are set, this may indicate that the card has * been physically ejected, so ignore it. */ if (statack == 0xff) { FXP_UNLOCK(sc); return; } /* * First ACK all the interrupts in this pass. */ CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); fxp_intr_body(sc, ifp, statack, -1); } FXP_UNLOCK(sc); } static void fxp_txeof(struct fxp_softc *sc) { struct fxp_tx *txp; bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREREAD); for (txp = sc->fxp_desc.tx_first; sc->tx_queued && (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0; txp = txp->tx_next) { if (txp->tx_mbuf != NULL) { bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); m_freem(txp->tx_mbuf); txp->tx_mbuf = NULL; /* clear this to reset csum offload bits */ txp->tx_cb->tbd[0].tb_addr = 0; } sc->tx_queued--; } sc->fxp_desc.tx_first = txp; bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); } static void fxp_intr_body(struct fxp_softc *sc, struct ifnet *ifp, u_int8_t statack, int count) { struct mbuf *m; struct fxp_rx *rxp; struct fxp_rfa *rfa; int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; mtx_assert(&sc->sc_mtx, MA_OWNED); if (rnr) fxp_rnr++; #ifdef DEVICE_POLLING /* Pick up a deferred RNR condition if `count' ran out last time. */ if (sc->flags & FXP_FLAG_DEFERRED_RNR) { sc->flags &= ~FXP_FLAG_DEFERRED_RNR; rnr = 1; } #endif /* * Free any finished transmit mbuf chains. * * Handle the CNA event likt a CXTNO event. It used to * be that this event (control unit not ready) was not * encountered, but it is now with the SMPng modifications. * The exact sequence of events that occur when the interface * is brought up are different now, and if this event * goes unhandled, the configuration/rxfilter setup sequence * can stall for several seconds. The result is that no * packets go out onto the wire for about 5 to 10 seconds * after the interface is ifconfig'ed for the first time. */ if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { fxp_txeof(sc); ifp->if_timer = 0; if (sc->tx_queued == 0) { if (sc->need_mcsetup) fxp_mc_setup(sc); } /* * Try to start more packets transmitting. */ if (ifp->if_snd.ifq_head != NULL) fxp_start_body(ifp); } /* * Just return if nothing happened on the receive side. */ if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) return; /* * Process receiver interrupts. If a no-resource (RNR) * condition exists, get whatever packets we can and * re-start the receiver. * * When using polling, we do not process the list to completion, * so when we get an RNR interrupt we must defer the restart * until we hit the last buffer with the C bit set. * If we run out of cycles and rfa_headm has the C bit set, * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so * that the info will be used in the subsequent polling cycle. */ for (;;) { rxp = sc->fxp_desc.rx_head; m = rxp->rx_mbuf; rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, BUS_DMASYNC_POSTREAD); #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ if (count >= 0 && count-- == 0) { if (rnr) { /* Defer RNR processing until the next time. */ sc->flags |= FXP_FLAG_DEFERRED_RNR; rnr = 0; } break; } #endif /* DEVICE_POLLING */ if ((le16toh(rfa->rfa_status) & FXP_RFA_STATUS_C) == 0) break; /* * Advance head forward. */ sc->fxp_desc.rx_head = rxp->rx_next; /* * Add a new buffer to the receive chain. * If this fails, the old buffer is recycled * instead. */ if (fxp_add_rfabuf(sc, rxp) == 0) { int total_len; /* * Fetch packet length (the top 2 bits of * actual_size are flags set by the controller * upon completion), and drop the packet in case * of bogus length or CRC errors. */ total_len = le16toh(rfa->actual_size) & 0x3fff; if (total_len < sizeof(struct ether_header) || total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - sc->rfa_size || le16toh(rfa->rfa_status) & FXP_RFA_STATUS_CRC) { m_freem(m); continue; } /* Do IP checksum checking. */ if (le16toh(rfa->rfa_status) & FXP_RFA_STATUS_PARSE) { if (rfa->rfax_csum_sts & FXP_RFDX_CS_IP_CSUM_BIT_VALID) m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; if (rfa->rfax_csum_sts & FXP_RFDX_CS_IP_CSUM_VALID) m->m_pkthdr.csum_flags |= CSUM_IP_VALID; if ((rfa->rfax_csum_sts & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) && (rfa->rfax_csum_sts & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) { m->m_pkthdr.csum_flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR; m->m_pkthdr.csum_data = 0xffff; } } m->m_pkthdr.len = m->m_len = total_len; m->m_pkthdr.rcvif = ifp; /* * Drop locks before calling if_input() since it * may re-enter fxp_start() in the netisr case. * This would result in a lock reversal. Better * performance might be obtained by chaining all * packets received, dropping the lock, and then * calling if_input() on each one. */ FXP_UNLOCK(sc); (*ifp->if_input)(ifp, m); FXP_LOCK(sc); } } if (rnr) { fxp_scb_wait(sc); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); } } /* * Update packet in/out/collision statistics. The i82557 doesn't * allow you to access these counters without doing a fairly * expensive DMA to get _all_ of the statistics it maintains, so * we do this operation here only once per second. The statistics * counters in the kernel are updated from the previous dump-stats * DMA and then a new dump-stats DMA is started. The on-chip * counters are zeroed when the DMA completes. If we can't start * the DMA immediately, we don't wait - we just prepare to read * them again next time. */ static void fxp_tick(void *xsc) { struct fxp_softc *sc = xsc; struct ifnet *ifp = &sc->sc_if; struct fxp_stats *sp = sc->fxp_stats; int s; FXP_LOCK(sc); s = splimp(); bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_POSTREAD); ifp->if_opackets += le32toh(sp->tx_good); ifp->if_collisions += le32toh(sp->tx_total_collisions); if (sp->rx_good) { ifp->if_ipackets += le32toh(sp->rx_good); sc->rx_idle_secs = 0; } else { /* * Receiver's been idle for another second. */ sc->rx_idle_secs++; } ifp->if_ierrors += le32toh(sp->rx_crc_errors) + le32toh(sp->rx_alignment_errors) + le32toh(sp->rx_rnr_errors) + le32toh(sp->rx_overrun_errors); /* * If any transmit underruns occured, bump up the transmit * threshold by another 512 bytes (64 * 8). */ if (sp->tx_underruns) { ifp->if_oerrors += le32toh(sp->tx_underruns); if (tx_threshold < 192) tx_threshold += 64; } /* * Release any xmit buffers that have completed DMA. This isn't * strictly necessary to do here, but it's advantagous for mbufs * with external storage to be released in a timely manner rather * than being defered for a potentially long time. This limits * the delay to a maximum of one second. */ fxp_txeof(sc); /* * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, * then assume the receiver has locked up and attempt to clear * the condition by reprogramming the multicast filter. This is * a work-around for a bug in the 82557 where the receiver locks * up if it gets certain types of garbage in the syncronization * bits prior to the packet header. This bug is supposed to only * occur in 10Mbps mode, but has been seen to occur in 100Mbps * mode as well (perhaps due to a 10/100 speed transition). */ if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { sc->rx_idle_secs = 0; fxp_mc_setup(sc); } /* * If there is no pending command, start another stats * dump. Otherwise punt for now. */ if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { /* * Start another stats dump. */ bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); } else { /* * A previous command is still waiting to be accepted. * Just zero our copy of the stats and wait for the * next timer event to update them. */ sp->tx_good = 0; sp->tx_underruns = 0; sp->tx_total_collisions = 0; sp->rx_good = 0; sp->rx_crc_errors = 0; sp->rx_alignment_errors = 0; sp->rx_rnr_errors = 0; sp->rx_overrun_errors = 0; } if (sc->miibus != NULL) mii_tick(device_get_softc(sc->miibus)); /* * Schedule another timeout one second from now. */ callout_reset(&sc->stat_ch, hz, fxp_tick, sc); FXP_UNLOCK(sc); splx(s); } /* * Stop the interface. Cancels the statistics updater and resets * the interface. */ static void fxp_stop(struct fxp_softc *sc) { struct ifnet *ifp = &sc->sc_if; struct fxp_tx *txp; int i; ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); ifp->if_timer = 0; #ifdef DEVICE_POLLING ether_poll_deregister(ifp); #endif /* * Cancel stats updater. */ callout_stop(&sc->stat_ch); /* * Issue software reset, which also unloads the microcode. */ sc->flags &= ~FXP_FLAG_UCODE; CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); DELAY(50); /* * Release any xmit buffers. */ txp = sc->fxp_desc.tx_list; if (txp != NULL) { for (i = 0; i < FXP_NTXCB; i++) { if (txp[i].tx_mbuf != NULL) { bus_dmamap_sync(sc->fxp_mtag, txp[i].tx_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->fxp_mtag, txp[i].tx_map); m_freem(txp[i].tx_mbuf); txp[i].tx_mbuf = NULL; /* clear this to reset csum offload bits */ txp[i].tx_cb->tbd[0].tb_addr = 0; } } } bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); sc->tx_queued = 0; } /* * Watchdog/transmission transmit timeout handler. Called when a * transmission is started on the interface, but no interrupt is * received before the timeout. This usually indicates that the * card has wedged for some reason. */ static void fxp_watchdog(struct ifnet *ifp) { struct fxp_softc *sc = ifp->if_softc; FXP_LOCK(sc); device_printf(sc->dev, "device timeout\n"); ifp->if_oerrors++; fxp_init_body(sc); FXP_UNLOCK(sc); } /* * Acquire locks and then call the real initialization function. This * is necessary because ether_ioctl() calls if_init() and this would * result in mutex recursion if the mutex was held. */ static void fxp_init(void *xsc) { struct fxp_softc *sc = xsc; FXP_LOCK(sc); fxp_init_body(sc); FXP_UNLOCK(sc); } /* * Perform device initialization. This routine must be called with the * softc lock held. */ static void fxp_init_body(struct fxp_softc *sc) { struct ifnet *ifp = &sc->sc_if; struct fxp_cb_config *cbp; struct fxp_cb_ias *cb_ias; struct fxp_cb_tx *tcbp; struct fxp_tx *txp; struct fxp_cb_mcs *mcsp; int i, prm, s; mtx_assert(&sc->sc_mtx, MA_OWNED); s = splimp(); /* * Cancel any pending I/O */ fxp_stop(sc); prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; /* * Initialize base of CBL and RFA memory. Loading with zero * sets it up for regular linear addressing. */ CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); fxp_scb_wait(sc); fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); /* * Initialize base of dump-stats buffer. */ fxp_scb_wait(sc); bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap, BUS_DMASYNC_PREREAD); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); /* * Attempt to load microcode if requested. */ if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) fxp_load_ucode(sc); /* * Initialize the multicast address list. */ if (fxp_mc_addrs(sc)) { mcsp = sc->mcsp; mcsp->cb_status = 0; mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL); mcsp->link_addr = 0xffffffff; /* * Start the multicast setup command. */ fxp_scb_wait(sc); bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* ...and wait for it to complete. */ fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map); bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_POSTWRITE); } /* * We temporarily use memory that contains the TxCB list to * construct the config CB. The TxCB list memory is rebuilt * later. */ cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list; /* * This bcopy is kind of disgusting, but there are a bunch of must be * zero and must be one bits in this structure and this is the easiest * way to initialize them all to proper values. */ bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template)); cbp->cb_status = 0; cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL); cbp->link_addr = 0xffffffff; /* (no) next command */ cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22; cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; cbp->type_enable = 0; /* actually reserved */ cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ cbp->dma_mbce = 0; /* (disable) dma max counters */ cbp->late_scb = 0; /* (don't) defer SCB update */ cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ cbp->ci_int = 1; /* interrupt on CU idle */ cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; cbp->ext_stats_dis = 1; /* disable extended counters */ cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; cbp->disc_short_rx = !prm; /* discard short packets */ cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; cbp->csma_dis = 0; /* (don't) disable link */ cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ cbp->nsai = 1; /* (don't) disable source addr insert */ cbp->preamble_length = 2; /* (7 byte) preamble */ cbp->loopback = 0; /* (don't) loopback */ cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ cbp->linear_pri_mode = 0; /* (wait after xmit only) */ cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ cbp->promiscuous = prm; /* promiscuous mode */ cbp->bcast_disable = 0; /* (don't) disable broadcasts */ cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; cbp->stripping = !prm; /* truncate rx packet to byte count */ cbp->padding = 1; /* (do) pad short tx packets */ cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; cbp->ia_wake_en = 0; /* (don't) wake up on address match */ cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ /* must set wake_en in PMCSR also */ cbp->force_fdx = 0; /* (don't) force full duplex */ cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ cbp->multi_ia = 0; /* (don't) accept multiple IAs */ cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0; if (fxp_noflow || sc->revision == FXP_REV_82557) { /* * The 82557 has no hardware flow control, the values * below are the defaults for the chip. */ cbp->fc_delay_lsb = 0; cbp->fc_delay_msb = 0x40; cbp->pri_fc_thresh = 3; cbp->tx_fc_dis = 0; cbp->rx_fc_restop = 0; cbp->rx_fc_restart = 0; cbp->fc_filter = 0; cbp->pri_fc_loc = 1; } else { cbp->fc_delay_lsb = 0x1f; cbp->fc_delay_msb = 0x01; cbp->pri_fc_thresh = 3; cbp->tx_fc_dis = 0; /* enable transmit FC */ cbp->rx_fc_restop = 1; /* enable FC restop frames */ cbp->rx_fc_restart = 1; /* enable FC restart frames */ cbp->fc_filter = !prm; /* drop FC frames to host */ cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ } /* * Start the config command/DMA. */ fxp_scb_wait(sc); bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* ...and wait for it to complete. */ fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); /* * Now initialize the station address. Temporarily use the TxCB * memory area like we did above for the config CB. */ cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list; cb_ias->cb_status = 0; cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL); cb_ias->link_addr = 0xffffffff; bcopy(sc->arpcom.ac_enaddr, cb_ias->macaddr, sizeof(sc->arpcom.ac_enaddr)); /* * Start the IAS (Individual Address Setup) command/DMA. */ fxp_scb_wait(sc); bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* ...and wait for it to complete. */ fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map); bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); /* * Initialize transmit control block (TxCB) list. */ txp = sc->fxp_desc.tx_list; tcbp = sc->fxp_desc.cbl_list; bzero(tcbp, FXP_TXCB_SZ); for (i = 0; i < FXP_NTXCB; i++) { txp[i].tx_cb = tcbp + i; txp[i].tx_mbuf = NULL; tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK); tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP); tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr + (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx))); if (sc->flags & FXP_FLAG_EXT_TXCB) tcbp[i].tbd_array_addr = htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2])); else tcbp[i].tbd_array_addr = htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0])); txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK]; } /* * Set the suspend flag on the first TxCB and start the control * unit. It will execute the NOP and then suspend. */ tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S); bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; sc->tx_queued = 1; fxp_scb_wait(sc); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* * Initialize receiver buffer area - RFA. */ fxp_scb_wait(sc); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); /* * Set current media. */ if (sc->miibus != NULL) mii_mediachg(device_get_softc(sc->miibus)); ifp->if_flags |= IFF_RUNNING; ifp->if_flags &= ~IFF_OACTIVE; /* * Enable interrupts. */ #ifdef DEVICE_POLLING /* * ... but only do that if we are not polling. And because (presumably) * the default is interrupts on, we need to disable them explicitly! */ if ( ifp->if_flags & IFF_POLLING ) CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); else #endif /* DEVICE_POLLING */ CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); /* * Start stats updater. */ callout_reset(&sc->stat_ch, hz, fxp_tick, sc); splx(s); } static int fxp_serial_ifmedia_upd(struct ifnet *ifp) { return (0); } static void fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; } /* * Change media according to request. */ static int fxp_ifmedia_upd(struct ifnet *ifp) { struct fxp_softc *sc = ifp->if_softc; struct mii_data *mii; mii = device_get_softc(sc->miibus); mii_mediachg(mii); return (0); } /* * Notify the world which media we're using. */ static void fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct fxp_softc *sc = ifp->if_softc; struct mii_data *mii; mii = device_get_softc(sc->miibus); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) sc->cu_resume_bug = 1; else sc->cu_resume_bug = 0; } /* * Add a buffer to the end of the RFA buffer list. * Return 0 if successful, 1 for failure. A failure results in * adding the 'oldm' (if non-NULL) on to the end of the list - * tossing out its old contents and recycling it. * The RFA struct is stuck at the beginning of mbuf cluster and the * data pointer is fixed up to point just past it. */ static int fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp) { struct mbuf *m; struct fxp_rfa *rfa, *p_rfa; struct fxp_rx *p_rx; bus_dmamap_t tmp_map; int error; m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return (ENOBUFS); /* * Move the data pointer up so that the incoming data packet * will be 32-bit aligned. */ m->m_data += RFA_ALIGNMENT_FUDGE; /* * Get a pointer to the base of the mbuf cluster and move * data start past it. */ rfa = mtod(m, struct fxp_rfa *); m->m_data += sc->rfa_size; rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE); rfa->rfa_status = 0; rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL); rfa->actual_size = 0; /* * Initialize the rest of the RFA. Note that since the RFA * is misaligned, we cannot store values directly. We're thus * using the le32enc() function which handles endianness and * is also alignment-safe. */ le32enc(&rfa->link_addr, 0xffffffff); le32enc(&rfa->rbd_addr, 0xffffffff); /* Map the RFA into DMA memory. */ error = bus_dmamap_load(sc->fxp_mtag, sc->spare_map, rfa, MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr, &rxp->rx_addr, 0); if (error) { m_freem(m); return (error); } bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); tmp_map = sc->spare_map; sc->spare_map = rxp->rx_map; rxp->rx_map = tmp_map; rxp->rx_mbuf = m; bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* * If there are other buffers already on the list, attach this * one to the end by fixing up the tail to point to this one. */ if (sc->fxp_desc.rx_head != NULL) { p_rx = sc->fxp_desc.rx_tail; p_rfa = (struct fxp_rfa *) (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE); p_rx->rx_next = rxp; le32enc(&p_rfa->link_addr, rxp->rx_addr); p_rfa->rfa_control = 0; bus_dmamap_sync(sc->fxp_mtag, p_rx->rx_map, BUS_DMASYNC_PREWRITE); } else { rxp->rx_next = NULL; sc->fxp_desc.rx_head = rxp; } sc->fxp_desc.rx_tail = rxp; return (0); } static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg) { struct fxp_softc *sc = device_get_softc(dev); int count = 10000; int value; CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 && count--) DELAY(10); if (count <= 0) device_printf(dev, "fxp_miibus_readreg: timed out\n"); return (value & 0xffff); } static void fxp_miibus_writereg(device_t dev, int phy, int reg, int value) { struct fxp_softc *sc = device_get_softc(dev); int count = 10000; CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | (value & 0xffff)); while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && count--) DELAY(10); if (count <= 0) device_printf(dev, "fxp_miibus_writereg: timed out\n"); } static int fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) { struct fxp_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *)data; struct mii_data *mii; int s, error = 0; /* * Detaching causes us to call ioctl with the mutex owned. Preclude * that by saying we're busy if the lock is already held. */ if (mtx_owned(&sc->sc_mtx)) return (EBUSY); FXP_LOCK(sc); s = splimp(); switch (command) { case SIOCSIFFLAGS: if (ifp->if_flags & IFF_ALLMULTI) sc->flags |= FXP_FLAG_ALL_MCAST; else sc->flags &= ~FXP_FLAG_ALL_MCAST; /* * If interface is marked up and not running, then start it. * If it is marked down and running, stop it. * XXX If it's up then re-initialize it. This is so flags * such as IFF_PROMISC are handled. */ if (ifp->if_flags & IFF_UP) { fxp_init_body(sc); } else { if (ifp->if_flags & IFF_RUNNING) fxp_stop(sc); } break; case SIOCADDMULTI: case SIOCDELMULTI: if (ifp->if_flags & IFF_ALLMULTI) sc->flags |= FXP_FLAG_ALL_MCAST; else sc->flags &= ~FXP_FLAG_ALL_MCAST; /* * Multicast list has changed; set the hardware filter * accordingly. */ if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) fxp_mc_setup(sc); /* * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it * again rather than else {}. */ if (sc->flags & FXP_FLAG_ALL_MCAST) fxp_init_body(sc); error = 0; break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: if (sc->miibus != NULL) { mii = device_get_softc(sc->miibus); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); } else { error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); } break; default: /* * ether_ioctl() will eventually call fxp_start() which * will result in mutex recursion so drop it first. */ FXP_UNLOCK(sc); error = ether_ioctl(ifp, command, data); } if (mtx_owned(&sc->sc_mtx)) FXP_UNLOCK(sc); splx(s); return (error); } /* * Fill in the multicast address list and return number of entries. */ static int fxp_mc_addrs(struct fxp_softc *sc) { struct fxp_cb_mcs *mcsp = sc->mcsp; struct ifnet *ifp = &sc->sc_if; struct ifmultiaddr *ifma; int nmcasts; nmcasts = 0; if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { #if __FreeBSD_version < 500000 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { #else TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { #endif if (ifma->ifma_addr->sa_family != AF_LINK) continue; if (nmcasts >= MAXMCADDR) { sc->flags |= FXP_FLAG_ALL_MCAST; nmcasts = 0; break; } bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), &sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN); nmcasts++; } } mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN); return (nmcasts); } /* * Program the multicast filter. * * We have an artificial restriction that the multicast setup command * must be the first command in the chain, so we take steps to ensure * this. By requiring this, it allows us to keep up the performance of * the pre-initialized command ring (esp. link pointers) by not actually * inserting the mcsetup command in the ring - i.e. its link pointer * points to the TxCB ring, but the mcsetup descriptor itself is not part * of it. We then can do 'CU_START' on the mcsetup descriptor and have it * lead into the regular TxCB ring when it completes. * * This function must be called at splimp. */ static void fxp_mc_setup(struct fxp_softc *sc) { struct fxp_cb_mcs *mcsp = sc->mcsp; struct ifnet *ifp = &sc->sc_if; struct fxp_tx *txp; int count; /* * If there are queued commands, we must wait until they are all * completed. If we are already waiting, then add a NOP command * with interrupt option so that we're notified when all commands * have been completed - fxp_start() ensures that no additional * TX commands will be added when need_mcsetup is true. */ if (sc->tx_queued) { /* * need_mcsetup will be true if we are already waiting for the * NOP command to be completed (see below). In this case, bail. */ if (sc->need_mcsetup) return; sc->need_mcsetup = 1; /* * Add a NOP command with interrupt so that we are notified * when all TX commands have been processed. */ txp = sc->fxp_desc.tx_last->tx_next; txp->tx_mbuf = NULL; txp->tx_cb->cb_status = 0; txp->tx_cb->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); /* * Advance the end of list forward. */ sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S); bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); sc->fxp_desc.tx_last = txp; sc->tx_queued++; /* * Issue a resume in case the CU has just suspended. */ fxp_scb_wait(sc); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); /* * Set a 5 second timer just in case we don't hear from the * card again. */ ifp->if_timer = 5; return; } sc->need_mcsetup = 0; /* * Initialize multicast setup descriptor. */ mcsp->cb_status = 0; mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I); mcsp->link_addr = htole32(sc->fxp_desc.cbl_addr); txp = &sc->fxp_desc.mcs_tx; txp->tx_mbuf = NULL; txp->tx_cb = (struct fxp_cb_tx *)sc->mcsp; txp->tx_next = sc->fxp_desc.tx_list; (void) fxp_mc_addrs(sc); sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp; sc->tx_queued = 1; /* * Wait until command unit is not active. This should never * be the case when nothing is queued, but make sure anyway. */ count = 100; while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == FXP_SCB_CUS_ACTIVE && --count) DELAY(10); if (count == 0) { device_printf(sc->dev, "command queue timeout\n"); return; } /* * Start the multicast setup command. */ fxp_scb_wait(sc); bus_dmamap_sync(sc->mcs_tag, sc->mcs_map, BUS_DMASYNC_PREWRITE); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); ifp->if_timer = 2; return; } static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; #define UCODE(x) x, sizeof(x) struct ucode { u_int32_t revision; u_int32_t *ucode; int length; u_short int_delay_offset; u_short bundle_max_offset; } ucode_table[] = { { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, { FXP_REV_82550, UCODE(fxp_ucode_d102), D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, { 0, NULL, 0, 0, 0 } }; static void fxp_load_ucode(struct fxp_softc *sc) { struct ucode *uc; struct fxp_cb_ucode *cbp; for (uc = ucode_table; uc->ucode != NULL; uc++) if (sc->revision == uc->revision) break; if (uc->ucode == NULL) return; cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list; cbp->cb_status = 0; cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL); cbp->link_addr = 0xffffffff; /* (no) next command */ memcpy(cbp->ucode, uc->ucode, uc->length); if (uc->int_delay_offset) *(u_int16_t *)&cbp->ucode[uc->int_delay_offset] = htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2); if (uc->bundle_max_offset) *(u_int16_t *)&cbp->ucode[uc->bundle_max_offset] = htole16(sc->tunable_bundle_max); /* * Download the ucode to the chip. */ fxp_scb_wait(sc); bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_PREWRITE); CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr); fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); /* ...and wait for it to complete. */ fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map); bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE); device_printf(sc->dev, "Microcode loaded, int_delay: %d usec bundle_max: %d\n", sc->tunable_int_delay, uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); sc->flags |= FXP_FLAG_UCODE; } static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) { int error, value; value = *(int *)arg1; error = sysctl_handle_int(oidp, &value, 0, req); if (error || !req->newptr) return (error); if (value < low || value > high) return (EINVAL); *(int *)arg1 = value; return (0); } /* * Interrupt delay is expressed in microseconds, a multiplier is used * to convert this to the appropriate clock ticks before using. */ static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); } static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) { return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); } Index: head/sys/dev/wi/if_wi.c =================================================================== --- head/sys/dev/wi/if_wi.c (revision 121696) +++ head/sys/dev/wi/if_wi.c (revision 121697) @@ -1,3158 +1,3158 @@ /* $NetBSD: wi.c,v 1.109 2003/01/09 08:52:19 dyoung Exp $ */ /* * Copyright (c) 1997, 1998, 1999 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ /* * Lucent WaveLAN/IEEE 802.11 PCMCIA driver. * * Original FreeBSD driver written by Bill Paul * Electrical Engineering Department * Columbia University, New York City */ /* * The WaveLAN/IEEE adapter is the second generation of the WaveLAN * from Lucent. Unlike the older cards, the new ones are programmed * entirely via a firmware-driven controller called the Hermes. * Unfortunately, Lucent will not release the Hermes programming manual * without an NDA (if at all). What they do release is an API library * called the HCF (Hardware Control Functions) which is supposed to * do the device-specific operations of a device driver for you. The * publically available version of the HCF library (the 'HCF Light') is * a) extremely gross, b) lacks certain features, particularly support * for 802.11 frames, and c) is contaminated by the GNU Public License. * * This driver does not use the HCF or HCF Light at all. Instead, it * programs the Hermes controller directly, using information gleaned * from the HCF Light code and corresponding documentation. * * This driver supports the ISA, PCMCIA and PCI versions of the Lucent * WaveLan cards (based on the Hermes chipset), as well as the newer * Prism 2 chipsets with firmware from Intersil and Symbol. */ #include __FBSDID("$FreeBSD$"); #define WI_HERMES_AUTOINC_WAR /* Work around data write autoinc bug. */ #define WI_HERMES_STATS_WAR /* Work around stats counter bug. */ #define NBPFILTER 1 #include #include #if __FreeBSD_version >= 500033 #include #endif #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define IF_POLL(ifq, m) ((m) = (ifq)->ifq_head) #define IFQ_POLL(ifq, m) IF_POLL((ifq), (m)) #define IFQ_DEQUEUE(ifq, m) IF_DEQUEUE((ifq), (m)) static void wi_start(struct ifnet *); static int wi_reset(struct wi_softc *); static void wi_watchdog(struct ifnet *); static int wi_ioctl(struct ifnet *, u_long, caddr_t); static int wi_media_change(struct ifnet *); static void wi_media_status(struct ifnet *, struct ifmediareq *); static void wi_rx_intr(struct wi_softc *); static void wi_tx_intr(struct wi_softc *); static void wi_tx_ex_intr(struct wi_softc *); static void wi_info_intr(struct wi_softc *); static int wi_get_cfg(struct ifnet *, u_long, caddr_t); static int wi_set_cfg(struct ifnet *, u_long, caddr_t); static int wi_write_txrate(struct wi_softc *); static int wi_write_wep(struct wi_softc *); static int wi_write_multi(struct wi_softc *); static int wi_alloc_fid(struct wi_softc *, int, int *); static void wi_read_nicid(struct wi_softc *); static int wi_write_ssid(struct wi_softc *, int, u_int8_t *, int); static int wi_cmd(struct wi_softc *, int, int, int, int); static int wi_seek_bap(struct wi_softc *, int, int); static int wi_read_bap(struct wi_softc *, int, int, void *, int); static int wi_write_bap(struct wi_softc *, int, int, void *, int); static int wi_mwrite_bap(struct wi_softc *, int, int, struct mbuf *, int); static int wi_read_rid(struct wi_softc *, int, void *, int *); static int wi_write_rid(struct wi_softc *, int, void *, int); static int wi_newstate(struct ieee80211com *, enum ieee80211_state, int); static int wi_scan_ap(struct wi_softc *, u_int16_t, u_int16_t); static void wi_scan_result(struct wi_softc *, int, int); static void wi_dump_pkt(struct wi_frame *, struct ieee80211_node *, int rssi); static int wi_get_debug(struct wi_softc *, struct wi_req *); static int wi_set_debug(struct wi_softc *, struct wi_req *); #if __FreeBSD_version >= 500000 /* support to download firmware for symbol CF card */ static int wi_symbol_write_firm(struct wi_softc *, const void *, int, const void *, int); static int wi_symbol_set_hcr(struct wi_softc *, int); #endif static __inline int wi_write_val(struct wi_softc *sc, int rid, u_int16_t val) { val = htole16(val); return wi_write_rid(sc, rid, &val, sizeof(val)); } SYSCTL_NODE(_hw, OID_AUTO, wi, CTLFLAG_RD, 0, "Wireless driver parameters"); static struct timeval lasttxerror; /* time of last tx error msg */ static int curtxeps; /* current tx error msgs/sec */ static int wi_txerate = 0; /* tx error rate: max msgs/sec */ SYSCTL_INT(_hw_wi, OID_AUTO, txerate, CTLFLAG_RW, &wi_txerate, 0, "max tx error msgs/sec; 0 to disable msgs"); #define WI_DEBUG #ifdef WI_DEBUG static int wi_debug = 0; SYSCTL_INT(_hw_wi, OID_AUTO, debug, CTLFLAG_RW, &wi_debug, 0, "control debugging printfs"); #define DPRINTF(X) if (wi_debug) printf X #define DPRINTF2(X) if (wi_debug > 1) printf X #define IFF_DUMPPKTS(_ifp) \ (((_ifp)->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) #else #define DPRINTF(X) #define DPRINTF2(X) #define IFF_DUMPPKTS(_ifp) 0 #endif #define WI_INTRS (WI_EV_RX | WI_EV_ALLOC | WI_EV_INFO) struct wi_card_ident wi_card_ident[] = { /* CARD_ID CARD_NAME FIRM_TYPE */ { WI_NIC_LUCENT_ID, WI_NIC_LUCENT_STR, WI_LUCENT }, { WI_NIC_SONY_ID, WI_NIC_SONY_STR, WI_LUCENT }, { WI_NIC_LUCENT_EMB_ID, WI_NIC_LUCENT_EMB_STR, WI_LUCENT }, { WI_NIC_EVB2_ID, WI_NIC_EVB2_STR, WI_INTERSIL }, { WI_NIC_HWB3763_ID, WI_NIC_HWB3763_STR, WI_INTERSIL }, { WI_NIC_HWB3163_ID, WI_NIC_HWB3163_STR, WI_INTERSIL }, { WI_NIC_HWB3163B_ID, WI_NIC_HWB3163B_STR, WI_INTERSIL }, { WI_NIC_EVB3_ID, WI_NIC_EVB3_STR, WI_INTERSIL }, { WI_NIC_HWB1153_ID, WI_NIC_HWB1153_STR, WI_INTERSIL }, { WI_NIC_P2_SST_ID, WI_NIC_P2_SST_STR, WI_INTERSIL }, { WI_NIC_EVB2_SST_ID, WI_NIC_EVB2_SST_STR, WI_INTERSIL }, { WI_NIC_3842_EVA_ID, WI_NIC_3842_EVA_STR, WI_INTERSIL }, { WI_NIC_3842_PCMCIA_AMD_ID, WI_NIC_3842_PCMCIA_STR, WI_INTERSIL }, { WI_NIC_3842_PCMCIA_SST_ID, WI_NIC_3842_PCMCIA_STR, WI_INTERSIL }, { WI_NIC_3842_PCMCIA_ATL_ID, WI_NIC_3842_PCMCIA_STR, WI_INTERSIL }, { WI_NIC_3842_PCMCIA_ATS_ID, WI_NIC_3842_PCMCIA_STR, WI_INTERSIL }, { WI_NIC_3842_MINI_AMD_ID, WI_NIC_3842_MINI_STR, WI_INTERSIL }, { WI_NIC_3842_MINI_SST_ID, WI_NIC_3842_MINI_STR, WI_INTERSIL }, { WI_NIC_3842_MINI_ATL_ID, WI_NIC_3842_MINI_STR, WI_INTERSIL }, { WI_NIC_3842_MINI_ATS_ID, WI_NIC_3842_MINI_STR, WI_INTERSIL }, { WI_NIC_3842_PCI_AMD_ID, WI_NIC_3842_PCI_STR, WI_INTERSIL }, { WI_NIC_3842_PCI_SST_ID, WI_NIC_3842_PCI_STR, WI_INTERSIL }, { WI_NIC_3842_PCI_ATS_ID, WI_NIC_3842_PCI_STR, WI_INTERSIL }, { WI_NIC_3842_PCI_ATL_ID, WI_NIC_3842_PCI_STR, WI_INTERSIL }, { WI_NIC_P3_PCMCIA_AMD_ID, WI_NIC_P3_PCMCIA_STR, WI_INTERSIL }, { WI_NIC_P3_PCMCIA_SST_ID, WI_NIC_P3_PCMCIA_STR, WI_INTERSIL }, { WI_NIC_P3_PCMCIA_ATL_ID, WI_NIC_P3_PCMCIA_STR, WI_INTERSIL }, { WI_NIC_P3_PCMCIA_ATS_ID, WI_NIC_P3_PCMCIA_STR, WI_INTERSIL }, { WI_NIC_P3_MINI_AMD_ID, WI_NIC_P3_MINI_STR, WI_INTERSIL }, { WI_NIC_P3_MINI_SST_ID, WI_NIC_P3_MINI_STR, WI_INTERSIL }, { WI_NIC_P3_MINI_ATL_ID, WI_NIC_P3_MINI_STR, WI_INTERSIL }, { WI_NIC_P3_MINI_ATS_ID, WI_NIC_P3_MINI_STR, WI_INTERSIL }, { 0, NULL, 0 }, }; devclass_t wi_devclass; int wi_attach(device_t dev) { struct wi_softc *sc = device_get_softc(dev); struct ieee80211com *ic = &sc->sc_ic; struct ifnet *ifp = &ic->ic_if; int i, nrates, buflen; u_int16_t val; u_int8_t ratebuf[2 + IEEE80211_RATE_SIZE]; struct ieee80211_rateset *rs; static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; int error; /* * NB: no locking is needed here; don't put it here * unless you can prove it! */ - error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, + error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, wi_intr, sc, &sc->wi_intrhand); if (error) { device_printf(dev, "bus_setup_intr() failed! (%d)\n", error); wi_free(dev); return (error); } #if __FreeBSD_version >= 500000 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE); #endif /* Reset the NIC. */ if (wi_reset(sc) != 0) return ENXIO; /* XXX */ /* * Read the station address. * And do it twice. I've seen PRISM-based cards that return * an error when trying to read it the first time, which causes * the probe to fail. */ buflen = IEEE80211_ADDR_LEN; error = wi_read_rid(sc, WI_RID_MAC_NODE, ic->ic_myaddr, &buflen); if (error != 0) { buflen = IEEE80211_ADDR_LEN; error = wi_read_rid(sc, WI_RID_MAC_NODE, ic->ic_myaddr, &buflen); } if (error || IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { if (error != 0) device_printf(dev, "mac read failed %d\n", error); else device_printf(dev, "mac read failed (all zeros)\n"); wi_free(dev); return (error); } device_printf(dev, "802.11 address: %6D\n", ic->ic_myaddr, ":"); /* Read NIC identification */ wi_read_nicid(sc); ifp->if_softc = sc; ifp->if_unit = sc->sc_unit; ifp->if_name = "wi"; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = wi_ioctl; ifp->if_start = wi_start; ifp->if_watchdog = wi_watchdog; ifp->if_init = wi_init; ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; ic->ic_phytype = IEEE80211_T_DS; ic->ic_opmode = IEEE80211_M_STA; ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_AHDEMO; ic->ic_state = IEEE80211_S_INIT; /* * Query the card for available channels and setup the * channel table. We assume these are all 11b channels. */ buflen = sizeof(val); if (wi_read_rid(sc, WI_RID_CHANNEL_LIST, &val, &buflen) != 0) val = htole16(0x1fff); /* assume 1-11 */ KASSERT(val != 0, ("wi_attach: no available channels listed!")); val <<= 1; /* shift for base 1 indices */ for (i = 1; i < 16; i++) { if (isset((u_int8_t*)&val, i)) { ic->ic_channels[i].ic_freq = ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; } } /* * Read the default channel from the NIC. This may vary * depending on the country where the NIC was purchased, so * we can't hard-code a default and expect it to work for * everyone. * * If no channel is specified, let the 802.11 code select. */ buflen = sizeof(val); if (wi_read_rid(sc, WI_RID_OWN_CHNL, &val, &buflen) == 0) { val = le16toh(val); KASSERT(val < IEEE80211_CHAN_MAX && ic->ic_channels[val].ic_flags != 0, ("wi_attach: invalid own channel %u!", val)); ic->ic_ibss_chan = &ic->ic_channels[val]; } else { device_printf(dev, "WI_RID_OWN_CHNL failed, using first channel!\n"); ic->ic_ibss_chan = &ic->ic_channels[0]; } /* * Set flags based on firmware version. */ switch (sc->sc_firmware_type) { case WI_LUCENT: sc->sc_ntxbuf = 1; sc->sc_flags |= WI_FLAGS_HAS_SYSSCALE; #ifdef WI_HERMES_AUTOINC_WAR /* XXX: not confirmed, but never seen for recent firmware */ if (sc->sc_sta_firmware_ver < 40000) { sc->sc_flags |= WI_FLAGS_BUG_AUTOINC; } #endif if (sc->sc_sta_firmware_ver >= 60000) sc->sc_flags |= WI_FLAGS_HAS_MOR; if (sc->sc_sta_firmware_ver >= 60006) { ic->ic_caps |= IEEE80211_C_IBSS; ic->ic_caps |= IEEE80211_C_MONITOR; } sc->sc_ibss_port = htole16(1); sc->sc_min_rssi = WI_LUCENT_MIN_RSSI; sc->sc_max_rssi = WI_LUCENT_MAX_RSSI; sc->sc_dbm_offset = WI_LUCENT_DBM_OFFSET; break; case WI_INTERSIL: sc->sc_ntxbuf = WI_NTXBUF; sc->sc_flags |= WI_FLAGS_HAS_FRAGTHR; sc->sc_flags |= WI_FLAGS_HAS_ROAMING; sc->sc_flags |= WI_FLAGS_HAS_SYSSCALE; if (sc->sc_sta_firmware_ver > 10101) sc->sc_flags |= WI_FLAGS_HAS_DBMADJUST; if (sc->sc_sta_firmware_ver >= 800) { ic->ic_caps |= IEEE80211_C_IBSS; ic->ic_caps |= IEEE80211_C_MONITOR; } /* * version 0.8.3 and newer are the only ones that are known * to currently work. Earlier versions can be made to work, * at least according to the Linux driver. */ if (sc->sc_sta_firmware_ver >= 803) ic->ic_caps |= IEEE80211_C_HOSTAP; sc->sc_ibss_port = htole16(0); sc->sc_min_rssi = WI_PRISM_MIN_RSSI; sc->sc_max_rssi = WI_PRISM_MAX_RSSI; sc->sc_dbm_offset = WI_PRISM_DBM_OFFSET; break; case WI_SYMBOL: sc->sc_ntxbuf = 1; sc->sc_flags |= WI_FLAGS_HAS_DIVERSITY; if (sc->sc_sta_firmware_ver >= 25000) ic->ic_caps |= IEEE80211_C_IBSS; sc->sc_ibss_port = htole16(4); sc->sc_min_rssi = WI_PRISM_MIN_RSSI; sc->sc_max_rssi = WI_PRISM_MAX_RSSI; sc->sc_dbm_offset = WI_PRISM_DBM_OFFSET; break; } /* * Find out if we support WEP on this card. */ buflen = sizeof(val); if (wi_read_rid(sc, WI_RID_WEP_AVAIL, &val, &buflen) == 0 && val != htole16(0)) ic->ic_caps |= IEEE80211_C_WEP; /* Find supported rates. */ buflen = sizeof(ratebuf); rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; if (wi_read_rid(sc, WI_RID_DATA_RATES, ratebuf, &buflen) == 0) { nrates = le16toh(*(u_int16_t *)ratebuf); if (nrates > IEEE80211_RATE_MAXSIZE) nrates = IEEE80211_RATE_MAXSIZE; rs->rs_nrates = 0; for (i = 0; i < nrates; i++) if (ratebuf[2+i]) rs->rs_rates[rs->rs_nrates++] = ratebuf[2+i]; } else { /* XXX fallback on error? */ rs->rs_nrates = 0; } buflen = sizeof(val); if ((sc->sc_flags & WI_FLAGS_HAS_DBMADJUST) && wi_read_rid(sc, WI_RID_DBM_ADJUST, &val, &buflen) == 0) { sc->sc_dbm_offset = le16toh(val); } sc->sc_max_datalen = 2304; sc->sc_system_scale = 1; sc->sc_cnfauthmode = IEEE80211_AUTH_OPEN; sc->sc_roaming_mode = 1; sc->sc_portnum = WI_DEFAULT_PORT; sc->sc_authtype = WI_DEFAULT_AUTHTYPE; bzero(sc->sc_nodename, sizeof(sc->sc_nodename)); sc->sc_nodelen = sizeof(WI_DEFAULT_NODENAME) - 1; bcopy(WI_DEFAULT_NODENAME, sc->sc_nodename, sc->sc_nodelen); bzero(sc->sc_net_name, sizeof(sc->sc_net_name)); bcopy(WI_DEFAULT_NETNAME, sc->sc_net_name, sizeof(WI_DEFAULT_NETNAME) - 1); /* * Call MI attach routine. */ ieee80211_ifattach(ifp); /* override state transition method */ sc->sc_newstate = ic->ic_newstate; ic->ic_newstate = wi_newstate; ieee80211_media_init(ifp, wi_media_change, wi_media_status); #if NBPFILTER > 0 bpfattach2(ifp, DLT_IEEE802_11_RADIO, sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), &sc->sc_drvbpf); /* * Initialize constant fields. * * NB: the channel is setup each time we transition to the * RUN state to avoid filling it in for each frame. */ sc->sc_tx_th.wt_ihdr.it_len = sizeof(sc->sc_tx_th); sc->sc_tx_th.wt_ihdr.it_present = WI_TX_RADIOTAP_PRESENT; sc->sc_rx_th.wr_ihdr.it_len = sizeof(sc->sc_rx_th); sc->sc_rx_th.wr_ihdr.it_present = WI_RX_RADIOTAP_PRESENT0; sc->sc_rx_th.wr_present1 = WI_RX_RADIOTAP_PRESENT1; #endif return (0); } int wi_detach(device_t dev) { struct wi_softc *sc = device_get_softc(dev); struct ifnet *ifp = &sc->sc_ic.ic_if; WI_LOCK_DECL(); WI_LOCK(sc); /* check if device was removed */ sc->wi_gone = !bus_child_present(dev); wi_stop(ifp, 0); #if NBPFILTER > 0 bpfdetach(ifp); #endif ieee80211_ifdetach(ifp); WI_UNLOCK(sc); bus_teardown_intr(dev, sc->irq, sc->wi_intrhand); wi_free(dev); #if __FreeBSD_version >= 500000 mtx_destroy(&sc->sc_mtx); #endif return (0); } #ifdef __NetBSD__ int wi_activate(struct device *self, enum devact act) { struct wi_softc *sc = (struct wi_softc *)self; int rv = 0, s; s = splnet(); switch (act) { case DVACT_ACTIVATE: rv = EOPNOTSUPP; break; case DVACT_DEACTIVATE: if_deactivate(&sc->sc_ic.ic_if); break; } splx(s); return rv; } void wi_power(struct wi_softc *sc, int why) { struct ifnet *ifp = &sc->sc_ic.ic_if; int s; s = splnet(); switch (why) { case PWR_SUSPEND: case PWR_STANDBY: wi_stop(ifp, 1); break; case PWR_RESUME: if (ifp->if_flags & IFF_UP) { wi_init(ifp); (void)wi_intr(sc); } break; case PWR_SOFTSUSPEND: case PWR_SOFTSTANDBY: case PWR_SOFTRESUME: break; } splx(s); } #endif /* __NetBSD__ */ void wi_shutdown(device_t dev) { struct wi_softc *sc = device_get_softc(dev); wi_stop(&sc->sc_if, 1); } void wi_intr(void *arg) { struct wi_softc *sc = arg; struct ifnet *ifp = &sc->sc_ic.ic_if; u_int16_t status; WI_LOCK_DECL(); WI_LOCK(sc); if (sc->wi_gone || (ifp->if_flags & IFF_UP) == 0) { CSR_WRITE_2(sc, WI_INT_EN, 0); CSR_WRITE_2(sc, WI_EVENT_ACK, ~0); WI_UNLOCK(sc); return; } /* Disable interrupts. */ CSR_WRITE_2(sc, WI_INT_EN, 0); status = CSR_READ_2(sc, WI_EVENT_STAT); if (status & WI_EV_RX) wi_rx_intr(sc); if (status & WI_EV_ALLOC) wi_tx_intr(sc); if (status & WI_EV_TX_EXC) wi_tx_ex_intr(sc); if (status & WI_EV_INFO) wi_info_intr(sc); if ((ifp->if_flags & IFF_OACTIVE) == 0 && (sc->sc_flags & WI_FLAGS_OUTRANGE) == 0 && _IF_QLEN(&ifp->if_snd) != 0) wi_start(ifp); /* Re-enable interrupts. */ CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS); WI_UNLOCK(sc); return; } void wi_init(void *arg) { struct wi_softc *sc = arg; struct ifnet *ifp = &sc->sc_if; struct ieee80211com *ic = &sc->sc_ic; struct wi_joinreq join; int i; int error = 0, wasenabled; struct ifaddr *ifa; struct sockaddr_dl *sdl; WI_LOCK_DECL(); WI_LOCK(sc); if (sc->wi_gone) { WI_UNLOCK(sc); return; } if ((wasenabled = sc->sc_enabled)) wi_stop(ifp, 0); wi_reset(sc); /* common 802.11 configuration */ ic->ic_flags &= ~IEEE80211_F_IBSSON; sc->sc_flags &= ~WI_FLAGS_OUTRANGE; switch (ic->ic_opmode) { case IEEE80211_M_STA: wi_write_val(sc, WI_RID_PORTTYPE, WI_PORTTYPE_BSS); break; case IEEE80211_M_IBSS: wi_write_val(sc, WI_RID_PORTTYPE, sc->sc_ibss_port); ic->ic_flags |= IEEE80211_F_IBSSON; break; case IEEE80211_M_AHDEMO: wi_write_val(sc, WI_RID_PORTTYPE, WI_PORTTYPE_ADHOC); break; case IEEE80211_M_HOSTAP: wi_write_val(sc, WI_RID_PORTTYPE, WI_PORTTYPE_HOSTAP); break; case IEEE80211_M_MONITOR: if (sc->sc_firmware_type == WI_LUCENT) wi_write_val(sc, WI_RID_PORTTYPE, WI_PORTTYPE_ADHOC); wi_cmd(sc, WI_CMD_DEBUG | (WI_TEST_MONITOR << 8), 0, 0, 0); break; } /* Intersil interprets this RID as joining ESS even in IBSS mode */ if (sc->sc_firmware_type == WI_LUCENT && (ic->ic_flags & IEEE80211_F_IBSSON) && ic->ic_des_esslen > 0) wi_write_val(sc, WI_RID_CREATE_IBSS, 1); else wi_write_val(sc, WI_RID_CREATE_IBSS, 0); wi_write_val(sc, WI_RID_MAX_SLEEP, ic->ic_lintval); wi_write_ssid(sc, WI_RID_DESIRED_SSID, ic->ic_des_essid, ic->ic_des_esslen); wi_write_val(sc, WI_RID_OWN_CHNL, ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); wi_write_ssid(sc, WI_RID_OWN_SSID, ic->ic_des_essid, ic->ic_des_esslen); ifa = ifaddr_byindex(ifp->if_index); sdl = (struct sockaddr_dl *) ifa->ifa_addr; IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(sdl)); wi_write_rid(sc, WI_RID_MAC_NODE, ic->ic_myaddr, IEEE80211_ADDR_LEN); wi_write_val(sc, WI_RID_PM_ENABLED, (ic->ic_flags & IEEE80211_F_PMGTON) ? 1 : 0); /* not yet common 802.11 configuration */ wi_write_val(sc, WI_RID_MAX_DATALEN, sc->sc_max_datalen); wi_write_val(sc, WI_RID_RTS_THRESH, ic->ic_rtsthreshold); if (sc->sc_flags & WI_FLAGS_HAS_FRAGTHR) wi_write_val(sc, WI_RID_FRAG_THRESH, ic->ic_fragthreshold); /* driver specific 802.11 configuration */ if (sc->sc_flags & WI_FLAGS_HAS_SYSSCALE) wi_write_val(sc, WI_RID_SYSTEM_SCALE, sc->sc_system_scale); if (sc->sc_flags & WI_FLAGS_HAS_ROAMING) wi_write_val(sc, WI_RID_ROAMING_MODE, sc->sc_roaming_mode); if (sc->sc_flags & WI_FLAGS_HAS_MOR) wi_write_val(sc, WI_RID_MICROWAVE_OVEN, sc->sc_microwave_oven); wi_write_txrate(sc); wi_write_ssid(sc, WI_RID_NODENAME, sc->sc_nodename, sc->sc_nodelen); if (ic->ic_opmode == IEEE80211_M_HOSTAP && sc->sc_firmware_type == WI_INTERSIL) { wi_write_val(sc, WI_RID_OWN_BEACON_INT, ic->ic_lintval); wi_write_val(sc, WI_RID_BASIC_RATE, 0x03); /* 1, 2 */ wi_write_val(sc, WI_RID_SUPPORT_RATE, 0x0f); /* 1, 2, 5.5, 11 */ wi_write_val(sc, WI_RID_DTIM_PERIOD, 1); } /* * Initialize promisc mode. * Being in the Host-AP mode causes a great * deal of pain if primisc mode is set. * Therefore we avoid confusing the firmware * and always reset promisc mode in Host-AP * mode. Host-AP sees all the packets anyway. */ if (ic->ic_opmode != IEEE80211_M_HOSTAP && (ifp->if_flags & IFF_PROMISC) != 0) { wi_write_val(sc, WI_RID_PROMISC, 1); } else { wi_write_val(sc, WI_RID_PROMISC, 0); } /* Configure WEP. */ if (ic->ic_caps & IEEE80211_C_WEP) wi_write_wep(sc); /* Set multicast filter. */ wi_write_multi(sc); /* Allocate fids for the card */ if (sc->sc_firmware_type != WI_SYMBOL || !wasenabled) { sc->sc_buflen = IEEE80211_MAX_LEN + sizeof(struct wi_frame); if (sc->sc_firmware_type == WI_SYMBOL) sc->sc_buflen = 1585; /* XXX */ for (i = 0; i < sc->sc_ntxbuf; i++) { error = wi_alloc_fid(sc, sc->sc_buflen, &sc->sc_txd[i].d_fid); if (error) { device_printf(sc->sc_dev, "tx buffer allocation failed (error %u)\n", error); goto out; } sc->sc_txd[i].d_len = 0; } } sc->sc_txcur = sc->sc_txnext = 0; /* Enable desired port */ wi_cmd(sc, WI_CMD_ENABLE | sc->sc_portnum, 0, 0, 0); sc->sc_enabled = 1; ifp->if_flags |= IFF_RUNNING; ifp->if_flags &= ~IFF_OACTIVE; if (ic->ic_opmode == IEEE80211_M_AHDEMO || ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_opmode == IEEE80211_M_HOSTAP) ieee80211_new_state(ic, IEEE80211_S_RUN, -1); /* Enable interrupts */ CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS); if (!wasenabled && ic->ic_opmode == IEEE80211_M_HOSTAP && sc->sc_firmware_type == WI_INTERSIL) { /* XXX: some card need to be re-enabled for hostap */ wi_cmd(sc, WI_CMD_DISABLE | WI_PORT0, 0, 0, 0); wi_cmd(sc, WI_CMD_ENABLE | WI_PORT0, 0, 0, 0); } if (ic->ic_opmode == IEEE80211_M_STA && ((ic->ic_flags & IEEE80211_F_DESBSSID) || ic->ic_des_chan != IEEE80211_CHAN_ANYC)) { memset(&join, 0, sizeof(join)); if (ic->ic_flags & IEEE80211_F_DESBSSID) IEEE80211_ADDR_COPY(&join.wi_bssid, ic->ic_des_bssid); if (ic->ic_des_chan != IEEE80211_CHAN_ANYC) join.wi_chan = htole16( ieee80211_chan2ieee(ic, ic->ic_des_chan)); /* Lucent firmware does not support the JOIN RID. */ if (sc->sc_firmware_type != WI_LUCENT) wi_write_rid(sc, WI_RID_JOIN_REQ, &join, sizeof(join)); } WI_UNLOCK(sc); return; out: if (error) { if_printf(ifp, "interface not running\n"); wi_stop(ifp, 0); } WI_UNLOCK(sc); DPRINTF(("wi_init: return %d\n", error)); return; } void wi_stop(struct ifnet *ifp, int disable) { struct ieee80211com *ic = (struct ieee80211com *) ifp; struct wi_softc *sc = ifp->if_softc; WI_LOCK_DECL(); WI_LOCK(sc); ieee80211_new_state(ic, IEEE80211_S_INIT, -1); if (sc->sc_enabled && !sc->wi_gone) { CSR_WRITE_2(sc, WI_INT_EN, 0); wi_cmd(sc, WI_CMD_DISABLE | sc->sc_portnum, 0, 0, 0); if (disable) { #ifdef __NetBSD__ if (sc->sc_disable) (*sc->sc_disable)(sc); #endif sc->sc_enabled = 0; } } sc->sc_tx_timer = 0; sc->sc_scan_timer = 0; sc->sc_syn_timer = 0; sc->sc_false_syns = 0; sc->sc_naps = 0; ifp->if_flags &= ~(IFF_OACTIVE | IFF_RUNNING); ifp->if_timer = 0; WI_UNLOCK(sc); } static void wi_start(struct ifnet *ifp) { struct wi_softc *sc = ifp->if_softc; struct ieee80211com *ic = &sc->sc_ic; struct ieee80211_node *ni; struct ieee80211_frame *wh; struct mbuf *m0; struct wi_frame frmhdr; int cur, fid, off, error; WI_LOCK_DECL(); WI_LOCK(sc); if (sc->wi_gone) { WI_UNLOCK(sc); return; } if (sc->sc_flags & WI_FLAGS_OUTRANGE) { WI_UNLOCK(sc); return; } memset(&frmhdr, 0, sizeof(frmhdr)); cur = sc->sc_txnext; for (;;) { IF_POLL(&ic->ic_mgtq, m0); if (m0 != NULL) { if (sc->sc_txd[cur].d_len != 0) { ifp->if_flags |= IFF_OACTIVE; break; } IF_DEQUEUE(&ic->ic_mgtq, m0); /* * Hack! The referenced node pointer is in the * rcvif field of the packet header. This is * placed there by ieee80211_mgmt_output because * we need to hold the reference with the frame * and there's no other way (other than packet * tags which we consider too expensive to use) * to pass it along. */ ni = (struct ieee80211_node *) m0->m_pkthdr.rcvif; m0->m_pkthdr.rcvif = NULL; m_copydata(m0, 4, ETHER_ADDR_LEN * 2, (caddr_t)&frmhdr.wi_ehdr); frmhdr.wi_ehdr.ether_type = 0; wh = mtod(m0, struct ieee80211_frame *); } else { if (ic->ic_state != IEEE80211_S_RUN) break; IFQ_POLL(&ifp->if_snd, m0); if (m0 == NULL) break; if (sc->sc_txd[cur].d_len != 0) { ifp->if_flags |= IFF_OACTIVE; break; } IFQ_DEQUEUE(&ifp->if_snd, m0); ifp->if_opackets++; m_copydata(m0, 0, ETHER_HDR_LEN, (caddr_t)&frmhdr.wi_ehdr); #if NBPFILTER > 0 BPF_MTAP(ifp, m0); #endif m0 = ieee80211_encap(ifp, m0, &ni); if (m0 == NULL) { ifp->if_oerrors++; continue; } wh = mtod(m0, struct ieee80211_frame *); if (ic->ic_flags & IEEE80211_F_WEPON) wh->i_fc[1] |= IEEE80211_FC1_WEP; } #if NBPFILTER > 0 if (ic->ic_rawbpf) bpf_mtap(ic->ic_rawbpf, m0); #endif frmhdr.wi_tx_ctl = htole16(WI_ENC_TX_802_11|WI_TXCNTL_TX_EX); if (ic->ic_opmode == IEEE80211_M_HOSTAP && (wh->i_fc[1] & IEEE80211_FC1_WEP)) { if ((m0 = ieee80211_wep_crypt(ifp, m0, 1)) == NULL) { ifp->if_oerrors++; if (ni && ni != ic->ic_bss) ieee80211_free_node(ic, ni); continue; } frmhdr.wi_tx_ctl |= htole16(WI_TXCNTL_NOCRYPT); } m_copydata(m0, 0, sizeof(struct ieee80211_frame), (caddr_t)&frmhdr.wi_whdr); m_adj(m0, sizeof(struct ieee80211_frame)); frmhdr.wi_dat_len = htole16(m0->m_pkthdr.len); #if NBPFILTER > 0 if (sc->sc_drvbpf) { struct mbuf *mb; MGETHDR(mb, M_DONTWAIT, m0->m_type); if (mb != NULL) { mb->m_next = m0; mb->m_data = (caddr_t)&sc->sc_tx_th; mb->m_len = sizeof(sc->sc_tx_th); mb->m_pkthdr.len += mb->m_len; bpf_mtap(sc->sc_drvbpf, mb); m_free(mb); } } #endif if (IFF_DUMPPKTS(ifp)) wi_dump_pkt(&frmhdr, NULL, -1); fid = sc->sc_txd[cur].d_fid; off = sizeof(frmhdr); error = wi_write_bap(sc, fid, 0, &frmhdr, sizeof(frmhdr)) != 0 || wi_mwrite_bap(sc, fid, off, m0, m0->m_pkthdr.len) != 0; m_freem(m0); if (ni && ni != ic->ic_bss) ieee80211_free_node(ic, ni); if (error) { ifp->if_oerrors++; continue; } sc->sc_txd[cur].d_len = off; if (sc->sc_txcur == cur) { if (wi_cmd(sc, WI_CMD_TX | WI_RECLAIM, fid, 0, 0)) { if_printf(ifp, "xmit failed\n"); sc->sc_txd[cur].d_len = 0; continue; } sc->sc_tx_timer = 5; ifp->if_timer = 1; } sc->sc_txnext = cur = (cur + 1) % sc->sc_ntxbuf; } WI_UNLOCK(sc); } static int wi_reset(struct wi_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; struct ifnet *ifp = &ic->ic_if; #define WI_INIT_TRIES 3 int i; int error = 0; int tries; /* Symbol firmware cannot be initialized more than once */ if (sc->sc_firmware_type != WI_INTERSIL && sc->sc_reset) return (0); if (sc->sc_firmware_type == WI_SYMBOL) tries = 1; else tries = WI_INIT_TRIES; for (i = 0; i < tries; i++) { if ((error = wi_cmd(sc, WI_CMD_INI, 0, 0, 0)) == 0) break; DELAY(WI_DELAY * 1000); } sc->sc_reset = 1; if (i == tries) { if_printf(ifp, "init failed\n"); return (error); } CSR_WRITE_2(sc, WI_INT_EN, 0); CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); /* Calibrate timer. */ wi_write_val(sc, WI_RID_TICK_TIME, 8); return (0); #undef WI_INIT_TRIES } static void wi_watchdog(struct ifnet *ifp) { struct wi_softc *sc = ifp->if_softc; ifp->if_timer = 0; if (!sc->sc_enabled) return; if (sc->sc_tx_timer) { if (--sc->sc_tx_timer == 0) { if_printf(ifp, "device timeout\n"); ifp->if_oerrors++; wi_init(ifp->if_softc); return; } ifp->if_timer = 1; } if (sc->sc_scan_timer) { if (--sc->sc_scan_timer <= WI_SCAN_WAIT - WI_SCAN_INQWAIT && sc->sc_firmware_type == WI_INTERSIL) { DPRINTF(("wi_watchdog: inquire scan\n")); wi_cmd(sc, WI_CMD_INQUIRE, WI_INFO_SCAN_RESULTS, 0, 0); } if (sc->sc_scan_timer) ifp->if_timer = 1; } if (sc->sc_syn_timer) { if (--sc->sc_syn_timer == 0) { struct ieee80211com *ic = (struct ieee80211com *) ifp; DPRINTF2(("wi_watchdog: %d false syns\n", sc->sc_false_syns)); sc->sc_false_syns = 0; ieee80211_new_state(ic, IEEE80211_S_RUN, -1); sc->sc_syn_timer = 5; } ifp->if_timer = 1; } /* TODO: rate control */ ieee80211_watchdog(ifp); } static int wi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct wi_softc *sc = ifp->if_softc; struct ieee80211com *ic = &sc->sc_ic; struct ifreq *ifr = (struct ifreq *)data; struct ieee80211req *ireq; u_int8_t nodename[IEEE80211_NWID_LEN]; int error = 0; #if __FreeBSD_version >= 500000 struct thread *td = curthread; #else struct proc *td = curproc; /* Little white lie */ #endif struct wi_req wreq; WI_LOCK_DECL(); WI_LOCK(sc); if (sc->wi_gone) { error = ENODEV; goto out; } switch (cmd) { case SIOCSIFFLAGS: /* * Can't do promisc and hostap at the same time. If all that's * changing is the promisc flag, try to short-circuit a call to * wi_init() by just setting PROMISC in the hardware. */ if (ifp->if_flags & IFF_UP) { if (ic->ic_opmode != IEEE80211_M_HOSTAP && ifp->if_flags & IFF_RUNNING) { if (ifp->if_flags & IFF_PROMISC && !(sc->sc_if_flags & IFF_PROMISC)) { wi_write_val(sc, WI_RID_PROMISC, 1); } else if (!(ifp->if_flags & IFF_PROMISC) && sc->sc_if_flags & IFF_PROMISC) { wi_write_val(sc, WI_RID_PROMISC, 0); } else { wi_init(sc); } } else { wi_init(sc); } } else { if (ifp->if_flags & IFF_RUNNING) { wi_stop(ifp, 0); } } sc->sc_if_flags = ifp->if_flags; error = 0; break; case SIOCADDMULTI: case SIOCDELMULTI: error = wi_write_multi(sc); break; case SIOCGIFGENERIC: error = wi_get_cfg(ifp, cmd, data); break; case SIOCSIFGENERIC: error = suser(td); if (error) break; error = wi_set_cfg(ifp, cmd, data); break; case SIOCGPRISM2DEBUG: error = copyin(ifr->ifr_data, &wreq, sizeof(wreq)); if (error) break; if (!(ifp->if_flags & IFF_RUNNING) || sc->sc_firmware_type == WI_LUCENT) { error = EIO; break; } error = wi_get_debug(sc, &wreq); if (error == 0) error = copyout(&wreq, ifr->ifr_data, sizeof(wreq)); break; case SIOCSPRISM2DEBUG: if ((error = suser(td))) goto out; error = copyin(ifr->ifr_data, &wreq, sizeof(wreq)); if (error) break; error = wi_set_debug(sc, &wreq); break; case SIOCG80211: ireq = (struct ieee80211req *) data; switch (ireq->i_type) { case IEEE80211_IOC_STATIONNAME: ireq->i_len = sc->sc_nodelen + 1; error = copyout(sc->sc_nodename, ireq->i_data, ireq->i_len); break; default: error = ieee80211_ioctl(ifp, cmd, data); break; } break; case SIOCS80211: error = suser(td); if (error) break; ireq = (struct ieee80211req *) data; switch (ireq->i_type) { case IEEE80211_IOC_STATIONNAME: if (ireq->i_val != 0 || ireq->i_len > IEEE80211_NWID_LEN) { error = EINVAL; break; } memset(nodename, 0, IEEE80211_NWID_LEN); error = copyin(ireq->i_data, nodename, ireq->i_len); if (error) break; if (sc->sc_enabled) { error = wi_write_ssid(sc, WI_RID_NODENAME, nodename, ireq->i_len); if (error) break; } memcpy(sc->sc_nodename, nodename, IEEE80211_NWID_LEN); sc->sc_nodelen = ireq->i_len; break; default: error = ieee80211_ioctl(ifp, cmd, data); break; } break; default: error = ieee80211_ioctl(ifp, cmd, data); break; } if (error == ENETRESET) { if (sc->sc_enabled) wi_init(sc); /* XXX no error return */ error = 0; } out: WI_UNLOCK(sc); return (error); } static int wi_media_change(struct ifnet *ifp) { struct wi_softc *sc = ifp->if_softc; int error; error = ieee80211_media_change(ifp); if (error == ENETRESET) { if (sc->sc_enabled) wi_init(sc); /* XXX no error return */ error = 0; } return error; } static void wi_media_status(struct ifnet *ifp, struct ifmediareq *imr) { struct wi_softc *sc = ifp->if_softc; struct ieee80211com *ic = &sc->sc_ic; u_int16_t val; int rate, len; if (sc->wi_gone || !sc->sc_enabled) { imr->ifm_active = IFM_IEEE80211 | IFM_NONE; imr->ifm_status = 0; return; } imr->ifm_status = IFM_AVALID; imr->ifm_active = IFM_IEEE80211; if (ic->ic_state == IEEE80211_S_RUN && (sc->sc_flags & WI_FLAGS_OUTRANGE) == 0) imr->ifm_status |= IFM_ACTIVE; len = sizeof(val); if (wi_read_rid(sc, WI_RID_CUR_TX_RATE, &val, &len) != 0) rate = 0; else { /* convert to 802.11 rate */ rate = val * 2; if (sc->sc_firmware_type == WI_LUCENT) { if (rate == 4 * 2) rate = 11; /* 5.5Mbps */ else if (rate == 5 * 2) rate = 22; /* 11Mbps */ } else { if (rate == 4*2) rate = 11; /* 5.5Mbps */ else if (rate == 8*2) rate = 22; /* 11Mbps */ } } imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); switch (ic->ic_opmode) { case IEEE80211_M_STA: break; case IEEE80211_M_IBSS: imr->ifm_active |= IFM_IEEE80211_ADHOC; break; case IEEE80211_M_AHDEMO: imr->ifm_active |= IFM_IEEE80211_ADHOC | IFM_FLAG0; break; case IEEE80211_M_HOSTAP: imr->ifm_active |= IFM_IEEE80211_HOSTAP; break; case IEEE80211_M_MONITOR: imr->ifm_active |= IFM_IEEE80211_MONITOR; break; } } static void wi_sync_bssid(struct wi_softc *sc, u_int8_t new_bssid[IEEE80211_ADDR_LEN]) { struct ieee80211com *ic = &sc->sc_ic; struct ieee80211_node *ni = ic->ic_bss; struct ifnet *ifp = &ic->ic_if; if (IEEE80211_ADDR_EQ(new_bssid, ni->ni_bssid)) return; DPRINTF(("wi_sync_bssid: bssid %s -> ", ether_sprintf(ni->ni_bssid))); DPRINTF(("%s ?\n", ether_sprintf(new_bssid))); /* In promiscuous mode, the BSSID field is not a reliable * indicator of the firmware's BSSID. Damp spurious * change-of-BSSID indications. */ if ((ifp->if_flags & IFF_PROMISC) != 0 && sc->sc_false_syns >= WI_MAX_FALSE_SYNS) return; ieee80211_new_state(ic, IEEE80211_S_RUN, -1); } static void wi_rx_monitor(struct wi_softc *sc, int fid) { struct ieee80211com *ic = &sc->sc_ic; struct ifnet *ifp = &ic->ic_if; struct wi_frame *rx_frame; struct mbuf *m; int datlen, hdrlen; /* first allocate mbuf for packet storage */ m = m_getcl(M_DONTWAIT, MT_DATA, 0); if (m == NULL) { ifp->if_ierrors++; return; } m->m_pkthdr.rcvif = ifp; /* now read wi_frame first so we know how much data to read */ if (wi_read_bap(sc, fid, 0, mtod(m, caddr_t), sizeof(*rx_frame))) { ifp->if_ierrors++; goto done; } rx_frame = mtod(m, struct wi_frame *); switch ((rx_frame->wi_status & WI_STAT_MAC_PORT) >> 8) { case 7: switch (rx_frame->wi_whdr.i_fc[0] & IEEE80211_FC0_TYPE_MASK) { case IEEE80211_FC0_TYPE_DATA: hdrlen = WI_DATA_HDRLEN; datlen = rx_frame->wi_dat_len + WI_FCS_LEN; break; case IEEE80211_FC0_TYPE_MGT: hdrlen = WI_MGMT_HDRLEN; datlen = rx_frame->wi_dat_len + WI_FCS_LEN; break; case IEEE80211_FC0_TYPE_CTL: /* * prism2 cards don't pass control packets * down properly or consistently, so we'll only * pass down the header. */ hdrlen = WI_CTL_HDRLEN; datlen = 0; break; default: if_printf(ifp, "received packet of unknown type " "on port 7\n"); ifp->if_ierrors++; goto done; } break; case 0: hdrlen = WI_DATA_HDRLEN; datlen = rx_frame->wi_dat_len + WI_FCS_LEN; break; default: if_printf(ifp, "received packet on invalid " "port (wi_status=0x%x)\n", rx_frame->wi_status); ifp->if_ierrors++; goto done; } if (hdrlen + datlen + 2 > MCLBYTES) { if_printf(ifp, "oversized packet received " "(wi_dat_len=%d, wi_status=0x%x)\n", datlen, rx_frame->wi_status); ifp->if_ierrors++; goto done; } if (wi_read_bap(sc, fid, hdrlen, mtod(m, caddr_t) + hdrlen, datlen + 2) == 0) { m->m_pkthdr.len = m->m_len = hdrlen + datlen; ifp->if_ipackets++; BPF_MTAP(ifp, m); /* Handle BPF listeners. */ } else ifp->if_ierrors++; done: m_freem(m); } static void wi_rx_intr(struct wi_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; struct ifnet *ifp = &ic->ic_if; struct wi_frame frmhdr; struct mbuf *m; struct ieee80211_frame *wh; struct ieee80211_node *ni; int fid, len, off, rssi; u_int8_t dir; u_int16_t status; u_int32_t rstamp; fid = CSR_READ_2(sc, WI_RX_FID); if (sc->wi_debug.wi_monitor) { /* * If we are in monitor mode just * read the data from the device. */ wi_rx_monitor(sc, fid); CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); return; } /* First read in the frame header */ if (wi_read_bap(sc, fid, 0, &frmhdr, sizeof(frmhdr))) { CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); ifp->if_ierrors++; DPRINTF(("wi_rx_intr: read fid %x failed\n", fid)); return; } if (IFF_DUMPPKTS(ifp)) wi_dump_pkt(&frmhdr, NULL, frmhdr.wi_rx_signal); /* * Drop undecryptable or packets with receive errors here */ status = le16toh(frmhdr.wi_status); if (status & WI_STAT_ERRSTAT) { CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); ifp->if_ierrors++; DPRINTF(("wi_rx_intr: fid %x error status %x\n", fid, status)); return; } rssi = frmhdr.wi_rx_signal; rstamp = (le16toh(frmhdr.wi_rx_tstamp0) << 16) | le16toh(frmhdr.wi_rx_tstamp1); len = le16toh(frmhdr.wi_dat_len); off = ALIGN(sizeof(struct ieee80211_frame)); /* * Sometimes the PRISM2.x returns bogusly large frames. Except * in monitor mode, just throw them away. */ if (off + len > MCLBYTES) { if (ic->ic_opmode != IEEE80211_M_MONITOR) { CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); ifp->if_ierrors++; DPRINTF(("wi_rx_intr: oversized packet\n")); return; } else len = 0; } MGETHDR(m, M_DONTWAIT, MT_DATA); if (m == NULL) { CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); ifp->if_ierrors++; DPRINTF(("wi_rx_intr: MGET failed\n")); return; } if (off + len > MHLEN) { MCLGET(m, M_DONTWAIT); if ((m->m_flags & M_EXT) == 0) { CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); m_freem(m); ifp->if_ierrors++; DPRINTF(("wi_rx_intr: MCLGET failed\n")); return; } } m->m_data += off - sizeof(struct ieee80211_frame); memcpy(m->m_data, &frmhdr.wi_whdr, sizeof(struct ieee80211_frame)); wi_read_bap(sc, fid, sizeof(frmhdr), m->m_data + sizeof(struct ieee80211_frame), len); m->m_pkthdr.len = m->m_len = sizeof(struct ieee80211_frame) + len; m->m_pkthdr.rcvif = ifp; CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); #if NBPFILTER > 0 if (sc->sc_drvbpf) { struct mbuf *mb; /* XXX pre-allocate space when setting up recv's */ MGETHDR(mb, M_DONTWAIT, m->m_type); if (mb != NULL) { /* XXX replace divide by table */ sc->sc_rx_th.wr_rate = frmhdr.wi_rx_rate / 5; sc->sc_rx_th.wr_antsignal = WI_RSSI_TO_DBM(sc, frmhdr.wi_rx_signal); sc->sc_rx_th.wr_antnoise = WI_RSSI_TO_DBM(sc, frmhdr.wi_rx_silence); sc->sc_rx_th.wr_time = htole32((frmhdr.wi_rx_tstamp1 << 16) | frmhdr.wi_rx_tstamp0); (void) m_dup_pkthdr(mb, m, M_DONTWAIT); mb->m_next = m; mb->m_data = (caddr_t)&sc->sc_rx_th; mb->m_len = sizeof(sc->sc_rx_th); mb->m_pkthdr.len += mb->m_len; bpf_mtap(sc->sc_drvbpf, mb); m_free(mb); } } #endif wh = mtod(m, struct ieee80211_frame *); if (wh->i_fc[1] & IEEE80211_FC1_WEP) { /* * WEP is decrypted by hardware. Clear WEP bit * header for ieee80211_input(). */ wh->i_fc[1] &= ~IEEE80211_FC1_WEP; } /* synchronize driver's BSSID with firmware's BSSID */ dir = wh->i_fc[1] & IEEE80211_FC1_DIR_MASK; if (ic->ic_opmode == IEEE80211_M_IBSS && dir == IEEE80211_FC1_DIR_NODS) wi_sync_bssid(sc, wh->i_addr3); /* * Locate the node for sender, track state, and * then pass this node (referenced) up to the 802.11 * layer for its use. We are required to pass * something so we fallback to ic_bss when this frame * is from an unknown sender. */ if (ic->ic_opmode != IEEE80211_M_STA) { ni = ieee80211_find_node(ic, wh->i_addr2); if (ni == NULL) ni = ieee80211_ref_node(ic->ic_bss); } else ni = ieee80211_ref_node(ic->ic_bss); /* * Send frame up for processing. */ ieee80211_input(ifp, m, ni, rssi, rstamp); /* * The frame may have caused the node to be marked for * reclamation (e.g. in response to a DEAUTH message) * so use free_node here instead of unref_node. */ if (ni == ic->ic_bss) ieee80211_unref_node(&ni); else ieee80211_free_node(ic, ni); } static void wi_tx_ex_intr(struct wi_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; struct ifnet *ifp = &ic->ic_if; struct wi_frame frmhdr; int fid; fid = CSR_READ_2(sc, WI_TX_CMP_FID); /* Read in the frame header */ if (wi_read_bap(sc, fid, 0, &frmhdr, sizeof(frmhdr)) == 0) { u_int16_t status = le16toh(frmhdr.wi_status); /* * Spontaneous station disconnects appear as xmit * errors. Don't announce them and/or count them * as an output error. */ if ((status & WI_TXSTAT_DISCONNECT) == 0) { if (ppsratecheck(&lasttxerror, &curtxeps, wi_txerate)) { if_printf(ifp, "tx failed"); if (status & WI_TXSTAT_RET_ERR) printf(", retry limit exceeded"); if (status & WI_TXSTAT_AGED_ERR) printf(", max transmit lifetime exceeded"); if (status & WI_TXSTAT_DISCONNECT) printf(", port disconnected"); if (status & WI_TXSTAT_FORM_ERR) printf(", invalid format (data len %u src %6D)", le16toh(frmhdr.wi_dat_len), frmhdr.wi_ehdr.ether_shost, ":"); if (status & ~0xf) printf(", status=0x%x", status); printf("\n"); } ifp->if_oerrors++; } else { DPRINTF(("port disconnected\n")); ifp->if_collisions++; /* XXX */ } } else DPRINTF(("wi_tx_ex_intr: read fid %x failed\n", fid)); CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_TX_EXC); } static void wi_tx_intr(struct wi_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; struct ifnet *ifp = &ic->ic_if; int fid, cur; fid = CSR_READ_2(sc, WI_ALLOC_FID); CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_ALLOC); cur = sc->sc_txcur; if (sc->sc_txd[cur].d_fid != fid) { if_printf(ifp, "bad alloc %x != %x, cur %d nxt %d\n", fid, sc->sc_txd[cur].d_fid, cur, sc->sc_txnext); return; } sc->sc_tx_timer = 0; sc->sc_txd[cur].d_len = 0; sc->sc_txcur = cur = (cur + 1) % sc->sc_ntxbuf; if (sc->sc_txd[cur].d_len == 0) ifp->if_flags &= ~IFF_OACTIVE; else { if (wi_cmd(sc, WI_CMD_TX | WI_RECLAIM, sc->sc_txd[cur].d_fid, 0, 0)) { if_printf(ifp, "xmit failed\n"); sc->sc_txd[cur].d_len = 0; } else { sc->sc_tx_timer = 5; ifp->if_timer = 1; } } } static void wi_info_intr(struct wi_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; struct ifnet *ifp = &ic->ic_if; int i, fid, len, off; u_int16_t ltbuf[2]; u_int16_t stat; u_int32_t *ptr; fid = CSR_READ_2(sc, WI_INFO_FID); wi_read_bap(sc, fid, 0, ltbuf, sizeof(ltbuf)); switch (le16toh(ltbuf[1])) { case WI_INFO_LINK_STAT: wi_read_bap(sc, fid, sizeof(ltbuf), &stat, sizeof(stat)); DPRINTF(("wi_info_intr: LINK_STAT 0x%x\n", le16toh(stat))); switch (le16toh(stat)) { case WI_INFO_LINK_STAT_CONNECTED: sc->sc_flags &= ~WI_FLAGS_OUTRANGE; if (ic->ic_state == IEEE80211_S_RUN && ic->ic_opmode != IEEE80211_M_IBSS) break; /* FALLTHROUGH */ case WI_INFO_LINK_STAT_AP_CHG: ieee80211_new_state(ic, IEEE80211_S_RUN, -1); break; case WI_INFO_LINK_STAT_AP_INR: sc->sc_flags &= ~WI_FLAGS_OUTRANGE; break; case WI_INFO_LINK_STAT_AP_OOR: if (sc->sc_firmware_type == WI_SYMBOL && sc->sc_scan_timer > 0) { if (wi_cmd(sc, WI_CMD_INQUIRE, WI_INFO_HOST_SCAN_RESULTS, 0, 0) != 0) sc->sc_scan_timer = 0; break; } if (ic->ic_opmode == IEEE80211_M_STA) sc->sc_flags |= WI_FLAGS_OUTRANGE; break; case WI_INFO_LINK_STAT_DISCONNECTED: case WI_INFO_LINK_STAT_ASSOC_FAILED: if (ic->ic_opmode == IEEE80211_M_STA) ieee80211_new_state(ic, IEEE80211_S_INIT, -1); break; } break; case WI_INFO_COUNTERS: /* some card versions have a larger stats structure */ len = min(le16toh(ltbuf[0]) - 1, sizeof(sc->sc_stats) / 4); ptr = (u_int32_t *)&sc->sc_stats; off = sizeof(ltbuf); for (i = 0; i < len; i++, off += 2, ptr++) { wi_read_bap(sc, fid, off, &stat, sizeof(stat)); #ifdef WI_HERMES_STATS_WAR if (stat & 0xf000) stat = ~stat; #endif *ptr += stat; } ifp->if_collisions = sc->sc_stats.wi_tx_single_retries + sc->sc_stats.wi_tx_multi_retries + sc->sc_stats.wi_tx_retry_limit; break; case WI_INFO_SCAN_RESULTS: case WI_INFO_HOST_SCAN_RESULTS: wi_scan_result(sc, fid, le16toh(ltbuf[0])); break; default: DPRINTF(("wi_info_intr: got fid %x type %x len %d\n", fid, le16toh(ltbuf[1]), le16toh(ltbuf[0]))); break; } CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_INFO); } static int wi_write_multi(struct wi_softc *sc) { struct ifnet *ifp = &sc->sc_ic.ic_if; int n; struct ifmultiaddr *ifma; struct wi_mcast mlist; if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { allmulti: memset(&mlist, 0, sizeof(mlist)); return wi_write_rid(sc, WI_RID_MCAST_LIST, &mlist, sizeof(mlist)); } n = 0; #if __FreeBSD_version < 500000 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { #else TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { #endif if (ifma->ifma_addr->sa_family != AF_LINK) continue; if (n >= 16) goto allmulti; IEEE80211_ADDR_COPY(&mlist.wi_mcast[n], (LLADDR((struct sockaddr_dl *)ifma->ifma_addr))); n++; } return wi_write_rid(sc, WI_RID_MCAST_LIST, &mlist, IEEE80211_ADDR_LEN * n); } static void wi_read_nicid(struct wi_softc *sc) { struct wi_card_ident *id; char *p; int len; u_int16_t ver[4]; /* getting chip identity */ memset(ver, 0, sizeof(ver)); len = sizeof(ver); wi_read_rid(sc, WI_RID_CARD_ID, ver, &len); device_printf(sc->sc_dev, "using "); sc->sc_firmware_type = WI_NOTYPE; for (id = wi_card_ident; id->card_name != NULL; id++) { if (le16toh(ver[0]) == id->card_id) { printf("%s", id->card_name); sc->sc_firmware_type = id->firm_type; break; } } if (sc->sc_firmware_type == WI_NOTYPE) { if (le16toh(ver[0]) & 0x8000) { printf("Unknown PRISM2 chip"); sc->sc_firmware_type = WI_INTERSIL; } else { printf("Unknown Lucent chip"); sc->sc_firmware_type = WI_LUCENT; } } /* get primary firmware version (Only Prism chips) */ if (sc->sc_firmware_type != WI_LUCENT) { memset(ver, 0, sizeof(ver)); len = sizeof(ver); wi_read_rid(sc, WI_RID_PRI_IDENTITY, ver, &len); sc->sc_pri_firmware_ver = le16toh(ver[2]) * 10000 + le16toh(ver[3]) * 100 + le16toh(ver[1]); } /* get station firmware version */ memset(ver, 0, sizeof(ver)); len = sizeof(ver); wi_read_rid(sc, WI_RID_STA_IDENTITY, ver, &len); sc->sc_sta_firmware_ver = le16toh(ver[2]) * 10000 + le16toh(ver[3]) * 100 + le16toh(ver[1]); if (sc->sc_firmware_type == WI_INTERSIL && (sc->sc_sta_firmware_ver == 10102 || sc->sc_sta_firmware_ver == 20102)) { char ident[12]; memset(ident, 0, sizeof(ident)); len = sizeof(ident); /* value should be the format like "V2.00-11" */ if (wi_read_rid(sc, WI_RID_SYMBOL_IDENTITY, ident, &len) == 0 && *(p = (char *)ident) >= 'A' && p[2] == '.' && p[5] == '-' && p[8] == '\0') { sc->sc_firmware_type = WI_SYMBOL; sc->sc_sta_firmware_ver = (p[1] - '0') * 10000 + (p[3] - '0') * 1000 + (p[4] - '0') * 100 + (p[6] - '0') * 10 + (p[7] - '0'); } } printf("\n"); device_printf(sc->sc_dev, "%s Firmware: ", sc->sc_firmware_type == WI_LUCENT ? "Lucent" : (sc->sc_firmware_type == WI_SYMBOL ? "Symbol" : "Intersil")); if (sc->sc_firmware_type != WI_LUCENT) /* XXX */ printf("Primary (%u.%u.%u), ", sc->sc_pri_firmware_ver / 10000, (sc->sc_pri_firmware_ver % 10000) / 100, sc->sc_pri_firmware_ver % 100); printf("Station (%u.%u.%u)\n", sc->sc_sta_firmware_ver / 10000, (sc->sc_sta_firmware_ver % 10000) / 100, sc->sc_sta_firmware_ver % 100); } static int wi_write_ssid(struct wi_softc *sc, int rid, u_int8_t *buf, int buflen) { struct wi_ssid ssid; if (buflen > IEEE80211_NWID_LEN) return ENOBUFS; memset(&ssid, 0, sizeof(ssid)); ssid.wi_len = htole16(buflen); memcpy(ssid.wi_ssid, buf, buflen); return wi_write_rid(sc, rid, &ssid, sizeof(ssid)); } static int wi_get_cfg(struct ifnet *ifp, u_long cmd, caddr_t data) { struct wi_softc *sc = ifp->if_softc; struct ieee80211com *ic = &sc->sc_ic; struct ifreq *ifr = (struct ifreq *)data; struct wi_req wreq; struct wi_scan_res *res; int len, n, error, mif, val, off, i; error = copyin(ifr->ifr_data, &wreq, sizeof(wreq)); if (error) return error; len = (wreq.wi_len - 1) * 2; if (len < sizeof(u_int16_t)) return ENOSPC; if (len > sizeof(wreq.wi_val)) len = sizeof(wreq.wi_val); switch (wreq.wi_type) { case WI_RID_IFACE_STATS: memcpy(wreq.wi_val, &sc->sc_stats, sizeof(sc->sc_stats)); if (len < sizeof(sc->sc_stats)) error = ENOSPC; else len = sizeof(sc->sc_stats); break; case WI_RID_ENCRYPTION: case WI_RID_TX_CRYPT_KEY: case WI_RID_DEFLT_CRYPT_KEYS: case WI_RID_TX_RATE: return ieee80211_cfgget(ifp, cmd, data); case WI_RID_MICROWAVE_OVEN: if (sc->sc_enabled && (sc->sc_flags & WI_FLAGS_HAS_MOR)) { error = wi_read_rid(sc, wreq.wi_type, wreq.wi_val, &len); break; } wreq.wi_val[0] = htole16(sc->sc_microwave_oven); len = sizeof(u_int16_t); break; case WI_RID_DBM_ADJUST: if (sc->sc_enabled && (sc->sc_flags & WI_FLAGS_HAS_DBMADJUST)) { error = wi_read_rid(sc, wreq.wi_type, wreq.wi_val, &len); break; } wreq.wi_val[0] = htole16(sc->sc_dbm_offset); len = sizeof(u_int16_t); break; case WI_RID_ROAMING_MODE: if (sc->sc_enabled && (sc->sc_flags & WI_FLAGS_HAS_ROAMING)) { error = wi_read_rid(sc, wreq.wi_type, wreq.wi_val, &len); break; } wreq.wi_val[0] = htole16(sc->sc_roaming_mode); len = sizeof(u_int16_t); break; case WI_RID_SYSTEM_SCALE: if (sc->sc_enabled && (sc->sc_flags & WI_FLAGS_HAS_SYSSCALE)) { error = wi_read_rid(sc, wreq.wi_type, wreq.wi_val, &len); break; } wreq.wi_val[0] = htole16(sc->sc_system_scale); len = sizeof(u_int16_t); break; case WI_RID_FRAG_THRESH: if (sc->sc_enabled && (sc->sc_flags & WI_FLAGS_HAS_FRAGTHR)) { error = wi_read_rid(sc, wreq.wi_type, wreq.wi_val, &len); break; } wreq.wi_val[0] = htole16(ic->ic_fragthreshold); len = sizeof(u_int16_t); break; case WI_RID_READ_APS: if (ic->ic_opmode == IEEE80211_M_HOSTAP) return ieee80211_cfgget(ifp, cmd, data); if (sc->sc_scan_timer > 0) { error = EINPROGRESS; break; } n = sc->sc_naps; if (len < sizeof(n)) { error = ENOSPC; break; } if (len < sizeof(n) + sizeof(struct wi_apinfo) * n) n = (len - sizeof(n)) / sizeof(struct wi_apinfo); len = sizeof(n) + sizeof(struct wi_apinfo) * n; memcpy(wreq.wi_val, &n, sizeof(n)); memcpy((caddr_t)wreq.wi_val + sizeof(n), sc->sc_aps, sizeof(struct wi_apinfo) * n); break; case WI_RID_PRISM2: wreq.wi_val[0] = sc->sc_firmware_type != WI_LUCENT; len = sizeof(u_int16_t); break; case WI_RID_MIF: mif = wreq.wi_val[0]; error = wi_cmd(sc, WI_CMD_READMIF, mif, 0, 0); val = CSR_READ_2(sc, WI_RESP0); wreq.wi_val[0] = val; len = sizeof(u_int16_t); break; case WI_RID_ZERO_CACHE: case WI_RID_PROCFRAME: /* ignore for compatibility */ /* XXX ??? */ break; case WI_RID_READ_CACHE: return ieee80211_cfgget(ifp, cmd, data); case WI_RID_SCAN_RES: /* compatibility interface */ if (ic->ic_opmode == IEEE80211_M_HOSTAP) return ieee80211_cfgget(ifp, cmd, data); if (sc->sc_scan_timer > 0) { error = EINPROGRESS; break; } n = sc->sc_naps; off = sc->sc_firmware_type != WI_LUCENT ? sizeof(struct wi_scan_p2_hdr) : 0; if (len < off + sizeof(struct wi_scan_res) * n) n = (len - off) / sizeof(struct wi_scan_res); len = off + sizeof(struct wi_scan_res) * n; if (off != 0) { struct wi_scan_p2_hdr *p2 = (struct wi_scan_p2_hdr *)wreq.wi_val; /* * Prepend Prism-specific header. */ if (len < sizeof(struct wi_scan_p2_hdr)) { error = ENOSPC; break; } p2 = (struct wi_scan_p2_hdr *)wreq.wi_val; p2->wi_rsvd = 0; p2->wi_reason = n; /* XXX */ } for (i = 0; i < n; i++) { const struct wi_apinfo *ap = &sc->sc_aps[i]; res = (struct wi_scan_res *)((char *)wreq.wi_val + off); res->wi_chan = ap->channel; res->wi_noise = ap->noise; res->wi_signal = ap->signal; IEEE80211_ADDR_COPY(res->wi_bssid, ap->bssid); res->wi_interval = ap->interval; res->wi_capinfo = ap->capinfo; res->wi_ssid_len = ap->namelen; memcpy(res->wi_ssid, ap->name, IEEE80211_NWID_LEN); if (sc->sc_firmware_type != WI_LUCENT) { /* XXX not saved from Prism cards */ memset(res->wi_srates, 0, sizeof(res->wi_srates)); res->wi_rate = ap->rate; res->wi_rsvd = 0; off += WI_PRISM2_RES_SIZE; } else off += WI_WAVELAN_RES_SIZE; } break; default: if (sc->sc_enabled) { error = wi_read_rid(sc, wreq.wi_type, wreq.wi_val, &len); break; } switch (wreq.wi_type) { case WI_RID_MAX_DATALEN: wreq.wi_val[0] = htole16(sc->sc_max_datalen); len = sizeof(u_int16_t); break; case WI_RID_RTS_THRESH: wreq.wi_val[0] = htole16(ic->ic_rtsthreshold); len = sizeof(u_int16_t); break; case WI_RID_CNFAUTHMODE: wreq.wi_val[0] = htole16(sc->sc_cnfauthmode); len = sizeof(u_int16_t); break; case WI_RID_NODENAME: if (len < sc->sc_nodelen + sizeof(u_int16_t)) { error = ENOSPC; break; } len = sc->sc_nodelen + sizeof(u_int16_t); wreq.wi_val[0] = htole16((sc->sc_nodelen + 1) / 2); memcpy(&wreq.wi_val[1], sc->sc_nodename, sc->sc_nodelen); break; default: return ieee80211_cfgget(ifp, cmd, data); } break; } if (error) return error; wreq.wi_len = (len + 1) / 2 + 1; return copyout(&wreq, ifr->ifr_data, (wreq.wi_len + 1) * 2); } static int wi_set_cfg(struct ifnet *ifp, u_long cmd, caddr_t data) { struct wi_softc *sc = ifp->if_softc; struct ieee80211com *ic = &sc->sc_ic; struct ifreq *ifr = (struct ifreq *)data; struct wi_req wreq; struct mbuf *m; int i, len, error, mif, val; struct ieee80211_rateset *rs; error = copyin(ifr->ifr_data, &wreq, sizeof(wreq)); if (error) return error; len = wreq.wi_len ? (wreq.wi_len - 1) * 2 : 0; switch (wreq.wi_type) { case WI_RID_DBM_ADJUST: return ENODEV; case WI_RID_NODENAME: if (le16toh(wreq.wi_val[0]) * 2 > len || le16toh(wreq.wi_val[0]) > sizeof(sc->sc_nodename)) { error = ENOSPC; break; } if (sc->sc_enabled) { error = wi_write_rid(sc, wreq.wi_type, wreq.wi_val, len); if (error) break; } sc->sc_nodelen = le16toh(wreq.wi_val[0]) * 2; memcpy(sc->sc_nodename, &wreq.wi_val[1], sc->sc_nodelen); break; case WI_RID_MICROWAVE_OVEN: case WI_RID_ROAMING_MODE: case WI_RID_SYSTEM_SCALE: case WI_RID_FRAG_THRESH: if (wreq.wi_type == WI_RID_MICROWAVE_OVEN && (sc->sc_flags & WI_FLAGS_HAS_MOR) == 0) break; if (wreq.wi_type == WI_RID_ROAMING_MODE && (sc->sc_flags & WI_FLAGS_HAS_ROAMING) == 0) break; if (wreq.wi_type == WI_RID_SYSTEM_SCALE && (sc->sc_flags & WI_FLAGS_HAS_SYSSCALE) == 0) break; if (wreq.wi_type == WI_RID_FRAG_THRESH && (sc->sc_flags & WI_FLAGS_HAS_FRAGTHR) == 0) break; /* FALLTHROUGH */ case WI_RID_RTS_THRESH: case WI_RID_CNFAUTHMODE: case WI_RID_MAX_DATALEN: if (sc->sc_enabled) { error = wi_write_rid(sc, wreq.wi_type, wreq.wi_val, sizeof(u_int16_t)); if (error) break; } switch (wreq.wi_type) { case WI_RID_FRAG_THRESH: ic->ic_fragthreshold = le16toh(wreq.wi_val[0]); break; case WI_RID_RTS_THRESH: ic->ic_rtsthreshold = le16toh(wreq.wi_val[0]); break; case WI_RID_MICROWAVE_OVEN: sc->sc_microwave_oven = le16toh(wreq.wi_val[0]); break; case WI_RID_ROAMING_MODE: sc->sc_roaming_mode = le16toh(wreq.wi_val[0]); break; case WI_RID_SYSTEM_SCALE: sc->sc_system_scale = le16toh(wreq.wi_val[0]); break; case WI_RID_CNFAUTHMODE: sc->sc_cnfauthmode = le16toh(wreq.wi_val[0]); break; case WI_RID_MAX_DATALEN: sc->sc_max_datalen = le16toh(wreq.wi_val[0]); break; } break; case WI_RID_TX_RATE: switch (le16toh(wreq.wi_val[0])) { case 3: ic->ic_fixed_rate = -1; break; default: rs = &ic->ic_sup_rates[IEEE80211_MODE_11B]; for (i = 0; i < rs->rs_nrates; i++) { if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) / 2 == le16toh(wreq.wi_val[0])) break; } if (i == rs->rs_nrates) return EINVAL; ic->ic_fixed_rate = i; } if (sc->sc_enabled) error = wi_write_txrate(sc); break; case WI_RID_SCAN_APS: if (sc->sc_enabled && ic->ic_opmode != IEEE80211_M_HOSTAP) error = wi_scan_ap(sc, 0x3fff, 0x000f); break; case WI_RID_SCAN_REQ: /* compatibility interface */ if (sc->sc_enabled && ic->ic_opmode != IEEE80211_M_HOSTAP) error = wi_scan_ap(sc, wreq.wi_val[0], wreq.wi_val[1]); break; case WI_RID_MGMT_XMIT: if (!sc->sc_enabled) { error = ENETDOWN; break; } if (ic->ic_mgtq.ifq_len > 5) { error = EAGAIN; break; } /* XXX wi_len looks in u_int8_t, not in u_int16_t */ m = m_devget((char *)&wreq.wi_val, wreq.wi_len, 0, ifp, NULL); if (m == NULL) { error = ENOMEM; break; } IF_ENQUEUE(&ic->ic_mgtq, m); break; case WI_RID_MIF: mif = wreq.wi_val[0]; val = wreq.wi_val[1]; error = wi_cmd(sc, WI_CMD_WRITEMIF, mif, val, 0); break; case WI_RID_PROCFRAME: /* ignore for compatibility */ break; case WI_RID_OWN_SSID: if (le16toh(wreq.wi_val[0]) * 2 > len || le16toh(wreq.wi_val[0]) > IEEE80211_NWID_LEN) { error = ENOSPC; break; } memset(ic->ic_des_essid, 0, IEEE80211_NWID_LEN); ic->ic_des_esslen = le16toh(wreq.wi_val[0]) * 2; memcpy(ic->ic_des_essid, &wreq.wi_val[1], ic->ic_des_esslen); error = ENETRESET; break; default: if (sc->sc_enabled) { error = wi_write_rid(sc, wreq.wi_type, wreq.wi_val, len); if (error) break; } error = ieee80211_cfgset(ifp, cmd, data); break; } return error; } static int wi_write_txrate(struct wi_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; int i; u_int16_t rate; if (ic->ic_fixed_rate < 0) rate = 0; /* auto */ else rate = (ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL) / 2; /* rate: 0, 1, 2, 5, 11 */ switch (sc->sc_firmware_type) { case WI_LUCENT: switch (rate) { case 0: /* auto == 11mbps auto */ rate = 3; break; /* case 1, 2 map to 1, 2*/ case 5: /* 5.5Mbps -> 4 */ rate = 4; break; case 11: /* 11mbps -> 5 */ rate = 5; break; default: break; } break; default: /* Choose a bit according to this table. * * bit | data rate * ----+------------------- * 0 | 1Mbps * 1 | 2Mbps * 2 | 5.5Mbps * 3 | 11Mbps */ for (i = 8; i > 0; i >>= 1) { if (rate >= i) break; } if (i == 0) rate = 0xf; /* auto */ else rate = i; break; } return wi_write_val(sc, WI_RID_TX_RATE, rate); } static int wi_write_wep(struct wi_softc *sc) { struct ieee80211com *ic = &sc->sc_ic; int error = 0; int i, keylen; u_int16_t val; struct wi_key wkey[IEEE80211_WEP_NKID]; switch (sc->sc_firmware_type) { case WI_LUCENT: val = (ic->ic_flags & IEEE80211_F_WEPON) ? 1 : 0; error = wi_write_val(sc, WI_RID_ENCRYPTION, val); if (error) break; error = wi_write_val(sc, WI_RID_TX_CRYPT_KEY, ic->ic_wep_txkey); if (error) break; memset(wkey, 0, sizeof(wkey)); for (i = 0; i < IEEE80211_WEP_NKID; i++) { keylen = ic->ic_nw_keys[i].wk_len; wkey[i].wi_keylen = htole16(keylen); memcpy(wkey[i].wi_keydat, ic->ic_nw_keys[i].wk_key, keylen); } error = wi_write_rid(sc, WI_RID_DEFLT_CRYPT_KEYS, wkey, sizeof(wkey)); break; case WI_INTERSIL: case WI_SYMBOL: if (ic->ic_flags & IEEE80211_F_WEPON) { /* * ONLY HWB3163 EVAL-CARD Firmware version * less than 0.8 variant2 * * If promiscuous mode disable, Prism2 chip * does not work with WEP . * It is under investigation for details. * (ichiro@netbsd.org) */ if (sc->sc_firmware_type == WI_INTERSIL && sc->sc_sta_firmware_ver < 802 ) { /* firm ver < 0.8 variant 2 */ wi_write_val(sc, WI_RID_PROMISC, 1); } wi_write_val(sc, WI_RID_CNFAUTHMODE, sc->sc_cnfauthmode); val = PRIVACY_INVOKED | EXCLUDE_UNENCRYPTED; /* * Encryption firmware has a bug for HostAP mode. */ if (sc->sc_firmware_type == WI_INTERSIL && ic->ic_opmode == IEEE80211_M_HOSTAP) val |= HOST_ENCRYPT; } else { wi_write_val(sc, WI_RID_CNFAUTHMODE, IEEE80211_AUTH_OPEN); val = HOST_ENCRYPT | HOST_DECRYPT; } error = wi_write_val(sc, WI_RID_P2_ENCRYPTION, val); if (error) break; error = wi_write_val(sc, WI_RID_P2_TX_CRYPT_KEY, ic->ic_wep_txkey); if (error) break; /* * It seems that the firmware accept 104bit key only if * all the keys have 104bit length. We get the length of * the transmit key and use it for all other keys. * Perhaps we should use software WEP for such situation. */ keylen = ic->ic_nw_keys[ic->ic_wep_txkey].wk_len; if (keylen > IEEE80211_WEP_KEYLEN) keylen = 13; /* 104bit keys */ else keylen = IEEE80211_WEP_KEYLEN; for (i = 0; i < IEEE80211_WEP_NKID; i++) { error = wi_write_rid(sc, WI_RID_P2_CRYPT_KEY0 + i, ic->ic_nw_keys[i].wk_key, keylen); if (error) break; } break; } return error; } static int wi_cmd(struct wi_softc *sc, int cmd, int val0, int val1, int val2) { int i, s = 0; static volatile int count = 0; if (count > 0) panic("Hey partner, hold on there!"); count++; /* wait for the busy bit to clear */ for (i = 500; i > 0; i--) { /* 5s */ if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) break; DELAY(10*1000); /* 10 m sec */ } if (i == 0) { device_printf(sc->sc_dev, "wi_cmd: busy bit won't clear.\n" ); count--; return(ETIMEDOUT); } CSR_WRITE_2(sc, WI_PARAM0, val0); CSR_WRITE_2(sc, WI_PARAM1, val1); CSR_WRITE_2(sc, WI_PARAM2, val2); CSR_WRITE_2(sc, WI_COMMAND, cmd); if (cmd == WI_CMD_INI) { /* XXX: should sleep here. */ DELAY(100*1000); /* 100ms delay for init */ } for (i = 0; i < WI_TIMEOUT; i++) { /* * Wait for 'command complete' bit to be * set in the event status register. */ s = CSR_READ_2(sc, WI_EVENT_STAT); if (s & WI_EV_CMD) { /* Ack the event and read result code. */ s = CSR_READ_2(sc, WI_STATUS); CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD); if (s & WI_STAT_CMD_RESULT) { count--; return(EIO); } break; } DELAY(WI_DELAY); } count--; if (i == WI_TIMEOUT) { device_printf(sc->sc_dev, "timeout in wi_cmd 0x%04x; event status 0x%04x\n", cmd, s); return(ETIMEDOUT); } return (0); } static int wi_seek_bap(struct wi_softc *sc, int id, int off) { int i, status; CSR_WRITE_2(sc, WI_SEL0, id); CSR_WRITE_2(sc, WI_OFF0, off); for (i = 0; ; i++) { status = CSR_READ_2(sc, WI_OFF0); if ((status & WI_OFF_BUSY) == 0) break; if (i == WI_TIMEOUT) { device_printf(sc->sc_dev, "timeout in wi_seek to %x/%x\n", id, off); sc->sc_bap_off = WI_OFF_ERR; /* invalidate */ return ETIMEDOUT; } DELAY(1); } if (status & WI_OFF_ERR) { device_printf(sc->sc_dev, "failed in wi_seek to %x/%x\n", id, off); sc->sc_bap_off = WI_OFF_ERR; /* invalidate */ return EIO; } sc->sc_bap_id = id; sc->sc_bap_off = off; return 0; } static int wi_read_bap(struct wi_softc *sc, int id, int off, void *buf, int buflen) { u_int16_t *ptr; int i, error, cnt; if (buflen == 0) return 0; if (id != sc->sc_bap_id || off != sc->sc_bap_off) { if ((error = wi_seek_bap(sc, id, off)) != 0) return error; } cnt = (buflen + 1) / 2; ptr = (u_int16_t *)buf; for (i = 0; i < cnt; i++) *ptr++ = CSR_READ_2(sc, WI_DATA0); sc->sc_bap_off += cnt * 2; return 0; } static int wi_write_bap(struct wi_softc *sc, int id, int off, void *buf, int buflen) { u_int16_t *ptr; int i, error, cnt; if (buflen == 0) return 0; #ifdef WI_HERMES_AUTOINC_WAR again: #endif if (id != sc->sc_bap_id || off != sc->sc_bap_off) { if ((error = wi_seek_bap(sc, id, off)) != 0) return error; } cnt = (buflen + 1) / 2; ptr = (u_int16_t *)buf; for (i = 0; i < cnt; i++) CSR_WRITE_2(sc, WI_DATA0, ptr[i]); sc->sc_bap_off += cnt * 2; #ifdef WI_HERMES_AUTOINC_WAR /* * According to the comments in the HCF Light code, there is a bug * in the Hermes (or possibly in certain Hermes firmware revisions) * where the chip's internal autoincrement counter gets thrown off * during data writes: the autoincrement is missed, causing one * data word to be overwritten and subsequent words to be written to * the wrong memory locations. The end result is that we could end * up transmitting bogus frames without realizing it. The workaround * for this is to write a couple of extra guard words after the end * of the transfer, then attempt to read then back. If we fail to * locate the guard words where we expect them, we preform the * transfer over again. */ if ((sc->sc_flags & WI_FLAGS_BUG_AUTOINC) && (id & 0xf000) == 0) { CSR_WRITE_2(sc, WI_DATA0, 0x1234); CSR_WRITE_2(sc, WI_DATA0, 0x5678); wi_seek_bap(sc, id, sc->sc_bap_off); sc->sc_bap_off = WI_OFF_ERR; /* invalidate */ if (CSR_READ_2(sc, WI_DATA0) != 0x1234 || CSR_READ_2(sc, WI_DATA0) != 0x5678) { device_printf(sc->sc_dev, "detect auto increment bug, try again\n"); goto again; } } #endif return 0; } static int wi_mwrite_bap(struct wi_softc *sc, int id, int off, struct mbuf *m0, int totlen) { int error, len; struct mbuf *m; for (m = m0; m != NULL && totlen > 0; m = m->m_next) { if (m->m_len == 0) continue; len = min(m->m_len, totlen); if (((u_long)m->m_data) % 2 != 0 || len % 2 != 0) { m_copydata(m, 0, totlen, (caddr_t)&sc->sc_txbuf); return wi_write_bap(sc, id, off, (caddr_t)&sc->sc_txbuf, totlen); } if ((error = wi_write_bap(sc, id, off, m->m_data, len)) != 0) return error; off += m->m_len; totlen -= len; } return 0; } static int wi_alloc_fid(struct wi_softc *sc, int len, int *idp) { int i; if (wi_cmd(sc, WI_CMD_ALLOC_MEM, len, 0, 0)) { device_printf(sc->sc_dev, "failed to allocate %d bytes on NIC\n", len); return ENOMEM; } for (i = 0; i < WI_TIMEOUT; i++) { if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_ALLOC) break; if (i == WI_TIMEOUT) { device_printf(sc->sc_dev, "timeout in alloc\n"); return ETIMEDOUT; } DELAY(1); } *idp = CSR_READ_2(sc, WI_ALLOC_FID); CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_ALLOC); return 0; } static int wi_read_rid(struct wi_softc *sc, int rid, void *buf, int *buflenp) { int error, len; u_int16_t ltbuf[2]; /* Tell the NIC to enter record read mode. */ error = wi_cmd(sc, WI_CMD_ACCESS | WI_ACCESS_READ, rid, 0, 0); if (error) return error; error = wi_read_bap(sc, rid, 0, ltbuf, sizeof(ltbuf)); if (error) return error; if (le16toh(ltbuf[1]) != rid) { device_printf(sc->sc_dev, "record read mismatch, rid=%x, got=%x\n", rid, le16toh(ltbuf[1])); return EIO; } len = (le16toh(ltbuf[0]) - 1) * 2; /* already got rid */ if (*buflenp < len) { device_printf(sc->sc_dev, "record buffer is too small, " "rid=%x, size=%d, len=%d\n", rid, *buflenp, len); return ENOSPC; } *buflenp = len; return wi_read_bap(sc, rid, sizeof(ltbuf), buf, len); } static int wi_write_rid(struct wi_softc *sc, int rid, void *buf, int buflen) { int error; u_int16_t ltbuf[2]; ltbuf[0] = htole16((buflen + 1) / 2 + 1); /* includes rid */ ltbuf[1] = htole16(rid); error = wi_write_bap(sc, rid, 0, ltbuf, sizeof(ltbuf)); if (error) return error; error = wi_write_bap(sc, rid, sizeof(ltbuf), buf, buflen); if (error) return error; return wi_cmd(sc, WI_CMD_ACCESS | WI_ACCESS_WRITE, rid, 0, 0); } static int wi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) { struct ifnet *ifp = &ic->ic_if; struct wi_softc *sc = ifp->if_softc; struct ieee80211_node *ni = ic->ic_bss; int buflen; u_int16_t val; struct wi_ssid ssid; u_int8_t old_bssid[IEEE80211_ADDR_LEN]; DPRINTF(("%s: %s -> %s\n", __func__, ieee80211_state_name[ic->ic_state], ieee80211_state_name[nstate])); switch (nstate) { case IEEE80211_S_INIT: ic->ic_flags &= ~IEEE80211_F_SIBSS; sc->sc_flags &= ~WI_FLAGS_OUTRANGE; return (*sc->sc_newstate)(ic, nstate, arg); case IEEE80211_S_RUN: sc->sc_flags &= ~WI_FLAGS_OUTRANGE; buflen = IEEE80211_ADDR_LEN; wi_read_rid(sc, WI_RID_CURRENT_BSSID, ni->ni_bssid, &buflen); IEEE80211_ADDR_COPY(ni->ni_macaddr, ni->ni_bssid); buflen = sizeof(val); wi_read_rid(sc, WI_RID_CURRENT_CHAN, &val, &buflen); /* XXX validate channel */ ni->ni_chan = &ic->ic_channels[le16toh(val)]; #if NBPFILTER > 0 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = htole16(ni->ni_chan->ic_freq); sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = htole16(ni->ni_chan->ic_flags); #endif if (IEEE80211_ADDR_EQ(old_bssid, ni->ni_bssid)) sc->sc_false_syns++; else sc->sc_false_syns = 0; if (ic->ic_opmode == IEEE80211_M_HOSTAP) { ni->ni_esslen = ic->ic_des_esslen; memcpy(ni->ni_essid, ic->ic_des_essid, ni->ni_esslen); ni->ni_rates = ic->ic_sup_rates[IEEE80211_MODE_11B]; ni->ni_intval = ic->ic_lintval; ni->ni_capinfo = IEEE80211_CAPINFO_ESS; if (ic->ic_flags & IEEE80211_F_WEPON) ni->ni_capinfo |= IEEE80211_CAPINFO_PRIVACY; } else { /* XXX check return value */ buflen = sizeof(ssid); wi_read_rid(sc, WI_RID_CURRENT_SSID, &ssid, &buflen); ni->ni_esslen = le16toh(ssid.wi_len); if (ni->ni_esslen > IEEE80211_NWID_LEN) ni->ni_esslen = IEEE80211_NWID_LEN; /*XXX*/ memcpy(ni->ni_essid, ssid.wi_ssid, ni->ni_esslen); } break; case IEEE80211_S_SCAN: case IEEE80211_S_AUTH: case IEEE80211_S_ASSOC: break; } ic->ic_state = nstate; /* NB: skip normal ieee80211 handling */ return 0; } static int wi_scan_ap(struct wi_softc *sc, u_int16_t chanmask, u_int16_t txrate) { int error = 0; u_int16_t val[2]; if (!sc->sc_enabled) return ENXIO; switch (sc->sc_firmware_type) { case WI_LUCENT: (void)wi_cmd(sc, WI_CMD_INQUIRE, WI_INFO_SCAN_RESULTS, 0, 0); break; case WI_INTERSIL: val[0] = chanmask; /* channel */ val[1] = txrate; /* tx rate */ error = wi_write_rid(sc, WI_RID_SCAN_REQ, val, sizeof(val)); break; case WI_SYMBOL: /* * XXX only supported on 3.x ? */ val[0] = BSCAN_BCAST | BSCAN_ONETIME; error = wi_write_rid(sc, WI_RID_BCAST_SCAN_REQ, val, sizeof(val[0])); break; } if (error == 0) { sc->sc_scan_timer = WI_SCAN_WAIT; sc->sc_ic.ic_if.if_timer = 1; DPRINTF(("wi_scan_ap: start scanning, " "chamask 0x%x txrate 0x%x\n", chanmask, txrate)); } return error; } static void wi_scan_result(struct wi_softc *sc, int fid, int cnt) { #define N(a) (sizeof (a) / sizeof (a[0])) int i, naps, off, szbuf; struct wi_scan_header ws_hdr; /* Prism2 header */ struct wi_scan_data_p2 ws_dat; /* Prism2 scantable*/ struct wi_apinfo *ap; off = sizeof(u_int16_t) * 2; memset(&ws_hdr, 0, sizeof(ws_hdr)); switch (sc->sc_firmware_type) { case WI_INTERSIL: wi_read_bap(sc, fid, off, &ws_hdr, sizeof(ws_hdr)); off += sizeof(ws_hdr); szbuf = sizeof(struct wi_scan_data_p2); break; case WI_SYMBOL: szbuf = sizeof(struct wi_scan_data_p2) + 6; break; case WI_LUCENT: szbuf = sizeof(struct wi_scan_data); break; default: device_printf(sc->sc_dev, "wi_scan_result: unknown firmware type %u\n", sc->sc_firmware_type); naps = 0; goto done; } naps = (cnt * 2 + 2 - off) / szbuf; if (naps > N(sc->sc_aps)) naps = N(sc->sc_aps); sc->sc_naps = naps; /* Read Data */ ap = sc->sc_aps; memset(&ws_dat, 0, sizeof(ws_dat)); for (i = 0; i < naps; i++, ap++) { wi_read_bap(sc, fid, off, &ws_dat, (sizeof(ws_dat) < szbuf ? sizeof(ws_dat) : szbuf)); DPRINTF2(("wi_scan_result: #%d: off %d bssid %s\n", i, off, ether_sprintf(ws_dat.wi_bssid))); off += szbuf; ap->scanreason = le16toh(ws_hdr.wi_reason); memcpy(ap->bssid, ws_dat.wi_bssid, sizeof(ap->bssid)); ap->channel = le16toh(ws_dat.wi_chid); ap->signal = le16toh(ws_dat.wi_signal); ap->noise = le16toh(ws_dat.wi_noise); ap->quality = ap->signal - ap->noise; ap->capinfo = le16toh(ws_dat.wi_capinfo); ap->interval = le16toh(ws_dat.wi_interval); ap->rate = le16toh(ws_dat.wi_rate); ap->namelen = le16toh(ws_dat.wi_namelen); if (ap->namelen > sizeof(ap->name)) ap->namelen = sizeof(ap->name); memcpy(ap->name, ws_dat.wi_name, ap->namelen); } done: /* Done scanning */ sc->sc_scan_timer = 0; DPRINTF(("wi_scan_result: scan complete: ap %d\n", naps)); #undef N } static void wi_dump_pkt(struct wi_frame *wh, struct ieee80211_node *ni, int rssi) { ieee80211_dump_pkt((u_int8_t *) &wh->wi_whdr, sizeof(wh->wi_whdr), ni ? ni->ni_rates.rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL : -1, rssi); printf(" status 0x%x rx_tstamp1 %u rx_tstamp0 0x%u rx_silence %u\n", le16toh(wh->wi_status), le16toh(wh->wi_rx_tstamp1), le16toh(wh->wi_rx_tstamp0), wh->wi_rx_silence); printf(" rx_signal %u rx_rate %u rx_flow %u\n", wh->wi_rx_signal, wh->wi_rx_rate, wh->wi_rx_flow); printf(" tx_rtry %u tx_rate %u tx_ctl 0x%x dat_len %u\n", wh->wi_tx_rtry, wh->wi_tx_rate, le16toh(wh->wi_tx_ctl), le16toh(wh->wi_dat_len)); printf(" ehdr dst %6D src %6D type 0x%x\n", wh->wi_ehdr.ether_dhost, ":", wh->wi_ehdr.ether_shost, ":", wh->wi_ehdr.ether_type); } int wi_alloc(device_t dev, int rid) { struct wi_softc *sc = device_get_softc(dev); if (sc->wi_bus_type != WI_BUS_PCI_NATIVE) { sc->iobase_rid = rid; sc->iobase = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->iobase_rid, 0, ~0, (1 << 6), rman_make_alignment_flags(1 << 6) | RF_ACTIVE); if (!sc->iobase) { device_printf(dev, "No I/O space?!\n"); return (ENXIO); } sc->wi_io_addr = rman_get_start(sc->iobase); sc->wi_btag = rman_get_bustag(sc->iobase); sc->wi_bhandle = rman_get_bushandle(sc->iobase); } else { sc->mem_rid = rid; sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->mem_rid, 0, ~0, 1, RF_ACTIVE); if (!sc->mem) { device_printf(dev, "No Mem space on prism2.5?\n"); return (ENXIO); } sc->wi_btag = rman_get_bustag(sc->mem); sc->wi_bhandle = rman_get_bushandle(sc->mem); } sc->irq_rid = 0; sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 0, ~0, 1, RF_ACTIVE | ((sc->wi_bus_type == WI_BUS_PCCARD) ? 0 : RF_SHAREABLE)); if (!sc->irq) { wi_free(dev); device_printf(dev, "No irq?!\n"); return (ENXIO); } sc->sc_dev = dev; sc->sc_unit = device_get_unit(dev); return (0); } void wi_free(device_t dev) { struct wi_softc *sc = device_get_softc(dev); if (sc->iobase != NULL) { bus_release_resource(dev, SYS_RES_IOPORT, sc->iobase_rid, sc->iobase); sc->iobase = NULL; } if (sc->irq != NULL) { bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); sc->irq = NULL; } if (sc->mem != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); sc->mem = NULL; } return; } static int wi_get_debug(struct wi_softc *sc, struct wi_req *wreq) { int error = 0; wreq->wi_len = 1; switch (wreq->wi_type) { case WI_DEBUG_SLEEP: wreq->wi_len++; wreq->wi_val[0] = sc->wi_debug.wi_sleep; break; case WI_DEBUG_DELAYSUPP: wreq->wi_len++; wreq->wi_val[0] = sc->wi_debug.wi_delaysupp; break; case WI_DEBUG_TXSUPP: wreq->wi_len++; wreq->wi_val[0] = sc->wi_debug.wi_txsupp; break; case WI_DEBUG_MONITOR: wreq->wi_len++; wreq->wi_val[0] = sc->wi_debug.wi_monitor; break; case WI_DEBUG_LEDTEST: wreq->wi_len += 3; wreq->wi_val[0] = sc->wi_debug.wi_ledtest; wreq->wi_val[1] = sc->wi_debug.wi_ledtest_param0; wreq->wi_val[2] = sc->wi_debug.wi_ledtest_param1; break; case WI_DEBUG_CONTTX: wreq->wi_len += 2; wreq->wi_val[0] = sc->wi_debug.wi_conttx; wreq->wi_val[1] = sc->wi_debug.wi_conttx_param0; break; case WI_DEBUG_CONTRX: wreq->wi_len++; wreq->wi_val[0] = sc->wi_debug.wi_contrx; break; case WI_DEBUG_SIGSTATE: wreq->wi_len += 2; wreq->wi_val[0] = sc->wi_debug.wi_sigstate; wreq->wi_val[1] = sc->wi_debug.wi_sigstate_param0; break; case WI_DEBUG_CONFBITS: wreq->wi_len += 2; wreq->wi_val[0] = sc->wi_debug.wi_confbits; wreq->wi_val[1] = sc->wi_debug.wi_confbits_param0; break; default: error = EIO; break; } return (error); } static int wi_set_debug(struct wi_softc *sc, struct wi_req *wreq) { int error = 0; u_int16_t cmd, param0 = 0, param1 = 0; switch (wreq->wi_type) { case WI_DEBUG_RESET: case WI_DEBUG_INIT: case WI_DEBUG_CALENABLE: break; case WI_DEBUG_SLEEP: sc->wi_debug.wi_sleep = 1; break; case WI_DEBUG_WAKE: sc->wi_debug.wi_sleep = 0; break; case WI_DEBUG_CHAN: param0 = wreq->wi_val[0]; break; case WI_DEBUG_DELAYSUPP: sc->wi_debug.wi_delaysupp = 1; break; case WI_DEBUG_TXSUPP: sc->wi_debug.wi_txsupp = 1; break; case WI_DEBUG_MONITOR: sc->wi_debug.wi_monitor = 1; break; case WI_DEBUG_LEDTEST: param0 = wreq->wi_val[0]; param1 = wreq->wi_val[1]; sc->wi_debug.wi_ledtest = 1; sc->wi_debug.wi_ledtest_param0 = param0; sc->wi_debug.wi_ledtest_param1 = param1; break; case WI_DEBUG_CONTTX: param0 = wreq->wi_val[0]; sc->wi_debug.wi_conttx = 1; sc->wi_debug.wi_conttx_param0 = param0; break; case WI_DEBUG_STOPTEST: sc->wi_debug.wi_delaysupp = 0; sc->wi_debug.wi_txsupp = 0; sc->wi_debug.wi_monitor = 0; sc->wi_debug.wi_ledtest = 0; sc->wi_debug.wi_ledtest_param0 = 0; sc->wi_debug.wi_ledtest_param1 = 0; sc->wi_debug.wi_conttx = 0; sc->wi_debug.wi_conttx_param0 = 0; sc->wi_debug.wi_contrx = 0; sc->wi_debug.wi_sigstate = 0; sc->wi_debug.wi_sigstate_param0 = 0; break; case WI_DEBUG_CONTRX: sc->wi_debug.wi_contrx = 1; break; case WI_DEBUG_SIGSTATE: param0 = wreq->wi_val[0]; sc->wi_debug.wi_sigstate = 1; sc->wi_debug.wi_sigstate_param0 = param0; break; case WI_DEBUG_CONFBITS: param0 = wreq->wi_val[0]; param1 = wreq->wi_val[1]; sc->wi_debug.wi_confbits = param0; sc->wi_debug.wi_confbits_param0 = param1; break; default: error = EIO; break; } if (error) return (error); cmd = WI_CMD_DEBUG | (wreq->wi_type << 8); error = wi_cmd(sc, cmd, param0, param1, 0); return (error); } #if __FreeBSD_version >= 500000 /* * Special routines to download firmware for Symbol CF card. * XXX: This should be modified generic into any PRISM-2 based card. */ #define WI_SBCF_PDIADDR 0x3100 /* unaligned load little endian */ #define GETLE32(p) ((p)[0] | ((p)[1]<<8) | ((p)[2]<<16) | ((p)[3]<<24)) #define GETLE16(p) ((p)[0] | ((p)[1]<<8)) int wi_symbol_load_firm(struct wi_softc *sc, const void *primsym, int primlen, const void *secsym, int seclen) { uint8_t ebuf[256]; int i; /* load primary code and run it */ wi_symbol_set_hcr(sc, WI_HCR_EEHOLD); if (wi_symbol_write_firm(sc, primsym, primlen, NULL, 0)) return EIO; wi_symbol_set_hcr(sc, WI_HCR_RUN); for (i = 0; ; i++) { if (i == 10) return ETIMEDOUT; tsleep(sc, PWAIT, "wiinit", 1); if (CSR_READ_2(sc, WI_CNTL) == WI_CNTL_AUX_ENA_STAT) break; /* write the magic key value to unlock aux port */ CSR_WRITE_2(sc, WI_PARAM0, WI_AUX_KEY0); CSR_WRITE_2(sc, WI_PARAM1, WI_AUX_KEY1); CSR_WRITE_2(sc, WI_PARAM2, WI_AUX_KEY2); CSR_WRITE_2(sc, WI_CNTL, WI_CNTL_AUX_ENA_CNTL); } /* issue read EEPROM command: XXX copied from wi_cmd() */ CSR_WRITE_2(sc, WI_PARAM0, 0); CSR_WRITE_2(sc, WI_PARAM1, 0); CSR_WRITE_2(sc, WI_PARAM2, 0); CSR_WRITE_2(sc, WI_COMMAND, WI_CMD_READEE); for (i = 0; i < WI_TIMEOUT; i++) { if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD) break; DELAY(1); } CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD); CSR_WRITE_2(sc, WI_AUX_PAGE, WI_SBCF_PDIADDR / WI_AUX_PGSZ); CSR_WRITE_2(sc, WI_AUX_OFFSET, WI_SBCF_PDIADDR % WI_AUX_PGSZ); CSR_READ_MULTI_STREAM_2(sc, WI_AUX_DATA, (uint16_t *)ebuf, sizeof(ebuf) / 2); if (GETLE16(ebuf) > sizeof(ebuf)) return EIO; if (wi_symbol_write_firm(sc, secsym, seclen, ebuf + 4, GETLE16(ebuf))) return EIO; return 0; } static int wi_symbol_write_firm(struct wi_softc *sc, const void *buf, int buflen, const void *ebuf, int ebuflen) { const uint8_t *p, *ep, *q, *eq; char *tp; uint32_t addr, id, eid; int i, len, elen, nblk, pdrlen; /* * Parse the header of the firmware image. */ p = buf; ep = p + buflen; while (p < ep && *p++ != ' '); /* FILE: */ while (p < ep && *p++ != ' '); /* filename */ while (p < ep && *p++ != ' '); /* type of the firmware */ nblk = strtoul(p, &tp, 10); p = tp; pdrlen = strtoul(p + 1, &tp, 10); p = tp; while (p < ep && *p++ != 0x1a); /* skip rest of header */ /* * Block records: address[4], length[2], data[length]; */ for (i = 0; i < nblk; i++) { addr = GETLE32(p); p += 4; len = GETLE16(p); p += 2; CSR_WRITE_2(sc, WI_AUX_PAGE, addr / WI_AUX_PGSZ); CSR_WRITE_2(sc, WI_AUX_OFFSET, addr % WI_AUX_PGSZ); CSR_WRITE_MULTI_STREAM_2(sc, WI_AUX_DATA, (const uint16_t *)p, len / 2); p += len; } /* * PDR: id[4], address[4], length[4]; */ for (i = 0; i < pdrlen; ) { id = GETLE32(p); p += 4; i += 4; addr = GETLE32(p); p += 4; i += 4; len = GETLE32(p); p += 4; i += 4; /* replace PDR entry with the values from EEPROM, if any */ for (q = ebuf, eq = q + ebuflen; q < eq; q += elen * 2) { elen = GETLE16(q); q += 2; eid = GETLE16(q); q += 2; elen--; /* elen includes eid */ if (eid == 0) break; if (eid != id) continue; CSR_WRITE_2(sc, WI_AUX_PAGE, addr / WI_AUX_PGSZ); CSR_WRITE_2(sc, WI_AUX_OFFSET, addr % WI_AUX_PGSZ); CSR_WRITE_MULTI_STREAM_2(sc, WI_AUX_DATA, (const uint16_t *)q, len / 2); break; } } return 0; } static int wi_symbol_set_hcr(struct wi_softc *sc, int mode) { uint16_t hcr; CSR_WRITE_2(sc, WI_COR, WI_COR_RESET); tsleep(sc, PWAIT, "wiinit", 1); hcr = CSR_READ_2(sc, WI_HCR); hcr = (hcr & WI_HCR_4WIRE) | (mode & ~WI_HCR_4WIRE); CSR_WRITE_2(sc, WI_HCR, hcr); tsleep(sc, PWAIT, "wiinit", 1); CSR_WRITE_2(sc, WI_COR, WI_COR_IOMODE); tsleep(sc, PWAIT, "wiinit", 1); return 0; } #endif Index: head/sys/pci/if_sis.c =================================================================== --- head/sys/pci/if_sis.c (revision 121696) +++ head/sys/pci/if_sis.c (revision 121697) @@ -1,2446 +1,2446 @@ /* * Copyright (c) 1997, 1998, 1999 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ /* * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are * available from http://www.sis.com.tw. * * This driver also supports the NatSemi DP83815. Datasheets are * available from http://www.national.com. * * Written by Bill Paul * Electrical Engineering Department * Columbia University, New York City */ /* * The SiS 900 is a fairly simple chip. It uses bus master DMA with * simple TX and RX descriptors of 3 longwords in size. The receiver * has a single perfect filter entry for the station address and a * 128-bit multicast hash table. The SiS 900 has a built-in MII-based * transceiver while the 7016 requires an external transceiver chip. * Both chips offer the standard bit-bang MII interface as well as * an enchanced PHY interface which simplifies accessing MII registers. * * The only downside to this chipset is that RX descriptors must be * longword aligned. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define SIS_USEIOSPACE #include MODULE_DEPEND(sis, pci, 1, 1, 1); MODULE_DEPEND(sis, ether, 1, 1, 1); MODULE_DEPEND(sis, miibus, 1, 1, 1); /* "controller miibus0" required. See GENERIC if you get errors here. */ #include "miibus_if.h" /* * Various supported device vendors/types and their names. */ static struct sis_type sis_devs[] = { { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" }, { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" }, { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" }, { 0, 0, NULL } }; static int sis_probe (device_t); static int sis_attach (device_t); static int sis_detach (device_t); static int sis_newbuf (struct sis_softc *, struct sis_desc *, struct mbuf *); static int sis_encap (struct sis_softc *, struct mbuf **, u_int32_t *); static void sis_rxeof (struct sis_softc *); static void sis_rxeoc (struct sis_softc *); static void sis_txeof (struct sis_softc *); static void sis_intr (void *); static void sis_tick (void *); static void sis_start (struct ifnet *); static int sis_ioctl (struct ifnet *, u_long, caddr_t); static void sis_init (void *); static void sis_stop (struct sis_softc *); static void sis_watchdog (struct ifnet *); static void sis_shutdown (device_t); static int sis_ifmedia_upd (struct ifnet *); static void sis_ifmedia_sts (struct ifnet *, struct ifmediareq *); static u_int16_t sis_reverse (u_int16_t); static void sis_delay (struct sis_softc *); static void sis_eeprom_idle (struct sis_softc *); static void sis_eeprom_putbyte (struct sis_softc *, int); static void sis_eeprom_getword (struct sis_softc *, int, u_int16_t *); static void sis_read_eeprom (struct sis_softc *, caddr_t, int, int, int); #ifdef __i386__ static void sis_read_cmos (struct sis_softc *, device_t, caddr_t, int, int); static void sis_read_mac (struct sis_softc *, device_t, caddr_t); static device_t sis_find_bridge (device_t); #endif static void sis_mii_sync (struct sis_softc *); static void sis_mii_send (struct sis_softc *, u_int32_t, int); static int sis_mii_readreg (struct sis_softc *, struct sis_mii_frame *); static int sis_mii_writereg (struct sis_softc *, struct sis_mii_frame *); static int sis_miibus_readreg (device_t, int, int); static int sis_miibus_writereg (device_t, int, int, int); static void sis_miibus_statchg (device_t); static void sis_setmulti_sis (struct sis_softc *); static void sis_setmulti_ns (struct sis_softc *); static u_int32_t sis_crc (struct sis_softc *, caddr_t); static void sis_reset (struct sis_softc *); static int sis_list_rx_init (struct sis_softc *); static int sis_list_tx_init (struct sis_softc *); static void sis_dma_map_desc_ptr (void *, bus_dma_segment_t *, int, int); static void sis_dma_map_desc_next (void *, bus_dma_segment_t *, int, int); static void sis_dma_map_ring (void *, bus_dma_segment_t *, int, int); #ifdef SIS_USEIOSPACE #define SIS_RES SYS_RES_IOPORT #define SIS_RID SIS_PCI_LOIO #else #define SIS_RES SYS_RES_MEMORY #define SIS_RID SIS_PCI_LOMEM #endif static device_method_t sis_methods[] = { /* Device interface */ DEVMETHOD(device_probe, sis_probe), DEVMETHOD(device_attach, sis_attach), DEVMETHOD(device_detach, sis_detach), DEVMETHOD(device_shutdown, sis_shutdown), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* MII interface */ DEVMETHOD(miibus_readreg, sis_miibus_readreg), DEVMETHOD(miibus_writereg, sis_miibus_writereg), DEVMETHOD(miibus_statchg, sis_miibus_statchg), { 0, 0 } }; static driver_t sis_driver = { "sis", sis_methods, sizeof(struct sis_softc) }; static devclass_t sis_devclass; DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0); DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0); #define SIS_SETBIT(sc, reg, x) \ CSR_WRITE_4(sc, reg, \ CSR_READ_4(sc, reg) | (x)) #define SIS_CLRBIT(sc, reg, x) \ CSR_WRITE_4(sc, reg, \ CSR_READ_4(sc, reg) & ~(x)) #define SIO_SET(x) \ CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x) #define SIO_CLR(x) \ CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x) static void sis_dma_map_desc_next(arg, segs, nseg, error) void *arg; bus_dma_segment_t *segs; int nseg, error; { struct sis_desc *r; r = arg; r->sis_next = segs->ds_addr; return; } static void sis_dma_map_desc_ptr(arg, segs, nseg, error) void *arg; bus_dma_segment_t *segs; int nseg, error; { struct sis_desc *r; r = arg; r->sis_ptr = segs->ds_addr; return; } static void sis_dma_map_ring(arg, segs, nseg, error) void *arg; bus_dma_segment_t *segs; int nseg, error; { u_int32_t *p; p = arg; *p = segs->ds_addr; return; } /* * Routine to reverse the bits in a word. Stolen almost * verbatim from /usr/games/fortune. */ static u_int16_t sis_reverse(n) u_int16_t n; { n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa); n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc); n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0); n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00); return(n); } static void sis_delay(sc) struct sis_softc *sc; { int idx; for (idx = (300 / 33) + 1; idx > 0; idx--) CSR_READ_4(sc, SIS_CSR); return; } static void sis_eeprom_idle(sc) struct sis_softc *sc; { register int i; SIO_SET(SIS_EECTL_CSEL); sis_delay(sc); SIO_SET(SIS_EECTL_CLK); sis_delay(sc); for (i = 0; i < 25; i++) { SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); SIO_SET(SIS_EECTL_CLK); sis_delay(sc); } SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); SIO_CLR(SIS_EECTL_CSEL); sis_delay(sc); CSR_WRITE_4(sc, SIS_EECTL, 0x00000000); return; } /* * Send a read command and address to the EEPROM, check for ACK. */ static void sis_eeprom_putbyte(sc, addr) struct sis_softc *sc; int addr; { register int d, i; d = addr | SIS_EECMD_READ; /* * Feed in each bit and stobe the clock. */ for (i = 0x400; i; i >>= 1) { if (d & i) { SIO_SET(SIS_EECTL_DIN); } else { SIO_CLR(SIS_EECTL_DIN); } sis_delay(sc); SIO_SET(SIS_EECTL_CLK); sis_delay(sc); SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); } return; } /* * Read a word of data stored in the EEPROM at address 'addr.' */ static void sis_eeprom_getword(sc, addr, dest) struct sis_softc *sc; int addr; u_int16_t *dest; { register int i; u_int16_t word = 0; /* Force EEPROM to idle state. */ sis_eeprom_idle(sc); /* Enter EEPROM access mode. */ sis_delay(sc); SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); SIO_SET(SIS_EECTL_CSEL); sis_delay(sc); /* * Send address of word we want to read. */ sis_eeprom_putbyte(sc, addr); /* * Start reading bits from EEPROM. */ for (i = 0x8000; i; i >>= 1) { SIO_SET(SIS_EECTL_CLK); sis_delay(sc); if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) word |= i; sis_delay(sc); SIO_CLR(SIS_EECTL_CLK); sis_delay(sc); } /* Turn off EEPROM access mode. */ sis_eeprom_idle(sc); *dest = word; return; } /* * Read a sequence of words from the EEPROM. */ static void sis_read_eeprom(sc, dest, off, cnt, swap) struct sis_softc *sc; caddr_t dest; int off; int cnt; int swap; { int i; u_int16_t word = 0, *ptr; for (i = 0; i < cnt; i++) { sis_eeprom_getword(sc, off + i, &word); ptr = (u_int16_t *)(dest + (i * 2)); if (swap) *ptr = ntohs(word); else *ptr = word; } return; } #ifdef __i386__ static device_t sis_find_bridge(dev) device_t dev; { devclass_t pci_devclass; device_t *pci_devices; int pci_count = 0; device_t *pci_children; int pci_childcount = 0; device_t *busp, *childp; device_t child = NULL; int i, j; if ((pci_devclass = devclass_find("pci")) == NULL) return(NULL); devclass_get_devices(pci_devclass, &pci_devices, &pci_count); for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) { pci_childcount = 0; device_get_children(*busp, &pci_children, &pci_childcount); for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { if (pci_get_vendor(*childp) == SIS_VENDORID && pci_get_device(*childp) == 0x0008) { child = *childp; goto done; } } } done: free(pci_devices, M_TEMP); free(pci_children, M_TEMP); return(child); } static void sis_read_cmos(sc, dev, dest, off, cnt) struct sis_softc *sc; device_t dev; caddr_t dest; int off; int cnt; { device_t bridge; u_int8_t reg; int i; bus_space_tag_t btag; bridge = sis_find_bridge(dev); if (bridge == NULL) return; reg = pci_read_config(bridge, 0x48, 1); pci_write_config(bridge, 0x48, reg|0x40, 1); /* XXX */ btag = I386_BUS_SPACE_IO; for (i = 0; i < cnt; i++) { bus_space_write_1(btag, 0x0, 0x70, i + off); *(dest + i) = bus_space_read_1(btag, 0x0, 0x71); } pci_write_config(bridge, 0x48, reg & ~0x40, 1); return; } static void sis_read_mac(sc, dev, dest) struct sis_softc *sc; device_t dev; caddr_t dest; { u_int32_t filtsave, csrsave; filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); csrsave = CSR_READ_4(sc, SIS_CSR); CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave); CSR_WRITE_4(sc, SIS_CSR, 0); CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA); CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1); ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA); CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); CSR_WRITE_4(sc, SIS_CSR, csrsave); return; } #endif /* * Sync the PHYs by setting data bit and strobing the clock 32 times. */ static void sis_mii_sync(sc) struct sis_softc *sc; { register int i; SIO_SET(SIS_MII_DIR|SIS_MII_DATA); for (i = 0; i < 32; i++) { SIO_SET(SIS_MII_CLK); DELAY(1); SIO_CLR(SIS_MII_CLK); DELAY(1); } return; } /* * Clock a series of bits through the MII. */ static void sis_mii_send(sc, bits, cnt) struct sis_softc *sc; u_int32_t bits; int cnt; { int i; SIO_CLR(SIS_MII_CLK); for (i = (0x1 << (cnt - 1)); i; i >>= 1) { if (bits & i) { SIO_SET(SIS_MII_DATA); } else { SIO_CLR(SIS_MII_DATA); } DELAY(1); SIO_CLR(SIS_MII_CLK); DELAY(1); SIO_SET(SIS_MII_CLK); } } /* * Read an PHY register through the MII. */ static int sis_mii_readreg(sc, frame) struct sis_softc *sc; struct sis_mii_frame *frame; { int i, ack, s; s = splimp(); /* * Set up frame for RX. */ frame->mii_stdelim = SIS_MII_STARTDELIM; frame->mii_opcode = SIS_MII_READOP; frame->mii_turnaround = 0; frame->mii_data = 0; /* * Turn on data xmit. */ SIO_SET(SIS_MII_DIR); sis_mii_sync(sc); /* * Send command/address info. */ sis_mii_send(sc, frame->mii_stdelim, 2); sis_mii_send(sc, frame->mii_opcode, 2); sis_mii_send(sc, frame->mii_phyaddr, 5); sis_mii_send(sc, frame->mii_regaddr, 5); /* Idle bit */ SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); DELAY(1); SIO_SET(SIS_MII_CLK); DELAY(1); /* Turn off xmit. */ SIO_CLR(SIS_MII_DIR); /* Check for ack */ SIO_CLR(SIS_MII_CLK); DELAY(1); ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; SIO_SET(SIS_MII_CLK); DELAY(1); /* * Now try reading data bits. If the ack failed, we still * need to clock through 16 cycles to keep the PHY(s) in sync. */ if (ack) { for(i = 0; i < 16; i++) { SIO_CLR(SIS_MII_CLK); DELAY(1); SIO_SET(SIS_MII_CLK); DELAY(1); } goto fail; } for (i = 0x8000; i; i >>= 1) { SIO_CLR(SIS_MII_CLK); DELAY(1); if (!ack) { if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA) frame->mii_data |= i; DELAY(1); } SIO_SET(SIS_MII_CLK); DELAY(1); } fail: SIO_CLR(SIS_MII_CLK); DELAY(1); SIO_SET(SIS_MII_CLK); DELAY(1); splx(s); if (ack) return(1); return(0); } /* * Write to a PHY register through the MII. */ static int sis_mii_writereg(sc, frame) struct sis_softc *sc; struct sis_mii_frame *frame; { int s; s = splimp(); /* * Set up frame for TX. */ frame->mii_stdelim = SIS_MII_STARTDELIM; frame->mii_opcode = SIS_MII_WRITEOP; frame->mii_turnaround = SIS_MII_TURNAROUND; /* * Turn on data output. */ SIO_SET(SIS_MII_DIR); sis_mii_sync(sc); sis_mii_send(sc, frame->mii_stdelim, 2); sis_mii_send(sc, frame->mii_opcode, 2); sis_mii_send(sc, frame->mii_phyaddr, 5); sis_mii_send(sc, frame->mii_regaddr, 5); sis_mii_send(sc, frame->mii_turnaround, 2); sis_mii_send(sc, frame->mii_data, 16); /* Idle bit. */ SIO_SET(SIS_MII_CLK); DELAY(1); SIO_CLR(SIS_MII_CLK); DELAY(1); /* * Turn off xmit. */ SIO_CLR(SIS_MII_DIR); splx(s); return(0); } static int sis_miibus_readreg(dev, phy, reg) device_t dev; int phy, reg; { struct sis_softc *sc; struct sis_mii_frame frame; sc = device_get_softc(dev); if (sc->sis_type == SIS_TYPE_83815) { if (phy != 0) return(0); /* * The NatSemi chip can take a while after * a reset to come ready, during which the BMSR * returns a value of 0. This is *never* supposed * to happen: some of the BMSR bits are meant to * be hardwired in the on position, and this can * confuse the miibus code a bit during the probe * and attach phase. So we make an effort to check * for this condition and wait for it to clear. */ if (!CSR_READ_4(sc, NS_BMSR)) DELAY(1000); return CSR_READ_4(sc, NS_BMCR + (reg * 4)); } /* * Chipsets < SIS_635 seem not to be able to read/write * through mdio. Use the enhanced PHY access register * again for them. */ if (sc->sis_type == SIS_TYPE_900 && sc->sis_rev < SIS_REV_635) { int i, val = 0; if (phy != 0) return(0); CSR_WRITE_4(sc, SIS_PHYCTL, (phy << 11) | (reg << 6) | SIS_PHYOP_READ); SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); for (i = 0; i < SIS_TIMEOUT; i++) { if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) break; } if (i == SIS_TIMEOUT) { printf("sis%d: PHY failed to come ready\n", sc->sis_unit); return(0); } val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF; if (val == 0xFFFF) return(0); return(val); } else { bzero((char *)&frame, sizeof(frame)); frame.mii_phyaddr = phy; frame.mii_regaddr = reg; sis_mii_readreg(sc, &frame); return(frame.mii_data); } } static int sis_miibus_writereg(dev, phy, reg, data) device_t dev; int phy, reg, data; { struct sis_softc *sc; struct sis_mii_frame frame; sc = device_get_softc(dev); if (sc->sis_type == SIS_TYPE_83815) { if (phy != 0) return(0); CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data); return(0); } /* * Chipsets < SIS_635 seem not to be able to read/write * through mdio. Use the enhanced PHY access register * again for them. */ if (sc->sis_type == SIS_TYPE_900 && sc->sis_rev < SIS_REV_635) { int i; if (phy != 0) return(0); CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) | (reg << 6) | SIS_PHYOP_WRITE); SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS); for (i = 0; i < SIS_TIMEOUT; i++) { if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS)) break; } if (i == SIS_TIMEOUT) printf("sis%d: PHY failed to come ready\n", sc->sis_unit); } else { bzero((char *)&frame, sizeof(frame)); frame.mii_phyaddr = phy; frame.mii_regaddr = reg; frame.mii_data = data; sis_mii_writereg(sc, &frame); } return(0); } static void sis_miibus_statchg(dev) device_t dev; { struct sis_softc *sc; sc = device_get_softc(dev); sis_init(sc); return; } static u_int32_t sis_crc(sc, addr) struct sis_softc *sc; caddr_t addr; { u_int32_t crc, carry; int i, j; u_int8_t c; /* Compute CRC for the address value. */ crc = 0xFFFFFFFF; /* initial value */ for (i = 0; i < 6; i++) { c = *(addr + i); for (j = 0; j < 8; j++) { carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); crc <<= 1; c >>= 1; if (carry) crc = (crc ^ 0x04c11db6) | carry; } } /* * return the filter bit position * * The NatSemi chip has a 512-bit filter, which is * different than the SiS, so we special-case it. */ if (sc->sis_type == SIS_TYPE_83815) return (crc >> 23); else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) return (crc >> 24); else return (crc >> 25); } static void sis_setmulti_ns(sc) struct sis_softc *sc; { struct ifnet *ifp; struct ifmultiaddr *ifma; u_int32_t h = 0, i, filtsave; int bit, index; ifp = &sc->arpcom.ac_if; if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); return; } /* * We have to explicitly enable the multicast hash table * on the NatSemi chip if we want to use it, which we do. */ SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH); SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI); filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); /* first, zot all the existing hash bits */ for (i = 0; i < 32; i++) { CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2)); CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0); } TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); index = h >> 3; bit = h & 0x1F; CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index); if (bit > 0xF) bit -= 0x10; SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit)); } CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave); return; } static void sis_setmulti_sis(sc) struct sis_softc *sc; { struct ifnet *ifp; struct ifmultiaddr *ifma; u_int32_t h, i, n, ctl; u_int16_t hashes[16]; ifp = &sc->arpcom.ac_if; /* hash table size */ if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B) n = 16; else n = 8; ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE; if (ifp->if_flags & IFF_BROADCAST) ctl |= SIS_RXFILTCTL_BROAD; if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { ctl |= SIS_RXFILTCTL_ALLMULTI; if (ifp->if_flags & IFF_PROMISC) ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS; for (i = 0; i < n; i++) hashes[i] = ~0; } else { for (i = 0; i < n; i++) hashes[i] = 0; i = 0; TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = sis_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); hashes[h >> 4] |= 1 << (h & 0xf); i++; } if (i > n) { ctl |= SIS_RXFILTCTL_ALLMULTI; for (i = 0; i < n; i++) hashes[i] = ~0; } } for (i = 0; i < n; i++) { CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16); CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]); } CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl); } static void sis_reset(sc) struct sis_softc *sc; { register int i; SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET); for (i = 0; i < SIS_TIMEOUT; i++) { if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET)) break; } if (i == SIS_TIMEOUT) printf("sis%d: reset never completed\n", sc->sis_unit); /* Wait a little while for the chip to get its brains in order. */ DELAY(1000); /* * If this is a NetSemi chip, make sure to clear * PME mode. */ if (sc->sis_type == SIS_TYPE_83815) { CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS); CSR_WRITE_4(sc, NS_CLKRUN, 0); } return; } /* * Probe for an SiS chip. Check the PCI vendor and device * IDs against our list and return a device name if we find a match. */ static int sis_probe(dev) device_t dev; { struct sis_type *t; t = sis_devs; while(t->sis_name != NULL) { if ((pci_get_vendor(dev) == t->sis_vid) && (pci_get_device(dev) == t->sis_did)) { device_set_desc(dev, t->sis_name); return(0); } t++; } return(ENXIO); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int sis_attach(dev) device_t dev; { u_char eaddr[ETHER_ADDR_LEN]; struct sis_softc *sc; struct ifnet *ifp; int unit, error = 0, rid, waittime = 0; waittime = 0; sc = device_get_softc(dev); unit = device_get_unit(dev); sc->sis_self = dev; mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE); if (pci_get_device(dev) == SIS_DEVICEID_900) sc->sis_type = SIS_TYPE_900; if (pci_get_device(dev) == SIS_DEVICEID_7016) sc->sis_type = SIS_TYPE_7016; if (pci_get_vendor(dev) == NS_VENDORID) sc->sis_type = SIS_TYPE_83815; sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1); #ifndef BURN_BRIDGES /* * Handle power management nonsense. */ if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { u_int32_t iobase, membase, irq; /* Save important PCI config data. */ iobase = pci_read_config(dev, SIS_PCI_LOIO, 4); membase = pci_read_config(dev, SIS_PCI_LOMEM, 4); irq = pci_read_config(dev, SIS_PCI_INTLINE, 4); /* Reset the power state. */ printf("sis%d: chip is in D%d power mode " "-- setting to D0\n", unit, pci_get_powerstate(dev)); pci_set_powerstate(dev, PCI_POWERSTATE_D0); /* Restore PCI config data. */ pci_write_config(dev, SIS_PCI_LOIO, iobase, 4); pci_write_config(dev, SIS_PCI_LOMEM, membase, 4); pci_write_config(dev, SIS_PCI_INTLINE, irq, 4); } #endif /* * Map control/status registers. */ pci_enable_busmaster(dev); rid = SIS_RID; sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid, 0, ~0, 1, RF_ACTIVE); if (sc->sis_res == NULL) { printf("sis%d: couldn't map ports/memory\n", unit); error = ENXIO; goto fail; } sc->sis_btag = rman_get_bustag(sc->sis_res); sc->sis_bhandle = rman_get_bushandle(sc->sis_res); /* Allocate interrupt */ rid = 0; sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); if (sc->sis_irq == NULL) { printf("sis%d: couldn't map interrupt\n", unit); error = ENXIO; goto fail; } /* Reset the adapter. */ sis_reset(sc); if (sc->sis_type == SIS_TYPE_900 && (sc->sis_rev == SIS_REV_635 || sc->sis_rev == SIS_REV_900B)) { SIO_SET(SIS_CFG_RND_CNT); SIO_SET(SIS_CFG_PERR_DETECT); } /* * Get station address from the EEPROM. */ switch (pci_get_vendor(dev)) { case NS_VENDORID: sc->sis_srr = CSR_READ_4(sc, NS_SRR); /* We can't update the device description, so spew */ if (sc->sis_srr == NS_SRR_15C) device_printf(dev, "Silicon Revision: DP83815C\n"); else if (sc->sis_srr == NS_SRR_15D) device_printf(dev, "Silicon Revision: DP83815D\n"); else if (sc->sis_srr == NS_SRR_16A) device_printf(dev, "Silicon Revision: DP83816A\n"); else device_printf(dev, "Silicon Revision %x\n", sc->sis_srr); /* * Reading the MAC address out of the EEPROM on * the NatSemi chip takes a bit more work than * you'd expect. The address spans 4 16-bit words, * with the first word containing only a single bit. * You have to shift everything over one bit to * get it aligned properly. Also, the bits are * stored backwards (the LSB is really the MSB, * and so on) so you have to reverse them in order * to get the MAC address into the form we want. * Why? Who the hell knows. */ { u_int16_t tmp[4]; sis_read_eeprom(sc, (caddr_t)&tmp, NS_EE_NODEADDR, 4, 0); /* Shift everything over one bit. */ tmp[3] = tmp[3] >> 1; tmp[3] |= tmp[2] << 15; tmp[2] = tmp[2] >> 1; tmp[2] |= tmp[1] << 15; tmp[1] = tmp[1] >> 1; tmp[1] |= tmp[0] << 15; /* Now reverse all the bits. */ tmp[3] = sis_reverse(tmp[3]); tmp[2] = sis_reverse(tmp[2]); tmp[1] = sis_reverse(tmp[1]); bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN); } break; case SIS_VENDORID: default: #ifdef __i386__ /* * If this is a SiS 630E chipset with an embedded * SiS 900 controller, we have to read the MAC address * from the APC CMOS RAM. Our method for doing this * is very ugly since we have to reach out and grab * ahold of hardware for which we cannot properly * allocate resources. This code is only compiled on * the i386 architecture since the SiS 630E chipset * is for x86 motherboards only. Note that there are * a lot of magic numbers in this hack. These are * taken from SiS's Linux driver. I'd like to replace * them with proper symbolic definitions, but that * requires some datasheets that I don't have access * to at the moment. */ if (sc->sis_rev == SIS_REV_630S || sc->sis_rev == SIS_REV_630E || sc->sis_rev == SIS_REV_630EA1) sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6); else if (sc->sis_rev == SIS_REV_635 || sc->sis_rev == SIS_REV_630ET) sis_read_mac(sc, dev, (caddr_t)&eaddr); else if (sc->sis_rev == SIS_REV_96x) { /* Allow to read EEPROM from LAN. It is shared * between a 1394 controller and the NIC and each * time we access it, we need to set SIS_EECMD_REQ. */ SIO_SET(SIS_EECMD_REQ); for (waittime = 0; waittime < SIS_TIMEOUT; waittime++) { /* Force EEPROM to idle state. */ sis_eeprom_idle(sc); if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) { sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); break; } DELAY(1); } /* * Set SIS_EECTL_CLK to high, so a other master * can operate on the i2c bus. */ SIO_SET(SIS_EECTL_CLK); /* Refuse EEPROM access by LAN */ SIO_SET(SIS_EECMD_DONE); } else #endif sis_read_eeprom(sc, (caddr_t)&eaddr, SIS_EE_NODEADDR, 3, 0); break; } /* * A SiS chip was detected. Inform the world. */ printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":"); sc->sis_unit = unit; callout_init(&sc->sis_stat_ch, CALLOUT_MPSAFE); bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); /* * Allocate the parent bus DMA tag appropriate for PCI. */ #define SIS_NSEG_NEW 32 error = bus_dma_tag_create(NULL, /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */ BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ BUS_DMA_ALLOCNOW, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->sis_parent_tag); if (error) goto fail; /* * Now allocate a tag for the DMA descriptor lists and a chunk * of DMA-able memory based on the tag. Also obtain the physical * addresses of the RX and TX ring, which we'll need later. * All of our lists are allocated as a contiguous block * of memory. */ error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */ BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 0, /* flags */ busdma_lock_mutex, /* lockfunc */ &Giant, /* lockarg */ &sc->sis_ldata.sis_rx_tag); if (error) goto fail; error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag, (void **)&sc->sis_ldata.sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->sis_ldata.sis_rx_dmamap); if (error) { printf("sis%d: no memory for rx list buffers!\n", unit); bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); sc->sis_ldata.sis_rx_tag = NULL; goto fail; } error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, &(sc->sis_ldata.sis_rx_list[0]), sizeof(struct sis_desc), sis_dma_map_ring, &sc->sis_cdata.sis_rx_paddr, 0); if (error) { printf("sis%d: cannot get address of the rx ring!\n", unit); bus_dmamem_free(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); sc->sis_ldata.sis_rx_tag = NULL; goto fail; } error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */ BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 0, /* flags */ busdma_lock_mutex, /* lockfunc */ &Giant, /* lockarg */ &sc->sis_ldata.sis_tx_tag); if (error) goto fail; error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag, (void **)&sc->sis_ldata.sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->sis_ldata.sis_tx_dmamap); if (error) { printf("sis%d: no memory for tx list buffers!\n", unit); bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); sc->sis_ldata.sis_tx_tag = NULL; goto fail; } error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, &(sc->sis_ldata.sis_tx_list[0]), sizeof(struct sis_desc), sis_dma_map_ring, &sc->sis_cdata.sis_tx_paddr, 0); if (error) { printf("sis%d: cannot get address of the tx ring!\n", unit); bus_dmamem_free(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); sc->sis_ldata.sis_tx_tag = NULL; goto fail; } error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, 1, /* maxsize,nsegments */ BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 0, /* flags */ busdma_lock_mutex, /* lockfunc */ &Giant, /* lockarg */ &sc->sis_tag); if (error) goto fail; /* * Obtain the physical addresses of the RX and TX * rings which we'll need later in the init routine. */ ifp = &sc->arpcom.ac_if; ifp->if_softc = sc; ifp->if_unit = unit; ifp->if_name = "sis"; ifp->if_mtu = ETHERMTU; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = sis_ioctl; ifp->if_output = ether_output; ifp->if_start = sis_start; ifp->if_watchdog = sis_watchdog; ifp->if_init = sis_init; ifp->if_baudrate = 10000000; ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1; /* * Do MII setup. */ if (mii_phy_probe(dev, &sc->sis_miibus, sis_ifmedia_upd, sis_ifmedia_sts)) { printf("sis%d: MII without any PHY!\n", sc->sis_unit); error = ENXIO; goto fail; } /* * Call MI attach routine. */ ether_ifattach(ifp, eaddr); /* * Tell the upper layer(s) we support long frames. */ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); ifp->if_capabilities |= IFCAP_VLAN_MTU; /* Hook interrupt last to avoid having to lock softc */ - error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET, + error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET | INTR_MPSAFE, sis_intr, sc, &sc->sis_intrhand); if (error) { printf("sis%d: couldn't set up irq\n", unit); ether_ifdetach(ifp); goto fail; } fail: if (error) sis_detach(dev); return(error); } /* * Shutdown hardware and free up resources. This can be called any * time after the mutex has been initialized. It is called in both * the error case in attach and the normal detach case so it needs * to be careful about only freeing resources that have actually been * allocated. */ static int sis_detach(dev) device_t dev; { struct sis_softc *sc; struct ifnet *ifp; sc = device_get_softc(dev); KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized")); SIS_LOCK(sc); ifp = &sc->arpcom.ac_if; /* These should only be active if attach succeeded. */ if (device_is_attached(dev)) { sis_reset(sc); sis_stop(sc); ether_ifdetach(ifp); } if (sc->sis_miibus) device_delete_child(dev, sc->sis_miibus); bus_generic_detach(dev); if (sc->sis_intrhand) bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand); if (sc->sis_irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq); if (sc->sis_res) bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res); if (sc->sis_ldata.sis_rx_tag) { bus_dmamap_unload(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap); bus_dmamem_free(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_list, sc->sis_ldata.sis_rx_dmamap); bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag); } if (sc->sis_ldata.sis_tx_tag) { bus_dmamap_unload(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap); bus_dmamem_free(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_list, sc->sis_ldata.sis_tx_dmamap); bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag); } if (sc->sis_parent_tag) bus_dma_tag_destroy(sc->sis_parent_tag); if (sc->sis_tag) bus_dma_tag_destroy(sc->sis_tag); SIS_UNLOCK(sc); mtx_destroy(&sc->sis_mtx); return(0); } /* * Initialize the transmit descriptors. */ static int sis_list_tx_init(sc) struct sis_softc *sc; { struct sis_list_data *ld; struct sis_ring_data *cd; int i, nexti; cd = &sc->sis_cdata; ld = &sc->sis_ldata; for (i = 0; i < SIS_TX_LIST_CNT; i++) { nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1; ld->sis_tx_list[i].sis_nextdesc = &ld->sis_tx_list[nexti]; bus_dmamap_load(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap, &ld->sis_tx_list[nexti], sizeof(struct sis_desc), sis_dma_map_desc_next, &ld->sis_tx_list[i], 0); ld->sis_tx_list[i].sis_mbuf = NULL; ld->sis_tx_list[i].sis_ptr = 0; ld->sis_tx_list[i].sis_ctl = 0; } cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0; bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); return(0); } /* * Initialize the RX descriptors and allocate mbufs for them. Note that * we arrange the descriptors in a closed ring, so that the last descriptor * points back to the first. */ static int sis_list_rx_init(sc) struct sis_softc *sc; { struct sis_list_data *ld; struct sis_ring_data *cd; int i,nexti; ld = &sc->sis_ldata; cd = &sc->sis_cdata; for (i = 0; i < SIS_RX_LIST_CNT; i++) { if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS) return(ENOBUFS); nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1; ld->sis_rx_list[i].sis_nextdesc = &ld->sis_rx_list[nexti]; bus_dmamap_load(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, &ld->sis_rx_list[nexti], sizeof(struct sis_desc), sis_dma_map_desc_next, &ld->sis_rx_list[i], 0); } bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap, BUS_DMASYNC_PREWRITE); cd->sis_rx_prod = 0; return(0); } /* * Initialize an RX descriptor and attach an MBUF cluster. */ static int sis_newbuf(sc, c, m) struct sis_softc *sc; struct sis_desc *c; struct mbuf *m; { if (c == NULL) return(EINVAL); if (m == NULL) { m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); if (m == NULL) return(ENOBUFS); } else m->m_data = m->m_ext.ext_buf; c->sis_mbuf = m; c->sis_ctl = SIS_RXLEN; bus_dmamap_create(sc->sis_tag, 0, &c->sis_map); bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES, sis_dma_map_desc_ptr, c, 0); bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE); return(0); } /* * A frame has been uploaded: pass the resulting mbuf chain up to * the higher level protocols. */ static void sis_rxeof(sc) struct sis_softc *sc; { struct mbuf *m; struct ifnet *ifp; struct sis_desc *cur_rx; int i, total_len = 0; u_int32_t rxstat; ifp = &sc->arpcom.ac_if; i = sc->sis_cdata.sis_rx_prod; while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) { #ifdef DEVICE_POLLING if (ifp->if_flags & IFF_POLLING) { if (sc->rxcycles <= 0) break; sc->rxcycles--; } #endif /* DEVICE_POLLING */ cur_rx = &sc->sis_ldata.sis_rx_list[i]; rxstat = cur_rx->sis_rxstat; bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map); bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map); m = cur_rx->sis_mbuf; cur_rx->sis_mbuf = NULL; total_len = SIS_RXBYTES(cur_rx); SIS_INC(i, SIS_RX_LIST_CNT); /* * If an error occurs, update stats, clear the * status word and leave the mbuf cluster in place: * it should simply get re-used next time this descriptor * comes up in the ring. */ if (!(rxstat & SIS_CMDSTS_PKT_OK)) { ifp->if_ierrors++; if (rxstat & SIS_RXSTAT_COLL) ifp->if_collisions++; sis_newbuf(sc, cur_rx, m); continue; } /* No errors; receive the packet. */ #ifdef __i386__ /* * On the x86 we do not have alignment problems, so try to * allocate a new buffer for the receive ring, and pass up * the one where the packet is already, saving the expensive * copy done in m_devget(). * If we are on an architecture with alignment problems, or * if the allocation fails, then use m_devget and leave the * existing buffer in the receive ring. */ if (sis_newbuf(sc, cur_rx, NULL) == 0) m->m_pkthdr.len = m->m_len = total_len; else #endif { struct mbuf *m0; m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, NULL); sis_newbuf(sc, cur_rx, m); if (m0 == NULL) { ifp->if_ierrors++; continue; } m = m0; } ifp->if_ipackets++; m->m_pkthdr.rcvif = ifp; (*ifp->if_input)(ifp, m); } sc->sis_cdata.sis_rx_prod = i; return; } static void sis_rxeoc(sc) struct sis_softc *sc; { sis_rxeof(sc); sis_init(sc); return; } /* * A frame was downloaded to the chip. It's safe for us to clean up * the list buffers. */ static void sis_txeof(sc) struct sis_softc *sc; { struct ifnet *ifp; u_int32_t idx; ifp = &sc->arpcom.ac_if; /* * Go through our tx list and free mbufs for those * frames that have been transmitted. */ for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0; sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) { struct sis_desc *cur_tx = &sc->sis_ldata.sis_tx_list[idx]; if (SIS_OWNDESC(cur_tx)) break; if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) continue; if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) { ifp->if_oerrors++; if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS) ifp->if_collisions++; if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL) ifp->if_collisions++; } ifp->if_collisions += (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16; ifp->if_opackets++; if (cur_tx->sis_mbuf != NULL) { m_freem(cur_tx->sis_mbuf); cur_tx->sis_mbuf = NULL; bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map); bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map); } } if (idx != sc->sis_cdata.sis_tx_cons) { /* we freed up some buffers */ sc->sis_cdata.sis_tx_cons = idx; ifp->if_flags &= ~IFF_OACTIVE; } ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5; return; } static void sis_tick(xsc) void *xsc; { struct sis_softc *sc; struct mii_data *mii; struct ifnet *ifp; sc = xsc; SIS_LOCK(sc); sc->in_tick = 1; ifp = &sc->arpcom.ac_if; mii = device_get_softc(sc->sis_miibus); mii_tick(mii); if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE && IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { sc->sis_link++; if (ifp->if_snd.ifq_head != NULL) sis_start(ifp); } callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); sc->in_tick = 0; SIS_UNLOCK(sc); return; } #ifdef DEVICE_POLLING static poll_handler_t sis_poll; static void sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) { struct sis_softc *sc = ifp->if_softc; SIS_LOCK(sc); if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ CSR_WRITE_4(sc, SIS_IER, 1); goto done; } /* * On the sis, reading the status register also clears it. * So before returning to intr mode we must make sure that all * possible pending sources of interrupts have been served. * In practice this means run to completion the *eof routines, * and then call the interrupt routine */ sc->rxcycles = count; sis_rxeof(sc); sis_txeof(sc); if (ifp->if_snd.ifq_head != NULL) sis_start(ifp); if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { u_int32_t status; /* Reading the ISR register clears all interrupts. */ status = CSR_READ_4(sc, SIS_ISR); if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) sis_rxeoc(sc); if (status & (SIS_ISR_RX_IDLE)) SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); if (status & SIS_ISR_SYSERR) { sis_reset(sc); sis_init(sc); } } done: SIS_UNLOCK(sc); return; } #endif /* DEVICE_POLLING */ static void sis_intr(arg) void *arg; { struct sis_softc *sc; struct ifnet *ifp; u_int32_t status; sc = arg; ifp = &sc->arpcom.ac_if; SIS_LOCK(sc); #ifdef DEVICE_POLLING if (ifp->if_flags & IFF_POLLING) goto done; if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */ CSR_WRITE_4(sc, SIS_IER, 0); goto done; } #endif /* DEVICE_POLLING */ /* Supress unwanted interrupts */ if (!(ifp->if_flags & IFF_UP)) { sis_stop(sc); goto done; } /* Disable interrupts. */ CSR_WRITE_4(sc, SIS_IER, 0); for (;;) { /* Reading the ISR register clears all interrupts. */ status = CSR_READ_4(sc, SIS_ISR); if ((status & SIS_INTRS) == 0) break; if (status & (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) ) sis_txeof(sc); if (status & (SIS_ISR_RX_DESC_OK|SIS_ISR_RX_OK|SIS_ISR_RX_IDLE)) sis_rxeof(sc); if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW)) sis_rxeoc(sc); if (status & (SIS_ISR_RX_IDLE)) SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); if (status & SIS_ISR_SYSERR) { sis_reset(sc); sis_init(sc); } } /* Re-enable interrupts. */ CSR_WRITE_4(sc, SIS_IER, 1); if (ifp->if_snd.ifq_head != NULL) sis_start(ifp); done: SIS_UNLOCK(sc); return; } /* * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data * pointers to the fragment pointers. */ static int sis_encap(sc, m_head, txidx) struct sis_softc *sc; struct mbuf **m_head; u_int32_t *txidx; { struct sis_desc *f = NULL; struct mbuf *m; int frag, cur, cnt = 0, chainlen = 0; /* * If there's no way we can send any packets, return now. */ if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2) return (ENOBUFS); /* * Count the number of frags in this chain to see if * we need to m_defrag. Since the descriptor list is shared * by all packets, we'll m_defrag long chains so that they * do not use up the entire list, even if they would fit. */ for (m = *m_head; m != NULL; m = m->m_next) chainlen++; if ((chainlen > SIS_TX_LIST_CNT / 4) || ((SIS_TX_LIST_CNT - (chainlen + sc->sis_cdata.sis_tx_cnt)) < 2)) { m = m_defrag(*m_head, M_DONTWAIT); if (m == NULL) return (ENOBUFS); *m_head = m; } /* * Start packing the mbufs in this chain into * the fragment pointers. Stop when we run out * of fragments or hit the end of the mbuf chain. */ cur = frag = *txidx; for (m = *m_head; m != NULL; m = m->m_next) { if (m->m_len != 0) { if ((SIS_TX_LIST_CNT - (sc->sis_cdata.sis_tx_cnt + cnt)) < 2) return(ENOBUFS); f = &sc->sis_ldata.sis_tx_list[frag]; f->sis_ctl = SIS_CMDSTS_MORE | m->m_len; bus_dmamap_create(sc->sis_tag, 0, &f->sis_map); bus_dmamap_load(sc->sis_tag, f->sis_map, mtod(m, void *), m->m_len, sis_dma_map_desc_ptr, f, 0); bus_dmamap_sync(sc->sis_tag, f->sis_map, BUS_DMASYNC_PREREAD); if (cnt != 0) f->sis_ctl |= SIS_CMDSTS_OWN; cur = frag; SIS_INC(frag, SIS_TX_LIST_CNT); cnt++; } } if (m != NULL) return(ENOBUFS); sc->sis_ldata.sis_tx_list[cur].sis_mbuf = *m_head; sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE; sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN; sc->sis_cdata.sis_tx_cnt += cnt; *txidx = frag; return(0); } /* * Main transmit routine. To avoid having to do mbuf copies, we put pointers * to the mbuf data regions directly in the transmit lists. We also save a * copy of the pointers since the transmit list fragment pointers are * physical addresses. */ static void sis_start(ifp) struct ifnet *ifp; { struct sis_softc *sc; struct mbuf *m_head = NULL; u_int32_t idx; sc = ifp->if_softc; SIS_LOCK(sc); if (!sc->sis_link) { SIS_UNLOCK(sc); return; } idx = sc->sis_cdata.sis_tx_prod; if (ifp->if_flags & IFF_OACTIVE) { SIS_UNLOCK(sc); return; } while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) { IF_DEQUEUE(&ifp->if_snd, m_head); if (m_head == NULL) break; if (sis_encap(sc, &m_head, &idx)) { IF_PREPEND(&ifp->if_snd, m_head); ifp->if_flags |= IFF_OACTIVE; break; } /* * If there's a BPF listener, bounce a copy of this frame * to him. */ BPF_MTAP(ifp, m_head); } /* Transmit */ sc->sis_cdata.sis_tx_prod = idx; SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE); /* * Set a timeout in case the chip goes out to lunch. */ ifp->if_timer = 5; SIS_UNLOCK(sc); return; } static void sis_init(xsc) void *xsc; { struct sis_softc *sc = xsc; struct ifnet *ifp = &sc->arpcom.ac_if; struct mii_data *mii; SIS_LOCK(sc); /* * Cancel pending I/O and free all RX/TX buffers. */ sis_stop(sc); #ifdef notyet if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) { /* * Configure 400usec of interrupt holdoff. This is based * on emperical tests on a Soekris 4801. */ CSR_WRITE_4(sc, NS_IHR, 0x100 | 4); } #endif mii = device_get_softc(sc->sis_miibus); /* Set MAC address */ if (sc->sis_type == SIS_TYPE_83815) { CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); } else { CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2); CSR_WRITE_4(sc, SIS_RXFILT_DATA, ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); } /* Init circular RX list. */ if (sis_list_rx_init(sc) == ENOBUFS) { printf("sis%d: initialization failed: no " "memory for rx buffers\n", sc->sis_unit); sis_stop(sc); SIS_UNLOCK(sc); return; } /* * Init tx descriptors. */ sis_list_tx_init(sc); /* * For the NatSemi chip, we have to explicitly enable the * reception of ARP frames, as well as turn on the 'perfect * match' filter where we store the station address, otherwise * we won't receive unicasts meant for this host. */ if (sc->sis_type == SIS_TYPE_83815) { SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP); SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT); } /* If we want promiscuous mode, set the allframes bit. */ if (ifp->if_flags & IFF_PROMISC) { SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); } else { SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS); } /* * Set the capture broadcast bit to capture broadcast frames. */ if (ifp->if_flags & IFF_BROADCAST) { SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); } else { SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD); } /* * Load the multicast filter. */ if (sc->sis_type == SIS_TYPE_83815) sis_setmulti_ns(sc); else sis_setmulti_sis(sc); /* Turn the receive filter on */ SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE); /* * Load the address of the RX and TX lists. */ CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr); CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr); /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of * the PCI bus. When this bit is set, the Max DMA Burst Size * for TX/RX DMA should be no larger than 16 double words. */ if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) { CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64); } else { CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256); } /* Accept Long Packets for VLAN support */ SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER); /* Set TX configuration */ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10); } else { CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100); } /* Set full/half duplex mode. */ if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { SIS_SETBIT(sc, SIS_TX_CFG, (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); } else { SIS_CLRBIT(sc, SIS_TX_CFG, (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR)); SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS); } if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A && IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { uint32_t reg; /* * Some DP83815s experience problems when used with short * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This * sequence adjusts the DSP's signal attenuation to fix the * problem. */ CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); reg = CSR_READ_4(sc, NS_PHY_DSPCFG); CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000); DELAY(100); reg = CSR_READ_4(sc, NS_PHY_TDATA); if ((reg & 0x0080) == 0 || (reg & 0xff) >= 0xd8) { device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg); CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8); SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20); } CSR_WRITE_4(sc, NS_PHY_PAGE, 0); } /* * Enable interrupts. */ CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS); #ifdef DEVICE_POLLING /* * ... only enable interrupts if we are not polling, make sure * they are off otherwise. */ if (ifp->if_flags & IFF_POLLING) CSR_WRITE_4(sc, SIS_IER, 0); else #endif /* DEVICE_POLLING */ CSR_WRITE_4(sc, SIS_IER, 1); /* Enable receiver and transmitter. */ SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); #ifdef notdef mii_mediachg(mii); #endif /* * Page 75 of the DP83815 manual recommends the * following register settings "for optimum * performance." Note however that at least three * of the registers are listed as "reserved" in * the register map, so who knows what they do. */ if (sc->sis_type == SIS_TYPE_83815) { CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); CSR_WRITE_4(sc, NS_PHY_CR, 0x189C); CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000); CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040); CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C); } ifp->if_flags |= IFF_RUNNING; ifp->if_flags &= ~IFF_OACTIVE; if (!sc->in_tick) callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc); SIS_UNLOCK(sc); return; } /* * Set media options. */ static int sis_ifmedia_upd(ifp) struct ifnet *ifp; { struct sis_softc *sc; struct mii_data *mii; sc = ifp->if_softc; mii = device_get_softc(sc->sis_miibus); sc->sis_link = 0; if (mii->mii_instance) { struct mii_softc *miisc; LIST_FOREACH(miisc, &mii->mii_phys, mii_list) mii_phy_reset(miisc); } mii_mediachg(mii); return(0); } /* * Report current media status. */ static void sis_ifmedia_sts(ifp, ifmr) struct ifnet *ifp; struct ifmediareq *ifmr; { struct sis_softc *sc; struct mii_data *mii; sc = ifp->if_softc; mii = device_get_softc(sc->sis_miibus); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; return; } static int sis_ioctl(ifp, command, data) struct ifnet *ifp; u_long command; caddr_t data; { struct sis_softc *sc = ifp->if_softc; struct ifreq *ifr = (struct ifreq *) data; struct mii_data *mii; int error = 0; switch(command) { case SIOCSIFFLAGS: if (ifp->if_flags & IFF_UP) { sis_init(sc); } else { if (ifp->if_flags & IFF_RUNNING) sis_stop(sc); } error = 0; break; case SIOCADDMULTI: case SIOCDELMULTI: SIS_LOCK(sc); if (sc->sis_type == SIS_TYPE_83815) sis_setmulti_ns(sc); else sis_setmulti_sis(sc); SIS_UNLOCK(sc); error = 0; break; case SIOCGIFMEDIA: case SIOCSIFMEDIA: mii = device_get_softc(sc->sis_miibus); SIS_LOCK(sc); error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); SIS_UNLOCK(sc); break; default: error = ether_ioctl(ifp, command, data); break; } return(error); } static void sis_watchdog(ifp) struct ifnet *ifp; { struct sis_softc *sc; sc = ifp->if_softc; SIS_LOCK(sc); ifp->if_oerrors++; printf("sis%d: watchdog timeout\n", sc->sis_unit); sis_stop(sc); sis_reset(sc); sis_init(sc); if (ifp->if_snd.ifq_head != NULL) sis_start(ifp); SIS_UNLOCK(sc); return; } /* * Stop the adapter and free any mbufs allocated to the * RX and TX lists. */ static void sis_stop(sc) struct sis_softc *sc; { register int i; struct ifnet *ifp; SIS_LOCK(sc); ifp = &sc->arpcom.ac_if; ifp->if_timer = 0; callout_stop(&sc->sis_stat_ch); ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); #ifdef DEVICE_POLLING ether_poll_deregister(ifp); #endif CSR_WRITE_4(sc, SIS_IER, 0); CSR_WRITE_4(sc, SIS_IMR, 0); SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE); DELAY(1000); CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0); CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0); sc->sis_link = 0; /* * Free data in the RX lists. */ for (i = 0; i < SIS_RX_LIST_CNT; i++) { if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) { bus_dmamap_unload(sc->sis_tag, sc->sis_ldata.sis_rx_list[i].sis_map); bus_dmamap_destroy(sc->sis_tag, sc->sis_ldata.sis_rx_list[i].sis_map); m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf); sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL; } } bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list)); /* * Free the TX list buffers. */ for (i = 0; i < SIS_TX_LIST_CNT; i++) { if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) { bus_dmamap_unload(sc->sis_tag, sc->sis_ldata.sis_tx_list[i].sis_map); bus_dmamap_destroy(sc->sis_tag, sc->sis_ldata.sis_tx_list[i].sis_map); m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf); sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL; } } bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list)); SIS_UNLOCK(sc); return; } /* * Stop all chip I/O so that the kernel's probe routines don't * get confused by errant DMAs when rebooting. */ static void sis_shutdown(dev) device_t dev; { struct sis_softc *sc; sc = device_get_softc(dev); SIS_LOCK(sc); sis_reset(sc); sis_stop(sc); SIS_UNLOCK(sc); return; }