Index: head/sys/dev/ata/ata-all.h =================================================================== --- head/sys/dev/ata/ata-all.h (revision 121309) +++ head/sys/dev/ata/ata-all.h (revision 121310) @@ -1,553 +1,555 @@ /*- * Copyright (c) 1998 - 2003 Søren Schmidt * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification, immediately at the beginning of the file. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* ATA register defines */ #define ATA_DATA 0x00 /* data register */ #define ATA_ERROR 0x01 /* (R) error register */ #define ATA_E_ILI 0x01 /* illegal length */ #define ATA_E_NM 0x02 /* no media */ #define ATA_E_ABORT 0x04 /* command aborted */ #define ATA_E_MCR 0x08 /* media change request */ #define ATA_E_IDNF 0x10 /* ID not found */ #define ATA_E_MC 0x20 /* media changed */ #define ATA_E_UNC 0x40 /* uncorrectable data */ #define ATA_E_ICRC 0x80 /* UDMA crc error */ #define ATA_E_MASK 0x0f /* error mask */ #define ATA_SK_MASK 0xf0 /* sense key mask */ #define ATA_SK_NO_SENSE 0x00 /* no specific sense key info */ #define ATA_SK_RECOVERED_ERROR 0x10 /* command OK, data recovered */ #define ATA_SK_NOT_READY 0x20 /* no access to drive */ #define ATA_SK_MEDIUM_ERROR 0x30 /* non-recovered data error */ #define ATA_SK_HARDWARE_ERROR 0x40 /* non-recoverable HW failure */ #define ATA_SK_ILLEGAL_REQUEST 0x50 /* invalid command param(s) */ #define ATA_SK_UNIT_ATTENTION 0x60 /* media changed */ #define ATA_SK_DATA_PROTECT 0x70 /* write protect */ #define ATA_SK_BLANK_CHECK 0x80 /* blank check */ #define ATA_SK_VENDOR_SPECIFIC 0x90 /* vendor specific skey */ #define ATA_SK_COPY_ABORTED 0xa0 /* copy aborted */ #define ATA_SK_ABORTED_COMMAND 0xb0 /* command aborted, try again */ #define ATA_SK_EQUAL 0xc0 /* equal */ #define ATA_SK_VOLUME_OVERFLOW 0xd0 /* volume overflow */ #define ATA_SK_MISCOMPARE 0xe0 /* data dont match the medium */ #define ATA_SK_RESERVED 0xf0 #define ATA_FEATURE 0x01 /* (W) feature register */ #define ATA_F_DMA 0x01 /* enable DMA */ #define ATA_F_OVL 0x02 /* enable overlap */ #define ATA_COUNT 0x02 /* (W) sector count */ #define ATA_IREASON 0x02 /* (R) interrupt reason */ #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ #define ATA_I_IN 0x02 /* read (1) | write (0) */ #define ATA_I_RELEASE 0x04 /* released bus (1) */ #define ATA_I_TAGMASK 0xf8 /* tag mask */ #define ATA_SECTOR 0x03 /* sector # */ #define ATA_CYL_LSB 0x04 /* cylinder# LSB */ #define ATA_CYL_MSB 0x05 /* cylinder# MSB */ #define ATA_DRIVE 0x06 /* Sector/Drive/Head register */ #define ATA_D_LBA 0x40 /* use LBA addressing */ #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ #define ATA_CMD 0x07 /* command register */ #define ATA_STATUS 0x07 /* status register */ #define ATA_S_ERROR 0x01 /* error */ #define ATA_S_INDEX 0x02 /* index */ #define ATA_S_CORR 0x04 /* data corrected */ #define ATA_S_DRQ 0x08 /* data request */ #define ATA_S_DSC 0x10 /* drive seek completed */ #define ATA_S_SERVICE 0x10 /* drive needs service */ #define ATA_S_DWF 0x20 /* drive write fault */ #define ATA_S_DMA 0x20 /* DMA ready */ #define ATA_S_READY 0x40 /* drive ready */ #define ATA_S_BUSY 0x80 /* busy */ #define ATA_ALTSTAT 0x08 /* alternate status register */ #define ATA_ALTOFFSET 0x206 /* alternate registers offset */ #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */ #define ATA_PC98_ALTOFFSET 0x10c /* do for PC98 devices */ #define ATA_A_IDS 0x02 /* disable interrupts */ #define ATA_A_RESET 0x04 /* RESET controller */ #define ATA_A_4BIT 0x08 /* 4 head bits */ /* ATAPI misc defines */ #define ATAPI_MAGIC_LSB 0x14 #define ATAPI_MAGIC_MSB 0xeb #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) #define ATAPI_P_WRITE (ATA_S_DRQ) #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) #define ATAPI_P_ABORT 0 /* misc defines */ #define ATA_PRIMARY 0x1f0 #define ATA_SECONDARY 0x170 #define ATA_PC98_BANK 0x432 #define ATA_IOSIZE 0x08 #define ATA_PC98_IOSIZE 0x10 #define ATA_ALTIOSIZE 0x01 #define ATA_BMIOSIZE 0x08 #define ATA_PC98_BANKIOSIZE 0x01 #define ATA_IOADDR_RID 0 #define ATA_ALTADDR_RID 1 #define ATA_BMADDR_RID 0x20 #define ATA_PC98_ALTADDR_RID 8 #define ATA_PC98_BANKADDR_RID 9 #define ATA_IRQ_RID 0 #define ATA_DEV(device) ((device == ATA_MASTER) ? 0 : 1) /* busmaster DMA related defines */ #define ATA_DMA_ENTRIES 256 #define ATA_DMA_EOT 0x80000000 #define ATA_BMCMD_PORT 0x09 #define ATA_BMCMD_START_STOP 0x01 #define ATA_BMCMD_WRITE_READ 0x08 #define ATA_BMCTL_PORT 0x09 #define ATA_BMDEVSPEC_0 0x0a #define ATA_BMSTAT_PORT 0x0b #define ATA_BMSTAT_ACTIVE 0x01 #define ATA_BMSTAT_ERROR 0x02 #define ATA_BMSTAT_INTERRUPT 0x04 #define ATA_BMSTAT_MASK 0x07 #define ATA_BMSTAT_DMA_MASTER 0x20 #define ATA_BMSTAT_DMA_SLAVE 0x40 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 #define ATA_BMDEVSPEC_1 0x0c #define ATA_BMDTP_PORT 0x0d #define ATA_IDX_ADDR 0x0e #define ATA_IDX_DATA 0x0f #define ATA_MAX_RES 0x10 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) #define ATA_OP_CONTINUES 0 #define ATA_OP_FINISHED 1 struct ata_request { struct ata_device *device; /* ptr to device softc */ void *driver; /* driver specific */ union { struct { u_int8_t command; /* command reg */ u_int8_t feature; /* feature reg */ u_int64_t lba; /* lba reg */ u_int16_t count; /* count reg */ } ata; struct { u_int8_t ccb[16]; /* ATAPI command block */ } atapi; } u; u_int8_t status; /* ATA status */ u_int8_t error; /* ATA error */ u_int8_t dmastat; /* DMA status */ u_int32_t bytecount; /* bytes to transfer */ u_int32_t transfersize; /* bytes pr transfer */ u_int32_t donecount; /* bytes transferred */ caddr_t data; /* pointer to data buf */ int flags; #define ATA_R_DONE 0x0001 #define ATA_R_CONTROL 0x0002 #define ATA_R_READ 0x0004 #define ATA_R_WRITE 0x0008 #define ATA_R_ATAPI 0x0010 #define ATA_R_QUIET 0x0020 #define ATA_R_DMA 0x0040 #define ATA_R_ORDERED 0x0100 #define ATA_R_AT_HEAD 0x0200 #define ATA_R_REQUEUE 0x0400 #define ATA_R_SKIPSTART 0x0800 void (*callback)(struct ata_request *request); int retries; /* retry count */ int timeout; /* timeout for this cmd */ struct callout_handle timeout_handle; /* handle for untimeout */ int result; /* result error code */ struct task task; /* task management */ TAILQ_ENTRY(ata_request) sequence; /* sequence management */ TAILQ_ENTRY(ata_request) chain; /* list management */ }; /* structure describing an ATA/ATAPI device */ struct ata_device { struct ata_channel *channel; int unit; /* unit number */ #define ATA_MASTER 0x00 #define ATA_SLAVE 0x10 char *name; /* device name */ struct ata_params *param; /* ata param structure */ void *softc; /* ptr to softc for device */ void (*attach)(struct ata_device *atadev); void (*detach)(struct ata_device *atadev); void (*start)(struct ata_device *atadev); int flags; #define ATA_D_USE_CHS 0x0001 #define ATA_D_DETACHING 0x0002 #define ATA_D_MEDIA_CHANGED 0x0004 #define ATA_D_ENC_PRESENT 0x0008 int cmd; /* last cmd executed */ int mode; /* transfermode */ void (*setmode)(struct ata_device *atadev, int mode); }; /* structure for holding DMA address data */ struct ata_dmaentry { u_int32_t base; u_int32_t count; }; /* structure holding DMA related information */ struct ata_dma { bus_dma_tag_t dmatag; /* parent DMA tag */ bus_dma_tag_t cdmatag; /* control DMA tag */ bus_dmamap_t cdmamap; /* control DMA map */ bus_dma_tag_t ddmatag; /* data DMA tag */ bus_dmamap_t ddmamap; /* data DMA map */ struct ata_dmaentry *dmatab; /* DMA transfer table */ bus_addr_t mdmatab; /* bus address of dmatab */ u_int32_t alignment; /* DMA engine alignment */ u_int32_t max_iosize; /* DMA engine max IO size */ + u_int32_t cur_iosize; /* DMA engine current IO size */ int flags; #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ #define ATA_DMA_READ 0x02 /* transaction is a read */ void (*alloc)(struct ata_channel *ch); void (*free)(struct ata_channel *ch); - int (*setup)(struct ata_device *atadev, caddr_t data, int32_t count); - int (*start)(struct ata_channel *ch, caddr_t data, int32_t count, int dir); + int (*load)(struct ata_device *atadev, caddr_t data, int32_t count,int dir); + int (*unload)(struct ata_channel *ch); + int (*start)(struct ata_channel *ch); int (*stop)(struct ata_channel *ch); }; /* structure holding lowlevel functions */ struct ata_lowlevel { void (*reset)(struct ata_channel *ch); int (*transaction)(struct ata_request *request); void (*interrupt)(void *channel); }; /* structure holding resources for an ATA channel */ struct ata_resource { struct resource *res; int offset; }; /* structure describing an ATA channel */ struct ata_channel { struct device *dev; /* device handle */ int unit; /* channel number */ struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ struct resource *r_irq; /* interrupt of this channel */ void *ih; /* interrupt handle */ struct ata_lowlevel hw; /* lowlevel HW functions */ struct ata_dma *dma; /* DMA data / functions */ int flags; /* channel flags */ #define ATA_NO_SLAVE 0x01 #define ATA_USE_16BIT 0x02 #define ATA_USE_PC98GEOM 0x04 #define ATA_ATAPI_DMA_RO 0x08 #define ATA_48BIT_ACTIVE 0x10 struct ata_device device[2]; /* devices on this channel */ #define MASTER 0x00 #define SLAVE 0x01 int devices; /* what is present */ #define ATA_ATA_MASTER 0x01 #define ATA_ATA_SLAVE 0x02 #define ATA_ATAPI_MASTER 0x04 #define ATA_ATAPI_SLAVE 0x08 int state; /* ATA channel state control */ #define ATA_IDLE 0x0000 #define ATA_ACTIVE 0x0001 #define ATA_CONTROL 0x0002 void (*locking)(struct ata_channel *, int); #define ATA_LF_LOCK 0x0001 #define ATA_LF_UNLOCK 0x0002 struct mtx queue_mtx; TAILQ_HEAD(, ata_request) ata_queue; /* head of ATA queue */ void *running; /* currently running request */ }; /* ATAPI request sense structure */ struct atapi_sense { u_int8_t error_code :7; /* current or deferred errors */ u_int8_t valid :1; /* follows ATAPI spec */ u_int8_t segment; /* Segment number */ u_int8_t sense_key :4; /* sense key */ u_int8_t reserved2_4 :1; /* reserved */ u_int8_t ili :1; /* incorrect length indicator */ u_int8_t eom :1; /* end of medium */ u_int8_t filemark :1; /* filemark */ u_int32_t cmd_info __packed; /* cmd information */ u_int8_t sense_length; /* additional sense len (n-7) */ u_int32_t cmd_specific_info __packed; /* additional cmd spec info */ u_int8_t asc; /* additional sense code */ u_int8_t ascq; /* additional sense code qual */ u_int8_t replaceable_unit_code; /* replaceable unit code */ u_int8_t sk_specific :7; /* sense key specific */ u_int8_t sksv :1; /* sense key specific info OK */ u_int8_t sk_specific1; /* sense key specific */ u_int8_t sk_specific2; /* sense key specific */ }; /* disk bay/enclosure related */ #define ATA_LED_OFF 0x00 #define ATA_LED_RED 0x01 #define ATA_LED_GREEN 0x02 #define ATA_LED_ORANGE 0x03 #define ATA_LED_MASK 0x03 /* externs */ extern devclass_t ata_devclass; extern struct intr_config_hook *ata_delayed_attach; extern int ata_dma, ata_wc, atapi_dma; /* public prototypes */ /* ata-all.c: */ int ata_probe(device_t dev); int ata_attach(device_t dev); int ata_detach(device_t dev); int ata_suspend(device_t dev); int ata_resume(device_t dev); int ata_printf(struct ata_channel *ch, int device, const char *fmt, ...) __printflike(3, 4); int ata_prtdev(struct ata_device *atadev, const char *fmt, ...) __printflike(2, 3); void ata_set_name(struct ata_device *atadev, char *name, int lun); void ata_free_name(struct ata_device *atadev); int ata_get_lun(u_int32_t *map); int ata_test_lun(u_int32_t *map, int lun); void ata_free_lun(u_int32_t *map, int lun); char *ata_mode2str(int mode); int ata_pmode(struct ata_params *ap); int ata_wmode(struct ata_params *ap); int ata_umode(struct ata_params *ap); int ata_limit_mode(struct ata_device *atadev, int mode, int maxmode); /* ata-queue.c: */ int ata_reinit(struct ata_channel *ch); void ata_start(struct ata_channel *ch); struct ata_request *ata_alloc_request(void); void ata_free_request(struct ata_request *request); int ata_controlcmd(struct ata_device *atadev, u_int8_t command, u_int16_t feature, u_int64_t lba, u_int16_t count); int ata_atapicmd(struct ata_device *atadev, u_int8_t *ccb, caddr_t data, int count, int flags, int timeout); void ata_queue_request(struct ata_request *request); void ata_finish(struct ata_request *request); char *ata_cmd2str(struct ata_request *request); /* ata-lowlevel.c: */ void ata_generic_hw(struct ata_channel *ch); /* subdrivers */ void ad_attach(struct ata_device *atadev); void acd_attach(struct ata_device *atadev); void afd_attach(struct ata_device *atadev); void ast_attach(struct ata_device *atadev); void atapi_cam_attach_bus(struct ata_channel *ch); void atapi_cam_detach_bus(struct ata_channel *ch); void atapi_cam_reinit_bus(struct ata_channel *ch); /* macros for locking a channel */ #define ATA_LOCK_CH(ch, value) \ atomic_cmpset_acq_int(&(ch)->state, ATA_IDLE, (value)) #define ATA_SLEEPLOCK_CH(ch, value) \ while (!atomic_cmpset_acq_int(&(ch)->state, ATA_IDLE, (value))) \ tsleep((caddr_t)&(ch), PRIBIO, "atalck", 1); #define ATA_FORCELOCK_CH(ch, value) atomic_store_rel_int(&(ch)->state, (value)) #define ATA_UNLOCK_CH(ch) atomic_store_rel_int(&(ch)->state, ATA_IDLE) /* macros to hide busspace uglyness */ #define ATA_INB(res, offset) \ bus_space_read_1(rman_get_bustag((res)), \ rman_get_bushandle((res)), (offset)) #define ATA_INW(res, offset) \ bus_space_read_2(rman_get_bustag((res)), \ rman_get_bushandle((res)), (offset)) #define ATA_INL(res, offset) \ bus_space_read_4(rman_get_bustag((res)), \ rman_get_bushandle((res)), (offset)) #define ATA_INSW(res, offset, addr, count) \ bus_space_read_multi_2(rman_get_bustag((res)), \ rman_get_bushandle((res)), \ (offset), (addr), (count)) #define ATA_INSW_STRM(res, offset, addr, count) \ bus_space_read_multi_stream_2(rman_get_bustag((res)), \ rman_get_bushandle((res)), \ (offset), (addr), (count)) #define ATA_INSL(res, offset, addr, count) \ bus_space_read_multi_4(rman_get_bustag((res)), \ rman_get_bushandle((res)), \ (offset), (addr), (count)) #define ATA_INSL_STRM(res, offset, addr, count) \ bus_space_read_multi_stream_4(rman_get_bustag((res)), \ rman_get_bushandle((res)), \ (offset), (addr), (count)) #define ATA_OUTB(res, offset, value) \ bus_space_write_1(rman_get_bustag((res)), \ rman_get_bushandle((res)), (offset), (value)) #define ATA_OUTW(res, offset, value) \ bus_space_write_2(rman_get_bustag((res)), \ rman_get_bushandle((res)), (offset), (value)) #define ATA_OUTL(res, offset, value) \ bus_space_write_4(rman_get_bustag((res)), \ rman_get_bushandle((res)), (offset), (value)) #define ATA_OUTSW(res, offset, addr, count) \ bus_space_write_multi_2(rman_get_bustag((res)), \ rman_get_bushandle((res)), \ (offset), (addr), (count)) #define ATA_OUTSW_STRM(res, offset, addr, count) \ bus_space_write_multi_stream_2(rman_get_bustag((res)), \ rman_get_bushandle((res)), \ (offset), (addr), (count)) #define ATA_OUTSL(res, offset, addr, count) \ bus_space_write_multi_4(rman_get_bustag((res)), \ rman_get_bushandle((res)), \ (offset), (addr), (count)) #define ATA_OUTSL_STRM(res, offset, addr, count) \ bus_space_write_multi_stream_4(rman_get_bustag((res)), \ rman_get_bushandle((res)), \ (offset), (addr), (count)) #define ATA_IDX_SET(ch, idx) \ ATA_OUTB(ch->r_io[ATA_IDX_ADDR].res, ch->r_io[ATA_IDX_ADDR].offset, \ ch->r_io[idx].offset) #define ATA_IDX_INB(ch, idx) \ ((ch->r_io[idx].res) \ ? ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) \ : (ATA_IDX_SET(ch, idx), \ ATA_INB(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) #define ATA_IDX_INW(ch, idx) \ ((ch->r_io[idx].res) \ ? ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) \ : (ATA_IDX_SET(ch, idx), \ ATA_INW(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) #define ATA_IDX_INL(ch, idx) \ ((ch->r_io[idx].res) \ ? ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) \ : (ATA_IDX_SET(ch, idx), \ ATA_INL(ch->r_io[ATA_IDX_DATA].res, ch->r_io[ATA_IDX_DATA].offset))) #define ATA_IDX_INSW(ch, idx, addr, count) \ ((ch->r_io[idx].res) \ ? ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ : (ATA_IDX_SET(ch, idx), \ ATA_INSW(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, addr, count))) #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ ((ch->r_io[idx].res) \ ? ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ : (ATA_IDX_SET(ch, idx), \ ATA_INSW_STRM(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, addr, count))) #define ATA_IDX_INSL(ch, idx, addr, count) \ ((ch->r_io[idx].res) \ ? ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ : (ATA_IDX_SET(ch, idx), \ ATA_INSL(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, addr, count))) #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ ((ch->r_io[idx].res) \ ? ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ : (ATA_IDX_SET(ch, idx), \ ATA_INSL_STRM(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, addr, count))) #define ATA_IDX_OUTB(ch, idx, value) \ ((ch->r_io[idx].res) \ ? ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ : (ATA_IDX_SET(ch, idx), \ ATA_OUTB(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, value))) #define ATA_IDX_OUTW(ch, idx, value) \ ((ch->r_io[idx].res) \ ? ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ : (ATA_IDX_SET(ch, idx), \ ATA_OUTW(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, value))) #define ATA_IDX_OUTL(ch, idx, value) \ ((ch->r_io[idx].res) \ ? ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) \ : (ATA_IDX_SET(ch, idx), \ ATA_OUTL(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, value))) #define ATA_IDX_OUTSW(ch, idx, addr, count) \ ((ch->r_io[idx].res) \ ? ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ : (ATA_IDX_SET(ch, idx), \ ATA_OUTSW(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, addr, count))) #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ ((ch->r_io[idx].res) \ ? ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ : (ATA_IDX_SET(ch, idx), \ ATA_OUTSW_STRM(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, addr, count))) #define ATA_IDX_OUTSL(ch, idx, addr, count) \ ((ch->r_io[idx].res) \ ? ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ : (ATA_IDX_SET(ch, idx), \ ATA_OUTSL(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, addr, count))) #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ ((ch->r_io[idx].res) \ ? ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) \ : (ATA_IDX_SET(ch, idx), \ ATA_OUTSL_STRM(ch->r_io[ATA_IDX_DATA].res, \ ch->r_io[ATA_IDX_DATA].offset, addr, count))) Index: head/sys/dev/ata/ata-chipset.c =================================================================== --- head/sys/dev/ata/ata-chipset.c (revision 121309) +++ head/sys/dev/ata/ata-chipset.c (revision 121310) @@ -1,2289 +1,2280 @@ /*- * Copyright (c) 1998 - 2003 Søren Schmidt * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification, immediately at the beginning of the file. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ata.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* misc defines */ #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) #define ATAPI_DEVICE(atadev) \ ((atadev->unit == ATA_MASTER && \ atadev->channel->devices & ATA_ATAPI_MASTER) ||\ (atadev->unit == ATA_SLAVE && \ atadev->channel->devices & ATA_ATAPI_SLAVE)) /* local prototypes */ static int ata_generic_chipinit(device_t); static void ata_generic_intr(void *); static void ata_generic_setmode(struct ata_device *, int); static int ata_acard_chipinit(device_t); static void ata_acard_intr(void *); static void ata_acard_850_setmode(struct ata_device *, int); static void ata_acard_86X_setmode(struct ata_device *, int); static int ata_ali_chipinit(device_t); static void ata_ali_setmode(struct ata_device *, int); static int ata_amd_chipinit(device_t); static int ata_cyrix_chipinit(device_t); static void ata_cyrix_setmode(struct ata_device *, int); static int ata_cypress_chipinit(device_t); static void ata_cypress_setmode(struct ata_device *, int); static int ata_highpoint_chipinit(device_t); static void ata_highpoint_intr(void *); static void ata_highpoint_setmode(struct ata_device *, int); static int ata_highpoint_check_80pin(struct ata_device *, int); static int ata_intel_chipinit(device_t); static void ata_intel_old_setmode(struct ata_device *, int); static void ata_intel_new_setmode(struct ata_device *, int); static int ata_national_chipinit(device_t); static void ata_national_setmode(struct ata_device *, int); static int ata_nvidia_chipinit(device_t); static int ata_via_chipinit(device_t); static void ata_via_family_setmode(struct ata_device *, int); static void ata_via_southbridge_fixup(device_t); static int ata_promise_chipinit(device_t); static int ata_promise_mio_allocate(device_t, struct ata_channel *); static void ata_promise_old_intr(void *); static void ata_promise_tx2_intr(void *); static void ata_promise_mio_intr(void *); static void ata_promise_setmode(struct ata_device *, int); static void ata_promise_new_dmainit(struct ata_channel *); -static int ata_promise_new_dmastart(struct ata_channel *, caddr_t, int32_t,int); +static int ata_promise_new_dmastart(struct ata_channel *); static int ata_promise_new_dmastop(struct ata_channel *); static void ata_promise_mio_dmainit(struct ata_channel *); -static int ata_promise_mio_dmastart(struct ata_channel *, caddr_t, int32_t,int); +static int ata_promise_mio_dmastart(struct ata_channel *); static int ata_promise_mio_dmastop(struct ata_channel *); static int ata_serverworks_chipinit(device_t); static void ata_serverworks_setmode(struct ata_device *, int); static int ata_sii_chipinit(device_t); static int ata_sii_mio_allocate(device_t, struct ata_channel *); static void ata_sii_intr(void *); static void ata_cmd_intr(void *); static void ata_sii_setmode(struct ata_device *, int); static void ata_cmd_setmode(struct ata_device *, int); static int ata_sis_chipinit(device_t); static void ata_sis_setmode(struct ata_device *, int); static int ata_check_80pin(struct ata_device *, int); static struct ata_chip_id *ata_find_chip(device_t, struct ata_chip_id *, int); static struct ata_chip_id *ata_match_chip(device_t, struct ata_chip_id *); static int ata_setup_interrupt(device_t); static void ata_serialize(struct ata_channel *, int); static int ata_mode2idx(int); /* generic or unknown ATA chipset init code */ int ata_generic_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); device_set_desc(dev, "GENERIC ATA controller"); ctlr->chipinit = ata_generic_chipinit; return 0; } static int ata_generic_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; ctlr->setmode = ata_generic_setmode; return 0; } static void ata_generic_intr(void *data) { struct ata_pci_controller *ctlr = data; struct ata_channel *ch; u_int8_t dmastat; int unit; /* implement this as a toggle instead to balance load XXX */ for (unit = 0; unit < 2; unit++) { if (!(ch = ctlr->interrupt[unit].argument)) continue; if (ch->dma->flags & ATA_DMA_ACTIVE) { if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT)) continue; ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT); DELAY(1); } ctlr->interrupt[unit].function(ch); } } static void ata_generic_setmode(struct ata_device *atadev, int mode) { mode = ata_check_80pin(atadev, mode); if (!ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) atadev->mode = mode; } /* * Acard chipset support functions */ int ata_acard_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "Acard ATP850" }, { ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860A" }, { ATA_ATP860R, 0, 0, 0x00, ATA_UDMA4, "Acard ATP860R" }, { ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865A" }, { ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "Acard ATP865R" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_acard_chipinit; return 0; } static int ata_acard_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); int rid = ATA_IRQ_RID; if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE))) { device_printf(dev, "unable to map interrupt\n"); return ENXIO; } if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, ata_acard_intr, ctlr, &ctlr->handle))) { device_printf(dev, "unable to setup interrupt\n"); return ENXIO; } if (ctlr->chip->cfg1 == ATPOLD) { ctlr->setmode = ata_acard_850_setmode; ctlr->locking = ata_serialize; } else ctlr->setmode = ata_acard_86X_setmode; return 0; } static void ata_acard_intr(void *data) { struct ata_pci_controller *ctlr = data; struct ata_channel *ch; u_int8_t dmastat; int unit; /* implement this as a toggle instead to balance load XXX */ for (unit = 0; unit < 2; unit++) { if (ctlr->chip->cfg1 == ATPOLD && ctlr->locked_ch != unit) continue; ch = ctlr->interrupt[unit].argument; if (ch->dma->flags & ATA_DMA_ACTIVE) { if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT)) continue; ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT); DELAY(1); ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); DELAY(1); } ctlr->interrupt[unit].function(ch); } } static void ata_acard_850_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int error; mode = ata_limit_mode(atadev, mode, ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma); /* XXX missing WDMA0+1 + PIO modes */ if (mode >= ATA_WDMA2) { error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (!error) { u_int8_t reg54 = pci_read_config(parent, 0x54, 1); reg54 &= ~(0x03 << (devno << 1)); if (mode >= ATA_UDMA0) reg54 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 1)); pci_write_config(parent, 0x54, reg54, 1); pci_write_config(parent, 0x4a, 0xa6, 1); pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); atadev->mode = mode; return; } } /* we could set PIO mode timings, but we assume the BIOS did that */ } static void ata_acard_86X_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int error; mode = ata_limit_mode(atadev, mode, ATAPI_DEVICE(atadev)?ATA_PIO_MAX:ctlr->chip->max_dma); mode = ata_check_80pin(atadev, mode); /* XXX missing WDMA0+1 + PIO modes */ if (mode >= ATA_WDMA2) { error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (!error) { u_int16_t reg44 = pci_read_config(parent, 0x44, 2); reg44 &= ~(0x000f << (devno << 2)); if (mode >= ATA_UDMA0) reg44 |= (((mode & ATA_MODE_MASK) + 1) << (devno << 2)); pci_write_config(parent, 0x44, reg44, 2); pci_write_config(parent, 0x4a, 0xa6, 1); pci_write_config(parent, 0x40 + devno, 0x31, 1); atadev->mode = mode; return; } } /* we could set PIO mode timings, but we assume the BIOS did that */ } /* * Acer Labs Inc (ALI) chipset support functions */ int ata_ali_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_ALI_5229, 0xc4, 0, ALINEW, ATA_UDMA5, "AcerLabs Aladdin" }, { ATA_ALI_5229, 0xc2, 0, ALINEW, ATA_UDMA4, "AcerLabs Aladdin" }, { ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "AcerLabs Aladdin" }, { ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "AcerLabs Aladdin" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_ali_chipinit; return 0; } static int ata_ali_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; /* deactivate the ATAPI FIFO and enable ATAPI UDMA */ pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1); /* enable cable detection and UDMA support on newer chips */ if (ctlr->chip->cfg2 & ALINEW) pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) | 0x09, 1); ctlr->setmode = ata_ali_setmode; return 0; } static void ata_ali_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int error; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); if (ctlr->chip->cfg2 & ALINEW) { if (mode > ATA_UDMA2 && pci_read_config(parent, 0x4a, 1) & (1 << atadev->channel->unit)) { ata_prtdev(atadev, "DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } } else mode = ata_check_80pin(atadev, mode); if (ctlr->chip->cfg2 & ALIOLD) { /* doesn't support ATAPI DMA on write */ atadev->channel->flags |= ATA_ATAPI_DMA_RO; if (atadev->channel->devices & ATA_ATAPI_MASTER && atadev->channel->devices & ATA_ATAPI_SLAVE) { /* doesn't support ATAPI DMA on two ATAPI devices */ ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX); } } error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (!error) { if (mode >= ATA_UDMA0) { u_int8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f}; u_int32_t word54 = pci_read_config(parent, 0x54, 4); word54 &= ~(0x000f000f << (devno << 2)); word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2)); pci_write_config(parent, 0x54, word54, 4); pci_write_config(parent, 0x58 + (atadev->channel->unit << 2), 0x00310001, 4); } else { u_int32_t piotimings[] = { 0x006d0003, 0x00580002, 0x00440001, 0x00330001, 0x00310001, 0x00440001, 0x00330001, 0x00310001}; pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 4) & ~(0x0008000f << (devno << 2)), 4); pci_write_config(parent, 0x58 + (atadev->channel->unit << 2), piotimings[ata_mode2idx(mode)], 4); } atadev->mode = mode; } } /* * American Micro Devices (AMD) support function */ int ata_amd_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "AMD 756" }, { ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "AMD 766" }, { ATA_AMD768, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA5, "AMD 768" }, { ATA_AMD8111, 0x00, AMDNVIDIA, 0x00, ATA_UDMA6, "AMD 8111" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_amd_chipinit; return 0; } static int ata_amd_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; /* set prefetch, postwrite */ if (ctlr->chip->cfg2 & AMDBUG) pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1); else pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); ctlr->setmode = ata_via_family_setmode; return 0; } /* * Cyrix chipset support functions */ int ata_cyrix_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (pci_get_devid(dev) == ATA_CYRIX_5530) { device_set_desc(dev, "Cyrix 5530 ATA33 controller"); ctlr->chipinit = ata_cyrix_chipinit; return 0; } return ENXIO; } static int ata_cyrix_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; if (ctlr->r_io1) ctlr->setmode = ata_cyrix_setmode; else ctlr->setmode = ata_generic_setmode; return 0; } static void ata_cyrix_setmode(struct ata_device *atadev, int mode) { struct ata_channel *ch = atadev->channel; int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); u_int32_t piotiming[] = { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 }; u_int32_t dmatiming[] = { 0x00077771, 0x00012121, 0x00002020 }; u_int32_t udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 }; int error; atadev->channel->dma->alignment = 16; atadev->channel->dma->max_iosize = 63 * 1024; mode = ata_limit_mode(atadev, mode, ATA_UDMA2); error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on Cyrix chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode)); if (!error) { if (mode >= ATA_UDMA0) { ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 0x24 + (devno << 3), udmatiming[mode & ATA_MODE_MASK]); } else if (mode >= ATA_WDMA0) { ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 0x24 + (devno << 3), dmatiming[mode & ATA_MODE_MASK]); } else { ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, 0x20 + (devno << 3), piotiming[mode & ATA_MODE_MASK]); } atadev->mode = mode; } } /* * Cypress chipset support functions */ int ata_cypress_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); /* * the Cypress chip is a mess, it contains two ATA functions, but * both channels are visible on the first one. * simply ignore the second function for now, as the right * solution (ignoring the second channel on the first function) * doesn't work with the crappy ATA interrupt setup on the alpha. */ if (pci_get_devid(dev) == ATA_CYPRESS_82C693 && pci_get_function(dev) == 1 && pci_get_subclass(dev) == PCIS_STORAGE_IDE) { device_set_desc(dev, "Cypress 82C693 ATA controller"); ctlr->chipinit = ata_cypress_chipinit; return 0; } return ENXIO; } static int ata_cypress_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; ctlr->setmode = ata_cypress_setmode; return 0; } static void ata_cypress_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); int error; mode = ata_limit_mode(atadev, mode, ATA_WDMA2); /* XXX missing WDMA0+1 + PIO modes */ if (mode == ATA_WDMA2) { error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,mode); if (bootverbose) ata_prtdev(atadev, "%ssetting WDMA2 on Cypress chip\n", error ? "FAILURE " : ""); if (!error) { pci_write_config(parent, atadev->channel->unit?0x4e:0x4c,0x2020,2); atadev->mode = mode; return; } } /* we could set PIO mode timings, but we assume the BIOS did that */ } /* * HighPoint chipset support functions */ int ata_highpoint_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_HPT366, 0x05, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" }, { ATA_HPT366, 0x03, HPT370, 0x00, ATA_UDMA5, "HighPoint HPT370" }, { ATA_HPT366, 0x02, HPT366, 0x00, ATA_UDMA4, "HighPoint HPT368" }, { ATA_HPT366, 0x00, HPT366, HPTOLD, ATA_UDMA4, "HighPoint HPT366" }, { ATA_HPT372, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT372" }, { ATA_HPT302, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT302" }, { ATA_HPT371, 0x01, HPT372, 0x00, ATA_UDMA6, "HighPoint HPT371" }, { ATA_HPT374, 0x07, HPT374, 0x00, ATA_UDMA6, "HighPoint HPT374" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; strcpy(buffer, idx->text); if (idx->cfg1 == HPT374) { if (pci_get_function(dev) == 0) strcat(buffer, " (channel 0+1)"); else if (pci_get_function(dev) == 1) strcat(buffer, " (channel 2+3)"); } sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_highpoint_chipinit; return 0; } static int ata_highpoint_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); int rid = ATA_IRQ_RID; if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE))) { device_printf(dev, "unable to map interrupt\n"); return ENXIO; } if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, ata_highpoint_intr, ctlr, &ctlr->handle))) { device_printf(dev, "unable to setup interrupt\n"); return ENXIO; } if (ctlr->chip->cfg2 == HPTOLD) { /* turn off interrupt prediction */ pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1); } else { /* turn off interrupt prediction */ pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1); pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1); /* turn on interrupts */ pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1); /* set clocks etc */ if (ctlr->chip->cfg1 < HPT372) pci_write_config(dev, 0x5b, 0x22, 1); else pci_write_config(dev, 0x5b, (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1); } ctlr->setmode = ata_highpoint_setmode; return 0; } static void ata_highpoint_intr(void *data) { struct ata_pci_controller *ctlr = data; struct ata_channel *ch; u_int8_t dmastat; int unit; /* implement this as a toggle instead to balance load XXX */ for (unit = 0; unit < 2; unit++) { if (!(ch = ctlr->interrupt[unit].argument)) continue; if (((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT))!=ATA_BMSTAT_INTERRUPT) continue; ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); DELAY(1); ctlr->interrupt[unit].function(ch); } } static void ata_highpoint_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int error; u_int32_t timings33[][4] = { /* HPT366 HPT370 HPT372 HPT374 mode */ { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */ { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */ { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */ { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */ { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */ { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */ { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */ { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */ { 0x10c8a731, 0x16514e31, 0x1c82dc62, 0x121882ea }, /* UDMA 0 */ { 0x10cba731, 0x164d4e31, 0x1c9adc62, 0x12148254 }, /* UDMA 1 */ { 0x10caa731, 0x16494e31, 0x1c91dc62, 0x120c8242 }, /* UDMA 2 */ { 0x10cfa731, 0x166d4e31, 0x1c8edc62, 0x128c8242 }, /* UDMA 3 */ { 0x10c9a731, 0x16454e31, 0x1c8ddc62, 0x12ac8242 }, /* UDMA 4 */ { 0, 0x16454e31, 0x1c6ddc62, 0x12848242 }, /* UDMA 5 */ { 0, 0, 0x1c81dc62, 0x12448242 } /* UDMA 6 */ }; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); if (ctlr->chip->cfg1 == HPT366 && ATAPI_DEVICE(atadev)) mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX); mode = ata_highpoint_check_80pin(atadev, mode); error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on HighPoint chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode)); if (!error) pci_write_config(parent, 0x40 + (devno << 2), timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); atadev->mode = mode; } static int ata_highpoint_check_80pin(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); u_int8_t reg, val, res; if (ctlr->chip->cfg1 == HPT374 && pci_get_function(parent) == 1) { reg = atadev->channel->unit ? 0x57 : 0x53; val = pci_read_config(parent, reg, 1); pci_write_config(parent, reg, val | 0x80, 1); } else { reg = 0x5b; val = pci_read_config(parent, reg, 1); pci_write_config(parent, reg, val & 0xfe, 1); } res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2); pci_write_config(parent, reg, val, 1); if (mode > ATA_UDMA2 && res) { ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } return mode; } /* * Intel chipset support functions */ int ata_intel_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX" }, { ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "Intel PIIX3" }, { ATA_I82371AB, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" }, { ATA_I82443MX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" }, { ATA_I82451NX, 0, 0, 0x00, ATA_UDMA2, "Intel PIIX4" }, { ATA_I82801AB, 0, 0, 0x00, ATA_UDMA2, "Intel ICH0" }, { ATA_I82801AA, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" }, { ATA_I82372FB, 0, 0, 0x00, ATA_UDMA4, "Intel ICH" }, { ATA_I82801BA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" }, { ATA_I82801BA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH2" }, { ATA_I82801CA, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" }, { ATA_I82801CA_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH3" }, { ATA_I82801DB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" }, { ATA_I82801DB_1, 0, 0, 0x00, ATA_UDMA5, "Intel ICH4" }, { ATA_I82801EB, 0, 0, 0x00, ATA_UDMA5, "Intel ICH5" }, { ATA_I82801EB_1, 0, 0, 0x00, ATA_SA150, "Intel ICH5" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_intel_chipinit; return 0; } static int ata_intel_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; if (ctlr->chip->chipid == ATA_I82371FB) ctlr->setmode = ata_intel_old_setmode; else ctlr->setmode = ata_intel_new_setmode; return 0; } static void ata_intel_old_setmode(struct ata_device *atadev, int mode) { /* NOT YET */ } static void ata_intel_new_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); u_int32_t reg40 = pci_read_config(parent, 0x40, 4); u_int8_t reg44 = pci_read_config(parent, 0x44, 1); u_int8_t reg48 = pci_read_config(parent, 0x48, 1); u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); u_int16_t reg54 = pci_read_config(parent, 0x54, 2); u_int32_t mask40 = 0, new40 = 0; u_int8_t mask44 = 0, new44 = 0; int error; u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); if (ctlr->chip->max_dma < ATA_SA150 && mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) { ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (error) return; if (ctlr->chip->max_dma < ATA_SA150) { if (mode >= ATA_UDMA0) { pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno<<2))) | (0x01 + !(mode & 0x01)), 2); } else { pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))), 2); } if (mode >= ATA_UDMA2) pci_write_config(parent, 0x54, reg54 | (0x1 << devno), 2); else pci_write_config(parent, 0x54, reg54 & ~(0x1 << devno), 2); if (mode >= ATA_UDMA5) pci_write_config(parent, 0x54, reg54 | (0x10000 << devno), 2); else pci_write_config(parent, 0x54, reg54 & ~(0x10000 << devno), 2); reg40 &= ~0x00ff00ff; reg40 |= 0x40774077; if (atadev->unit == ATA_MASTER) { mask40 = 0x3300; new40 = timings[ata_mode2idx(mode)] << 8; } else { mask44 = 0x0f; new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) | (timings[ata_mode2idx(mode)] & 0x03); } if (atadev->channel->unit) { mask40 <<= 16; new40 <<= 16; mask44 <<= 4; new44 <<= 4; } pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); } atadev->mode = mode; } /* * National chipset support functions */ int ata_national_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); /* this chip is a clone of the Cyrix chip, bugs and all */ if (pci_get_devid(dev) == ATA_SC1100) { device_set_desc(dev, "National Geode SC1100 ATA33 controller"); ctlr->chipinit = ata_national_chipinit; return 0; } return ENXIO; } static device_t nat_host = NULL; static int ata_national_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); device_t *children; int nchildren, i; if (ata_setup_interrupt(dev)) return ENXIO; /* locate the ISA part in the southbridge and enable UDMA33 */ if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ for (i = 0; i < nchildren; i++) { if (pci_get_devid(children[i]) == 0x0510100b) { nat_host = children[i]; break; } } free(children, M_TEMP); } ctlr->setmode = ata_national_setmode; return 0; } static void ata_national_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); u_int32_t piotiming[] = { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010, 0x00803020, 0x20102010, 0x00100010, 0x00100010, 0x00100010, 0x00100010 }; u_int32_t dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 }; u_int32_t udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 }; int error; atadev->channel->dma->alignment = 16; atadev->channel->dma->max_iosize = 63 * 1024; mode = ata_limit_mode(atadev, mode, ATA_UDMA2); error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%s setting %s on National chip\n", (error) ? "failed" : "success", ata_mode2str(mode)); if (!error) { if (mode >= ATA_UDMA0) { pci_write_config(parent, 0x44 + (devno << 3), udmatiming[mode & ATA_MODE_MASK], 4); } else if (mode >= ATA_WDMA0) { pci_write_config(parent, 0x44 + (devno << 3), dmatiming[mode & ATA_MODE_MASK], 4); } else { pci_write_config(parent, 0x44 + (devno << 3), pci_read_config(parent, 0x44 + (devno << 3), 4) | 0x80000000, 4); } pci_write_config(parent, 0x40 + (devno << 3), piotiming[ata_mode2idx(mode)], 4); atadev->mode = mode; } } /* * nVidia chipset support functions */ int ata_nvidia_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA5, "nVidia nForce" }, { ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA6, "nVidia nForce2" }, { ATA_NFORCE3, 0, AMDNVIDIA, NVIDIA|AMDBUG, ATA_UDMA6, "nVidia nForce3" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_nvidia_chipinit; return 0; } static int ata_nvidia_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; /* set prefetch, postwrite */ if (ctlr->chip->cfg2 & AMDBUG) pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) & 0x0f, 1); else pci_write_config(dev, 0x51, pci_read_config(dev, 0x51, 1) | 0xf0, 1); ctlr->setmode = ata_via_family_setmode; return 0; } /* * Promise chipset support functions */ int ata_promise_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_PDC20246, 0, PROLD, 0x00, ATA_UDMA2, "Promise PDC20246" }, { ATA_PDC20262, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20262" }, { ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise PDC20263" }, { ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20265" }, { ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise PDC20267" }, { ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20268" }, { ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20269" }, { ATA_PDC20270, 0, PRTX, PRTX4, ATA_UDMA5, "Promise PDC20270" }, { ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20271" }, { ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20275" }, { ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise PDC20276" }, { ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise PDC20277" }, { ATA_PDC20318, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20318" }, { ATA_PDC20319, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20319" }, { ATA_PDC20371, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20371" }, { ATA_PDC20375, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20375" }, { ATA_PDC20376, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20376" }, { ATA_PDC20377, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20377" }, { ATA_PDC20378, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20378" }, { ATA_PDC20379, 0, PRMIO, PRSATA, ATA_SA150, "Promise PDC20379" }, { ATA_PDC20617, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20617" }, { ATA_PDC20618, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20618" }, { ATA_PDC20619, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20619" }, { ATA_PDC20620, 0, PRMIO, PRDUAL, ATA_UDMA6, "Promise PDC20620" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; uintptr_t devid = 0; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; /* if we are on a SuperTrak SX6000 dont attach */ if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && devid == ATA_I960RM) return ENXIO; strcpy(buffer, idx->text); /* if we are on a FastTrak TX4, adjust the interrupt resource */ if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && devid == ATA_DEC_21150) { static long start = 0, end = 0; if (pci_get_slot(dev) == 1) { bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); strcat(buffer, " (channel 0+1)"); } else if (pci_get_slot(dev) == 2 && start && end) { bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); start = end = 0; strcat(buffer, " (channel 2+3)"); } else { start = end = 0; } } sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_promise_chipinit; return 0; } static int ata_promise_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); int rid = ATA_IRQ_RID; if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE))) { device_printf(dev, "unable to map interrupt\n"); return ENXIO; } switch (ctlr->chip->cfg1) { case PRNEW: /* setup clocks */ ATA_OUTB(ctlr->r_io1, 0x11, ATA_INB(ctlr->r_io1, 0x11) | 0x0a); ctlr->dmainit = ata_promise_new_dmainit; /* FALLTHROUGH */ case PROLD: /* enable burst mode */ ATA_OUTB(ctlr->r_io1, 0x1f, ATA_INB(ctlr->r_io1, 0x1f) | 0x01); if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, ata_promise_old_intr, ctlr, &ctlr->handle))) { device_printf(dev, "unable to setup interrupt\n"); return ENXIO; } break; case PRTX: if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, ata_promise_tx2_intr, ctlr, &ctlr->handle))) { device_printf(dev, "unable to setup interrupt\n"); return ENXIO; } break; case PRMIO: rid = 0x1c; if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE))) return ENXIO; ctlr->dmainit = ata_promise_mio_dmainit; ctlr->allocate = ata_promise_mio_allocate; if (ctlr->chip->cfg2 & PRDUAL) { ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x01) > 0) + ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 2; } else if (ctlr->chip->cfg2 & PRSATA) { ATA_OUTL(ctlr->r_io2, 0x06c, 0x00ff0033); ctlr->channels = ((ATA_INL(ctlr->r_io2, 0x48) & 0x02) > 0) + 3; } else ctlr->channels = 4; if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, ata_promise_mio_intr, ctlr, &ctlr->handle))) { device_printf(dev, "unable to setup interrupt\n"); return ENXIO; } break; } ctlr->setmode = ata_promise_setmode; return 0; } static int ata_promise_mio_allocate(device_t dev, struct ata_channel *ch) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); int i; for (i = ATA_DATA; i <= ATA_STATUS; i++) { ch->r_io[i].res = ctlr->r_io2; ch->r_io[i].offset = 0x200 + (i << 2) + (ch->unit << 7); } ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2; ch->r_io[ATA_ALTSTAT].offset = 0x238 + (ch->unit << 7); ch->r_io[ATA_BMCTL_PORT].res = ctlr->r_io2; ch->r_io[ATA_BMCTL_PORT].offset = 0x260 + (ch->unit << 7); ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2; ch->r_io[ATA_BMDTP_PORT].offset = 0x244 + (ch->unit << 7); ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2; ch->r_io[ATA_BMDEVSPEC_0].offset = (ch->unit << 2); ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2; ATA_IDX_OUTL(ch, ATA_BMCMD_PORT, (ATA_IDX_INL(ch, ATA_BMCMD_PORT) & ~0x00000f8f) | ch->unit); ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001); ch->flags |= (ATA_NO_SLAVE | ATA_USE_16BIT); ctlr->dmainit(ch); return 0; } static void ata_promise_old_intr(void *data) { struct ata_pci_controller *ctlr = data; struct ata_channel *ch; u_int8_t dmastat; int unit; /* implement this as a toggle instead to balance load XXX */ for (unit = 0; unit < 2; unit++) { if (!(ch = ctlr->interrupt[unit].argument)) continue; if (ATA_INL(ctlr->r_io1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { if (ch->dma->flags & ATA_DMA_ACTIVE) { if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT)) continue; ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT); DELAY(1); } ctlr->interrupt[unit].function(ch); } } } static void ata_promise_tx2_intr(void *data) { struct ata_pci_controller *ctlr = data; struct ata_channel *ch; u_int8_t dmastat; int unit; /* implement this as a toggle instead to balance load XXX */ for (unit = 0; unit < 2; unit++) { if (!(ch = ctlr->interrupt[unit].argument)) continue; ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { if (ch->dma->flags & ATA_DMA_ACTIVE) { if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT)) continue; ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT); DELAY(1); } ctlr->interrupt[unit].function(ch); } } } static void ata_promise_mio_intr(void *data) { struct ata_pci_controller *ctlr = data; struct ata_channel *ch; u_int32_t irq_vector; int unit; irq_vector = ATA_INL(ctlr->r_io2, 0x0040); for (unit = 0; unit < ctlr->channels; unit++) { if (irq_vector & (1 << unit)) { if ((ch = ctlr->interrupt[unit].argument)) { ctlr->interrupt[unit].function(ch); ATA_IDX_OUTL(ch, ATA_BMDEVSPEC_0, 0x00000001); } } } } static void ata_promise_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int error; u_int32_t timings33[][2] = { /* PROLD PRNEW mode */ { 0x004ff329, 0x004fff2f }, /* PIO 0 */ { 0x004fec25, 0x004ff82a }, /* PIO 1 */ { 0x004fe823, 0x004ff026 }, /* PIO 2 */ { 0x004fe622, 0x004fec24 }, /* PIO 3 */ { 0x004fe421, 0x004fe822 }, /* PIO 4 */ { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ { 0, 0x00424ef6 }, /* UDMA 3 */ { 0, 0x004127f3 }, /* UDMA 4 */ { 0, 0x004127f3 } /* UDMA 5 */ }; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); switch (ctlr->chip->cfg1) { case PROLD: case PRNEW: if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x50, 2) & (atadev->channel->unit ? 1 << 11 : 1 << 10))) { ata_prtdev(atadev, "DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } if (ATAPI_DEVICE(atadev) && mode > ATA_PIO_MAX) mode = ata_limit_mode(atadev, mode, ATA_PIO_MAX); break; case PRTX: ATA_IDX_OUTB(atadev->channel, ATA_BMDEVSPEC_0, 0x0b); if (mode > ATA_UDMA2 && ATA_IDX_INB(atadev->channel, ATA_BMDEVSPEC_1) & 0x04) { ata_prtdev(atadev, "DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } break; case PRMIO: if (mode > ATA_UDMA2 && (ATA_IDX_INL(atadev->channel, ATA_BMCTL_PORT) & 0x01000000)) { ata_prtdev(atadev, "DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } break; } error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (!error) { if (ctlr->chip->cfg1 < PRTX) pci_write_config(parent, 0x60 + (devno << 2), timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4); atadev->mode = mode; } return; } static void ata_promise_new_dmainit(struct ata_channel *ch) { ata_dmainit(ch); if (ch->dma) { ch->dma->start = ata_promise_new_dmastart; ch->dma->stop = ata_promise_new_dmastop; } } static int -ata_promise_new_dmastart(struct ata_channel *ch, - caddr_t data, int32_t count, int dir) +ata_promise_new_dmastart(struct ata_channel *ch) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(ch->dev)); - int error; - if ((error = ata_dmastart(ch, data, count, dir))) - return error; if (ch->flags & ATA_48BIT_ACTIVE) { ATA_OUTB(ctlr->r_io1, 0x11, ATA_INB(ctlr->r_io1, 0x11) | (ch->unit ? 0x08 : 0x02)); ATA_OUTL(ctlr->r_io1, 0x20, - (dir ? 0x05000000 : 0x06000000) | (count >> 1)); + ((ch->dma->flags & ATA_DMA_READ) ? 0x05000000 : 0x06000000) | + (ch->dma->cur_iosize >> 1)); } ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab); ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, - (dir ? ATA_BMCMD_WRITE_READ : 0) | ATA_BMCMD_START_STOP); - return error; + ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | + ATA_BMCMD_START_STOP); + return 0; } static int ata_promise_new_dmastop(struct ata_channel *ch) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(ch->dev)); int error; if (ch->flags & ATA_48BIT_ACTIVE) { ATA_OUTB(ctlr->r_io1, 0x11, ATA_INB(ctlr->r_io1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); ATA_OUTL(ctlr->r_io1, 0x20, 0); } error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); - ata_dmastop(ch); return error; } static void ata_promise_mio_dmainit(struct ata_channel *ch) { ata_dmainit(ch); if (ch->dma) { ch->dma->start = ata_promise_mio_dmastart; ch->dma->stop = ata_promise_mio_dmastop; } } static int -ata_promise_mio_dmastart(struct ata_channel *ch, - caddr_t data, int32_t count, int dir) +ata_promise_mio_dmastart(struct ata_channel *ch) { - int error; - - if ((error = ata_dmastart(ch, data, count, dir))) - return error; - ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab); ATA_IDX_OUTL(ch, ATA_BMCTL_PORT, (ATA_IDX_INL(ch, ATA_BMCTL_PORT) & ~0x000000c0) | - ((dir) ? 0x00000080 : 0x000000c0)); - return error; + ((ch->dma->flags & ATA_DMA_READ) ? 0x00000080 : 0x000000c0)); + return 0; } static int ata_promise_mio_dmastop(struct ata_channel *ch) { ATA_IDX_OUTL(ch, ATA_BMCTL_PORT, ATA_IDX_INL(ch, ATA_BMCTL_PORT) & ~0x00000080); - return ata_dmastop(ch); + return 0; } /* * ServerWorks chipset support functions */ int ata_serverworks_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_ROSB4, 0x00, SWKS33, 0x00, ATA_UDMA2, "ServerWorks ROSB4" }, { ATA_CSB5, 0x92, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB5" }, { ATA_CSB5, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB5" }, { ATA_CSB6, 0x00, SWKS100, 0x00, ATA_UDMA5, "ServerWorks CSB6" }, { ATA_CSB6_1, 0x00, SWKS66, 0x00, ATA_UDMA4, "ServerWorks CSB6" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_serverworks_chipinit; return 0; } static int ata_serverworks_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; if (ctlr->chip->cfg1 == SWKS33) { device_t *children; int nchildren, i; /* locate the ISA part in the southbridge and enable UDMA33 */ if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ for (i = 0; i < nchildren; i++) { if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { pci_write_config(children[i], 0x64, (pci_read_config(children[i], 0x64, 4) & ~0x00002000) | 0x00004000, 4); break; } } free(children, M_TEMP); } } else { pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x40) | (ctlr->chip->cfg1 == SWKS100) ? 0x03 : 0x02, 1); } ctlr->setmode = ata_serverworks_setmode; return 0; } static void ata_serverworks_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int offset = devno ^ 0x01; int error; u_int8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 }; u_int8_t dmatimings[] = { 0x77, 0x21, 0x20 }; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); mode = ata_check_80pin(atadev, mode); error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (!error) { if (mode >= ATA_UDMA0) { pci_write_config(parent, 0x56, (pci_read_config(parent, 0x56, 2) & ~(0xf << (devno << 2))) | ((mode & ATA_MODE_MASK) << (devno << 2)), 2); pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) | (0x01 << devno), 1); pci_write_config(parent, 0x44, (pci_read_config(parent, 0x44, 4) & ~(0xff << (offset << 8))) | (dmatimings[2] << (offset << 8)), 4); } else if (mode >= ATA_WDMA0) { pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) & ~(0x01 << devno), 1); pci_write_config(parent, 0x44, (pci_read_config(parent, 0x44, 4) & ~(0xff << (offset << 8))) | (dmatimings[mode & ATA_MODE_MASK]<<(offset<<8)),4); } else pci_write_config(parent, 0x54, pci_read_config(parent, 0x54, 1) & ~(0x01 << devno), 1); pci_write_config(parent, 0x40, (pci_read_config(parent, 0x40, 4) & ~(0xff << (offset << 8))) | (piotimings[ata_mode2idx(mode)] << (offset << 8)), 4); atadev->mode = mode; } } /* * Silicon Image (former CMD) chipset support functions */ int ata_sii_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_SII3112, 0x00, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, { ATA_SII3112_1, 0x00, SIIMEMIO, 0, ATA_SA150, "SiI 3112" }, { ATA_SII0680, 0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" }, { ATA_CMD649, 0x00, 0, SIIINTR, ATA_UDMA5, "CMD 649" }, { ATA_CMD648, 0x00, 0, SIIINTR, ATA_UDMA4, "CMD 648" }, { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" }, { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; if (!(idx = ata_match_chip(dev, ids))) return ENXIO; sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_sii_chipinit; return 0; } static int ata_sii_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); int rid = ATA_IRQ_RID; if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE))) { device_printf(dev, "unable to map interrupt\n"); return ENXIO; } if (ctlr->chip->cfg1 == SIIMEMIO) { if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, ata_sii_intr, ctlr, &ctlr->handle))) { device_printf(dev, "unable to setup interrupt\n"); return ENXIO; } rid = 0x24; if (!(ctlr->r_io2 = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE))) return ENXIO; if (ctlr->chip->cfg2 & SIISETCLK) { if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) device_printf(dev, "%s could not set ATA133 clock\n", ctlr->chip->text); } /* enable interrupt as BIOS might not */ pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); ctlr->allocate = ata_sii_mio_allocate; ctlr->setmode = ata_sii_setmode; } else { if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, ctlr->chip->cfg2 & SIIINTR ? ata_cmd_intr : ata_generic_intr, ctlr, &ctlr->handle))) { device_printf(dev, "unable to setup interrupt\n"); return ENXIO; } if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { device_printf(dev, "HW has secondary channel disabled\n"); ctlr->channels = 1; } /* enable interrupt as BIOS might not */ pci_write_config(dev, 0x71, 0x01, 1); ctlr->setmode = ata_cmd_setmode; } return 0; } static int ata_sii_mio_allocate(device_t dev, struct ata_channel *ch) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); int i; for (i = ATA_DATA; i <= ATA_STATUS; i++) { ch->r_io[i].res = ctlr->r_io2; ch->r_io[i].offset = 0x80 + i + (ch->unit << 6); } ch->r_io[ATA_ALTSTAT].res = ctlr->r_io2; ch->r_io[ATA_ALTSTAT].offset = 0x8a + (ch->unit << 6); ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_io2; ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (ch->unit << 3); ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_io2; ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (ch->unit << 3); ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_io2; ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (ch->unit << 3); ch->r_io[ATA_BMDEVSPEC_0].res = ctlr->r_io2; ch->r_io[ATA_BMDEVSPEC_0].offset = 0xa1 + (ch->unit << 6); ch->r_io[ATA_IDX_ADDR].res = ctlr->r_io2; if (ctlr->chip->max_dma >= ATA_SA150) ch->flags |= ATA_NO_SLAVE; ctlr->dmainit(ch); return 0; } static void ata_sii_intr(void *data) { struct ata_pci_controller *ctlr = data; struct ata_channel *ch; u_int8_t dmastat; int unit; /* implement this as a toggle instead to balance load XXX */ for (unit = 0; unit < 2; unit++) { if (!(ch = ctlr->interrupt[unit].argument)) continue; if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) { if (ch->dma->flags & ATA_DMA_ACTIVE) { if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT)) continue; ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT); DELAY(1); } ctlr->interrupt[unit].function(ch); } } } static void ata_cmd_intr(void *data) { struct ata_pci_controller *ctlr = data; struct ata_channel *ch; u_int8_t dmastat, reg71; int unit; /* implement this as a toggle instead to balance load XXX */ for (unit = 0; unit < 2; unit++) { if (!(ch = ctlr->interrupt[unit].argument)) continue; if (!((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) & (ch->unit ? 0x08 : 0x04))) continue; pci_write_config(device_get_parent(ch->dev), 0x71, reg71 & ~(ch->unit ? 0x04 : 0x08), 1); if (ch->dma->flags & ATA_DMA_ACTIVE) { if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT)) continue; ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT); DELAY(1); } ctlr->interrupt[unit].function(ch); } } static void ata_sii_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int rego = (atadev->channel->unit << 4) + (ATA_DEV(atadev->unit) << 1); int mreg = atadev->channel->unit ? 0x84 : 0x80; int mask = 0x03 << (ATA_DEV(atadev->unit) << 2); int mval; int error; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); if (ctlr->chip->max_dma < ATA_UDMA2) { mode = ata_check_80pin(atadev, mode); } else if (ctlr->chip->max_dma < ATA_SA150 && mode > ATA_UDMA2 && (pci_read_config(parent, 0x79, 1) & (atadev->channel->unit ? 0x02 : 0x01))) { ata_prtdev(atadev, "DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (error) return; mval = pci_read_config(parent, mreg, 1) & ~mask; if (ctlr->chip->max_dma < ATA_SA150) { if (mode >= ATA_UDMA0) { u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; u_int8_t ureg = 0xac + rego; pci_write_config(parent, mreg, mval | (0x03 << (ATA_DEV(atadev->unit) << 2)), 1); pci_write_config(parent, ureg, (pci_read_config(parent, ureg, 1) & ~0x3f) | udmatimings[mode & ATA_MODE_MASK], 1); } else if (mode >= ATA_WDMA0) { u_int8_t dreg = 0xa8 + rego; u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; pci_write_config(parent, mreg, mval | (0x02 << (ATA_DEV(atadev->unit) << 2)), 1); pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); } else { u_int8_t preg = 0xa4 + rego; u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; pci_write_config(parent, mreg, mval | (0x01 << (ATA_DEV(atadev->unit) << 2)), 1); pci_write_config(parent, preg, piotimings[mode & ATA_MODE_MASK], 2); } } atadev->mode = mode; } static void ata_cmd_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int error; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); mode = ata_check_80pin(atadev, mode); error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (!error) { int treg = 0x54 + (devno < 3) ? (devno << 1) : 7; int ureg = atadev->channel->unit ? 0x7b : 0x73; if (mode >= ATA_UDMA0) { int udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 }, { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } }; u_int8_t umode = pci_read_config(parent, ureg, 1); umode &= ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca); umode |= udmatimings[mode & ATA_MODE_MASK][ATA_DEV(atadev->unit)]; pci_write_config(parent, ureg, umode, 1); } else if (mode >= ATA_WDMA0) { int dmatimings[] = { 0x87, 0x32, 0x3f }; pci_write_config(parent, treg, dmatimings[mode & ATA_MODE_MASK], 1); pci_write_config(parent, ureg, pci_read_config(parent, ureg, 1) & ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); } else { int piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f }; pci_write_config(parent, treg, piotimings[(mode & ATA_MODE_MASK) - ATA_PIO0], 1); pci_write_config(parent, ureg, pci_read_config(parent, ureg, 1) & ~(atadev->unit == ATA_MASTER ? 0x35 : 0xca), 1); } atadev->mode = mode; } } /* * SiS chipset support functions */ int ata_sis_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_SIS963, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 963" }, /* south */ { ATA_SIS962, 0x00, SIS133NEW, 0, ATA_UDMA6, "SiS 962" }, /* south */ { ATA_SIS755, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 755" }, /* ext south */ { ATA_SIS752, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 752" }, /* unknown */ { ATA_SIS751, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 751" }, /* unknown */ { ATA_SIS750, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 750" }, /* unknown */ { ATA_SIS748, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 748" }, /* unknown */ { ATA_SIS746, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 746" }, /* ext south */ { ATA_SIS745, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 745" }, /* 1chip */ { ATA_SIS740, 0x00, SIS_SOUTH, 0, ATA_UDMA5, "SiS 740" }, /* ext south */ { ATA_SIS735, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 735" }, /* 1chip */ { ATA_SIS733, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 733" }, /* 1chip */ { ATA_SIS730, 0x00, SIS100OLD, 0, ATA_UDMA5, "SiS 730" }, /* 1chip */ { ATA_SIS658, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 658" }, /* ext south */ { ATA_SIS655, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 655" }, /* ext south */ { ATA_SIS652, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 652" }, /* unknown */ { ATA_SIS651, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 651" }, /* ext south */ { ATA_SIS650, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 650" }, /* ext south */ { ATA_SIS648, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 648" }, /* ext south */ { ATA_SIS646, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 645DX"},/* ext south */ { ATA_SIS645, 0x00, SIS_SOUTH, 0, ATA_UDMA6, "SiS 645" }, /* ext south */ { ATA_SIS640, 0x00, SIS_SOUTH, 0, ATA_UDMA4, "SiS 640" }, /* ext south */ { ATA_SIS635, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 635" }, /* 1chip */ { ATA_SIS633, 0x00, SIS100NEW, 0, ATA_UDMA5, "SiS 633" }, /* unknown */ { ATA_SIS630, 0x30, SIS100OLD, 0, ATA_UDMA5, "SiS 630S"}, /* 1chip */ { ATA_SIS630, 0x00, SIS66, 0, ATA_UDMA4, "SiS 630" }, /* 1chip */ { ATA_SIS620, 0x00, SIS66, 0, ATA_UDMA4, "SiS 620" }, /* 1chip */ { ATA_SIS550, 0x00, SIS66, 0, ATA_UDMA5, "SiS 550" }, { ATA_SIS540, 0x00, SIS66, 0, ATA_UDMA4, "SiS 540" }, { ATA_SIS530, 0x00, SIS66, 0, ATA_UDMA4, "SiS 530" }, { ATA_SIS5513, 0xc2, SIS33, 0, ATA_UDMA2, "SiS 5513" }, { ATA_SIS5513, 0x00, SIS33, 0, ATA_WDMA2, "SiS 5513" }, { 0, 0, 0, 0, 0, 0 }}; char buffer[64]; if (!(idx = ata_find_chip(dev, ids, -1))) return ENXIO; if (idx->cfg1 == SIS_SOUTH) { pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) & 0x7f, 1); if (pci_read_config(dev, 0x00, 4) == ATA_SIS5518) { idx->cfg1 = SIS133NEW; sprintf(buffer, "SiS 96X %s controller",ata_mode2str(idx->max_dma)); } else { struct ata_chip_id id[] = {{ ATA_SISSOUTH, 0x10, 0, 0, ATA_UDMA6, "SiS 961" }, { 0, 0, 0, 0, 0, 0 }}; if (ata_find_chip(dev, id, pci_get_slot(dev))) idx->cfg1 = SIS133OLD; else { idx->max_dma = ATA_UDMA5; idx->cfg1 = SIS100NEW; } sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma)); } pci_write_config(dev, 0x57, pci_read_config(dev, 0x57, 1) | 0x80, 1); } else sprintf(buffer,"%s %s controller",idx->text,ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_sis_chipinit; return 0; } static int ata_sis_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; switch (ctlr->chip->cfg1) { case SIS33: break; case SIS66: case SIS100OLD: pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) | 0x04, 1); break; case SIS100NEW: case SIS133OLD: pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) | 0x01, 1); break; case SIS133NEW: pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) & 0xfff7, 2); pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) & 0xfff7, 2); break; default: return ENXIO; } ctlr->setmode = ata_sis_setmode; return 0; } static void ata_sis_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int error; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); if (ctlr->chip->cfg1 == SIS133NEW) { if (mode > ATA_UDMA2 && pci_read_config(parent, atadev->channel->unit?0x52:0x50,2)&0x8000){ ata_prtdev(atadev, "DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } } else { if (mode > ATA_UDMA2 && pci_read_config(parent, 0x48, 1)&(atadev->channel->unit?0x20:0x10)){ ata_prtdev(atadev, "DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } } error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (!error) { switch (ctlr->chip->cfg1) { case SIS133NEW: { u_int32_t timings[] = { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008, 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac, 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c}; u_int32_t reg; reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2); pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4); break; } case SIS133OLD: { u_int16_t timings[] = { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 }; u_int16_t reg = 0x40 + (devno << 1); pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); break; } case SIS100NEW: { u_int16_t timings[] = { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 }; u_int16_t reg = 0x40 + (devno << 1); pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); break; } case SIS100OLD: case SIS66: case SIS33: { u_int16_t timings[] = { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 }; u_int16_t reg = 0x40 + (devno << 1); pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2); break; } } atadev->mode = mode; } } /* VIA chipsets */ int ata_via_ident(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); struct ata_chip_id *idx; static struct ata_chip_id ids[] = {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "VIA 82C586B" }, { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "VIA 82C586" }, { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "VIA 82C596B" }, { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C596" }, { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "VIA 82C686B"}, { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "VIA 82C686A" }, { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "VIA 82C686" }, { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "VIA 8231" }, { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233" }, { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "VIA 8233C" }, { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8233A" }, { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "VIA 8235" }, { 0, 0, 0, 0, 0, 0 }}; char buffer[64]; if (!(idx = ata_find_chip(dev, ids, pci_get_slot(dev)))) return ENXIO; sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma)); device_set_desc_copy(dev, buffer); ctlr->chip = idx; ctlr->chipinit = ata_via_chipinit; return 0; } static int ata_via_chipinit(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); if (ata_setup_interrupt(dev)) return ENXIO; /* prepare for ATA-66 on the 82C686a and 82C596b */ if (ctlr->chip->cfg2 & VIACLK) pci_write_config(dev, 0x50, 0x030b030b, 4); /* the southbridge might need the data corruption fix */ if (ctlr->chip->cfg2 & VIABUG) ata_via_southbridge_fixup(dev); /* set prefetch, postwrite */ pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1); /* set fifo configuration half'n'half */ pci_write_config(dev, 0x43, (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1); /* set status register read retry */ pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1); /* set DMA read & end-of-sector fifo flush */ pci_write_config(dev, 0x46, (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1); /* set sector size */ pci_write_config(dev, 0x60, DEV_BSIZE, 2); pci_write_config(dev, 0x68, DEV_BSIZE, 2); ctlr->setmode = ata_via_family_setmode; return 0; } static void ata_via_southbridge_fixup(device_t dev) { device_t *children; int nchildren, i; if (device_get_children(device_get_parent(dev), &children, &nchildren)) return; for (i = 0; i < nchildren; i++) { if (pci_get_devid(children[i]) == ATA_VIA8363 || pci_get_devid(children[i]) == ATA_VIA8371 || pci_get_devid(children[i]) == ATA_VIA8662 || pci_get_devid(children[i]) == ATA_VIA8361) { u_int8_t reg76 = pci_read_config(children[i], 0x76, 1); if ((reg76 & 0xf0) != 0xd0) { device_printf(dev, "Correcting VIA config for southbridge data corruption bug\n"); pci_write_config(children[i], 0x75, 0x80, 1); pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1); } break; } } free(children, M_TEMP); } /* common code for VIA, AMD & nVidia */ static void ata_via_family_setmode(struct ata_device *atadev, int mode) { device_t parent = device_get_parent(atadev->channel->dev); struct ata_pci_controller *ctlr = device_get_softc(parent); u_int8_t timings[] = { 0xff, 0xff, 0xff, 0x55, 0x51, 0xff, 0x55, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51 }; int modes[][7] = { { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ int devno = (atadev->channel->unit << 1) + ATA_DEV(atadev->unit); int reg = 0x53 - devno; int error; mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma); if (ctlr->chip->cfg2 & AMDCABLE) { if (mode > ATA_UDMA2 && !pci_read_config(parent, 0x42, 1) & (1<chip->cfg2 & NVIDIA) reg += 0x10; pci_write_config(parent, reg - 0x08, timings[ata_mode2idx(mode)], 1); error = ata_controlcmd(atadev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode); if (bootverbose) ata_prtdev(atadev, "%ssetting %s on %s chip\n", (error) ? "FAILURE " : "", ata_mode2str(mode), ctlr->chip->text); if (!error) { if (mode >= ATA_UDMA0) pci_write_config(parent, reg, modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1); else pci_write_config(parent, reg, 0x8b, 1); atadev->mode = mode; } } /* misc functions */ static struct ata_chip_id * ata_find_chip(device_t dev, struct ata_chip_id *index, int slot) { device_t *children; int nchildren, i; if (device_get_children(device_get_parent(dev), &children, &nchildren)) return 0; while (index->chipid != 0) { for (i = 0; i < nchildren; i++) { if (((slot >= 0 && pci_get_slot(children[i]) == slot) || slot < 0)&& pci_get_devid(children[i]) == index->chipid && pci_get_revid(children[i]) >= index->chiprev) { free(children, M_TEMP); return index; } } index++; } free(children, M_TEMP); return NULL; } static struct ata_chip_id * ata_match_chip(device_t dev, struct ata_chip_id *index) { while (index->chipid != 0) { if (pci_get_devid(dev) == index->chipid && pci_get_revid(dev) >= index->chiprev) return index; index++; } return NULL; } static int ata_setup_interrupt(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); int rid = ATA_IRQ_RID; if (!ATA_MASTERDEV(dev)) { if (!(ctlr->r_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE))) { device_printf(dev, "unable to map interrupt\n"); return ENXIO; } if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, ata_generic_intr, ctlr, &ctlr->handle))) { device_printf(dev, "unable to setup interrupt\n"); return ENXIO; } } return 0; } static void ata_serialize(struct ata_channel *ch, int flags) { struct ata_pci_controller *scp = device_get_softc(device_get_parent(ch->dev)); switch (flags) { case ATA_LF_LOCK: if (scp->locked_ch == ch->unit) break; while (!atomic_cmpset_acq_int(&scp->locked_ch, -1, ch->unit)) tsleep(ch->locking, PRIBIO, "atasrl", 1); break; case ATA_LF_UNLOCK: if (scp->locked_ch == -1 || scp->locked_ch != ch->unit) break; atomic_store_rel_int(&scp->locked_ch, -1); wakeup(ch->locking); break; } return; } static int ata_check_80pin(struct ata_device *atadev, int mode) { if (mode > ATA_UDMA2 && !(atadev->param->hwres & ATA_CABLE_ID)) { ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); mode = ATA_UDMA2; } return mode; } static int ata_mode2idx(int mode) { if ((mode & ATA_DMA_MASK) == ATA_UDMA0) return (mode & ATA_MODE_MASK) + 8; if ((mode & ATA_DMA_MASK) == ATA_WDMA0) return (mode & ATA_MODE_MASK) + 5; return (mode & ATA_MODE_MASK) - ATA_PIO0; } Index: head/sys/dev/ata/ata-dma.c =================================================================== --- head/sys/dev/ata/ata-dma.c (revision 121309) +++ head/sys/dev/ata/ata-dma.c (revision 121310) @@ -1,252 +1,253 @@ /*- * Copyright (c) 1998 - 2003 Søren Schmidt * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification, immediately at the beginning of the file. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* prototypes */ static void ata_dmaalloc(struct ata_channel *); static void ata_dmafree(struct ata_channel *); static void ata_dmasetupd_cb(void *, bus_dma_segment_t *, int, int); -static int ata_dmasetup(struct ata_device *, caddr_t, int32_t); +static int ata_dmaload(struct ata_device *, caddr_t, int32_t, int); +static int ata_dmaunload(struct ata_channel *); /* local vars */ static MALLOC_DEFINE(M_ATADMA, "ATA DMA", "ATA driver DMA"); /* misc defines */ #define MAXSEGSZ PAGE_SIZE #define MAXTABSZ PAGE_SIZE #define MAXCTLDMASZ (2 * (MAXTABSZ + MAXPHYS)) struct ata_dc_cb_args { bus_addr_t maddr; int error; }; void ata_dmainit(struct ata_channel *ch) { if ((ch->dma = malloc(sizeof(struct ata_dma), M_ATADMA, M_NOWAIT|M_ZERO))) { ch->dma->alloc = ata_dmaalloc; ch->dma->free = ata_dmafree; - ch->dma->setup = ata_dmasetup; - ch->dma->start = ata_dmastart; - ch->dma->stop = ata_dmastop; + ch->dma->load = ata_dmaload; + ch->dma->unload = ata_dmaunload; ch->dma->alignment = 2; ch->dma->max_iosize = 64*1024; } } static void ata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) { struct ata_dc_cb_args *cba = (struct ata_dc_cb_args *)xsc; if (!(cba->error = error)) cba->maddr = segs[0].ds_addr; } static void ata_dmaalloc(struct ata_channel *ch) { struct ata_dc_cb_args ccba; if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXCTLDMASZ, ATA_DMA_ENTRIES, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL, &ch->dma->dmatag)) goto error; if (bus_dma_tag_create(ch->dma->dmatag, PAGE_SIZE, PAGE_SIZE, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXTABSZ, 1, MAXTABSZ, BUS_DMA_ALLOCNOW, NULL, NULL, &ch->dma->cdmatag)) goto error; if (bus_dma_tag_create(ch->dma->dmatag, ch->dma->alignment, 64*1024, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXPHYS, ATA_DMA_ENTRIES, MAXSEGSZ, BUS_DMA_ALLOCNOW, NULL, NULL, &ch->dma->ddmatag)) goto error; if (bus_dmamem_alloc(ch->dma->cdmatag, (void **)&ch->dma->dmatab, 0, &ch->dma->cdmamap)) goto error; if (bus_dmamap_load(ch->dma->cdmatag, ch->dma->cdmamap, ch->dma->dmatab, MAXTABSZ, ata_dmasetupc_cb, &ccba, 0) || ccba.error) { bus_dmamem_free(ch->dma->cdmatag, ch->dma->dmatab,ch->dma->cdmamap); goto error; } ch->dma->mdmatab = ccba.maddr; if (bus_dmamap_create(ch->dma->ddmatag, 0, &ch->dma->ddmamap)) goto error; return; error: ata_printf(ch, -1, "WARNING - DMA tag allocation failed, disabling DMA\n"); ata_dmafree(ch); free(ch->dma, M_ATADMA); ch->dma = NULL; } static void ata_dmafree(struct ata_channel *ch) { if (ch->dma->mdmatab) { bus_dmamap_unload(ch->dma->cdmatag, ch->dma->cdmamap); bus_dmamem_free(ch->dma->cdmatag, ch->dma->dmatab, ch->dma->cdmamap); ch->dma->mdmatab = 0; ch->dma->cdmamap = NULL; ch->dma->dmatab = NULL; } if (ch->dma->ddmamap) { bus_dmamap_destroy(ch->dma->ddmatag, ch->dma->ddmamap); ch->dma->ddmamap = NULL; } if (ch->dma->cdmatag) { bus_dma_tag_destroy(ch->dma->cdmatag); ch->dma->cdmatag = NULL; } if (ch->dma->ddmatag) { bus_dma_tag_destroy(ch->dma->ddmatag); ch->dma->ddmatag = NULL; } if (ch->dma->dmatag) { bus_dma_tag_destroy(ch->dma->dmatag); ch->dma->dmatag = NULL; } } struct ata_dmasetup_data_cb_args { struct ata_dmaentry *dmatab; int error; }; static void ata_dmasetupd_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) { struct ata_dmasetup_data_cb_args *cba = (struct ata_dmasetup_data_cb_args *)xsc; bus_size_t cnt; u_int32_t lastcount; int i, j; cba->error = error; if (error != 0) return; lastcount = j = 0; for (i = 0; i < nsegs; i++) { /* * A maximum segment size was specified for bus_dma_tag_create, but * some busdma code does not seem to honor this, so fix up if needed. */ for (cnt = 0; cnt < segs[i].ds_len; cnt += MAXSEGSZ, j++) { cba->dmatab[j].base = htole32(segs[i].ds_addr + cnt); lastcount = ulmin(segs[i].ds_len - cnt, MAXSEGSZ) & 0xffff; cba->dmatab[j].count = htole32(lastcount); } } cba->dmatab[j - 1].count = htole32(lastcount | ATA_DMA_EOT); } static int -ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count) +ata_dmaload(struct ata_device *atadev, caddr_t data, int32_t count, int dir) { struct ata_channel *ch = atadev->channel; + struct ata_dmasetup_data_cb_args cba; - if (((uintptr_t)data & (ch->dma->alignment - 1)) || - (count & (ch->dma->alignment - 1))) { - ata_prtdev(atadev, "FAILURE - non aligned DMA transfer attempted\n"); + if (ch->dma->flags & ATA_DMA_ACTIVE) { + ata_prtdev(atadev, "FAILURE - already active DMA on this device\n"); return -1; } if (!count) { ata_prtdev(atadev, "FAILURE - zero length DMA transfer attempted\n"); return -1; } + if (((uintptr_t)data & (ch->dma->alignment - 1)) || + (count & (ch->dma->alignment - 1))) { + ata_prtdev(atadev, "FAILURE - non aligned DMA transfer attempted\n"); + return -1; + } if (count > ch->dma->max_iosize) { ata_prtdev(atadev, "FAILURE - oversized DMA transfer attempted %d > %d\n", count, ch->dma->max_iosize); return -1; } - return 0; -} -int -ata_dmastart(struct ata_channel *ch, caddr_t data, int32_t count, int dir) -{ - struct ata_dmasetup_data_cb_args cba; - - if (ch->dma->flags & ATA_DMA_ACTIVE) - panic("ata_dmasetup: transfer active on this device!"); - cba.dmatab = ch->dma->dmatab; + bus_dmamap_sync(ch->dma->cdmatag, ch->dma->cdmamap, BUS_DMASYNC_PREWRITE); + if (bus_dmamap_load(ch->dma->ddmatag, ch->dma->ddmamap, data, count, ata_dmasetupd_cb, &cba, 0) || cba.error) return -1; bus_dmamap_sync(ch->dma->ddmatag, ch->dma->ddmamap, dir ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); + ch->dma->cur_iosize = count; ch->dma->flags = dir ? (ATA_DMA_ACTIVE | ATA_DMA_READ) : ATA_DMA_ACTIVE; + return 0; } int -ata_dmastop(struct ata_channel *ch) +ata_dmaunload(struct ata_channel *ch) { bus_dmamap_sync(ch->dma->cdmatag, ch->dma->cdmamap, BUS_DMASYNC_POSTWRITE); bus_dmamap_sync(ch->dma->ddmatag, ch->dma->ddmamap, (ch->dma->flags & ATA_DMA_READ) != 0 ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(ch->dma->ddmatag, ch->dma->ddmamap); + ch->dma->cur_iosize = 0; ch->dma->flags = 0; + return 0; } Index: head/sys/dev/ata/ata-lowlevel.c =================================================================== --- head/sys/dev/ata/ata-lowlevel.c (revision 121309) +++ head/sys/dev/ata/ata-lowlevel.c (revision 121310) @@ -1,835 +1,838 @@ /*- * Copyright (c) 1998 - 2003 Søren Schmidt * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification, immediately at the beginning of the file. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ata.h" #include #include #include #include #include #include #include #include #include #include #include /* prototypes */ static int ata_transaction(struct ata_request *); static void ata_interrupt(void *); static void ata_reset(struct ata_channel *); static int ata_wait(struct ata_device *, u_int8_t); static int ata_command(struct ata_device *, u_int8_t, u_int64_t, u_int16_t, u_int16_t); static void ata_pio_read(struct ata_request *, int); static void ata_pio_write(struct ata_request *, int); /* local vars */ static int atadebug = 0; /* * low level ATA functions */ void ata_generic_hw(struct ata_channel *ch) { ch->hw.reset = ata_reset; ch->hw.transaction = ata_transaction; ch->hw.interrupt = ata_interrupt; } /* must be called with ATA channel locked */ static int ata_transaction(struct ata_request *request) { /* record the request as running */ request->device->channel->running = request; /* disable ATAPI DMA writes if HW doesn't support it */ if ((request->device->channel->flags & ATA_ATAPI_DMA_RO) && ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) request->flags &= ~ATA_R_DMA; switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { /* ATA PIO data transfer and control commands */ default: { /* record command direction here as our request might be done later */ int write = (request->flags & ATA_R_WRITE); /* issue command */ if (ata_command(request->device, request->u.ata.command, request->u.ata.lba, request->u.ata.count, request->u.ata.feature)) { ata_prtdev(request->device, "error issueing PIO command\n"); request->result = EIO; break; } /* if write command output the data */ if (write) { if (ata_wait(request->device, (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { ata_prtdev(request->device,"timeout waiting for write DRQ"); request->result = EIO; break; } ata_pio_write(request, request->transfersize); } } /* return and wait for interrupt */ return ATA_OP_CONTINUES; /* ATA DMA data transfer commands */ case ATA_R_DMA: - /* check sanity and setup DMA engine */ - if (request->device->channel->dma->setup(request->device, - request->data, - request->bytecount)) { + /* check sanity, setup SG list and DMA engine */ + if (request->device->channel->dma->load(request->device, + request->data, + request->bytecount, + request->flags & ATA_R_READ)) { ata_prtdev(request->device, "setting up DMA failed\n"); request->result = EIO; break; } /* issue command */ if (ata_command(request->device, request->u.ata.command, request->u.ata.lba, request->u.ata.count, request->u.ata.feature)) { ata_prtdev(request->device, "error issuing DMA command\n"); request->result = EIO; break; } /* start DMA engine */ - if (request->device->channel->dma->start(request->device->channel, - request->data, - request->bytecount, - request->flags & ATA_R_READ)) { + if (request->device->channel->dma->start(request->device->channel)) { ata_prtdev(request->device, "error starting DMA\n"); request->result = EIO; break; } /* return and wait for interrupt */ return ATA_OP_CONTINUES; /* ATAPI PIO commands */ case ATA_R_ATAPI: /* is this just a POLL DSC command ? */ if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { ATA_IDX_OUTB(request->device->channel, ATA_DRIVE, ATA_D_IBM | request->device->unit); DELAY(10); if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC)) request->result = EBUSY; break; } /* start ATAPI operation */ if (ata_command(request->device, ATA_PACKET_CMD, request->transfersize << 8, 0, 0)) { ata_prtdev(request->device, "error issuing ATA PACKET command\n"); request->result = EIO; break; } /* command interrupt device ? just return and wait for interrupt */ if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) return ATA_OP_CONTINUES; /* wait for ready to write ATAPI command block */ { int timeout = 5000; /* might be less for fast devices */ while (timeout--) { int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON); int status = ATA_IDX_INB(request->device->channel, ATA_STATUS); if (((reason & (ATA_I_CMD | ATA_I_IN)) | (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) break; DELAY(20); } if (timeout <= 0) { ata_prtdev(request->device, "timeout waiting for ATAPI ready\n"); request->result = EIO; break; } } /* this seems to be needed for some (slow) devices */ DELAY(10); /* output actual command block */ ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA, (int16_t *)request->u.atapi.ccb, (request->device->param->config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12 ? 6 : 8); /* return and wait for interrupt */ return ATA_OP_CONTINUES; case ATA_R_ATAPI|ATA_R_DMA: /* is this just a POLL DSC command ? */ if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { ATA_IDX_OUTB(request->device->channel, ATA_DRIVE, ATA_D_IBM | request->device->unit); DELAY(10); if (!(ATA_IDX_INB(request->device->channel, ATA_ALTSTAT)&ATA_S_DSC)) request->result = EBUSY; break; } - /* check sanity and setup DMA engine */ - if (request->device->channel->dma->setup(request->device, - request->data, - request->bytecount)) { + /* check sanity, setup SG list and DMA engine */ + if (request->device->channel->dma->load(request->device, + request->data, + request->bytecount, + request->flags & ATA_R_READ)) { ata_prtdev(request->device, "setting up DMA failed\n"); request->result = EIO; break; } /* start ATAPI operation */ if (ata_command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { ata_prtdev(request->device, "error issuing ATAPI packet command\n"); request->result = EIO; break; } /* wait for ready to write ATAPI command block */ { int timeout = 5000; /* might be less for fast devices */ while (timeout--) { int reason = ATA_IDX_INB(request->device->channel, ATA_IREASON); int status = ATA_IDX_INB(request->device->channel, ATA_STATUS); if (((reason & (ATA_I_CMD | ATA_I_IN)) | (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) break; DELAY(20); } if (timeout <= 0) { ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); request->result = EIO; break; } } /* this seems to be needed for some (slow) devices */ DELAY(10); /* output actual command block */ ATA_IDX_OUTSW_STRM(request->device->channel, ATA_DATA, (int16_t *)request->u.atapi.ccb, (request->device->param->config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12 ? 6 : 8); /* start DMA engine */ - if (request->device->channel->dma->start(request->device->channel, - request->data, - request->bytecount, - request->flags & ATA_R_READ)) { + if (request->device->channel->dma->start(request->device->channel)) { request->result = EIO; break; } /* return and wait for interrupt */ return ATA_OP_CONTINUES; } /* request finish here */ request->device->channel->running = NULL; return ATA_OP_FINISHED; } static void ata_interrupt(void *data) { struct ata_channel *ch = (struct ata_channel *)data; struct ata_request *request = ch->running; int length; /* ignore this interrupt if there is no running request */ if (!request) { if (ATA_LOCK_CH(ch, ATA_CONTROL)) { u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR); if (bootverbose) ata_printf(ch, -1, "spurious interrupt - status=0x%02x error=0x%02x\n", status, error); ATA_UNLOCK_CH(ch); } else { if (bootverbose) ata_printf(ch, -1, "spurious interrupt - channel busy\n"); } return; } /* ignore interrupt if device is busy */ if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { DELAY(100); if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ)) return; } /* clear interrupt and get status */ request->status = ATA_IDX_INB(ch, ATA_STATUS); switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { /* ATA PIO data transfer and control commands */ default: /* if we got an error we are done with the HW */ if (request->status & ATA_S_ERROR) { request->error = ATA_IDX_INB(ch, ATA_ERROR); break; } /* if read data get it */ if (request->flags & ATA_R_READ) ata_pio_read(request, request->transfersize); /* update how far we've gotten */ request->donecount += request->transfersize; /* do we need a scoop more ? */ if (request->bytecount > request->donecount) { /* set this transfer size according to HW capabilities */ request->transfersize = min((request->bytecount - request->donecount), request->transfersize); /* if data write command, output the data */ if (request->flags & ATA_R_WRITE) { /* if we get an error here we are done with the HW */ if (ata_wait(request->device, (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { ata_prtdev(request->device,"timeout waiting for write DRQ"); request->status = ATA_IDX_INB(ch, ATA_STATUS); break; } /* output data and return waiting for new interrupt */ ata_pio_write(request, request->transfersize); return; } /* if data read command, return & wait for interrupt */ else if (request->flags & ATA_R_READ) { return; } else ata_prtdev(request->device, "FAILURE - %s shouldn't loop on control cmd\n", ata_cmd2str(request)); } /* done with HW */ break; /* ATA DMA data transfer commands */ case ATA_R_DMA: /* stop DMA engine and get status */ request->dmastat = ch->dma->stop(ch); /* did we get error or data */ if (request->status & ATA_S_ERROR) request->error = ATA_IDX_INB(ch, ATA_ERROR); else if (request->dmastat & ATA_BMSTAT_ERROR) request->status |= ATA_S_ERROR; else request->donecount = request->bytecount; + /* release SG list etc */ + ch->dma->unload(ch); + /* done with HW */ break; /* ATAPI PIO commands */ case ATA_R_ATAPI: length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | (request->status & ATA_S_DRQ)) { case ATAPI_P_CMDOUT: /* this seems to be needed for some (slow) devices */ DELAY(10); if (!(request->status & ATA_S_DRQ)) { ata_prtdev(request->device, "command interrupt without DRQ\n"); request->status = ATA_S_ERROR; break; } ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, (request->device->param->config & ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); /* return wait for interrupt */ return; case ATAPI_P_WRITE: if (request->flags & ATA_R_READ) { request->status = ATA_S_ERROR; ata_prtdev(request->device, "%s trying to write on read buffer\n", ata_cmd2str(request)); break; } ata_pio_write(request, length); request->donecount += length; /* set next transfer size according to HW capabilities */ request->transfersize = min((request->bytecount-request->donecount), request->transfersize); /* return wait for interrupt */ return; case ATAPI_P_READ: if (request->flags & ATA_R_WRITE) { request->status = ATA_S_ERROR; ata_prtdev(request->device, "%s trying to read on write buffer\n", ata_cmd2str(request)); break; } ata_pio_read(request, length); request->donecount += length; /* set next transfer size according to HW capabilities */ request->transfersize = min((request->bytecount-request->donecount), request->transfersize); /* return wait for interrupt */ return; case ATAPI_P_DONEDRQ: ata_prtdev(request->device, "WARNING - %s DONEDRQ non conformant device\n", ata_cmd2str(request)); if (request->flags & ATA_R_READ) { ata_pio_read(request, length); request->donecount += length; } else if (request->flags & ATA_R_WRITE) { ata_pio_write(request, length); request->donecount += length; } else request->status = ATA_S_ERROR; /* FALLTHROUGH */ case ATAPI_P_ABORT: case ATAPI_P_DONE: if (request->status & (ATA_S_ERROR | ATA_S_DWF)) request->error = ATA_IDX_INB(ch, ATA_ERROR); break; default: ata_prtdev(request->device, "unknown transfer phase\n"); request->status = ATA_S_ERROR; } + /* done with HW */ break; /* ATAPI DMA commands */ case ATA_R_ATAPI|ATA_R_DMA: /* stop the engine and get engine status */ request->dmastat = ch->dma->stop(ch); /* did we get error or data */ if (request->status & (ATA_S_ERROR | ATA_S_DWF)) request->error = ATA_IDX_INB(ch, ATA_ERROR); else if (request->dmastat & ATA_BMSTAT_ERROR) request->status |= ATA_S_ERROR; else request->donecount = request->bytecount; + + /* release SG list etc */ + ch->dma->unload(ch); /* done with HW */ break; } ata_finish(request); - /* unlock the ATA HW for new work */ + /* unlock the ATA channel for new work */ ch->running = NULL; ATA_UNLOCK_CH(ch); ch->locking(ch, ATA_LF_UNLOCK); } /* must be called with ATA channel locked */ static void ata_reset(struct ata_channel *ch) { u_int8_t err, lsb, msb, ostat0, ostat1; u_int8_t stat0 = 0, stat1 = 0; int mask = 0, timeout; /* do we have any signs of ATA/ATAPI HW being present ? */ ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); DELAY(10); ostat0 = ATA_IDX_INB(ch, ATA_STATUS); if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) { stat0 = ATA_S_BUSY; mask |= 0x01; } ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); DELAY(10); ostat1 = ATA_IDX_INB(ch, ATA_STATUS); /* in some setups we dont want to test for a slave */ if (!(ch->flags & ATA_NO_SLAVE)) { if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) { stat1 = ATA_S_BUSY; mask |= 0x02; } } /* if nothing showed up no need to get any further */ /* SOS is that too strong?, we just might loose devices here XXX */ ch->devices = 0; if (!mask) return; if (bootverbose) ata_printf(ch, -1, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n", mask, ostat0, ostat1); /* reset channel */ ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); DELAY(10); ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS | ATA_A_RESET); DELAY(10000); ATA_IDX_OUTB(ch, ATA_ALTSTAT, ATA_A_IDS); DELAY(100000); ATA_IDX_INB(ch, ATA_ERROR); /* wait for BUSY to go inactive */ for (timeout = 0; timeout < 310; timeout++) { if (stat0 & ATA_S_BUSY) { ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); DELAY(10); err = ATA_IDX_INB(ch, ATA_ERROR); lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); msb = ATA_IDX_INB(ch, ATA_CYL_MSB); stat0 = ATA_IDX_INB(ch, ATA_STATUS); if (bootverbose) ata_printf(ch, ATA_MASTER, "stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", stat0, err, lsb, msb); if (!(stat0 & ATA_S_BUSY)) { if ((err & 0x7f) == ATA_E_ILI) { if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { ch->devices |= ATA_ATAPI_MASTER; } else if (stat0 & ATA_S_READY) { ch->devices |= ATA_ATA_MASTER; } } else if ((stat0 & 0x4f) && err == lsb && err == msb) { stat0 |= ATA_S_BUSY; } } } if (stat1 & ATA_S_BUSY) { ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); DELAY(10); err = ATA_IDX_INB(ch, ATA_ERROR); lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); msb = ATA_IDX_INB(ch, ATA_CYL_MSB); stat1 = ATA_IDX_INB(ch, ATA_STATUS); if (bootverbose) ata_printf(ch, ATA_SLAVE, " stat=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n", stat1, err, lsb, msb); if (!(stat1 & ATA_S_BUSY)) { if ((err & 0x7f) == ATA_E_ILI) { if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) { ch->devices |= ATA_ATAPI_SLAVE; } else if (stat1 & ATA_S_READY) { ch->devices |= ATA_ATA_SLAVE; } } else if ((stat1 & 0x4f) && err == lsb && err == msb) { stat1 |= ATA_S_BUSY; } } } if (mask == 0x01) /* wait for master only */ if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 20)) break; if (mask == 0x02) /* wait for slave only */ if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 20)) break; if (mask == 0x03) /* wait for both master & slave */ if ((!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 20)) && (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 20))) break; DELAY(100000); } if (stat0 & ATA_S_BUSY) mask &= ~0x01; if (stat1 & ATA_S_BUSY) mask &= ~0x02; if (bootverbose) ata_printf(ch, -1, "reset tp2 mask=%02x stat0=%02x stat1=%02x devices=0x%b\n", mask, stat0, stat1, ch->devices, "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); #if 0 if (!mask) return; if (mask & 0x01 && ostat0 != 0x00 && !(ch->devices & (ATA_ATA_MASTER | ATA_ATAPI_MASTER))) { ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_MASTER); DELAY(10); ATA_IDX_OUTB(ch, ATA_ERROR, 0x58); ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0xa5); err = ATA_IDX_INB(ch, ATA_ERROR); lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); if (bootverbose) ata_printf(ch, ATA_MASTER, "ATA err=0x%02x lsb=0x%02x\n", err, lsb); if (err != 0x58 && lsb == 0xa5) ch->devices |= ATA_ATA_MASTER; } if (mask & 0x02 && ostat1 != 0x00 && !(ch->devices & (ATA_ATA_SLAVE | ATA_ATAPI_SLAVE))) { ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_SLAVE); DELAY(10); ATA_IDX_OUTB(ch, ATA_ERROR, 0x58); ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0xa5); err = ATA_IDX_INB(ch, ATA_ERROR); lsb = ATA_IDX_INB(ch, ATA_CYL_LSB); if (bootverbose) ata_printf(ch, ATA_SLAVE, "ATA err=0x%02x lsb=0x%02x\n", err, lsb); if (err != 0x58 && lsb == 0xa5) ch->devices |= ATA_ATA_SLAVE; } if (bootverbose) ata_printf(ch, -1, "reset tp3 devices=0x%b\n", ch->devices, "\20\4ATAPI_SLAVE\3ATAPI_MASTER\2ATA_SLAVE\1ATA_MASTER"); #endif } static int ata_wait(struct ata_device *atadev, u_int8_t mask) { u_int8_t status; int timeout = 0; DELAY(1); /* wait 5 seconds for device to get !BUSY */ while (timeout < 5000000) { status = ATA_IDX_INB(atadev->channel, ATA_STATUS); /* if drive fails status, reselect the drive just to be sure */ if (status == 0xff) { ata_prtdev(atadev, "WARNING no status, reselecting device\n"); ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); DELAY(10); status = ATA_IDX_INB(atadev->channel, ATA_STATUS); if (status == 0xff) return -1; } /* are we done ? */ if (!(status & ATA_S_BUSY)) break; if (timeout > 1000) { timeout += 1000; DELAY(1000); } else { timeout += 10; DELAY(10); } } if (timeout >= 5000000) return -1; if (!mask) return (status & ATA_S_ERROR); DELAY(1); /* wait 50 msec for bits wanted */ timeout = 5000; while (timeout--) { status = ATA_IDX_INB(atadev->channel, ATA_STATUS); if ((status & mask) == mask) return (status & ATA_S_ERROR); DELAY (10); } return -1; } static int ata_command(struct ata_device *atadev, u_int8_t command, u_int64_t lba, u_int16_t count, u_int16_t feature) { if (atadebug) ata_prtdev(atadev, "ata_command: addr=%04lx, command=%02x, " "lba=%jd, count=%d, feature=%d\n", rman_get_start(atadev->channel->r_io[ATA_DATA].res), command, (intmax_t)lba, count, feature); /* select device */ ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit); /* ready to issue command ? */ if (ata_wait(atadev, 0) < 0) { ata_prtdev(atadev, "timeout sending command=%02x\n", command); return -1; } /* enable interrupt */ ATA_IDX_OUTB(atadev->channel, ATA_ALTSTAT, ATA_A_4BIT); /* only use 48bit addressing if needed (avoid bugs and overhead) */ if ((lba > 268435455 || count > 256) && atadev->param && atadev->param->support.command2 & ATA_SUPPORT_ADDRESS48) { /* translate command into 48bit version */ switch (command) { case ATA_READ: command = ATA_READ48; break; case ATA_READ_MUL: command = ATA_READ_MUL48; break; case ATA_READ_DMA: command = ATA_READ_DMA48; break; case ATA_READ_DMA_QUEUED: command = ATA_READ_DMA_QUEUED48; break; case ATA_WRITE: command = ATA_WRITE48; break; case ATA_WRITE_MUL: command = ATA_WRITE_MUL48; break; case ATA_WRITE_DMA: command = ATA_WRITE_DMA48; break; case ATA_WRITE_DMA_QUEUED: command = ATA_WRITE_DMA_QUEUED48; break; case ATA_FLUSHCACHE: command = ATA_FLUSHCACHE48; break; default: ata_prtdev(atadev, "can't translate cmd to 48bit version\n"); return -1; } ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, (feature>>8) & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_COUNT, (count>>8) & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, (lba>>24) & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>32) & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>40) & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_LBA | atadev->unit); atadev->channel->flags |= ATA_48BIT_ACTIVE; } else { ATA_IDX_OUTB(atadev->channel, ATA_FEATURE, feature); ATA_IDX_OUTB(atadev->channel, ATA_COUNT, count); ATA_IDX_OUTB(atadev->channel, ATA_SECTOR, lba & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_CYL_LSB, (lba>>8) & 0xff); ATA_IDX_OUTB(atadev->channel, ATA_CYL_MSB, (lba>>16) & 0xff); if (atadev->flags & ATA_D_USE_CHS) ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | atadev->unit | ((lba>>24) & 0xf)); else ATA_IDX_OUTB(atadev->channel, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | atadev->unit|((lba>>24)&0xf)); atadev->channel->flags &= ~ATA_48BIT_ACTIVE; } /* issue command to controller */ ATA_IDX_OUTB(atadev->channel, ATA_CMD, command); return 0; } static void ata_pio_read(struct ata_request *request, int length) { int size = min(request->transfersize, length); struct ata_channel *ch = request->device->channel; int resid; if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) ATA_IDX_INSW_STRM(ch, ATA_DATA, (void*)((uintptr_t)request->data+request->donecount), size / sizeof(int16_t)); else ATA_IDX_INSL_STRM(ch, ATA_DATA, (void*)((uintptr_t)request->data+request->donecount), size / sizeof(int32_t)); if (request->transfersize < length) { ata_prtdev(request->device, "WARNING - %s read data overrun %d>%d\n", ata_cmd2str(request), length, request->transfersize); for (resid = request->transfersize; resid < length; resid += sizeof(int16_t)) ATA_IDX_INW(ch, ATA_DATA); } } static void ata_pio_write(struct ata_request *request, int length) { int size = min(request->transfersize, length); struct ata_channel *ch = request->device->channel; int resid; if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t))) ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (void*)((uintptr_t)request->data+request->donecount), size / sizeof(int16_t)); else ATA_IDX_OUTSL_STRM(ch, ATA_DATA, (void*)((uintptr_t)request->data+request->donecount), size / sizeof(int32_t)); if (request->transfersize < length) { ata_prtdev(request->device, "WARNING - %s write data underrun %d>%d\n", ata_cmd2str(request), length, request->transfersize); for (resid = request->transfersize; resid < length; resid += sizeof(int16_t)) ATA_IDX_OUTW(ch, ATA_DATA, 0); } } Index: head/sys/dev/ata/ata-pci.c =================================================================== --- head/sys/dev/ata/ata-pci.c (revision 121309) +++ head/sys/dev/ata/ata-pci.c (revision 121310) @@ -1,526 +1,522 @@ /*- * Copyright (c) 1998 - 2003 Søren Schmidt * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification, immediately at the beginning of the file. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_ata.h" #include #include #include #include #include #include #include #include #include #include #ifdef __alpha__ #include #endif #include #include #include #include #include /* local vars */ static MALLOC_DEFINE(M_ATAPCI, "ATA PCI", "ATA driver PCI"); /* misc defines */ #define IOMASK 0xfffffffc /* prototypes */ static int ata_pci_allocate(device_t, struct ata_channel *); static void ata_pci_dmainit(struct ata_channel *); static void ata_pci_locknoop(struct ata_channel *, int); static int ata_pci_probe(device_t dev) { if (pci_get_class(dev) != PCIC_STORAGE) return ENXIO; switch (pci_get_vendor(dev)) { case ATA_ACARD_ID: return ata_acard_ident(dev); case ATA_ACER_LABS_ID: return ata_ali_ident(dev); case ATA_AMD_ID: return ata_amd_ident(dev); case ATA_CYRIX_ID: return ata_cyrix_ident(dev); case ATA_CYPRESS_ID: return ata_cypress_ident(dev); case ATA_HIGHPOINT_ID: return ata_highpoint_ident(dev); case ATA_INTEL_ID: return ata_intel_ident(dev); case ATA_NATIONAL_ID: return ata_national_ident(dev); case ATA_NVIDIA_ID: return ata_nvidia_ident(dev); case ATA_PROMISE_ID: return ata_promise_ident(dev); case ATA_SERVERWORKS_ID: return ata_serverworks_ident(dev); case ATA_SILICON_IMAGE_ID: return ata_sii_ident(dev); case ATA_SIS_ID: return ata_sis_ident(dev); case ATA_VIA_ID: return ata_via_ident(dev); case 0x16ca: if (pci_get_devid(dev) == 0x000116ca) { ata_generic_ident(dev); device_set_desc(dev, "Cenatek Rocket Drive controller"); return 0; } return ENXIO; case 0x1042: if (pci_get_devid(dev)==0x10001042 || pci_get_devid(dev)==0x10011042) { ata_generic_ident(dev); device_set_desc(dev, "RZ 100? ATA controller !WARNING! buggy HW data loss possible"); return 0; } return ENXIO; /* unknown chipset, try generic DMA if it seems possible */ default: if (pci_get_class(dev) == PCIC_STORAGE && (pci_get_subclass(dev) == PCIS_STORAGE_IDE)) return ata_generic_ident(dev); } return ENXIO; } static int ata_pci_attach(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(dev); u_int8_t class, subclass; u_int32_t type, cmd; int unit; /* set up vendor-specific stuff */ type = pci_get_devid(dev); class = pci_get_class(dev); subclass = pci_get_subclass(dev); cmd = pci_read_config(dev, PCIR_COMMAND, 2); if (!(cmd & PCIM_CMD_PORTEN)) { device_printf(dev, "ATA channel disabled by BIOS\n"); return 0; } /* do chipset specific setups only needed once */ if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK) ctlr->channels = 2; else ctlr->channels = 1; ctlr->allocate = ata_pci_allocate; ctlr->dmainit = ata_pci_dmainit; ctlr->locking = ata_pci_locknoop; #ifdef __sparc64__ if (!(cmd & PCIM_CMD_BUSMASTEREN)) { pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2); cmd = pci_read_config(dev, PCIR_COMMAND, 2); } #endif /* if busmastering configured get the I/O resource */ if ((cmd & PCIM_CMD_BUSMASTEREN) == PCIM_CMD_BUSMASTEREN) { int rid = ATA_BMADDR_RID; ctlr->r_io1 = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1, RF_ACTIVE); } ctlr->chipinit(dev); /* attach all channels on this controller */ for (unit = 0; unit < ctlr->channels; unit++) device_add_child(dev, "ata", ATA_MASTERDEV(dev) ? unit : devclass_find_free_unit(ata_devclass, 2)); return bus_generic_attach(dev); } static int ata_pci_print_child(device_t dev, device_t child) { struct ata_channel *ch = device_get_softc(child); int retval = 0; retval += bus_print_child_header(dev, child); retval += printf(": at 0x%lx", rman_get_start(ch->r_io[ATA_IDX_ADDR].res)); if (ATA_MASTERDEV(dev)) retval += printf(" irq %d", 14 + ch->unit); retval += bus_print_child_footer(dev, child); return retval; } static struct resource * ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags) { struct ata_pci_controller *controller = device_get_softc(dev); int unit = ((struct ata_channel *)device_get_softc(child))->unit; struct resource *res = NULL; int myrid; if (type == SYS_RES_IOPORT) { switch (*rid) { case ATA_IOADDR_RID: if (ATA_MASTERDEV(dev)) { myrid = 0; start = (unit ? ATA_SECONDARY : ATA_PRIMARY); end = start + ATA_IOSIZE - 1; count = ATA_IOSIZE; res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, SYS_RES_IOPORT, &myrid, start, end, count, flags); } else { myrid = 0x10 + 8 * unit; res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, SYS_RES_IOPORT, &myrid, start, end, count, flags); } break; case ATA_ALTADDR_RID: if (ATA_MASTERDEV(dev)) { myrid = 0; start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET; end = start + ATA_ALTIOSIZE - 1; count = ATA_ALTIOSIZE; res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, SYS_RES_IOPORT, &myrid, start, end, count, flags); } else { myrid = 0x14 + 8 * unit; res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, SYS_RES_IOPORT, &myrid, start, end, count, flags); if (res) { start = rman_get_start(res) + 2; end = start + ATA_ALTIOSIZE - 1; count = ATA_ALTIOSIZE; BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, SYS_RES_IOPORT, myrid, res); res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, SYS_RES_IOPORT, &myrid, start, end, count, flags); } } break; } return res; } if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) { if (ATA_MASTERDEV(dev)) { #ifdef __alpha__ return alpha_platform_alloc_ide_intr(unit); #else int irq = (unit == 0 ? 14 : 15); return BUS_ALLOC_RESOURCE(device_get_parent(dev), child, SYS_RES_IRQ, rid, irq, irq, 1, flags); #endif } else { return controller->r_irq; } } return 0; } static int ata_pci_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) { int unit = ((struct ata_channel *)device_get_softc(child))->unit; if (type == SYS_RES_IOPORT) { switch (rid) { case ATA_IOADDR_RID: if (ATA_MASTERDEV(dev)) return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, SYS_RES_IOPORT, 0x0, r); else return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, SYS_RES_IOPORT, 0x10 + 8 * unit, r); break; case ATA_ALTADDR_RID: if (ATA_MASTERDEV(dev)) return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, SYS_RES_IOPORT, 0x0, r); else return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, SYS_RES_IOPORT, 0x14 + 8 * unit, r); break; default: return ENOENT; } } if (type == SYS_RES_IRQ) { if (rid != ATA_IRQ_RID) return ENOENT; if (ATA_MASTERDEV(dev)) { #ifdef __alpha__ return alpha_platform_release_ide_intr(unit, r); #else return BUS_RELEASE_RESOURCE(device_get_parent(dev), child, SYS_RES_IRQ, rid, r); #endif } else return 0; } return EINVAL; } static int ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, driver_intr_t *function, void *argument, void **cookiep) { if (ATA_MASTERDEV(dev)) { #ifdef __alpha__ return alpha_platform_setup_ide_intr(child, irq, function, argument, cookiep); #else return BUS_SETUP_INTR(device_get_parent(dev), child, irq, flags, function, argument, cookiep); #endif } else { struct ata_pci_controller *controller = device_get_softc(dev); int unit = ((struct ata_channel *)device_get_softc(child))->unit; controller->interrupt[unit].function = function; controller->interrupt[unit].argument = argument; *cookiep = controller; return 0; } } static int ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq, void *cookie) { if (ATA_MASTERDEV(dev)) { #ifdef __alpha__ return alpha_platform_teardown_ide_intr(child, irq, cookie); #else return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie); #endif } else { struct ata_pci_controller *controller = device_get_softc(dev); int unit = ((struct ata_channel *)device_get_softc(child))->unit; controller->interrupt[unit].function = NULL; controller->interrupt[unit].argument = NULL; return 0; } } static int ata_pci_allocate(device_t dev, struct ata_channel *ch) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct resource *io = NULL, *altio = NULL; int i, rid; rid = ATA_IOADDR_RID; io = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, ATA_IOSIZE, RF_ACTIVE); if (!io) return ENXIO; rid = ATA_ALTADDR_RID; altio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, ATA_ALTIOSIZE, RF_ACTIVE); if (!altio) { bus_release_resource(dev, SYS_RES_IOPORT, ATA_IOADDR_RID, io); return ENXIO; } for (i = ATA_DATA; i <= ATA_STATUS; i ++) { ch->r_io[i].res = io; ch->r_io[i].offset = i; } ch->r_io[ATA_ALTSTAT].res = altio; ch->r_io[ATA_ALTSTAT].offset = 0; ch->r_io[ATA_IDX_ADDR].res = io; if (ctlr->r_io1) { for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) { ch->r_io[i].res = ctlr->r_io1; ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE); } /* if simplex controller, only allow DMA on primary channel */ ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); if (ch->unit > 0 && (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX)) device_printf(dev, "simplex device, DMA on primary only\n"); else ctlr->dmainit(ch); } return 0; } static int -ata_pci_dmastart(struct ata_channel *ch, caddr_t data, int32_t count, int dir) +ata_pci_dmastart(struct ata_channel *ch) { - int error; - - if ((error = ata_dmastart(ch, data, count, dir))) - return error; ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, ch->dma->mdmatab); ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, - (dir ? ATA_BMCMD_WRITE_READ : 0) | ATA_BMCMD_START_STOP); + ((ch->dma->flags & ATA_DMA_READ) ? ATA_BMCMD_WRITE_READ : 0) | + ATA_BMCMD_START_STOP); return 0; } static int ata_pci_dmastop(struct ata_channel *ch) { int error; error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); - ata_dmastop(ch); return error; } static void ata_pci_dmainit(struct ata_channel *ch) { ata_dmainit(ch); if (ch->dma) { ch->dma->start = ata_pci_dmastart; ch->dma->stop = ata_pci_dmastop; } } static void ata_pci_locknoop(struct ata_channel *ch, int flags) { } static device_method_t ata_pci_methods[] = { /* device interface */ DEVMETHOD(device_probe, ata_pci_probe), DEVMETHOD(device_attach, ata_pci_attach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), /* bus methods */ DEVMETHOD(bus_print_child, ata_pci_print_child), DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource), DEVMETHOD(bus_release_resource, ata_pci_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_setup_intr, ata_pci_setup_intr), DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr), { 0, 0 } }; static driver_t ata_pci_driver = { "atapci", ata_pci_methods, sizeof(struct ata_pci_controller), }; static devclass_t ata_pci_devclass; DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0); static int ata_pcisub_probe(device_t dev) { struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); device_t *children; int count, error, i; /* find channel number on this controller */ device_get_children(device_get_parent(dev), &children, &count); for (i = 0; i < count; i++) { if (children[i] == dev) ch->unit = i; } free(children, M_TEMP); if ((error = ctlr->allocate(dev, ch))) return error; ch->device[MASTER].setmode = ctlr->setmode; ch->device[SLAVE].setmode = ctlr->setmode; ch->locking = ctlr->locking; return ata_probe(dev); } static device_method_t ata_pcisub_methods[] = { /* device interface */ DEVMETHOD(device_probe, ata_pcisub_probe), DEVMETHOD(device_attach, ata_attach), DEVMETHOD(device_detach, ata_detach), DEVMETHOD(device_suspend, ata_suspend), DEVMETHOD(device_resume, ata_resume), { 0, 0 } }; static driver_t ata_pcisub_driver = { "ata", ata_pcisub_methods, sizeof(struct ata_channel), }; DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);