Index: head/sys/ia64/ia64/sapic.c =================================================================== --- head/sys/ia64/ia64/sapic.c (revision 104437) +++ head/sys/ia64/ia64/sapic.c (revision 104438) @@ -1,184 +1,184 @@ /*- * Copyright (c) 2001 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include "opt_ddb.h" #include #include #include #include #include #include #include #include static MALLOC_DEFINE(M_SAPIC, "sapic", "I/O SAPIC devices"); struct sapic_rte { u_int64_t rte_vector :8; u_int64_t rte_delivery_mode :3; u_int64_t rte_destination_mode :1; u_int64_t rte_delivery_status :1; u_int64_t rte_polarity :1; u_int64_t rte_rirr :1; u_int64_t rte_trigger_mode :1; u_int64_t rte_mask :1; u_int64_t rte_flushen :1; u_int64_t rte_reserved :30; u_int64_t rte_destination_eid :8; u_int64_t rte_destination_id :8; }; static u_int32_t sapic_read(struct sapic *sa, int which) { vm_offset_t reg = sa->sa_registers; *(volatile u_int32_t *) (reg + SAPIC_IO_SELECT) = which; ia64_mf(); ia64_mf_a(); return *(volatile u_int32_t *) (reg + SAPIC_IO_WINDOW); } static void sapic_write(struct sapic *sa, int which, u_int32_t value) { vm_offset_t reg = sa->sa_registers; *(volatile u_int32_t *) (reg + SAPIC_IO_SELECT) = which; ia64_mf(); ia64_mf_a(); *(volatile u_int32_t *) (reg + SAPIC_IO_WINDOW) = value; ia64_mf(); ia64_mf_a(); } #ifdef DDB static void sapic_read_rte(struct sapic *sa, int which, struct sapic_rte *rte) { u_int32_t *p = (u_int32_t *) rte; register_t c; c = intr_disable(); p[0] = sapic_read(sa, SAPIC_RTE_BASE + 2*which); p[1] = sapic_read(sa, SAPIC_RTE_BASE + 2*which + 1); intr_restore(c); } #endif static void sapic_write_rte(struct sapic *sa, int which, struct sapic_rte *rte) { u_int32_t *p = (u_int32_t *) rte; register_t c; c = intr_disable(); sapic_write(sa, SAPIC_RTE_BASE + 2*which, p[0]); sapic_write(sa, SAPIC_RTE_BASE + 2*which + 1, p[1]); intr_restore(c); } struct sapic * sapic_create(int id, int base, u_int64_t address) { struct sapic *sa; int max; sa = malloc(sizeof(struct sapic), M_SAPIC, M_NOWAIT); if (!sa) return 0; sa->sa_id = id; sa->sa_base = base; sa->sa_registers = IA64_PHYS_TO_RR6(address); max = (sapic_read(sa, SAPIC_VERSION) >> 16) & 0xff; sa->sa_limit = base + max; ia64_add_sapic(sa); return sa; } void sapic_enable(struct sapic *sa, int input, int vector, int trigger_mode, int polarity) { struct sapic_rte rte; u_int64_t lid = ia64_get_lid(); bzero(&rte, sizeof(rte)); rte.rte_destination_id = (lid >> 24) & 255; rte.rte_destination_eid = (lid >> 16) & 255; rte.rte_trigger_mode = trigger_mode; rte.rte_polarity = polarity; - rte.rte_delivery_mode = 0; /* fixed */ + rte.rte_delivery_mode = SAPIC_DELMODE_LOWPRI; rte.rte_vector = vector; sapic_write_rte(sa, input, &rte); } void sapic_eoi(struct sapic *sa, int vector) { vm_offset_t reg = sa->sa_registers; *(volatile u_int32_t *) (reg + SAPIC_APIC_EOI) = vector; ia64_mf(); } #ifdef DDB #include void sapic_print(struct sapic *sa, int input) { struct sapic_rte rte; sapic_read_rte(sa, input, &rte); if (rte.rte_mask == 0) { db_printf("%3d %d %d %s %s %s %s %s ID=%x EID=%x\n", rte.rte_vector, rte.rte_delivery_mode, rte.rte_destination_mode, rte.rte_delivery_status ? "DS" : " ", rte.rte_polarity ? "low-active " : "high-active", rte.rte_rirr ? "RIRR" : " ", rte.rte_trigger_mode ? "level" : "edge ", rte.rte_flushen ? "F" : " ", rte.rte_destination_id, rte.rte_destination_eid); } } #endif Index: head/sys/ia64/include/sapicvar.h =================================================================== --- head/sys/ia64/include/sapicvar.h (revision 104437) +++ head/sys/ia64/include/sapicvar.h (revision 104438) @@ -1,53 +1,60 @@ /*- * Copyright (c) 2001 Doug Rabson * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_SAPICVAR_H_ #define _MACHINE_SAPICVAR_H_ struct sapic { int sa_id; /* I/O SAPIC Id */ int sa_base; /* ACPI vector base */ int sa_limit; /* last ACPI vector handled here */ vm_offset_t sa_registers; /* virtual address of sapic */ }; #define SAPIC_TRIGGER_EDGE 0 #define SAPIC_TRIGGER_LEVEL 1 #define SAPIC_POLARITY_HIGH 0 #define SAPIC_POLARITY_LOW 1 +#define SAPIC_DELMODE_FIXED 0 +#define SAPIC_DELMODE_LOWPRI 1 +#define SAPIC_DELMODE_PMI 2 +#define SAPIC_DELMODE_NMI 4 +#define SAPIC_DELMODE_INIT 5 +#define SAPIC_DELMODE_EXTINT 7 + struct sapic *sapic_create(int id, int base, u_int64_t address); void sapic_enable(struct sapic *sa, int input, int vector, int trigger_mode, int polarity); void sapic_eoi(struct sapic *sa, int vector); #ifdef DDB void sapic_print(struct sapic *sa, int input); #endif #endif /* ! _MACHINE_SAPICVAR_H_ */