Index: head/cad/iverilog/files/patch-bison =================================================================== --- head/cad/iverilog/files/patch-bison (revision 552884) +++ head/cad/iverilog/files/patch-bison (nonexistent) @@ -1,58 +0,0 @@ ---- Makefile.in.orig 2017-08-24 15:22:49 UTC -+++ Makefile.in -@@ -255,6 +255,7 @@ parse.o: parse.cc - # Build this in two steps to avoid parallel build issues (see pr3462585) - parse.cc: $(srcdir)/parse.y - $(YACC) --verbose -t -p VL -d -o $@ $< -+ touch parse.hh - parse.h: parse.cc - mv parse.cc.h $@ 2>/dev/null || mv parse.hh $@ - ---- tgt-pcb/fp.y.orig 2017-08-24 15:22:49 UTC -+++ tgt-pcb/fp.y -@@ -1,5 +1,5 @@ - --%pure-parser -+%define api.pure - %parse-param {const char*file_path} - - %{ ---- tgt-pcb/Makefile.in.orig 2017-08-24 15:22:49 UTC -+++ tgt-pcb/Makefile.in -@@ -89,6 +89,7 @@ fp_lex.cc: $(srcdir)/fp.lex - - fp.cc: $(srcdir)/fp.y - $(YACC) --verbose -t -p fp -d -o $@ $< -+ touch fp.hh - fp.h: fp.cc - mv fp.cc.h $@ 2>/dev/null || mv fp.hh $@ - ---- vhdlpp/Makefile.in.orig 2017-08-24 15:22:49 UTC -+++ vhdlpp/Makefile.in -@@ -118,6 +118,7 @@ lexor.cc: $(srcdir)/lexor.lex - # Build this in two steps to avoid parallel build issues (see pr3462585) - parse.cc: $(srcdir)/parse.y - $(YACC) --verbose -t -d -o $@ $< -+ touch parse.hh - parse.h: parse.cc - mv parse.cc.h $@ 2>/dev/null || mv parse.hh $@ - ---- vhdlpp/parse.y.orig 2017-08-24 15:22:49 UTC -+++ vhdlpp/parse.y -@@ -1,5 +1,5 @@ - --%pure-parser -+%define api.pure - %lex-param { yyscan_t yyscanner } - %parse-param {yyscan_t yyscanner } - %parse-param {const char*file_path} ---- vvp/Makefile.in.orig 2017-08-24 15:22:49 UTC -+++ vvp/Makefile.in -@@ -166,6 +166,7 @@ tables.o: tables.cc - # Build this in two steps to avoid parallel build issues (see pr3462585) - parse.cc: $(srcdir)/parse.y - $(YACC) --verbose -t -d -o $@ $< -+ touch parse.hh - parse.h: parse.cc - mv parse.cc.h $@ 2>/dev/null || mv parse.hh $@ - Property changes on: head/cad/iverilog/files/patch-bison ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/cad/iverilog/files/patch-d49d26a5.c =================================================================== --- head/cad/iverilog/files/patch-d49d26a5.c (revision 552884) +++ head/cad/iverilog/files/patch-d49d26a5.c (nonexistent) @@ -1,37 +0,0 @@ -diff --git a/driver/cflexor.lex b/driver/cflexor.lex -index 5e9e2f506..1bf7cec1d 100644 ---- driver/cflexor.lex -+++ driver/cflexor.lex -@@ -27,6 +27,8 @@ - # include "globals.h" - # include - -+char *current_file = NULL; -+ - static int comment_enter; - static char* trim_trailing_white(char*txt, int trim); - -diff --git a/driver/cfparse_misc.h b/driver/cfparse_misc.h -index 3cb7ddd6e..0323690ce 100644 ---- driver/cfparse_misc.h -+++ driver/cfparse_misc.h -@@ -39,6 +39,6 @@ int cferror(const char *); - int cfparse(void); - void switch_to_command_file(const char *); - void destroy_lexor(void); --char *current_file; -+extern char *current_file; - - #endif /* IVL_cfparse_misc_H */ -diff --git a/libveriuser/priv.h b/libveriuser/priv.h -index 8256e16d3..8d3566087 100644 ---- libveriuser/priv.h -+++ libveriuser/priv.h -@@ -31,6 +31,6 @@ extern char* __acc_newstring(const char*txt); - /* - * Trace file for logging ACC and TF calls. - */ --FILE* pli_trace; -+extern FILE* pli_trace; - - #endif /* IVL_priv_H */ Property changes on: head/cad/iverilog/files/patch-d49d26a5.c ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/cad/iverilog/Makefile =================================================================== --- head/cad/iverilog/Makefile (revision 552884) +++ head/cad/iverilog/Makefile (revision 552885) @@ -1,20 +1,20 @@ # Created by: Ying-Chieh Liao # $FreeBSD$ PORTNAME= iverilog -PORTVERSION= 10.3 +PORTVERSION= 11.0 CATEGORIES= cad -MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v10/ +MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v11/ DISTNAME= verilog-${PORTVERSION} MAINTAINER= zeising@FreeBSD.org COMMENT= Verilog simulation and synthesis tool LICENSE= GPLv2 GNU_CONFIGURE= yes CONFIGURE_ARGS= --disable-suffix USES= bison gmake readline .include Index: head/cad/iverilog/distinfo =================================================================== --- head/cad/iverilog/distinfo (revision 552884) +++ head/cad/iverilog/distinfo (revision 552885) @@ -1,3 +1,3 @@ -TIMESTAMP = 1566058481 -SHA256 (verilog-10.3.tar.gz) = 86bd45e7e12d1bc8772c3cdd394e68a9feccb2a6d14aaf7dae0773b7274368ef -SIZE (verilog-10.3.tar.gz) = 1698889 +TIMESTAMP = 1603302018 +SHA256 (verilog-11.0.tar.gz) = d54785616b63fe6739948e9967499624f29ded54adb57e1e00eb897567a655d5 +SIZE (verilog-11.0.tar.gz) = 1784307 Index: head/cad/iverilog/pkg-plist =================================================================== --- head/cad/iverilog/pkg-plist (revision 552884) +++ head/cad/iverilog/pkg-plist (revision 552885) @@ -1,55 +1,51 @@ bin/iverilog bin/iverilog-vpi bin/vvp include/iverilog/_pli_types.h include/iverilog/acc_user.h include/iverilog/ivl_target.h include/iverilog/sv_vpi_user.h include/iverilog/veriuser.h include/iverilog/vpi_user.h lib/ivl/blif-s.conf lib/ivl/blif.conf lib/ivl/blif.tgt lib/ivl/cadpli.vpl lib/ivl/include/constants.vams lib/ivl/include/disciplines.vams lib/ivl/ivl lib/ivl/ivlpp lib/ivl/null-s.conf lib/ivl/null.conf lib/ivl/null.tgt lib/ivl/pcb-s.conf lib/ivl/pcb.conf lib/ivl/pcb.tgt lib/ivl/sizer-s.conf lib/ivl/sizer.conf lib/ivl/sizer.tgt lib/ivl/stub-s.conf lib/ivl/stub.conf lib/ivl/stub.tgt -lib/ivl/system.sft lib/ivl/system.vpi lib/ivl/vlog95-s.conf lib/ivl/vlog95.conf lib/ivl/vlog95.tgt lib/ivl/vpi_debug.vpi -lib/ivl/v2005_math.sft lib/ivl/v2005_math.vpi -lib/ivl/v2009.sft lib/ivl/v2009.vpi -lib/ivl/va_math.sft lib/ivl/va_math.vpi lib/ivl/vhdl-s.conf -lib/ivl/vhdl_sys.sft lib/ivl/vhdl_sys.vpi +lib/ivl/vhdl_textio.vpi lib/ivl/vhdl.conf lib/ivl/vhdl.tgt lib/ivl/vhdlpp lib/ivl/vvp-s.conf lib/ivl/vvp.conf lib/ivl/vvp.tgt lib/libveriuser.a lib/libvpi.a man/man1/iverilog.1.gz man/man1/iverilog-vpi.1.gz man/man1/vvp.1.gz