Index: head/cad/Makefile =================================================================== --- head/cad/Makefile (revision 528957) +++ head/cad/Makefile (revision 528958) @@ -1,119 +1,120 @@ # $FreeBSD$ # COMMENT = CAD tools SUBDIR += NASTRAN-95 SUBDIR += PrusaSlicer SUBDIR += abc SUBDIR += admesh SUBDIR += adms SUBDIR += alliance SUBDIR += astk-client SUBDIR += astk-serveur SUBDIR += atlc SUBDIR += basicdsp SUBDIR += brlcad SUBDIR += calculix SUBDIR += calculix-ccx SUBDIR += caneda SUBDIR += cascade SUBDIR += cascade-compiler SUBDIR += chipvault SUBDIR += cura-engine SUBDIR += digital SUBDIR += dinotrace SUBDIR += electric SUBDIR += electric-ng SUBDIR += fasm SUBDIR += feappv SUBDIR += fidocadj SUBDIR += freecad SUBDIR += freehdl SUBDIR += fritzing SUBDIR += gdsreader SUBDIR += gdt SUBDIR += geda SUBDIR += gerbv SUBDIR += ghdl SUBDIR += gmsh SUBDIR += gnucap SUBDIR += gplcver SUBDIR += graywolf SUBDIR += gspiceui SUBDIR += gtkwave SUBDIR += impact SUBDIR += irsim SUBDIR += iverilog SUBDIR += jspice3 SUBDIR += k40-whisperer SUBDIR += kicad SUBDIR += kicad-devel SUBDIR += kicad-doc SUBDIR += kicad-library-footprints SUBDIR += kicad-library-footprints-devel SUBDIR += kicad-library-packages3d SUBDIR += kicad-library-packages3d-devel SUBDIR += kicad-library-symbols SUBDIR += kicad-library-symbols-devel SUBDIR += kicad-library-templates SUBDIR += kicad-library-templates-devel SUBDIR += klayout SUBDIR += ktechlab SUBDIR += ldraw SUBDIR += leocad SUBDIR += lepton-eda SUBDIR += libopencad SUBDIR += librecad SUBDIR += libredwg SUBDIR += librepcb SUBDIR += linux-eagle5 SUBDIR += logisim SUBDIR += magic SUBDIR += meshdev SUBDIR += netgen SUBDIR += netgen-lvs SUBDIR += ngspice_rework SUBDIR += nvc SUBDIR += opencascade SUBDIR += openctm SUBDIR += openscad SUBDIR += openscad-devel + SUBDIR += opensta SUBDIR += openvsp SUBDIR += oregano SUBDIR += p5-GDS2 SUBDIR += p5-Verilog-Perl SUBDIR += pcb SUBDIR += pdnmesh SUBDIR += py-gdspy SUBDIR += py-lcapy SUBDIR += py-phidl SUBDIR += py-pyfda SUBDIR += python-gdsii SUBDIR += qcad SUBDIR += qelectrotech SUBDIR += qflow SUBDIR += qmls SUBDIR += qrouter SUBDIR += repsnapper SUBDIR += rubygem-gdsii SUBDIR += scotch SUBDIR += solvespace SUBDIR += sp2sp SUBDIR += spice SUBDIR += stepcode SUBDIR += sumo SUBDIR += sweethome3d SUBDIR += tkgate SUBDIR += tochnog SUBDIR += transcalc SUBDIR += varkon SUBDIR += verilator SUBDIR += verilog-mode.el SUBDIR += veroroute SUBDIR += xcircuit SUBDIR += yosys SUBDIR += z88 SUBDIR += zcad .include Index: head/cad/opensta/Makefile =================================================================== --- head/cad/opensta/Makefile (nonexistent) +++ head/cad/opensta/Makefile (revision 528958) @@ -0,0 +1,29 @@ +# $FreeBSD$ + +PORTNAME= opensta +DISTVERSION= g20200315 +CATEGORIES= cad + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Gate level static timing verifier + +LICENSE= GPLv3 +LICENSE_FILE= ${WRKSRC}/LICENSE + +BUILD_DEPENDS= swig3.0:devel/swig30 +LIB_DEPENDS= libcudd.so:math/cudd + +USES= bison compiler:c++11-lang cmake tcl +USE_GITHUB= yes +GH_ACCOUNT= The-OpenROAD-Project +GH_PROJECT= OpenSTA +GH_TAGNAME= 057481441231748ce8a1c96092c5a6174f7581d8 +USE_LDCONFIG= yes + +CMAKE_ARGS= -DFREEBSD_TCL_VER=${TCL_VER:S/.//} -DFREEBSD_TCL_INCLUDEDIR=${TCL_INCLUDEDIR} -DCUDD=${LOCALBASE} + +LDFLAGS+= -pthread + +BINARY_ALIAS= tclsh=${TCLSH} + +.include Property changes on: head/cad/opensta/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/opensta/distinfo =================================================================== --- head/cad/opensta/distinfo (nonexistent) +++ head/cad/opensta/distinfo (revision 528958) @@ -0,0 +1,3 @@ +TIMESTAMP = 1584937080 +SHA256 (The-OpenROAD-Project-OpenSTA-g20200315-057481441231748ce8a1c96092c5a6174f7581d8_GH0.tar.gz) = faa86a3d61d2fcc132cc5b02acd6de2b25cce6e3be3647aa92c26f97a572239c +SIZE (The-OpenROAD-Project-OpenSTA-g20200315-057481441231748ce8a1c96092c5a6174f7581d8_GH0.tar.gz) = 4859287 Property changes on: head/cad/opensta/distinfo ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/opensta/files/patch-CMakeLists.txt =================================================================== --- head/cad/opensta/files/patch-CMakeLists.txt (nonexistent) +++ head/cad/opensta/files/patch-CMakeLists.txt (revision 528958) @@ -0,0 +1,11 @@ +--- CMakeLists.txt.orig 2020-03-16 14:40:15 UTC ++++ CMakeLists.txt +@@ -627,7 +627,7 @@ set(STA_INCLUDE_DIRS + # compatibility with configure + set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${STA_HOME}/app) + +-add_library(OpenSTA ++add_library(OpenSTA SHARED + ${STA_SOURCE} + + ${STA_TCL_INIT} Property changes on: head/cad/opensta/files/patch-CMakeLists.txt ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/opensta/files/patch-cmake_FindTCL.cmake =================================================================== --- head/cad/opensta/files/patch-cmake_FindTCL.cmake (nonexistent) +++ head/cad/opensta/files/patch-cmake_FindTCL.cmake (revision 528958) @@ -0,0 +1,20 @@ +--- cmake/FindTCL.cmake.orig 2020-03-16 14:40:15 UTC ++++ cmake/FindTCL.cmake +@@ -22,7 +22,7 @@ + # because there doesn't appear to be a way to override + # searching OSX system directories before unix directories. + +-set(TCL_POSSIBLE_NAMES tcl87 tcl8.7 ++set(TCL_POSSIBLE_NAMES tcl${FREEBSD_TCL_VER} tcl87 tcl8.7 + tcl86 tcl8.6 + tcl85 tcl8.5 + tcl84 tcl8.4 +@@ -67,7 +67,7 @@ get_filename_component(TCL_LIB_PARENT2 "${TCL_LIB_PARE + # Locate tcl.h + if (NOT TCL_HEADER) + find_file(TCL_HEADER tcl.h +- PATHS ${TCL_LIB_PARENT1} ${TCL_LIB_PARENT2} ++ PATHS ${FREEBSD_TCL_INCLUDEDIR} ${TCL_LIB_PARENT1} ${TCL_LIB_PARENT2} + PATH_SUFFIXES include include/tcl + NO_DEFAULT_PATH + ) Property changes on: head/cad/opensta/files/patch-cmake_FindTCL.cmake ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/opensta/pkg-descr =================================================================== --- head/cad/opensta/pkg-descr (nonexistent) +++ head/cad/opensta/pkg-descr (revision 528958) @@ -0,0 +1,13 @@ +OpenSTA is a gate level static timing verifier. As a stand-alone executable it +can be used to verify the timing of a design using standard file formats. + +* Verilog netlist +* Liberty library +* SDC timing constraints +* SDF delay annotation +* SPEF parasitics + +OpenSTA uses a TCL command interpreter to read the design, specify timing +constraints and print timing reports. + +WWW: https://github.com/The-OpenROAD-Project/OpenSTA Property changes on: head/cad/opensta/pkg-descr ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/opensta/pkg-plist =================================================================== --- head/cad/opensta/pkg-plist (nonexistent) +++ head/cad/opensta/pkg-plist (revision 528958) @@ -0,0 +1,166 @@ +bin/sta +include/ArcDelayCalc.hh +include/Arnoldi.hh +include/ArnoldiDelayCalc.hh +include/ArnoldiReduce.hh +include/Bfs.hh +include/CheckMaxSkews.hh +include/CheckMinPeriods.hh +include/CheckMinPulseWidths.hh +include/CheckSlewLimits.hh +include/CheckTiming.hh +include/ClkInfo.hh +include/ClkSkew.hh +include/Clock.hh +include/ClockGatingCheck.hh +include/ClockGroups.hh +include/ClockInsertion.hh +include/ClockLatency.hh +include/ConcreteLibrary.hh +include/ConcreteNetwork.hh +include/ConcreteParasitics.hh +include/ConcreteParasiticsPvt.hh +include/Corner.hh +include/Crpr.hh +include/CycleAccting.hh +include/DataCheck.hh +include/DcalcAnalysisPt.hh +include/Debug.hh +include/Delay.hh +include/DelayCalc.hh +include/DelayFloat.hh +include/DelayNormal1.hh +include/DelayNormal2.hh +include/DeratingFactors.hh +include/DisabledPorts.hh +include/DisallowCopyAssign.hh +include/DispatchQueue.hh +include/DmpCeff.hh +include/DmpDelayCalc.hh +include/EnumNameMap.hh +include/EquivCells.hh +include/Error.hh +include/EstimateParasitics.hh +include/ExceptionPath.hh +include/FindRegister.hh +include/FuncExpr.hh +include/Fuzzy.hh +include/GatedClk.hh +include/Genclks.hh +include/Graph.hh +include/GraphClass.hh +include/GraphCmp.hh +include/GraphDelayCalc.hh +include/GraphDelayCalc1.hh +include/Hash.hh +include/HashSet.hh +include/HpinDrvrLoad.hh +include/InputDrive.hh +include/InternalPower.hh +include/Iterator.hh +include/Latches.hh +include/LeakagePower.hh +include/Levelize.hh +include/Liberty.hh +include/LibertyBuilder.hh +include/LibertyClass.hh +include/LibertyExpr.hh +include/LibertyParser.hh +include/LibertyReader.hh +include/LibertyReaderPvt.hh +include/LinearModel.hh +include/LumpedCapDelayCalc.hh +include/Machine.hh +include/MakeConcreteNetwork.hh +include/MakeConcreteParasitics.hh +include/Map.hh +include/MinMax.hh +include/MinMaxValues.hh +include/Mutex.hh +include/NetCaps.hh +include/Network.hh +include/NetworkClass.hh +include/NetworkCmp.hh +include/NullParasitics.hh +include/ObjectId.hh +include/ObjectTable.hh +include/Parasitics.hh +include/ParasiticsClass.hh +include/ParseBus.hh +include/Path.hh +include/PathAnalysisPt.hh +include/PathEnd.hh +include/PathEnum.hh +include/PathEnumed.hh +include/PathExpanded.hh +include/PathGroup.hh +include/PathRef.hh +include/PathVertex.hh +include/PathVertexRep.hh +include/PatternMatch.hh +include/PinPair.hh +include/PortDelay.hh +include/PortDirection.hh +include/PortExtCap.hh +include/Power.hh +include/Property.hh +include/RCDelayCalc.hh +include/ReduceParasitics.hh +include/Report.hh +include/ReportAnnotation.hh +include/ReportPath.hh +include/ReportStd.hh +include/ReportTcl.hh +include/RiseFallMinMax.hh +include/RiseFallValues.hh +include/Sdc.hh +include/SdcClass.hh +include/SdcCmdComment.hh +include/SdcNetwork.hh +include/Sdf.hh +include/SdfReader.hh +include/SdfWriter.hh +include/Search.hh +include/SearchClass.hh +include/SearchPred.hh +include/Sequential.hh +include/Set.hh +include/Sim.hh +include/SimpleRCDelayCalc.hh +include/SpefNamespace.hh +include/SpefReader.hh +include/Sta.hh +include/StaConfig.hh +include/StaMain.hh +include/StaState.hh +include/Stats.hh +include/StringSeq.hh +include/StringSet.hh +include/StringUtil.hh +include/TableModel.hh +include/Tag.hh +include/TagGroup.hh +include/TimingArc.hh +include/TimingModel.hh +include/TimingRole.hh +include/TokenParser.hh +include/Transition.hh +include/UnitDelayCalc.hh +include/Units.hh +include/UnorderedMap.hh +include/UnorderedSet.hh +include/Vector.hh +include/VerilogNamespace.hh +include/VerilogReader.hh +include/VerilogReaderPvt.hh +include/VerilogWriter.hh +include/VertexVisitor.hh +include/VisitPathEnds.hh +include/VisitPathGroupVertices.hh +include/Wireload.hh +include/WorstSlack.hh +include/WritePathSpice.hh +include/WriteSdc.hh +include/WriteSdcPvt.hh +include/Zlib.hh +lib/libOpenSTA.so Property changes on: head/cad/opensta/pkg-plist ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property