Index: head/cad/Makefile =================================================================== --- head/cad/Makefile (revision 528681) +++ head/cad/Makefile (revision 528682) @@ -1,115 +1,116 @@ # $FreeBSD$ # COMMENT = CAD tools SUBDIR += NASTRAN-95 SUBDIR += PrusaSlicer SUBDIR += abc SUBDIR += admesh SUBDIR += adms SUBDIR += alliance SUBDIR += astk-client SUBDIR += astk-serveur SUBDIR += atlc SUBDIR += basicdsp SUBDIR += brlcad SUBDIR += calculix SUBDIR += calculix-ccx SUBDIR += caneda SUBDIR += cascade SUBDIR += cascade-compiler SUBDIR += chipvault SUBDIR += cura-engine SUBDIR += digital SUBDIR += dinotrace SUBDIR += electric SUBDIR += electric-ng SUBDIR += fasm SUBDIR += feappv SUBDIR += fidocadj SUBDIR += freecad SUBDIR += freehdl SUBDIR += fritzing SUBDIR += gdsreader SUBDIR += gdt SUBDIR += geda SUBDIR += gerbv SUBDIR += ghdl SUBDIR += gmsh SUBDIR += gnucap SUBDIR += gplcver SUBDIR += gspiceui SUBDIR += gtkwave SUBDIR += impact SUBDIR += irsim SUBDIR += iverilog SUBDIR += jspice3 SUBDIR += k40-whisperer SUBDIR += kicad SUBDIR += kicad-devel SUBDIR += kicad-doc SUBDIR += kicad-library-footprints SUBDIR += kicad-library-footprints-devel SUBDIR += kicad-library-packages3d SUBDIR += kicad-library-packages3d-devel SUBDIR += kicad-library-symbols SUBDIR += kicad-library-symbols-devel SUBDIR += kicad-library-templates SUBDIR += kicad-library-templates-devel SUBDIR += klayout SUBDIR += ktechlab SUBDIR += ldraw SUBDIR += leocad SUBDIR += lepton-eda SUBDIR += libopencad SUBDIR += librecad SUBDIR += libredwg SUBDIR += librepcb SUBDIR += linux-eagle5 SUBDIR += logisim SUBDIR += magic SUBDIR += meshdev SUBDIR += netgen + SUBDIR += netgen-lvs SUBDIR += ngspice_rework SUBDIR += nvc SUBDIR += opencascade SUBDIR += openctm SUBDIR += openscad SUBDIR += openscad-devel SUBDIR += openvsp SUBDIR += oregano SUBDIR += p5-GDS2 SUBDIR += p5-Verilog-Perl SUBDIR += pcb SUBDIR += pdnmesh SUBDIR += py-gdspy SUBDIR += py-lcapy SUBDIR += py-phidl SUBDIR += py-pyfda SUBDIR += python-gdsii SUBDIR += qcad SUBDIR += qelectrotech SUBDIR += qmls SUBDIR += repsnapper SUBDIR += rubygem-gdsii SUBDIR += scotch SUBDIR += solvespace SUBDIR += sp2sp SUBDIR += spice SUBDIR += stepcode SUBDIR += sumo SUBDIR += sweethome3d SUBDIR += tkgate SUBDIR += tochnog SUBDIR += transcalc SUBDIR += varkon SUBDIR += verilator SUBDIR += verilog-mode.el SUBDIR += veroroute SUBDIR += xcircuit SUBDIR += yosys SUBDIR += z88 SUBDIR += zcad .include Index: head/cad/netgen-lvs/Makefile =================================================================== --- head/cad/netgen-lvs/Makefile (nonexistent) +++ head/cad/netgen-lvs/Makefile (revision 528682) @@ -0,0 +1,25 @@ +# $FreeBSD$ + +PORTNAME= netgen +DISTVERSION= 1.5.144 +CATEGORIES= cad +MASTER_SITES= http://opencircuitdesign.com/netgen/archive/ +PKGNAMESUFFIX= -lvs + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Tool for comparing netlists (a process known as LVS) + +LICENSE= GPLv1 +LICENSE_FILE= ${WRKSRC}/Copying + +USES= gmake python tar:tgz + +GNU_CONFIGURE= yes + +post-patch: + @${REINPLACE_CMD} -e 's|^#!/bin/env python3$$|#!${PYTHON_CMD}|' ${WRKSRC}/python/*.py + +post-stage: + @${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/* + +.include Property changes on: head/cad/netgen-lvs/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/netgen-lvs/distinfo =================================================================== --- head/cad/netgen-lvs/distinfo (nonexistent) +++ head/cad/netgen-lvs/distinfo (revision 528682) @@ -0,0 +1,3 @@ +TIMESTAMP = 1584583774 +SHA256 (netgen-1.5.144.tgz) = 209b801d8c8051f60cf0845e564a5b200791b6a955d96f64d1b4d959133d9aa9 +SIZE (netgen-1.5.144.tgz) = 522869 Property changes on: head/cad/netgen-lvs/distinfo ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/netgen-lvs/files/patch-python_Makefile =================================================================== --- head/cad/netgen-lvs/files/patch-python_Makefile (nonexistent) +++ head/cad/netgen-lvs/files/patch-python_Makefile (revision 528682) @@ -0,0 +1,12 @@ +--- python/Makefile.orig 2020-02-24 21:24:48 UTC ++++ python/Makefile +@@ -46,6 +46,9 @@ $(DESTDIR)${INSTALL_PYDIR}/lvs_help.txt: lvs_help.txt + + install: install-tcl + ++$(DESTDIR)${INSTALL_PYDIR}: ++ mkdir -p $(DESTDIR)${INSTALL_PYDIR} ++ + install-tcl: $(DESTDIR)${INSTALL_PYDIR} $(DESTDIR)${INSTALL_PYDIR}/consoletext.py \ + $(DESTDIR)${INSTALL_PYDIR}/helpwindow.py $(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py \ + $(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py $(DESTDIR)${INSTALL_PYDIR}/tksimpledialog.py \ Property changes on: head/cad/netgen-lvs/files/patch-python_Makefile ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/netgen-lvs/pkg-descr =================================================================== --- head/cad/netgen-lvs/pkg-descr (nonexistent) +++ head/cad/netgen-lvs/pkg-descr (revision 528682) @@ -0,0 +1,12 @@ +Netgen is a tool for comparing netlists, a process known as LVS, which stands +for "Layout vs. Schematic". This is an important step in the integrated circuit +design flow, ensuring that the geometry that has been laid out matches the +expected circuit. Very small circuits can bypass this step by confirming circuit +operation through extraction and simulation. Very large digital circuits are +usually generated by tools from high-level descriptions, using compilers that +ensure the correct layout geometry. The greatest need for LVS is in large analog +or mixed-signal circuits that cannot be simulated in reasonable time. Even for +small circuits, LVS can be done much faster than simulation, and provides +feedback that makes it easier to find an error than does a simulation. + +WWW: http://opencircuitdesign.com/netgen/ Property changes on: head/cad/netgen-lvs/pkg-descr ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/netgen-lvs/pkg-plist =================================================================== --- head/cad/netgen-lvs/pkg-plist (nonexistent) +++ head/cad/netgen-lvs/pkg-plist (revision 528682) @@ -0,0 +1,17 @@ +bin/inetcomp +bin/netcomp +bin/netgen +bin/ntk2adl +bin/ntk2xnf +lib/netgen/doc/netgen.doc +lib/netgen/ntk2adl.sh +lib/netgen/python/consoletext.py +lib/netgen/python/helpwindow.py +lib/netgen/python/lvs_help.txt +lib/netgen/python/lvs_manager.py +lib/netgen/python/tksimpledialog.py +lib/netgen/python/tooltip.py +lib/netgen/python/treeviewsplit.py +lib/netgen/spice +lib/netgen/spice.bot +lib/netgen/spice.top Property changes on: head/cad/netgen-lvs/pkg-plist ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property