Index: head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_boringssl_src_crypto_cpu-aarch64-linux.c =================================================================== --- head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_boringssl_src_crypto_cpu-aarch64-linux.c (revision 527874) +++ head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_boringssl_src_crypto_cpu-aarch64-linux.c (revision 527875) @@ -1,63 +1,75 @@ ---- src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig 2019-05-23 12:39:34 UTC +--- src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig 2019-10-21 10:14:54 UTC +++ src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c -@@ -14,49 +14,35 @@ +@@ -14,49 +14,47 @@ #include -#if defined(OPENSSL_AARCH64) && defined(OPENSSL_LINUX) && \ - !defined(OPENSSL_STATIC_ARMCAP) +#if defined(OPENSSL_AARCH64) -#include - #include #include "internal.h" - extern uint32_t OPENSSL_armcap_P; -+#include -+#include -+ - void OPENSSL_cpuid_setup(void) { +-void OPENSSL_cpuid_setup(void) { - unsigned long hwcap = getauxval(AT_HWCAP); -+ uint64_t id_aa64isar0; ++#include - // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of - // these values. - static const unsigned long kNEON = 1 << 1; - static const unsigned long kAES = 1 << 3; - static const unsigned long kPMULL = 1 << 4; - static const unsigned long kSHA1 = 1 << 5; - static const unsigned long kSHA256 = 1 << 6; -+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1); ++#ifndef ID_AA64ISAR0_AES_VAL ++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES ++#endif ++#ifndef ID_AA64ISAR0_AES_VAL ++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES ++#endif ++#ifndef ID_AA64ISAR0_SHA1_VAL ++#define ID_AA64ISAR0_SHA1_VAL ID_AA64ISAR0_SHA1 ++#endif ++#ifndef ID_AA64ISAR0_SHA2_VAL ++#define ID_AA64ISAR0_SHA2_VAL ID_AA64ISAR0_SHA2 ++#endif - if ((hwcap & kNEON) == 0) { - // Matching OpenSSL, if NEON is missing, don't report other features - // either. - return; - } -- ++void OPENSSL_cpuid_setup(void) { ++ uint64_t id_aa64isar0; + ++ id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1); ++ OPENSSL_armcap_P |= ARMV7_NEON; - if (hwcap & kAES) { -+ if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_BASE) { ++ if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) { OPENSSL_armcap_P |= ARMV8_AES; } - if (hwcap & kPMULL) { -+ if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) { ++ if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) { OPENSSL_armcap_P |= ARMV8_PMULL; } - if (hwcap & kSHA1) { -+ if (ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) { ++ if (ID_AA64ISAR0_SHA1_VAL(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) { OPENSSL_armcap_P |= ARMV8_SHA1; } - if (hwcap & kSHA256) { -+ if(ID_AA64ISAR0_SHA2(id_aa64isar0) == ID_AA64ISAR0_SHA2_BASE) { ++ if(ID_AA64ISAR0_SHA2_VAL(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) { OPENSSL_armcap_P |= ARMV8_SHA256; } } - -#endif // OPENSSL_AARCH64 && !OPENSSL_STATIC_ARMCAP +#endif // OPENSSL_AARCH64 Index: head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h =================================================================== --- head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h (revision 527874) +++ head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h (revision 527875) @@ -1,35 +1,40 @@ ---- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig 2019-05-23 12:39:34 UTC +--- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig 2019-10-21 10:14:54 UTC +++ src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h -@@ -16,6 +16,24 @@ +@@ -16,6 +16,29 @@ #if HAVE_ARM64_CRC32C +#if defined(__FreeBSD__) +#include -+#include ++#ifndef ID_AA64ISAR0_AES_VAL ++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES ++#endif ++#ifndef ID_AA64ISAR0_CRC32_VAL ++#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32 ++#endif +namespace crc32c { + +inline bool CanUseArm64Linux() { + uint64_t id_aa64isar0; + -+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1); -+ if ((ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \ -+ (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)) ++ id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1); ++ if ((ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \ ++ (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)) + return true; + return false; +} + +} // namespace crc32c + +#elif defined(__linux__) #if HAVE_STRONG_GETAUXVAL #include #elif HAVE_WEAK_GETAUXVAL -@@ -43,6 +61,7 @@ inline bool CanUseArm64Linux() { +@@ -43,6 +66,7 @@ inline bool CanUseArm64Linux() { } // namespace crc32c +#endif #endif // HAVE_ARM64_CRC32C #endif // CRC32C_CRC32C_ARM_LINUX_CHECK_H_ Index: head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp =================================================================== --- head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp (revision 527874) +++ head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp (revision 527875) @@ -1,36 +1,39 @@ ---- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp.orig 2019-05-23 12:39:34 UTC +--- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp 2019-10-21 10:14:54 UTC +++ src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp -@@ -70,6 +70,20 @@ +@@ -70,6 +70,23 @@ return features; } +#elif defined(SK_CPU_ARM64) && defined(__FreeBSD__) + #include ++ #ifndef ID_AA64ISAR0_CRC32_VAL ++ #define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32 ++ #endif + + static uint32_t read_cpu_features() { + uint32_t features = 0; + uint64_t id_aa64isar0; + -+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1); -+ if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) { ++ id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1); ++ if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) { + features |= SkCpu::CRC32; + } + return features; + } + #elif defined(SK_CPU_ARM64) && __has_include() #include -@@ -95,7 +109,12 @@ - const uint32_t kHWCAP_VFPv4 = (1<<16); +@@ -78,7 +95,12 @@ + kHWCAP_ASIMDHP = (1<<10); uint32_t features = 0; +#if defined(__FreeBSD__) + uint32_t hwcaps = 0; + elf_aux_info(AT_HWCAP, &hwcaps, sizeof(hwcaps)); +#else uint32_t hwcaps = getauxval(AT_HWCAP); +#endif - if (hwcaps & kHWCAP_NEON ) { - features |= SkCpu::NEON; - if (hwcaps & kHWCAP_VFPv4) { features |= SkCpu::NEON_FMA|SkCpu::VFP_FP16; } + if (hwcaps & kHWCAP_CRC32 ) { features |= SkCpu::CRC32; } + if (hwcaps & kHWCAP_ASIMDHP) { features |= SkCpu::ASIMDHP; } + return features; Index: head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c =================================================================== --- head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c (revision 527874) +++ head/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c (revision 527875) @@ -1,97 +1,102 @@ ---- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig 2019-05-23 12:39:34 UTC +--- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig 2019-10-21 10:14:54 UTC +++ src/3rdparty/chromium/third_party/zlib/arm_features.c -@@ -8,83 +8,30 @@ +@@ -8,83 +8,36 @@ #include "zutil.h" -int ZLIB_INTERNAL arm_cpu_enable_crc32 = 0; -int ZLIB_INTERNAL arm_cpu_enable_pmull = 0; - -#if !defined(_MSC_VER) #include #include +#include +#include -#if defined(ARMV8_OS_ANDROID) -#include -#elif defined(ARMV8_OS_LINUX) -#include -#include -#else -#error ### No ARM CPU features detection in your platform/OS -#endif +int ZLIB_INTERNAL arm_cpu_enable_crc32 = 0; +int ZLIB_INTERNAL arm_cpu_enable_pmull = 0; static pthread_once_t cpu_check_inited_once = PTHREAD_ONCE_INIT; static void init_arm_features(void) { - uint64_t flag_crc32 = 0, flag_pmull = 0, capabilities = 0; -+#if defined (__aarch64__) -+ uint64_t id_aa64isar0; - +- -#if defined(ARMV8_OS_ANDROID) - flag_crc32 = ANDROID_CPU_ARM_FEATURE_CRC32; - flag_pmull = ANDROID_CPU_ARM_FEATURE_PMULL; - capabilities = android_getCpuFeatures(); -#elif defined(ARMV8_OS_LINUX) - #if defined(__aarch64__) - flag_crc32 = HWCAP_CRC32; - flag_pmull = HWCAP_PMULL; - capabilities = getauxval(AT_HWCAP); - #elif defined(__ARM_NEON) || defined(__ARM_NEON__) - /* The use of HWCAP2 is for getting features of newer ARMv8-A SoCs - * while running in 32bits mode (i.e. aarch32). - */ - flag_crc32 = HWCAP2_CRC32; - flag_pmull = HWCAP2_PMULL; - capabilities = getauxval(AT_HWCAP2); - #endif --#endif -- ++#if defined (__aarch64__) ++#ifndef ID_AA64ISAR0_AES_VAL ++#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES + #endif ++#ifndef ID_AA64ISAR0_CRC32_VAL ++#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32 ++#endif ++ uint64_t id_aa64isar0; + - if (capabilities & flag_crc32) - arm_cpu_enable_crc32 = 1; - - if (capabilities & flag_pmull) -+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1); -+ if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) ++ id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1); ++ if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) arm_cpu_enable_pmull = 1; -+ if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) ++ if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) + arm_cpu_enable_crc32 = 1; +#endif } void ZLIB_INTERNAL arm_check_features(void) { pthread_once(&cpu_check_inited_once, init_arm_features); } -#else -#include - -static BOOL CALLBACK _arm_check_features(PINIT_ONCE once, - PVOID param, - PVOID *context); -static INIT_ONCE cpu_check_inited_once = INIT_ONCE_STATIC_INIT; - - -void ZLIB_INTERNAL arm_check_features(void) -{ - InitOnceExecuteOnce(&cpu_check_inited_once, _arm_check_features, - NULL, NULL); -} - -static BOOL CALLBACK _arm_check_features(PINIT_ONCE once, - PVOID param, - PVOID *context) -{ - if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) - arm_cpu_enable_crc32 = 1; - - if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) - arm_cpu_enable_pmull = 1; - - return TRUE; -} -#endif /* _MSC_VER */