Index: head/cad/p5-Verilog-Perl/Makefile
===================================================================
--- head/cad/p5-Verilog-Perl/Makefile	(revision 526257)
+++ head/cad/p5-Verilog-Perl/Makefile	(revision 526258)
@@ -1,27 +1,29 @@
 # Created by: Otacilio de Araujo Ramos Neto <otacilio.neto@bsd.com.br>
 # $FreeBSD$
 
 PORTNAME=	Verilog-Perl
 PORTVERSION=	3.418
 CATEGORIES=	cad perl5
 MASTER_SITES=	CPAN
 PKGNAMEPREFIX=	p5-
 
 MAINTAINER=	otacilio.neto@bsd.com.br
 COMMENT=	Building point for Verilog support in the Perl language
 
-LICENSE=	LGPL3
+LICENSE=	ART20 LGPL3
+LICENSE_COMB=	dual
+LICENSE_FILE_ART20=	${WRKSRC}/COPYING
 
 BUILD_DEPENDS=	flex>=2.5.35:textproc/flex
 
 USES=		bison gmake perl5
 USE_PERL5=	configure
 CONFIGURE_ENV=	CXX=${CXX}\
 		CPP=${CPP}\
 		CC=${CC}
 
 post-install:
-	${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so
-	${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Preproc/*.so
+	@${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so
+	@${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Preproc/*.so
 
 .include <bsd.port.mk>
Index: head/cad/p5-Verilog-Perl/pkg-descr
===================================================================
--- head/cad/p5-Verilog-Perl/pkg-descr	(revision 526257)
+++ head/cad/p5-Verilog-Perl/pkg-descr	(revision 526258)
@@ -1,19 +1,19 @@
 The Verilog-Perl library is a building point for Verilog support in the Perl
 language. It includes:
 * Verilog::Getopt which parses command line options similar to C++ and VCS.
 * Verilog::Language which knows the language keywords and parses numbers.
 * Verilog::Netlist which builds netlists out of Verilog files. This allows
   easy scripts to determine things such as the hierarchy of modules.
 * Verilog::Parser invokes callbacks for language tokens.
 * Verilog::Preproc preprocesses the language, and allows reading
   post-processed files right from Perl without temporary files.
 * vpassert inserts PLIish warnings and assertions for any simulator.
 * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
 * vrename renames and cross-references Verilog symbols. Vrename creates Verilog
   cross references and makes it easy to rename signal and module names across
   multiple files. Vrename uses a simple and efficient three step process.
   First, you run vrename to create a list of signals in the design. You then
   edit this list, changing as many symbols as you wish. Vrename is then run a
   second time to apply the changes.
 
-WWW: http://www.veripool.org/wiki/verilog-perl
+WWW: https://www.veripool.org/wiki/verilog-perl