Index: head/cad/verilator/Makefile
===================================================================
--- head/cad/verilator/Makefile	(revision 525898)
+++ head/cad/verilator/Makefile	(revision 525899)
@@ -1,29 +1,29 @@
 # $FreeBSD$
 
 PORTNAME=	verilator
-DISTVERSION=	4.024
+DISTVERSION=	4.028
 CATEGORIES=	cad
 MASTER_SITES=	https://www.veripool.org/ftp/
 
 MAINTAINER=	kevinz5000@gmail.com
 COMMENT=	Synthesizable Verilog to C++ compiler
 
 LICENSE=	GPLv3
 LICENSE_FILE=	${WRKSRC}/LICENSE
 
 USES=		bison compiler:c++14-lang gmake pathfix perl5 tar:tgz
 
 GNU_CONFIGURE=	yes
 CONFIGURE_ENV=	INSTALL_PROGRAM="${INSTALL_SCRIPT}"
 
 post-patch:
 	${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \
 	    ${WRKSRC}/Makefile.in
 
 post-build:
 	@${STRIP_CMD} ${WRKSRC}/bin/verilator_bin
 
 post-install:
 	@${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg
 
 .include <bsd.port.mk>
Index: head/cad/verilator/distinfo
===================================================================
--- head/cad/verilator/distinfo	(revision 525898)
+++ head/cad/verilator/distinfo	(revision 525899)
@@ -1,3 +1,3 @@
-TIMESTAMP = 1578206387
-SHA256 (verilator-4.024.tgz) = dab91beaa85293564cf0a931f847f7a6cd4ff30b0c11edd1957a9ab1db57b25a
-SIZE (verilator-4.024.tgz) = 2377845
+TIMESTAMP = 1581485426
+SHA256 (verilator-4.028.tgz) = 344c859b105eb4d382ab89fbc515fd3bf915dc17bf75f90e918141afac1489e6
+SIZE (verilator-4.028.tgz) = 2448209