Index: head/cad/iverilog/Makefile
===================================================================
--- head/cad/iverilog/Makefile	(revision 509185)
+++ head/cad/iverilog/Makefile	(revision 509186)
@@ -1,21 +1,20 @@
 # Created by: Ying-Chieh Liao <ijliao@FreeBSD.org>
 # $FreeBSD$
 
 PORTNAME=	iverilog
-PORTVERSION=	10.2
-PORTREVISION=	1
+PORTVERSION=	10.3
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v10/
 DISTNAME=	verilog-${PORTVERSION}
 
 MAINTAINER=	zeising@FreeBSD.org
 COMMENT=	Verilog simulation and synthesis tool
 
 LICENSE=	GPLv2
 
 GNU_CONFIGURE=	yes
 CONFIGURE_ARGS=	--disable-suffix
 
 USES=		bison gmake readline
 
 .include <bsd.port.mk>
Index: head/cad/iverilog/distinfo
===================================================================
--- head/cad/iverilog/distinfo	(revision 509185)
+++ head/cad/iverilog/distinfo	(revision 509186)
@@ -1,3 +1,3 @@
-TIMESTAMP = 1508676832
-SHA256 (verilog-10.2.tar.gz) = 96dedbddb12d375edb45a144a926a3ba1e3e138d6598b18e7d79f2ae6de9e500
-SIZE (verilog-10.2.tar.gz) = 1695227
+TIMESTAMP = 1566058481
+SHA256 (verilog-10.3.tar.gz) = 86bd45e7e12d1bc8772c3cdd394e68a9feccb2a6d14aaf7dae0773b7274368ef
+SIZE (verilog-10.3.tar.gz) = 1698889