Index: head/cad/verilator/Makefile
===================================================================
--- head/cad/verilator/Makefile	(revision 491343)
+++ head/cad/verilator/Makefile	(revision 491344)
@@ -1,31 +1,30 @@
 # $FreeBSD$
 
 PORTNAME=	verilator
 PORTVERSION=	4.008
+PORTREVISION=	1
 CATEGORIES=	cad
 MASTER_SITES=	https://www.veripool.org/ftp/
 
 MAINTAINER=	kevinz5000@gmail.com
 COMMENT=	Synthesizable Verilog to C++ compiler
 
 LICENSE=	GPLv3
 LICENSE_FILE=	${WRKSRC}/COPYING
-
-BUILD_DEPENDS=	flex:textproc/flex
 
 USES=		bison gmake pathfix perl5 tar:tgz
 
 GNU_CONFIGURE=	yes
 CONFIGURE_ENV=	INSTALL_PROGRAM="${INSTALL_SCRIPT}"
 
 post-patch:
 	${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \
 	    ${WRKSRC}/Makefile.in
 
 post-build:
 	@${STRIP_CMD} ${WRKSRC}/bin/verilator_bin
 
 post-install:
 	${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg
 
 .include <bsd.port.mk>