Index: head/cad/verilog-mode.el/pkg-descr
===================================================================
--- head/cad/verilog-mode.el/pkg-descr	(revision 482418)
+++ head/cad/verilog-mode.el/pkg-descr	(revision 482419)
@@ -1,9 +1,9 @@
 Verilog-mode.el is a Verilog mode for Emacs which provides context-sensitive
 highlighting, auto indenting, and provides macro expansion capabilities to
 greatly reduce Verilog coding time.
 
 Recent versions allow you to insert AUTOS in non-AUTO designs, so IP
 interconnect can be easily modified. You can also expand Verilog-2001 ".*"
 instantiations, to see what ports will be connected by simulators.
 
-WWW: http://www.veripool.org/wiki/verilog-mode
+WWW: https://www.veripool.org/wiki/verilog-mode