Index: head/emulators/riscv-isa-sim/Makefile =================================================================== --- head/emulators/riscv-isa-sim/Makefile (revision 481272) +++ head/emulators/riscv-isa-sim/Makefile (revision 481273) @@ -1,53 +1,53 @@ # $FreeBSD$ PORTNAME= riscv-isa-sim DISTVERSION= git -PORTREVISION= 20180104 +PORTREVISION= 20181005 CATEGORIES= emulators MAINTAINER= lwhsu@FreeBSD.org COMMENT= Spike, a RISC-V ISA Simulator LICENSE= BSD3CLAUSE -LIB_DEPENDS= libfesvr.so:emulators/riscv-fesvr - ONLY_FOR_ARCHS= amd64 -GH_ACCOUNT= freebsd-riscv -GH_TAGNAME= acf9589 +LIB_DEPENDS= libfesvr.so:emulators/riscv-fesvr USES= compiler:c++11-lang gmake shebangfix + +GH_ACCOUNT= freebsd-riscv +GH_TAGNAME= aae60e0 HAS_CONFIGURE= yes SHEBANG_FILES= scripts/vcs-version.sh USE_GITHUB= yes USE_LDCONFIG= yes LDFLAGS+= -L${LOCALBASE}/lib CFLAGS+= -I${LOCALBASE}/include \ -DRISCV_ENABLE_DIRTY=1 STRIP_FILES= bin/spike \ bin/spike-dasm \ bin/termios-xspike \ bin/xspike \ lib/libdummy_rocc.so \ lib/libriscv.so \ lib/libsoftfloat.so \ lib/libspike_main.so post-extract: @${MV} ${WRKSRC}/riscv/insn_template.h ${WRKSRC}/riscv/insn_template.hpp post-patch: ${REINPLACE_CMD} -e \ 's|[(]install_libs_dir[)]/pkgconfig|(INSTALLDIR)/libdata/pkgconfig|g' \ ${WRKSRC}/Makefile.in post-install: . for f in ${STRIP_FILES} ${STRIP_CMD} ${STAGEDIR}${PREFIX}/${f} . endfor .include Index: head/emulators/riscv-isa-sim/distinfo =================================================================== --- head/emulators/riscv-isa-sim/distinfo (revision 481272) +++ head/emulators/riscv-isa-sim/distinfo (revision 481273) @@ -1,3 +1,3 @@ -TIMESTAMP = 1515149913 -SHA256 (freebsd-riscv-riscv-isa-sim-git-acf9589_GH0.tar.gz) = 163689110e1742271b02984f378974418d23d69e7c1943b75ebca0761769693b -SIZE (freebsd-riscv-riscv-isa-sim-git-acf9589_GH0.tar.gz) = 227934 +TIMESTAMP = 1538736497 +SHA256 (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 423005144e71b272fad7f13b57af7de561a178af096a71d304e0a3c590520195 +SIZE (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 232817 Index: head/emulators/riscv-isa-sim/files/patch-Makefile.in =================================================================== --- head/emulators/riscv-isa-sim/files/patch-Makefile.in (revision 481272) +++ head/emulators/riscv-isa-sim/files/patch-Makefile.in (revision 481273) @@ -1,19 +1,19 @@ ---- Makefile.in.orig 2017-08-08 20:00:25.889361000 +0100 -+++ Makefile.in 2017-08-08 20:06:41.633896000 +0100 -@@ -187,13 +187,13 @@ +--- Makefile.in.orig 2018-10-05 10:52:51 UTC ++++ Makefile.in +@@ -187,13 +187,13 @@ _$(1).cc : # Build the object files for this subproject -$(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs)) +$(2)_pch := $$(patsubst %.hpp, %.h.gch, $$($(2)_precompiled_hdrs)) $(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs)) $(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs)) $(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs)) $(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs)) -$(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs)) -$$($(2)_pch) : %.h.gch : %.h +$(2)_deps += $$(patsubst %.hpp, %.h.d, $$($(2)_precompiled_hdrs)) +$$($(2)_pch) : %.h.gch : %.hpp $(COMPILE) -x c++-header $$< -o $$@ # If using clang, don't depend (and thus don't build) precompiled headers $$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch)) Index: head/emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc =================================================================== --- head/emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc (revision 481272) +++ head/emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc (revision 481273) @@ -1,10 +1,10 @@ ---- riscv/insn_template.cc.orig 2016-08-01 15:40:47 UTC +--- riscv/insn_template.cc.orig 2018-10-05 10:52:33 UTC +++ riscv/insn_template.cc @@ -1,6 +1,6 @@ // See LICENSE for license details. -#include "insn_template.h" +#include "insn_template.hpp" reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc) { Index: head/emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in =================================================================== --- head/emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in (revision 481272) +++ head/emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in (revision 481273) @@ -1,19 +1,20 @@ ---- riscv/riscv.mk.in.orig 2017-07-11 13:58:22.000000000 +0100 -+++ riscv/riscv.mk.in 2017-08-08 20:08:06.247906000 +0100 -@@ -21,14 +21,14 @@ +--- riscv/riscv.mk.in.orig 2018-10-05 10:52:11 UTC ++++ riscv/riscv.mk.in +@@ -23,7 +23,7 @@ riscv_hdrs = \ tracer.h \ extension.h \ rocc.h \ - insn_template.h \ + insn_template.hpp \ mulhi.h \ debug_module.h \ - remote_bitbang.h \ + debug_rom_defines.h \ +@@ -31,7 +31,7 @@ riscv_hdrs = \ jtag_dtm.h \ riscv_precompiled_hdrs = \ - insn_template.h \ + insn_template.hpp \ riscv_srcs = \ processor.cc \ Index: head/emulators/riscv-isa-sim/pkg-plist =================================================================== --- head/emulators/riscv-isa-sim/pkg-plist (revision 481272) +++ head/emulators/riscv-isa-sim/pkg-plist (revision 481273) @@ -1,40 +1,44 @@ bin/spike bin/spike-dasm bin/termios-xspike bin/xspike include/spike/cachesim.h include/spike/common.h include/spike/config.h include/spike/debug_module.h +include/spike/debug_rom_defines.h include/spike/decode.h include/spike/devices.h include/spike/disasm.h +include/spike/dts.h include/spike/encoding.h include/spike/extension.h include/spike/icache.h include/spike/insn_list.h include/spike/insn_template.hpp include/spike/internals.h include/spike/jtag_dtm.h include/spike/memtracer.h include/spike/mmu.h include/spike/mulhi.h +include/spike/platform.h include/spike/primitiveTypes.h include/spike/primitives.h include/spike/processor.h include/spike/remote_bitbang.h include/spike/rocc.h include/spike/sim.h +include/spike/simif.h include/spike/softfloat.h include/spike/softfloat_types.h include/spike/specialize.h include/spike/tracer.h include/spike/trap.h lib/libdummy_rocc.so lib/libriscv.so lib/libsoftfloat.so lib/libspike_main.so libdata/pkgconfig/riscv-dummy_rocc.pc libdata/pkgconfig/riscv-riscv.pc libdata/pkgconfig/riscv-softfloat.pc libdata/pkgconfig/riscv-spike_main.pc