Index: head/cad/Makefile =================================================================== --- head/cad/Makefile (revision 460846) +++ head/cad/Makefile (revision 460847) @@ -1,101 +1,102 @@ # $FreeBSD$ # COMMENT = CAD tools SUBDIR += NASTRAN-95 SUBDIR += admesh SUBDIR += adms SUBDIR += alliance SUBDIR += astk-client SUBDIR += astk-serveur SUBDIR += atlc SUBDIR += basicdsp SUBDIR += brickutils SUBDIR += brlcad SUBDIR += calculix SUBDIR += calculix-ccx SUBDIR += cascade SUBDIR += chipvault SUBDIR += cider SUBDIR += cura-engine SUBDIR += dinotrace SUBDIR += dxf2fig SUBDIR += electric SUBDIR += electric-ng SUBDIR += elmerfem SUBDIR += feappv SUBDIR += fidocadj SUBDIR += freecad SUBDIR += freehdl SUBDIR += fritzing SUBDIR += gdsreader SUBDIR += gdt SUBDIR += geda SUBDIR += gerbv SUBDIR += ghdl SUBDIR += gmsh SUBDIR += gmsh-occ SUBDIR += gnucap SUBDIR += gplcver SUBDIR += gspiceui SUBDIR += gtkwave SUBDIR += impact SUBDIR += irsim SUBDIR += iverilog SUBDIR += jspice3 SUBDIR += kicad SUBDIR += kicad-devel SUBDIR += kicad-library SUBDIR += kicad-library-devel SUBDIR += klayout SUBDIR += layouteditor SUBDIR += ldraw SUBDIR += leocad SUBDIR += libopencad SUBDIR += librecad SUBDIR += linux-eagle5 SUBDIR += linuxcnc-devel SUBDIR += logisim SUBDIR += magic SUBDIR += meshdev SUBDIR += meshlab SUBDIR += netgen SUBDIR += ngspice_rework SUBDIR += opencascade SUBDIR += openscad SUBDIR += openvsp SUBDIR += p5-GDS2 SUBDIR += p5-Verilog-Perl SUBDIR += pcb SUBDIR += pdnmesh SUBDIR += py-gdspy SUBDIR += py-lcapy SUBDIR += py-pycam + SUBDIR += py-pyfda SUBDIR += python-gdsii SUBDIR += pythoncad SUBDIR += qcad SUBDIR += qelectrotech SUBDIR += qfsm SUBDIR += qmls SUBDIR += qucs SUBDIR += repsnapper SUBDIR += rubygem-gdsii SUBDIR += sceptre SUBDIR += scotch SUBDIR += solvespace SUBDIR += sp2sp SUBDIR += spice SUBDIR += stepcode SUBDIR += sumo SUBDIR += sweethome3d SUBDIR += tkgate SUBDIR += tochnog SUBDIR += transcalc SUBDIR += varkon SUBDIR += verilog-mode.el SUBDIR += xcircuit SUBDIR += z88 SUBDIR += zcad .include Index: head/cad/py-pyfda/Makefile =================================================================== --- head/cad/py-pyfda/Makefile (nonexistent) +++ head/cad/py-pyfda/Makefile (revision 460847) @@ -0,0 +1,47 @@ +# $FreeBSD$ + +PORTNAME= pyfda +PORTVERSION= 0.1 +DISTVERSIONSUFFIX= rc6 +CATEGORIES= cad python devel +MASTER_SITES= CHEESESHOP +PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} + +MAINTAINER= yuri@FreeBSD.org +COMMENT= GUI tool for designing and analysing discrete time filters + +LICENSE= MIT +LICENSE_FILE= ${WRKSRC}/LICENSE + +RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}docutils>0:textproc/py-docutils@${FLAVOR} \ + ${PYTHON_PKGNAMEPREFIX}matplotlib>0:math/py-matplotlib@${FLAVOR} \ + ${PYNUMPY} \ + ${PYTHON_PKGNAMEPREFIX}scipy>0:science/py-scipy@${FLAVOR} + +USES= python:3.4+ pyqt:5 +USE_PYTHON= distutils autoplist noflavors +USE_PYQT= core_run gui_run widgets_run +NO_ARCH= yes + +post-extract: + @${MV} ${WRKSRC}/pyfda/pyfda_log.conf ${WRKSRC}/pyfda/pyfda_log.conf.sample + @${MV} ${WRKSRC}/pyfda/pyfda_log_debug.conf ${WRKSRC}/pyfda/pyfda_log_debug.conf.sample + +post-patch: + @${REINPLACE_CMD} -e " \ + s|package_data={'pyfda': \['pyfda_log.conf', 'pyfda_log_debug.conf',|package_data={'pyfda': [|; \ + s|data_files = \[|data_files = [('${PREFIX}/etc', ['pyfda/pyfda_log.conf.sample', 'pyfda/pyfda_log_debug.conf.sample'])|" \ + ${WRKSRC}/setup.py + @${REINPLACE_CMD} -e " \ + s|logging.config.fileConfig(os.path.join(base_dir, rc.log_config_file))|logging.config.fileConfig(os.path.join('${PREFIX}/etc', rc.log_config_file))|" \ + ${WRKSRC}/pyfda/pyfdax.py + @${REINPLACE_CMD} -e " \ + s|'pyfda.log'|'/tmp/pyfda.log'|" \ + ${WRKSRC}/pyfda/*.conf.sample + +post-stage: + @${REINPLACE_CMD} -E " \ + s|(.*\.sample)$$|@sample \1|" \ + ${WRKDIR}/.PLIST.pymodtmp + +.include Property changes on: head/cad/py-pyfda/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/py-pyfda/distinfo =================================================================== --- head/cad/py-pyfda/distinfo (nonexistent) +++ head/cad/py-pyfda/distinfo (revision 460847) @@ -0,0 +1,3 @@ +TIMESTAMP = 1505805392 +SHA256 (pyfda-0.1rc6.tar.gz) = 65c09211a860e4ae84715363a4efdf9049c6855e548da17fea5cbbb628925261 +SIZE (pyfda-0.1rc6.tar.gz) = 188694 Property changes on: head/cad/py-pyfda/distinfo ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/py-pyfda/pkg-descr =================================================================== --- head/cad/py-pyfda/pkg-descr (nonexistent) +++ head/cad/py-pyfda/pkg-descr (revision 460847) @@ -0,0 +1,9 @@ +pyFDA is a GUI based tool in Python/Qt for analysing and designing discrete +time filters. The capability for generating Verilog and VHDL code for the +designed and quantized filters will be added in the next release. + +Since the digital filter design is a research area with many unanswered +questions, this project is also a research project. +Please expect freezes in case of some parameter values. + +WWW: https://github.com/chipmuenk/pyFDA Property changes on: head/cad/py-pyfda/pkg-descr ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property