Index: head/cad/iverilog/files/patch-load_module.cc
===================================================================
--- head/cad/iverilog/files/patch-load_module.cc	(revision 452816)
+++ head/cad/iverilog/files/patch-load_module.cc	(nonexistent)
@@ -1,10 +0,0 @@
---- load_module.cc.orig	2015-08-23 21:41:41 UTC
-+++ load_module.cc
-@@ -21,6 +21,7 @@
- # include  "util.h"
- # include  "parse_api.h"
- # include  "compiler.h"
-+# include  <assert.h>
- # include  <iostream>
- # include  <map>
- # include  <cstdlib>

Property changes on: head/cad/iverilog/files/patch-load_module.cc
___________________________________________________________________
Deleted: fbsd:nokeywords
## -1 +0,0 ##
-yes
\ No newline at end of property
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-text/plain
\ No newline at end of property
Index: head/cad/iverilog/Makefile
===================================================================
--- head/cad/iverilog/Makefile	(revision 452816)
+++ head/cad/iverilog/Makefile	(revision 452817)
@@ -1,21 +1,20 @@
 # Created by: Ying-Chieh Liao <ijliao@FreeBSD.org>
 # $FreeBSD$
 
 PORTNAME=	iverilog
-PORTVERSION=	10.1.1
+PORTVERSION=	10.2
 CATEGORIES=	cad
-MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]\.[0-9]$,,}/
+MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v10/
 DISTNAME=	verilog-${PORTVERSION}
 
 MAINTAINER=	zeising@FreeBSD.org
 COMMENT=	Verilog simulation and synthesis tool
 
 LICENSE=	GPLv2
 
 GNU_CONFIGURE=	yes
 CONFIGURE_ARGS=	--disable-suffix
-USES=		bison gmake
 
-MAKE_JOBS_UNSAFE=	yes
+USES=		bison gmake readline
 
 .include <bsd.port.mk>
Index: head/cad/iverilog/distinfo
===================================================================
--- head/cad/iverilog/distinfo	(revision 452816)
+++ head/cad/iverilog/distinfo	(revision 452817)
@@ -1,3 +1,3 @@
-TIMESTAMP = 1464367614
-SHA256 (verilog-10.1.1.tar.gz) = fdaa75dfe7c58cbc471fc12710ee49b3f32fd6cc055d9181b5190cbcbbd6cada
-SIZE (verilog-10.1.1.tar.gz) = 1684925
+TIMESTAMP = 1508676832
+SHA256 (verilog-10.2.tar.gz) = 96dedbddb12d375edb45a144a926a3ba1e3e138d6598b18e7d79f2ae6de9e500
+SIZE (verilog-10.2.tar.gz) = 1695227