Index: head/cad/iverilog/Makefile
===================================================================
--- head/cad/iverilog/Makefile	(revision 415949)
+++ head/cad/iverilog/Makefile	(revision 415950)
@@ -1,29 +1,29 @@
 # Created by: Ying-Chieh Liao <ijliao@FreeBSD.org>
 # $FreeBSD$
 
 PORTNAME=	iverilog
-PORTVERSION=	10.1
+PORTVERSION=	10.1.1
 CATEGORIES=	cad
-MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/
+MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]\.[0-9]$,,}/
 DISTNAME=	verilog-${PORTVERSION}
 
 MAINTAINER=	zeising@FreeBSD.org
 COMMENT=	Verilog simulation and synthesis tool
 
 LICENSE=	GPLv2
 
 GNU_CONFIGURE=	yes
 USES=		bison gmake
 
 MAKE_JOBS_UNSAFE=	yes
 
 .include <bsd.port.options.mk>
 
 .if ${OSVERSION} < 1000033
 BUILD_DEPENDS+=	flex>=0:textproc/flex
 CONFIGURE_ENV+=	ac_cv_prog_LEX="${LOCALBASE}/bin/flex"
 .endif
 
 CONFIGURE_ARGS=	--disable-suffix
 
 .include <bsd.port.mk>
Index: head/cad/iverilog/distinfo
===================================================================
--- head/cad/iverilog/distinfo	(revision 415949)
+++ head/cad/iverilog/distinfo	(revision 415950)
@@ -1,2 +1,3 @@
-SHA256 (verilog-10.1.tar.gz) = e822f397e3b7a496c8138c2b05b4209eb47b74370bc173a91c293fa8e809e529
-SIZE (verilog-10.1.tar.gz) = 1685176
+TIMESTAMP = 1464367614
+SHA256 (verilog-10.1.1.tar.gz) = fdaa75dfe7c58cbc471fc12710ee49b3f32fd6cc055d9181b5190cbcbbd6cada
+SIZE (verilog-10.1.1.tar.gz) = 1684925