diff --git a/sys/powerpc/booke/machdep_e500.c b/sys/powerpc/booke/machdep_e500.c
index 0e4ac3943e2b..08c1b71c9cdb 100644
--- a/sys/powerpc/booke/machdep_e500.c
+++ b/sys/powerpc/booke/machdep_e500.c
@@ -1,143 +1,140 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
  *
  * Copyright (c) 2011-2012 Semihalf.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 #include <sys/cdefs.h>
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/reboot.h>
 
 #include <vm/vm.h>
 #include <vm/pmap.h>
 
 #include <machine/machdep.h>
 
 #include <dev/fdt/fdt_common.h>
 
 #include <powerpc/mpc85xx/mpc85xx.h>
 
 extern void dcache_enable(void);
 extern void dcache_inval(void);
 extern void icache_enable(void);
 extern void icache_inval(void);
 extern void l2cache_enable(void);
 extern void l2cache_inval(void);
 extern void bpred_enable(void);
 
 void
 booke_enable_l1_cache(void)
 {
 	uint32_t csr;
 
 	/* Enable D-cache if applicable */
 	csr = mfspr(SPR_L1CSR0);
 	if ((csr & L1CSR0_DCE) == 0) {
 		dcache_inval();
 		dcache_enable();
 	}
 
 	csr = mfspr(SPR_L1CSR0);
 	if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
 		printf("L1 D-cache %sabled\n",
 		    (csr & L1CSR0_DCE) ? "en" : "dis");
 
 	/* Enable L1 I-cache if applicable. */
 	csr = mfspr(SPR_L1CSR1);
 	if ((csr & L1CSR1_ICE) == 0) {
 		icache_inval();
 		icache_enable();
 	}
 
 	csr = mfspr(SPR_L1CSR1);
 	if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
 		printf("L1 I-cache %sabled\n",
 		    (csr & L1CSR1_ICE) ? "en" : "dis");
 }
 
 void
 booke_enable_l2_cache(void)
 {
 	uint32_t csr;
 
 	/* Enable L2 cache on E500mc */
 	if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
 	    (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
 		csr = mfspr(SPR_L2CSR0);
 		/*
 		 * Don't actually attempt to manipulate the L2 cache if
 		 * L2CFG0 is zero.
 		 *
 		 * Any chip with a working L2 cache will have a nonzero
 		 * L2CFG0, as it will have a nonzero L2CSIZE field.
 		 *
 		 * This fixes waiting forever for cache enable in qemu,
 		 * which does not implement the L2 cache.
 		 */
 		if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) {
 			l2cache_inval();
 			l2cache_enable();
 		}
 
 		csr = mfspr(SPR_L2CSR0);
 		if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
 			printf("L2 cache %sabled\n",
 			    (csr & L2CSR0_L2E) ? "en" : "dis");
 	}
 }
 
 void
 booke_enable_bpred(void)
 {
 	uint32_t csr;
 
 	bpred_enable();
 	csr = mfspr(SPR_BUCSR);
 	if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0)
 		printf("Branch Predictor %sabled\n",
 		    (csr & BUCSR_BPEN) ? "en" : "dis");
 }
 
 void
 booke_disable_l2_cache(void)
 {
 }
 
 /* Return 0 on handled success, otherwise signal number. */
 int
 cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode)
 {
-	register_t mcsr;
-
-	mcsr = mfspr(SPR_MCSR);
 
 	*ucode = BUS_OBJERR;
 	return (SIGBUS);
 }